basesystem-jjsandbox/ToshikazuOhiwa/master-jj

recipes

1 files changed, 38 insertions, 0 deletions

diff --git a/bsp/meta-freescale-3rdparty/recipes-kernel/linux/linux-fslc-lts-4.19/ccimx6ul/0003-ARM-dts-imx6ul-use-nvmem-cells-for-cpu-speed-grading.patch b/bsp/meta-freescale-3rdparty/recipes-kernel/linux/linux-fslc-lts-4.19/ccimx6ul/0003-ARM-dts-imx6ul-use-nvmem-cells-for-cpu-speed-grading.patch
new file mode 100644
index 00000000..e8c6d16a
--- /dev/null
+++ b/bsp/meta-freescale-3rdparty/recipes-kernel/linux/linux-fslc-lts-4.19/ccimx6ul/0003-ARM-dts-imx6ul-use-nvmem-cells-for-cpu-speed-grading.patch
@@ -0,0 +1,38 @@
+From: Anson Huang <Anson.Huang@nxp.com>
+Date: Fri, 14 Sep 2018 10:59:21 +0800
+Subject: [PATCH] ARM: dts: imx6ul: use nvmem-cells for cpu speed grading
+
+On i.MX6UL, accessing OCOTP directly is wrong because the ocotp clock
+needs to be enabled first, so use the nvmem-cells binding instead.
+
+Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+(cherry picked from commit 92f0eb08c66a73594cf200e65689e767f7f0da5e)
+---
+ arch/arm/boot/dts/imx6ul.dtsi | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
+index 6dc0b569acdf..c670d8e4e0a9 100644
+--- a/arch/arm/boot/dts/imx6ul.dtsi
++++ b/arch/arm/boot/dts/imx6ul.dtsi
+@@ -89,6 +89,8 @@
+ 				      "pll1_sys";
+ 			arm-supply = <&reg_arm>;
+ 			soc-supply = <&reg_soc>;
++			nvmem-cells = <&cpu_speed_grade>;
++			nvmem-cell-names = "speed_grade";
+ 		};
+ 	};
+ 
+@@ -932,6 +934,10 @@
+ 				tempmon_temp_grade: temp-grade@20 {
+ 					reg = <0x20 4>;
+ 				};
++
++				cpu_speed_grade: speed-grade@10 {
++					reg = <0x10 4>;
++				};
+ 			};
+ 
+ 			lcdif: lcdif@21c8000 {