agl-basesystem

3 files changed, 535 insertions, 0 deletions

diff --git a/bsp/meta-sancloud/recipes-kernel/linux/linux-bbe-4.19/0001-Update-DTS-for-Automotive-Cape-ICU.patch b/bsp/meta-sancloud/recipes-kernel/linux/linux-bbe-4.19/0001-Update-DTS-for-Automotive-Cape-ICU.patch
new file mode 100644
index 00000000..b1bb2214
--- /dev/null
+++ b/bsp/meta-sancloud/recipes-kernel/linux/linux-bbe-4.19/0001-Update-DTS-for-Automotive-Cape-ICU.patch
@@ -0,0 +1,305 @@
+From 86446c29c1818abdff438440b70b34a9390eb4b3 Mon Sep 17 00:00:00 2001
+From: Paul Barker <paul.barker@sancloud.co.uk>
+Date: Mon, 20 May 2019 15:57:15 +0000
+Subject: [PATCH] Update DTS for Automotive Cape (ICU)
+
+Signed-off-by: Paul Barker <paul.barker@sancloud.co.uk>
+---
+ arch/arm/boot/dts/am335x-sancloud-bbe.dts     | 154 ++++++++++++++++++
+ .../dt-bindings/board/am335x-bbw-bbb-base.h   | 108 ++++++++++++
+ 2 files changed, 262 insertions(+)
+ create mode 100644 include/dt-bindings/board/am335x-bbw-bbb-base.h
+
+diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe.dts b/arch/arm/boot/dts/am335x-sancloud-bbe.dts
+index f2ec84683109..cb35368c975b 100644
+--- a/arch/arm/boot/dts/am335x-sancloud-bbe.dts
++++ b/arch/arm/boot/dts/am335x-sancloud-bbe.dts
+@@ -10,6 +10,7 @@
+ #include "am33xx.dtsi"
+ #include "am335x-bone-common.dtsi"
+ #include "am335x-boneblack-common.dtsi"
++#include <dt-bindings/board/am335x-bbw-bbb-base.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ 
+ / {
+@@ -97,6 +98,46 @@
+ 			AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE7)     /* gpmc_a10.gpio1_26 */
+ 		>;
+ 	};
++
++	icu_led_pins: pinmux_icu_led_pins {
++		pinctrl-single,pins = <
++			BONE_P9_27 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)				/* LED_1 */
++			BONE_P9_25 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)				/* LED_2 */
++			BONE_P9_23 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)				/* LED_3 */
++			BONE_P9_42 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)				/* LED_4 */
++			BONE_P9_15 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)				/* LED_5 */
++			BONE_P9_24 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)				/* LED_6 */
++		>;
++	};
++
++	icu_i2c1_pins: pinmux_icu_i2c1_pins {
++		pinctrl-single,pins = <
++			BONE_P9_18 (PIN_INPUT_PULLUP | SLEWCTRL_SLOW | MUX_MODE2)		/* I2C1_SDA */
++			BONE_P9_17 (PIN_INPUT_PULLUP | SLEWCTRL_SLOW | MUX_MODE2)		/* I2C1_SCL */
++		>;
++	};
++
++	icu_can0_pins: pinmux_icu_can0_pins {
++		pinctrl-single,pins = <
++			BONE_P9_19 (PIN_INPUT_PULLUP | MUX_MODE2)				/* CAN0_RXD */
++			BONE_P9_20 (PIN_OUTPUT_PULLUP | MUX_MODE2)				/* CAN0_TXD */
++		>;
++	};
++
++	icu_vda_pins: pinmux_icu_vda_pins {
++		pinctrl-single,pins = <
++			BONE_P8_18 (PIN_INPUT | MUX_MODE7)					/* RADIO */
++			BONE_P8_15 (PIN_INPUT | MUX_MODE7)					/* BEAM */
++			BONE_P8_17 (PIN_INPUT | WAKEUP_EN | MUX_MODE7)				/* IGNITION */
++		>;
++	};
++
++	icu_wireless_pins: pinmux_icu_wireless_pins {
++		pinctrl-single,pins = <
++			BONE_P8_27 (PIN_OUTPUT_PULLUP | MUX_MODE7)				/* WIRELESS_OFF_N */
++			BONE_P9_26 (PIN_OUTPUT_PULLUP | MUX_MODE7)				/* WIRELESS_RST_N */
++		>;
++	};
+ };
+ 
+ &mac {
+@@ -142,3 +183,116 @@
+ 		/* wifi on port 4 */
+ 	};
+ };
++
++&i2c1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&icu_i2c1_pins>;
++	status = "okay";
++	clock-frequency = <400000>;
++
++	rtc1@68 {
++		compatible = "dallas,ds1337";
++		reg = <0x68>;
++		status = "okay";
++	};
++};
++
++&i2c2 {
++	/* Disable I2C2 as it shares pins with CAN0 */
++	pinctrl-0 = "";
++	status = "disabled";
++};
++
++&dcan0 {
++	#address-cells = <1>;
++	#size-cells = <0>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&icu_can0_pins>;
++	status = "okay";
++};
++
++/ {
++	icu_leds {
++		compatible = "gpio-leds";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&icu_led_pins>;
++		status = "okay";
++
++		icu_led@2 {
++			label = "beaglebone:red:led1";
++			gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "mmc0";
++			default-state = "off";
++		};
++
++		icu_led@3 {
++			label = "beaglebone:green:led2";
++			gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "heartbeat";
++			default-state = "off";
++		};
++
++		icu_led@1 {
++			label = "beaglebone:red:led3";
++			gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "none";
++			default-state = "off";
++		};
++
++		icu_led@6 {
++			label = "beaglebone:green:led4";
++			gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "none";
++			default-state = "off";
++		};
++
++		icu_led@5 {
++			label = "beaglebone:red:led5";
++			gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "none";
++			default-state = "off";
++		};
++
++		icu_led@4 {
++			label = "beaglebone:green:led6";
++			gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "none";
++			default-state = "off";
++		};
++	};
++
++	icu_vda {
++		compatible = "gpio-keys";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&icu_vda_pins>;
++		status = "okay";
++
++		radio_pin {
++			label = "radio";
++			linux,code = <0x3b>;	/* KEY_F1 */
++			gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
++			gpio-key;
++			debounce-interval = <10>;
++		};
++
++		ignition_pin {
++			label = "ignition";
++			linux,code = <0x8f>;	/* KEY_WAKEUP */
++			gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
++			wakeup-source;
++			debounce-interval = <10>;
++		};
++
++		beam_pin {
++			label = "beam";
++			linux,code = <0x3c>;	/* KEY_F2 */
++			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
++			gpio-key;
++			debounce-interval = <10>;
++		};
++	};
++};
+diff --git a/include/dt-bindings/board/am335x-bbw-bbb-base.h b/include/dt-bindings/board/am335x-bbw-bbb-base.h
+new file mode 100644
+index 000000000000..ad745f042c70
+--- /dev/null
++++ b/include/dt-bindings/board/am335x-bbw-bbb-base.h
+@@ -0,0 +1,108 @@
++/*
++ * This header provides constants for bbw/bbb pinctrl bindings.
++ *
++ * Copyright (C) 2014 Robert Nelson <robertcnelson@gmail.com>
++ *
++ * Numbers Based on: https://github.com/derekmolloy/boneDeviceTree/tree/master/docs
++ */
++
++#ifndef _DT_BINDINGS_BOARD_AM335X_BBW_BBB_BASE_H
++#define _DT_BINDINGS_BOARD_AM335X_BBW_BBB_BASE_H
++
++#define BONE_P8_03 0x018
++#define BONE_P8_04 0x01C
++
++#define BONE_P8_05 0x008
++#define BONE_P8_06 0x00C
++#define BONE_P8_07 0x090
++#define BONE_P8_08 0x094
++
++#define BONE_P8_09 0x09C
++#define BONE_P8_10 0x098
++#define BONE_P8_11 0x034
++#define BONE_P8_12 0x030
++
++#define BONE_P8_13 0x024
++#define BONE_P8_14 0x028
++#define BONE_P8_15 0x03C
++#define BONE_P8_16 0x038
++
++#define BONE_P8_17 0x02C
++#define BONE_P8_18 0x08C
++#define BONE_P8_19 0x020
++#define BONE_P8_20 0x084
++
++#define BONE_P8_21 0x080
++#define BONE_P8_22 0x014
++#define BONE_P8_23 0x010
++#define BONE_P8_24 0x004
++
++#define BONE_P8_25 0x000
++#define BONE_P8_26 0x07C
++#define BONE_P8_27 0x0E0
++#define BONE_P8_28 0x0E8
++
++#define BONE_P8_29 0x0E4
++#define BONE_P8_30 0x0EC
++#define BONE_P8_31 0x0D8
++#define BONE_P8_32 0x0DC
++
++#define BONE_P8_33 0x0D4
++#define BONE_P8_34 0x0CC
++#define BONE_P8_35 0x0D0
++#define BONE_P8_36 0x0C8
++
++#define BONE_P8_37 0x0C0
++#define BONE_P8_38 0x0C4
++#define BONE_P8_39 0x0B8
++#define BONE_P8_40 0x0BC
++
++#define BONE_P8_41 0x0B0
++#define BONE_P8_42 0x0B4
++#define BONE_P8_43 0x0A8
++#define BONE_P8_44 0x0AC
++
++#define BONE_P8_45 0x0A0
++#define BONE_P8_46 0x0A4
++
++#define BONE_P9_11 0x070
++#define BONE_P9_12 0x078
++
++#define BONE_P9_13 0x074
++#define BONE_P9_14 0x048
++#define BONE_P9_15 0x040
++#define BONE_P9_16 0x04C
++
++#define BONE_P9_17 0x15C
++#define BONE_P9_18 0x158
++#define BONE_P9_19 0x17C
++#define BONE_P9_20 0x178
++
++#define BONE_P9_21 0x154
++#define BONE_P9_22 0x150
++#define BONE_P9_23 0x044
++#define BONE_P9_24 0x184
++
++#define BONE_P9_25 0x1AC
++#define BONE_P9_26 0x180
++#define BONE_P9_27 0x1A4
++#define BONE_P9_28 0x19C
++
++#define BONE_P9_29 0x194
++#define BONE_P9_30 0x198
++#define BONE_P9_31 0x190
++
++/* Shared P21 of P11 */
++#define BONE_P9_41 0x1B4
++#define BONE_P9_41A 0x1B4
++#define BONE_P9_41B 0x1A8
++#define BONE_P9_91 0x1A8
++
++/* Shared P22 of P11 */
++#define BONE_P9_42 0x164
++#define BONE_P9_42A 0x164
++#define BONE_P9_42B 0x1A0
++#define BONE_P9_92 0x1A0
++
++#endif
++
+-- 
+2.17.1
+
diff --git a/bsp/meta-sancloud/recipes-kernel/linux/linux-bbe-4.19/am335x-pru-uio.dtsi b/bsp/meta-sancloud/recipes-kernel/linux/linux-bbe-4.19/am335x-pru-uio.dtsi
new file mode 100644
index 00000000..714b1d78
--- /dev/null
+++ b/bsp/meta-sancloud/recipes-kernel/linux/linux-bbe-4.19/am335x-pru-uio.dtsi
@@ -0,0 +1,192 @@
+&pruss_soc_bus {
+		uio_pruss_mdio: uio_pruss_mdio@32400 {
+			compatible = "ti,davinci_mdio";
+			reg = <0x32400 0x90>;
+			clocks = <&dpll_core_m4_ck>;
+			clock-names = "fck";
+			bus_freq = <1000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		uio_pruss_mem: uio_pruss_mem {
+			compatible = "ti,uio-module-drv";
+			mem = <0x4a300000 0x2000>,
+			      <0x4a302000 0x2000>,
+			      <0x4a310000 0x3000>,
+			      <0x4a320000 0x2000>,
+			      <0x4a326000 0x2000>,
+			      <0x4a32e000 0x31c>,
+			      <0x4a332000 0x58>;
+			mem-names = "dram0", "dram1", "shrdram2", "intc", "cfg",
+				    "iep", "mii_rt";
+
+			status = "okay";
+		};
+		uio_pruss_mem2: uio_pruss_mem2 {
+			compatible = "ti,uio-module-drv";
+			mem = <0x4a328000 0xd4>,
+			      <0x4a330000 0x174>,
+			      <0x4a332400 0x90>,
+			      <0x40302000 0x0e000>;
+			mem-names = "uart", "ecap", "mdio", "ocmc";
+			status = "okay";
+		};
+
+		uio_pruss_evt0: uio_pruss_evt0 {
+			compatible = "ti,uio-module-drv";
+                        interrupts = <20>;
+			interrupt-mode = <1>;
+			status = "okay";
+		};
+		uio_pruss_evt1: uio_pruss_evt1 {
+			compatible = "ti,uio-module-drv";
+                        interrupts = <21>;
+			interrupt-mode = <1>;
+			status = "okay";
+		};
+		uio_pruss_evt2: uio_pruss_evt2 {
+			compatible = "ti,uio-module-drv";
+                        interrupts = <22>;
+			interrupt-mode = <1>;
+			status = "okay";
+		};
+		uio_pruss_evt3: uio_pruss_evt3 {
+			compatible = "ti,uio-module-drv";
+                        interrupts = <23>;
+			interrupt-mode = <1>;
+			status = "okay";
+		};
+		uio_pruss_evt4: uio_pruss_evt4 {
+			compatible = "ti,uio-module-drv";
+                        interrupts = <24>;
+			interrupt-mode = <1>;
+			status = "okay";
+		};
+		uio_pruss_evt5: uio_pruss_evt5 {
+			compatible = "ti,uio-module-drv";
+                        interrupts = <25>;
+			interrupt-mode = <1>;
+			status = "okay";
+		};
+		uio_pruss_evt6: uio_pruss_evt6 {
+			compatible = "ti,uio-module-drv";
+                        interrupts = <26>;
+			interrupt-mode = <1>;
+			status = "okay";
+		};
+		uio_pruss_evt7: uio_pruss_evt7 {
+			compatible = "ti,uio-module-drv";
+                        interrupts = <27>;
+			interrupt-mode = <1>;
+			status = "okay";
+		};
+
+		uio_pruss_0_mem: uio_pruss_0_mem {
+			compatible = "ti,uio-module-drv";
+			mem = <0x4a334000 0x2000>,
+			      <0x4a322000 0x400>,
+			      <0x4a322400 0x100>;
+			mem-names = "iram", "control", "debug";
+			status = "okay";
+		};
+
+		uio_pruss_1_mem: uio_pruss_1_mem {
+			compatible = "ti,uio-module-drv";
+			mem = <0x4a338000 0x2000>,
+			      <0x4a324000 0x400>,
+			      <0x4a324400 0x100>;
+			mem-names = "iram", "control", "debug";
+			status = "okay";
+		};
+};
+
+&am33xx_pinmux {
+	uio_pruss_mdio_eth_default: uio_pruss_mdio_eht_default {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x88c, (PIN_OUTPUT | MUX_MODE5))           /* gpmc_clk.pr1_mdio_mdclk */
+			AM33XX_IOPAD(0x888, (PIN_INPUT  | MUX_MODE5))           /* gpmc_csn3.pr1_mdio_data */
+			AM33XX_IOPAD(0x89c, (PIN_INPUT_PULLUP | MUX_MODE7))     /* gpmc_ben0_cle.gpio2_5 */
+			/* disable CPSW MDIO */
+			AM33XX_IOPAD(0x948, (PIN_INPUT_PULLUP | MUX_MODE7))     /* mdio_data.gpio0_0 */
+			AM33XX_IOPAD(0x94c, (PIN_INPUT_PULLUP | MUX_MODE7))     /* mdio_clk.gpio0_1 */
+			AM33XX_IOPAD(0x8a0, (PIN_INPUT  | MUX_MODE2))   /* dss_data0.pr1_mii_mt0_clk */
+			AM33XX_IOPAD(0x8b4, (PIN_OUTPUT | MUX_MODE2))   /* dss_data5.pr1_mii0_txd0 */
+			AM33XX_IOPAD(0x8b0, (PIN_OUTPUT | MUX_MODE2))   /* dss_data4.pr1_mii0_txd1 */
+			AM33XX_IOPAD(0x8ac, (PIN_OUTPUT | MUX_MODE2))   /* dss_data3.pr1_mii0_txd2 */
+			AM33XX_IOPAD(0x8a8, (PIN_OUTPUT | MUX_MODE2))   /* dss_data2.pr1_mii0_txd3 */
+			AM33XX_IOPAD(0x8cc, (PIN_INPUT  | MUX_MODE5))   /* dss_data11.pr1_mii0_rxd0 */
+			AM33XX_IOPAD(0x8c8, (PIN_INPUT  | MUX_MODE5))   /* dss_data10.pr1_mii0_rxd1 */
+			AM33XX_IOPAD(0x8c4, (PIN_INPUT  | MUX_MODE5))   /* dss_data9.pr1_mii0_rxd2 */
+			AM33XX_IOPAD(0x8c0, (PIN_INPUT  | MUX_MODE5))   /* dss_data8.pr1_mii0_rxd3 */
+			AM33XX_IOPAD(0x8a4, (PIN_OUTPUT | MUX_MODE2))   /* dss_data1.pr1_mii0_txen */
+			AM33XX_IOPAD(0x8d8, (PIN_INPUT  | MUX_MODE5))   /* dss_data14.pr1_mii_mr0_clk */
+			AM33XX_IOPAD(0x8dc, (PIN_INPUT  | MUX_MODE5))   /* dss_data15.pr1_mii0_rxdv */
+			AM33XX_IOPAD(0x8d4, (PIN_INPUT  | MUX_MODE5))   /* dss_data13.pr1_mii0_rxer */
+			AM33XX_IOPAD(0x8d0, (PIN_INPUT  | MUX_MODE5))   /* dss_data12.pr1_mii0_rxlink */
+			AM33XX_IOPAD(0x8e8, (PIN_INPUT  | MUX_MODE2))   /* dss_pclk.pr1_mii0_crs */
+
+			AM33XX_IOPAD(0x840, (PIN_INPUT  | MUX_MODE5))   /* gpmc_a0.pr1_mii_mt1_clk */
+			AM33XX_IOPAD(0x850, (PIN_OUTPUT | MUX_MODE5))   /* gpmc_a4.pr1_mii1_txd0 */
+			AM33XX_IOPAD(0x84c, (PIN_OUTPUT | MUX_MODE5))   /* gpmc_a3.pr1_mii1_txd1 */
+			AM33XX_IOPAD(0x848, (PIN_OUTPUT | MUX_MODE5))   /* gpmc_a2.pr1_mii1_txd2 */
+			AM33XX_IOPAD(0x844, (PIN_OUTPUT | MUX_MODE5))   /* gpmc_a1.pr1_mii1_txd3 */
+			AM33XX_IOPAD(0x860, (PIN_INPUT  | MUX_MODE5))   /* gpmc_a8.pr1_mii1_rxd0 */
+			AM33XX_IOPAD(0x85c, (PIN_INPUT  | MUX_MODE5))   /* gpmc_a7.pr1_mii1_rxd1 */
+			AM33XX_IOPAD(0x858, (PIN_INPUT  | MUX_MODE5))   /* gpmc_a6.pr1_mii1_rxd2 */
+			AM33XX_IOPAD(0x854, (PIN_INPUT  | MUX_MODE5))   /* gpmc_a5.pr1_mii1_rxd3 */
+			AM33XX_IOPAD(0x874, (PIN_OUTPUT | MUX_MODE5))   /* gpmc_wpn.pr1_mii1_txen */
+			AM33XX_IOPAD(0x864, (PIN_INPUT  | MUX_MODE5))   /* gpmc_a9.pr1_mii_mr1_clk */
+			AM33XX_IOPAD(0x868, (PIN_INPUT  | MUX_MODE5))   /* gpmc_a10.pr1_mii1_rxdv */
+			AM33XX_IOPAD(0x86c, (PIN_INPUT  | MUX_MODE5))   /* gpmc_a11.pr1_mii1_rxer */
+			AM33XX_IOPAD(0x878, (PIN_INPUT  | MUX_MODE5))   /* gpmc_ben1.pr1_mii1_rxlink */
+			AM33XX_IOPAD(0x8ec, (PIN_INPUT  | MUX_MODE2))   /* lcd_ac_bias_en.pr1_mii1_crs */
+			AM33XX_IOPAD(0x870, (PIN_INPUT  | MUX_MODE5))   /* gpmc_wait0.pr1_mii1_col */
+		>;
+	};
+};
+
+&uio_pruss_mdio {
+	pinctrl-0 = <&uio_pruss_mdio_eth_default>;
+	pinctrl-names = "default";
+	reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+	reset-delay-us = <2>; /* PHY datasheet states 1uS min */
+	status = "okay";
+
+	uio_pruss_eth0_phy: ethernet-phy@1 {
+		reg = <1>;
+	};
+
+	uio_pruss_eth1_phy: ethernet-phy@3 {
+		reg = <3>;
+	};
+};
+
+&pruss {
+	status = "disabled";
+};
+
+&pru0 {
+	status = "disabled";
+};
+
+&pru1 {
+	status = "disabled";
+};
+
+&pruss_intc {
+	status = "disabled";
+};
+
+&pruss_mdio {
+	status = "disabled";
+};
+
+&pruss_emac0 {
+        status = "disabled";
+};
+
+&pruss_emac1 {
+        status = "disabled";
+};
diff --git a/bsp/meta-sancloud/recipes-kernel/linux/linux-bbe-4.19/cmem.dtsi b/bsp/meta-sancloud/recipes-kernel/linux/linux-bbe-4.19/cmem.dtsi
new file mode 100644
index 00000000..23119861
--- /dev/null
+++ b/bsp/meta-sancloud/recipes-kernel/linux/linux-bbe-4.19/cmem.dtsi
@@ -0,0 +1,38 @@
+/*
+ * This is a placeholder for CMEM reserved memory declarations. This
+ * is simply an example and does not actually reserve any memory for
+ * CMEM.
+ *
+ * The commented sections below provide an example for how to provide
+ * a reserved memory region for CMEM to use as a buffer pool.
+ */
+/ {
+/*
+	reserved-memory {
+		cmem_block_mem_0: cmem_block_mem@a0000000 {
+			reg = <0x0 0xa0000000 0x0 0x0a000000>;
+			no-map;
+			status = "okay";
+		};
+	};
+*/
+
+	cmem {
+		compatible = "ti,cmem";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		#pool-size-cells = <2>;
+
+		status = "disabled";
+/*
+		status = "okay";
+
+                cmem_block_0: cmem_block@0 {
+                        reg = <0>;
+                        memory-region = <&cmem_block_mem_0>;
+                        cmem-buf-pools = <1 0x0 0x0a000000>;
+                };
+*/
+        };
+};