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author | ToshikazuOhiwa <toshikazu_ohiwa@mail.toyota.co.jp> | 2020-03-30 09:24:26 +0900 |
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committer | ToshikazuOhiwa <toshikazu_ohiwa@mail.toyota.co.jp> | 2020-03-30 09:24:26 +0900 |
commit | 5b80bfd7bffd4c20d80b7c70a7130529e9a755dd (patch) | |
tree | b4bb18dcd1487dbf1ea8127e5671b7bb2eded033 /external/poky/meta/recipes-devtools/python-numpy/files/0001-npy_cpu-Add-riscv-support.patch | |
parent | 706ad73eb02caf8532deaf5d38995bd258725cb8 (diff) |
agl-basesystem
Diffstat (limited to 'external/poky/meta/recipes-devtools/python-numpy/files/0001-npy_cpu-Add-riscv-support.patch')
-rw-r--r-- | external/poky/meta/recipes-devtools/python-numpy/files/0001-npy_cpu-Add-riscv-support.patch | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/external/poky/meta/recipes-devtools/python-numpy/files/0001-npy_cpu-Add-riscv-support.patch b/external/poky/meta/recipes-devtools/python-numpy/files/0001-npy_cpu-Add-riscv-support.patch new file mode 100644 index 00000000..4f5c4f5f --- /dev/null +++ b/external/poky/meta/recipes-devtools/python-numpy/files/0001-npy_cpu-Add-riscv-support.patch @@ -0,0 +1,28 @@ +From 30fb1bf9244bb0789c02ec7c98a923acc7200206 Mon Sep 17 00:00:00 2001 +From: Khem Raj <raj.khem@gmail.com> +Date: Fri, 16 Mar 2018 19:55:21 -0700 +Subject: [PATCH] npy_cpu: Add riscv support + +Signed-off-by: Khem Raj <raj.khem@gmail.com> +--- +Upstream-Status: Submitted [https://github.com/numpy/numpy/pull/10761] + + numpy/core/include/numpy/npy_cpu.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/numpy/core/include/numpy/npy_cpu.h b/numpy/core/include/numpy/npy_cpu.h +index 84653ea18..9e88db873 100644 +--- a/numpy/core/include/numpy/npy_cpu.h ++++ b/numpy/core/include/numpy/npy_cpu.h +@@ -78,6 +78,8 @@ + #define NPY_CPU_AARCH64 + #elif defined(__mc68000__) + #define NPY_CPU_M68K ++#elif defined(__riscv) ++ #define NPY_CPU_RISCV + #elif defined(__arc__) && defined(__LITTLE_ENDIAN__) + #define NPY_CPU_ARCEL + #elif defined(__arc__) && defined(__BIG_ENDIAN__) +-- +2.16.2 + |