diff options
author | ToshikazuOhiwa <toshikazu_ohiwa@mail.toyota.co.jp> | 2020-03-30 09:24:26 +0900 |
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committer | ToshikazuOhiwa <toshikazu_ohiwa@mail.toyota.co.jp> | 2020-03-30 09:24:26 +0900 |
commit | 5b80bfd7bffd4c20d80b7c70a7130529e9a755dd (patch) | |
tree | b4bb18dcd1487dbf1ea8127e5671b7bb2eded033 /external/poky/meta/recipes-support/liburcu/files/Add-support-for-the-RISC-V-architecture.patch | |
parent | 706ad73eb02caf8532deaf5d38995bd258725cb8 (diff) |
agl-basesystem
Diffstat (limited to 'external/poky/meta/recipes-support/liburcu/files/Add-support-for-the-RISC-V-architecture.patch')
-rw-r--r-- | external/poky/meta/recipes-support/liburcu/files/Add-support-for-the-RISC-V-architecture.patch | 157 |
1 files changed, 157 insertions, 0 deletions
diff --git a/external/poky/meta/recipes-support/liburcu/files/Add-support-for-the-RISC-V-architecture.patch b/external/poky/meta/recipes-support/liburcu/files/Add-support-for-the-RISC-V-architecture.patch new file mode 100644 index 00000000..b026782b --- /dev/null +++ b/external/poky/meta/recipes-support/liburcu/files/Add-support-for-the-RISC-V-architecture.patch @@ -0,0 +1,157 @@ +From fdfad81006c2c964781b616f0a75578507be809c Mon Sep 17 00:00:00 2001 +From: Michael Jeanson <mjeanson@efficios.com> +Date: Wed, 21 Mar 2018 17:38:41 -0400 +Subject: [PATCH] Add support for the RISC-V architecture + +Tested in QEMU 2.12.0-rc0, requires --disable-compiler-tls to go +through the benchmarks reliably. + +Signed-off-by: Michael Jeanson <mjeanson@efficios.com> +Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> +Upstream-Status: Backport +--- + configure.ac | 1 + + include/Makefile.am | 2 ++ + include/urcu/arch/riscv.h | 49 ++++++++++++++++++++++++++++++++++++++++++++ + include/urcu/uatomic/riscv.h | 44 +++++++++++++++++++++++++++++++++++++++ + 4 files changed, 96 insertions(+) + create mode 100644 include/urcu/arch/riscv.h + create mode 100644 include/urcu/uatomic/riscv.h + +diff --git a/configure.ac b/configure.ac +index d0b4a9ac..9145081a 100644 +--- a/configure.ac ++++ b/configure.ac +@@ -151,6 +151,7 @@ AS_CASE([$host_cpu], + [tile*], [ARCHTYPE="tile"], + [hppa*], [ARCHTYPE="hppa"], + [m68k], [ARCHTYPE="m68k"], ++ [riscv*], [ARCHTYPE="riscv"], + [ARCHTYPE="unknown"] + ) + +diff --git a/include/Makefile.am b/include/Makefile.am +index dcdf304b..36667b43 100644 +--- a/include/Makefile.am ++++ b/include/Makefile.am +@@ -27,6 +27,7 @@ EXTRA_DIST = urcu/arch/aarch64.h \ + urcu/arch/mips.h \ + urcu/arch/nios2.h \ + urcu/arch/ppc.h \ ++ urcu/arch/riscv.h \ + urcu/arch/s390.h \ + urcu/arch/sparc64.h \ + urcu/arch/tile.h \ +@@ -43,6 +44,7 @@ EXTRA_DIST = urcu/arch/aarch64.h \ + urcu/uatomic/mips.h \ + urcu/uatomic/nios2.h \ + urcu/uatomic/ppc.h \ ++ urcu/uatomic/riscv.h \ + urcu/uatomic/s390.h \ + urcu/uatomic/sparc64.h \ + urcu/uatomic/tile.h \ +diff --git a/include/urcu/arch/riscv.h b/include/urcu/arch/riscv.h +new file mode 100644 +index 00000000..1fd7d62b +--- /dev/null ++++ b/include/urcu/arch/riscv.h +@@ -0,0 +1,49 @@ ++#ifndef _URCU_ARCH_RISCV_H ++#define _URCU_ARCH_RISCV_H ++ ++/* ++ * arch/riscv.h: definitions for the RISC-V architecture ++ * ++ * Copyright (c) 2018 Michael Jeanson <mjeanson@efficios.com> ++ * ++ * This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU Lesser General Public ++ * License as published by the Free Software Foundation; either ++ * version 2.1 of the License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * Lesser General Public License for more details. ++ * ++ * You should have received a copy of the GNU Lesser General Public ++ * License along with this library; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA ++ */ ++ ++#include <urcu/compiler.h> ++#include <urcu/config.h> ++#include <urcu/syscall-compat.h> ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include <stdlib.h> ++#include <sys/time.h> ++ ++/* ++ * On Linux, define the membarrier system call number if not yet available in ++ * the system headers. ++ */ ++#if (defined(__linux__) && !defined(__NR_membarrier)) ++#define __NR_membarrier 283 ++#endif ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#include <urcu/arch/generic.h> ++ ++#endif /* _URCU_ARCH_RISCV_H */ +diff --git a/include/urcu/uatomic/riscv.h b/include/urcu/uatomic/riscv.h +new file mode 100644 +index 00000000..a6700e17 +--- /dev/null ++++ b/include/urcu/uatomic/riscv.h +@@ -0,0 +1,44 @@ ++/* ++ * Atomic exchange operations for the RISC-V architecture. Let GCC do it. ++ * ++ * Copyright (c) 2018 Michael Jeanson <mjeanson@efficios.com> ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a copy ++ * of this software and associated documentation files (the "Software"), to ++ * deal in the Software without restriction, including without limitation the ++ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the Software is ++ * furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS ++ * IN THE SOFTWARE. ++ */ ++ ++#ifndef _URCU_ARCH_UATOMIC_RISCV_H ++#define _URCU_ARCH_UATOMIC_RISCV_H ++ ++#include <urcu/compiler.h> ++#include <urcu/system.h> ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#define UATOMIC_HAS_ATOMIC_BYTE ++#define UATOMIC_HAS_ATOMIC_SHORT ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#include <urcu/uatomic/generic.h> ++ ++#endif /* _URCU_ARCH_UATOMIC_RISCV_H */ |