diff options
Diffstat (limited to 'bsp/meta-arm/meta-arm-bsp/recipes-bsp')
20 files changed, 1031 insertions, 0 deletions
diff --git a/bsp/meta-arm/meta-arm-bsp/recipes-bsp/boot-wrapper-aaarch64/boot-wrapper-aarch64.inc b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/boot-wrapper-aaarch64/boot-wrapper-aarch64.inc new file mode 100644 index 00000000..3cd39177 --- /dev/null +++ b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/boot-wrapper-aaarch64/boot-wrapper-aarch64.inc @@ -0,0 +1,87 @@ + +SUMMARY = "Linux aarch64 boot wrapper with FDT support" +LICENSE = "BSD" + +inherit autotools deploy + +PROVIDES = "virtual/gem5-bootloader boot-wrapper-aarch64" + +PACKAGE_ARCH = "${MACHINE_ARCH}" + +COMPATIBLE_MACHINE ?= "" + +# Device tree to put in the image +# by default use the standard kernel devicetree +# This should be overwritten if the devicetree is not generated +# by the kernel. +# This should point to a file in the deploy image directory +BOOT_WRAPPER_AARCH64_DEVICETREE ??= "${KERNEL_DEVICETREE}" + +# Kernel image to put in the image +# This should point to a file in the deploy image directory +BOOT_WRAPPER_AARCH64_KERNEL ??= "Image" + +# Kernel command line for the image +BOOT_WRAPPER_AARCH64_CMDLINE ??= "rw" + +# Image generated by boot wrapper +BOOT_WRAPPER_AARCH64_IMAGE ??= "linux-system.axf" + +DEPENDS += "virtual/kernel dtc-native" + +EXTRA_OECONF += "--with-kernel-dir=${WORKDIR}/kernel" +EXTRA_OECONF += "--with-dtb=${WORKDIR}/kernel/dummy.dtb" +EXTRA_OECONF += "--with-cmdline=\"\"" +EXTRA_OECONF += "--enable-psci --enable-gicv3" + +# unset LDFLAGS solves this error when compiling kernel modules: +# aarch64-poky-linux-ld: unrecognized option '-Wl,-O1' +EXTRA_OEMAKE += "'LDFLAGS= --gc-sections '" + +# Strip prefix if any +REAL_DTB = "${@os.path.basename(d.getVar('BOOT_WRAPPER_AARCH64_DEVICETREE'))}" + +EXTRA_OEMAKE += "'KERNEL_DTB=${DEPLOY_DIR_IMAGE}/${REAL_DTB}'" +EXTRA_OEMAKE += "'KERNEL_IMAGE=${DEPLOY_DIR_IMAGE}/${BOOT_WRAPPER_AARCH64_KERNEL}'" +EXTRA_OEMAKE += "'CMDLINE=${BOOT_WRAPPER_AARCH64_CMDLINE}'" + + +do_configure_prepend() { + # Create dummy files to make configure happy. + # We will pass the generated ones directly to make. + mkdir -p ${WORKDIR}/kernel/arch/arm64/boot + echo "dummy" > ${WORKDIR}/kernel/arch/arm64/boot/Image + echo "dummy" > ${WORKDIR}/kernel/dummy.dtb + + # Generate configure + (cd ${S} && autoreconf -i || exit 1) +} + +do_compile[noexec] = "1" +do_install[noexec] = "1" + +# We need the kernel to create an image +do_deploy[depends] += "virtual/kernel:do_deploy" + +do_deploy() { + if [ ! -f ${DEPLOY_DIR_IMAGE}/${REAL_DTB} ]; then + echo "ERROR: cannot find ${REAL_DTB} in ${DEPLOY_DIR_IMAGE}" >&2 + echo "Please check your BOOT_WRAPPER_AARCH64_DEVICETREE settings" >&2 + exit 1 + fi + + if [ ! -f ${DEPLOY_DIR_IMAGE}/${BOOT_WRAPPER_AARCH64_KERNEL} ]; then + echo "ERROR: cannot find ${BOOT_WRAPPER_AARCH64_KERNEL}" \ + " in ${DEPLOY_DIR_IMAGE}" >&2 + echo "Please check your BOOT_WRAPPER_AARCH64_KERNEL settings" >&2 + exit 1 + fi + + oe_runmake clean + oe_runmake all + + install -D -p -m 644 ${BOOT_WRAPPER_AARCH64_IMAGE} \ + ${DEPLOYDIR}/linux-system.axf +} +addtask deploy before do_build after do_compile + diff --git a/bsp/meta-arm/meta-arm-bsp/recipes-bsp/boot-wrapper-aaarch64/boot-wrapper-aarch64_git.bb b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/boot-wrapper-aaarch64/boot-wrapper-aarch64_git.bb new file mode 100644 index 00000000..a071f609 --- /dev/null +++ b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/boot-wrapper-aaarch64/boot-wrapper-aarch64_git.bb @@ -0,0 +1,27 @@ + +LIC_FILES_CHKSUM = "file://LICENSE.txt;md5=bb63326febfb5fb909226c8e7ebcef5c" + +SRC_URI = "git://git.kernel.org/pub/scm/linux/kernel/git/mark/boot-wrapper-aarch64.git" + +PV = "git${SRCPV}" + +S = "${WORKDIR}/git" + +SRCREV = "fd74c8cbd0e17483d2299208cad9742bee605ca7" + +BPN = "boot-wrapper-aarch64" + +require boot-wrapper-aarch64.inc + +# Gem5 aarch64 support +COMPATIBLE_MACHINE_gem5_arm64 = "gem5-arm64" + +# For gem5 we use the dtb generated by gem5 directly +DEPENDS_append_gem5-arm64 = " gem5-aarch64-dtb" +BOOT_WRAPPER_AARCH64_DEVICETREE_gem5-arm64 = "gem5-aarch64.dtb" + +# The dtb must be generated for us to generate the axf +DEPLOY_DEPEND_LIST ?= "" +DEPLOY_DEPEND_LIST_gem5-arm64 = " gem5-aarch64-dtb:do_deploy" +do_deploy[depends] += "${DEPLOY_DEPEND_LIST}" + diff --git a/bsp/meta-arm/meta-arm-bsp/recipes-bsp/firmware/scp-firmware-juno_19.06.bb b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/firmware/scp-firmware-juno_19.06.bb new file mode 100644 index 00000000..a6ac9caa --- /dev/null +++ b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/firmware/scp-firmware-juno_19.06.bb @@ -0,0 +1,38 @@ +DESCRIPTION = "System Control Processor (SCP) firmware for Juno" +HOMEPAGE = "https://github.com/ARM-software/SCP-firmware" +LICENSE = "BSD-3-Clause" +SECTION = "firmware" +LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/BSD-3-Clause;md5=550794465ba0ec5312d6919e203a55f9" + +PACKAGE_ARCH = "${MACHINE_ARCH}" + +COMPATIBLE_MACHINE = "juno" + +PROVIDES += "virtual/scp-firmware" + +# For now, for juno we retrieve the SCP firmware in binary format +# from Linaro Releases. +SRC_URI = "http://releases.linaro.org/members/arm/platforms/${PV}/juno-latest-oe-uboot.zip;subdir=${UNPACK_DIR}" + +SRC_URI[md5sum] = "01b662b81fa409d55ff298238ad24003" +SRC_URI[sha256sum] = "b8a3909bb3bc4350a8771b863193a3e33b358e2a727624a77c9ecf13516cec82" + +UNPACK_DIR = "juno-firmware" + +S = "${WORKDIR}/${UNPACK_DIR}" + +SCP_FIRMWARE_BINARIES = "scp_bl1.bin scp_bl2.bin" + +inherit nopackages + +do_configure[noexec] = "1" +do_configure[compile] = "1" + +do_install() { + install -d ${D}/firmware + for file in ${SCP_FIRMWARE_BINARIES}; do + install -m 644 ${S}/SOFTWARE/${file} ${D}/firmware + done +} + +SYSROOT_DIRS += "/firmware" diff --git a/bsp/meta-arm/meta-arm-bsp/recipes-bsp/images/firmware-image-juno.bb b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/images/firmware-image-juno.bb new file mode 100644 index 00000000..b0ad14f1 --- /dev/null +++ b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/images/firmware-image-juno.bb @@ -0,0 +1,75 @@ +DESCRIPTION = "Firmware Image for Juno to be copied to the Configuration \ +microSD card" + +LICENSE = "BSD-3-Clause" +SECTION = "firmware" +LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/BSD-3-Clause;md5=550794465ba0ec5312d6919e203a55f9" + +DEPENDS = "virtual/trusted-firmware-a virtual/kernel" + +PACKAGE_ARCH = "${MACHINE_ARCH}" + +COMPATIBLE_MACHINE = "juno" + +LINARO_RELEASE = "19.06" + +SRC_URI = "http://releases.linaro.org/members/arm/platforms/${LINARO_RELEASE}/juno-latest-oe-uboot.zip;subdir=${UNPACK_DIR} \ + file://images-r0.txt \ + file://images-r1.txt \ + file://images-r2.txt \ + file://uEnv.txt \ +" +SRC_URI[md5sum] = "01b662b81fa409d55ff298238ad24003" +SRC_URI[sha256sum] = "b8a3909bb3bc4350a8771b863193a3e33b358e2a727624a77c9ecf13516cec82" + +UNPACK_DIR = "juno-firmware-${LINARO_RELEASE}" + +inherit deploy nopackages + +do_configure[noexec] = "1" +do_compile[noexec] = "1" + +# The ${D} is used as a temporary directory and we don't generate any +# packages for this recipe. +do_install() { + cp -a ${WORKDIR}/${UNPACK_DIR} ${D} + cp -f ${RECIPE_SYSROOT}/firmware/bl1-juno.bin \ + ${D}/${UNPACK_DIR}/SOFTWARE/bl1.bin + + cp -f ${RECIPE_SYSROOT}/firmware/fip-juno.bin \ + ${D}/${UNPACK_DIR}/SOFTWARE/fip.bin + + # u-boot environment file + cp -f ${WORKDIR}/uEnv.txt ${D}/${UNPACK_DIR}/SOFTWARE/ + + # Juno images list file + cp -f ${WORKDIR}/images-r0.txt ${D}/${UNPACK_DIR}/SITE1/HBI0262B/images.txt + cp -f ${WORKDIR}/images-r1.txt ${D}/${UNPACK_DIR}/SITE1/HBI0262C/images.txt + cp -f ${WORKDIR}/images-r2.txt ${D}/${UNPACK_DIR}/SITE1/HBI0262D/images.txt +} + +do_deploy() { + # To avoid dependency loop between firmware-image-juno:do_install + # and virtual/kernel:do_deploy when INITRAMFS_IMAGE_BUNDLE = "1", + # we need to handle the kernel binaries copying in the do_deploy + # task. + for f in ${KERNEL_DEVICETREE}; do + install -m 755 -c ${DEPLOY_DIR_IMAGE}/$(basename $f) \ + ${D}/${UNPACK_DIR}/SOFTWARE/. + done + + if [ "${INITRAMFS_IMAGE_BUNDLE}" -eq 1 ]; then + cp -L -f ${DEPLOY_DIR_IMAGE}/Image-initramfs-juno.bin \ + ${D}/${UNPACK_DIR}/SOFTWARE/Image + else + cp -L -f ${DEPLOY_DIR_IMAGE}/Image ${D}/${UNPACK_DIR}/SOFTWARE/ + fi + + # Compress the files + tar -C ${D}/${UNPACK_DIR} -zcvf ${WORKDIR}/${PN}.tar.gz ./ + + # Deploy the compressed archive to the deploy folder + install -D -p -m0644 ${WORKDIR}/${PN}.tar.gz ${DEPLOYDIR}/${PN}.tar.gz +} +do_deploy[depends] += "virtual/kernel:do_deploy" +addtask deploy after do_install diff --git a/bsp/meta-arm/meta-arm-bsp/recipes-bsp/images/firmware-image-juno/images-r0.txt b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/images/firmware-image-juno/images-r0.txt new file mode 100644 index 00000000..286dac74 --- /dev/null +++ b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/images/firmware-image-juno/images-r0.txt @@ -0,0 +1,71 @@ +TITLE: Versatile Express Images Configuration File + +[IMAGES] +TOTALIMAGES: 10 ;Number of Images (Max: 32) + +NOR0UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR0ADDRESS: 0x00000000 ;Image Flash Address +NOR0FILE: \SOFTWARE\fip.bin ;Image File Name +NOR0LOAD: 00000000 ;Image Load Address +NOR0ENTRY: 00000000 ;Image Entry Point + +NOR1UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR1ADDRESS: 0x03EC0000 ;Image Flash Address +NOR1FILE: \SOFTWARE\bl1.bin ;Image File Name +NOR1LOAD: 00000000 ;Image Load Address +NOR1ENTRY: 00000000 ;Image Entry Point + +NOR2UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR2ADDRESS: 0x00500000 ;Image Flash Address +NOR2FILE: \SOFTWARE\Image ;Image File Name +NOR2NAME: norkern ;Rename kernel to norkern +NOR2LOAD: 00000000 ;Image Load Address +NOR2ENTRY: 00000000 ;Image Entry Point + +NOR3UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR3ADDRESS: 0x02700000 ;Image Flash Address +NOR3FILE: \SOFTWARE\juno.dtb ;Image File Name +NOR3NAME: board.dtb ;Specify target filename to preserve file extension +NOR3LOAD: 00000000 ;Image Load Address +NOR3ENTRY: 00000000 ;Image Entry Point + +NOR4UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR4ADDRESS: 0x025C0000 ;Image Flash Address +NOR4FILE: \SOFTWARE\hdlcdclk.dat ;Image File Name +NOR4LOAD: 00000000 ;Image Load Address +NOR4ENTRY: 00000000 ;Image Entry Point + +NOR5UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR5ADDRESS: 0x03E40000 ;Image Flash Address +NOR5FILE: \SOFTWARE\scp_bl1.bin ;Image File Name +NOR5LOAD: 00000000 ;Image Load Address +NOR5ENTRY: 00000000 ;Image Entry Point + +NOR6UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR6ADDRESS: 0x0BF00000 ;Image Flash Address +NOR6FILE: \SOFTWARE\startup.nsh ;Image File Name +NOR6NAME: startup.nsh +NOR6LOAD: 00000000 ;Image Load Address +NOR6ENTRY: 00000000 ;Image Entry Point + +NOR7UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR7ADDRESS: 0x0BFC0000 ;Image Flash Address +NOR7FILE: \SOFTWARE\blank.img ;Image File Name +NOR7NAME: BOOTENV +NOR7LOAD: 00000000 ;Image Load Address +NOR7ENTRY: 00000000 ;Image Entry Point + +NOR8UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR8ADDRESS: 0x02600000 ;Image Flash Address +NOR8FILE: \SOFTWARE\selftest ;Image File Name +NOR8LOAD: 00000000 ;Image Load Address +NOR8ENTRY: 00000000 ;Image Entry Point + +NOR9UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR9ADDRESS: 0x02780000 ;Image Flash Address +NOR9NAME: uEnv.txt +NOR9FILE: \SOFTWARE\uEnv.txt ;Image File Name +NOR9LOAD: 00000000 ;Image Load Address +NOR9ENTRY: 00000000 ;Image Entry Point + + diff --git a/bsp/meta-arm/meta-arm-bsp/recipes-bsp/images/firmware-image-juno/images-r1.txt b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/images/firmware-image-juno/images-r1.txt new file mode 100644 index 00000000..f84caaf9 --- /dev/null +++ b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/images/firmware-image-juno/images-r1.txt @@ -0,0 +1,71 @@ +TITLE: Versatile Express Images Configuration File + +[IMAGES] +TOTALIMAGES: 10 ;Number of Images (Max: 32) + +NOR0UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR0ADDRESS: 0x00000000 ;Image Flash Address +NOR0FILE: \SOFTWARE\fip.bin ;Image File Name +NOR0LOAD: 00000000 ;Image Load Address +NOR0ENTRY: 00000000 ;Image Entry Point + +NOR1UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR1ADDRESS: 0x03EC0000 ;Image Flash Address +NOR1FILE: \SOFTWARE\bl1.bin ;Image File Name +NOR1LOAD: 00000000 ;Image Load Address +NOR1ENTRY: 00000000 ;Image Entry Point + +NOR2UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR2ADDRESS: 0x00500000 ;Image Flash Address +NOR2FILE: \SOFTWARE\Image ;Image File Name +NOR2NAME: norkern ;Rename kernel to norkern +NOR2LOAD: 00000000 ;Image Load Address +NOR2ENTRY: 00000000 ;Image Entry Point + +NOR3UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR3ADDRESS: 0x02700000 ;Image Flash Address +NOR3FILE: \SOFTWARE\juno-r1.dtb ;Image File Name +NOR3NAME: board.dtb ;Specify target filename to preserve file extension +NOR3LOAD: 00000000 ;Image Load Address +NOR3ENTRY: 00000000 ;Image Entry Point + +NOR4UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR4ADDRESS: 0x025C0000 ;Image Flash Address +NOR4FILE: \SOFTWARE\hdlcdclk.dat ;Image File Name +NOR4LOAD: 00000000 ;Image Load Address +NOR4ENTRY: 00000000 ;Image Entry Point + +NOR5UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR5ADDRESS: 0x03E40000 ;Image Flash Address +NOR5FILE: \SOFTWARE\scp_bl1.bin ;Image File Name +NOR5LOAD: 00000000 ;Image Load Address +NOR5ENTRY: 00000000 ;Image Entry Point + +NOR6UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR6ADDRESS: 0x0BF00000 ;Image Flash Address +NOR6FILE: \SOFTWARE\startup.nsh ;Image File Name +NOR6NAME: startup.nsh +NOR6LOAD: 00000000 ;Image Load Address +NOR6ENTRY: 00000000 ;Image Entry Point + +NOR7UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR7ADDRESS: 0x0BFC0000 ;Image Flash Address +NOR7FILE: \SOFTWARE\blank.img ;Image File Name +NOR7NAME: BOOTENV +NOR7LOAD: 00000000 ;Image Load Address +NOR7ENTRY: 00000000 ;Image Entry Point + +NOR8UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR8ADDRESS: 0x02600000 ;Image Flash Address +NOR8FILE: \SOFTWARE\selftest ;Image File Name +NOR8LOAD: 00000000 ;Image Load Address +NOR8ENTRY: 00000000 ;Image Entry Point + +NOR9UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR9ADDRESS: 0x02780000 ;Image Flash Address +NOR9NAME: uEnv.txt +NOR9FILE: \SOFTWARE\uEnv.txt ;Image File Name +NOR9LOAD: 00000000 ;Image Load Address +NOR9ENTRY: 00000000 ;Image Entry Point + + diff --git a/bsp/meta-arm/meta-arm-bsp/recipes-bsp/images/firmware-image-juno/images-r2.txt b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/images/firmware-image-juno/images-r2.txt new file mode 100644 index 00000000..149e0c4c --- /dev/null +++ b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/images/firmware-image-juno/images-r2.txt @@ -0,0 +1,71 @@ +TITLE: Versatile Express Images Configuration File + +[IMAGES] +TOTALIMAGES: 10 ;Number of Images (Max: 32) + +NOR0UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR0ADDRESS: 0x00000000 ;Image Flash Address +NOR0FILE: \SOFTWARE\fip.bin ;Image File Name +NOR0LOAD: 00000000 ;Image Load Address +NOR0ENTRY: 00000000 ;Image Entry Point + +NOR1UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR1ADDRESS: 0x03EC0000 ;Image Flash Address +NOR1FILE: \SOFTWARE\bl1.bin ;Image File Name +NOR1LOAD: 00000000 ;Image Load Address +NOR1ENTRY: 00000000 ;Image Entry Point + +NOR2UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR2ADDRESS: 0x00500000 ;Image Flash Address +NOR2FILE: \SOFTWARE\Image ;Image File Name +NOR2NAME: norkern ;Rename kernel to norkern +NOR2LOAD: 00000000 ;Image Load Address +NOR2ENTRY: 00000000 ;Image Entry Point + +NOR3UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR3ADDRESS: 0x02700000 ;Image Flash Address +NOR3FILE: \SOFTWARE\juno-r2.dtb ;Image File Name +NOR3NAME: board.dtb ;Specify target filename to preserve file extension +NOR3LOAD: 00000000 ;Image Load Address +NOR3ENTRY: 00000000 ;Image Entry Point + +NOR4UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR4ADDRESS: 0x025C0000 ;Image Flash Address +NOR4FILE: \SOFTWARE\hdlcdclk.dat ;Image File Name +NOR4LOAD: 00000000 ;Image Load Address +NOR4ENTRY: 00000000 ;Image Entry Point + +NOR5UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR5ADDRESS: 0x03E40000 ;Image Flash Address +NOR5FILE: \SOFTWARE\scp_bl1.bin ;Image File Name +NOR5LOAD: 00000000 ;Image Load Address +NOR5ENTRY: 00000000 ;Image Entry Point + +NOR6UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR6ADDRESS: 0x0BF00000 ;Image Flash Address +NOR6FILE: \SOFTWARE\startup.nsh ;Image File Name +NOR6NAME: startup.nsh +NOR6LOAD: 00000000 ;Image Load Address +NOR6ENTRY: 00000000 ;Image Entry Point + +NOR7UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR7ADDRESS: 0x0BFC0000 ;Image Flash Address +NOR7FILE: \SOFTWARE\blank.img ;Image File Name +NOR7NAME: BOOTENV +NOR7LOAD: 00000000 ;Image Load Address +NOR7ENTRY: 00000000 ;Image Entry Point + +NOR8UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR8ADDRESS: 0x02600000 ;Image Flash Address +NOR8FILE: \SOFTWARE\selftest ;Image File Name +NOR8LOAD: 00000000 ;Image Load Address +NOR8ENTRY: 00000000 ;Image Entry Point + +NOR9UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE +NOR9ADDRESS: 0x02780000 ;Image Flash Address +NOR9NAME: uEnv.txt +NOR9FILE: \SOFTWARE\uEnv.txt ;Image File Name +NOR9LOAD: 00000000 ;Image Load Address +NOR9ENTRY: 00000000 ;Image Entry Point + + diff --git a/bsp/meta-arm/meta-arm-bsp/recipes-bsp/images/firmware-image-juno/uEnv.txt b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/images/firmware-image-juno/uEnv.txt new file mode 100644 index 00000000..93eb5fb0 --- /dev/null +++ b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/images/firmware-image-juno/uEnv.txt @@ -0,0 +1,11 @@ +uenvcmd=run mybootcmd +mybootcmd=echo Loading custom boot command; \ +echo Loading kernel; \ +afs load ${kernel_name} ${kernel_addr} ; \ +if test $? -eq 1; then echo Loading ${kernel_alt_name} instead of ${kernel_name}; afs load ${kernel_alt_name} ${kernel_addr}; fi; \ +echo Loading device tree; \ +afs load ${fdtfile} ${fdt_addr}; \ +if test $? -eq 1; then echo Loading ${fdt_alt_name} instead of ${fdtfile}; \ +afs load ${fdt_alt_name} ${fdt_addr}; fi; fdt addr ${fdt_addr}; fdt resize; \ +booti ${kernel_addr} - ${fdt_addr}; + diff --git a/bsp/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/a5ds/0001-plat-arm-a5ds-move-dtb-to-a-new-address.patch b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/a5ds/0001-plat-arm-a5ds-move-dtb-to-a-new-address.patch new file mode 100644 index 00000000..8d848ec9 --- /dev/null +++ b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/a5ds/0001-plat-arm-a5ds-move-dtb-to-a-new-address.patch @@ -0,0 +1,31 @@ +From d3cadbc6f1060020960dc05af0465db919bbbe2b Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva <rui.silva@linaro.org> +Date: Fri, 30 Aug 2019 13:38:44 +0100 +Subject: [PATCH] plat/arm: a5ds: move dtb to a new address + +When Using bigger kernel images (>8.4MB compressed zImage) and at +decompress and final location init stage of kernel start makes it +override dtb at this address, to avoid this move the dtb a little +higher in address related. + +Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> +--- + plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts b/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts +index 9ab2d9656600..c616ff772237 100644 +--- a/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts ++++ b/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts +@@ -10,7 +10,7 @@ + /* Platform Config */ + plat_arm_bl2 { + compatible = "arm,tb_fw"; +- hw_config_addr = <0x0 0x82000000>; ++ hw_config_addr = <0x0 0x83000000>; + hw_config_max_size = <0x01000000>; + /* Disable authentication for development */ + disable_auth = <0x0>; +-- +2.22.1 + diff --git a/bsp/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-a5ds.inc b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-a5ds.inc new file mode 100644 index 00000000..aa21b743 --- /dev/null +++ b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-a5ds.inc @@ -0,0 +1,22 @@ +# Cortex-A5 Designstart specific TFA support + +COMPATIBLE_MACHINE = "a5ds" +TFA_PLATFORM = "a5ds" +TFA_DEBUG = "1" +TFA_UBOOT = "1" +TFA_BUILD_TARGET = "all fip" +TFA_INSTALL_TARGET = "bl1.bin fip.bin" + +SRCREV = "5d3ee0764b03567bf3501edf47d67d72daff0cb3" +LIC_FILES_CHKSUM = "file://license.rst;md5=1dd070c98a281d18d9eefd938729b031" + +EXTRA_OEMAKE_append = " \ + ARCH=aarch32 \ + FVP_HW_CONFIG_DTS=fdts/a5ds.dts \ + ARM_ARCH_MAJOR=7 \ + AARCH32_SP=sp_min \ + ARM_CORTEX_A5=yes \ + ARM_XLAT_TABLES_LIB_V1=1 \ + " + + diff --git a/bsp/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-fvp.inc b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-fvp.inc new file mode 100644 index 00000000..27031ebc --- /dev/null +++ b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-fvp.inc @@ -0,0 +1,13 @@ +# FVP specific TFA parameters + +# +# Armv8-A Base Platform FVP and Armv8-A Foundation Platform uses the same +# TFAs. +# + +COMPATIBLE_MACHINE = "fvp-base|foundation-armv8" +TFA_PLATFORM = "fvp" +TFA_DEBUG = "1" +TFA_MBEDTLS = "1" +TFA_UBOOT = "1" +TFA_BUILD_TARGET = "bl1 bl2 bl31 dtbs fip" diff --git a/bsp/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-juno.inc b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-juno.inc new file mode 100644 index 00000000..2f1559cb --- /dev/null +++ b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-juno.inc @@ -0,0 +1,13 @@ +# Juno specific TFA support + +COMPATIBLE_MACHINE = "juno" +TFA_PLATFORM = "juno" +TFA_DEBUG = "1" +TFA_MBEDTLS = "1" +TFA_UBOOT = "1" +TFA_BUILD_TARGET = "bl1 fip" + +# Juno needs the System Control Processor Firmware +DEPENDS += "virtual/scp-firmware" + +EXTRA_OEMAKE_append = " SCP_BL2=${RECIPE_SYSROOT}/firmware/scp_bl2.bin" diff --git a/bsp/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.%.bbappend b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.%.bbappend new file mode 100644 index 00000000..47915387 --- /dev/null +++ b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.%.bbappend @@ -0,0 +1,9 @@ +# Machine specific TFAs + +MACHINE_TFA_REQUIRE ?= "" + +MACHINE_TFA_REQUIRE_foundation-armv8 = "trusted-firmware-a-fvp.inc" +MACHINE_TFA_REQUIRE_fvp-base = "trusted-firmware-a-fvp.inc" +MACHINE_TFA_REQUIRE_juno = "trusted-firmware-a-juno.inc" + +require ${MACHINE_TFA_REQUIRE} diff --git a/bsp/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_git.bbappend b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_git.bbappend new file mode 100644 index 00000000..772f65a1 --- /dev/null +++ b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_git.bbappend @@ -0,0 +1,7 @@ +# Machine specific TFAs + +MACHINE_TFA_REQUIRE ?= "" + +MACHINE_TFA_REQUIRE_a5ds = "trusted-firmware-a-a5ds.inc" + +require ${MACHINE_TFA_REQUIRE} diff --git a/bsp/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/files/a5ds/0001-armv7-add-mmio-timer.patch b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/files/a5ds/0001-armv7-add-mmio-timer.patch new file mode 100644 index 00000000..fbf8a14f --- /dev/null +++ b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/files/a5ds/0001-armv7-add-mmio-timer.patch @@ -0,0 +1,105 @@ +From 8525c72c438b0aa66f1f38db37bd7aacf7e3ce34 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva <rui.silva@linaro.org> +Date: Wed, 18 Dec 2019 21:52:34 +0000 +Subject: [PATCH 1/2] armv7: add mmio timer + +This timer can be used by u-boot when arch-timer is not available in +core, for example, Cortex-A5. + +Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> +--- + arch/arm/cpu/armv7/Makefile | 1 + + arch/arm/cpu/armv7/mmio_timer.c | 56 +++++++++++++++++++++++++++++++++ + scripts/config_whitelist.txt | 1 + + 3 files changed, 58 insertions(+) + create mode 100644 arch/arm/cpu/armv7/mmio_timer.c + +diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile +index 8c955d0d5284..82af9c031277 100644 +--- a/arch/arm/cpu/armv7/Makefile ++++ b/arch/arm/cpu/armv7/Makefile +@@ -28,6 +28,7 @@ obj-$(CONFIG_ARMV7_PSCI) += psci.o psci-common.o + obj-$(CONFIG_IPROC) += iproc-common/ + obj-$(CONFIG_KONA) += kona-common/ + obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o ++obj-$(CONFIG_SYS_MMIO_TIMER) += mmio_timer.o + + ifneq (,$(filter s5pc1xx exynos,$(SOC))) + obj-y += s5p-common/ +diff --git a/arch/arm/cpu/armv7/mmio_timer.c b/arch/arm/cpu/armv7/mmio_timer.c +new file mode 100644 +index 000000000000..1b905db8bb19 +--- /dev/null ++++ b/arch/arm/cpu/armv7/mmio_timer.c +@@ -0,0 +1,56 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (c) 2019, Arm Limited. All rights reserved. ++ * ++ */ ++ ++#include <common.h> ++#include <asm/io.h> ++#include <div64.h> ++#include <bootstage.h> ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#define CNTCTLBASE 0x1a020000UL ++#define CNTREADBASE 0x1a030000UL ++ ++static inline uint32_t mmio_read32(uintptr_t addr) ++{ ++ return *(volatile uint32_t*)addr; ++} ++ ++int timer_init(void) ++{ ++ gd->arch.timer_rate_hz = mmio_read32(CNTCTLBASE); ++ ++ return 0; ++} ++ ++unsigned long long get_ticks(void) ++{ ++ return ((mmio_read32(CNTCTLBASE + 0x4) << 32) | ++ mmio_read32(CNTREADBASE)); ++} ++ ++ulong get_timer(ulong base) ++{ ++ return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base; ++} ++ ++void __udelay(unsigned long usec) ++{ ++ unsigned long endtime; ++ ++ endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz, ++ 1000UL); ++ ++ endtime += get_ticks(); ++ ++ while (get_ticks() < endtime) ++ ; ++} ++ ++ulong get_tbclk(void) ++{ ++ return gd->arch.timer_rate_hz; ++} +diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt +index cf1808e051c8..8624714ae7a6 100644 +--- a/scripts/config_whitelist.txt ++++ b/scripts/config_whitelist.txt +@@ -3138,6 +3138,7 @@ CONFIG_SYS_MMC_U_BOOT_DST + CONFIG_SYS_MMC_U_BOOT_OFFS + CONFIG_SYS_MMC_U_BOOT_SIZE + CONFIG_SYS_MMC_U_BOOT_START ++CONFIG_SYS_MMIO_TIMER + CONFIG_SYS_MONITOR_ + CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_BASE_EARLY +-- +2.25.0 + diff --git a/bsp/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/files/a5ds/0002-board-arm-add-designstart-cortex-a5-board.patch b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/files/a5ds/0002-board-arm-add-designstart-cortex-a5-board.patch new file mode 100644 index 00000000..3c527ae2 --- /dev/null +++ b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/files/a5ds/0002-board-arm-add-designstart-cortex-a5-board.patch @@ -0,0 +1,309 @@ +From 2417d0991f73ee2c83946fcac208a7d6894f4530 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva <rui.silva@linaro.org> +Date: Wed, 8 Jan 2020 09:48:11 +0000 +Subject: [PATCH 2/2] board: arm: add designstart cortex-a5 board + +Arm added a new board, designstart, with a cortex-a5 chip, add the +default configuration, initialization and makefile for this system. + +Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> +--- + arch/arm/Kconfig | 7 ++ + board/armltd/designstart/Kconfig | 12 +++ + board/armltd/designstart/Makefile | 8 ++ + board/armltd/designstart/designstart.c | 49 ++++++++++ + configs/designstart_ca5_defconfig | 37 ++++++++ + include/configs/designstart_ca5.h | 122 +++++++++++++++++++++++++ + 6 files changed, 235 insertions(+) + create mode 100644 board/armltd/designstart/Kconfig + create mode 100644 board/armltd/designstart/Makefile + create mode 100644 board/armltd/designstart/designstart.c + create mode 100644 configs/designstart_ca5_defconfig + create mode 100644 include/configs/designstart_ca5.h + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index f9dab073ea14..2cc9413114de 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -628,6 +628,12 @@ config ARCH_BCM6858 + select OF_CONTROL + imply CMD_DM + ++config TARGET_DESIGNSTART_CA5 ++ bool "Support Designstart Cortex-A5" ++ select CPU_V7A ++ select SEMIHOSTING ++ select PL01X_SERIAL ++ + config TARGET_VEXPRESS_CA15_TC2 + bool "Support vexpress_ca15_tc2" + select CPU_V7A +@@ -1782,6 +1788,7 @@ source "board/Marvell/gplugd/Kconfig" + source "board/armadeus/apf27/Kconfig" + source "board/armltd/vexpress/Kconfig" + source "board/armltd/vexpress64/Kconfig" ++source "board/armltd/designstart/Kconfig" + source "board/broadcom/bcm23550_w1d/Kconfig" + source "board/broadcom/bcm28155_ap/Kconfig" + source "board/broadcom/bcm963158/Kconfig" +diff --git a/board/armltd/designstart/Kconfig b/board/armltd/designstart/Kconfig +new file mode 100644 +index 000000000000..6446fe3f4492 +--- /dev/null ++++ b/board/armltd/designstart/Kconfig +@@ -0,0 +1,12 @@ ++if TARGET_DESIGNSTART_CA5 ++ ++config SYS_BOARD ++ default "designstart" ++ ++config SYS_VENDOR ++ default "armltd" ++ ++config SYS_CONFIG_NAME ++ default "designstart_ca5" ++ ++endif +diff --git a/board/armltd/designstart/Makefile b/board/armltd/designstart/Makefile +new file mode 100644 +index 000000000000..b64c905c7021 +--- /dev/null ++++ b/board/armltd/designstart/Makefile +@@ -0,0 +1,8 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++# ++# (C) Copyright 2020 ARM Limited ++# (C) Copyright 2020 Linaro ++# Rui Miguel Silva <rui.silva@linaro.org> ++# ++ ++obj-y := designstart.o +diff --git a/board/armltd/designstart/designstart.c b/board/armltd/designstart/designstart.c +new file mode 100644 +index 000000000000..b0400f110ce2 +--- /dev/null ++++ b/board/armltd/designstart/designstart.c +@@ -0,0 +1,49 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2020 ARM Limited ++ * (C) Copyright 2020 Linaro ++ * Rui Miguel Silva <rui.silva@linaro.org> ++ */ ++ ++#include <common.h> ++#include <dm.h> ++#include <dm/platform_data/serial_pl01x.h> ++#include <malloc.h> ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++static const struct pl01x_serial_platdata serial_platdata = { ++ .base = V2M_UART0, ++ .type = TYPE_PL011, ++ .clock = CONFIG_PL011_CLOCK, ++}; ++ ++U_BOOT_DEVICE(designstart_serials) = { ++ .name = "serial_pl01x", ++ .platdata = &serial_platdata, ++}; ++ ++int board_init(void) ++{ ++ return 0; ++} ++ ++int dram_init(void) ++{ ++ gd->ram_size = PHYS_SDRAM_1_SIZE; ++ ++ return 0; ++} ++ ++int dram_init_banksize(void) ++{ ++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; ++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; ++ ++ return 0; ++} ++ ++void reset_cpu(ulong addr) ++{ ++} ++ +diff --git a/configs/designstart_ca5_defconfig b/configs/designstart_ca5_defconfig +new file mode 100644 +index 000000000000..a2a756740295 +--- /dev/null ++++ b/configs/designstart_ca5_defconfig +@@ -0,0 +1,37 @@ ++CONFIG_ARM=y ++CONFIG_TARGET_DESIGNSTART_CA5=y ++CONFIG_SYS_TEXT_BASE=0x88000000 ++CONFIG_SYS_MALLOC_F_LEN=0x2000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_IDENT_STRING=" ca5ds aarch32" ++CONFIG_BOOTDELAY=1 ++CONFIG_USE_BOOTARGS=y ++CONFIG_BOOTARGS="console=ttyAMA0 earlycon=pl011,0x1a200000 root=/dev/ram0 rw loglevel=9" ++# CONFIG_DISPLAY_CPUINFO is not set ++# CONFIG_DISPLAY_BOARDINFO is not set ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_PROMPT="ca5ds32# " ++CONFIG_CMD_BOOTZ=y ++# CONFIG_CMD_CONSOLE is not set ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_XIMG is not set ++# CONFIG_CMD_EDITENV is not set ++# CONFIG_CMD_ENV_EXISTS is not set ++CONFIG_CMD_MEMTEST=y ++CONFIG_MTD_NOR_FLASH=y ++# CONFIG_CMD_LOADS is not set ++CONFIG_CMD_ARMFLASH=y ++# CONFIG_CMD_FPGA is not set ++# CONFIG_CMD_ITEST is not set ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_DHCP=y ++# CONFIG_CMD_NFS is not set ++CONFIG_CMD_MII=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_CACHE=y ++# CONFIG_CMD_MISC is not set ++CONFIG_CMD_FAT=y ++CONFIG_DM=y ++CONFIG_DM_SERIAL=y ++CONFIG_OF_LIBFDT=y ++ +diff --git a/include/configs/designstart_ca5.h b/include/configs/designstart_ca5.h +new file mode 100644 +index 000000000000..79c4b36060d2 +--- /dev/null ++++ b/include/configs/designstart_ca5.h +@@ -0,0 +1,122 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * (C) Copyright 2020 ARM Limited ++ * (C) Copyright 2020 Linaro ++ * Rui Miguel Silva <rui.silva@linaro.org> ++ * ++ * Configuration for Cortex-A5 Designstart. Parts were derived from other ARM ++ * configurations. ++ */ ++ ++#ifndef __DESISGNSTART_CA5_H ++#define __DESISGNSTART_CA5_H ++ ++#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) ++#define CONFIG_SKIP_LOWLEVEL_INIT ++ ++/* Generic Timer Definitions */ ++#define CONFIG_SYS_HZ_CLOCK 7500000 ++#define CONFIG_SYS_HZ 1000 ++#define COUNTER_FREQUENCY CONFIG_SYS_HZ_CLOCK ++ ++#ifdef CONFIG_DESIGNSTART_MEMORY_MAP_EXTENDED ++#define V2M_SRAM0 0x00010000 ++#define V2M_SRAM1 0x02200000 ++#define V2M_QSPI 0x0A800000 ++#else ++#define V2M_SRAM0 0x00000000 ++#define V2M_SRAM1 0x02000000 ++#define V2M_QSPI 0x08000000 ++#endif ++ ++#define V2M_DEBUG 0x10000000 ++#define V2M_BASE_PERIPH 0x1A000000 ++#define V2M_A5_PERIPH 0x1C000000 ++#define V2M_L2CC_PERIPH 0x1C010000 ++ ++#define V2M_MASTER_EXPANSION0 0x40000000 ++#define V2M_MASTER_EXPANSION1 0x60000000 ++ ++#define V2M_BASE 0x80000000 ++ ++#define V2M_PERIPH_OFFSET(x) (x << 16) ++ ++#define V2M_SYSID (V2M_BASE_PERIPH) ++#define V2M_SYCTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(1)) ++#define V2M_COUNTER_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(2)) ++#define V2M_COUNTER_READ (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(3)) ++#define V2M_TIMER_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(4)) ++#define V2M_TIMER0 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(5)) ++ ++#define V2M_WATCHDOG_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(16)) ++#define V2M_WATCHDOG_REFRESH (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(17)) ++ ++#define V2M_UART0 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(32)) ++#define V2M_UART1 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(33)) ++ ++#define V2M_RTC (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(34)) ++#define V2M_TRNG (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(35)) ++ ++/* PL011 Serial Configuration */ ++#define CONFIG_CONS_INDEX 0 ++#define CONFIG_PL011_CLOCK 7500000 ++ ++/* Physical Memory Map */ ++#define PHYS_SDRAM_1 (V2M_BASE) ++ ++/* Top 16MB reserved for secure world use */ ++#define DRAM_SEC_SIZE 0x01000000 ++#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE ++ ++/* Size of malloc() pool */ ++#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) ++ ++/* Miscellaneous configurable options */ ++#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) ++ ++#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 ++ ++#define CONFIG_SYS_MMIO_TIMER ++ ++/* Enable memtest */ ++#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 ++#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "kernel_name=Image\0" \ ++ "kernel_addr=0x80F00000\0" \ ++ "initrd_name=ramdisk.img\0" \ ++ "initrd_addr=0x84000000\0" \ ++ "fdt_name=devtree.dtb\0" \ ++ "fdt_addr=0x83000000\0" \ ++ "fdt_high=0xffffffff\0" \ ++ "initrd_high=0xffffffff\0" ++ ++#define CONFIG_BOOTCOMMAND "echo copy to RAM...; " \ ++ "cp.b 0x80100000 $kernel_addr 0xB00000; " \ ++ "cp.b 0x80D00000 $initrd_addr 0x800000; " \ ++ "bootz $kernel_addr $initrd_addr $fdt_addr" ++ ++/* Monitor Command Prompt */ ++#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ ++#define CONFIG_SYS_MAXARGS 64 /* max command args */ ++ ++#define CONFIG_SYS_FLASH_BASE 0x80000000 ++/* 256 x 256KiB sectors */ ++#define CONFIG_SYS_MAX_FLASH_SECT 256 ++/* Store environment at top of flash */ ++#define CONFIG_ENV_ADDR 0x0A7C0000 ++#define CONFIG_ENV_SECT_SIZE 0x00040000 ++ ++#define CONFIG_SYS_FLASH_CFI 1 ++#define CONFIG_FLASH_CFI_DRIVER 1 ++#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT ++#define CONFIG_SYS_MAX_FLASH_BANKS 1 ++ ++#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ ++#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ ++#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ ++#define FLASH_MAX_SECTOR_SIZE 0x00040000 ++#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE ++#define CONFIG_ENV_IS_IN_FLASH 1 ++#endif +-- +2.25.0 + diff --git a/bsp/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/files/fvp-common/u-boot_vexpress_fvp.patch b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/files/fvp-common/u-boot_vexpress_fvp.patch new file mode 100644 index 00000000..bdca202c --- /dev/null +++ b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/files/fvp-common/u-boot_vexpress_fvp.patch @@ -0,0 +1,13 @@ +diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig +index c9cec8322c..3a339be6a2 100644 +--- a/configs/vexpress_aemv8a_semi_defconfig ++++ b/configs/vexpress_aemv8a_semi_defconfig +@@ -9,7 +9,7 @@ CONFIG_IDENT_STRING=" vexpress_aemv8a" + CONFIG_DISTRO_DEFAULTS=y + CONFIG_BOOTDELAY=1 + CONFIG_USE_BOOTARGS=y +-CONFIG_BOOTARGS="console=ttyAMA0 earlycon=pl011,0x1c090000 debug user_debug=31 loglevel=9" ++CONFIG_BOOTARGS="console=ttyAMA0 earlyprintk=pl011,0x1c090000 debug user_debug=31 androidboot.hardware=fvpbase root=/dev/vda2 rw rootwait loglevel=9" + # CONFIG_USE_BOOTCOMMAND is not set + # CONFIG_DISPLAY_CPUINFO is not set + # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/bsp/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/files/juno/u-boot_vexpress_uenv.patch b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/files/juno/u-boot_vexpress_uenv.patch new file mode 100644 index 00000000..bb90c176 --- /dev/null +++ b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/files/juno/u-boot_vexpress_uenv.patch @@ -0,0 +1,37 @@ +diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h +index 2354f4e958..3e01f477dc 100644 +--- a/include/configs/vexpress_aemv8a.h ++++ b/include/configs/vexpress_aemv8a.h +@@ -151,6 +151,32 @@ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ ++ "bootenvfile=uEnv.txt\0" \ ++ "bootcmd=run envboot\0" \ ++ "envboot=if run loadbootenv; then echo Loading env from ${bootenvfile}; run importbootenv; else run default_bootcmd; fi; if test -n $uenvcmd; then echo Running uenvcmd ...; run uenvcmd;fi;\0" \ ++ "importbootenv=echo Importing environment from memory, size ${filesize}; env import -t ${loadaddr} ${filesize}\0" \ ++ "loadaddr=0x82000000\0" \ ++ "filesize=0x4000\0" \ ++ "loadbootenv=mw.l ${loadaddr} 0 0x1000; afs load ${bootenvfile} ${loadaddr}\0" \ ++ "default_bootcmd=echo running default boot command; afs load ${kernel_name} ${kernel_addr} ; " \ ++ "if test $? -eq 1; then "\ ++ " echo Loading ${kernel_alt_name} instead of "\ ++ "${kernel_name}; "\ ++ " afs load ${kernel_alt_name} ${kernel_addr};"\ ++ "fi ; "\ ++ "afs load ${fdtfile} ${fdt_addr} ; " \ ++ "if test $? -eq 1; then "\ ++ " echo Loading ${fdt_alt_name} instead of "\ ++ "${fdtfile}; "\ ++ " afs load ${fdt_alt_name} ${fdt_addr}; "\ ++ "fi ; "\ ++ "fdt addr ${fdt_addr}; fdt resize; " \ ++ "if afs load ${initrd_name} ${initrd_addr} ; "\ ++ "then "\ ++ " setenv initrd_param ${initrd_addr}; "\ ++ " else setenv initrd_param -; "\ ++ "fi ; " \ ++ "booti ${kernel_addr} ${initrd_param} ${fdt_addr}\0" + + /* Copy the kernel and FDT to DRAM memory and boot */ + #define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr} ; " \ diff --git a/bsp/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend new file mode 100644 index 00000000..20133a4d --- /dev/null +++ b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend @@ -0,0 +1,8 @@ +# Machine specific u-boot + +FILESEXTRAPATHS_prepend := "${THISDIR}/files/${MACHINE}:" + +SRC_URI_append_a5ds = " file://0001-armv7-add-mmio-timer.patch \ + file://0002-board-arm-add-designstart-cortex-a5-board.patch" + + diff --git a/bsp/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot_2020.%.bbappend b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot_2020.%.bbappend new file mode 100644 index 00000000..a46e36f0 --- /dev/null +++ b/bsp/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot_2020.%.bbappend @@ -0,0 +1,13 @@ +# u-boot_2020 patch for fvp machinesboard + +# +# Patch u-boot to change kernel command line +# + +FILESEXTRAPATHS_prepend_fvp-base := "${THISDIR}/files/fvp-common:" +FILESEXTRAPATHS_prepend_foundation-armv8 := "${THISDIR}/files/fvp-common:" +FILESEXTRAPATHS_prepend_juno := "${THISDIR}/files:" + +SRC_URI_append_fvp-base = " file://u-boot_vexpress_fvp.patch" +SRC_URI_append_foundation-armv8 = " file://u-boot_vexpress_fvp.patch" +SRC_URI_append_juno = " file://u-boot_vexpress_uenv.patch" |