diff options
Diffstat (limited to 'bsp/meta-freescale-3rdparty/recipes-bsp/rcw')
9 files changed, 1471 insertions, 0 deletions
diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0001-lx2160acex7-misc-RCW-files.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0001-lx2160acex7-misc-RCW-files.patch new file mode 100644 index 00000000..ae873990 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0001-lx2160acex7-misc-RCW-files.patch @@ -0,0 +1,640 @@ +From ef5ab1b5a7262a6ef9caf334b0c772b0ebf00fdf Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Sun, 28 Jul 2019 14:43:06 +0300 +Subject: [PATCH] lx2160acex7 misc RCW files + +This patch adds support for lx2160a rcw project. +In general RCW has lots of redundent files and can be restructured +better as in this patch. + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + lx2160acex7/Makefile | 2 + + lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig | 61 +++++++++++++++++++ + .../rcw_1900_600_2600_17_4_2.rcw | 4 ++ + .../rcw_1900_600_2600_17_4_2_sd.rcw | 4 ++ + .../rcw_2000_700_2400_13_5_2_sd.rcw | 4 ++ + .../rcw_2000_700_2400_20_5_2_sd.rcw | 4 ++ + .../rcw_2000_700_2400_8_5_2_sd.rcw | 4 ++ + .../rcw_2000_700_2600_8_5_2_sd.rcw | 4 ++ + .../rcw_2000_700_2900_17_4_2_sd.rcw | 4 ++ + .../rcw_2000_700_2900_8_5_2_sd.rcw | 4 ++ + .../rcw_2000_700_3200_17_4_2_sd.rcw | 4 ++ + .../rcw_2000_700_3200_20_5_2_sd.rcw | 4 ++ + .../rcw_2000_700_3200_8_5_0_sd.rcw | 4 ++ + .../rcw_2000_700_3200_8_5_2_sd.rcw | 4 ++ + .../rcw_2000_700_3200_8_5_2_xspi.rcw | 4 ++ + .../rcw_2400_700_3200_8_5_2_sd.rcw | 4 ++ + .../rcw_2500_700_3200_8_5_2_sd.rcw | 4 ++ + .../rcw_2600_700_3200_8_5_2_sd.rcw | 4 ++ + .../XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw | 4 ++ + lx2160acex7/configs/lx2160a_13_5_2.rcwi | 3 + + lx2160acex7/configs/lx2160a_17_4_2.rcwi | 7 +++ + .../configs/lx2160a_1900_600_2600.rcwi | 12 ++++ + .../configs/lx2160a_2000_700_2400.rcwi | 12 ++++ + .../configs/lx2160a_2000_700_2600.rcwi | 12 ++++ + .../configs/lx2160a_2000_700_2900.rcwi | 12 ++++ + .../configs/lx2160a_2000_700_3200.rcwi | 12 ++++ + lx2160acex7/configs/lx2160a_20_5_2.rcwi | 7 +++ + .../configs/lx2160a_2400_700_3200.rcwi | 12 ++++ + .../configs/lx2160a_2500_700_3200.rcwi | 12 ++++ + .../configs/lx2160a_2600_700_3200.rcwi | 12 ++++ + lx2160acex7/configs/lx2160a_8_5_0.rcwi | 7 +++ + lx2160acex7/configs/lx2160a_8_5_2.rcwi | 7 +++ + lx2160acex7/configs/lx2160a_defaults.rcwi | 19 ++++++ + lx2160acex7/configs/lx2160a_sdboot.rcwi | 20 ++++++ + lx2160acex7/configs/lx2160a_test.rcwi | 20 ++++++ + lx2160acex7/configs/lx2160a_xspiboot.rcwi | 17 ++++++ + 36 files changed, 334 insertions(+) + create mode 100644 lx2160acex7/Makefile + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw + create mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw + create mode 100644 lx2160acex7/configs/lx2160a_13_5_2.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_17_4_2.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_1900_600_2600.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_2000_700_2400.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_2000_700_2600.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_2000_700_2900.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_2000_700_3200.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_20_5_2.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_2400_700_3200.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_2500_700_3200.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_2600_700_3200.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_8_5_0.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_8_5_2.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_defaults.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_sdboot.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_test.rcwi + create mode 100644 lx2160acex7/configs/lx2160a_xspiboot.rcwi + +diff --git a/lx2160acex7/Makefile b/lx2160acex7/Makefile +new file mode 100644 +index 0000000..d7e9447 +--- /dev/null ++++ b/lx2160acex7/Makefile +@@ -0,0 +1,2 @@ ++include ../Makefile.inc ++ +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig +new file mode 100644 +index 0000000..cdb6446 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig +@@ -0,0 +1,61 @@ ++/* ++ * SerDes Protocol 1 - 19 ++ * SerDes Protocol 2 - 5 ++ * SerDes Protocol 3 - 2 ++ * ++ * Frequencies: ++ * Core -- 1900 MHz ++ * Platform -- 600 MHz ++ * DDR -- 2600 MT/s ++ */ ++ ++#include <../lx2160asi/lx2160a.rcwi> ++ ++SYS_PLL_RAT=12 ++MEM_PLL_CFG=3 ++MEM_PLL_RAT=26 ++MEM2_PLL_CFG=3 ++MEM2_PLL_RAT=26 ++CGA_PLL1_RAT=19 ++CGA_PLL2_RAT=19 ++CGB_PLL1_RAT=19 ++CGB_PLL2_RAT=9 ++C5_PLL_SEL=0 ++C6_PLL_SEL=0 ++C7_PLL_SEL=0 ++C8_PLL_SEL=0 ++HWA_CGA_M1_CLK_SEL=1 ++HWA_CGB_M1_CLK_SEL=7 ++BOOT_LOC=26 ++SYSCLK_FREQ=600 ++IIC2_PMUX=6 ++IIC3_PMUX=2 ++IIC4_PMUX=2 ++USB3_CLK_FSEL=39 ++SRDS_PRTCL_S1=19 ++SRDS_PRTCL_S2=5 ++SRDS_PRTCL_S3=2 ++SRDS_PLL_REF_CLK_SEL_S1=2 ++SRDS_DIV_PEX_S1=1 ++SRDS_DIV_PEX_S2=3 ++SRDS_DIV_PEX_S3=1 ++ ++/* Errata to write on scratch reg for validation */ ++#include <../lx2160asi/scratchrw1.rcw> ++ ++/* Copy SPL Uboot to Ocram */ ++.pbi ++blockcopy 0x08,0x00100000,0x1800a000,0x00020000 ++.end ++ ++/* Boot Location Pointer */ ++#include <../lx2160asi/bootlocptr_sd.rcw> ++ ++/* Errata for SATA controller */ ++#include <../lx2160asi/a010554.rcw> ++ ++/* Modify FlexSPI Clock Divisor value */ ++#include <../lx2160asi/flexspi_divisor_24.rcw> ++ ++/* common PBI commands */ ++#include <../lx2160asi/common.rcw> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw +new file mode 100644 +index 0000000..13ab0b9 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_1900_600_2600.rcwi> ++#include <configs/lx2160a_17_4_2.rcwi> ++#include <configs/lx2160a_xspiboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw +new file mode 100644 +index 0000000..14fae8c +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_1900_600_2600.rcwi> ++#include <configs/lx2160a_17_4_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw +new file mode 100644 +index 0000000..2dae5a2 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2000_700_2400.rcwi> ++#include <configs/lx2160a_13_5_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw +new file mode 100644 +index 0000000..5335072 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2000_700_2400.rcwi> ++#include <configs/lx2160a_20_5_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw +new file mode 100644 +index 0000000..e2a5bd3 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2000_700_2400.rcwi> ++#include <configs/lx2160a_8_5_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw +new file mode 100644 +index 0000000..a330bfe +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2000_700_2600.rcwi> ++#include <configs/lx2160a_8_5_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw +new file mode 100644 +index 0000000..8535dbd +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2000_700_2900.rcwi> ++#include <configs/lx2160a_17_4_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw +new file mode 100644 +index 0000000..698be01 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2000_700_2900.rcwi> ++#include <configs/lx2160a_8_5_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw +new file mode 100644 +index 0000000..780d8c3 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2000_700_3200.rcwi> ++#include <configs/lx2160a_17_4_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw +new file mode 100644 +index 0000000..eb9d240 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2000_700_3200.rcwi> ++#include <configs/lx2160a_20_5_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw +new file mode 100644 +index 0000000..ceb53a3 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2000_700_3200.rcwi> ++#include <configs/lx2160a_8_5_0.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw +new file mode 100644 +index 0000000..a220e98 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2000_700_3200.rcwi> ++#include <configs/lx2160a_8_5_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw +new file mode 100644 +index 0000000..1eabd7d +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2000_700_3200.rcwi> ++#include <configs/lx2160a_8_5_2.rcwi> ++#include <configs/lx2160a_xspiboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw +new file mode 100644 +index 0000000..2ac59b1 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2400_700_3200.rcwi> ++#include <configs/lx2160a_8_5_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw +new file mode 100644 +index 0000000..e7c08df +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2500_700_3200.rcwi> ++#include <configs/lx2160a_8_5_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw +new file mode 100644 +index 0000000..1e7a8f7 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_2600_700_3200.rcwi> ++#include <configs/lx2160a_8_5_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw +new file mode 100644 +index 0000000..86f12f8 +--- /dev/null ++++ b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw +@@ -0,0 +1,4 @@ ++#include <configs/lx2160a_defaults.rcwi> ++#include <configs/lx2160a_test.rcwi> ++#include <configs/lx2160a_17_4_2.rcwi> ++#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/configs/lx2160a_13_5_2.rcwi b/lx2160acex7/configs/lx2160a_13_5_2.rcwi +new file mode 100644 +index 0000000..76f44bc +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_13_5_2.rcwi +@@ -0,0 +1,3 @@ ++SRDS_PRTCL_S1=13 ++SRDS_PRTCL_S2=5 ++SRDS_PRTCL_S3=2 +diff --git a/lx2160acex7/configs/lx2160a_17_4_2.rcwi b/lx2160acex7/configs/lx2160a_17_4_2.rcwi +new file mode 100644 +index 0000000..358972d +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_17_4_2.rcwi +@@ -0,0 +1,7 @@ ++SRDS_PRTCL_S1=17 ++SRDS_PRTCL_S2=4 ++SRDS_PRTCL_S3=2 ++ ++/*SRDS_INTRA_REF_CLK_S1 = 1*/ /* PLLF used for PLLS */ ++/*SRDS_PLL_REF_CLK_SEL_S1=2*/ ++ +diff --git a/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi b/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi +new file mode 100644 +index 0000000..8b61021 +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi +@@ -0,0 +1,12 @@ ++CGA_PLL1_RAT=19 ++CGA_PLL2_RAT=19 ++CGB_PLL1_RAT=19 ++CGB_PLL2_RAT=9 ++ ++SYS_PLL_RAT=12 ++ ++MEM_PLL_RAT=26 ++MEM2_PLL_RAT=26 ++ ++/* Modify FlexSPI Clock Divisor value */ ++/* #include <../lx2160asi/flexspi_divisor_24.rcw>*/ +diff --git a/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi b/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi +new file mode 100644 +index 0000000..6b0b150 +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi +@@ -0,0 +1,12 @@ ++CGA_PLL1_RAT=20 ++CGA_PLL2_RAT=20 ++CGB_PLL1_RAT=20 ++CGB_PLL2_RAT=9 ++ ++SYS_PLL_RAT=14 ++ ++MEM_PLL_RAT=24 ++MEM2_PLL_RAT=24 ++ ++/* Modify FlexSPI Clock Divisor value */ ++/* #include <../lx2160asi/flexspi_divisor_28.rcw>*/ +diff --git a/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi b/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi +new file mode 100644 +index 0000000..21dce67 +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi +@@ -0,0 +1,12 @@ ++CGA_PLL1_RAT=20 ++CGA_PLL2_RAT=20 ++CGB_PLL1_RAT=20 ++CGB_PLL2_RAT=9 ++ ++SYS_PLL_RAT=14 ++ ++MEM_PLL_RAT=26 ++MEM2_PLL_RAT=26 ++ ++/* Modify FlexSPI Clock Divisor value */ ++/* #include <../lx2160asi/flexspi_divisor_28.rcw>*/ +diff --git a/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi b/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi +new file mode 100644 +index 0000000..e6a8e30 +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi +@@ -0,0 +1,12 @@ ++CGA_PLL1_RAT=20 ++CGA_PLL2_RAT=20 ++CGB_PLL1_RAT=20 ++CGB_PLL2_RAT=9 ++ ++SYS_PLL_RAT=14 ++ ++MEM_PLL_RAT=29 ++MEM2_PLL_RAT=29 ++ ++/* Modify FlexSPI Clock Divisor value */ ++/* #include <../lx2160asi/flexspi_divisor_28.rcw>*/ +diff --git a/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi +new file mode 100644 +index 0000000..27ee377 +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi +@@ -0,0 +1,12 @@ ++CGA_PLL1_RAT=20 ++CGA_PLL2_RAT=20 ++CGB_PLL1_RAT=20 ++CGB_PLL2_RAT=9 ++ ++SYS_PLL_RAT=14 ++ ++MEM_PLL_RAT=32 ++MEM2_PLL_RAT=32 ++ ++/* Modify FlexSPI Clock Divisor value */ ++#include <../lx2160asi/flexspi_divisor_28.rcw> +diff --git a/lx2160acex7/configs/lx2160a_20_5_2.rcwi b/lx2160acex7/configs/lx2160a_20_5_2.rcwi +new file mode 100644 +index 0000000..c2c7bea +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_20_5_2.rcwi +@@ -0,0 +1,7 @@ ++SRDS_PRTCL_S1=20 ++SRDS_PRTCL_S2=5 ++SRDS_PRTCL_S3=2 ++ ++SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */ ++SRDS_PLL_REF_CLK_SEL_S1=2 ++SRDS_PLL_PD_PLL1=1 +diff --git a/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi +new file mode 100644 +index 0000000..fc0fd6c +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi +@@ -0,0 +1,12 @@ ++CGA_PLL1_RAT=24 ++CGA_PLL2_RAT=24 ++CGB_PLL1_RAT=24 ++CGB_PLL2_RAT=9 ++ ++SYS_PLL_RAT=14 ++ ++MEM_PLL_RAT=32 ++MEM2_PLL_RAT=32 ++ ++/* Modify FlexSPI Clock Divisor value */ ++#include <../lx2160asi/flexspi_divisor_28.rcw> +diff --git a/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi +new file mode 100644 +index 0000000..62d9069 +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi +@@ -0,0 +1,12 @@ ++CGA_PLL1_RAT=25 ++CGA_PLL2_RAT=25 ++CGB_PLL1_RAT=25 ++CGB_PLL2_RAT=9 ++ ++SYS_PLL_RAT=14 ++ ++MEM_PLL_RAT=32 ++MEM2_PLL_RAT=32 ++ ++/* Modify FlexSPI Clock Divisor value */ ++#include <../lx2160asi/flexspi_divisor_28.rcw> +diff --git a/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi +new file mode 100644 +index 0000000..e244917 +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi +@@ -0,0 +1,12 @@ ++CGA_PLL1_RAT=26 ++CGA_PLL2_RAT=26 ++CGB_PLL1_RAT=26 ++CGB_PLL2_RAT=9 ++ ++SYS_PLL_RAT=14 ++ ++MEM_PLL_RAT=32 ++MEM2_PLL_RAT=32 ++ ++/* Modify FlexSPI Clock Divisor value */ ++#include <../lx2160asi/flexspi_divisor_28.rcw> +diff --git a/lx2160acex7/configs/lx2160a_8_5_0.rcwi b/lx2160acex7/configs/lx2160a_8_5_0.rcwi +new file mode 100644 +index 0000000..62ff153 +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_8_5_0.rcwi +@@ -0,0 +1,7 @@ ++SRDS_PRTCL_S1=8 /* should be 8 */ ++SRDS_PRTCL_S2=5 ++SRDS_PRTCL_S3=0 ++ ++SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */ ++SRDS_PLL_REF_CLK_SEL_S1=2 ++SRDS_PLL_PD_PLL1=1 +diff --git a/lx2160acex7/configs/lx2160a_8_5_2.rcwi b/lx2160acex7/configs/lx2160a_8_5_2.rcwi +new file mode 100644 +index 0000000..d7d707a +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_8_5_2.rcwi +@@ -0,0 +1,7 @@ ++SRDS_PRTCL_S1=8 /* should be 8 */ ++SRDS_PRTCL_S2=5 ++SRDS_PRTCL_S3=2 ++ ++SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */ ++SRDS_PLL_REF_CLK_SEL_S1=2 ++SRDS_PLL_PD_PLL1=1 +diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi +new file mode 100644 +index 0000000..6fd65ec +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_defaults.rcwi +@@ -0,0 +1,19 @@ ++#include <../lx2160asi/lx2160a.rcwi> ++MEM_PLL_CFG=3 ++MEM2_PLL_CFG=3 ++C5_PLL_SEL=0 ++C6_PLL_SEL=0 ++C7_PLL_SEL=0 ++C8_PLL_SEL=0 ++HWA_CGA_M1_CLK_SEL=1 ++HWA_CGB_M1_CLK_SEL=7 ++BOOT_LOC=26 ++SYSCLK_FREQ=600 ++IIC2_PMUX=6 ++IIC3_PMUX=0 ++IIC4_PMUX=2 ++USB3_CLK_FSEL=39 ++SRDS_DIV_PEX_S1=1 ++SRDS_DIV_PEX_S2=3 ++SRDS_DIV_PEX_S3=1 ++ +diff --git a/lx2160acex7/configs/lx2160a_sdboot.rcwi b/lx2160acex7/configs/lx2160a_sdboot.rcwi +new file mode 100644 +index 0000000..d537ea5 +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_sdboot.rcwi +@@ -0,0 +1,20 @@ ++/* Errata to write on scratch reg for validation */ ++#include <../lx2160asi/scratchrw1.rcw> ++ ++/* Copy SPL Uboot to Ocram */ ++.pbi ++blockcopy 0x08,0x00100000,0x1800a000,0x00020000 ++.end ++ ++/* Boot Location Pointer */ ++#include <../lx2160asi/bootlocptr_sd.rcw> ++ ++/* Errata for SATA controller */ ++#include <../lx2160asi/a010554.rcw> ++ ++/* Errata for PCIe controller */ ++#include <../lx2160asi/a011270.rcw> ++ ++/* common PBI commands */ ++#include <../lx2160asi/common.rcw> ++ +diff --git a/lx2160acex7/configs/lx2160a_test.rcwi b/lx2160acex7/configs/lx2160a_test.rcwi +new file mode 100644 +index 0000000..a223be1 +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_test.rcwi +@@ -0,0 +1,20 @@ ++CGA_PLL1_RAT=20 ++CGA_PLL2_RAT=20 ++CGB_PLL1_RAT=20 ++CGB_PLL2_RAT=8 ++ ++SYS_PLL_RAT=12 ++ ++MEM_PLL_RAT=32 ++MEM2_PLL_RAT=32 ++ ++/* Modify FlexSPI Clock Divisor value */ ++/* #include <../lx2160asi/flexspi_divisor_24.rcw> */ ++ ++SRDS_PLL_PD_PLL1=1 ++SRDS_PLL_PD_PLL2=1 ++SRDS_PLL_PD_PLL3=1 ++SRDS_PLL_PD_PLL4=1 ++SRDS_PLL_PD_PLL5=1 ++SRDS_PLL_PD_PLL6=1 ++ +diff --git a/lx2160acex7/configs/lx2160a_xspiboot.rcwi b/lx2160acex7/configs/lx2160a_xspiboot.rcwi +new file mode 100644 +index 0000000..eecc314 +--- /dev/null ++++ b/lx2160acex7/configs/lx2160a_xspiboot.rcwi +@@ -0,0 +1,17 @@ ++/* Errata to write on scratch reg for validation */ ++#include <../lx2160asi/scratchrw1.rcw> ++ ++/* Boot Location Pointer */ ++#include <../lx2160asi/bootlocptr_nor.rcw> ++ ++/* Errata for SATA controller */ ++#include <../lx2160asi/a010554.rcw> ++ ++/* Errata for PCIe controller */ ++#include <../lx2160asi/a011270.rcw> ++ ++/* common PBI commands */ ++#include <../lx2160asi/common.rcw> ++ ++/* Modify FlexSPI Clock Divisor value */ ++#include <../lx2160asi/flexspi_divisor_24.rcw> +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0002-Set-io-pads-as-GPIO.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0002-Set-io-pads-as-GPIO.patch new file mode 100644 index 00000000..b156a018 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0002-Set-io-pads-as-GPIO.patch @@ -0,0 +1,38 @@ +From b184697cff85d8f98e765014309b97444ff1c5b7 Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Wed, 30 Oct 2019 11:43:37 +0200 +Subject: [PATCH 2/2] Set io pads as GPIO + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + lx2160acex7/configs/lx2160a_defaults.rcwi | 9 +++++++-- + 1 file changed, 7 insertions(+), 2 deletions(-) + +diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi +index 6fd65ec..dbc843f 100644 +--- a/lx2160acex7/configs/lx2160a_defaults.rcwi ++++ b/lx2160acex7/configs/lx2160a_defaults.rcwi +@@ -9,11 +9,16 @@ HWA_CGA_M1_CLK_SEL=1 + HWA_CGB_M1_CLK_SEL=7 + BOOT_LOC=26 + SYSCLK_FREQ=600 +-IIC2_PMUX=6 ++IIC2_PMUX=1 + IIC3_PMUX=0 + IIC4_PMUX=2 + USB3_CLK_FSEL=39 + SRDS_DIV_PEX_S1=1 + SRDS_DIV_PEX_S2=3 + SRDS_DIV_PEX_S3=1 +- ++SDHC1_DIR_PMUX=1 ++IRQ03_00_PMUX=1 ++IRQ07_04_PMUX=1 ++IRQ11_08_PMUX=1 ++EVT20_PMUX=1 ++EVT43_PMUX=1 +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0003-S2-enable-gen3-xspi-increase-divisor-to-28.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0003-S2-enable-gen3-xspi-increase-divisor-to-28.patch new file mode 100644 index 00000000..18d37a65 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0003-S2-enable-gen3-xspi-increase-divisor-to-28.patch @@ -0,0 +1,42 @@ +From 3b0e8b6e242549c2ed992d7556d7966a77b6da86 Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Tue, 5 Nov 2019 10:35:32 +0200 +Subject: [PATCH] S2 - enable gen3, xspi increase divisor to 28 + +Serdes group 2 enable PCIe gen 3 +XSPI increase divisor to 28 - this fixes UEFI SPI flash detection. + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + lx2160acex7/configs/lx2160a_defaults.rcwi | 2 +- + lx2160acex7/configs/lx2160a_xspiboot.rcwi | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi +index dbc843f..3ea7683 100644 +--- a/lx2160acex7/configs/lx2160a_defaults.rcwi ++++ b/lx2160acex7/configs/lx2160a_defaults.rcwi +@@ -14,7 +14,7 @@ IIC3_PMUX=0 + IIC4_PMUX=2 + USB3_CLK_FSEL=39 + SRDS_DIV_PEX_S1=1 +-SRDS_DIV_PEX_S2=3 ++SRDS_DIV_PEX_S2=1 + SRDS_DIV_PEX_S3=1 + SDHC1_DIR_PMUX=1 + IRQ03_00_PMUX=1 +diff --git a/lx2160acex7/configs/lx2160a_xspiboot.rcwi b/lx2160acex7/configs/lx2160a_xspiboot.rcwi +index eecc314..28310c9 100644 +--- a/lx2160acex7/configs/lx2160a_xspiboot.rcwi ++++ b/lx2160acex7/configs/lx2160a_xspiboot.rcwi +@@ -14,4 +14,4 @@ + #include <../lx2160asi/common.rcw> + + /* Modify FlexSPI Clock Divisor value */ +-#include <../lx2160asi/flexspi_divisor_24.rcw> ++#include <../lx2160asi/flexspi_divisor_28.rcw> +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0004-refactor-a009531-a008851-and-a011270.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0004-refactor-a009531-a008851-and-a011270.patch new file mode 100644 index 00000000..0bcc5d33 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0004-refactor-a009531-a008851-and-a011270.patch @@ -0,0 +1,181 @@ +From c7c3ed47f1de7c20de348a6ca5fe0d5a18912f4b Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Mon, 23 Mar 2020 12:16:13 +0200 +Subject: [PATCH 4/4] refactor a009531, a008851 and a011270 + +1. Add 'load conditional', 'jump condidional' and 'jump' to PBI +instructions. +2. Use SVR register to execute the PCIe workarounds on the relevant rev +of the device. + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + lx2160asi/a009531_a008851.rcw | 96 +++++++++++++++++++++++++++++++++++ + lx2160asi/a011270.rcw | 6 +++ + rcw.py | 28 ++++++++++ + 3 files changed, 130 insertions(+) + create mode 100644 lx2160asi/a009531_a008851.rcw + +diff --git a/lx2160asi/a009531_a008851.rcw b/lx2160asi/a009531_a008851.rcw +new file mode 100644 +index 0000000..0eb7051 +--- /dev/null ++++ b/lx2160asi/a009531_a008851.rcw +@@ -0,0 +1,96 @@ ++/* ++ * Work-around for erratum A-009531 ++ * ++ * Description: ++ * As defined in section 2.2.6.4, Relaxed Ordering and ID-Based Ordering (IDO) ++ * Attributes of the PCI Express Base Specification Rev 3.1, “A Completer ++ * is permitted to set IDO only if the IDO Completion Enable bit in the Device ++ * Control 2 Register is set. It is not required to copy the value of IDO from ++ * the Request into the Completion(s) for that Request". ++ * ++ * However, the PCI Express controller as the completer sets the IDO bit in the ++ * completion packet header, in response to non-posted requests (memory read) with ++ * IDO bit set in the packet header, even if the IDO Completion Enable bit in the ++ * Device Control 2 Register is not set. ++ * ++ * Impact: ++ * The PCI Express controller as the completer sends completion packets with IDO ++ * bit set in packet header even when the IDO Completion Enable bit is cleared in ++ * the controller’s Device Control 2 Register. ++ * Applicable for SNP PCIe controller ++ */ ++ ++/* ++ * Work-around for erratum A-008851 ++ * ++ * Invalid transmitter/receiver preset values are used in Gen3 equalization ++ * phases during link training for RC mode ++ * This errata is valid only for PCI gen3. ++ * Workaround: ++ * write 0x00000001 to MISC_CONTROL_1_OFF ++ * write 0x4747 to Lane Equalization Control register for each lane ++ * Applicable for SNP PCIe controller ++ */ ++ ++.pbi ++/* Load condition SVR register mask major ID */ ++loadc 0x01e000a4,0x000000f0 ++ ++/* If it is rev 2, skip the following jump command */ ++jumpc 0x00000014,0x00000020 ++ ++/* Jump all the below instructions */ ++jump 0x190 /* All instruction below including the jump are 0x190 bytes */ ++ ++loadc 0x01ea1080,0x70000000 ++jumpc 0x00000034,0x00000000 ++write 0x03400098,0x00000000 ++write 0x034008bc,0x00000001 ++write 0x03400154,0x47474747 ++write 0x03400158,0x47474747 ++write 0x034008bc,0x00000000 ++ ++loadc 0x01ea1080,0x00700000 ++jumpc 0x00000034,0x00000000 ++write 0x03500098,0x00000000 ++write 0x035008bc,0x00000001 ++write 0x03500154,0x47474747 ++write 0x03500158,0x47474747 ++write 0x035008bc,0x00000000 ++ ++loadc 0x01eb1080,0x70000000 ++jumpc 0x00000044,0x00000000 ++write 0x03600098,0x00000000 ++write 0x036008bc,0x00000001 ++write 0x03600164,0x47474747 ++write 0x03600168,0x47474747 ++write 0x0360016c,0x47474747 ++write 0x03600170,0x47474747 ++write 0x036008bc,0x00000000 ++ ++loadc 0x01eb1080,0x00700000 ++jumpc 0x00000034,0x00000000 ++write 0x03700098,0x00000000 ++write 0x037008bc,0x00000001 ++write 0x03700154,0x47474747 ++write 0x03700158,0x47474747 ++write 0x037008bc,0x00000000 ++ ++loadc 0x01ec1080,0x70000000 ++jumpc 0x00000044,0x00000000 ++write 0x03800098,0x00000000 ++write 0x038008bc,0x00000001 ++write 0x03800164,0x47474747 ++write 0x03800168,0x47474747 ++write 0x0380016c,0x47474747 ++write 0x03800170,0x47474747 ++write 0x038008bc,0x00000000 ++ ++loadc 0x01ec1080,0x00700000 ++jumpc 0x00000034,0x00000000 ++write 0x03900098,0x00000000 ++write 0x039008bc,0x00000001 ++write 0x03900154,0x47474747 ++write 0x03900158,0x47474747 ++write 0x039008bc,0x00000000 ++.end +diff --git a/lx2160asi/a011270.rcw b/lx2160asi/a011270.rcw +index 0dc774d..5bd5558 100644 +--- a/lx2160asi/a011270.rcw ++++ b/lx2160asi/a011270.rcw +@@ -4,6 +4,12 @@ + */ + + .pbi ++/* Load condition SVR register mask major ID */ ++loadc 0x01e000a4,0x000000f0 ++/* If it is rev 1, skip the following jump command */ ++jumpc 0x00000014,0x00000010 ++/* Skip the following instructions by jumping to the end */ ++jump 0x38 + write 0x03400688,0x00000001 + write 0x03500688,0x00000001 + write 0x03600688,0x00000001 +diff --git a/rcw.py b/rcw.py +index 863f755..c2d06f6 100755 +--- a/rcw.py ++++ b/rcw.py +@@ -328,6 +328,34 @@ def build_pbi(lines): + v2 = struct.pack(endianess + 'L', p2) + subsection += v1 + subsection += v2 ++ elif op == 'loadc': ++ if p1 == None or p2 == None: ++ print('Error: "loadc" instruction requires two parameters') ++ return '' ++ v1 = struct.pack(endianess + 'L', 0x80140000) ++ v2 = struct.pack(endianess + 'L', p1) ++ v3 = struct.pack(endianess + 'L', p2) ++ subsection += v1 ++ subsection += v2 ++ subsection += v3 ++ elif op == 'jumpc': ++ if p1 == None or p2 == None: ++ print('Error: "jumpc" instruction requires two parameters') ++ return '' ++ v1 = struct.pack(endianess + 'L', 0x80850000) ++ v2 = struct.pack(endianess + 'L', p1) ++ v3 = struct.pack(endianess + 'L', p2) ++ subsection += v1 ++ subsection += v2 ++ subsection += v3 ++ elif op == 'jump': ++ if p1 == None: ++ print('Error: "jump" instruction requires a parameter') ++ return '' ++ v1 = struct.pack(endianess + 'L', 0x80840000) ++ v2 = struct.pack(endianess + 'L', p1) ++ subsection += v1 ++ subsection += v2 + elif op == 'awrite': + if p1 == None or p2 == None: + print('Error: "awrite" instruction requires two parameters') +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0006-lx2160a-add-SVR-check-for-a050234-to-apply-only-on-r.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0006-lx2160a-add-SVR-check-for-a050234-to-apply-only-on-r.patch new file mode 100644 index 00000000..68091513 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0006-lx2160a-add-SVR-check-for-a050234-to-apply-only-on-r.patch @@ -0,0 +1,32 @@ +From 2ebdb6a46e6db66cc0b09c51260a90ea8abc4713 Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Mon, 23 Mar 2020 12:35:04 +0200 +Subject: [PATCH 6/8] lx2160a: add SVR check for a050234 to apply only on rev1 + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + lx2160asi/a050234.rcw | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/lx2160asi/a050234.rcw b/lx2160asi/a050234.rcw +index 72a40e4..2130709 100644 +--- a/lx2160asi/a050234.rcw ++++ b/lx2160asi/a050234.rcw +@@ -4,6 +4,12 @@ + */ + + .pbi ++/* Load condition SVR register mask major ID */ ++loadc 0x01e000a4,0x000000f0 ++/* If it is rev 1, skip the following jump command */ ++jumpc 0x00000014,0x00000010 ++/* Skip the following instructions by jumping to the end */ ++jump 0xc8 + write 0x1ea1200,0x20081004 + write 0x1ea1240,0x20081004 + write 0x1ea1280,0x20081004 +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0007-lx2160acex7-pcie-workarounds-and-fan-full-speed.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0007-lx2160acex7-pcie-workarounds-and-fan-full-speed.patch new file mode 100644 index 00000000..9074b5cc --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0007-lx2160acex7-pcie-workarounds-and-fan-full-speed.patch @@ -0,0 +1,95 @@ +From 6d634d64528e5ba510c369a2ae19c337ae7d692e Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Mon, 23 Mar 2020 12:36:20 +0200 +Subject: [PATCH 7/8] lx2160acex7 - pcie workarounds and fan full speed + +1. Moves calling the workarounds to the _defaults.rcwi +2. Toggle fan-full-speed GPIO. The fan controller starts throttling when +a driver exists (i.e. kernel); in order to avoid overheating until then +enable full speed. +3. Run a050234.rcw on rev1 - fixes some issues observed when using Mellanox +ConnectX-5 NICs +4. Run a009531 and a00885 on rev2. + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + lx2160acex7/configs/lx2160a_defaults.rcwi | 21 +++++++++++++++++---- + lx2160acex7/configs/lx2160a_sdboot.rcwi | 6 ------ + lx2160acex7/configs/lx2160a_xspiboot.rcwi | 6 ------ + 3 files changed, 17 insertions(+), 16 deletions(-) + +diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi +index 3ea7683..7af1f5b 100644 +--- a/lx2160acex7/configs/lx2160a_defaults.rcwi ++++ b/lx2160acex7/configs/lx2160a_defaults.rcwi +@@ -1,10 +1,6 @@ + #include <../lx2160asi/lx2160a.rcwi> + MEM_PLL_CFG=3 + MEM2_PLL_CFG=3 +-C5_PLL_SEL=0 +-C6_PLL_SEL=0 +-C7_PLL_SEL=0 +-C8_PLL_SEL=0 + HWA_CGA_M1_CLK_SEL=1 + HWA_CGB_M1_CLK_SEL=7 + BOOT_LOC=26 +@@ -22,3 +18,20 @@ IRQ07_04_PMUX=1 + IRQ11_08_PMUX=1 + EVT20_PMUX=1 + EVT43_PMUX=1 ++ ++/* Drive the fan full speed pin */ ++.pbi ++write 0x2320000,0x20000000 ++.end ++ ++/* Errata for SATA controller */ ++#include <../lx2160asi/a010554.rcw> ++ ++/* Errata for rev 1 PCIe controller */ ++#include <../lx2160asi/a011270.rcw> ++ ++/* Errata a050234 - fix elastic buffer threshold in rev 1 */ ++#include <../lx2160asi/a050234.rcw> ++ ++/* LX2 rev 2 PCIe Errata A-009531 and A-008851*/ ++#include <../lx2160asi/a009531_a008851.rcw> +diff --git a/lx2160acex7/configs/lx2160a_sdboot.rcwi b/lx2160acex7/configs/lx2160a_sdboot.rcwi +index d537ea5..9086ffc 100644 +--- a/lx2160acex7/configs/lx2160a_sdboot.rcwi ++++ b/lx2160acex7/configs/lx2160a_sdboot.rcwi +@@ -9,12 +9,6 @@ blockcopy 0x08,0x00100000,0x1800a000,0x00020000 + /* Boot Location Pointer */ + #include <../lx2160asi/bootlocptr_sd.rcw> + +-/* Errata for SATA controller */ +-#include <../lx2160asi/a010554.rcw> +- +-/* Errata for PCIe controller */ +-#include <../lx2160asi/a011270.rcw> +- + /* common PBI commands */ + #include <../lx2160asi/common.rcw> + +diff --git a/lx2160acex7/configs/lx2160a_xspiboot.rcwi b/lx2160acex7/configs/lx2160a_xspiboot.rcwi +index 28310c9..fa092c9 100644 +--- a/lx2160acex7/configs/lx2160a_xspiboot.rcwi ++++ b/lx2160acex7/configs/lx2160a_xspiboot.rcwi +@@ -4,12 +4,6 @@ + /* Boot Location Pointer */ + #include <../lx2160asi/bootlocptr_nor.rcw> + +-/* Errata for SATA controller */ +-#include <../lx2160asi/a010554.rcw> +- +-/* Errata for PCIe controller */ +-#include <../lx2160asi/a011270.rcw> +- + /* common PBI commands */ + #include <../lx2160asi/common.rcw> + +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0008-lx2160a-add-generic-bootloc-section.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0008-lx2160a-add-generic-bootloc-section.patch new file mode 100644 index 00000000..820f7b21 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0008-lx2160a-add-generic-bootloc-section.patch @@ -0,0 +1,113 @@ +From f7f0ad5e568862f7dc70fbd0f790845ee576734d Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Tue, 24 Mar 2020 03:42:14 +0200 +Subject: [PATCH 8/8] lx2160a: add generic bootloc section + +The generic bootloc section does conditional blockcopy from SD/eMMC and +SPI with some predefined addresses. +Later on if ATF is used; those addresses are modified with ATF's +create_pbl.c + +With this method a single boot image is unified for all the 3 different +boot methods. + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + lx2160acex7/configs/lx2160a_defaults.rcwi | 12 +++++ + lx2160asi/bootlocptr.rcw | 62 +++++++++++++++++++++++ + 2 files changed, 74 insertions(+) + create mode 100644 lx2160asi/bootlocptr.rcw + +diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi +index 7af1f5b..7997d49 100644 +--- a/lx2160acex7/configs/lx2160a_defaults.rcwi ++++ b/lx2160acex7/configs/lx2160a_defaults.rcwi +@@ -35,3 +35,15 @@ write 0x2320000,0x20000000 + + /* LX2 rev 2 PCIe Errata A-009531 and A-008851*/ + #include <../lx2160asi/a009531_a008851.rcw> ++ ++/* Unified boot location copy */ ++#include <../lx2160asi/bootlocptr.rcw> ++ ++/* Errata to write on scratch reg for validation */ ++#include <../lx2160asi/scratchrw1.rcw> ++ ++/* common PBI commands */ ++#include <../lx2160asi/common.rcw> ++ ++/* Modify FlexSPI Clock Divisor value - for now keep it fixed value but using loadc/jumpc/jump it can be calculated on the fly */ ++#include <../lx2160asi/flexspi_divisor_28.rcw> +diff --git a/lx2160asi/bootlocptr.rcw b/lx2160asi/bootlocptr.rcw +new file mode 100644 +index 0000000..645182f +--- /dev/null ++++ b/lx2160asi/bootlocptr.rcw +@@ -0,0 +1,62 @@ ++/* ++ * Generic code for auto booting. ++ * For each section blockcopy followed by write to bootlocl then bootloch must ++ * be followed in each section since when using ATF with create_pbl script in ++ * auto mode; it counts on the sequence of to be in that order. ++ */ ++ ++/* Boot from SD - copy SPL Uboot to Ocram */ ++.pbi ++/* Load condition PORSR1 and mask RCW_SRC */ ++loadc 0x01e00000,0x07800000 ++ ++/* If it is 0x8 << 23 then skip the following jump command */ ++jumpc 0x00000014,0x04000000 ++ ++/* Jump all the below instructions */ ++jump 0x28 /* All instruction below including the jump are 40 bytes */ ++ ++/* blockcopy must be followed by two writes to bootlocl and bootloch */ ++blockcopy 0x08,0x00100000,0x1800a000,0x00020000 ++write 0x01e00400,0x1800a000 ++write 0x01e00404,0x00000000 ++.end ++ ++/* Boot from eMMC - copy SPL Uboot to Ocram */ ++.pbi ++/* Load condition PORSR1 and mask RCW_SRC */ ++loadc 0x01e00000,0x07800000 ++ ++/* If it is 0x9 << 23 then skip the following jump command */ ++jumpc 0x00000014,0x04800000 ++ ++/* Jump all the below instructions */ ++jump 0x28 /* All instruction below including the jump are 40 bytes */ ++ ++/* blockcopy must be followed by two writes to bootlocl and bootloch */ ++blockcopy 0x09,0x00100000,0x1800a000,0x00020000 ++write 0x01e00400,0x1800a000 ++write 0x01e00404,0x00000000 ++.end ++ ++/* XSPI boot Location Pointer */ ++/* ++ * Set the boot location pointer to the NOR flash boot area. ++ */ ++ ++.pbi ++/* Load condition PORSR1 and mask RCW_SRC */ ++loadc 0x01e00000,0x07800000 ++ ++/* If it is 0xf << 23 then skip the following jump command */ ++jumpc 0x00000014,0x07800000 ++ ++/* Jump all the below instructions */ ++jump 0x28 /* All instruction below including the jump are 0x190 bytes */ ++ ++/* blockcopy must be followed by two writes to bootlocl and bootloch */ ++blockcopy 0x0f,0x00100000,0x1800a000,0x00020000 ++write 0x01e00400,0x20100000 ++write 0x01e00404,0x00000000 ++.end ++ +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0009-lx2160acex7-remove-all-predefined-RCW-files.patch b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0009-lx2160acex7-remove-all-predefined-RCW-files.patch new file mode 100644 index 00000000..20d77e6f --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw-lx2160acex7/0009-lx2160acex7-remove-all-predefined-RCW-files.patch @@ -0,0 +1,301 @@ +From 151f650f383fc5ddd9c405cf96bc189c2eaf13bd Mon Sep 17 00:00:00 2001 +From: Rabeeh Khoury <rabeeh@solid-run.com> +Date: Tue, 24 Mar 2020 03:51:28 +0200 +Subject: [PATCH 9/9] lx2160acex7: remove all predefined RCW files + +Remove all predefined RCW files and use on-the-fly created RCW from +external script. +For instance when using lx2160a_build repo; the runme.sh file creates +lx2160acex7/RCW/template.rcw file the gets compiled. +The creation is done using a simple bash script - + +cd $ROOTDIR/build/rcw/lx2160acex7 +mkdir -p RCW +echo "#include <configs/lx2160a_defaults.rcwi>" > RCW/template.rcw +echo "#include <configs/lx2160a_${SPEED}.rcwi>" >> RCW/template.rcw +echo "#include <configs/lx2160a_${SERDES}.rcwi>" >> RCW/template.rcw +make clean +make -j${PARALLEL} + +Upstream-Status: Inappropriate [Solid-Run BSP] + +Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> +--- + lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig | 61 ------------------- + .../rcw_1900_600_2600_17_4_2.rcw | 4 -- + .../rcw_1900_600_2600_17_4_2_sd.rcw | 4 -- + .../rcw_2000_700_2400_13_5_2_sd.rcw | 4 -- + .../rcw_2000_700_2400_20_5_2_sd.rcw | 4 -- + .../rcw_2000_700_2400_8_5_2_sd.rcw | 4 -- + .../rcw_2000_700_2600_8_5_2_sd.rcw | 4 -- + .../rcw_2000_700_2900_17_4_2_sd.rcw | 4 -- + .../rcw_2000_700_2900_8_5_2_sd.rcw | 4 -- + .../rcw_2000_700_3200_17_4_2_sd.rcw | 4 -- + .../rcw_2000_700_3200_20_5_2_sd.rcw | 4 -- + .../rcw_2000_700_3200_8_5_0_sd.rcw | 4 -- + .../rcw_2000_700_3200_8_5_2_sd.rcw | 4 -- + .../rcw_2000_700_3200_8_5_2_xspi.rcw | 4 -- + .../rcw_2400_700_3200_8_5_2_sd.rcw | 4 -- + .../rcw_2500_700_3200_8_5_2_sd.rcw | 4 -- + .../rcw_2600_700_3200_8_5_2_sd.rcw | 4 -- + .../XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw | 4 -- + 18 files changed, 129 deletions(-) + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw + delete mode 100644 lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw + +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig +deleted file mode 100644 +index cdb6446..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw.orig ++++ /dev/null +@@ -1,61 +0,0 @@ +-/* +- * SerDes Protocol 1 - 19 +- * SerDes Protocol 2 - 5 +- * SerDes Protocol 3 - 2 +- * +- * Frequencies: +- * Core -- 1900 MHz +- * Platform -- 600 MHz +- * DDR -- 2600 MT/s +- */ +- +-#include <../lx2160asi/lx2160a.rcwi> +- +-SYS_PLL_RAT=12 +-MEM_PLL_CFG=3 +-MEM_PLL_RAT=26 +-MEM2_PLL_CFG=3 +-MEM2_PLL_RAT=26 +-CGA_PLL1_RAT=19 +-CGA_PLL2_RAT=19 +-CGB_PLL1_RAT=19 +-CGB_PLL2_RAT=9 +-C5_PLL_SEL=0 +-C6_PLL_SEL=0 +-C7_PLL_SEL=0 +-C8_PLL_SEL=0 +-HWA_CGA_M1_CLK_SEL=1 +-HWA_CGB_M1_CLK_SEL=7 +-BOOT_LOC=26 +-SYSCLK_FREQ=600 +-IIC2_PMUX=6 +-IIC3_PMUX=2 +-IIC4_PMUX=2 +-USB3_CLK_FSEL=39 +-SRDS_PRTCL_S1=19 +-SRDS_PRTCL_S2=5 +-SRDS_PRTCL_S3=2 +-SRDS_PLL_REF_CLK_SEL_S1=2 +-SRDS_DIV_PEX_S1=1 +-SRDS_DIV_PEX_S2=3 +-SRDS_DIV_PEX_S3=1 +- +-/* Errata to write on scratch reg for validation */ +-#include <../lx2160asi/scratchrw1.rcw> +- +-/* Copy SPL Uboot to Ocram */ +-.pbi +-blockcopy 0x08,0x00100000,0x1800a000,0x00020000 +-.end +- +-/* Boot Location Pointer */ +-#include <../lx2160asi/bootlocptr_sd.rcw> +- +-/* Errata for SATA controller */ +-#include <../lx2160asi/a010554.rcw> +- +-/* Modify FlexSPI Clock Divisor value */ +-#include <../lx2160asi/flexspi_divisor_24.rcw> +- +-/* common PBI commands */ +-#include <../lx2160asi/common.rcw> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw +deleted file mode 100644 +index 13ab0b9..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_1900_600_2600.rcwi> +-#include <configs/lx2160a_17_4_2.rcwi> +-#include <configs/lx2160a_xspiboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw +deleted file mode 100644 +index 14fae8c..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_1900_600_2600_17_4_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_1900_600_2600.rcwi> +-#include <configs/lx2160a_17_4_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw +deleted file mode 100644 +index 2dae5a2..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_13_5_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2000_700_2400.rcwi> +-#include <configs/lx2160a_13_5_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw +deleted file mode 100644 +index 5335072..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_20_5_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2000_700_2400.rcwi> +-#include <configs/lx2160a_20_5_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw +deleted file mode 100644 +index e2a5bd3..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2400_8_5_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2000_700_2400.rcwi> +-#include <configs/lx2160a_8_5_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw +deleted file mode 100644 +index a330bfe..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2600_8_5_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2000_700_2600.rcwi> +-#include <configs/lx2160a_8_5_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw +deleted file mode 100644 +index 8535dbd..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_17_4_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2000_700_2900.rcwi> +-#include <configs/lx2160a_17_4_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw +deleted file mode 100644 +index 698be01..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_8_5_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2000_700_2900.rcwi> +-#include <configs/lx2160a_8_5_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw +deleted file mode 100644 +index 780d8c3..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_17_4_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2000_700_3200.rcwi> +-#include <configs/lx2160a_17_4_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw +deleted file mode 100644 +index eb9d240..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_20_5_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2000_700_3200.rcwi> +-#include <configs/lx2160a_20_5_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw +deleted file mode 100644 +index ceb53a3..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_0_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2000_700_3200.rcwi> +-#include <configs/lx2160a_8_5_0.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw +deleted file mode 100644 +index a220e98..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2000_700_3200.rcwi> +-#include <configs/lx2160a_8_5_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw +deleted file mode 100644 +index 1eabd7d..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_3200_8_5_2_xspi.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2000_700_3200.rcwi> +-#include <configs/lx2160a_8_5_2.rcwi> +-#include <configs/lx2160a_xspiboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw +deleted file mode 100644 +index 2ac59b1..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2400_700_3200_8_5_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2400_700_3200.rcwi> +-#include <configs/lx2160a_8_5_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw +deleted file mode 100644 +index e7c08df..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2500_700_3200_8_5_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2500_700_3200.rcwi> +-#include <configs/lx2160a_8_5_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw +deleted file mode 100644 +index 1e7a8f7..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_2600_700_3200_8_5_2_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_2600_700_3200.rcwi> +-#include <configs/lx2160a_8_5_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +diff --git a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw b/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw +deleted file mode 100644 +index 86f12f8..0000000 +--- a/lx2160acex7/XGGFF_PP_HHHH_RR_19_5_2/rcw_test_sd.rcw ++++ /dev/null +@@ -1,4 +0,0 @@ +-#include <configs/lx2160a_defaults.rcwi> +-#include <configs/lx2160a_test.rcwi> +-#include <configs/lx2160a_17_4_2.rcwi> +-#include <configs/lx2160a_sdboot.rcwi> +-- +2.17.1 + diff --git a/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw_git.bbappend b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw_git.bbappend new file mode 100644 index 00000000..4384c042 --- /dev/null +++ b/bsp/meta-freescale-3rdparty/recipes-bsp/rcw/rcw_git.bbappend @@ -0,0 +1,29 @@ +FILESEXTRAPATHS_append_lx2160acex7 := "${THISDIR}/${PN}-lx2160acex7:" + +SRC_URI_append_lx2160acex7 = "\ + file://0001-lx2160acex7-misc-RCW-files.patch \ + file://0002-Set-io-pads-as-GPIO.patch \ + file://0003-S2-enable-gen3-xspi-increase-divisor-to-28.patch \ + file://0004-refactor-a009531-a008851-and-a011270.patch \ + file://0006-lx2160a-add-SVR-check-for-a050234-to-apply-only-on-r.patch \ + file://0007-lx2160acex7-pcie-workarounds-and-fan-full-speed.patch \ + file://0008-lx2160a-add-generic-bootloc-section.patch \ + file://0009-lx2160acex7-remove-all-predefined-RCW-files.patch \ +" + +do_configure_prepend_lx2160acex7 () { + for BT in ${BOARD_TARGETS} + do + mkdir -p ${S}/${BOARD_TARGETS}/${SERDES} + cat <<EOF >${S}/${BOARD_TARGETS}/README +The RCW directories for lx2160acex7 are created based on existing SERDES +configuration. Currently created automatically - later maybe by building +cross product of serdes & ddr speeds in a final commit. +EOF + cat <<EOF >${S}/${BOARD_TARGETS}/${SERDES}/${SPEED}.rcw +#include <configs/lx2160a_defaults.rcwi> +#include <configs/lx2160a_${SPEED}.rcwi> +#include <configs/lx2160a_${SERDES}.rcwi> +EOF + done +} |