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Diffstat (limited to 'bsp/meta-rcar/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0217-arm64-dts-renesas-r8a779-7-8-0-add-CMT-support.patch')
-rw-r--r--bsp/meta-rcar/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0217-arm64-dts-renesas-r8a779-7-8-0-add-CMT-support.patch185
1 files changed, 185 insertions, 0 deletions
diff --git a/bsp/meta-rcar/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0217-arm64-dts-renesas-r8a779-7-8-0-add-CMT-support.patch b/bsp/meta-rcar/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0217-arm64-dts-renesas-r8a779-7-8-0-add-CMT-support.patch
new file mode 100644
index 00000000..b5bdf788
--- /dev/null
+++ b/bsp/meta-rcar/meta-rcar-gen3-adas/recipes-kernel/linux/linux-renesas/0217-arm64-dts-renesas-r8a779-7-8-0-add-CMT-support.patch
@@ -0,0 +1,185 @@
+From a0eacde243624af6648986c8f38caea744a4e5f8 Mon Sep 17 00:00:00 2001
+From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Date: Fri, 7 Sep 2018 21:58:41 +0300
+Subject: [PATCH 037/211] arm64: dts: renesas: r8a779{7|8}0: add CMT support
+
+Describe CMTs in the R8A779{7|8}0 device trees.
+
+Based on the original (and large) patches by Vladimir Barinov.
+
+Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
+(cherry picked from commit a215af751dc5d24b4e3a8fc9976ae95737843934)
+Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
+---
+ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 70 +++++++++++++++++++++++++++++++
+ arch/arm64/boot/dts/renesas/r8a77980.dtsi | 70 +++++++++++++++++++++++++++++++
+ 2 files changed, 140 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+index f4b0270..934a15f 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+@@ -209,6 +209,76 @@
+ reg = <0 0xe6060000 0 0x504>;
+ };
+
++ cmt0: timer@e60f0000 {
++ compatible = "renesas,r8a77970-cmt0",
++ "renesas,rcar-gen3-cmt0";
++ reg = <0 0xe60f0000 0 0x1004>;
++ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cpg CPG_MOD 303>;
++ clock-names = "fck";
++ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++ resets = <&cpg 303>;
++ status = "disabled";
++ };
++
++ cmt1: timer@e6130000 {
++ compatible = "renesas,r8a77970-cmt1",
++ "renesas,rcar-gen3-cmt1";
++ reg = <0 0xe6130000 0 0x1004>;
++ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cpg CPG_MOD 302>;
++ clock-names = "fck";
++ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++ resets = <&cpg 302>;
++ status = "disabled";
++ };
++
++ cmt2: timer@e6140000 {
++ compatible = "renesas,r8a77970-cmt1",
++ "renesas,rcar-gen3-cmt1";
++ reg = <0 0xe6140000 0 0x1004>;
++ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cpg CPG_MOD 301>;
++ clock-names = "fck";
++ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++ resets = <&cpg 301>;
++ status = "disabled";
++ };
++
++ cmt3: timer@e6148000 {
++ compatible = "renesas,r8a77970-cmt1",
++ "renesas,rcar-gen3-cmt1";
++ reg = <0 0xe6148000 0 0x1004>;
++ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cpg CPG_MOD 300>;
++ clock-names = "fck";
++ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
++ resets = <&cpg 300>;
++ status = "disabled";
++ };
++
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a77970-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+index 7dd4ad2..cb135f6 100644
+--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
++++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+@@ -239,6 +239,76 @@
+ reg = <0 0xe6060000 0 0x50c>;
+ };
+
++ cmt0: timer@e60f0000 {
++ compatible = "renesas,r8a77980-cmt0",
++ "renesas,rcar-gen3-cmt0";
++ reg = <0 0xe60f0000 0 0x1004>;
++ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cpg CPG_MOD 303>;
++ clock-names = "fck";
++ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
++ resets = <&cpg 303>;
++ status = "disabled";
++ };
++
++ cmt1: timer@e6130000 {
++ compatible = "renesas,r8a77980-cmt1",
++ "renesas,rcar-gen3-cmt1";
++ reg = <0 0xe6130000 0 0x1004>;
++ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cpg CPG_MOD 302>;
++ clock-names = "fck";
++ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
++ resets = <&cpg 302>;
++ status = "disabled";
++ };
++
++ cmt2: timer@e6140000 {
++ compatible = "renesas,r8a77980-cmt1",
++ "renesas,rcar-gen3-cmt1";
++ reg = <0 0xe6140000 0 0x1004>;
++ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cpg CPG_MOD 301>;
++ clock-names = "fck";
++ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
++ resets = <&cpg 301>;
++ status = "disabled";
++ };
++
++ cmt3: timer@e6148000 {
++ compatible = "renesas,r8a77980-cmt1",
++ "renesas,rcar-gen3-cmt1";
++ reg = <0 0xe6148000 0 0x1004>;
++ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cpg CPG_MOD 300>;
++ clock-names = "fck";
++ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
++ resets = <&cpg 300>;
++ status = "disabled";
++ };
++
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a77980-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+--
+2.7.4
+