diff options
Diffstat (limited to 'meta-agl-devel/meta-agl-jailhouse/recipes-extended/jailhouse/files')
5 files changed, 1183 insertions, 0 deletions
diff --git a/meta-agl-devel/meta-agl-jailhouse/recipes-extended/jailhouse/files/agl-apic-demo.c b/meta-agl-devel/meta-agl-jailhouse/recipes-extended/jailhouse/files/agl-apic-demo.c new file mode 100644 index 00000000..f49cd3a4 --- /dev/null +++ b/meta-agl-devel/meta-agl-jailhouse/recipes-extended/jailhouse/files/agl-apic-demo.c @@ -0,0 +1,78 @@ +/* + * Jailhouse, a Linux-based partitioning hypervisor + * + * Minimal configuration for demo inmates, 1 CPU, 1 MB RAM, 1 serial port + * + * Copyright (c) Siemens AG, 2013 + * + * Authors: + * Jan Kiszka <jan.kiszka@siemens.com> + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + */ + +#include <jailhouse/types.h> +#include <jailhouse/cell-config.h> + +struct { + struct jailhouse_cell_desc cell; + __u64 cpus[1]; + struct jailhouse_memory mem_regions[2]; + struct jailhouse_cache cache_regions[1]; + struct jailhouse_pio pio_regions[1];//[2]->[1] stop @0x3f8 +} __attribute__((packed)) config = { + .cell = { + .signature = JAILHOUSE_CELL_DESC_SIGNATURE, + .revision = JAILHOUSE_CONFIG_REVISION, + .name = "agl-apic-demo", + .flags = JAILHOUSE_CELL_VIRTUAL_CONSOLE_PERMITTED, + + .cpu_set_size = sizeof(config.cpus), + .num_memory_regions = ARRAY_SIZE(config.mem_regions), + .num_cache_regions = ARRAY_SIZE(config.cache_regions), + .num_irqchips = 0, + .num_pio_regions = ARRAY_SIZE(config.pio_regions), + .num_pci_devices = 0, + + .console = { + .type = JAILHOUSE_CON_TYPE_8250, + .flags = JAILHOUSE_CON_ACCESS_PIO, + .address = 0x2f8, /* ######## ttyS0 is host -> ttyS1 */ + }, + }, + + .cpus = { + 0x8, + }, + + .mem_regions = { + /* RAM */ { /* JH_memory: 0x22600000-0x271fffff */ + .phys_start = 0x26e00000 , /* agl-linux-x86: 0x22600000-0x26e00000 */ + .virt_start = 0, /* agl-ivshmem: 0x26e00000- (end of ivshmem cell) */ + .size = 0x00100000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE, + }, + /* communication region */ { + .virt_start = 0x00100000, + .size = 0x00001000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_COMM_REGION, + }, + }, + + .cache_regions = { + { + .start = 0, + .size = 2, + .type = JAILHOUSE_CACHE_L3, + }, + }, + + .pio_regions = { + PIO_RANGE(0x2f8, 8), /* serial 2 */ +// PIO_RANGE(0x3f8, 8), /* serial 1 */ + PIO_RANGE(0xe010, 8), /* OXPCIe952 serial */ + }, +}; diff --git a/meta-agl-devel/meta-agl-jailhouse/recipes-extended/jailhouse/files/agl-ivshmem-demo.c b/meta-agl-devel/meta-agl-jailhouse/recipes-extended/jailhouse/files/agl-ivshmem-demo.c new file mode 100644 index 00000000..79feb6c5 --- /dev/null +++ b/meta-agl-devel/meta-agl-jailhouse/recipes-extended/jailhouse/files/agl-ivshmem-demo.c @@ -0,0 +1,119 @@ +/* + * Jailhouse, a Linux-based partitioning hypervisor + * + * Minimal configuration for ivshmem inmate demo: + * 1 CPU, 1MB RAM, serial ports, 4K shmem + * + * Copyright (c) Siemens AG, 2013, 2014 + * + * Authors: + * Henning Schild <henning.schild@siemens.com> + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + */ + +#include <jailhouse/types.h> +#include <jailhouse/cell-config.h> + +struct { + struct jailhouse_cell_desc cell; + __u64 cpus[1]; + struct jailhouse_memory mem_regions[7]; + struct jailhouse_pio pio_regions[1]; + struct jailhouse_pci_device pci_devices[1]; + struct jailhouse_pci_capability pci_caps[0]; +} __attribute__((packed)) config = { + .cell = { + .signature = JAILHOUSE_CELL_DESC_SIGNATURE, + .revision = JAILHOUSE_CONFIG_REVISION, + .name = "ivshmem-demo", + .flags = JAILHOUSE_CELL_PASSIVE_COMMREG | + JAILHOUSE_CELL_VIRTUAL_CONSOLE_PERMITTED, + + .cpu_set_size = sizeof(config.cpus), + .num_memory_regions = ARRAY_SIZE(config.mem_regions), + .num_irqchips = 0, + .num_pio_regions = ARRAY_SIZE(config.pio_regions), + .num_pci_devices = ARRAY_SIZE(config.pci_devices), + .num_pci_caps = ARRAY_SIZE(config.pci_caps), + + .console = { + .type = JAILHOUSE_CON_TYPE_8250, + .flags = JAILHOUSE_CON_ACCESS_PIO, + .address = 0x2f8,/* ######## ttyS0 is host -> ttyS1 */ + }, + }, + + .cpus = { + 0b0010, + }, + + .mem_regions = { + /* IVSHMEM shared memory regions (demo) */ + { + .phys_start = 0x271f0000, + .virt_start = 0x271f0000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0x271f1000, + .virt_start = 0x271f1000, + .size = 0x9000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0x271fa000, + .virt_start = 0x271fa000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0x271fc000, + .virt_start = 0x271fc000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0x271fe000, + .virt_start = 0x271fe000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + /* RAM */ { + .phys_start = 0x27200000,/* to 0x27300000 */ + .virt_start = 0, + .size = 0x00100000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE, + }, + /* communication region */ { + .virt_start = 0x00100000, + .size = 0x00001000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_COMM_REGION, + }, + }, + + .pio_regions = { + PIO_RANGE(0x2f8, 8), /* serial 2 */ +// PIO_RANGE(0x3f8, 8), /* serial 1 */ + }, + + .pci_devices = { + { + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .domain = 0x0000, + .bdf = 0x0e << 3, + .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_MSIX, + .num_msix_vectors = 16, + .shmem_regions_start = 0, + .shmem_dev_id = 1, + .shmem_peers = 3, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED, + }, + }, +}; diff --git a/meta-agl-devel/meta-agl-jailhouse/recipes-extended/jailhouse/files/agl-linux-x86-demo.c b/meta-agl-devel/meta-agl-jailhouse/recipes-extended/jailhouse/files/agl-linux-x86-demo.c new file mode 100644 index 00000000..06085df5 --- /dev/null +++ b/meta-agl-devel/meta-agl-jailhouse/recipes-extended/jailhouse/files/agl-linux-x86-demo.c @@ -0,0 +1,246 @@ +/* + * Jailhouse, a Linux-based partitioning hypervisor + * + * Configuration for Linux inmate, 1 CPU, 74 MB RAM, ~1MB shmem, serial ports + * + * Copyright (c) Siemens AG, 2013-2015 + * + * Authors: + * Jan Kiszka <jan.kiszka@siemens.com> + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + */ + +#include <jailhouse/types.h> +#include <jailhouse/cell-config.h> + +struct { + struct jailhouse_cell_desc cell; + __u64 cpus[1]; + struct jailhouse_memory mem_regions[20]; + struct jailhouse_cache cache_regions[1]; + struct jailhouse_irqchip irqchips[1]; + struct jailhouse_pio pio_regions[1]; + struct jailhouse_pci_device pci_devices[4]; + struct jailhouse_pci_capability pci_caps[6]; +} __attribute__((packed)) config = { + .cell = { + .signature = JAILHOUSE_CELL_DESC_SIGNATURE, + .revision = JAILHOUSE_CONFIG_REVISION, + .name = "linux-x86-demo", + .flags = JAILHOUSE_CELL_PASSIVE_COMMREG | + JAILHOUSE_CELL_VIRTUAL_CONSOLE_PERMITTED, + + .cpu_set_size = sizeof(config.cpus), + .num_memory_regions = ARRAY_SIZE(config.mem_regions), + .num_cache_regions = ARRAY_SIZE(config.cache_regions), + .num_irqchips = ARRAY_SIZE(config.irqchips), + .num_pio_regions = ARRAY_SIZE(config.pio_regions), + .num_pci_devices = ARRAY_SIZE(config.pci_devices), + .num_pci_caps = ARRAY_SIZE(config.pci_caps), + }, + + .cpus = { + 0b1100, + }, + + .mem_regions = { + /* IVSHMEM shared memory region (virtio-blk front) */ + { + .phys_start = 0x27000000, /* to 0x27001000 */ + .virt_start = 0x27000000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0x27001000,/* to 0x270e0000 */ + .virt_start = 0x27001000, + .size = 0xdf000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_ROOTSHARED, + }, + { 0 }, + { 0 }, + /* IVSHMEM shared memory region (virtio-con front) */ + { + .phys_start = 0x270e0000,/* to 0x270e1000 */ + .virt_start = 0x270e0000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0x270e1000,/*to 0x270f0000 */ + .virt_start = 0x270e1000, + .size = 0xf000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_ROOTSHARED, + }, + { 0 }, + { 0 }, + /* IVSHMEM shared memory regions (demo) */ + { + .phys_start = 0x270f0000,/*to 0x270f1000 */ + .virt_start = 0x270f0000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0x270f1000,/*to 0x270fa000 */ + .virt_start = 0x270f1000, + .size = 0x9000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0x270fa000,/* to 0x270fc000 */ + .virt_start = 0x270fa000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0x270fc000,/* to 0x270fe000*/ + .virt_start = 0x270fc000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0x270fe000,/* to 0x27100000 */ + .virt_start = 0x270fe000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_ROOTSHARED, + }, + /* IVSHMEM shared memory regions (networking) */ + JAILHOUSE_SHMEM_NET_REGIONS(0x27100000, 1), + /* low RAM */ { + .phys_start = 0x22600000,/* to 0x22700000*/ + .virt_start = 0, + .size = 0x00100000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA | + JAILHOUSE_MEM_LOADABLE, + }, + /* communication region */ { + /*.phys_start = ? */ + .virt_start = 0x00100000, + .size = 0x00001000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_COMM_REGION, + }, + /* high RAM */ { + .phys_start = 0x22700000,/*to 0x26e00000 */ + .virt_start = 0x00200000, + .size = 0x4700000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA | + JAILHOUSE_MEM_LOADABLE, + }, + }, + + .cache_regions = { + { + .start = 0, + .size = 2, + .type = JAILHOUSE_CACHE_L3, + }, + }, + + .irqchips = { + /* IOAPIC */ { + .address = 0xfec00000, + .id = 0xff00, + .pin_bitmap = { + (1 << 3) | (1 << 4), + }, + }, + }, + + .pio_regions = { + PIO_RANGE(0x2f8, 8), /* serial 2 */ +// PIO_RANGE(0x3f8, 8), /* serial 1 */ + PIO_RANGE(0xe010, 8), /* OXPCIe952 serial1 */ + }, + + .pci_devices = { + { + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .domain = 0x0, + .bdf = 0x0c << 3, + .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_MSIX, + .num_msix_vectors = 2, + .shmem_regions_start = 0, + .shmem_dev_id = 1, + .shmem_peers = 2, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_VIRTIO_FRONT + + VIRTIO_DEV_BLOCK, + }, + { + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .domain = 0x0, + .bdf = 0x0d << 3, + .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_MSIX, + .num_msix_vectors = 3, + .shmem_regions_start = 4, + .shmem_dev_id = 1, + .shmem_peers = 2, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_VIRTIO_FRONT + + VIRTIO_DEV_CONSOLE, + }, + { + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .domain = 0x0, + .bdf = 0x0e << 3, + .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_MSIX, + .num_msix_vectors = 16, + .shmem_regions_start = 8, + .shmem_dev_id = 2, + .shmem_peers = 3, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED, + }, + { + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .domain = 0x0, + .bdf = 0x0f << 3, + .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_MSIX, + .num_msix_vectors = 2, + .shmem_regions_start = 13, + .shmem_dev_id = 1, + .shmem_peers = 2, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH, + }, + }, + + .pci_caps = { + { + .id = PCI_CAP_ID_MSI, + .start = 0xd0, + .len = 14, + .flags = JAILHOUSE_PCICAPS_WRITE, + }, + { + .id = PCI_CAP_ID_EXP, + .start = 0xe0, + .len = 20, + .flags = JAILHOUSE_PCICAPS_WRITE, + }, + { + .id = PCI_CAP_ID_MSIX, + .start = 0xa0, + .len = 12, + .flags = JAILHOUSE_PCICAPS_WRITE, + }, + { + .id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP, + .start = 0x100, + .len = 4, + .flags = 0, + }, + { + .id = PCI_EXT_CAP_ID_DSN | JAILHOUSE_PCI_EXT_CAP, + .start = 0x140, + .len = 4, + .flags = 0, + }, + } +}; diff --git a/meta-agl-devel/meta-agl-jailhouse/recipes-extended/jailhouse/files/agl-pci-demo.c b/meta-agl-devel/meta-agl-jailhouse/recipes-extended/jailhouse/files/agl-pci-demo.c new file mode 100644 index 00000000..59d42323 --- /dev/null +++ b/meta-agl-devel/meta-agl-jailhouse/recipes-extended/jailhouse/files/agl-pci-demo.c @@ -0,0 +1,103 @@ +/* + * Jailhouse, a Linux-based partitioning hypervisor + * + * Minimal configuration for PCI demo inmate: + * 1 CPU, 1 MB RAM, serial ports, 1 Intel HDA PCI device + * + * Copyright (c) Siemens AG, 2014 + * + * Authors: + * Jan Kiszka <jan.kiszka@siemens.com> + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + */ + +#include <jailhouse/types.h> +#include <jailhouse/cell-config.h> + +struct { + struct jailhouse_cell_desc cell; + __u64 cpus[1]; + struct jailhouse_memory mem_regions[3]; + struct jailhouse_pio pio_regions[1]; /* ttyS0 is host -> ttyS1 */ + struct jailhouse_pci_device pci_devices[1]; + struct jailhouse_pci_capability pci_caps[1]; +} __attribute__((packed)) config = { + .cell = { + .signature = JAILHOUSE_CELL_DESC_SIGNATURE, + .revision = JAILHOUSE_CONFIG_REVISION, + .name = "agl-pci-demo", + .flags = JAILHOUSE_CELL_PASSIVE_COMMREG | + JAILHOUSE_CELL_VIRTUAL_CONSOLE_PERMITTED, + + .cpu_set_size = sizeof(config.cpus), + .num_memory_regions = ARRAY_SIZE(config.mem_regions), + .num_irqchips = 0, + .num_pio_regions = ARRAY_SIZE(config.pio_regions), + .num_pci_devices = ARRAY_SIZE(config.pci_devices), + .num_pci_caps = ARRAY_SIZE(config.pci_caps), + + + .console = { + .type = JAILHOUSE_CON_TYPE_8250, + .flags = JAILHOUSE_CON_ACCESS_PIO, + .address = 0x2f8, + }, + }, + + .cpus = { + 0x4, + }, + + .mem_regions = { + /* RAM */ { + .phys_start = 0x26f00000,/*to 0x27000000| apic-demo @0x26e00000-@0x26f00000 */ + .virt_start = 0, + .size = 0x00100000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE, + }, + /* communication region */ { + .virt_start = 0x00100000, + .size = 0x00001000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_COMM_REGION, + }, + /* HDA BAR0 */ { + .phys_start = 0xfebd4000, + .virt_start = 0xfebd4000, + .size = 0x00004000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, + }, + }, + + + .pio_regions = { + PIO_RANGE(0x2f8, 8), /* serial 2 */ + //PIO_RANGE(0x3f8, 8), /* serial 1 */ + PIO_RANGE(0xe010, 8), /* OXPCIe952 serial2 */ + }, + + + .pci_devices = { + { /* Intel HDA @00:1b.0 */ + .type = JAILHOUSE_PCI_TYPE_DEVICE, + .domain = 0x0000, + .bdf = 0x00d8, + .caps_start = 0, + .num_caps = 1, + .num_msi_vectors = 1, + .msi_64bits = 1, + }, + }, + + .pci_caps = { + { /* Intel HDA @00:1b.0 */ + .id = PCI_CAP_ID_MSI, + .start = 0x60, + .len = 14, + .flags = JAILHOUSE_PCICAPS_WRITE, + }, + }, +}; diff --git a/meta-agl-devel/meta-agl-jailhouse/recipes-extended/jailhouse/files/qemu-agl.c b/meta-agl-devel/meta-agl-jailhouse/recipes-extended/jailhouse/files/qemu-agl.c new file mode 100644 index 00000000..cf193c08 --- /dev/null +++ b/meta-agl-devel/meta-agl-jailhouse/recipes-extended/jailhouse/files/qemu-agl.c @@ -0,0 +1,637 @@ +/* + * Jailhouse, a Linux-based partitioning hypervisor + * + * Copyright (c) Siemens AG, 2014-2017 + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + * + * Alternatively, you can use or redistribute this file under the following + * BSD license: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * Configuration for QEMU Standard PC (Q35 + ICH9, 2009) + * created with '/usr/libexec/jailhouse/jailhouse config create -c ttyS1 qemu-agl.c' + * + * NOTE: This config expects the following to be appended to your kernel cmdline + * "memmap=0x5200000$0x22000000" + */ + +#include <jailhouse/types.h> +#include <jailhouse/cell-config.h> + +struct { + struct jailhouse_system header; + __u64 cpus[1]; + struct jailhouse_memory mem_regions[17]; + struct jailhouse_irqchip irqchips[1]; + struct jailhouse_pio pio_regions[14]; + struct jailhouse_pci_device pci_devices[13]; + struct jailhouse_pci_capability pci_caps[14]; +} __attribute__((packed)) config = { + .header = { + .signature = JAILHOUSE_SYSTEM_SIGNATURE, + .revision = JAILHOUSE_CONFIG_REVISION, + .flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE, + .hypervisor_memory = { + .phys_start = 0x22000000, + .size = 0x600000, + }, + .debug_console = { + .address = 0x2f8, + .type = JAILHOUSE_CON_TYPE_8250, + .flags = JAILHOUSE_CON_ACCESS_PIO | + JAILHOUSE_CON_REGDIST_1, + }, + .platform_info = { + .pci_mmconfig_base = 0xb0000000, + .pci_mmconfig_end_bus = 0xff, + .iommu_units = { + { + .type = JAILHOUSE_IOMMU_INTEL, + .base = 0xfed90000, + .size = 0x1000, + }, + }, + .x86 = { + .pm_timer_address = 0x608, + .vtd_interrupt_limit = 256, + }, + }, + .root_cell = { + .name = "RootCell", + .cpu_set_size = sizeof(config.cpus), + .num_memory_regions = ARRAY_SIZE(config.mem_regions), + .num_irqchips = ARRAY_SIZE(config.irqchips), + .num_pio_regions = ARRAY_SIZE(config.pio_regions), + .num_pci_devices = ARRAY_SIZE(config.pci_devices), + .num_pci_caps = ARRAY_SIZE(config.pci_caps), + }, + }, + + .cpus = { + 0x000000000000000f, + }, + + .mem_regions = { + /* MemRegion: 00000000-0009fbff : System RAM */ + { + .phys_start = 0x0, + .virt_start = 0x0, + .size = 0xa0000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA, + }, + /* MemRegion: 00100000-201fffff : System RAM */ + { + .phys_start = 0x100000, + .virt_start = 0x100000, + .size = 0x20100000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA, + }, + /* MemRegion: 20200000-21ffffff : Kernel */ + { + .phys_start = 0x20200000, + .virt_start = 0x20200000, + .size = 0x1e00000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA, + }, + /* MemRegion: 27200000-31ffffff : System RAM */ + { + .phys_start = 0x27200000, + .virt_start = 0x27200000, + .size = 0xae00000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA, + }, + /* MemRegion: 32000000-33ffffff : RAM buffer */ + { + .phys_start = 0x32000000, + .virt_start = 0x32000000, + .size = 0x2000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA, + }, + /* MemRegion: fe000000-fe7fffff : 0000:00:01.0 */ + { + .phys_start = 0xfe000000, + .virt_start = 0xfe000000, + .size = 0x800000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, + }, + /* MemRegion: fe800000-fe803fff : virtio-pci-modern */ + { + .phys_start = 0xfe800000, + .virt_start = 0xfe800000, + .size = 0x4000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, + }, + /* MemRegion: fe804000-fe807fff : virtio-pci-modern */ + { + .phys_start = 0xfe804000, + .virt_start = 0xfe804000, + .size = 0x4000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, + }, + /* MemRegion: fe808000-fe80bfff : virtio-pci-modern */ + { + .phys_start = 0xfe808000, + .virt_start = 0xfe808000, + .size = 0x4000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, + }, + /* MemRegion: fe80c000-fe80ffff : virtio-pci-modern */ + { + .phys_start = 0xfe80c000, + .virt_start = 0xfe80c000, + .size = 0x4000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, + }, + /* MemRegion: feb80000-febbffff : 0000:00:02.0 */ + { + .phys_start = 0xfeb80000, + .virt_start = 0xfeb80000, + .size = 0x40000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, + }, + /* MemRegion: febd0000-febd3fff : ICH HD audio */ + { + .phys_start = 0xfebd0000, + .virt_start = 0xfebd0000, + .size = 0x4000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, + }, + /* MemRegion: febd7000-febd7fff : ehci_hcd */ + { + .phys_start = 0xfebd7000, + .virt_start = 0xfebd7000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, + }, + /* MemRegion: febd8000-febd8fff : ahci */ + { + .phys_start = 0xfebd8000, + .virt_start = 0xfebd8000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, + }, + /* MemRegion: fed00000-fed003ff : PNP0103:00 */ + { + .phys_start = 0xfed00000, + .virt_start = 0xfed00000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, + }, + /* MemRegion: 000c0000-000dffff : ROMs */ + { + .phys_start = 0xc0000, + .virt_start = 0xc0000, + .size = 0x20000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, + }, + /* MemRegion: 22600000-271fffff : JAILHOUSE Inmate Memory */ + { + .phys_start = 0x22600000, + .virt_start = 0x22600000, + .size = 0x4c00000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, + }, + }, + + .irqchips = { + /* IOAPIC 0, GSI base 0 */ + { + .address = 0xfec00000, + .id = 0xff00, + .pin_bitmap = { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff + }, + }, + }, + + .pio_regions = { + /* Port I/O: 0000-001f : dma1 */ + /* PIO_RANGE(0x0, 0x20), */ + /* Port I/O: 0020-0021 : pic1 */ + /* PIO_RANGE(0x20, 0x2), */ + /* Port I/O: 0040-0043 : timer0 */ + PIO_RANGE(0x40, 0x4), + /* Port I/O: 0050-0053 : timer1 */ + /* PIO_RANGE(0x50, 0x4), */ + /* Port I/O: 0060-0060 : keyboard */ + PIO_RANGE(0x60, 0x1), + /* Port I/O: 0064-0064 : keyboard */ + PIO_RANGE(0x64, 0x1), + /* Port I/O: 0070-0077 : rtc0 */ + PIO_RANGE(0x70, 0x8), + /* Port I/O: 0080-008f : dma page reg */ + /* PIO_RANGE(0x80, 0x10), */ + /* Port I/O: 00a0-00a1 : pic2 */ + /* PIO_RANGE(0xa0, 0x2), */ + /* Port I/O: 00c0-00df : dma2 */ + /* PIO_RANGE(0xc0, 0x20), */ + /* Port I/O: 00f0-00ff : fpu */ + /* PIO_RANGE(0xf0, 0x10), */ + /* Port I/O: 02f8-02ff : serial */ + PIO_RANGE(0x2f8, 0x8), + /* Port I/O: 0378-037a : parport0 */ + /* PIO_RANGE(0x378, 0x3), */ + /* Port I/O: 03c0-03df : vga+ */ + PIO_RANGE(0x3c0, 0x20), + /* Port I/O: 03f8-03ff : serial */ + PIO_RANGE(0x3f8, 0x8), + /* Port I/O: 0510-051b : QEMU0002:00 */ + /* PIO_RANGE(0x510, 0xc), */ + /* Port I/O: 0600-0603 : ACPI PM1a_EVT_BLK */ + /* PIO_RANGE(0x600, 0x4), */ + /* Port I/O: 0604-0605 : ACPI PM1a_CNT_BLK */ + /* PIO_RANGE(0x604, 0x2), */ + /* Port I/O: 0608-060b : ACPI PM_TMR */ + /* PIO_RANGE(0x608, 0x4), */ + /* Port I/O: 0620-062f : ACPI GPE0_BLK */ + /* PIO_RANGE(0x620, 0x10), */ + /* Port I/O: 0700-073f : i801_smbus */ + /* PIO_RANGE(0x700, 0x40), */ + /* Port I/O: c000-c07f : 0000:00:04.0 */ + PIO_RANGE(0xc000, 0x80), + /* Port I/O: c0c0-c0df : 0000:00:02.0 */ + PIO_RANGE(0xc0c0, 0x20), + /* Port I/O: c0e0-c0ff : 0000:00:03.0 */ + PIO_RANGE(0xc0e0, 0x20), + /* Port I/O: c100-c11f : 0000:00:1d.0 */ + PIO_RANGE(0xc100, 0x20), + /* Port I/O: c120-c13f : 0000:00:1d.1 */ + PIO_RANGE(0xc120, 0x20), + /* Port I/O: c140-c15f : 0000:00:1d.2 */ + PIO_RANGE(0xc140, 0x20), + /* Port I/O: c160-c17f : 0000:00:1f.2 */ + PIO_RANGE(0xc160, 0x20), + }, + + .pci_devices = { + /* PCIDevice: 00:00.0 */ + { + .type = JAILHOUSE_PCI_TYPE_DEVICE, + .iommu = 0, + .domain = 0x0, + .bdf = 0x0, + .bar_mask = { + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, + }, + .caps_start = 0, + .num_caps = 0, + .num_msi_vectors = 0, + .msi_64bits = 0, + .msi_maskable = 0, + .num_msix_vectors = 0, + .msix_region_size = 0x0, + .msix_address = 0x0, + }, + /* PCIDevice: 00:01.0 */ + { + .type = JAILHOUSE_PCI_TYPE_DEVICE, + .iommu = 0, + .domain = 0x0, + .bdf = 0x8, + .bar_mask = { + 0xff800000, 0x00000000, 0xffffc000, + 0xffffffff, 0xfffff000, 0x00000000, + }, + .caps_start = 0, + .num_caps = 6, + .num_msi_vectors = 0, + .msi_64bits = 0, + .msi_maskable = 0, + .num_msix_vectors = 3, + .msix_region_size = 0x1000, + .msix_address = 0xfebd4000, + }, + /* PCIDevice: 00:02.0 */ + { + .type = JAILHOUSE_PCI_TYPE_DEVICE, + .iommu = 0, + .domain = 0x0, + .bdf = 0x10, + .bar_mask = { + 0xffffffe0, 0xfffff000, 0x00000000, + 0x00000000, 0xffffc000, 0xffffffff, + }, + .caps_start = 0, + .num_caps = 6, + .num_msi_vectors = 0, + .msi_64bits = 0, + .msi_maskable = 0, + .num_msix_vectors = 3, + .msix_region_size = 0x1000, + .msix_address = 0xfebd5000, + }, + /* PCIDevice: 00:03.0 */ + { + .type = JAILHOUSE_PCI_TYPE_DEVICE, + .iommu = 0, + .domain = 0x0, + .bdf = 0x18, + .bar_mask = { + 0xffffffe0, 0x00000000, 0x00000000, + 0x00000000, 0xffffc000, 0xffffffff, + }, + .caps_start = 6, + .num_caps = 5, + .num_msi_vectors = 0, + .msi_64bits = 0, + .msi_maskable = 0, + .num_msix_vectors = 0, + .msix_region_size = 0x0, + .msix_address = 0x0, + }, + /* PCIDevice: 00:04.0 */ + { + .type = JAILHOUSE_PCI_TYPE_DEVICE, + .iommu = 0, + .domain = 0x0, + .bdf = 0x20, + .bar_mask = { + 0xffffff80, 0xfffff000, 0x00000000, + 0x00000000, 0xffffc000, 0xffffffff, + }, + .caps_start = 0, + .num_caps = 6, + .num_msi_vectors = 0, + .msi_64bits = 0, + .msi_maskable = 0, + .num_msix_vectors = 2, + .msix_region_size = 0x1000, + .msix_address = 0xfebd6000, + }, + /* PCIDevice: 00:1b.0 */ + { + .type = JAILHOUSE_PCI_TYPE_DEVICE, + .iommu = 0, + .domain = 0x0, + .bdf = 0xd8, + .bar_mask = { + 0xffffc000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, + }, + .caps_start = 11, + .num_caps = 1, + .num_msi_vectors = 1, + .msi_64bits = 1, + .msi_maskable = 0, + .num_msix_vectors = 0, + .msix_region_size = 0x0, + .msix_address = 0x0, + }, + /* PCIDevice: 00:1d.0 */ + { + .type = JAILHOUSE_PCI_TYPE_DEVICE, + .iommu = 0, + .domain = 0x0, + .bdf = 0xe8, + .bar_mask = { + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0xffffffe0, 0x00000000, + }, + .caps_start = 0, + .num_caps = 0, + .num_msi_vectors = 0, + .msi_64bits = 0, + .msi_maskable = 0, + .num_msix_vectors = 0, + .msix_region_size = 0x0, + .msix_address = 0x0, + }, + /* PCIDevice: 00:1d.1 */ + { + .type = JAILHOUSE_PCI_TYPE_DEVICE, + .iommu = 0, + .domain = 0x0, + .bdf = 0xe9, + .bar_mask = { + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0xffffffe0, 0x00000000, + }, + .caps_start = 0, + .num_caps = 0, + .num_msi_vectors = 0, + .msi_64bits = 0, + .msi_maskable = 0, + .num_msix_vectors = 0, + .msix_region_size = 0x0, + .msix_address = 0x0, + }, + /* PCIDevice: 00:1d.2 */ + { + .type = JAILHOUSE_PCI_TYPE_DEVICE, + .iommu = 0, + .domain = 0x0, + .bdf = 0xea, + .bar_mask = { + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0xffffffe0, 0x00000000, + }, + .caps_start = 0, + .num_caps = 0, + .num_msi_vectors = 0, + .msi_64bits = 0, + .msi_maskable = 0, + .num_msix_vectors = 0, + .msix_region_size = 0x0, + .msix_address = 0x0, + }, + /* PCIDevice: 00:1d.7 */ + { + .type = JAILHOUSE_PCI_TYPE_DEVICE, + .iommu = 0, + .domain = 0x0, + .bdf = 0xef, + .bar_mask = { + 0xfffff000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, + }, + .caps_start = 0, + .num_caps = 0, + .num_msi_vectors = 0, + .msi_64bits = 0, + .msi_maskable = 0, + .num_msix_vectors = 0, + .msix_region_size = 0x0, + .msix_address = 0x0, + }, + /* PCIDevice: 00:1f.0 */ + { + .type = JAILHOUSE_PCI_TYPE_DEVICE, + .iommu = 0, + .domain = 0x0, + .bdf = 0xf8, + .bar_mask = { + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, + }, + .caps_start = 0, + .num_caps = 0, + .num_msi_vectors = 0, + .msi_64bits = 0, + .msi_maskable = 0, + .num_msix_vectors = 0, + .msix_region_size = 0x0, + .msix_address = 0x0, + }, + /* PCIDevice: 00:1f.2 */ + { + .type = JAILHOUSE_PCI_TYPE_DEVICE, + .iommu = 0, + .domain = 0x0, + .bdf = 0xfa, + .bar_mask = { + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0xffffffe0, 0xfffff000, + }, + .caps_start = 12, + .num_caps = 2, + .num_msi_vectors = 1, + .msi_64bits = 1, + .msi_maskable = 0, + .num_msix_vectors = 0, + .msix_region_size = 0x0, + .msix_address = 0x0, + }, + /* PCIDevice: 00:1f.3 */ + { + .type = JAILHOUSE_PCI_TYPE_DEVICE, + .iommu = 0, + .domain = 0x0, + .bdf = 0xfb, + .bar_mask = { + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0xffffffc0, 0x00000000, + }, + .caps_start = 0, + .num_caps = 0, + .num_msi_vectors = 0, + .msi_64bits = 0, + .msi_maskable = 0, + .num_msix_vectors = 0, + .msix_region_size = 0x0, + .msix_address = 0x0, + }, + }, + + .pci_caps = { + /* PCIDevice: 00:01.0 */ + /* PCIDevice: 00:02.0 */ + /* PCIDevice: 00:04.0 */ + { + .id = PCI_CAP_ID_MSIX, + .start = 0x98, + .len = 0xc, + .flags = JAILHOUSE_PCICAPS_WRITE, + }, + { + .id = PCI_CAP_ID_VNDR, + .start = 0x84, + .len = 0x2, + .flags = 0, + }, + { + .id = PCI_CAP_ID_VNDR, + .start = 0x70, + .len = 0x2, + .flags = 0, + }, + { + .id = PCI_CAP_ID_VNDR, + .start = 0x60, + .len = 0x2, + .flags = 0, + }, + { + .id = PCI_CAP_ID_VNDR, + .start = 0x50, + .len = 0x2, + .flags = 0, + }, + { + .id = PCI_CAP_ID_VNDR, + .start = 0x40, + .len = 0x2, + .flags = 0, + }, + /* PCIDevice: 00:03.0 */ + { + .id = PCI_CAP_ID_VNDR, + .start = 0x84, + .len = 0x2, + .flags = 0, + }, + { + .id = PCI_CAP_ID_VNDR, + .start = 0x70, + .len = 0x2, + .flags = 0, + }, + { + .id = PCI_CAP_ID_VNDR, + .start = 0x60, + .len = 0x2, + .flags = 0, + }, + { + .id = PCI_CAP_ID_VNDR, + .start = 0x50, + .len = 0x2, + .flags = 0, + }, + { + .id = PCI_CAP_ID_VNDR, + .start = 0x40, + .len = 0x2, + .flags = 0, + }, + /* PCIDevice: 00:1b.0 */ + { + .id = PCI_CAP_ID_MSI, + .start = 0x60, + .len = 0xe, + .flags = JAILHOUSE_PCICAPS_WRITE, + }, + /* PCIDevice: 00:1f.2 */ + { + .id = PCI_CAP_ID_MSI, + .start = 0x80, + .len = 0xe, + .flags = JAILHOUSE_PCICAPS_WRITE, + }, + { + .id = PCI_CAP_ID_SATA, + .start = 0xa8, + .len = 0x2, + .flags = 0, + }, + }, +}; |