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From a859bc214aa913be022a7aa8f03723079a325b07 Mon Sep 17 00:00:00 2001
From: Chee Hong Ang <chee.hong.ang@intel.com>
Date: Fri, 20 Apr 2018 18:28:07 +0800
Subject: [PATCH 04/12] ARM: socfpga: stratix10: Enable SMC/PSCI calls from
slave CPUs
Before this patch, only master CPU (CPU0) is able to
make SMC/PSCI calls to EL3 exception handler. This patch
allow SMC/PSCI calls from slave CPUs (CPU1/2/3) as well.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
arch/arm/mach-socfpga/Makefile | 1 +
arch/arm/mach-socfpga/lowlevel_init.S | 97 +++++++++++++++++++++++
include/configs/socfpga_stratix10_socdk.h | 6 ++
3 files changed, 104 insertions(+)
create mode 100644 arch/arm/mach-socfpga/lowlevel_init.S
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index f77b229a38..d34198d159 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -29,6 +29,7 @@ obj-y += reset_manager_arria10.o
endif
ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+obj-y += lowlevel_init.o
obj-y += clock_manager_s10.o
obj-y += mailbox_s10.o
obj-y += misc_s10.o
diff --git a/arch/arm/mach-socfpga/lowlevel_init.S b/arch/arm/mach-socfpga/lowlevel_init.S
new file mode 100644
index 0000000000..832785a682
--- /dev/null
+++ b/arch/arm/mach-socfpga/lowlevel_init.S
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2018 Intel Corporation. All rights reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMV8_PSCI)
+.align 3
+_el3_exception_vectors:
+ .word el3_exception_vectors;
+ .word 0
+#endif
+
+ENTRY(lowlevel_init)
+ mov x29, lr /* Save LR */
+
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+ branch_if_slave x0, 1f
+ ldr x0, =GICD_BASE
+ bl gic_init_secure
+1:
+#if defined(CONFIG_GICV3)
+ ldr x0, =GICR_BASE
+ bl gic_init_secure_percpu
+#elif defined(CONFIG_GICV2)
+ ldr x0, =GICD_BASE
+ ldr x1, =GICC_BASE
+ bl gic_init_secure_percpu
+#endif
+#endif
+
+#ifdef CONFIG_ARMV8_MULTIENTRY
+ branch_if_master x0, x1, 2f
+
+ /*
+ * Slave should wait for master clearing spin table.
+ * This sync prevent slaves observing incorrect
+ * value of spin table and jumping to wrong place.
+ */
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+#ifdef CONFIG_GICV2
+ ldr x0, =GICC_BASE
+#endif
+ bl gic_wait_for_interrupt
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+ /*
+ * Read the u-boot's PSCI exception handler's vector base
+ * address from the sysmgr.boot_scratch_cold6 & 7 and update
+ * their VBAR_EL3 respectively.
+ */
+wait_vbar_el3:
+ ldr x4, =VBAR_EL3_BASE_ADDR
+ ldr x5, [x4]
+ cbz x5, wait_vbar_el3
+ msr vbar_el3, x5
+#endif
+ /*
+ * All slaves will enter EL2 and optionally EL1.
+ */
+ adr x4, lowlevel_in_el2
+ ldr x5, =ES_TO_AARCH64
+ bl armv8_switch_to_el2
+
+lowlevel_in_el2:
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+ adr x4, lowlevel_in_el1
+ ldr x5, =ES_TO_AARCH64
+ bl armv8_switch_to_el1
+
+lowlevel_in_el1:
+#endif
+
+#endif /* CONFIG_ARMV8_MULTIENTRY */
+
+2:
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMV8_PSCI)
+ /*
+ * Write the u-boot PSCI exception handler's vector base address
+ * into a sysmgr.boot_scratch_cold6 & 7 so that other slave cpus
+ * are able to get the vector base address and update their VBAR_EL3
+ * respectively.
+ */
+ adr x0, _el3_exception_vectors
+ ldr x5, [x0]
+ ldr x4, =VBAR_EL3_BASE_ADDR
+ str x5, [x4]
+#endif
+ mov lr, x29 /* Restore LR */
+ ret
+ENDPROC(lowlevel_init)
diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h
index 8d2971c6e2..39d757d737 100644
--- a/include/configs/socfpga_stratix10_socdk.h
+++ b/include/configs/socfpga_stratix10_socdk.h
@@ -19,6 +19,12 @@
#define CONFIG_REMAKE_ELF
/* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
#define CPU_RELEASE_ADDR 0xFFD12210
+/*
+ * sysmgr.boot_scratch_cold6 & 7 (64bit) will be used by master CPU to
+ * store its VBAR_EL3 value. Other slave CPUs will read from this
+ * location and update their VBAR_EL3 respectively
+ */
+#define VBAR_EL3_BASE_ADDR 0xFFD12218
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_MEM_RESERVE_SECURE 0 /* using OCRAM, not DDR */
--
2.21.0
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