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From 16460c05fe576050cf485282151fd5623d6e862a Mon Sep 17 00:00:00 2001
From: Dalon Westergreen <dalon.westergreen@intel.com>
Date: Wed, 22 May 2019 17:05:12 -0700
Subject: [PATCH 05/12] ARM: socfpga: stratix10: Add SOCFPGA bridges reset
support for PSCI call
Add SOCFPGA bridges reset support for FPGA configuration SMC services
to disable/enable the bridges before and after the FPGA configuration
process.
Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
---
.../include/mach/reset_manager_s10.h | 1 +
arch/arm/mach-socfpga/reset_manager_s10.c | 25 ++++++++++++++++++-
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
index 452147b017..1939ffa149 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
@@ -11,6 +11,7 @@ void reset_cpu(ulong addr);
int cpu_has_been_warmreset(void);
void socfpga_bridges_reset(int enable);
+void socfpga_bridges_reset_psci(int enable);
void socfpga_per_reset(u32 reset, int set);
void socfpga_per_reset_all(void);
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index 499a84aff5..4494f6666f 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -9,6 +9,7 @@
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+#include <asm/secure.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -20,6 +21,8 @@ static const struct socfpga_system_manager *system_manager_base =
/* Assert or de-assert SoCFPGA reset manager reset. */
void socfpga_per_reset(u32 reset, int set)
{
+ static const struct socfpga_reset_manager *reset_manager_base =
+ (void *)SOCFPGA_RSTMGR_ADDRESS;
const void *reg;
if (RSTMGR_BANK(reset) == 0)
@@ -46,6 +49,8 @@ void socfpga_per_reset(u32 reset, int set)
*/
void socfpga_per_reset_all(void)
{
+ static const struct socfpga_reset_manager *reset_manager_base =
+ (void *)SOCFPGA_RSTMGR_ADDRESS;
const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
/* disable all except OCP and l4wd0. OCP disable later */
@@ -55,8 +60,13 @@ void socfpga_per_reset_all(void)
writel(0xffffffff, &reset_manager_base->per1modrst);
}
-void socfpga_bridges_reset(int enable)
+static __always_inline void __socfpga_bridges_reset(int enable)
{
+ static const struct socfpga_reset_manager *reset_manager_base =
+ (void *)SOCFPGA_RSTMGR_ADDRESS;
+ static const struct socfpga_system_manager *system_manager_base =
+ (void *)SOCFPGA_SYSMGR_ADDRESS;
+
if (enable) {
/* clear idle request to all bridges */
setbits_le32(&system_manager_base->noc_idlereq_clr, ~0);
@@ -94,11 +104,24 @@ void socfpga_bridges_reset(int enable)
}
}
+void socfpga_bridges_reset(int enable)
+{
+ __socfpga_bridges_reset(enable);
+}
+
+void __secure socfpga_bridges_reset_psci(int enable)
+{
+ __socfpga_bridges_reset(enable);
+}
+
/*
* Return non-zero if the CPU has been warm reset
*/
int cpu_has_been_warmreset(void)
{
+ static const struct socfpga_reset_manager *reset_manager_base =
+ (void *)SOCFPGA_RSTMGR_ADDRESS;
+
return readl(&reset_manager_base->status) &
RSTMGR_L4WD_MPU_WARMRESET_MASK;
}
--
2.21.0
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