path: root/bsp/meta-rcar/meta-rcar-gen3-adas/recipes-bsp/arm-trusted-firmware/files/0003-plat-renesas-rcar-Add-R-Car-V3M-support.patch

From 9f99c84671caae858cf20b8cce85a37ad7470fe2 Mon Sep 17 00:00:00 2001
From: Valentine Barshak <valentine.barshak@cogentembedded.com>
Date: Tue, 30 Oct 2018 02:06:17 +0300
Subject: [PATCH 3/5] plat: renesas: rcar: Add R-Car V3M support

Add R-Car V3M support. This is based on the original
V3M support patch for Yocto v2.23.1 by Vladimir Barinov.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
---
 plat/renesas/rcar/bl2_cpg_init.c                   |   68 ++
 plat/renesas/rcar/bl2_rcar_setup.c                 |   13 +-
 .../rcar/ddr/V3M/boot_init_dram_regdef_v3m.h       |    0
 plat/renesas/rcar/ddr/ddr.mk                       |    6 +-
 .../rcar/ddr/ddr_a/boot_init_dram_regdef_v3m.h     |  320 ++++++
 plat/renesas/rcar/ddr/ddr_a/ddr_a.mk               |    5 +
 plat/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c         |  364 +++++++
 plat/renesas/rcar/ddr/ddr_a/ddr_init_v3m.h         |   38 +
 plat/renesas/rcar/drivers/board/board.c            |    2 +
 plat/renesas/rcar/drivers/rom/rom_api.c            |   21 +-
 plat/renesas/rcar/drivers/scif/scif.S              |   36 +-
 plat/renesas/rcar/include/bl2_dma_register.h       |    4 +
 plat/renesas/rcar/include/platform_def.h           |   19 +-
 plat/renesas/rcar/pfc/V3M/pfc_init_v3m.c           | 1077 ++++++++++++++++++++
 plat/renesas/rcar/pfc/V3M/pfc_init_v3m.h           |   37 +
 plat/renesas/rcar/pfc/pfc.mk                       |    7 +
 plat/renesas/rcar/pfc/pfc_init.c                   |   20 +
 plat/renesas/rcar/platform.mk                      |   18 +
 plat/renesas/rcar/qos/V3M/qos_init_v3m.c           |  411 ++++++++
 plat/renesas/rcar/qos/V3M/qos_init_v3m.h           |   37 +
 plat/renesas/rcar/qos/qos.mk                       |    7 +
 plat/renesas/rcar/qos/qos_init.c                   |   27 +-
 plat/renesas/rcar/rcar_def.h                       |    1 +
 23 files changed, 2511 insertions(+), 27 deletions(-)
 mode change 100644 => 100755 plat/renesas/rcar/bl2_rcar_setup.c
 create mode 100644 plat/renesas/rcar/ddr/V3M/boot_init_dram_regdef_v3m.h
 create mode 100644 plat/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_v3m.h
 create mode 100644 plat/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
 create mode 100644 plat/renesas/rcar/ddr/ddr_a/ddr_init_v3m.h
 create mode 100644 plat/renesas/rcar/pfc/V3M/pfc_init_v3m.c
 create mode 100644 plat/renesas/rcar/pfc/V3M/pfc_init_v3m.h
 create mode 100644 plat/renesas/rcar/qos/V3M/qos_init_v3m.c
 create mode 100644 plat/renesas/rcar/qos/V3M/qos_init_v3m.h

diff --git a/plat/renesas/rcar/bl2_cpg_init.c b/plat/renesas/rcar/bl2_cpg_init.c
index 2377cd2..32a6746 100644
--- a/plat/renesas/rcar/bl2_cpg_init.c
+++ b/plat/renesas/rcar/bl2_cpg_init.c
@@ -28,6 +28,10 @@ static void bl2_system_cpg_init_m3n(void);
 static void bl2_realtime_cpg_init_e3(void);
 static void bl2_system_cpg_init_e3(void);
 #endif  /* (RCAR_LSI == RCAR_E3) */
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3M)
+static void bl2_realtime_cpg_init_v3m(void);
+static void bl2_system_cpg_init_v3m(void);
+#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3M) */
 
 typedef struct {
 	uintptr_t	adr;
@@ -365,6 +369,60 @@ static void bl2_system_cpg_init_e3(void)
 }
 #endif /* RCAR_LSI == RCAR_E3 */
 
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3M)
+static void bl2_realtime_cpg_init_v3m(void)
+{
+	/* CPG (REALTIME) registers */
+
+	/* Realtime Module Stop Control Register 0 */
+	cpg_write(RMSTPCR0,	0x00230000U);
+	/* Realtime Module Stop Control Register 1 */
+	cpg_write(RMSTPCR1,	0xFFFFFFFFU);
+	/* Realtime Module Stop Control Register 2 */
+	cpg_write(RMSTPCR2,	0x14062FD8U);
+	/* Realtime Module Stop Control Register 3 */
+	cpg_write(RMSTPCR3,	0xFFFFFFDFU);
+	/* Realtime Module Stop Control Register 4 */
+	cpg_write(RMSTPCR4,	0x80000184U);
+	/* Realtime Module Stop Control Register 5 */
+	cpg_write(RMSTPCR5,	0x83FFFFFFU);
+	/* Realtime Module Stop Control Register 6 */
+	cpg_write(RMSTPCR6,	0xFFFFFFFFU);
+	/* Realtime Module Stop Control Register 7 */
+	cpg_write(RMSTPCR7,	0xFFFFFFFFU);
+	/* Realtime Module Stop Control Register 8 */
+	cpg_write(RMSTPCR8,	0x7FF3FFF4U);
+	/* Realtime Module Stop Control Register 9 */
+	cpg_write(RMSTPCR9,	0xFFFFFFFEU);
+}
+
+static void bl2_system_cpg_init_v3m(void)
+{
+	/* CPG (SYSTEM) registers */
+
+	/* System Module Stop Control Register 0 */
+	cpg_write(SMSTPCR0,	0x00210000U);
+	/* System Module Stop Control Register 1 */
+	cpg_write(SMSTPCR1,	0xFFFFFFFFU);
+	/* System Module Stop Control Register 2 */
+	cpg_write(SMSTPCR2,	0x340E2FDCU);
+	/* System Module Stop Control Register 3 */
+	cpg_write(SMSTPCR3,	0xFFFFFBDFU);
+	/* System Module Stop Control Register 4 */
+	cpg_write(SMSTPCR4,	0x80000004U);
+	/* System Module Stop Control Register 5 */
+	cpg_write(SMSTPCR5,	0xC3FFFFFFU);
+	/* System Module Stop Control Register 6 */
+	cpg_write(SMSTPCR6,	0xFFFFFFFFU);
+	/* System Module Stop Control Register 7 */
+	cpg_write(SMSTPCR7,	0xFFFFFFFFU);
+	/* System Module Stop Control Register 8 */
+	cpg_write(SMSTPCR8,	0x01F1FFF5U);
+	/* System Module Stop Control Register 9 */
+	cpg_write(SMSTPCR9,	0xFFFFFFFEU);
+}
+#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3M) */
+
 void bl2_cpg_init(void)
 {
 	uint32_t	modemr;
@@ -393,6 +451,9 @@ void bl2_cpg_init(void)
 		case RCAR_PRODUCT_M3N:
 			bl2_realtime_cpg_init_m3n();
 			break;
+		case RCAR_PRODUCT_V3M:
+			bl2_realtime_cpg_init_v3m();
+			break;
 		default:
 			panic();
 			break;
@@ -405,6 +466,8 @@ void bl2_cpg_init(void)
 		bl2_realtime_cpg_init_m3n();
 #elif RCAR_LSI == RCAR_E3
 		bl2_realtime_cpg_init_e3();
+#elif RCAR_LSI == RCAR_V3M
+		bl2_realtime_cpg_init_v3m();
 #else /* RCAR_LSI == RCAR_XX */
 #error "Don't have CPG initialize routine(unknown)."
 #endif /* RCAR_LSI == RCAR_XX */
@@ -427,6 +490,9 @@ void bl2_system_cpg_init(void)
 	case RCAR_PRODUCT_M3N:
 		bl2_system_cpg_init_m3n();
 		break;
+	case RCAR_PRODUCT_V3M:
+		bl2_system_cpg_init_v3m();
+		break;
 	default:
 		panic();
 		break;
@@ -439,6 +505,8 @@ void bl2_system_cpg_init(void)
 	bl2_system_cpg_init_m3n();
 #elif RCAR_LSI == RCAR_E3
 	bl2_system_cpg_init_e3();
+#elif RCAR_LSI == RCAR_V3M
+	bl2_system_cpg_init_v3m();
 #else /* RCAR_LSI == RCAR_XX */
 #error "Don't have CPG initialize routine(unknown)."
 #endif /* RCAR_LSI == RCAR_XX */
diff --git a/plat/renesas/rcar/bl2_rcar_setup.c b/plat/renesas/rcar/bl2_rcar_setup.c
old mode 100644
new mode 100755
index 516ab09..02a15c2
--- a/plat/renesas/rcar/bl2_rcar_setup.c
+++ b/plat/renesas/rcar/bl2_rcar_setup.c
@@ -129,8 +129,11 @@
 #elif RCAR_LSI == RCAR_E3
 #define TARGET_PRODUCT		RCAR_PRODUCT_E3
 #define TARGET_NAME		"R-Car E3"
+#elif RCAR_LSI == RCAR_V3M
+#define TARGET_PRODUCT		RCAR_PRODUCT_V3M
+#define TARGET_NAME		"R-Car V3M"
 #elif RCAR_LSI == RCAR_AUTO
-#define TARGET_NAME		"R-Car H3/M3/M3N"
+#define TARGET_NAME		"R-Car H3/M3/M3N/V3M"
 #endif
 
 /* for SuspendToRAM */
@@ -386,6 +389,7 @@ static void rcar_bl2_early_platform_setup(const meminfo_t *mem_layout)
 	const char *product_m3      = "M3";
 	const char *product_m3n     = "M3N";
 	const char *product_e3      = "E3";
+	const char *product_v3m     = "V3M";
 	const char *lcs_cm          = "CM";
 	const char *lcs_dm          = "DM";
 	const char *lcs_sd          = "SD";
@@ -470,6 +474,9 @@ static void rcar_bl2_early_platform_setup(const meminfo_t *mem_layout)
 	case RCAR_PRODUCT_E3:
 		str = product_e3;
 		break;
+	case RCAR_PRODUCT_V3M:
+		str = product_v3m;
+		break;
 	default:
 		str = unknown;
 		break;
@@ -544,11 +551,13 @@ static void rcar_bl2_early_platform_setup(const meminfo_t *mem_layout)
 	}
 #endif /* RCAR_LSI != RCAR_AUTO */
 
+#if RCAR_LSI != RCAR_V3M
 	/* Initialize AVS Settings */
 	bl2_avs_init();
 
 	/* Proceed with separated AVS processing */
 	bl2_avs_setting();
+#endif
 
 	switch (modemr_boot_dev) {
 	case MODEMR_BOOT_DEV_HYPERFLASH160:
@@ -576,8 +585,10 @@ static void rcar_bl2_early_platform_setup(const meminfo_t *mem_layout)
 	(void)sprintf(msg, "BL2: Boot device is %s\n", str);
 	NOTICE("%s", msg);
 
+#if RCAR_LSI != RCAR_V3M
 	/* Proceed with separated AVS processing */
 	bl2_avs_setting();
+#endif
 
 	reg = ROM_GetLcs(&lcs);
 	if (reg == 0U) {
diff --git a/plat/renesas/rcar/ddr/V3M/boot_init_dram_regdef_v3m.h b/plat/renesas/rcar/ddr/V3M/boot_init_dram_regdef_v3m.h
new file mode 100644
index 0000000..e69de29
diff --git a/plat/renesas/rcar/ddr/ddr.mk b/plat/renesas/rcar/ddr/ddr.mk
index adabc0b..73d192e 100644
--- a/plat/renesas/rcar/ddr/ddr.mk
+++ b/plat/renesas/rcar/ddr/ddr.mk
@@ -4,10 +4,10 @@
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
-ifeq (${RCAR_LSI},${RCAR_E3})
-    include plat/renesas/rcar/ddr/ddr_a/ddr_a.mk
+ifneq ($(filter ${RCAR_LSI},${RCAR_E3} ${RCAR_V3M}),)
+include plat/renesas/rcar/ddr/ddr_a/ddr_a.mk
 else
-    include plat/renesas/rcar/ddr/ddr_b/ddr_b.mk
+include plat/renesas/rcar/ddr/ddr_b/ddr_b.mk
 endif
 
 BL2_SOURCES += plat/renesas/rcar/ddr/dram_sub_func.c
diff --git a/plat/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_v3m.h b/plat/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_v3m.h
new file mode 100644
index 0000000..40383ad
--- /dev/null
+++ b/plat/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_v3m.h
@@ -0,0 +1,320 @@
+/*
+ * Copyright (c) 2015-2016, Renesas Electronics Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *
+ *   - Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *
+ *   - Neither the name of Renesas nor the names of its contributors may be
+ *     used to endorse or promote products derived from this software without
+ *     specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef BOOT_INIT_DRAM_REGDEF_V3M_H_
+#define BOOT_INIT_DRAM_REGDEF_V3M_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define				BIT0						0x00000001U
+#define				BIT30						0x40000000U
+
+/* DBSC registers */
+
+// modified , last 2016.12.08 
+
+#define				DBSC_V3M_DBSYSCONF0         0xE6790000U
+#define				DBSC_V3M_DBSYSCONF1         0xE6790004U
+#define				DBSC_V3M_DBPHYCONF0         0xE6790010U
+#define				DBSC_V3M_DBKIND             0xE6790020U
+#define				DBSC_V3M_DBMEMCONF00        0xE6790030U
+#define				DBSC_V3M_DBMEMCONF01        0xE6790034U
+#define				DBSC_V3M_DBMEMCONF02        0xE6790038U
+#define				DBSC_V3M_DBMEMCONF03        0xE679003CU
+#define				DBSC_V3M_DBMEMCONF10        0xE6790040U
+#define				DBSC_V3M_DBMEMCONF11        0xE6790044U
+#define				DBSC_V3M_DBMEMCONF12        0xE6790048U
+#define				DBSC_V3M_DBMEMCONF13        0xE679004CU
+#define				DBSC_V3M_DBMEMCONF20        0xE6790050U
+#define				DBSC_V3M_DBMEMCONF21        0xE6790054U
+#define				DBSC_V3M_DBMEMCONF22        0xE6790058U
+#define				DBSC_V3M_DBMEMCONF23        0xE679005CU
+#define				DBSC_V3M_DBMEMCONF30        0xE6790060U
+#define				DBSC_V3M_DBMEMCONF31        0xE6790064U
+#define				DBSC_V3M_DBMEMCONF32        0xE6790068U
+#define				DBSC_V3M_DBMEMCONF33        0xE679006CU
+#define				DBSC_V3M_DBSYSCNT0          0xE6790100U
+#define				DBSC_V3M_DBSVCR1            0xE6790104U
+#define				DBSC_V3M_DBSTATE0           0xE6790108U
+#define				DBSC_V3M_DBSTATE1           0xE679010CU
+#define				DBSC_V3M_DBINTEN            0xE6790180U
+#define				DBSC_V3M_DBINTSTAT0         0xE6790184U
+#define				DBSC_V3M_DBACEN             0xE6790200U
+#define				DBSC_V3M_DBRFEN             0xE6790204U
+#define				DBSC_V3M_DBCMD              0xE6790208U
+#define				DBSC_V3M_DBWAIT             0xE6790210U
+#define				DBSC_V3M_DBSYSCTRL0         0xE6790280U
+#define				DBSC_V3M_DBTR0              0xE6790300U
+#define				DBSC_V3M_DBTR1              0xE6790304U
+#define				DBSC_V3M_DBTR2              0xE6790308U
+#define				DBSC_V3M_DBTR3              0xE679030CU
+#define				DBSC_V3M_DBTR4              0xE6790310U
+#define				DBSC_V3M_DBTR5              0xE6790314U
+#define				DBSC_V3M_DBTR6              0xE6790318U
+#define				DBSC_V3M_DBTR7              0xE679031CU
+#define				DBSC_V3M_DBTR8              0xE6790320U
+#define				DBSC_V3M_DBTR9              0xE6790324U
+#define				DBSC_V3M_DBTR10             0xE6790328U
+#define				DBSC_V3M_DBTR11             0xE679032CU
+#define				DBSC_V3M_DBTR12             0xE6790330U
+#define				DBSC_V3M_DBTR13             0xE6790334U
+#define				DBSC_V3M_DBTR14             0xE6790338U
+#define				DBSC_V3M_DBTR15             0xE679033CU
+#define				DBSC_V3M_DBTR16             0xE6790340U
+#define				DBSC_V3M_DBTR17             0xE6790344U
+#define				DBSC_V3M_DBTR18             0xE6790348U
+#define				DBSC_V3M_DBTR19             0xE679034CU
+#define				DBSC_V3M_DBTR20             0xE6790350U
+#define				DBSC_V3M_DBTR21             0xE6790354U
+#define				DBSC_V3M_DBTR22             0xE6790358U
+#define				DBSC_V3M_DBTR23             0xE679035CU
+#define				DBSC_V3M_DBTR24             0xE6790360U
+#define				DBSC_V3M_DBTR25             0xE6790364U
+#define				DBSC_V3M_DBBL               0xE6790400U
+#define				DBSC_V3M_DBRFCNF1           0xE6790414U
+#define				DBSC_V3M_DBRFCNF2           0xE6790418U
+#define				DBSC_V3M_DBTSPCNF           0xE6790420U
+#define				DBSC_V3M_DBCALCNF           0xE6790424U
+#define				DBSC_V3M_DBRNK2             0xE6790438U
+#define				DBSC_V3M_DBRNK3             0xE679043CU
+#define				DBSC_V3M_DBRNK4             0xE6790440U
+#define				DBSC_V3M_DBRNK5             0xE6790444U
+#define				DBSC_V3M_DBPDNCNF           0xE6790450U
+#define				DBSC_V3M_DBODT0             0xE6790460U
+#define				DBSC_V3M_DBODT1             0xE6790464U
+#define				DBSC_V3M_DBODT2             0xE6790468U
+#define				DBSC_V3M_DBODT3             0xE679046CU
+#define				DBSC_V3M_DBODT4             0xE6790470U
+#define				DBSC_V3M_DBODT5             0xE6790474U
+#define				DBSC_V3M_DBODT6             0xE6790478U
+#define				DBSC_V3M_DBODT7             0xE679047CU
+#define				DBSC_V3M_DBADJ0             0xE6790500U
+#define				DBSC_V3M_DBDBICNT           0xE6790518U
+#define				DBSC_V3M_DBDFIPMSTRCNF      0xE6790520U
+#define				DBSC_V3M_DBDFIPMSTRSTAT     0xE6790524U
+#define				DBSC_V3M_DBDFILPCNF         0xE6790528U
+#define				DBSC_V3M_DBDFICUPDCNF       0xE679052CU
+#define				DBSC_V3M_DBDFISTAT0         0xE6790600U
+#define				DBSC_V3M_DBDFICNT0          0xE6790604U
+#define				DBSC_V3M_DBPDCNT00          0xE6790610U
+#define				DBSC_V3M_DBPDCNT01          0xE6790614U
+#define				DBSC_V3M_DBPDCNT02          0xE6790618U
+#define				DBSC_V3M_DBPDCNT03          0xE679061CU
+#define				DBSC_V3M_DBPDLK0            0xE6790620U
+#define				DBSC_V3M_DBPDRGA0           0xE6790624U
+#define				DBSC_V3M_DBPDRGD0           0xE6790628U
+#define				DBSC_V3M_DBPDSTAT00         0xE6790630U
+#define				DBSC_V3M_DBDFISTAT1         0xE6790640U
+#define				DBSC_V3M_DBDFICNT1          0xE6790644U
+#define				DBSC_V3M_DBPDCNT10          0xE6790650U
+#define				DBSC_V3M_DBPDCNT11          0xE6790654U
+#define				DBSC_V3M_DBPDCNT12          0xE6790658U
+#define				DBSC_V3M_DBPDCNT13          0xE679065CU
+#define				DBSC_V3M_DBPDLK1            0xE6790660U
+#define				DBSC_V3M_DBPDRGA1           0xE6790664U
+#define				DBSC_V3M_DBPDRGD1           0xE6790668U
+#define				DBSC_V3M_DBPDSTAT10         0xE6790670U
+#define				DBSC_V3M_DBDFISTAT2         0xE6790680U
+#define				DBSC_V3M_DBDFICNT2          0xE6790684U
+#define				DBSC_V3M_DBPDCNT20          0xE6790690U
+#define				DBSC_V3M_DBPDCNT21          0xE6790694U
+#define				DBSC_V3M_DBPDCNT22          0xE6790698U
+#define				DBSC_V3M_DBPDCNT23          0xE679069CU
+#define				DBSC_V3M_DBPDLK2            0xE67906A0U
+#define				DBSC_V3M_DBPDRGA2           0xE67906A4U
+#define				DBSC_V3M_DBPDRGD2           0xE67906A8U
+#define				DBSC_V3M_DBPDSTAT20         0xE67906B0U
+#define				DBSC_V3M_DBDFISTAT3         0xE67906C0U
+#define				DBSC_V3M_DBDFICNT3          0xE67906C4U
+#define				DBSC_V3M_DBPDCNT30          0xE67906D0U
+#define				DBSC_V3M_DBPDCNT31          0xE67906D4U
+#define				DBSC_V3M_DBPDCNT32          0xE67906D8U
+#define				DBSC_V3M_DBPDCNT33          0xE67906DCU
+#define				DBSC_V3M_DBPDLK3            0xE67906E0U
+#define				DBSC_V3M_DBPDRGA3           0xE67906E4U
+#define				DBSC_V3M_DBPDRGD3           0xE67906E8U
+#define				DBSC_V3M_DBPDSTAT30         0xE67906F0U
+#define				DBSC_V3M_DBBUS0CNF0         0xE6790800U
+#define				DBSC_V3M_DBBUS0CNF1         0xE6790804U
+#define				DBSC_V3M_DBCAM0CNF1         0xE6790904U
+#define				DBSC_V3M_DBCAM0CNF2         0xE6790908U
+#define				DBSC_V3M_DBCAM0CNF3         0xE679090CU
+#define				DBSC_V3M_DBCAM0CTRL0        0xE6790940U
+#define				DBSC_V3M_DBCAM0STAT0        0xE6790980U
+#define				DBSC_V3M_DBCAM1STAT0        0xE6790990U
+#define				DBSC_V3M_DBBCAMSWAP         0xE67909F0U
+#define				DBSC_V3M_DBBCAMDIS          0xE67909FCU
+#define				DBSC_V3M_DBSCHCNT0          0xE6791000U
+#define				DBSC_V3M_DBSCHCNT1          0xE6791004U
+#define				DBSC_V3M_DBSCHSZ0           0xE6791010U
+#define				DBSC_V3M_DBSCHRW0           0xE6791020U
+#define				DBSC_V3M_DBSCHRW1           0xE6791024U
+#define				DBSC_V3M_DBSCHQOS00         0xE6791030U
+#define				DBSC_V3M_DBSCHQOS01         0xE6791034U
+#define				DBSC_V3M_DBSCHQOS02         0xE6791038U
+#define				DBSC_V3M_DBSCHQOS03         0xE679103CU
+#define				DBSC_V3M_DBSCHQOS10         0xE6791040U
+#define				DBSC_V3M_DBSCHQOS11         0xE6791044U
+#define				DBSC_V3M_DBSCHQOS12         0xE6791048U
+#define				DBSC_V3M_DBSCHQOS13         0xE679104CU
+#define				DBSC_V3M_DBSCHQOS20         0xE6791050U
+#define				DBSC_V3M_DBSCHQOS21         0xE6791054U
+#define				DBSC_V3M_DBSCHQOS22         0xE6791058U
+#define				DBSC_V3M_DBSCHQOS23         0xE679105CU
+#define				DBSC_V3M_DBSCHQOS30         0xE6791060U
+#define				DBSC_V3M_DBSCHQOS31         0xE6791064U
+#define				DBSC_V3M_DBSCHQOS32         0xE6791068U
+#define				DBSC_V3M_DBSCHQOS33         0xE679106CU
+#define				DBSC_V3M_DBSCHQOS40         0xE6791070U
+#define				DBSC_V3M_DBSCHQOS41         0xE6791074U
+#define				DBSC_V3M_DBSCHQOS42         0xE6791078U
+#define				DBSC_V3M_DBSCHQOS43         0xE679107CU
+#define				DBSC_V3M_DBSCHQOS50         0xE6791080U
+#define				DBSC_V3M_DBSCHQOS51         0xE6791084U
+#define				DBSC_V3M_DBSCHQOS52         0xE6791088U
+#define				DBSC_V3M_DBSCHQOS53         0xE679108CU
+#define				DBSC_V3M_DBSCHQOS60         0xE6791090U
+#define				DBSC_V3M_DBSCHQOS61         0xE6791094U
+#define				DBSC_V3M_DBSCHQOS62         0xE6791098U
+#define				DBSC_V3M_DBSCHQOS63         0xE679109CU
+#define				DBSC_V3M_DBSCHQOS70         0xE67910A0U
+#define				DBSC_V3M_DBSCHQOS71         0xE67910A4U
+#define				DBSC_V3M_DBSCHQOS72         0xE67910A8U
+#define				DBSC_V3M_DBSCHQOS73         0xE67910ACU
+#define				DBSC_V3M_DBSCHQOS80         0xE67910B0U
+#define				DBSC_V3M_DBSCHQOS81         0xE67910B4U
+#define				DBSC_V3M_DBSCHQOS82         0xE67910B8U
+#define				DBSC_V3M_DBSCHQOS83         0xE67910BCU
+#define				DBSC_V3M_DBSCHQOS90         0xE67910C0U
+#define				DBSC_V3M_DBSCHQOS91         0xE67910C4U
+#define				DBSC_V3M_DBSCHQOS92         0xE67910C8U
+#define				DBSC_V3M_DBSCHQOS93         0xE67910CCU
+#define				DBSC_V3M_DBSCHQOS100        0xE67910D0U
+#define				DBSC_V3M_DBSCHQOS101        0xE67910D4U
+#define				DBSC_V3M_DBSCHQOS102        0xE67910D8U
+#define				DBSC_V3M_DBSCHQOS103        0xE67910DCU
+#define				DBSC_V3M_DBSCHQOS110        0xE67910E0U
+#define				DBSC_V3M_DBSCHQOS111        0xE67910E4U
+#define				DBSC_V3M_DBSCHQOS112        0xE67910E8U
+#define				DBSC_V3M_DBSCHQOS113        0xE67910ECU
+#define				DBSC_V3M_DBSCHQOS120        0xE67910F0U
+#define				DBSC_V3M_DBSCHQOS121        0xE67910F4U
+#define				DBSC_V3M_DBSCHQOS122        0xE67910F8U
+#define				DBSC_V3M_DBSCHQOS123        0xE67910FCU
+#define				DBSC_V3M_DBSCHQOS130        0xE6791100U
+#define				DBSC_V3M_DBSCHQOS131        0xE6791104U
+#define				DBSC_V3M_DBSCHQOS132        0xE6791108U
+#define				DBSC_V3M_DBSCHQOS133        0xE679110CU
+#define				DBSC_V3M_DBSCHQOS140        0xE6791110U
+#define				DBSC_V3M_DBSCHQOS141        0xE6791114U
+#define				DBSC_V3M_DBSCHQOS142        0xE6791118U
+#define				DBSC_V3M_DBSCHQOS143        0xE679111CU
+#define				DBSC_V3M_DBSCHQOS150        0xE6791120U
+#define				DBSC_V3M_DBSCHQOS151        0xE6791124U
+#define				DBSC_V3M_DBSCHQOS152        0xE6791128U
+#define				DBSC_V3M_DBSCHQOS153        0xE679112CU
+#define				DBSC_V3M_SCFCTST0           0xE6791700U
+#define				DBSC_V3M_SCFCTST1           0xE6791708U
+#define				DBSC_V3M_SCFCTST2           0xE679170CU
+#define				DBSC_V3M_DBMRRDR0           0xE6791800U
+#define				DBSC_V3M_DBMRRDR1           0xE6791804U
+#define				DBSC_V3M_DBMRRDR2           0xE6791808U
+#define				DBSC_V3M_DBMRRDR3           0xE679180CU
+#define				DBSC_V3M_DBMRRDR4           0xE6791810U
+#define				DBSC_V3M_DBMRRDR5           0xE6791814U
+#define				DBSC_V3M_DBMRRDR6           0xE6791818U
+#define				DBSC_V3M_DBMRRDR7           0xE679181CU
+#define				DBSC_V3M_DBDTMP0            0xE6791820U
+#define				DBSC_V3M_DBDTMP1            0xE6791824U
+#define				DBSC_V3M_DBDTMP2            0xE6791828U
+#define				DBSC_V3M_DBDTMP3            0xE679182CU
+#define				DBSC_V3M_DBDTMP4            0xE6791830U
+#define				DBSC_V3M_DBDTMP5            0xE6791834U
+#define				DBSC_V3M_DBDTMP6            0xE6791838U
+#define				DBSC_V3M_DBDTMP7            0xE679183CU
+#define				DBSC_V3M_DBDQSOSC00         0xE6791840U
+#define				DBSC_V3M_DBDQSOSC01         0xE6791844U
+#define				DBSC_V3M_DBDQSOSC10         0xE6791848U
+#define				DBSC_V3M_DBDQSOSC11         0xE679184CU
+#define				DBSC_V3M_DBDQSOSC20         0xE6791850U
+#define				DBSC_V3M_DBDQSOSC21         0xE6791854U
+#define				DBSC_V3M_DBDQSOSC30         0xE6791858U
+#define				DBSC_V3M_DBDQSOSC31         0xE679185CU
+#define				DBSC_V3M_DBDQSOSC40         0xE6791860U
+#define				DBSC_V3M_DBDQSOSC41         0xE6791864U
+#define				DBSC_V3M_DBDQSOSC50         0xE6791868U
+#define				DBSC_V3M_DBDQSOSC51         0xE679186CU
+#define				DBSC_V3M_DBDQSOSC60         0xE6791870U
+#define				DBSC_V3M_DBDQSOSC61         0xE6791874U
+#define				DBSC_V3M_DBDQSOSC70         0xE6791878U
+#define				DBSC_V3M_DBDQSOSC71         0xE679187CU
+#define				DBSC_V3M_DBOSCTHH00         0xE6791880U
+#define				DBSC_V3M_DBOSCTHH01         0xE6791884U
+#define				DBSC_V3M_DBOSCTHH10         0xE6791888U
+#define				DBSC_V3M_DBOSCTHH11         0xE679188CU
+#define				DBSC_V3M_DBOSCTHH20         0xE6791890U
+#define				DBSC_V3M_DBOSCTHH21         0xE6791894U
+#define				DBSC_V3M_DBOSCTHH30         0xE6791898U
+#define				DBSC_V3M_DBOSCTHH31         0xE679189CU
+#define				DBSC_V3M_DBOSCTHH40         0xE67918A0U
+#define				DBSC_V3M_DBOSCTHH41         0xE67918A4U
+#define				DBSC_V3M_DBOSCTHH50         0xE67918A8U
+#define				DBSC_V3M_DBOSCTHH51         0xE67918ACU
+#define				DBSC_V3M_DBOSCTHH60         0xE67918B0U
+#define				DBSC_V3M_DBOSCTHH61         0xE67918B4U
+#define				DBSC_V3M_DBOSCTHH70         0xE67918B8U
+#define				DBSC_V3M_DBOSCTHH71         0xE67918BCU
+#define				DBSC_V3M_DBOSCTHL00         0xE67918C0U
+#define				DBSC_V3M_DBOSCTHL01         0xE67918C4U
+#define				DBSC_V3M_DBOSCTHL10         0xE67918C8U
+#define				DBSC_V3M_DBOSCTHL11         0xE67918CCU
+#define				DBSC_V3M_DBOSCTHL20         0xE67918D0U
+#define				DBSC_V3M_DBOSCTHL21         0xE67918D4U
+#define				DBSC_V3M_DBOSCTHL30         0xE67918D8U
+#define				DBSC_V3M_DBOSCTHL31         0xE67918DCU
+#define				DBSC_V3M_DBOSCTHL40         0xE67918E0U
+#define				DBSC_V3M_DBOSCTHL41         0xE67918E4U
+#define				DBSC_V3M_DBOSCTHL50         0xE67918E8U
+#define				DBSC_V3M_DBOSCTHL51         0xE67918ECU
+#define				DBSC_V3M_DBOSCTHL60         0xE67918F0U
+#define				DBSC_V3M_DBOSCTHL61         0xE67918F4U
+#define				DBSC_V3M_DBOSCTHL70         0xE67918F8U
+#define				DBSC_V3M_DBOSCTHL71         0xE67918FCU
+#define				DBSC_V3M_DBMEMSWAPCONF0     0xE6792000U
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* BOOT_INIT_DRAM_REGDEF_V3M_H_*/
\ No newline at end of file
diff --git a/plat/renesas/rcar/ddr/ddr_a/ddr_a.mk b/plat/renesas/rcar/ddr/ddr_a/ddr_a.mk
index e6471a0..1be3172 100644
--- a/plat/renesas/rcar/ddr/ddr_a/ddr_a.mk
+++ b/plat/renesas/rcar/ddr/ddr_a/ddr_a.mk
@@ -4,4 +4,9 @@
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
+ifeq (${RCAR_LSI},${RCAR_E3})
 BL2_SOURCES += plat/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
+endif
+ifeq (${RCAR_LSI},${RCAR_V3M})
+BL2_SOURCES += plat/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
+endif
diff --git a/plat/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c b/plat/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
new file mode 100644
index 0000000..0120e78
--- /dev/null
+++ b/plat/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
@@ -0,0 +1,364 @@
+/*
+ * Copyright (c) 2015-2016, Renesas Electronics Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *
+ *   - Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *
+ *   - Neither the name of Renesas nor the names of its contributors may be
+ *     used to endorse or promote products derived from this software without
+ *     specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include "boot_init_dram.h"
+#include "boot_init_dram_regdef_v3m.h"
+
+void WriteReg_32(uintptr_t a, uint32_t v)
+{
+	*(volatile uint32_t*)a = v;
+}
+
+uint32_t ReadReg_32(uintptr_t a)
+{
+	uint32_t w = *(volatile uint32_t*)a;
+	return w;
+}
+
+uint32_t init_ddr_v3m1600(void)
+{
+	// last modified 2016.12.16
+
+	uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12;
+
+   WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234);
+   WriteReg_32(DBSC_V3M_DBKIND,0x00000007);
+#if RCAR_DRAM_DDR3L_MEMCONF == 0
+   WriteReg_32(DBSC_V3M_DBMEMCONF00,0x0f030a02); // 1GB: Eagle
+#else
+   WriteReg_32(DBSC_V3M_DBMEMCONF00,0x10030a02); // 2GB: V3MSK
+#endif
+   WriteReg_32(DBSC_V3M_DBPHYCONF0,0x00000001);
+   WriteReg_32(DBSC_V3M_DBTR0,0x0000000B);
+   WriteReg_32(DBSC_V3M_DBTR1,0x00000008);
+   WriteReg_32(DBSC_V3M_DBTR3,0x0000000B);
+   WriteReg_32(DBSC_V3M_DBTR4,0x000B000B);
+   WriteReg_32(DBSC_V3M_DBTR5,0x00000027);
+   WriteReg_32(DBSC_V3M_DBTR6,0x0000001C);
+   WriteReg_32(DBSC_V3M_DBTR7,0x00060006);
+   WriteReg_32(DBSC_V3M_DBTR8,0x00000020);
+   WriteReg_32(DBSC_V3M_DBTR9,0x00000006);
+   WriteReg_32(DBSC_V3M_DBTR10,0x0000000C);
+   WriteReg_32(DBSC_V3M_DBTR11,0x0000000B);
+   WriteReg_32(DBSC_V3M_DBTR12,0x00120012);
+   WriteReg_32(DBSC_V3M_DBTR13,0x01180118);
+   WriteReg_32(DBSC_V3M_DBTR14,0x00140005);
+   WriteReg_32(DBSC_V3M_DBTR15,0x00050004);
+   WriteReg_32(DBSC_V3M_DBTR16,0x071D0305);
+   WriteReg_32(DBSC_V3M_DBTR17,0x040C0010);
+   WriteReg_32(DBSC_V3M_DBTR18,0x00000200);
+   WriteReg_32(DBSC_V3M_DBTR19,0x01000040);
+   WriteReg_32(DBSC_V3M_DBTR20,0x02000120);
+   WriteReg_32(DBSC_V3M_DBTR21,0x00040004);
+   WriteReg_32(DBSC_V3M_DBBL,0x00000000);
+   WriteReg_32(DBSC_V3M_DBODT0,0x00000001);
+   WriteReg_32(DBSC_V3M_DBADJ0,0x00000001);
+   WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00082010);
+   WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x00002000);
+   WriteReg_32(DBSC_V3M_DBSCHCNT0,0x080f003f);
+   WriteReg_32(DBSC_V3M_DBSCHCNT1,0x00001010);
+   WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000001);
+   WriteReg_32(DBSC_V3M_DBSCHRW0,0x00000200);
+   WriteReg_32(DBSC_V3M_DBSCHRW1,0x00000040);
+   WriteReg_32(DBSC_V3M_DBSCHQOS40,0x00000600);
+   WriteReg_32(DBSC_V3M_DBSCHQOS41,0x00000480);
+   WriteReg_32(DBSC_V3M_DBSCHQOS42,0x00000300);
+   WriteReg_32(DBSC_V3M_DBSCHQOS43,0x00000180);
+   WriteReg_32(DBSC_V3M_DBSCHQOS90,0x00000400);
+   WriteReg_32(DBSC_V3M_DBSCHQOS91,0x00000300);
+   WriteReg_32(DBSC_V3M_DBSCHQOS92,0x00000200);
+   WriteReg_32(DBSC_V3M_DBSCHQOS93,0x00000100);
+   WriteReg_32(DBSC_V3M_DBSCHQOS130,0x00000300);
+   WriteReg_32(DBSC_V3M_DBSCHQOS131,0x00000240);
+   WriteReg_32(DBSC_V3M_DBSCHQOS132,0x00000180);
+   WriteReg_32(DBSC_V3M_DBSCHQOS133,0x000000c0);
+   WriteReg_32(DBSC_V3M_DBSCHQOS140,0x00000200);
+   WriteReg_32(DBSC_V3M_DBSCHQOS141,0x00000180);
+   WriteReg_32(DBSC_V3M_DBSCHQOS142,0x00000100);
+   WriteReg_32(DBSC_V3M_DBSCHQOS143,0x00000080);
+   WriteReg_32(DBSC_V3M_DBSCHQOS150,0x00000100);
+   WriteReg_32(DBSC_V3M_DBSCHQOS151,0x000000c0);
+   WriteReg_32(DBSC_V3M_DBSCHQOS152,0x00000080);
+   WriteReg_32(DBSC_V3M_DBSCHQOS153,0x00000040);
+   WriteReg_32(DBSC_V3M_DBSYSCONF1,0x00000002);
+   WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00040C04);
+   WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x000001c4);
+   WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000003);
+   WriteReg_32(DBSC_V3M_DBSCHRW1,0x001a0080);
+   WriteReg_32(DBSC_V3M_DBDFICNT0,0x00000010);
+
+   WriteReg_32(DBSC_V3M_DBPDLK0,0X0000A55A);
+   WriteReg_32(DBSC_V3M_DBCMD,0x01000001);
+   WriteReg_32(DBSC_V3M_DBCMD,0x08000000);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X80010000);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000008);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X000B8000);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058904);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000091);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000095);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6B);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000099);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024641E);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010073);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0C058900);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0780C700);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007);
+   while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000004);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X08C0C170);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000022);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X1000040B);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000023);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X2D9C0B66);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000024);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X2A88C400);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000025);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X30005200);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000026);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0014A9C9);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000027);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000D70);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000028);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000004);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000029);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000018);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003047);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000020);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X00181884);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000001A);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X13C03C10);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A7);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A8);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A9);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C7);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C8);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C9);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E7);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E8);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E9);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000107);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000108);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000109);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010181);
+   WriteReg_32(DBSC_V3M_DBCMD,0x08000001);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010601);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+
+   for (uint32_t i = 0; i<4; i++)
+   {
+      WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1 + i*0x20);
+      RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8;
+      WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4 + i*0x20);
+      RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ;
+      WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3 + i*0x20);
+      RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ;
+      if ( RegVal_R6 > 0 )
+      {
+         WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;
+
+         WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
+         WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7+1)&0X00000007) | RegVal_R2);
+         WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;
+         WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
+         WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R6);
+      } else 
+      {
+         WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;
+         WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
+         WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R7);
+
+         WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;
+         WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
+         WriteReg_32(DBSC_V3M_DBPDRGD0,(((RegVal_R5<<1) + RegVal_R6 ) & 0X000000FF )| RegVal_R2);
+      }
+   }
+
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00A0);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010801);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00B8);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0001F001);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003087);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010401);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+
+   for (uint32_t i = 0; i < 4; i++)
+   {
+	   WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B1 + i * 0x20);
+	   RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8;
+	   WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B4 + i * 0x20);
+	   RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF);
+
+	   WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B3 + i * 0x20);
+	   RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007);
+	   RegVal_R12 = (RegVal_R5 >> 2);
+	   if (RegVal_R6 - RegVal_R12 > 0)
+	   {
+		   WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
+		   RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8);
+
+		   WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
+		   WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R7 + 1) & 0X00000007) | RegVal_R2);
+		   WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
+		   RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00);
+
+		   WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
+		   WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 - RegVal_R12) & 0X000000FF) | RegVal_R2);
+	   }
+	   else
+	   {
+		   WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
+		   RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8);
+		   WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
+		   WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal_R7 & 0X00000007) | RegVal_R2);
+		   WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
+		   RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00);
+		   WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
+		   WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 + RegVal_R5 + (RegVal_R5 >> 1) + RegVal_R12) & 0X000000FF) | RegVal_R2);
+	   }
+   }
+
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X00015001);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0380C700);
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007);
+   while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) != 0 );
+   WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021);
+   WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024643E);
+
+   WriteReg_32(DBSC_V3M_DBBUS0CNF1,0x00000000);
+   WriteReg_32(DBSC_V3M_DBBUS0CNF0,0x00010001);
+   WriteReg_32(DBSC_V3M_DBCALCNF,0x0100200E);
+   WriteReg_32(DBSC_V3M_DBRFCNF1,0x00081860);
+   WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000);
+   WriteReg_32(DBSC_V3M_DBDFICUPDCNF,0x40100001);
+   WriteReg_32(DBSC_V3M_DBRFEN,0x00000001);
+   WriteReg_32(DBSC_V3M_DBACEN,0x00000001);
+   WriteReg_32(DBSC_V3M_DBPDLK0,0X00000000);
+   WriteReg_32(0xE67F0024, 0x00000001);
+   WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000);
+
+   return 1;
+}
+
+int32_t InitDram(void)
+{
+	return init_ddr_v3m1600() ? INITDRAM_OK : INITDRAM_NG;
+}
diff --git a/plat/renesas/rcar/ddr/ddr_a/ddr_init_v3m.h b/plat/renesas/rcar/ddr/ddr_a/ddr_init_v3m.h
new file mode 100644
index 0000000..59db5f6
--- /dev/null
+++ b/plat/renesas/rcar/ddr/ddr_a/ddr_init_v3m.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2015-2016, Renesas Electronics Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *
+ *   - Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *
+ *   - Neither the name of Renesas nor the names of its contributors may be
+ *     used to endorse or promote products derived from this software without
+ *     specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef	__DDR_INIT_V3M__
+#define	__DDR_INIT_V3M__
+
+extern void init_ddr_v3m1600(void);
+extern int32_t InitDram(void);
+
+#endif /* BOOT_INIT_DRAM_V3M__ */
diff --git a/plat/renesas/rcar/drivers/board/board.c b/plat/renesas/rcar/drivers/board/board.c
index 4e3a21a..8f93b36 100644
--- a/plat/renesas/rcar/drivers/board/board.c
+++ b/plat/renesas/rcar/drivers/board/board.c
@@ -15,6 +15,8 @@
 #ifndef BOARD_DEFAULT
 #if (RCAR_LSI == RCAR_E3)
 #define BOARD_DEFAULT		(BOARD_EBISU << BOARD_CODE_SHIFT)
+#elif (RCAR_LSI == RCAR_V3M)
+#define BOARD_DEFAULT		(BOARD_UNKNOWN << BOARD_CODE_SHIFT)
 #else  /* (RCAR_LSI == RCAR_E3) */
 #define BOARD_DEFAULT		(BOARD_SALVATOR_X << BOARD_CODE_SHIFT)
 #endif /* (RCAR_LSI == RCAR_E3) */
diff --git a/plat/renesas/rcar/drivers/rom/rom_api.c b/plat/renesas/rcar/drivers/rom/rom_api.c
index 876e7cd..c683fc8 100644
--- a/plat/renesas/rcar/drivers/rom/rom_api.c
+++ b/plat/renesas/rcar/drivers/rom/rom_api.c
@@ -21,8 +21,10 @@ static uint32_t get_table_index(void);
 #define OLD_API_TABLE1	(0U)	/* H3 Ver.1.0/Ver.1.1 */
 #define OLD_API_TABLE2	(1U)	/* H3 Ver.2.0 */
 #define OLD_API_TABLE3	(2U)	/* M3 Ver.1.0 */
-#define NEW_API_TABLE	(3U)	/* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3 */
-#define API_TABLE_MAX	(4U)	/* table max */
+#define NEW_API_TABLE	(3U)	/* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3, */
+				/* V3M WS2.0 */
+#define NEW_API_TABLE2	(4U)	/* V3M WS1.0 */
+#define API_TABLE_MAX	(5U)	/* table max */
 
 
 
@@ -35,7 +37,9 @@ uint32_t ROM_SecureBootAPI( uint32_t *pKeyCert,
 		0xEB10DD64U,	/* H3 Ver.1.0/Ver.1.1 */
 		0xEB116ED4U,	/* H3 Ver.2.0 */
 		0xEB1102FCU,	/* M3 Ver.1.0 */
-		0xEB100180U	/* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3 */
+		0xEB100180U,	/* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3, */
+				/* V3M WS2.0 */
+		0xEB110128U,	/* V3M WS1.0 */
 	};
 
 	ROM_SECURE_BOOT_API func;
@@ -55,7 +59,9 @@ uint32_t ROM_GetLcs(uint32_t *pLcs)
 		0xEB10DFE0U,	/* H3 Ver.1.0/Ver.1.1 */
 		0xEB117150U,	/* H3 Ver.2.0 */
 		0xEB110578U,	/* M3 Ver.1.0 */
-		0xEB10018CU	/* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3 */
+		0xEB10018CU,	/* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3, */
+				/* V3M WS2.0 */
+		0xEB1103A4U,	/* V3M WS1.0 */
 	};
 
 	ROM_GETLCS_API func;
@@ -96,6 +102,13 @@ static uint32_t get_table_index(void)
 			index = NEW_API_TABLE;	/* M3 Ver.1.1 or later */
 		}
 		break;
+	case RCAR_PRODUCT_V3M:
+		if (cut_ver == RCAR_CUT_VER10) {
+			index = NEW_API_TABLE2;	/* V3M WS1.0 */
+		} else {
+			index = NEW_API_TABLE;	/* V3M WS2.0 or later */
+		}
+		break;
 	default:
 		index = NEW_API_TABLE;		/* M3N and E3 */
 		break;
diff --git a/plat/renesas/rcar/drivers/scif/scif.S b/plat/renesas/rcar/drivers/scif/scif.S
index 4178848..2b0bae5 100644
--- a/plat/renesas/rcar/drivers/scif/scif.S
+++ b/plat/renesas/rcar/drivers/scif/scif.S
@@ -17,14 +17,30 @@
 
 /* module stop */
 #define	CPG_BASE		(0xE6150000)
+#define	CPG_SMSTPCR2		(0x0138)
 #define	CPG_SMSTPCR3		(0x013C)
+#define CPG_MSTPSR2		(0x0040)
 #define CPG_MSTPSR3		(0x0048)
+#define	MSTP207			(1 << 7)
 #define	MSTP310			(1 << 10)
 #define	CPG_CPGWPR		(0x0900)
 
-/* SCIF2 */
+/* SCIF */
+#define	SCIF0_BASE		(0xE6E60000)	/* SCIF-0 base address */
 #define	SCIF2_BASE		(0xE6E88000)	/* SCIF-2 base address */
 
+#if RCAR_LSI == RCAR_V3M	/* V3M */
+#define SCIF_BASE		SCIF0_BASE
+#define CPG_SMSTPCR		CPG_SMSTPCR2
+#define CPG_MSTPSR		CPG_MSTPSR2
+#define MSTP			MSTP207
+#else
+#define SCIF_BASE		SCIF2_BASE
+#define CPG_SMSTPCR		CPG_SMSTPCR3
+#define CPG_MSTPSR		CPG_MSTPSR3
+#define MSTP			MSTP310
+#endif
+
 #define	SCIF_SCSMR		(0x00)		/* Serial mode register */
 #define	SCIF_SCBRR		(0x04)		/* Bit rate register */
 #define	SCIF_SCSCR		(0x08)		/* Serial control register */
@@ -147,17 +163,17 @@ endfunc console_init
 	 */
 func console_core_init
 	ldr	x0, =CPG_BASE
-	ldr	w1, [x0, #CPG_SMSTPCR3]
-	and	w1, w1, #~MSTP310		/* MSTP310=0 */
+	ldr	w1, [x0, #CPG_SMSTPCR]
+	and	w1, w1, #~MSTP
 	mvn	w2, w1
 	str	w2, [x0, #CPG_CPGWPR]
-	str	w1, [x0, #CPG_SMSTPCR3]
+	str	w1, [x0, #CPG_SMSTPCR]
 5:
-	ldr w1, [x0, #CPG_MSTPSR3]
-	and w1, w1, #MSTP310
+	ldr w1, [x0, #CPG_MSTPSR]
+	and w1, w1, #MSTP
 	cbnz w1, 5b
 
-	ldr	x0, =SCIF2_BASE
+	ldr	x0, =SCIF_BASE
 	/* Clear bits TE and RE in SCSCR to 0 */
 	mov	w1, #(SCSCR_TE_DIS + SCSCR_RE_DIS)	/* TE=0,RE=0 */
 	strh	w1, [x0, #SCIF_SCSCR]
@@ -256,7 +272,7 @@ endfunc console_putc
 	 * --------------------------------------------------------
 	 */
 func console_core_putc
-	ldr	x1, =SCIF2_BASE
+	ldr	x1, =SCIF_BASE
 	cmp	w0, #0xA
 	/* Prepend '\r' to '\n' */
 	bne	2f
@@ -307,7 +323,7 @@ endfunc console_getc
 	 * ---------------------------------------------
 	 */
 func console_flush
-	ldr	x0, =SCIF2_BASE
+	ldr	x0, =SCIF_BASE
 1:
 	/* Check TEND flag */
 	ldrh	w1, [x0, #SCIF_SCFSR]
@@ -315,7 +331,7 @@ func console_flush
 	cmp	w1, #SCFSR_TEND_TRANS_END
 	bne	1b
 
-	ldr	x0, =SCIF2_BASE
+	ldr	x0, =SCIF_BASE
 	ldrh	w1, [x0, #SCIF_SCSCR]
 	and	w1, w1, #~(SCSCR_TE_EN + SCSCR_RE_EN)	/* TE=0,RE=0 */
 	strh	w1, [x0, #SCIF_SCSCR]
diff --git a/plat/renesas/rcar/include/bl2_dma_register.h b/plat/renesas/rcar/include/bl2_dma_register.h
index de25dfc..f359156 100644
--- a/plat/renesas/rcar/include/bl2_dma_register.h
+++ b/plat/renesas/rcar/include/bl2_dma_register.h
@@ -7,7 +7,11 @@
 #ifndef BL2_DMA_REGISTER_H__
 #define BL2_DMA_REGISTER_H__
 
+#if RCAR_LSI == RCAR_V3M	/* V3M */
+#define	DMACH	16	/* DMA CH setting (0/16/32) */
+#else
 #define	DMACH	0	/* DMA CH setting (0/16/32) */
+#endif
 
 #if (DMACH==0)		/* SYS-DMAC0 (CH0) */
 #define SYS_DMAC_BIT	((uint32_t)1U << 19U)
diff --git a/plat/renesas/rcar/include/platform_def.h b/plat/renesas/rcar/include/platform_def.h
index 2194e65..e9da655 100644
--- a/plat/renesas/rcar/include/platform_def.h
+++ b/plat/renesas/rcar/include/platform_def.h
@@ -104,18 +104,21 @@
  * size plus a little space for growth.
  */
 #define RCAR_SYSRAM_BASE		U(0xE6300000)
-#if RCAR_LSI == RCAR_E3
-#define BL2_LIMIT			U(0xE6320000)
-#else  /* RCAR_LSI == RCAR_E3 */
-#define BL2_LIMIT			U(0xE6360000)
-#endif /* RCAR_LSI == RCAR_E3 */
 
+#if RCAR_LSI == RCAR_V3M
+#define BL2_BASE			U(0xE6344000)
+#define BL2_LIMIT			U(0xE6360000)
+#define BL2_IMAGE_LIMIT			U(0xE636E800)
+#elif RCAR_LSI == RCAR_E3
 #define BL2_BASE			U(0xE6304000)
-#if RCAR_LSI == RCAR_E3
+#define BL2_LIMIT			U(0xE6320000)
 #define BL2_IMAGE_LIMIT			U(0xE6318000)
-#else  /* RCAR_LSI == RCAR_E3 */
+#else
+#define BL2_BASE			U(0xE6304000)
+#define BL2_LIMIT			U(0xE6360000)
 #define BL2_IMAGE_LIMIT			U(0xE632E800)
-#endif /* RCAR_LSI == RCAR_E3 */
+#endif
+
 #define RCAR_SYSRAM_SIZE		(BL2_BASE - RCAR_SYSRAM_BASE)
 
 /*******************************************************************************
diff --git a/plat/renesas/rcar/pfc/V3M/pfc_init_v3m.c b/plat/renesas/rcar/pfc/V3M/pfc_init_v3m.c
new file mode 100644
index 0000000..5aa2303
--- /dev/null
+++ b/plat/renesas/rcar/pfc/V3M/pfc_init_v3m.c
@@ -0,0 +1,1077 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *
+ *   - Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *
+ *   - Neither the name of Renesas nor the names of its contributors may be
+ *     used to endorse or promote products derived from this software without
+ *     specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>		/* for uint32_t */
+#include <mmio.h>
+#include "bl2_cpg_init.h"
+#include "pfc_init_v3m.h"
+#include "rcar_def.h"
+#include "rcar_private.h"
+
+#define	RST_MODEMR		0xE6160060		// Mode Monitor Register
+
+/* GPIO base address */
+#define	GPIO_BASE		(0xE6050000U)
+
+/* GPIO registers */
+#define	GPIO_IOINTSEL0		(GPIO_BASE + 0x0000U)
+#define	GPIO_INOUTSEL0		(GPIO_BASE + 0x0004U)
+#define	GPIO_OUTDT0			(GPIO_BASE + 0x0008U)
+#define	GPIO_INDT0			(GPIO_BASE + 0x000CU)
+#define	GPIO_INTDT0			(GPIO_BASE + 0x0010U)
+#define	GPIO_INTCLR0		(GPIO_BASE + 0x0014U)
+#define	GPIO_INTMSK0		(GPIO_BASE + 0x0018U)
+#define	GPIO_MSKCLR0		(GPIO_BASE + 0x001CU)
+#define	GPIO_POSNEG0		(GPIO_BASE + 0x0020U)
+#define	GPIO_EDGLEVEL0		(GPIO_BASE + 0x0024U)
+#define	GPIO_FILONOFF0		(GPIO_BASE + 0x0028U)
+#define	GPIO_INTMSKS0		(GPIO_BASE + 0x0038U)
+#define	GPIO_MSKCLRS0		(GPIO_BASE + 0x003CU)
+#define	GPIO_OUTDTSEL0		(GPIO_BASE + 0x0040U)
+#define	GPIO_OUTDTH0		(GPIO_BASE + 0x0044U)
+#define	GPIO_OUTDTL0		(GPIO_BASE + 0x0048U)
+#define	GPIO_BOTHEDGE0		(GPIO_BASE + 0x004CU)
+#define	GPIO_IOINTSEL1		(GPIO_BASE + 0x1000U)
+#define	GPIO_INOUTSEL1		(GPIO_BASE + 0x1004U)
+#define	GPIO_OUTDT1			(GPIO_BASE + 0x1008U)
+#define	GPIO_INDT1			(GPIO_BASE + 0x100CU)
+#define	GPIO_INTDT1			(GPIO_BASE + 0x1010U)
+#define	GPIO_INTCLR1		(GPIO_BASE + 0x1014U)
+#define	GPIO_INTMSK1		(GPIO_BASE + 0x1018U)
+#define	GPIO_MSKCLR1		(GPIO_BASE + 0x101CU)
+#define	GPIO_POSNEG1		(GPIO_BASE + 0x1020U)
+#define	GPIO_EDGLEVEL1		(GPIO_BASE + 0x1024U)
+#define	GPIO_FILONOFF1		(GPIO_BASE + 0x1028U)
+#define	GPIO_INTMSKS1		(GPIO_BASE + 0x1038U)
+#define	GPIO_MSKCLRS1		(GPIO_BASE + 0x103CU)
+#define	GPIO_OUTDTSEL1		(GPIO_BASE + 0x1040U)
+#define	GPIO_OUTDTH1		(GPIO_BASE + 0x1044U)
+#define	GPIO_OUTDTL1		(GPIO_BASE + 0x1048U)
+#define	GPIO_BOTHEDGE1		(GPIO_BASE + 0x104CU)
+#define	GPIO_IOINTSEL2		(GPIO_BASE + 0x2000U)
+#define	GPIO_INOUTSEL2		(GPIO_BASE + 0x2004U)
+#define	GPIO_OUTDT2			(GPIO_BASE + 0x2008U)
+#define	GPIO_INDT2			(GPIO_BASE + 0x200CU)
+#define	GPIO_INTDT2			(GPIO_BASE + 0x2010U)
+#define	GPIO_INTCLR2		(GPIO_BASE + 0x2014U)
+#define	GPIO_INTMSK2		(GPIO_BASE + 0x2018U)
+#define	GPIO_MSKCLR2		(GPIO_BASE + 0x201CU)
+#define	GPIO_POSNEG2		(GPIO_BASE + 0x2020U)
+#define	GPIO_EDGLEVEL2		(GPIO_BASE + 0x2024U)
+#define	GPIO_FILONOFF2		(GPIO_BASE + 0x2028U)
+#define	GPIO_INTMSKS2		(GPIO_BASE + 0x2038U)
+#define	GPIO_MSKCLRS2		(GPIO_BASE + 0x203CU)
+#define	GPIO_OUTDTSEL2		(GPIO_BASE + 0x2040U)
+#define	GPIO_OUTDTH2		(GPIO_BASE + 0x2044U)
+#define	GPIO_OUTDTL2		(GPIO_BASE + 0x2048U)
+#define	GPIO_BOTHEDGE2		(GPIO_BASE + 0x204CU)
+#define	GPIO_IOINTSEL3		(GPIO_BASE + 0x3000U)
+#define	GPIO_INOUTSEL3		(GPIO_BASE + 0x3004U)
+#define	GPIO_OUTDT3			(GPIO_BASE + 0x3008U)
+#define	GPIO_INDT3			(GPIO_BASE + 0x300CU)
+#define	GPIO_INTDT3			(GPIO_BASE + 0x3010U)
+#define	GPIO_INTCLR3		(GPIO_BASE + 0x3014U)
+#define	GPIO_INTMSK3		(GPIO_BASE + 0x3018U)
+#define	GPIO_MSKCLR3		(GPIO_BASE + 0x301CU)
+#define	GPIO_POSNEG3		(GPIO_BASE + 0x3020U)
+#define	GPIO_EDGLEVEL3		(GPIO_BASE + 0x3024U)
+#define	GPIO_FILONOFF3		(GPIO_BASE + 0x3028U)
+#define	GPIO_INTMSKS3		(GPIO_BASE + 0x3038U)
+#define	GPIO_MSKCLRS3		(GPIO_BASE + 0x303CU)
+#define	GPIO_OUTDTSEL3		(GPIO_BASE + 0x3040U)
+#define	GPIO_OUTDTH3		(GPIO_BASE + 0x3044U)
+#define	GPIO_OUTDTL3		(GPIO_BASE + 0x3048U)
+#define	GPIO_BOTHEDGE3		(GPIO_BASE + 0x304CU)
+#define	GPIO_IOINTSEL4		(GPIO_BASE + 0x4000U)
+#define	GPIO_INOUTSEL4		(GPIO_BASE + 0x4004U)
+#define	GPIO_OUTDT4			(GPIO_BASE + 0x4008U)
+#define	GPIO_INDT4			(GPIO_BASE + 0x400CU)
+#define	GPIO_INTDT4			(GPIO_BASE + 0x4010U)
+#define	GPIO_INTCLR4		(GPIO_BASE + 0x4014U)
+#define	GPIO_INTMSK4		(GPIO_BASE + 0x4018U)
+#define	GPIO_MSKCLR4		(GPIO_BASE + 0x401CU)
+#define	GPIO_POSNEG4		(GPIO_BASE + 0x4020U)
+#define	GPIO_EDGLEVEL4		(GPIO_BASE + 0x4024U)
+#define	GPIO_FILONOFF4		(GPIO_BASE + 0x4028U)
+#define	GPIO_INTMSKS4		(GPIO_BASE + 0x4038U)
+#define	GPIO_MSKCLRS4		(GPIO_BASE + 0x403CU)
+#define	GPIO_OUTDTSEL4		(GPIO_BASE + 0x4040U)
+#define	GPIO_OUTDTH4		(GPIO_BASE + 0x4044U)
+#define	GPIO_OUTDTL4		(GPIO_BASE + 0x4048U)
+#define	GPIO_BOTHEDGE4		(GPIO_BASE + 0x404CU)
+#define	GPIO_IOINTSEL5		(GPIO_BASE + 0x5000U)
+#define	GPIO_INOUTSEL5		(GPIO_BASE + 0x5004U)
+#define	GPIO_OUTDT5			(GPIO_BASE + 0x5008U)
+#define	GPIO_INDT5			(GPIO_BASE + 0x500CU)
+#define	GPIO_INTDT5			(GPIO_BASE + 0x5010U)
+#define	GPIO_INTCLR5		(GPIO_BASE + 0x5014U)
+#define	GPIO_INTMSK5		(GPIO_BASE + 0x5018U)
+#define	GPIO_MSKCLR5		(GPIO_BASE + 0x501CU)
+#define	GPIO_POSNEG5		(GPIO_BASE + 0x5020U)
+#define	GPIO_EDGLEVEL5		(GPIO_BASE + 0x5024U)
+#define	GPIO_FILONOFF5		(GPIO_BASE + 0x5028U)
+#define	GPIO_INTMSKS5		(GPIO_BASE + 0x5038U)
+#define	GPIO_MSKCLRS5		(GPIO_BASE + 0x503CU)
+#define	GPIO_OUTDTSEL5		(GPIO_BASE + 0x5040U)
+#define	GPIO_OUTDTH5		(GPIO_BASE + 0x5044U)
+#define	GPIO_OUTDTL5		(GPIO_BASE + 0x5048U)
+#define	GPIO_BOTHEDGE5		(GPIO_BASE + 0x504CU)
+
+/* Pin functon base address */
+#define	PFC_BASE		(0xE6060000U)
+
+/* Pin functon registers */
+#define	PFC_PMMR		(PFC_BASE + 0x0000U)
+#define PFC_GPSR0		(PFC_BASE + 0x0100U)
+#define PFC_GPSR1		(PFC_BASE + 0x0104U)
+#define PFC_GPSR2		(PFC_BASE + 0x0108U)
+#define PFC_GPSR3		(PFC_BASE + 0x010CU)
+#define PFC_GPSR4		(PFC_BASE + 0x0110U)
+#define	PFC_GPSR5		(PFC_BASE + 0x0114U)
+#define	PFC_IPSR0		(PFC_BASE + 0x0200U)
+#define	PFC_IPSR1		(PFC_BASE + 0x0204U)
+#define	PFC_IPSR2		(PFC_BASE + 0x0208U)
+#define	PFC_IPSR3		(PFC_BASE + 0x020CU)
+#define	PFC_IPSR4		(PFC_BASE + 0x0210U)
+#define	PFC_IPSR5		(PFC_BASE + 0x0214U)
+#define	PFC_IPSR6		(PFC_BASE + 0x0218U)
+#define	PFC_IPSR7		(PFC_BASE + 0x021CU)
+#define	PFC_IPSR8		(PFC_BASE + 0x0220U)
+#define	PFC_IOCTRL30	(PFC_BASE + 0x0380U)
+#define	PFC_IOCTRL31	(PFC_BASE + 0x0384U)
+#define	PFC_IOCTRL32	(PFC_BASE + 0x0388U)
+#define	PFC_IOCTRL40	(PFC_BASE + 0x03C0U)
+#define	PFC_PUEN0		(PFC_BASE + 0x0400U)
+#define	PFC_PUEN1		(PFC_BASE + 0x0404U)
+#define	PFC_PUEN2		(PFC_BASE + 0x0408U)
+#define	PFC_PUEN3		(PFC_BASE + 0x040CU)
+#define	PFC_PUD0		(PFC_BASE + 0x0440U)
+#define	PFC_PUD1		(PFC_BASE + 0x0444U)
+#define	PFC_PUD2		(PFC_BASE + 0x0448U)
+#define	PFC_PUD3		(PFC_BASE + 0x044CU)
+#define	PFC_MOD_SEL0	(PFC_BASE + 0x0500U)
+
+/* Pin functon bit */
+#define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE			((uint32_t)1U << 21U)
+#define GPSR0_DU_EXVSYNC_DU_VSYNC					((uint32_t)1U << 20U)
+#define GPSR0_DU_EXHSYNC_DU_HSYNC					((uint32_t)1U << 19U)
+#define GPSR0_DU_DOTCLKOUT							((uint32_t)1U << 18U)
+#define GPSR0_DU_DB7								((uint32_t)1U << 17U)
+#define GPSR0_DU_DB6								((uint32_t)1U << 16U)
+#define GPSR0_DU_DB5								((uint32_t)1U << 15U)
+#define GPSR0_DU_DB4								((uint32_t)1U << 14U)
+#define GPSR0_DU_DB3								((uint32_t)1U << 13U)
+#define GPSR0_DU_DB2								((uint32_t)1U << 12U)
+#define GPSR0_DU_DG7								((uint32_t)1U << 11U)
+#define GPSR0_DU_DG6								((uint32_t)1U << 10U)
+#define GPSR0_DU_DG5								((uint32_t)1U << 9U)
+#define GPSR0_DU_DG4								((uint32_t)1U << 8U)
+#define GPSR0_DU_DG3								((uint32_t)1U << 7U)
+#define GPSR0_DU_DG2								((uint32_t)1U << 6U)
+#define GPSR0_DU_DR7								((uint32_t)1U << 5U)
+#define GPSR0_DU_DR6								((uint32_t)1U << 4U)
+#define GPSR0_DU_DR5								((uint32_t)1U << 3U)
+#define GPSR0_DU_DR4								((uint32_t)1U << 2U)
+#define GPSR0_DU_DR3								((uint32_t)1U << 1U)
+#define GPSR0_DU_DR2								((uint32_t)1U << 0U)
+
+#define GPSR1_DIGRF_CLKOUT							((uint32_t)1U << 27U)
+#define GPSR1_DIGRF_CLKIN							((uint32_t)1U << 26U)
+#define GPSR1_CANFD_CLK								((uint32_t)1U << 25U)
+#define GPSR1_CANFD1_RX								((uint32_t)1U << 24U)
+#define GPSR1_CANFD1_TX								((uint32_t)1U << 23U)
+#define GPSR1_CANFD0_RX								((uint32_t)1U << 22U)
+#define GPSR1_CANFD0_TX								((uint32_t)1U << 21U)
+#define GPSR1_AVB0_AVTP_CAPTURE						((uint32_t)1U << 20U)
+#define GPSR1_AVB0_AVTP_MATCH						((uint32_t)1U << 19U)
+#define GPSR1_AVB0_LINK								((uint32_t)1U << 18U)
+#define GPSR1_AVB0_PHY_INT							((uint32_t)1U << 17U)
+#define GPSR1_AVB0_MAGIC							((uint32_t)1U << 16U)
+#define GPSR1_AVB0_MDC								((uint32_t)1U << 15U)
+#define GPSR1_AVB0_MDIO								((uint32_t)1U << 14U)
+#define GPSR1_AVB0_TXCREFCLK						((uint32_t)1U << 13U)
+#define GPSR1_AVB0_TD3								((uint32_t)1U << 12U)
+#define GPSR1_AVB0_TD2								((uint32_t)1U << 11U)
+#define GPSR1_AVB0_TD1								((uint32_t)1U << 10U)
+#define GPSR1_AVB0_TD0								((uint32_t)1U << 9U)
+#define GPSR1_AVB0_TXC								((uint32_t)1U << 8U)
+#define GPSR1_AVB0_TX_CTL							((uint32_t)1U << 7U)
+#define GPSR1_AVB0_RD3								((uint32_t)1U << 6U)
+#define GPSR1_AVB0_RD2								((uint32_t)1U << 5U)
+#define GPSR1_AVB0_RD1								((uint32_t)1U << 4U)
+#define GPSR1_AVB0_RD0								((uint32_t)1U << 3U)
+#define GPSR1_AVB0_RXC								((uint32_t)1U << 2U)
+#define GPSR1_AVB0_RX_CTL							((uint32_t)1U << 1U)
+#define GPSR1_IRQ0									((uint32_t)1U << 0U)
+
+#define GPSR2_VI0_FIELD								((uint32_t)1U << 16U)
+#define GPSR2_VI0_DATA11							((uint32_t)1U << 15U)
+#define GPSR2_VI0_DATA10							((uint32_t)1U << 14U)
+#define GPSR2_VI0_DATA9								((uint32_t)1U << 13U)
+#define GPSR2_VI0_DATA8								((uint32_t)1U << 12U)
+#define GPSR2_VI0_DATA7								((uint32_t)1U << 11U)
+#define GPSR2_VI0_DATA6								((uint32_t)1U << 10U)
+#define GPSR2_VI0_DATA5								((uint32_t)1U << 9U)
+#define GPSR2_VI0_DATA4								((uint32_t)1U << 8U)
+#define GPSR2_VI0_DATA3								((uint32_t)1U << 7U)
+#define GPSR2_VI0_DATA2								((uint32_t)1U << 6U)
+#define GPSR2_VI0_DATA1								((uint32_t)1U << 5U)
+#define GPSR2_VI0_DATA0								((uint32_t)1U << 4U)
+#define GPSR2_VI0_VSYNC_N							((uint32_t)1U << 3U)
+#define GPSR2_VI0_HSYNC_N							((uint32_t)1U << 2U)
+#define GPSR2_VI0_CLKENB							((uint32_t)1U << 1U)
+#define GPSR2_VI0_CLK								((uint32_t)1U << 0U)
+
+#define GPSR3_VI1_FIELD								((uint32_t)1U << 16U)
+#define GPSR3_VI1_DATA11							((uint32_t)1U << 15U)
+#define GPSR3_VI1_DATA10							((uint32_t)1U << 14U)
+#define GPSR3_VI1_DATA9								((uint32_t)1U << 13U)
+#define GPSR3_VI1_DATA8								((uint32_t)1U << 12U)
+#define GPSR3_VI1_DATA7								((uint32_t)1U << 11U)
+#define GPSR3_VI1_DATA6								((uint32_t)1U << 10U)
+#define GPSR3_VI1_DATA5								((uint32_t)1U << 9U)
+#define GPSR3_VI1_DATA4								((uint32_t)1U << 8U)
+#define GPSR3_VI1_DATA3								((uint32_t)1U << 7U)
+#define GPSR3_VI1_DATA2								((uint32_t)1U << 6U)
+#define GPSR3_VI1_DATA1								((uint32_t)1U << 5U)
+#define GPSR3_VI1_DATA0								((uint32_t)1U << 4U)
+#define GPSR3_VI1_VSYNC_N							((uint32_t)1U << 3U)
+#define GPSR3_VI1_HSYNC_N							((uint32_t)1U << 2U)
+#define GPSR3_VI1_CLKENB							((uint32_t)1U << 1U)
+#define GPSR3_VI1_CLK								((uint32_t)1U << 0U)
+
+#define GPSR4_SDA2									((uint32_t)1U << 5U)
+#define GPSR4_SCL2									((uint32_t)1U << 4U)
+#define GPSR4_SDA1									((uint32_t)1U << 3U)
+#define GPSR4_SCL1									((uint32_t)1U << 2U)
+#define GPSR4_SDA0									((uint32_t)1U << 1U)
+#define GPSR4_SCL0									((uint32_t)1U << 0U)
+
+#define GPSR5_RPC_INT_N								((uint32_t)1U << 14U)
+#define GPSR5_RPC_WP_N								((uint32_t)1U << 13U)
+#define GPSR5_RPC_RESET_N							((uint32_t)1U << 12U)
+#define GPSR5_QSPI1_SSL								((uint32_t)1U << 11U)
+#define GPSR5_QSPI1_IO3								((uint32_t)1U << 10U)
+#define GPSR5_QSPI1_IO2								((uint32_t)1U << 9U)
+#define GPSR5_QSPI1_MISO_IO1						((uint32_t)1U << 8U)
+#define GPSR5_QSPI1_MOSI_IO0						((uint32_t)1U << 7U)
+#define GPSR5_QSPI1_SPCLK							((uint32_t)1U << 6U)
+#define GPSR5_QSPI0_SSL								((uint32_t)1U << 5U)
+#define GPSR5_QSPI0_IO3								((uint32_t)1U << 4U)
+#define GPSR5_QSPI0_IO2								((uint32_t)1U << 3U)
+#define GPSR5_QSPI0_MISO_IO1						((uint32_t)1U << 2U)
+#define GPSR5_QSPI0_MOSI_IO0						((uint32_t)1U << 1U)
+#define GPSR5_QSPI0_SPCLK							((uint32_t)1U << 0U)
+
+#define	IPSR_28_FUNC(x)								((uint32_t)(x) << 28U)
+#define	IPSR_24_FUNC(x)								((uint32_t)(x) << 24U)
+#define	IPSR_20_FUNC(x)								((uint32_t)(x) << 20U)
+#define	IPSR_16_FUNC(x)								((uint32_t)(x) << 16U)
+#define	IPSR_12_FUNC(x)								((uint32_t)(x) << 12U)
+#define	IPSR_8_FUNC(x)								((uint32_t)(x) << 8U)
+#define	IPSR_4_FUNC(x)								((uint32_t)(x) << 4U)
+#define	IPSR_0_FUNC(x)								((uint32_t)(x) << 0U)
+
+#define IOCTRL30_POC_VI0_DATA5						((uint32_t)1U << 31U)
+#define IOCTRL30_POC_VI0_DATA4						((uint32_t)1U << 30U)
+#define IOCTRL30_POC_VI0_DATA3						((uint32_t)1U << 29U)
+#define IOCTRL30_POC_VI0_DATA2						((uint32_t)1U << 28U)
+#define IOCTRL30_POC_VI0_DATA1						((uint32_t)1U << 27U)
+#define IOCTRL30_POC_VI0_DATA0						((uint32_t)1U << 26U)
+#define IOCTRL30_POC_VI0_VSYNC_N					((uint32_t)1U << 25U)
+#define IOCTRL30_POC_VI0_HSYNC_N					((uint32_t)1U << 24U)
+#define IOCTRL30_POC_VI0_CLKENB						((uint32_t)1U << 23U)
+#define IOCTRL30_POC_VI0_CLK						((uint32_t)1U << 22U)
+#define IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE		((uint32_t)1U << 21U)
+#define IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC			((uint32_t)1U << 20U)
+#define IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC			((uint32_t)1U << 19U)
+#define IOCTRL30_POC_DU_DOTCLKOUT					((uint32_t)1U << 18U)
+#define IOCTRL30_POC_DU_DB7							((uint32_t)1U << 17U)
+#define IOCTRL30_POC_DU_DB6							((uint32_t)1U << 16U)
+#define IOCTRL30_POC_DU_DB5							((uint32_t)1U << 15U)
+#define IOCTRL30_POC_DU_DB4							((uint32_t)1U << 14U)
+#define IOCTRL30_POC_DU_DB3							((uint32_t)1U << 13U)
+#define IOCTRL30_POC_DU_DB2							((uint32_t)1U << 12U)
+#define IOCTRL30_POC_DU_DG7							((uint32_t)1U << 11U)
+#define IOCTRL30_POC_DU_DG6							((uint32_t)1U << 10U)
+#define IOCTRL30_POC_DU_DG5							((uint32_t)1U << 9U)
+#define IOCTRL30_POC_DU_DG4							((uint32_t)1U << 8U)
+#define IOCTRL30_POC_DU_DG3							((uint32_t)1U << 7U)
+#define IOCTRL30_POC_DU_DG2							((uint32_t)1U << 6U)
+#define IOCTRL30_POC_DU_DR7							((uint32_t)1U << 5U)
+#define IOCTRL30_POC_DU_DR6							((uint32_t)1U << 4U)
+#define IOCTRL30_POC_DU_DR5							((uint32_t)1U << 3U)
+#define IOCTRL30_POC_DU_DR4							((uint32_t)1U << 2U)
+#define IOCTRL30_POC_DU_DR3							((uint32_t)1U << 1U)
+#define IOCTRL30_POC_DU_DR2							((uint32_t)1U << 0U)
+
+#define IOCTRL31_POC_DUMMY_31						((uint32_t)1U << 31U)
+#define IOCTRL31_POC_DUMMY_30						((uint32_t)1U << 30U)
+#define IOCTRL31_POC_DUMMY_29						((uint32_t)1U << 29U)
+#define IOCTRL31_POC_DUMMY_28						((uint32_t)1U << 28U)
+#define IOCTRL31_POC_DUMMY_27						((uint32_t)1U << 27U)
+#define IOCTRL31_POC_DUMMY_26						((uint32_t)1U << 26U)
+#define IOCTRL31_POC_DUMMY_25						((uint32_t)1U << 25U)
+#define IOCTRL31_POC_DUMMY_24						((uint32_t)1U << 24U)
+#define IOCTRL31_POC_VI1_FIELD						((uint32_t)1U << 23U)
+#define IOCTRL31_POC_VI1_DATA11						((uint32_t)1U << 22U)
+#define IOCTRL31_POC_VI1_DATA10						((uint32_t)1U << 21U)
+#define IOCTRL31_POC_VI1_DATA9						((uint32_t)1U << 20U)
+#define IOCTRL31_POC_VI1_DATA8						((uint32_t)1U << 19U)
+#define IOCTRL31_POC_VI1_DATA7						((uint32_t)1U << 18U)
+#define IOCTRL31_POC_VI1_DATA6						((uint32_t)1U << 17U)
+#define IOCTRL31_POC_VI1_DATA5						((uint32_t)1U << 16U)
+#define IOCTRL31_POC_VI1_DATA4						((uint32_t)1U << 15U)
+#define IOCTRL31_POC_VI1_DATA3						((uint32_t)1U << 14U)
+#define IOCTRL31_POC_VI1_DATA2						((uint32_t)1U << 13U)
+#define IOCTRL31_POC_VI1_DATA1						((uint32_t)1U << 12U)
+#define IOCTRL31_POC_VI1_DATA0						((uint32_t)1U << 11U)
+#define IOCTRL31_POC_VI1_VSYNC_N					((uint32_t)1U << 10U)
+#define IOCTRL31_POC_VI1_HSYNC_N					((uint32_t)1U << 9U)
+#define IOCTRL31_POC_VI1_CLKENB						((uint32_t)1U << 8U)
+#define IOCTRL31_POC_VI1_CLK						((uint32_t)1U << 7U)
+#define IOCTRL31_POC_VI0_FIELD						((uint32_t)1U << 6U)
+#define IOCTRL31_POC_VI0_DATA11						((uint32_t)1U << 5U)
+#define IOCTRL31_POC_VI0_DATA10						((uint32_t)1U << 4U)
+#define IOCTRL31_POC_VI0_DATA9						((uint32_t)1U << 3U)
+#define IOCTRL31_POC_VI0_DATA8						((uint32_t)1U << 2U)
+#define IOCTRL31_POC_VI0_DATA7						((uint32_t)1U << 1U)
+#define IOCTRL31_POC_VI0_DATA6						((uint32_t)1U << 0U)
+#define IOCTRL32_POC2_VREF							((uint32_t)1U << 0U)
+#define IOCTRL40_SD0TDSEL1							((uint32_t)1U << 1U)
+#define IOCTRL40_SD0TDSEL0							((uint32_t)1U << 0U)
+
+#define PUEN0_PUEN_VI0_CLK							((uint32_t)1U << 31U)
+#define PUEN0_PUEN_TDI								((uint32_t)1U << 30U)
+#define PUEN0_PUEN_TMS								((uint32_t)1U << 29U)
+#define PUEN0_PUEN_TCK								((uint32_t)1U << 28U)
+#define PUEN0_PUEN_TRST_N							((uint32_t)1U << 27U)
+#define PUEN0_PUEN_IRQ0								((uint32_t)1U << 26U)
+#define PUEN0_PUEN_FSCLKST_N						((uint32_t)1U << 25U)
+#define PUEN0_PUEN_EXTALR							((uint32_t)1U << 24U)
+#define PUEN0_PUEN_PRESETOUT_N						((uint32_t)1U << 23U)
+#define PUEN0_PUEN_DU_DOTCLKIN						((uint32_t)1U << 22U)
+#define PUEN0_PUEN_DU_EXODDF_DU_ODDF_DISP_CDE		((uint32_t)1U << 21U)
+#define PUEN0_PUEN_DU_EXVSYNC_DU_VSYNC				((uint32_t)1U << 20U)
+#define PUEN0_PUEN_DU_EXHSYNC_DU_HSYNC				((uint32_t)1U << 19U)
+#define PUEN0_PUEN_DU_DOTCLKOUT						((uint32_t)1U << 18U)
+#define PUEN0_PUEN_DU_DB7							((uint32_t)1U << 17U)
+#define PUEN0_PUEN_DU_DB6							((uint32_t)1U << 16U)
+#define PUEN0_PUEN_DU_DB5							((uint32_t)1U << 15U)
+#define PUEN0_PUEN_DU_DB4							((uint32_t)1U << 14U)
+#define PUEN0_PUEN_DU_DB3							((uint32_t)1U << 13U)
+#define PUEN0_PUEN_DU_DB2							((uint32_t)1U << 12U)
+#define PUEN0_PUEN_DU_DG7							((uint32_t)1U << 11U)
+#define PUEN0_PUEN_DU_DG6							((uint32_t)1U << 10U)
+#define PUEN0_PUEN_DU_DG5							((uint32_t)1U << 9U)
+#define PUEN0_PUEN_DU_DG4							((uint32_t)1U << 8U)
+#define PUEN0_PUEN_DU_DG3							((uint32_t)1U << 7U)
+#define PUEN0_PUEN_DU_DG2							((uint32_t)1U << 6U)
+#define PUEN0_PUEN_DU_DR7							((uint32_t)1U << 5U)
+#define PUEN0_PUEN_DU_DR6							((uint32_t)1U << 4U)
+#define PUEN0_PUEN_DU_DR5							((uint32_t)1U << 3U)
+#define PUEN0_PUEN_DU_DR4							((uint32_t)1U << 2U)
+#define PUEN0_PUEN_DU_DR3							((uint32_t)1U << 1U)
+#define PUEN0_PUEN_DU_DR2							((uint32_t)1U << 0U)
+
+#define PUEN1_PUEN_VI1_DATA11						((uint32_t)1U << 31U)
+#define PUEN1_PUEN_VI1_DATA10						((uint32_t)1U << 30U)
+#define PUEN1_PUEN_VI1_DATA9						((uint32_t)1U << 29U)
+#define PUEN1_PUEN_VI1_DATA8						((uint32_t)1U << 28U)
+#define PUEN1_PUEN_VI1_DATA7						((uint32_t)1U << 27U)
+#define PUEN1_PUEN_VI1_DATA6						((uint32_t)1U << 26U)
+#define PUEN1_PUEN_VI1_DATA5						((uint32_t)1U << 25U)
+#define PUEN1_PUEN_VI1_DATA4						((uint32_t)1U << 24U)
+#define PUEN1_PUEN_VI1_DATA3						((uint32_t)1U << 23U)
+#define PUEN1_PUEN_VI1_DATA2						((uint32_t)1U << 22U)
+#define PUEN1_PUEN_VI1_DATA1						((uint32_t)1U << 21U)
+#define PUEN1_PUEN_VI1_DATA0						((uint32_t)1U << 20U)
+#define PUEN1_PUEN_VI1_VSYNC_N						((uint32_t)1U << 19U)
+#define PUEN1_PUEN_VI1_HSYNC_N						((uint32_t)1U << 18U)
+#define PUEN1_PUEN_VI1_CLKENB						((uint32_t)1U << 17U)
+#define PUEN1_PUEN_VI1_CLK							((uint32_t)1U << 16U)
+#define PUEN1_PUEN_VI0_FIELD						((uint32_t)1U << 15U)
+#define PUEN1_PUEN_VI0_DATA11						((uint32_t)1U << 14U)
+#define PUEN1_PUEN_VI0_DATA10						((uint32_t)1U << 13U)
+#define PUEN1_PUEN_VI0_DATA9						((uint32_t)1U << 12U)
+#define PUEN1_PUEN_VI0_DATA8						((uint32_t)1U << 11U)
+#define PUEN1_PUEN_VI0_DATA7						((uint32_t)1U << 10U)
+#define PUEN1_PUEN_VI0_DATA6						((uint32_t)1U << 9U)
+#define PUEN1_PUEN_VI0_DATA5						((uint32_t)1U << 8U)
+#define PUEN1_PUEN_VI0_DATA4						((uint32_t)1U << 7U)
+#define PUEN1_PUEN_VI0_DATA3						((uint32_t)1U << 6U)
+#define PUEN1_PUEN_VI0_DATA2						((uint32_t)1U << 5U)
+#define PUEN1_PUEN_VI0_DATA1						((uint32_t)1U << 4U)
+#define PUEN1_PUEN_VI0_DATA0						((uint32_t)1U << 3U)
+#define PUEN1_PUEN_VI0_VSYNC_N						((uint32_t)1U << 2U)
+#define PUEN1_PUEN_VI0_HSYNC_N						((uint32_t)1U << 1U)
+#define PUEN1_PUEN_VI0_CLKENB						((uint32_t)1U << 0U)
+
+#define PUEN2_PUEN_CANFD_CLK						((uint32_t)1U << 31U)
+#define PUEN2_PUEN_CANFD1_RX						((uint32_t)1U << 30U)
+#define PUEN2_PUEN_CANFD1_TX						((uint32_t)1U << 29U)
+#define PUEN2_PUEN_CANFD0_RX						((uint32_t)1U << 28U)
+#define PUEN2_PUEN_CANFD0_TX						((uint32_t)1U << 27U)
+#define PUEN2_PUEN_AVB0_AVTP_CAPTURE				((uint32_t)1U << 26U)
+#define PUEN2_PUEN_AVB0_AVTP_MATCH					((uint32_t)1U << 25U)
+#define PUEN2_PUEN_AVB0_LINK						((uint32_t)1U << 24U)
+#define PUEN2_PUEN_AVB0_PHY_INT						((uint32_t)1U << 23U)
+#define PUEN2_PUEN_AVB0_MAGIC						((uint32_t)1U << 22U)
+#define PUEN2_PUEN_AVB0_MDC							((uint32_t)1U << 21U)
+#define PUEN2_PUEN_AVB0_MDIO						((uint32_t)1U << 20U)
+#define PUEN2_PUEN_AVB0_TXCREFCLK					((uint32_t)1U << 19U)
+#define PUEN2_PUEN_AVB0_TD3							((uint32_t)1U << 18U)
+#define PUEN2_PUEN_AVB0_TD2							((uint32_t)1U << 17U)
+#define PUEN2_PUEN_AVB0_TD1							((uint32_t)1U << 16U)
+#define PUEN2_PUEN_AVB0_TD0							((uint32_t)1U << 15U)
+#define PUEN2_PUEN_AVB0_TXC							((uint32_t)1U << 14U)
+#define PUEN2_PUEN_AVB0_TX_CTL						((uint32_t)1U << 13U)
+#define PUEN2_PUEN_AVB0_RD3							((uint32_t)1U << 12U)
+#define PUEN2_PUEN_AVB0_RD2							((uint32_t)1U << 11U)
+#define PUEN2_PUEN_AVB0_RD1							((uint32_t)1U << 10U)
+#define PUEN2_PUEN_AVB0_RD0							((uint32_t)1U << 9U)
+#define PUEN2_PUEN_AVB0_RXC							((uint32_t)1U << 8U)
+#define PUEN2_PUEN_AVB0_RX_CTL						((uint32_t)1U << 7U)
+#define PUEN2_PUEN_SDA2								((uint32_t)1U << 6U)
+#define PUEN2_PUEN_SCL2								((uint32_t)1U << 5U)
+#define PUEN2_PUEN_SDA1								((uint32_t)1U << 4U)
+#define PUEN2_PUEN_SCL1								((uint32_t)1U << 3U)
+#define PUEN2_PUEN_SDA0								((uint32_t)1U << 2U)
+#define PUEN2_PUEN_SCL0								((uint32_t)1U << 1U)
+#define PUEN2_PUEN_VI1_FIELD						((uint32_t)1U << 0U)
+
+#define PUEN3_PUEN_DIGRF_CLKOUT						((uint32_t)1U << 16U)
+#define PUEN3_PUEN_DIGRF_CLKIN						((uint32_t)1U << 15U)
+#define PUEN3_PUEN_RPC_INT_N						((uint32_t)1U << 14U)
+#define PUEN3_PUEN_RPC_WP_N							((uint32_t)1U << 13U)
+#define PUEN3_PUEN_RPC_RESET_N						((uint32_t)1U << 12U)
+#define PUEN3_PUEN_QSPI1_SSL						((uint32_t)1U << 11U)
+#define PUEN3_PUEN_QSPI1_IO3						((uint32_t)1U << 10U)
+#define PUEN3_PUEN_QSPI1_IO2						((uint32_t)1U << 9U)
+#define PUEN3_PUEN_QSPI1_MISO_IO1					((uint32_t)1U << 8U)
+#define PUEN3_PUEN_QSPI1_MOSI_IO0					((uint32_t)1U << 7U)
+#define PUEN3_PUEN_QSPI1_SPCLK						((uint32_t)1U << 6U)
+#define PUEN3_PUEN_QSPI0_SSL						((uint32_t)1U << 5U)
+#define PUEN3_PUEN_QSPI0_IO3						((uint32_t)1U << 4U)
+#define PUEN3_PUEN_QSPI0_IO2						((uint32_t)1U << 3U)
+#define PUEN3_PUEN_QSPI0_MISO_IO1					((uint32_t)1U << 2U)
+#define PUEN3_PUEN_QSPI0_MOSI_IO0					((uint32_t)1U << 1U)
+#define PUEN3_PUEN_QSPI0_SPCLK						((uint32_t)1U << 0U)
+
+#define PUD0_PUD_VI0_CLK							((uint32_t)1U << 31U)
+#define PUD0_PUD_IRQ0								((uint32_t)1U << 26U)
+#define PUD0_PUD_FSCLKST_N							((uint32_t)1U << 25U)
+#define PUD0_PUD_PRESETOUT_N						((uint32_t)1U << 23U)
+#define PUD0_PUD_DU_EXODDF_DU_ODDF_DISP_CDE			((uint32_t)1U << 21U)
+#define PUD0_PUD_DU_EXVSYNC_DU_VSYNC				((uint32_t)1U << 20U)
+#define PUD0_PUD_DU_EXHSYNC_DU_HSYNC				((uint32_t)1U << 19U)
+#define PUD0_PUD_DU_DOTCLKOUT						((uint32_t)1U << 18U)
+#define PUD0_PUD_DU_DB7								((uint32_t)1U << 17U)
+#define PUD0_PUD_DU_DB6								((uint32_t)1U << 16U)
+#define PUD0_PUD_DU_DB5								((uint32_t)1U << 15U)
+#define PUD0_PUD_DU_DB4								((uint32_t)1U << 14U)
+#define PUD0_PUD_DU_DB3								((uint32_t)1U << 13U)
+#define PUD0_PUD_DU_DB2								((uint32_t)1U << 12U)
+#define PUD0_PUD_DU_DG7								((uint32_t)1U << 11U)
+#define PUD0_PUD_DU_DG6								((uint32_t)1U << 10U)
+#define PUD0_PUD_DU_DG5								((uint32_t)1U << 9U)
+#define PUD0_PUD_DU_DG4								((uint32_t)1U << 8U)
+#define PUD0_PUD_DU_DG3								((uint32_t)1U << 7U)
+#define PUD0_PUD_DU_DG2								((uint32_t)1U << 6U)
+#define PUD0_PUD_DU_DR7								((uint32_t)1U << 5U)
+#define PUD0_PUD_DU_DR6								((uint32_t)1U << 4U)
+#define PUD0_PUD_DU_DR5								((uint32_t)1U << 3U)
+#define PUD0_PUD_DU_DR4								((uint32_t)1U << 2U)
+#define PUD0_PUD_DU_DR3								((uint32_t)1U << 1U)
+#define PUD0_PUD_DU_DR2								((uint32_t)1U << 0U)
+
+#define PUD1_PUD_VI1_DATA11							((uint32_t)1U << 31U)
+#define PUD1_PUD_VI1_DATA10							((uint32_t)1U << 30U)
+#define PUD1_PUD_VI1_DATA9 							((uint32_t)1U << 29U)
+#define PUD1_PUD_VI1_DATA8 							((uint32_t)1U << 28U)
+#define PUD1_PUD_VI1_DATA7 							((uint32_t)1U << 27U)
+#define PUD1_PUD_VI1_DATA6 							((uint32_t)1U << 26U)
+#define PUD1_PUD_VI1_DATA5 							((uint32_t)1U << 25U)
+#define PUD1_PUD_VI1_DATA4 							((uint32_t)1U << 24U)
+#define PUD1_PUD_VI1_DATA3 							((uint32_t)1U << 23U)
+#define PUD1_PUD_VI1_DATA2 							((uint32_t)1U << 22U)
+#define PUD1_PUD_VI1_DATA1 							((uint32_t)1U << 21U)
+#define PUD1_PUD_VI1_DATA0 							((uint32_t)1U << 20U)
+#define PUD1_PUD_VI1_VSYNC_N						((uint32_t)1U << 19U)
+#define PUD1_PUD_VI1_HSYNC_N						((uint32_t)1U << 18U)
+#define PUD1_PUD_VI1_CLKENB							((uint32_t)1U << 17U)
+#define PUD1_PUD_VI1_CLK							((uint32_t)1U << 16U)
+#define PUD1_PUD_VI0_FIELD 							((uint32_t)1U << 15U)
+#define PUD1_PUD_VI0_DATA11							((uint32_t)1U << 14U)
+#define PUD1_PUD_VI0_DATA10							((uint32_t)1U << 13U)
+#define PUD1_PUD_VI0_DATA9 							((uint32_t)1U << 12U)
+#define PUD1_PUD_VI0_DATA8 							((uint32_t)1U << 11U)
+#define PUD1_PUD_VI0_DATA7 							((uint32_t)1U << 10U)
+#define PUD1_PUD_VI0_DATA6 							((uint32_t)1U << 9U)
+#define PUD1_PUD_VI0_DATA5 							((uint32_t)1U << 8U)
+#define PUD1_PUD_VI0_DATA4 							((uint32_t)1U << 7U)
+#define PUD1_PUD_VI0_DATA3 							((uint32_t)1U << 6U)
+#define PUD1_PUD_VI0_DATA2 							((uint32_t)1U << 5U)
+#define PUD1_PUD_VI0_DATA1 							((uint32_t)1U << 4U)
+#define PUD1_PUD_VI0_DATA0 							((uint32_t)1U << 3U)
+#define PUD1_PUD_VI0_VSYNC_N						((uint32_t)1U << 2U)
+#define PUD1_PUD_VI0_HSYNC_N						((uint32_t)1U << 1U)
+#define PUD1_PUD_VI0_CLKENB							((uint32_t)1U << 0U)
+
+#define PUD2_PUD_CANFD_CLK							((uint32_t)1U << 31U)
+#define PUD2_PUD_CANFD1_RX							((uint32_t)1U << 30U)
+#define PUD2_PUD_CANFD1_TX							((uint32_t)1U << 29U)
+#define PUD2_PUD_CANFD0_RX							((uint32_t)1U << 28U)
+#define PUD2_PUD_CANFD0_TX							((uint32_t)1U << 27U)
+#define PUD2_PUD_AVB0_AVTP_CAPTURE					((uint32_t)1U << 26U)
+#define PUD2_PUD_AVB0_AVTP_MATCH					((uint32_t)1U << 25U)
+#define PUD2_PUD_AVB0_LINK							((uint32_t)1U << 24U)
+#define PUD2_PUD_AVB0_PHY_INT						((uint32_t)1U << 23U)
+#define PUD2_PUD_AVB0_MAGIC							((uint32_t)1U << 22U)
+#define PUD2_PUD_AVB0_MDC							((uint32_t)1U << 21U)
+#define PUD2_PUD_AVB0_MDIO							((uint32_t)1U << 20U)
+#define PUD2_PUD_AVB0_TXCREFCLK						((uint32_t)1U << 19U)
+#define PUD2_PUD_AVB0_TD3							((uint32_t)1U << 18U)
+#define PUD2_PUD_AVB0_TD2							((uint32_t)1U << 17U)
+#define PUD2_PUD_AVB0_TD1							((uint32_t)1U << 16U)
+#define PUD2_PUD_AVB0_TD0							((uint32_t)1U << 15U)
+#define PUD2_PUD_AVB0_TXC							((uint32_t)1U << 14U)
+#define PUD2_PUD_AVB0_TX_CTL						((uint32_t)1U << 13U)
+#define PUD2_PUD_AVB0_RD3							((uint32_t)1U << 12U)
+#define PUD2_PUD_AVB0_RD2							((uint32_t)1U << 11U)
+#define PUD2_PUD_AVB0_RD1							((uint32_t)1U << 10U)
+#define PUD2_PUD_AVB0_RD0							((uint32_t)1U << 9U)
+#define PUD2_PUD_AVB0_RXC							((uint32_t)1U << 8U)
+#define PUD2_PUD_AVB0_RX_CTL						((uint32_t)1U << 7U)
+#define PUD2_PUD_SDA2								((uint32_t)1U << 6U)
+#define PUD2_PUD_SCL2								((uint32_t)1U << 5U)
+#define PUD2_PUD_SDA1								((uint32_t)1U << 4U)
+#define PUD2_PUD_SCL1								((uint32_t)1U << 3U)
+#define PUD2_PUD_SDA0								((uint32_t)1U << 2U)
+#define PUD2_PUD_SCL0								((uint32_t)1U << 1U)
+#define PUD2_PUD_VI1_FIELD							((uint32_t)1U << 0U)
+
+#define PUD3_PUD_DIGRF_CLKOUT						((uint32_t)1U << 16U)
+#define PUD3_PUD_DIGRF_CLKIN						((uint32_t)1U << 15U)
+#define PUD3_PUD_RPC_INT_N							((uint32_t)1U << 14U)
+#define PUD3_PUD_RPC_WP_N							((uint32_t)1U << 13U)
+#define PUD3_PUD_RPC_RESET_N						((uint32_t)1U << 12U)
+#define PUD3_PUD_QSPI1_SSL							((uint32_t)1U << 11U)
+#define PUD3_PUD_QSPI1_IO3							((uint32_t)1U << 10U)
+#define PUD3_PUD_QSPI1_IO2							((uint32_t)1U << 9U)
+#define PUD3_PUD_QSPI1_MISO_IO1						((uint32_t)1U << 8U)
+#define PUD3_PUD_QSPI1_MOSI_IO0						((uint32_t)1U << 7U)
+#define PUD3_PUD_QSPI1_SPCLK						((uint32_t)1U << 6U)
+#define PUD3_PUD_QSPI0_SSL							((uint32_t)1U << 5U)
+#define PUD3_PUD_QSPI0_IO3							((uint32_t)1U << 4U)
+#define PUD3_PUD_QSPI0_IO2							((uint32_t)1U << 3U)
+#define PUD3_PUD_QSPI0_MISO_IO1						((uint32_t)1U << 2U)
+#define PUD3_PUD_QSPI0_MOSI_IO0						((uint32_t)1U << 1U)
+#define PUD3_PUD_QSPI0_SPCLK						((uint32_t)1U << 0U)
+
+#define MOD_SEL0_sel_hscif0							((uint32_t)1U << 10U)
+#define MOD_SEL0_sel_scif1							((uint32_t)1U << 9U)
+#define MOD_SEL0_sel_canfd0							((uint32_t)1U << 8U)
+#define MOD_SEL0_sel_pwm4							((uint32_t)1U << 7U)
+#define MOD_SEL0_sel_pwm3							((uint32_t)1U << 6U)
+#define MOD_SEL0_sel_pwm2							((uint32_t)1U << 5U)
+#define MOD_SEL0_sel_pwm1							((uint32_t)1U << 4U)
+#define MOD_SEL0_sel_pwm0							((uint32_t)1U << 3U)
+#define MOD_SEL0_sel_rfso							((uint32_t)1U << 2U)
+#define MOD_SEL0_sel_rsp							((uint32_t)1U << 1U)
+#define MOD_SEL0_sel_tmu							((uint32_t)1U << 0U)
+
+/* SCIF3 Registers for Dummy write */
+#define SCIF3_BASE		(0xE6C50000U)
+#define SCIF3_SCFCR		(SCIF3_BASE + 0x0018U)
+#define SCIF3_SCFDR		(SCIF3_BASE + 0x001CU)
+#define SCFCR_DATA		(0x0000U)
+
+/* Realtime module stop control */
+#define	CPG_BASE		(0xE6150000U)
+#define CPG_MSTPSR0		(CPG_BASE + 0x0030U)
+#define CPG_RMSTPCR0		(CPG_BASE + 0x0110U)
+#define RMSTPCR0_RTDMAC		(0x00200000U)
+
+/* RT-DMAC Registers */
+#define RTDMAC_CH		(0U)		/* choose 0 to 15 */
+
+#define RTDMAC_BASE		(0xFFC10000U)
+#define RTDMAC_RDMOR		(RTDMAC_BASE + 0x0060U)
+#define RTDMAC_RDMCHCLR		(RTDMAC_BASE + 0x0080U)
+#define RTDMAC_RDMSAR(x)	(RTDMAC_BASE + 0x8000U + (0x80U * (x)))
+#define RTDMAC_RDMDAR(x)	(RTDMAC_BASE + 0x8004U + (0x80U * (x)))
+#define RTDMAC_RDMTCR(x)	(RTDMAC_BASE + 0x8008U + (0x80U * (x)))
+#define RTDMAC_RDMCHCR(x)	(RTDMAC_BASE + 0x800CU + (0x80U * (x)))
+#define RTDMAC_RDMCHCRB(x)	(RTDMAC_BASE + 0x801CU + (0x80U * (x)))
+#define RTDMAC_RDMDPBASE(x)	(RTDMAC_BASE + 0x8050U + (0x80U * (x)))
+#define RTDMAC_DESC_BASE	(RTDMAC_BASE + 0xA000U)
+#define RTDMAC_DESC_RDMSAR	(RTDMAC_DESC_BASE + 0x0000U)
+#define RTDMAC_DESC_RDMDAR	(RTDMAC_DESC_BASE + 0x0004U)
+#define RTDMAC_DESC_RDMTCR	(RTDMAC_DESC_BASE + 0x0008U)
+
+#define RDMOR_DME		(0x0001U)	/* DMA Master Enable */
+#define RDMCHCR_DPM_INFINITE	(0x30000000U)	/* Infinite repeat mode */
+#define RDMCHCR_RPT_TCR		(0x02000000U)	/* enable to update TCR */
+#define RDMCHCR_TS_2		(0x00000008U)	/* Word(2byte) units transfer */
+#define RDMCHCR_RS_AUTO		(0x00000400U)	/* Auto request */
+#define RDMCHCR_DE		(0x00000001U)	/* DMA Enable */
+#define RDMCHCRB_DRST		(0x00008000U)	/* Descriptor reset */
+#define RDMCHCRB_SLM_256	(0x00000080U)	/* once in 256 clock cycle */
+#define RDMDPBASE_SEL_EXT	(0x00000001U)	/* External memory use */
+
+static void pfc_reg_write(uint32_t addr, uint32_t data);
+static void StartRtDma0_Descriptor(void);
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+	mmio_write_32(PFC_PMMR, ~data);
+	mmio_write_32((uintptr_t)addr, data);
+}
+
+static void StartRtDma0_Descriptor(void)
+{
+	uint32_t reg;
+
+	/* Module stop clear */
+	while((mmio_read_32(CPG_MSTPSR0) & RMSTPCR0_RTDMAC) != 0U) {
+		reg = mmio_read_32(CPG_RMSTPCR0);
+		reg &= ~RMSTPCR0_RTDMAC;
+		cpg_write(CPG_RMSTPCR0, reg);
+	}
+
+	/* Initialize ch0, Reset Descriptor */
+	mmio_write_32(RTDMAC_RDMCHCLR, ((uint32_t)1U << RTDMAC_CH));
+	mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_DRST);
+
+	/* Enable DMA */
+	mmio_write_16(RTDMAC_RDMOR, RDMOR_DME);
+
+	/* Set first transfer */
+	mmio_write_32(RTDMAC_RDMSAR(RTDMAC_CH), RCAR_PRR);
+	mmio_write_32(RTDMAC_RDMDAR(RTDMAC_CH), SCIF3_SCFDR);
+	mmio_write_32(RTDMAC_RDMTCR(RTDMAC_CH), 0x00000001U);
+
+	/* Set descriptor */
+	mmio_write_32(RTDMAC_DESC_RDMSAR, 0x00000000U);
+	mmio_write_32(RTDMAC_DESC_RDMDAR, 0x00000000U);
+	mmio_write_32(RTDMAC_DESC_RDMTCR, 0x00200000U);
+	mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_SLM_256);
+	mmio_write_32(RTDMAC_RDMDPBASE(RTDMAC_CH), RTDMAC_DESC_BASE
+						 | RDMDPBASE_SEL_EXT);
+
+	/* Set transfer parameter, Start transfer */
+	mmio_write_32(RTDMAC_RDMCHCR(RTDMAC_CH), RDMCHCR_DPM_INFINITE
+					       | RDMCHCR_RPT_TCR
+					       | RDMCHCR_TS_2
+					       | RDMCHCR_RS_AUTO
+					       | RDMCHCR_DE);
+}
+
+void pfc_init_v3m(void)
+{
+	/* Work around for PFC eratta */
+	StartRtDma0_Descriptor();
+
+	// pin function
+	// md[4:1]!=0000
+	/* initialize GPIO/perihperal function select */
+
+	pfc_reg_write(PFC_GPSR0, 0x00000000);
+
+	pfc_reg_write(PFC_GPSR1, GPSR1_CANFD_CLK);
+
+	pfc_reg_write(PFC_GPSR2, 0x00000000);
+
+	pfc_reg_write(PFC_GPSR3, 0x00000000);
+
+	pfc_reg_write(PFC_GPSR4, GPSR4_SDA2
+				   | GPSR4_SCL2);
+	
+	pfc_reg_write(PFC_GPSR5, GPSR5_QSPI1_SSL
+				   | GPSR5_QSPI1_IO3
+				   | GPSR5_QSPI1_IO2
+				   | GPSR5_QSPI1_MISO_IO1
+				   | GPSR5_QSPI1_MOSI_IO0
+				   | GPSR5_QSPI1_SPCLK
+				   | GPSR5_QSPI0_SSL
+				   | GPSR5_QSPI0_IO3
+				   | GPSR5_QSPI0_IO2
+				   | GPSR5_QSPI0_MISO_IO1
+				   | GPSR5_QSPI0_MOSI_IO0
+				   | GPSR5_QSPI0_SPCLK);
+
+
+	/* initialize peripheral function select */
+	pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
+				   | IPSR_24_FUNC(0)
+				   | IPSR_20_FUNC(0)
+				   | IPSR_16_FUNC(0)
+				   | IPSR_12_FUNC(0)
+				   | IPSR_8_FUNC(0)
+				   | IPSR_4_FUNC(0)
+				   | IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(0)
+				   | IPSR_24_FUNC(0)
+				   | IPSR_20_FUNC(0)
+				   | IPSR_16_FUNC(0)
+				   | IPSR_12_FUNC(0)
+				   | IPSR_8_FUNC(0)
+				   | IPSR_4_FUNC(0)
+				   | IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
+				   | IPSR_24_FUNC(0)
+				   | IPSR_20_FUNC(0)
+				   | IPSR_16_FUNC(0)
+				   | IPSR_12_FUNC(0)
+				   | IPSR_8_FUNC(0)
+				   | IPSR_4_FUNC(0)
+				   | IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(0)
+				   | IPSR_24_FUNC(0)
+				   | IPSR_20_FUNC(0)
+				   | IPSR_16_FUNC(0)
+				   | IPSR_12_FUNC(0)
+				   | IPSR_8_FUNC(0)
+				   | IPSR_4_FUNC(0)
+				   | IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
+				   | IPSR_24_FUNC(0)
+				   | IPSR_20_FUNC(0)
+				   | IPSR_16_FUNC(0)
+				   | IPSR_12_FUNC(0)
+				   | IPSR_8_FUNC(0)
+				   | IPSR_4_FUNC(0)
+				   | IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0)
+				   | IPSR_24_FUNC(0)
+				   | IPSR_20_FUNC(0)
+				   | IPSR_16_FUNC(0)
+				   | IPSR_12_FUNC(0)
+				   | IPSR_8_FUNC(0)
+				   | IPSR_4_FUNC(0)
+				   | IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(0)
+				   | IPSR_24_FUNC(0)
+				   | IPSR_20_FUNC(0)
+				   | IPSR_16_FUNC(0)
+				   | IPSR_12_FUNC(0)
+				   | IPSR_8_FUNC(0)
+				   | IPSR_4_FUNC(0)
+				   | IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
+				   | IPSR_24_FUNC(4)
+				   | IPSR_20_FUNC(4)
+				   | IPSR_16_FUNC(4)
+				   | IPSR_12_FUNC(4)
+				   | IPSR_8_FUNC(0)
+				   | IPSR_4_FUNC(0)
+				   | IPSR_0_FUNC(0));
+
+	pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(0)
+				   | IPSR_24_FUNC(0)
+				   | IPSR_20_FUNC(0)
+				   | IPSR_16_FUNC(4)
+				   | IPSR_12_FUNC(0)
+				   | IPSR_8_FUNC(0)
+				   | IPSR_4_FUNC(0)
+				   | IPSR_0_FUNC(0));
+
+	/* initialize POC Control */
+
+	pfc_reg_write(PFC_IOCTRL30, IOCTRL30_POC_VI0_DATA5
+				   | IOCTRL30_POC_VI0_DATA4
+				   | IOCTRL30_POC_VI0_DATA3
+				   | IOCTRL30_POC_VI0_DATA2
+				   | IOCTRL30_POC_VI0_DATA1
+				   | IOCTRL30_POC_VI0_DATA0
+				   | IOCTRL30_POC_VI0_VSYNC_N
+				   | IOCTRL30_POC_VI0_HSYNC_N
+				   | IOCTRL30_POC_VI0_CLKENB
+				   | IOCTRL30_POC_VI0_CLK
+				   | IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE
+				   | IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC
+				   | IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC
+				   | IOCTRL30_POC_DU_DOTCLKOUT
+				   | IOCTRL30_POC_DU_DB7
+				   | IOCTRL30_POC_DU_DB6
+				   | IOCTRL30_POC_DU_DB5
+				   | IOCTRL30_POC_DU_DB4
+				   | IOCTRL30_POC_DU_DB3
+				   | IOCTRL30_POC_DU_DB2
+				   | IOCTRL30_POC_DU_DG7
+				   | IOCTRL30_POC_DU_DG6
+				   | IOCTRL30_POC_DU_DG5
+				   | IOCTRL30_POC_DU_DG4
+				   | IOCTRL30_POC_DU_DG3
+				   | IOCTRL30_POC_DU_DG2
+				   | IOCTRL30_POC_DU_DR7
+				   | IOCTRL30_POC_DU_DR6
+				   | IOCTRL30_POC_DU_DR5
+				   | IOCTRL30_POC_DU_DR4
+				   | IOCTRL30_POC_DU_DR3
+				   | IOCTRL30_POC_DU_DR2);
+
+	pfc_reg_write(PFC_IOCTRL31, IOCTRL31_POC_DUMMY_31
+				   | IOCTRL31_POC_DUMMY_30
+				   | IOCTRL31_POC_DUMMY_29
+				   | IOCTRL31_POC_DUMMY_28
+				   | IOCTRL31_POC_DUMMY_27
+				   | IOCTRL31_POC_DUMMY_26
+				   | IOCTRL31_POC_DUMMY_25
+				   | IOCTRL31_POC_DUMMY_24
+				   | IOCTRL31_POC_VI1_FIELD
+				   | IOCTRL31_POC_VI1_DATA11
+				   | IOCTRL31_POC_VI1_DATA10
+				   | IOCTRL31_POC_VI1_DATA9
+				   | IOCTRL31_POC_VI1_DATA8
+				   | IOCTRL31_POC_VI1_DATA7
+				   | IOCTRL31_POC_VI1_DATA6
+				   | IOCTRL31_POC_VI1_DATA5
+				   | IOCTRL31_POC_VI1_DATA4
+				   | IOCTRL31_POC_VI1_DATA3
+				   | IOCTRL31_POC_VI1_DATA2
+				   | IOCTRL31_POC_VI1_DATA1
+				   | IOCTRL31_POC_VI1_DATA0
+				   | IOCTRL31_POC_VI1_VSYNC_N
+				   | IOCTRL31_POC_VI1_HSYNC_N
+				   | IOCTRL31_POC_VI1_CLKENB
+				   | IOCTRL31_POC_VI1_CLK
+				   | IOCTRL31_POC_VI0_FIELD
+				   | IOCTRL31_POC_VI0_DATA11
+				   | IOCTRL31_POC_VI0_DATA10
+				   | IOCTRL31_POC_VI0_DATA9
+				   | IOCTRL31_POC_VI0_DATA8
+				   | IOCTRL31_POC_VI0_DATA7
+				   | IOCTRL31_POC_VI0_DATA6);
+
+	pfc_reg_write(PFC_IOCTRL32,0x00000000);
+
+	pfc_reg_write(PFC_IOCTRL40,0x00000000);
+	
+	/* initialize Pull enable */
+	pfc_reg_write(PFC_PUEN0,PUEN0_PUEN_VI0_CLK
+				   | PUEN0_PUEN_TDI
+				   | PUEN0_PUEN_TMS
+				   | PUEN0_PUEN_TCK
+				   | PUEN0_PUEN_TRST_N
+				   | PUEN0_PUEN_IRQ0
+				   | PUEN0_PUEN_FSCLKST_N
+				   | PUEN0_PUEN_DU_EXHSYNC_DU_HSYNC
+				   | PUEN0_PUEN_DU_DOTCLKOUT
+				   | PUEN0_PUEN_DU_DB7
+				   | PUEN0_PUEN_DU_DB6
+				   | PUEN0_PUEN_DU_DB5
+				   | PUEN0_PUEN_DU_DB4
+				   | PUEN0_PUEN_DU_DB3
+				   | PUEN0_PUEN_DU_DB2
+				   | PUEN0_PUEN_DU_DG7
+				   | PUEN0_PUEN_DU_DG6
+				   | PUEN0_PUEN_DU_DG5
+				   | PUEN0_PUEN_DU_DG4
+				   | PUEN0_PUEN_DU_DG3
+				   | PUEN0_PUEN_DU_DG2
+				   | PUEN0_PUEN_DU_DR7
+				   | PUEN0_PUEN_DU_DR6
+				   | PUEN0_PUEN_DU_DR5
+				   | PUEN0_PUEN_DU_DR4
+				   | PUEN0_PUEN_DU_DR3
+				   | PUEN0_PUEN_DU_DR2);
+
+	pfc_reg_write(PFC_PUEN1,PUEN1_PUEN_VI1_DATA11
+				   | PUEN1_PUEN_VI1_DATA10
+				   | PUEN1_PUEN_VI1_DATA9
+				   | PUEN1_PUEN_VI1_DATA8
+				   | PUEN1_PUEN_VI1_DATA7
+				   | PUEN1_PUEN_VI1_DATA6
+				   | PUEN1_PUEN_VI1_DATA5
+				   | PUEN1_PUEN_VI1_DATA4
+				   | PUEN1_PUEN_VI1_DATA3
+				   | PUEN1_PUEN_VI1_DATA2
+				   | PUEN1_PUEN_VI1_DATA1
+				   | PUEN1_PUEN_VI1_DATA0
+				   | PUEN1_PUEN_VI1_VSYNC_N
+				   | PUEN1_PUEN_VI1_HSYNC_N
+				   | PUEN1_PUEN_VI1_CLKENB
+				   | PUEN1_PUEN_VI1_CLK
+				   | PUEN1_PUEN_VI0_DATA11
+				   | PUEN1_PUEN_VI0_DATA10
+				   | PUEN1_PUEN_VI0_DATA9
+				   | PUEN1_PUEN_VI0_DATA8
+				   | PUEN1_PUEN_VI0_DATA7
+				   | PUEN1_PUEN_VI0_DATA6
+				   | PUEN1_PUEN_VI0_DATA5
+				   | PUEN1_PUEN_VI0_DATA4
+				   | PUEN1_PUEN_VI0_DATA3
+				   | PUEN1_PUEN_VI0_DATA2
+				   | PUEN1_PUEN_VI0_DATA1);
+
+	pfc_reg_write(PFC_PUEN2,PUEN2_PUEN_CANFD_CLK
+				   | PUEN2_PUEN_CANFD1_RX
+				   | PUEN2_PUEN_CANFD1_TX
+				   | PUEN2_PUEN_CANFD0_RX
+				   | PUEN2_PUEN_CANFD0_TX
+				   | PUEN2_PUEN_AVB0_AVTP_CAPTURE
+				   | PUEN2_PUEN_AVB0_AVTP_MATCH
+				   | PUEN2_PUEN_AVB0_LINK
+				   | PUEN2_PUEN_AVB0_PHY_INT
+				   | PUEN2_PUEN_AVB0_MAGIC
+				   | PUEN2_PUEN_AVB0_TXCREFCLK
+				   | PUEN2_PUEN_AVB0_TD3
+				   | PUEN2_PUEN_AVB0_TD2
+				   | PUEN2_PUEN_AVB0_TD1
+				   | PUEN2_PUEN_AVB0_TD0
+				   | PUEN2_PUEN_AVB0_TXC
+				   | PUEN2_PUEN_AVB0_TX_CTL
+				   | PUEN2_PUEN_AVB0_RD3
+				   | PUEN2_PUEN_AVB0_RD2
+				   | PUEN2_PUEN_AVB0_RD1
+				   | PUEN2_PUEN_AVB0_RD0
+				   | PUEN2_PUEN_AVB0_RXC
+				   | PUEN2_PUEN_AVB0_RX_CTL
+				   | PUEN2_PUEN_VI1_FIELD);
+
+	pfc_reg_write(PFC_PUEN3,PUEN3_PUEN_DIGRF_CLKOUT
+				   | PUEN3_PUEN_DIGRF_CLKIN);
+
+	/* initialize PUD Control */
+	pfc_reg_write(PFC_PUD0,PUD0_PUD_VI0_CLK
+				   | PUD0_PUD_IRQ0
+				   | PUD0_PUD_FSCLKST_N
+				   | PUD0_PUD_DU_EXODDF_DU_ODDF_DISP_CDE
+				   | PUD0_PUD_DU_EXVSYNC_DU_VSYNC
+				   | PUD0_PUD_DU_EXHSYNC_DU_HSYNC
+				   | PUD0_PUD_DU_DOTCLKOUT
+				   | PUD0_PUD_DU_DB7
+				   | PUD0_PUD_DU_DB6
+				   | PUD0_PUD_DU_DB5
+				   | PUD0_PUD_DU_DB4
+				   | PUD0_PUD_DU_DB3
+				   | PUD0_PUD_DU_DB2
+				   | PUD0_PUD_DU_DG7
+				   | PUD0_PUD_DU_DG6
+				   | PUD0_PUD_DU_DG5
+				   | PUD0_PUD_DU_DG4
+				   | PUD0_PUD_DU_DG3
+				   | PUD0_PUD_DU_DG2
+				   | PUD0_PUD_DU_DR7
+				   | PUD0_PUD_DU_DR6
+				   | PUD0_PUD_DU_DR5
+				   | PUD0_PUD_DU_DR4
+				   | PUD0_PUD_DU_DR3
+				   | PUD0_PUD_DU_DR2);
+
+	pfc_reg_write(PFC_PUD1,PUD1_PUD_VI1_DATA11
+				   | PUD1_PUD_VI1_DATA10
+				   | PUD1_PUD_VI1_DATA9 
+				   | PUD1_PUD_VI1_DATA8 
+				   | PUD1_PUD_VI1_DATA7 
+				   | PUD1_PUD_VI1_DATA6 
+				   | PUD1_PUD_VI1_DATA5 
+				   | PUD1_PUD_VI1_DATA4 
+				   | PUD1_PUD_VI1_DATA3 
+				   | PUD1_PUD_VI1_DATA2 
+				   | PUD1_PUD_VI1_DATA1 
+				   | PUD1_PUD_VI1_DATA0 
+				   | PUD1_PUD_VI1_VSYNC_N
+				   | PUD1_PUD_VI1_HSYNC_N
+				   | PUD1_PUD_VI1_CLKENB
+				   | PUD1_PUD_VI1_CLK
+				   | PUD1_PUD_VI0_DATA11
+				   | PUD1_PUD_VI0_DATA10
+				   | PUD1_PUD_VI0_DATA9 
+				   | PUD1_PUD_VI0_DATA8 
+				   | PUD1_PUD_VI0_DATA7 
+				   | PUD1_PUD_VI0_DATA6 
+				   | PUD1_PUD_VI0_DATA5 
+				   | PUD1_PUD_VI0_DATA4 
+				   | PUD1_PUD_VI0_DATA3 
+				   | PUD1_PUD_VI0_DATA2 
+				   | PUD1_PUD_VI0_DATA1 
+				   | PUD1_PUD_VI0_DATA0 
+				   | PUD1_PUD_VI0_VSYNC_N
+				   | PUD1_PUD_VI0_HSYNC_N
+				   | PUD1_PUD_VI0_CLKENB);
+
+	pfc_reg_write(PFC_PUD2,PUD2_PUD_CANFD_CLK
+				   | PUD2_PUD_CANFD1_RX
+				   | PUD2_PUD_CANFD1_TX
+				   | PUD2_PUD_CANFD0_RX
+				   | PUD2_PUD_CANFD0_TX
+				   | PUD2_PUD_AVB0_AVTP_CAPTURE
+				   | PUD2_PUD_VI1_FIELD);
+
+	pfc_reg_write(PFC_PUD3,PUD3_PUD_DIGRF_CLKOUT
+				   | PUD3_PUD_DIGRF_CLKIN);
+
+	/* initialize Module Select */
+	pfc_reg_write(PFC_MOD_SEL0,0x00000000);
+
+	// gpio
+	/* initialize positive/negative logic select */
+	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+
+	/* initialize general IO/interrupt switching */
+	mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+
+	/* initialize general output register */
+	mmio_write_32(GPIO_OUTDT0, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT2, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT3, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT4, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT5, 0x00000000U);
+
+	/* initialize general input/output switching */
+	mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL1, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL2, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL3, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL5, 0x00000000U);
+}
diff --git a/plat/renesas/rcar/pfc/V3M/pfc_init_v3m.h b/plat/renesas/rcar/pfc/V3M/pfc_init_v3m.h
new file mode 100644
index 0000000..bfc0253
--- /dev/null
+++ b/plat/renesas/rcar/pfc/V3M/pfc_init_v3m.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *
+ *   - Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *
+ *   - Neither the name of Renesas nor the names of its contributors may be
+ *     used to endorse or promote products derived from this software without
+ *     specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef PFC_INIT_V3M_H__
+#define PFC_INIT_V3M_H__
+
+void pfc_init_v3m(void);
+
+#endif	/* PFC_INIT_V3M_H__ */
diff --git a/plat/renesas/rcar/pfc/pfc.mk b/plat/renesas/rcar/pfc/pfc.mk
index 27af928..d539dd2 100644
--- a/plat/renesas/rcar/pfc/pfc.mk
+++ b/plat/renesas/rcar/pfc/pfc.mk
@@ -9,6 +9,7 @@ ifeq (${RCAR_LSI},${RCAR_AUTO})
     BL2_SOURCES += plat/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
     BL2_SOURCES += plat/renesas/rcar/pfc/M3/pfc_init_m3.c
     BL2_SOURCES += plat/renesas/rcar/pfc/M3N/pfc_init_m3n.c
+    BL2_SOURCES += plat/renesas/rcar/pfc/V3M/pfc_init_v3m.c
 
 else ifdef RCAR_LSI_CUT_COMPAT
   ifeq (${RCAR_LSI},${RCAR_H3})
@@ -28,6 +29,9 @@ else ifdef RCAR_LSI_CUT_COMPAT
   ifeq (${RCAR_LSI},${RCAR_E3})
     BL2_SOURCES += plat/renesas/rcar/pfc/E3/pfc_init_e3.c
   endif
+  ifeq (${RCAR_LSI},${RCAR_V3M})
+    BL2_SOURCES += plat/renesas/rcar/pfc/V3M/pfc_init_v3m.c
+  endif
 else
   ifeq (${RCAR_LSI},${RCAR_H3})
     ifeq (${LSI_CUT},10)
@@ -51,6 +55,9 @@ else
   ifeq (${RCAR_LSI},${RCAR_E3})
     BL2_SOURCES += plat/renesas/rcar/pfc/E3/pfc_init_e3.c
   endif
+  ifeq (${RCAR_LSI},${RCAR_V3M})
+    BL2_SOURCES += plat/renesas/rcar/pfc/V3M/pfc_init_v3m.c
+  endif
 endif
 
 BL2_SOURCES += plat/renesas/rcar/pfc/pfc_init.c
diff --git a/plat/renesas/rcar/pfc/pfc_init.c b/plat/renesas/rcar/pfc/pfc_init.c
index ae14af5..75fecd6 100644
--- a/plat/renesas/rcar/pfc/pfc_init.c
+++ b/plat/renesas/rcar/pfc/pfc_init.c
@@ -14,6 +14,7 @@
   #include "H3/pfc_init_h3_v2.h"
   #include "M3/pfc_init_m3.h"
   #include "M3N/pfc_init_m3n.h"
+  #include "V3M/pfc_init_v3m.h"
 #endif
 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)	/* H3 */
   #include "H3/pfc_init_h3_v1.h"
@@ -28,6 +29,9 @@
 #if RCAR_LSI == RCAR_E3	/* E3 */
   #include "E3/pfc_init_e3.h"
 #endif
+#if RCAR_LSI == RCAR_V3M	/* V3M */
+  #include "V3M/pfc_init_v3m.h"
+#endif
 
  /* Product Register */
 #define PRR			(0xFFF00044U)
@@ -35,6 +39,7 @@
 #define PRR_CUT_MASK		(0x000000FFU)
 #define PRR_PRODUCT_H3		(0x00004F00U)           /* R-Car H3 */
 #define PRR_PRODUCT_M3		(0x00005200U)           /* R-Car M3 */
+#define PRR_PRODUCT_V3M		(0x00005400U)           /* R-Car V3M */
 #define PRR_PRODUCT_M3N		(0x00005500U)           /* R-Car M3N */
 #define PRR_PRODUCT_E3		(0x00005700U)		/* R-Car E3 */
 #define PRR_PRODUCT_10		(0x00U)
@@ -78,6 +83,9 @@ void pfc_init(void)
 	case RCAR_PRODUCT_M3N:
 		pfc_init_m3n();
 		break;
+	case RCAR_PRODUCT_V3M:
+		pfc_init_v3m();
+		break;
 	default:
 		PRR_PRODUCT_ERR(reg);
 		break;
@@ -123,6 +131,13 @@ void pfc_init(void)
 		pfc_init_e3();
 #endif
 		break;
+	case PRR_PRODUCT_V3M:
+#if RCAR_LSI != RCAR_V3M
+		PRR_PRODUCT_ERR(reg);
+#else
+		pfc_init_v3m();
+#endif
+		break;
 	default:
 		PRR_PRODUCT_ERR(reg);
 		break;
@@ -166,6 +181,11 @@ void pfc_init(void)
 		PRR_PRODUCT_ERR(reg);
 
 	pfc_init_e3();
+ #elif RCAR_LSI == RCAR_V3M	/* V3M */
+	if ((PRR_PRODUCT_V3M) != (reg & PRR_PRODUCT_MASK))
+		PRR_PRODUCT_ERR(reg);
+
+	pfc_init_v3m();
  #else
   #error "Don't have PFC initialize routine(unknown)."
  #endif
diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk
index 3cac10a..e6eb04b 100644
--- a/plat/renesas/rcar/platform.mk
+++ b/plat/renesas/rcar/platform.mk
@@ -97,12 +97,14 @@ RCAR_M3:=1
 RCAR_M3N:=2
 RCAR_E3:=3
 RCAR_H3N:=4
+RCAR_V3M:=5
 RCAR_AUTO:=99
 $(eval $(call add_define,RCAR_H3))
 $(eval $(call add_define,RCAR_M3))
 $(eval $(call add_define,RCAR_M3N))
 $(eval $(call add_define,RCAR_E3))
 $(eval $(call add_define,RCAR_H3N))
+$(eval $(call add_define,RCAR_V3M))
 $(eval $(call add_define,RCAR_AUTO))
 RCAR_CUT_10:=0
 RCAR_CUT_11:=1
@@ -211,6 +213,22 @@ else
       endif
       $(eval $(call add_define,RCAR_LSI_CUT))
     endif
+  else ifeq (${LSI},V3M)
+    RCAR_LSI:=${RCAR_V3M}
+    ifndef LSI_CUT
+      # enable compatible function.
+      RCAR_LSI_CUT_COMPAT := 1
+      $(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
+    else
+      # disable compatible function.
+      ifeq (${LSI_CUT},10)
+        RCAR_LSI_CUT:=0
+      endif
+      ifeq (${LSI_CUT},20)
+        RCAR_LSI_CUT:=10
+      endif
+      $(eval $(call add_define,RCAR_LSI_CUT))
+    endif
   else
     $(error "Error: ${LSI} is not supported.")
   endif
diff --git a/plat/renesas/rcar/qos/V3M/qos_init_v3m.c b/plat/renesas/rcar/qos/V3M/qos_init_v3m.c
new file mode 100644
index 0000000..9e6afa2
--- /dev/null
+++ b/plat/renesas/rcar/qos/V3M/qos_init_v3m.c
@@ -0,0 +1,411 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *
+ *   - Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *
+ *   - Neither the name of Renesas nor the names of its contributors may be
+ *     used to endorse or promote products derived from this software without
+ *     specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <debug.h>
+#include "qos_init_v3m.h"
+
+#define	RCAR_QOS_VERSION		"rev.0.01"
+
+#define	RCAR_QOS_NONE			(3U)
+#define	RCAR_QOS_TYPE_DEFAULT		(0U)
+
+#define	RCAR_DRAM_SPLIT_LINEAR		(0U)
+#define	RCAR_DRAM_SPLIT_4CH		(1U)
+#define	RCAR_DRAM_SPLIT_2CH		(2U)
+
+#define	DBSC_BASE			(0xE6790000U)
+#define	DBSC_AXARB			(DBSC_BASE + 0x0800U)
+
+#define DBSC_DBCAM0CNF0			(DBSC_BASE + 0x0900U)
+#define DBSC_DBCAM0CNF1			(DBSC_BASE + 0x0904U)
+#define DBSC_DBCAM0CNF2			(DBSC_BASE + 0x0908U)
+#define DBSC_DBCAM0CNF3			(DBSC_BASE + 0x090CU)
+#define DBSC_DBCAMDIS			(DBSC_BASE + 0x09fCU)
+#define DBSC_DBSCHCNT0			(DBSC_BASE + 0x1000U)
+#define DBSC_DBSCHCNT1			(DBSC_BASE + 0x1004U)
+#define DBSC_DBSCHSZ0			(DBSC_BASE + 0x1010U)
+#define DBSC_DBSCHRW0			(DBSC_BASE + 0x1020U)
+#define DBSC_DBSCHRW1			(DBSC_BASE + 0x1024U)
+#define DBSC_DBSCHQOS_0_0		(DBSC_BASE + 0x1030U)
+#define DBSC_DBSCHQOS_0_1		(DBSC_BASE + 0x1034U)
+#define DBSC_DBSCHQOS_0_2		(DBSC_BASE + 0x1038U)
+#define DBSC_DBSCHQOS_0_3		(DBSC_BASE + 0x103CU)
+#define DBSC_DBSCHQOS_1_0		(DBSC_BASE + 0x1040U)
+#define DBSC_DBSCHQOS_1_1		(DBSC_BASE + 0x1044U)
+#define DBSC_DBSCHQOS_1_2		(DBSC_BASE + 0x1048U)
+#define DBSC_DBSCHQOS_1_3		(DBSC_BASE + 0x104CU)
+#define DBSC_DBSCHQOS_2_0		(DBSC_BASE + 0x1050U)
+#define DBSC_DBSCHQOS_2_1		(DBSC_BASE + 0x1054U)
+#define DBSC_DBSCHQOS_2_2		(DBSC_BASE + 0x1058U)
+#define DBSC_DBSCHQOS_2_3		(DBSC_BASE + 0x105CU)
+#define DBSC_DBSCHQOS_3_0		(DBSC_BASE + 0x1060U)
+#define DBSC_DBSCHQOS_3_1		(DBSC_BASE + 0x1064U)
+#define DBSC_DBSCHQOS_3_2		(DBSC_BASE + 0x1068U)
+#define DBSC_DBSCHQOS_3_3		(DBSC_BASE + 0x106CU)
+#define DBSC_DBSCHQOS_4_0		(DBSC_BASE + 0x1070U)
+#define DBSC_DBSCHQOS_4_1		(DBSC_BASE + 0x1074U)
+#define DBSC_DBSCHQOS_4_2		(DBSC_BASE + 0x1078U)
+#define DBSC_DBSCHQOS_4_3		(DBSC_BASE + 0x107CU)
+#define DBSC_DBSCHQOS_5_0		(DBSC_BASE + 0x1080U)
+#define DBSC_DBSCHQOS_5_1		(DBSC_BASE + 0x1084U)
+#define DBSC_DBSCHQOS_5_2		(DBSC_BASE + 0x1088U)
+#define DBSC_DBSCHQOS_5_3		(DBSC_BASE + 0x108CU)
+#define DBSC_DBSCHQOS_6_0		(DBSC_BASE + 0x1090U)
+#define DBSC_DBSCHQOS_6_1		(DBSC_BASE + 0x1094U)
+#define DBSC_DBSCHQOS_6_2		(DBSC_BASE + 0x1098U)
+#define DBSC_DBSCHQOS_6_3		(DBSC_BASE + 0x109CU)
+#define DBSC_DBSCHQOS_7_0		(DBSC_BASE + 0x10A0U)
+#define DBSC_DBSCHQOS_7_1		(DBSC_BASE + 0x10A4U)
+#define DBSC_DBSCHQOS_7_2		(DBSC_BASE + 0x10A8U)
+#define DBSC_DBSCHQOS_7_3		(DBSC_BASE + 0x10ACU)
+#define DBSC_DBSCHQOS_8_0		(DBSC_BASE + 0x10B0U)
+#define DBSC_DBSCHQOS_8_1		(DBSC_BASE + 0x10B4U)
+#define DBSC_DBSCHQOS_8_2		(DBSC_BASE + 0x10B8U)
+#define DBSC_DBSCHQOS_8_3		(DBSC_BASE + 0x10BCU)
+#define DBSC_DBSCHQOS_9_0		(DBSC_BASE + 0x10C0U)
+#define DBSC_DBSCHQOS_9_1		(DBSC_BASE + 0x10C4U)
+#define DBSC_DBSCHQOS_9_2		(DBSC_BASE + 0x10C8U)
+#define DBSC_DBSCHQOS_9_3		(DBSC_BASE + 0x10CCU)
+#define DBSC_DBSCHQOS_10_0		(DBSC_BASE + 0x10D0U)
+#define DBSC_DBSCHQOS_10_1		(DBSC_BASE + 0x10D4U)
+#define DBSC_DBSCHQOS_10_2		(DBSC_BASE + 0x10D8U)
+#define DBSC_DBSCHQOS_10_3		(DBSC_BASE + 0x10DCU)
+#define DBSC_DBSCHQOS_11_0		(DBSC_BASE + 0x10E0U)
+#define DBSC_DBSCHQOS_11_1		(DBSC_BASE + 0x10E4U)
+#define DBSC_DBSCHQOS_11_2		(DBSC_BASE + 0x10E8U)
+#define DBSC_DBSCHQOS_11_3		(DBSC_BASE + 0x10ECU)
+#define DBSC_DBSCHQOS_12_0		(DBSC_BASE + 0x10F0U)
+#define DBSC_DBSCHQOS_12_1		(DBSC_BASE + 0x10F4U)
+#define DBSC_DBSCHQOS_12_2		(DBSC_BASE + 0x10F8U)
+#define DBSC_DBSCHQOS_12_3		(DBSC_BASE + 0x10FCU)
+#define DBSC_DBSCHQOS_13_0		(DBSC_BASE + 0x1100U)
+#define DBSC_DBSCHQOS_13_1		(DBSC_BASE + 0x1104U)
+#define DBSC_DBSCHQOS_13_2		(DBSC_BASE + 0x1108U)
+#define DBSC_DBSCHQOS_13_3		(DBSC_BASE + 0x110CU)
+#define DBSC_DBSCHQOS_14_0		(DBSC_BASE + 0x1110U)
+#define DBSC_DBSCHQOS_14_1		(DBSC_BASE + 0x1114U)
+#define DBSC_DBSCHQOS_14_2		(DBSC_BASE + 0x1118U)
+#define DBSC_DBSCHQOS_14_3		(DBSC_BASE + 0x111CU)
+#define DBSC_DBSCHQOS_15_0		(DBSC_BASE + 0x1120U)
+#define DBSC_DBSCHQOS_15_1		(DBSC_BASE + 0x1124U)
+#define DBSC_DBSCHQOS_15_2		(DBSC_BASE + 0x1128U)
+#define DBSC_DBSCHQOS_15_3		(DBSC_BASE + 0x112CU)
+#define DBSC_SCFCTST0			(DBSC_BASE + 0x1700U)
+#define DBSC_SCFCTST1			(DBSC_BASE + 0x1708U)
+#define DBSC_SCFCTST2			(DBSC_BASE + 0x170CU)
+
+#define	AXI_BASE			(0xE6784000U)
+#define	AXI_ADSPLCR0			(AXI_BASE + 0x0008U)
+#define	AXI_ADSPLCR1			(AXI_BASE + 0x000CU)
+#define	AXI_ADSPLCR2			(AXI_BASE + 0x0010U)
+#define	AXI_ADSPLCR3			(AXI_BASE + 0x0014U)
+#define	ADSPLCR0_ADRMODE_DEFAULT	((uint32_t)0U << 31U)
+#define	ADSPLCR0_ADRMODE_GEN2		((uint32_t)1U << 31U)
+#define	ADSPLCR0_SPLITSEL(x)		((uint32_t)(x) << 16U)
+#define	ADSPLCR0_AREA(x)		((uint32_t)(x) <<  8U)
+#define	ADSPLCR0_SWP			(0x0CU)
+
+#define	MSTAT_BASE			(0xE67E0000U)
+#define	MSTAT_FIX_QOS_BANK0		(MSTAT_BASE + 0x0000U)
+#define	MSTAT_FIX_QOS_BANK1		(MSTAT_BASE + 0x1000U)
+#define	MSTAT_BE_QOS_BANK0		(MSTAT_BASE + 0x2000U)
+#define	MSTAT_BE_QOS_BANK1		(MSTAT_BASE + 0x3000U)
+#define	MSTAT_SL_INIT			(MSTAT_BASE + 0x8000U)
+#define	MSTAT_REF_ARS			(MSTAT_BASE + 0x8004U)
+#define	MSTAT_STATQC			(MSTAT_BASE + 0x8008U)
+
+#define	RALLOC_BASE			(0xE67F0000U)
+#define	RALLOC_RAS			(RALLOC_BASE + 0x0000U)
+#define	RALLOC_FIXTH			(RALLOC_BASE + 0x0004U)
+#define	RALLOC_RAEN			(RALLOC_BASE + 0x0018U)
+#define	RALLOC_REGGD			(RALLOC_BASE + 0x0020U)
+#define	RALLOC_DANN			(RALLOC_BASE + 0x0030U)
+#define	RALLOC_DANT			(RALLOC_BASE + 0x0038U)
+#define	RALLOC_EC			(RALLOC_BASE + 0x003CU)
+#define	RALLOC_EMS			(RALLOC_BASE + 0x0040U)
+#define	RALLOC_INSFC			(RALLOC_BASE + 0x0050U)
+#define	RALLOC_BERR			(RALLOC_BASE + 0x0054U)
+#define	RALLOC_RACNT0			(RALLOC_BASE + 0x0080U)
+
+#define ARRAY_SIZE(a)	(sizeof(a) / sizeof((a)[0]))
+
+
+static inline void io_write_32(uintptr_t addr, uint32_t value)
+{
+	*(volatile uint32_t*)addr = value;
+}
+
+static inline void io_write_64(uintptr_t addr, uint64_t value)
+{
+	*(volatile uint64_t*)addr = value;
+}
+
+
+typedef struct {
+	uintptr_t addr;
+	uint64_t value;
+} mstat_slot_t;
+
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+static const mstat_slot_t mstat_fix[] = {
+	{0x0000U, 0x000000000000FFFFU},
+	{0x0008U, 0x000000000000FFFFU},
+	{0x0010U, 0x000000000000FFFFU},
+	{0x0018U, 0x000000000000FFFFU},
+	{0x0020U, 0x001414090000FFFFU},
+	{0x0028U, 0x000C00000000FFFFU},
+	{0x0030U, 0x001008040000FFFFU},
+	{0x0038U, 0x001004040000FFFFU},
+	{0x0040U, 0x001004040000FFFFU},
+	{0x0048U, 0x000000000000FFFFU},
+	{0x0050U, 0x001004040000FFFFU},
+	{0x0058U, 0x001004040000FFFFU},
+	{0x0060U, 0x000000000000FFFFU},
+	{0x0068U, 0x001404040000FFFFU},
+	{0x0070U, 0x001008030000FFFFU},
+	{0x0078U, 0x001004030000FFFFU},
+	{0x0080U, 0x001004030000FFFFU},
+	{0x0088U, 0x000000000000FFFFU},
+	{0x0090U, 0x001004040000FFFFU},
+	{0x0098U, 0x001004040000FFFFU},
+	{0x00A0U, 0x000000000000FFFFU},
+	{0x00A8U, 0x000000000000FFFFU},
+	{0x00B0U, 0x000000000000FFFFU},
+	{0x00B8U, 0x000000000000FFFFU},
+	{0x00C0U, 0x000000000000FFFFU},
+	{0x00C8U, 0x000000000000FFFFU},
+	{0x00D0U, 0x000000000000FFFFU},
+	{0x00D8U, 0x000000000000FFFFU},
+	{0x00E0U, 0x001404020000FFFFU},
+	{0x00E8U, 0x000000000000FFFFU},
+	{0x00F0U, 0x000000000000FFFFU},
+	{0x00F8U, 0x000000000000FFFFU},
+	{0x0100U, 0x000000000000FFFFU},
+	{0x0108U, 0x000C04020000FFFFU},
+	{0x0110U, 0x000000000000FFFFU},
+	{0x0118U, 0x001404020000FFFFU},
+	{0x0120U, 0x000000000000FFFFU},
+	{0x0128U, 0x000000000000FFFFU},
+	{0x0130U, 0x000000000000FFFFU},
+	{0x0138U, 0x000000000000FFFFU},
+	{0x0140U, 0x000000000000FFFFU},
+	{0x0148U, 0x000000000000FFFFU},
+};
+
+static const mstat_slot_t mstat_be[] = {
+	{0x0000U, 0x00100020447FFC01U},
+	{0x0008U, 0x00100020447FFC01U},
+	{0x0010U, 0x00100040447FFC01U},
+	{0x0018U, 0x00100040447FFC01U},
+	{0x0020U, 0x0000000000000000U},
+	{0x0028U, 0x0000000000000000U},
+	{0x0030U, 0x0000000000000000U},
+	{0x0038U, 0x0000000000000000U},
+	{0x0040U, 0x0000000000000000U},
+	{0x0048U, 0x0000000000000000U},
+	{0x0050U, 0x0000000000000000U},
+	{0x0058U, 0x0000000000000000U},
+	{0x0060U, 0x0000000000000000U},
+	{0x0068U, 0x0000000000000000U},
+	{0x0070U, 0x0000000000000000U},
+	{0x0078U, 0x0000000000000000U},
+	{0x0080U, 0x0000000000000000U},
+	{0x0088U, 0x0000000000000000U},
+	{0x0090U, 0x0000000000000000U},
+	{0x0098U, 0x0000000000000000U},
+	{0x00A0U, 0x00100010447FFC01U},
+	{0x00A8U, 0x00100010447FFC01U},
+	{0x00B0U, 0x00100010447FFC01U},
+	{0x00B8U, 0x00100010447FFC01U},
+	{0x00C0U, 0x00100010447FFC01U},
+	{0x00C8U, 0x00100010447FFC01U},
+	{0x00D0U, 0x0000000000000000U},
+	{0x00D8U, 0x00100010447FFC01U},
+	{0x00E0U, 0x0000000000000000U},
+	{0x00E8U, 0x00100010447FFC01U},
+	{0x00F0U, 0x00100010447FFC01U},
+	{0x00F8U, 0x00100010447FFC01U},
+	{0x0100U, 0x00100010447FFC01U},
+	{0x0108U, 0x0000000000000000U},
+	{0x0110U, 0x00100010447FFC01U},
+	{0x0118U, 0x0000000000000000U},
+	{0x0120U, 0x00100010447FFC01U},
+	{0x0128U, 0x00100010447FFC01U},
+	{0x0130U, 0x00100010447FFC01U},
+	{0x0138U, 0x00100010447FFC01U},
+	{0x0140U, 0x00100020447FFC01U},
+	{0x0148U, 0x00100020447FFC01U},
+};
+#endif
+
+static void dbsc_setting(void)
+{
+
+	/* BUFCAM settings */
+	//DBSC_DBCAM0CNF0 not set
+	io_write_32(DBSC_DBCAM0CNF1, 0x00044218);	//dbcam0cnf1
+	io_write_32(DBSC_DBCAM0CNF2, 0x000000F4);	//dbcam0cnf2
+	//io_write_32(DBSC_DBCAM0CNF3, 0x00000007);	//dbcam0cnf3
+	io_write_32(DBSC_DBSCHCNT0,  0x080F003F);	//dbschcnt0
+	io_write_32(DBSC_DBSCHCNT1,  0x00001010);	//dbschcnt0
+
+	io_write_32(DBSC_DBSCHSZ0,   0x00000001);	//dbschsz0
+	io_write_32(DBSC_DBSCHRW0,   0x22421111);	//dbschrw0
+	io_write_32(DBSC_DBSCHRW1,   0x00180034);	//dbschrw1
+	io_write_32(DBSC_SCFCTST0,0x180B1708);
+	io_write_32(DBSC_SCFCTST1,0x0808070C);
+	io_write_32(DBSC_SCFCTST2,0x012F1123);
+
+	/* QoS Settings */
+	io_write_32(DBSC_DBSCHQOS_0_0,  0x0000F000);
+	io_write_32(DBSC_DBSCHQOS_0_1,  0x0000E000);
+	io_write_32(DBSC_DBSCHQOS_0_2,  0x00007000);
+	io_write_32(DBSC_DBSCHQOS_0_3,  0x00000000);
+	//DBSC_DBSCHQOS_1_0 not set
+	//DBSC_DBSCHQOS_1_1 not set
+	//DBSC_DBSCHQOS_1_2 not set
+	//DBSC_DBSCHQOS_1_3 not set
+	//DBSC_DBSCHQOS_2_0 not set
+	//DBSC_DBSCHQOS_2_1 not set
+	//DBSC_DBSCHQOS_2_2 not set
+	//DBSC_DBSCHQOS_2_3 not set
+	//DBSC_DBSCHQOS_3_0 not set
+	//DBSC_DBSCHQOS_3_1 not set
+	//DBSC_DBSCHQOS_3_2 not set
+	//DBSC_DBSCHQOS_3_3 not set
+	io_write_32(DBSC_DBSCHQOS_4_0,  0x0000F000);
+	io_write_32(DBSC_DBSCHQOS_4_1,  0x0000EFFF);
+	io_write_32(DBSC_DBSCHQOS_4_2,  0x0000B000);
+	io_write_32(DBSC_DBSCHQOS_4_3,  0x00000000);
+	//DBSC_DBSCHQOS_5_0 not set
+	//DBSC_DBSCHQOS_5_1 not set
+	//DBSC_DBSCHQOS_5_2 not set
+	//DBSC_DBSCHQOS_5_3 not set
+	//DBSC_DBSCHQOS_6_0 not set
+	//DBSC_DBSCHQOS_6_1 not set
+	//DBSC_DBSCHQOS_6_2 not set
+	//DBSC_DBSCHQOS_6_3 not set
+	//DBSC_DBSCHQOS_7_0 not set
+	//DBSC_DBSCHQOS_7_1 not set
+	//DBSC_DBSCHQOS_7_2 not set
+	//DBSC_DBSCHQOS_7_3 not set
+	//DBSC_DBSCHQOS_8_0 not set
+	//DBSC_DBSCHQOS_8_1 not set
+	//DBSC_DBSCHQOS_8_2 not set
+	//DBSC_DBSCHQOS_8_3 not set
+	io_write_32(DBSC_DBSCHQOS_9_0,  0x0000F000);
+	io_write_32(DBSC_DBSCHQOS_9_1,  0x0000EFFF);
+	io_write_32(DBSC_DBSCHQOS_9_2,  0x0000D000);
+	io_write_32(DBSC_DBSCHQOS_9_3,  0x00000000);
+	//DBSC_DBSCHQOS_10_0 not set
+	//DBSC_DBSCHQOS_10_1 not set
+	//DBSC_DBSCHQOS_10_2 not set
+	//DBSC_DBSCHQOS_10_3 not set
+	//DBSC_DBSCHQOS_11_0 not set
+	//DBSC_DBSCHQOS_11_1 not set
+	//DBSC_DBSCHQOS_11_2 not set
+	//DBSC_DBSCHQOS_11_3 not set
+	//DBSC_DBSCHQOS_12_0 not set
+	//DBSC_DBSCHQOS_12_1 not set
+	//DBSC_DBSCHQOS_12_2 not set
+	//DBSC_DBSCHQOS_12_3 not set
+	io_write_32(DBSC_DBSCHQOS_13_0, 0x0000F000);
+	io_write_32(DBSC_DBSCHQOS_13_1, 0x0000EFFF);
+	io_write_32(DBSC_DBSCHQOS_13_2, 0x0000E800);
+	io_write_32(DBSC_DBSCHQOS_13_3, 0x00007000);
+	io_write_32(DBSC_DBSCHQOS_14_0, 0x0000F000);
+	io_write_32(DBSC_DBSCHQOS_14_1, 0x0000EFFF);
+	io_write_32(DBSC_DBSCHQOS_14_2, 0x0000E800);
+	io_write_32(DBSC_DBSCHQOS_14_3, 0x0000B000);
+	io_write_32(DBSC_DBSCHQOS_15_0, 0x000007D0);
+	io_write_32(DBSC_DBSCHQOS_15_1, 0x000007CF);
+	io_write_32(DBSC_DBSCHQOS_15_2, 0x000005D0);
+	io_write_32(DBSC_DBSCHQOS_15_3, 0x000003D0);
+}
+
+void qos_init_v3m(void)
+{
+return;
+
+	dbsc_setting();
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+	NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+	
+	/* Resource Alloc setting */
+	io_write_32(RALLOC_RAS,   0x00000020U);
+	io_write_32(RALLOC_FIXTH, 0x000F0005U);
+	io_write_32(RALLOC_REGGD, 0x00000004U);
+	io_write_64(RALLOC_DANN,  0x0202020104040200U);
+	io_write_32(RALLOC_DANT,  0x00201008U);
+	io_write_32(RALLOC_EC,    0x00080001U);	/* need for H3 ES1 */
+	io_write_64(RALLOC_EMS,   0x0000000000000000U);
+	io_write_32(RALLOC_INSFC, 0x63C20001U);
+	io_write_32(RALLOC_BERR,  0x00000000U);
+
+	/* MSTAT setting */
+	io_write_32(MSTAT_SL_INIT, 0x0305007DU);
+	io_write_32(MSTAT_REF_ARS, 0x00330000U);
+
+	/* MSTAT SRAM setting */
+	{
+	uint32_t i;
+
+	for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+		io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
+				mstat_fix[i].value);
+		io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
+				mstat_fix[i].value);
+	}
+	for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+		io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
+				mstat_be[i].value);
+		io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
+				mstat_be[i].value);
+	}
+	}
+
+	/* AXI-IF arbitration setting */
+	io_write_32(DBSC_AXARB, 0x18010000U);
+
+	/* Resource Alloc start */
+	io_write_32(RALLOC_RAEN,  0x00000001U);
+
+	/* MSTAT start */
+	io_write_32(MSTAT_STATQC, 0x00000001U);
+
+#else
+	NOTICE("BL2: QoS is None\n");
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/plat/renesas/rcar/qos/V3M/qos_init_v3m.h b/plat/renesas/rcar/qos/V3M/qos_init_v3m.h
new file mode 100644
index 0000000..43a2d5b
--- /dev/null
+++ b/plat/renesas/rcar/qos/V3M/qos_init_v3m.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *
+ *   - Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *
+ *   - Neither the name of Renesas nor the names of its contributors may be
+ *     used to endorse or promote products derived from this software without
+ *     specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef QOS_INIT_H_V3M__
+#define QOS_INIT_H_V3M__
+
+void qos_init_v3m(void);
+
+#endif	/* QOS_INIT_H_V3M__ */
diff --git a/plat/renesas/rcar/qos/qos.mk b/plat/renesas/rcar/qos/qos.mk
index 3e15860..2512373 100644
--- a/plat/renesas/rcar/qos/qos.mk
+++ b/plat/renesas/rcar/qos/qos.mk
@@ -14,6 +14,7 @@ ifeq (${RCAR_LSI},${RCAR_AUTO})
     BL2_SOURCES += plat/renesas/rcar/qos/M3/qos_init_m3_v11.c
     BL2_SOURCES += plat/renesas/rcar/qos/M3/qos_init_m3_v30.c
     BL2_SOURCES += plat/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
+    BL2_SOURCES += plat/renesas/rcar/qos/V3M/qos_init_v3m.c
 else ifdef RCAR_LSI_CUT_COMPAT
   ifeq (${RCAR_LSI},${RCAR_H3})
     BL2_SOURCES += plat/renesas/rcar/qos/H3/qos_init_h3_v10.c
@@ -35,6 +36,9 @@ else ifdef RCAR_LSI_CUT_COMPAT
   ifeq (${RCAR_LSI},${RCAR_E3})
     BL2_SOURCES += plat/renesas/rcar/qos/E3/qos_init_e3_v10.c
   endif
+  ifeq (${RCAR_LSI},${RCAR_V3M})
+    BL2_SOURCES += plat/renesas/rcar/qos/V3M/qos_init_v3m.c
+  endif
 else
   ifeq (${RCAR_LSI},${RCAR_H3})
     ifeq (${LSI_CUT},10)
@@ -88,6 +92,9 @@ else
      BL2_SOURCES += plat/renesas/rcar/qos/E3/qos_init_e3_v10.c
     endif
   endif
+  ifeq (${RCAR_LSI},${RCAR_V3M})
+    BL2_SOURCES += plat/renesas/rcar/qos/V3M/qos_init_v3m.c
+  endif
 endif
 
 BL2_SOURCES += plat/renesas/rcar/qos/qos_init.c
diff --git a/plat/renesas/rcar/qos/qos_init.c b/plat/renesas/rcar/qos/qos_init.c
index b2915f4..cab2c28 100644
--- a/plat/renesas/rcar/qos/qos_init.c
+++ b/plat/renesas/rcar/qos/qos_init.c
@@ -18,6 +18,7 @@
   #include "M3/qos_init_m3_v11.h"
   #include "M3/qos_init_m3_v30.h"
   #include "M3N/qos_init_m3n_v10.h"
+  #include "V3M/qos_init_v3m.h"
 #endif
 #if RCAR_LSI == RCAR_H3	/* H3 */
   #include "H3/qos_init_h3_v10.h"
@@ -39,6 +40,9 @@
 #if RCAR_LSI == RCAR_E3	/* E3 */
   #include "E3/qos_init_e3_v10.h"
 #endif
+#if RCAR_LSI == RCAR_V3M	/* V3M */
+  #include "V3M/qos_init_v3m.h"
+#endif
 
  /* Product Register */
 #define PRR			(0xFFF00044U)
@@ -46,6 +50,7 @@
 #define PRR_CUT_MASK		(0x000000FFU)
 #define PRR_PRODUCT_H3		(0x00004F00U)           /* R-Car H3 */
 #define PRR_PRODUCT_M3		(0x00005200U)           /* R-Car M3 */
+#define PRR_PRODUCT_V3M		(0x00005400U)           /* R-Car V3M */
 #define PRR_PRODUCT_M3N		(0x00005500U)           /* R-Car M3N */
 #define PRR_PRODUCT_E3		(0x00005700U)           /* R-Car E3 */
 #define PRR_PRODUCT_10		(0x00U)
@@ -76,7 +81,7 @@ uint8_t  qos_init_ddr_phyvalid;
 void qos_init(void)
 {
 	uint32_t reg;
-#if !(RCAR_LSI == RCAR_E3)
+#if !(RCAR_LSI == RCAR_E3) && !(RCAR_LSI == RCAR_V3M)
 	uint32_t i;
 
 	qos_init_ddr_ch = 0;
@@ -161,6 +166,19 @@ void qos_init(void)
 		PRR_PRODUCT_ERR(reg);
  #endif
 		break;
+	case PRR_PRODUCT_V3M:
+ #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_V3M)
+		switch (reg & PRR_CUT_MASK) {
+		case PRR_PRODUCT_10:
+		case PRR_PRODUCT_20:
+		default:
+			qos_init_v3m();
+			break;
+		}
+ #else
+		PRR_PRODUCT_ERR(reg);
+ #endif
+		break;
 	default:
 		PRR_PRODUCT_ERR(reg);
 		break;
@@ -247,6 +265,13 @@ void qos_init(void)
 		PRR_PRODUCT_ERR(reg);
 	}
 	qos_init_e3_v10();
+ #elif RCAR_LSI == RCAR_V3M	/* V3M */
+	/* V3M Cut 10 or later */
+	if ((PRR_PRODUCT_V3M)
+			!= (reg & (PRR_PRODUCT_MASK))) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	qos_init_v3m();
  #else
   #error "Don't have QoS initialize routine(Unknown chip)."
  #endif
diff --git a/plat/renesas/rcar/rcar_def.h b/plat/renesas/rcar/rcar_def.h
index efd9c5d..50c868b 100644
--- a/plat/renesas/rcar/rcar_def.h
+++ b/plat/renesas/rcar/rcar_def.h
@@ -205,6 +205,7 @@
 #define RCAR_CUT_MASK			U(0x000000FF)
 #define RCAR_PRODUCT_H3			U(0x00004F00)
 #define RCAR_PRODUCT_M3			U(0x00005200)
+#define RCAR_PRODUCT_V3M		U(0x00005400)
 #define RCAR_PRODUCT_M3N		U(0x00005500)
 #define RCAR_PRODUCT_E3			U(0x00005700)
 #define RCAR_CUT_VER10			U(0x00000000)
-- 
2.7.4