path: root/bsp/meta-rcar/meta-rcar-gen3-adas/recipes-bsp/u-boot/u-boot/0018-ARM-rmobile-Add-R8A77980-V3HSK-board-support.patch

From 071b9f4120d39d4b5277bf1e48b888fa984135bd Mon Sep 17 00:00:00 2001
From: Valentine Barshak <valentine.barshak@cogentembedded.com>
Date: Tue, 23 Apr 2019 23:44:57 +0300
Subject: [PATCH 18/23] ARM: rmobile: Add R8A77980 V3HSK board support

This adds V3HSK board support based on the Condor board.

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
---
 arch/arm/dts/Makefile                  |   1 +
 arch/arm/dts/r8a77980-v3hsk-u-boot.dts |  34 +++++++++
 arch/arm/dts/r8a77980-v3hsk.dts        | 131 +++++++++++++++++++++++++++++++++
 arch/arm/mach-rmobile/Kconfig.64       |   6 ++
 board/renesas/v3hsk/Kconfig            |  15 ++++
 board/renesas/v3hsk/Makefile           |  10 +++
 board/renesas/v3hsk/v3hsk.c            | 107 +++++++++++++++++++++++++++
 configs/r8a77980_v3hsk_defconfig       |  77 +++++++++++++++++++
 include/configs/v3hsk.h                |  40 ++++++++++
 9 files changed, 421 insertions(+)
 create mode 100644 arch/arm/dts/r8a77980-v3hsk-u-boot.dts
 create mode 100644 arch/arm/dts/r8a77980-v3hsk.dts
 create mode 100644 board/renesas/v3hsk/Kconfig
 create mode 100644 board/renesas/v3hsk/Makefile
 create mode 100644 board/renesas/v3hsk/v3hsk.c
 create mode 100644 configs/r8a77980_v3hsk_defconfig
 create mode 100644 include/configs/v3hsk.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b6a5ef2..a3554e7 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -468,6 +468,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \
 	r8a77970-eagle-u-boot.dtb \
 	r8a77970-v3msk-u-boot.dtb \
 	r8a77980-condor-u-boot.dtb \
+	r8a77980-v3hsk-u-boot.dtb \
 	r8a77990-ebisu-u-boot.dtb \
 	r8a77990-ebisu-4d-u-boot.dtb \
 	r8a77995-draak-u-boot.dtb
diff --git a/arch/arm/dts/r8a77980-v3hsk-u-boot.dts b/arch/arm/dts/r8a77980-v3hsk-u-boot.dts
new file mode 100644
index 0000000..28090c5
--- /dev/null
+++ b/arch/arm/dts/r8a77980-v3hsk-u-boot.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Eagle board
+ *
+ * Copyright (C) 2019 Cogent Embedded, Inc.
+ */
+
+#include "r8a77980-v3hsk.dts"
+#include "r8a77980-u-boot.dtsi"
+
+/ {
+	aliases {
+		spi0 = &rpc;
+	};
+};
+
+&rpc {
+	num-cs = <1>;
+	status = "okay";
+	spi-max-frequency = <50000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	flash0: spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "s25fs512s", "spi-flash", "jedec,spi-nor";
+		spi-max-frequency = <50000000>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+		reg = <0>;
+		status = "okay";
+	};
+};
diff --git a/arch/arm/dts/r8a77980-v3hsk.dts b/arch/arm/dts/r8a77980-v3hsk.dts
new file mode 100644
index 0000000..9042483
--- /dev/null
+++ b/arch/arm/dts/r8a77980-v3hsk.dts
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the V3H Starter Kit board
+ *
+ * Copyright (C) 2019 Renesas Electronics Corp.
+ * Copyright (C) 2019 Cogent Embedded, Inc.
+ */
+
+/dts-v1/;
+#include "r8a77980.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Renesas V3H Starter Kit board";
+	compatible = "renesas,v3hsk", "renesas,r8a77980";
+
+	aliases {
+		serial0 = &scif0;
+		ethernet0 = &gether;
+	};
+
+	chosen {
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@48000000 {
+		device_type = "memory";
+		/* first 128MB is reserved for secure area. */
+		reg = <0 0x48000000 0 0x78000000>;
+	};
+
+	vcc3v3_d5: regulator-1 {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC3V3_D5";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vddq_vin01: regulator-2 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDQ_VIN01";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
+&extal_clk {
+	clock-frequency = <16666666>;
+};
+
+&extalr_clk {
+	clock-frequency = <32768>;
+};
+
+&gether {
+	pinctrl-0 = <&gether_pins>;
+	pinctrl-names = "default";
+
+	phy-mode = "rgmii-id";
+	phy-handle = <&phy0>;
+	renesas,no-ether-link;
+	status = "okay";
+
+	phy0: ethernet-phy@0 {
+		rxc-skew-ps = <1500>;
+		reg = <0>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+		reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&mmc0 {
+	/* used for on-board eMMC */
+	pinctrl-0 = <&mmc_pins>;
+	pinctrl-1 = <&mmc_pins_uhs>;
+	pinctrl-names = "default", "state_uhs";
+
+	vmmc-supply = <&vcc3v3_d5>;
+	vqmmc-supply = <&vddq_vin01>;
+	mmc-hs200-1_8v;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&pfc {
+	gether_pins: gether {
+		groups = "gether_mdio_a", "gether_rgmii",
+			 "gether_txcrefclk", "gether_txcrefclk_mega";
+		function = "gether";
+	};
+
+	mmc_pins: mmc {
+		groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
+		function = "mmc";
+		power-source = <1800>;
+	};
+
+	mmc_pins_uhs: mmc_uhs {
+		groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
+		function = "mmc";
+		power-source = <1800>;
+	};
+
+	scif0_pins: scif0 {
+		groups = "scif0_data";
+		function = "scif0";
+	};
+
+	scif_clk_pins: scif_clk {
+		groups = "scif_clk_b";
+		function = "scif_clk";
+	};
+};
+
+&scif0 {
+	pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&scif_clk {
+	clock-frequency = <14745600>;
+};
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 00e74f8..c8889bd 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -47,6 +47,11 @@ config TARGET_CONDOR
 	help
           Support for Renesas R-Car Gen3 Condor platform
 
+config TARGET_V3HSK
+	bool "V3HSK board"
+	help
+          Support for Renesas R-Car Gen3 V3HSK platform
+
 config TARGET_EBISU
 	bool "Ebisu board"
 	help
@@ -71,6 +76,7 @@ source "board/renesas/draak/Kconfig"
 source "board/renesas/eagle/Kconfig"
 source "board/renesas/v3msk/Kconfig"
 source "board/renesas/condor/Kconfig"
+source "board/renesas/v3hsk/Kconfig"
 source "board/renesas/ebisu/Kconfig"
 source "board/renesas/salvator-x/Kconfig"
 source "board/renesas/ulcb/Kconfig"
diff --git a/board/renesas/v3hsk/Kconfig b/board/renesas/v3hsk/Kconfig
new file mode 100644
index 0000000..531ceb7
--- /dev/null
+++ b/board/renesas/v3hsk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_V3HSK
+
+config SYS_SOC
+	default "rmobile"
+
+config SYS_BOARD
+	default "v3hsk"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "v3hsk"
+
+endif
diff --git a/board/renesas/v3hsk/Makefile b/board/renesas/v3hsk/Makefile
new file mode 100644
index 0000000..f41c7ab
--- /dev/null
+++ b/board/renesas/v3hsk/Makefile
@@ -0,0 +1,10 @@
+#
+# board/renesas/v3hsk/Makefile
+#
+# Copyright (C) 2019 Renesas Electronics Corporation
+# Copyright (C) 2019 Cogent Embedded, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y	:= v3hsk.o
diff --git a/board/renesas/v3hsk/v3hsk.c b/board/renesas/v3hsk/v3hsk.c
new file mode 100644
index 0000000..05c62d2
--- /dev/null
+++ b/board/renesas/v3hsk/v3hsk.c
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board/renesas/v3hsk/v3hsk.c
+ *     This file is V3HSK board support.
+ *
+ * Based on Condor board support
+ *
+ * Copyright (C) 2019 Cogent Embedded, Inc.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/sh_sdhi.h>
+#include <i2c.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CPGWPR  0xE6150900
+#define CPGWPCR	0xE6150904
+
+/* PLL */
+#define PLL0CR		0xE61500D8
+#define PLL0_STC_MASK	0x7F000000
+#define PLL0_STC_OFFSET	24
+
+#define CLK2MHZ(clk)	(clk / 1000 / 1000)
+void s_init(void)
+{
+	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+	u32 stc;
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	/* CPU frequency setting. Set to 0.8GHz */
+	stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_OFFSET;
+	clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+}
+
+int board_early_init_f(void)
+{
+	/* Unlock CPG access */
+	writel(0xA5A5FFFF, CPGWPR);
+	writel(0x5A5A0000, CPGWPCR);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+#define RST_BASE	0xE6160000
+#define RST_CA57RESCNT	(RST_BASE + 0x40)
+#define RST_CA53RESCNT	(RST_BASE + 0x44)
+#define RST_RSTOUTCR	(RST_BASE + 0x58)
+#define RST_CA57_CODE	0xA5A5000F
+#define RST_CA53_CODE	0x5A5A000F
+
+void reset_cpu(ulong addr)
+{
+	unsigned long midr, cputype;
+
+	asm volatile("mrs %0, midr_el1" : "=r" (midr));
+	cputype = (midr >> 4) & 0xfff;
+
+	if (cputype == 0xd03)
+		writel(RST_CA53_CODE, RST_CA53RESCNT);
+	else if (cputype == 0xd07)
+		writel(RST_CA57_CODE, RST_CA57RESCNT);
+	else
+		hang();
+}
diff --git a/configs/r8a77980_v3hsk_defconfig b/configs/r8a77980_v3hsk_defconfig
new file mode 100644
index 0000000..f52f813
--- /dev/null
+++ b/configs/r8a77980_v3hsk_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_RCAR_GEN3=y
+CONFIG_R8A77980=y
+CONFIG_TARGET_V3HSK=y
+CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_FIT=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_DEFAULT_FDT_FILE="r8a77980-v3hsk.dtb"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="r8a77980-v3hsk-u-boot"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_DM_GPIO=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_RENESAS_SDHI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_SH_ETHER=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_PFC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SCIF_CONSOLE=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_RENESAS_RPC_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SMBIOS_MANUFACTURER=""
diff --git a/include/configs/v3hsk.h b/include/configs/v3hsk.h
new file mode 100644
index 0000000..e5a981e
--- /dev/null
+++ b/include/configs/v3hsk.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * include/configs/v3hsk.h
+ *     This file is V3HSK board configuration.
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation
+ * Copyright (C) 2019 Cogent Embedded, Inc.
+ */
+
+#ifndef __V3HSK_H
+#define __V3HSK_H
+
+#include "rcar-gen3-common.h"
+
+/* Ethernet */
+#ifdef CONFIG_SH_ETHER
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	0x0
+#define CONFIG_SH_ETHER_PHY_MODE	PHY_INTERFACE_MODE_RGMII_ID
+#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#endif
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Environment compatibility */
+#undef CONFIG_ENV_SIZE_REDUND
+#undef CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SECT_SIZE	(256 * 1024)
+#define CONFIG_ENV_OFFSET	0x700000
+
+/* Board Clock */
+/* XTAL_CLK : 33.33MHz */
+#define CONFIG_SYS_CLK_FREQ	33333333u
+
+/* Generic Timer Definitions (use in assembler source) */
+#define COUNTER_FREQUENCY	0xFE502A	/* 16.66MHz from CPclk */
+
+#endif /* __V3HSK_H */
-- 
2.7.4