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From 58543097fab7bfb26c3f81ebb8cdfe8a29161c16 Mon Sep 17 00:00:00 2001
From: Valentine Barshak <valentine.barshak@cogentembedded.com>
Date: Mon, 29 Oct 2018 13:37:25 +0300
Subject: [PATCH 109/211] clk: renesas: r8a77970: cpg-mssr: Add ISP clock
This adds ISP clock.
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
---
drivers/clk/renesas/r8a77970-cpg-mssr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c
index ab847ee..5ae694b 100644
--- a/drivers/clk/renesas/r8a77970-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c
@@ -152,6 +152,7 @@ static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = {
DEF_MOD("vin1", 810, R8A77970_CLK_S2D1),
DEF_MOD("vin0", 811, R8A77970_CLK_S2D1),
DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2),
+ DEF_MOD("isp", 817, R8A77970_CLK_S2D1),
DEF_MOD("imr3", 820, R8A77970_CLK_S2D1),
DEF_MOD("imr2", 821, R8A77970_CLK_S2D1),
DEF_MOD("imr1", 822, R8A77970_CLK_S2D1),
--
2.7.4
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