blob: 22d2fcf697735aeb889f5d954ee26affeaaa1be1 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
|
From 8ba13604f545465951c92f5f1d677eb10ff71dec Mon Sep 17 00:00:00 2001
From: Valentine Barshak <valentine.barshak@cogentembedded.com>
Date: Fri, 16 Nov 2018 00:03:54 +0300
Subject: [PATCH 194/211] arm64: dts: renesas: condor: Add s25fs512s QSPI flash
node
Add s25fs512s QSPI flash node. This is based
on the original patch by Dmitry Shifrin.
Signed-off-by: Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
---
arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 72 +++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
index 577ff3a..6b5f574 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -629,6 +629,16 @@
power-source = <1800>;
};
+ qspi0_pins: qspi0 {
+ groups = "qspi0_ctrl", "qspi0_data4";
+ function = "qspi0";
+ };
+
+ qspi1_pins: qspi1 {
+ groups = "qspi1_ctrl", "qspi1_data4";
+ function = "qspi1";
+ };
+
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
@@ -640,6 +650,68 @@
};
};
+&qspi0 {
+ pinctrl-0 = <&qspi0_pins &qspi1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ flash@0 {
+ compatible = "spansion,s25fs512s", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootparam@0 {
+ reg = <0x00000000 0x040000>;
+ read-only;
+ };
+ cr7@00040000 {
+ reg = <0x00040000 0x080000>;
+ read-only;
+ };
+ cert_header_sa3@000C0000 {
+ reg = <0x000C0000 0x080000>;
+ read-only;
+ };
+ bl2@00140000 {
+ reg = <0x00140000 0x040000>;
+ read-only;
+ };
+ cert_header_sa6@00180000 {
+ reg = <0x00180000 0x040000>;
+ read-only;
+ };
+ bl31@001C0000 {
+ reg = <0x001C0000 0x480000>;
+ read-only;
+ };
+ uboot@00640000 {
+ reg = <0x00640000 0x0C0000>;
+ read-only;
+ };
+ uboot-env@00700000 {
+ reg = <0x00700000 0x040000>;
+ read-only;
+ };
+ dtb@00740000 {
+ reg = <0x00740000 0x080000>;
+ };
+ kernel@007C0000 {
+ reg = <0x007C0000 0x1400000>;
+ };
+ user@01BC0000 {
+ reg = <0x01BC0000 0x2440000>;
+ };
+ };
+ };
+};
+
&rwdt {
timeout-sec = <60>;
status = "okay";
--
2.7.4
|
