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| author |   Vladimir Barinov <vladimir.barinov@cogentembedded.com> | 2018-02-07 19:38:59 +0300 |
|---|---|---|
| committer | Vladimir Barinov <vladimir.barinov@cogentembedded.com> | 2018-02-26 23:24:54 +0300 |
| commit | 0a5fdaadc4a535cfb693d98738fde8d48b77447f (patch) | |
| tree | 28cf7c30342eba61fcfa441399907ca41716436c /meta-rcar-gen3-adas/recipes-bsp/iio-utils | |
| parent | 37054f0dd97c4833bd29bafd4a230244ac6ce1ff (diff) | |
V3M/V3H: sysc workaround for power down, cpu clock fixup
This adds SYSC workaround for power domains power down sequence
on V3M/V3H and add cpu clock fixup on V3H.
Also add VisionIP nodes and fix VSP i/f on V3H
Diffstat (limited to 'meta-rcar-gen3-adas/recipes-bsp/iio-utils')
0 files changed, 0 insertions, 0 deletions