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author | 2023-10-10 14:33:42 +0000 | |
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committer | 2023-10-10 14:33:42 +0000 | |
commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /capstone/MCInstrDesc.h | |
parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'capstone/MCInstrDesc.h')
-rw-r--r-- | capstone/MCInstrDesc.h | 147 |
1 files changed, 147 insertions, 0 deletions
diff --git a/capstone/MCInstrDesc.h b/capstone/MCInstrDesc.h new file mode 100644 index 000000000..084da9b7d --- /dev/null +++ b/capstone/MCInstrDesc.h @@ -0,0 +1,147 @@ +//===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the MCOperandInfo and MCInstrDesc classes, which +// are used to describe target instructions and their operands. +// +//===----------------------------------------------------------------------===// + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */ + +#ifndef CS_LLVM_MC_MCINSTRDESC_H +#define CS_LLVM_MC_MCINSTRDESC_H + +#include "MCRegisterInfo.h" +#include "capstone/platform.h" + +//===----------------------------------------------------------------------===// +// Machine Operand Flags and Description +//===----------------------------------------------------------------------===// + +// Operand constraints +enum MCOI_OperandConstraint { + MCOI_TIED_TO = 0, // Must be allocated the same register as. + MCOI_EARLY_CLOBBER // Operand is an early clobber register operand +}; + +/// OperandFlags - These are flags set on operands, but should be considered +/// private, all access should go through the MCOperandInfo accessors. +/// See the accessors for a description of what these are. +enum MCOI_OperandFlags { + MCOI_LookupPtrRegClass = 0, + MCOI_Predicate, + MCOI_OptionalDef +}; + +/// Operand Type - Operands are tagged with one of the values of this enum. +enum MCOI_OperandType { + MCOI_OPERAND_UNKNOWN = 0, + MCOI_OPERAND_IMMEDIATE = 1, + MCOI_OPERAND_REGISTER = 2, + MCOI_OPERAND_MEMORY = 3, + MCOI_OPERAND_PCREL = 4, + + MCOI_OPERAND_FIRST_GENERIC = 6, + MCOI_OPERAND_GENERIC_0 = 6, + MCOI_OPERAND_GENERIC_1 = 7, + MCOI_OPERAND_GENERIC_2 = 8, + MCOI_OPERAND_GENERIC_3 = 9, + MCOI_OPERAND_GENERIC_4 = 10, + MCOI_OPERAND_GENERIC_5 = 11, + MCOI_OPERAND_LAST_GENERIC = 11, + + MCOI_OPERAND_FIRST_TARGET = 12, +}; + + +/// MCOperandInfo - This holds information about one operand of a machine +/// instruction, indicating the register class for register operands, etc. +/// +typedef struct MCOperandInfo { + /// This specifies the register class enumeration of the operand + /// if the operand is a register. If isLookupPtrRegClass is set, then this is + /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to + /// get a dynamic register class. + int16_t RegClass; + + /// These are flags from the MCOI::OperandFlags enum. + uint8_t Flags; + + /// Information about the type of the operand. + uint8_t OperandType; + + /// The lower 16 bits are used to specify which constraints are set. + /// The higher 16 bits are used to specify the value of constraints (4 bits each). + uint32_t Constraints; + /// Currently no other information. +} MCOperandInfo; + + +//===----------------------------------------------------------------------===// +// Machine Instruction Flags and Description +//===----------------------------------------------------------------------===// + +/// MCInstrDesc flags - These should be considered private to the +/// implementation of the MCInstrDesc class. Clients should use the predicate +/// methods on MCInstrDesc, not use these directly. These all correspond to +/// bitfields in the MCInstrDesc::Flags field. +enum { + MCID_Variadic = 0, + MCID_HasOptionalDef, + MCID_Pseudo, + MCID_Return, + MCID_Call, + MCID_Barrier, + MCID_Terminator, + MCID_Branch, + MCID_IndirectBranch, + MCID_Compare, + MCID_MoveImm, + MCID_MoveReg, + MCID_Bitcast, + MCID_Select, + MCID_DelaySlot, + MCID_FoldableAsLoad, + MCID_MayLoad, + MCID_MayStore, + MCID_Predicable, + MCID_NotDuplicable, + MCID_UnmodeledSideEffects, + MCID_Commutable, + MCID_ConvertibleTo3Addr, + MCID_UsesCustomInserter, + MCID_HasPostISelHook, + MCID_Rematerializable, + MCID_CheapAsAMove, + MCID_ExtraSrcRegAllocReq, + MCID_ExtraDefRegAllocReq, + MCID_RegSequence, + MCID_ExtractSubreg, + MCID_InsertSubreg, + MCID_Convergent, + MCID_Add, + MCID_Trap, +}; + +/// MCInstrDesc - Describe properties that are true of each instruction in the +/// target description file. This captures information about side effects, +/// register use and many other things. There is one instance of this struct +/// for each target instruction class, and the MachineInstr class points to +/// this struct directly to describe itself. +typedef struct MCInstrDesc { + unsigned char NumOperands; // Num of args (may be more if variable_ops) + const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands +} MCInstrDesc; + +bool MCOperandInfo_isPredicate(const MCOperandInfo *m); + +bool MCOperandInfo_isOptionalDef(const MCOperandInfo *m); + +#endif |