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authorAngelos Mouzakitis <a.mouzakitis@virtualopensystems.com>2023-10-10 14:33:42 +0000
committerAngelos Mouzakitis <a.mouzakitis@virtualopensystems.com>2023-10-10 14:33:42 +0000
commitaf1a266670d040d2f4083ff309d732d648afba2a (patch)
tree2fc46203448ddcc6f81546d379abfaeb323575e9 /capstone/arch/Mips
parente02cda008591317b1625707ff8e115a4841aa889 (diff)
Add submodule dependency filesHEADmaster
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'capstone/arch/Mips')
-rw-r--r--capstone/arch/Mips/MipsDisassembler.c1794
-rw-r--r--capstone/arch/Mips/MipsDisassembler.h16
-rw-r--r--capstone/arch/Mips/MipsGenAsmWriter.inc5725
-rw-r--r--capstone/arch/Mips/MipsGenDisassemblerTables.inc6942
-rw-r--r--capstone/arch/Mips/MipsGenInstrInfo.inc1805
-rw-r--r--capstone/arch/Mips/MipsGenRegisterInfo.inc1679
-rw-r--r--capstone/arch/Mips/MipsGenSubtargetInfo.inc52
-rw-r--r--capstone/arch/Mips/MipsInstPrinter.c424
-rw-r--r--capstone/arch/Mips/MipsInstPrinter.h25
-rw-r--r--capstone/arch/Mips/MipsMapping.c1070
-rw-r--r--capstone/arch/Mips/MipsMapping.h25
-rw-r--r--capstone/arch/Mips/MipsMappingInsn.inc9315
-rw-r--r--capstone/arch/Mips/MipsModule.c52
-rw-r--r--capstone/arch/Mips/MipsModule.h12
14 files changed, 28936 insertions, 0 deletions
diff --git a/capstone/arch/Mips/MipsDisassembler.c b/capstone/arch/Mips/MipsDisassembler.c
new file mode 100644
index 000000000..294082394
--- /dev/null
+++ b/capstone/arch/Mips/MipsDisassembler.c
@@ -0,0 +1,1794 @@
+//===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file is part of the Mips Disassembler.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifdef CAPSTONE_HAS_MIPS
+
+#include <stdio.h>
+#include <string.h>
+
+#include "capstone/platform.h"
+
+#include "MipsDisassembler.h"
+
+#include "../../utils.h"
+
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+
+#include "../../MathExtras.h"
+
+//#include "Mips.h"
+//#include "MipsRegisterInfo.h"
+//#include "MipsSubtarget.h"
+#include "../../MCFixedLenDisassembler.h"
+#include "../../MCInst.h"
+//#include "llvm/MC/MCSubtargetInfo.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCDisassembler.h"
+
+// Forward declare these because the autogenerated code will reference them.
+// Definitions are further down.
+static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodePtrRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeCCRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeBranchTarget(MCInst *Inst,
+ unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeJumpTarget(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeBranchTarget21(MCInst *Inst,
+ unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeBranchTarget26(MCInst *Inst,
+ unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder);
+
+// DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
+// shifted left by 1 bit.
+static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst,
+ unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
+
+// DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
+// shifted left by 1 bit.
+static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst,
+ unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
+
+// DecodeBranchTargetMM - Decode microMIPS branch offset, which is
+// shifted left by 1 bit.
+static DecodeStatus DecodeBranchTargetMM(MCInst *Inst,
+ unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder);
+
+// DecodeJumpTargetMM - Decode microMIPS jump target, which is
+// shifted left by 1 bit.
+static DecodeStatus DecodeJumpTargetMM(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeMem(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeCacheOp(MCInst *Inst,
+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeCacheOpR6(MCInst *Inst,
+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeCacheOpMM(MCInst *Inst,
+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeSyncI(MCInst *Inst,
+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeMSA128Mem(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeMemMMImm4(MCInst *Inst,
+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst,
+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst,
+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst,
+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeMemMMImm12(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeMemMMImm16(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn,
+ uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeFMem2(MCInst *Inst, unsigned Insn,
+ uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeFMem3(MCInst *Inst, unsigned Insn,
+ uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, unsigned Insn,
+ uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst,
+ unsigned Value, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst,
+ unsigned Value, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeLiSimm7(MCInst *Inst,
+ unsigned Value, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeSimm4(MCInst *Inst,
+ unsigned Value, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeSimm16(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
+
+// Decode the immediate field of an LSA instruction which
+// is off by one.
+static DecodeStatus DecodeLSAImm(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeInsSize(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeExtSize(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeSimm9SP(MCInst *Inst,
+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeANDI16Imm(MCInst *Inst,
+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeUImm5lsl2(MCInst *Inst,
+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst,
+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
+/// handle.
+static DecodeStatus DecodeINSVE_DF_4(MCInst *MI,
+ uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI,
+ uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI,
+ uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI,
+ uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI,
+ uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI,
+ uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI,
+ uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeRegListOperand(MCInst *Inst,
+ uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeRegListOperand16(MCInst *Inst,
+ uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeMovePRegPair(MCInst *Inst,
+ uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+#define GET_SUBTARGETINFO_ENUM
+#include "MipsGenSubtargetInfo.inc"
+
+// Hacky: enable all features for disassembler
+static uint64_t getFeatureBits(int mode)
+{
+ uint64_t Bits = (uint64_t)-1; // include every features at first
+
+ // By default we do not support Mips1
+ Bits &= ~Mips_FeatureMips1;
+
+ // No MicroMips
+ Bits &= ~Mips_FeatureMicroMips;
+
+ // ref: MipsGenDisassemblerTables.inc::checkDecoderPredicate()
+ // some features are mutually execlusive
+ if (mode & CS_MODE_16) {
+ //Bits &= ~Mips_FeatureMips32r2;
+ //Bits &= ~Mips_FeatureMips32;
+ //Bits &= ~Mips_FeatureFPIdx;
+ //Bits &= ~Mips_FeatureBitCount;
+ //Bits &= ~Mips_FeatureSwap;
+ //Bits &= ~Mips_FeatureSEInReg;
+ //Bits &= ~Mips_FeatureMips64r2;
+ //Bits &= ~Mips_FeatureFP64Bit;
+ } else if (mode & CS_MODE_32) {
+ Bits &= ~Mips_FeatureMips16;
+ Bits &= ~Mips_FeatureFP64Bit;
+ Bits &= ~Mips_FeatureMips64r2;
+ Bits &= ~Mips_FeatureMips32r6;
+ Bits &= ~Mips_FeatureMips64r6;
+ } else if (mode & CS_MODE_64) {
+ Bits &= ~Mips_FeatureMips16;
+ Bits &= ~Mips_FeatureMips64r6;
+ Bits &= ~Mips_FeatureMips32r6;
+ } else if (mode & CS_MODE_MIPS32R6) {
+ Bits |= Mips_FeatureMips32r6;
+ Bits &= ~Mips_FeatureMips16;
+ Bits &= ~Mips_FeatureFP64Bit;
+ Bits &= ~Mips_FeatureMips64r6;
+ Bits &= ~Mips_FeatureMips64r2;
+ }
+
+ if (mode & CS_MODE_MICRO) {
+ Bits |= Mips_FeatureMicroMips;
+ Bits &= ~Mips_FeatureMips4_32r2;
+ Bits &= ~Mips_FeatureMips2;
+ }
+
+ return Bits;
+}
+
+#include "MipsGenDisassemblerTables.inc"
+
+#define GET_REGINFO_ENUM
+#include "MipsGenRegisterInfo.inc"
+
+#define GET_REGINFO_MC_DESC
+#include "MipsGenRegisterInfo.inc"
+
+#define GET_INSTRINFO_ENUM
+#include "MipsGenInstrInfo.inc"
+
+void Mips_init(MCRegisterInfo *MRI)
+{
+ // InitMCRegisterInfo(MipsRegDesc, 394, RA, PC,
+ // MipsMCRegisterClasses, 62,
+ // MipsRegUnitRoots,
+ // 273,
+ // MipsRegDiffLists,
+ // MipsLaneMaskLists,
+ // MipsRegStrings,
+ // MipsRegClassStrings,
+ // MipsSubRegIdxLists,
+ // 12,
+ // MipsSubRegIdxRanges,
+ // MipsRegEncodingTable);
+
+
+ MCRegisterInfo_InitMCRegisterInfo(MRI, MipsRegDesc, 394,
+ 0, 0,
+ MipsMCRegisterClasses, 62,
+ 0, 0,
+ MipsRegDiffLists,
+ 0,
+ MipsSubRegIdxLists, 12,
+ 0);
+}
+
+/// Read two bytes from the ArrayRef and return 16 bit halfword sorted
+/// according to the given endianess.
+static void readInstruction16(unsigned char *code, uint32_t *insn,
+ bool isBigEndian)
+{
+ // We want to read exactly 2 Bytes of data.
+ if (isBigEndian)
+ *insn = (code[0] << 8) | code[1];
+ else
+ *insn = (code[1] << 8) | code[0];
+}
+
+/// readInstruction - read four bytes from the MemoryObject
+/// and return 32 bit word sorted according to the given endianess
+static void readInstruction32(unsigned char *code, uint32_t *insn, bool isBigEndian, bool isMicroMips)
+{
+ // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
+ // always precede the low 16 bits in the instruction stream (that is, they
+ // are placed at lower addresses in the instruction stream).
+ //
+ // microMIPS byte ordering:
+ // Big-endian: 0 | 1 | 2 | 3
+ // Little-endian: 1 | 0 | 3 | 2
+
+ // We want to read exactly 4 Bytes of data.
+ if (isBigEndian) {
+ // Encoded as a big-endian 32-bit word in the stream.
+ *insn =
+ (code[3] << 0) | (code[2] << 8) | (code[1] << 16) | ((uint32_t) code[0] << 24);
+ } else {
+ if (isMicroMips) {
+ *insn = (code[2] << 0) | (code[3] << 8) | (code[0] << 16) |
+ ((uint32_t) code[1] << 24);
+ } else {
+ *insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) |
+ ((uint32_t) code[3] << 24);
+ }
+ }
+}
+
+static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
+ const uint8_t *code, size_t code_len,
+ uint16_t *Size,
+ uint64_t Address, bool isBigEndian, MCRegisterInfo *MRI)
+{
+ uint32_t Insn;
+ DecodeStatus Result;
+
+ if (instr->flat_insn->detail) {
+ memset(instr->flat_insn->detail, 0, offsetof(cs_detail, mips)+sizeof(cs_mips));
+ }
+
+ if (mode & CS_MODE_MICRO) {
+ if (code_len < 2)
+ // not enough data
+ return MCDisassembler_Fail;
+
+ readInstruction16((unsigned char*)code, &Insn, isBigEndian);
+
+ // Calling the auto-generated decoder function.
+ Result = decodeInstruction(DecoderTableMicroMips16, instr, Insn, Address, MRI, mode);
+ if (Result != MCDisassembler_Fail) {
+ *Size = 2;
+ return Result;
+ }
+
+ if (code_len < 4)
+ // not enough data
+ return MCDisassembler_Fail;
+
+ readInstruction32((unsigned char*)code, &Insn, isBigEndian, true);
+
+ //DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
+ // Calling the auto-generated decoder function.
+ Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address, MRI, mode);
+ if (Result != MCDisassembler_Fail) {
+ *Size = 4;
+ return Result;
+ }
+ return MCDisassembler_Fail;
+ }
+
+ if (code_len < 4)
+ // not enough data
+ return MCDisassembler_Fail;
+
+ readInstruction32((unsigned char*)code, &Insn, isBigEndian, false);
+
+ if ((mode & CS_MODE_MIPS2) && ((mode & CS_MODE_MIPS3) == 0)) {
+ // DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
+ Result = decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, MRI, mode);
+ if (Result != MCDisassembler_Fail) {
+ *Size = 4;
+ return Result;
+ }
+ }
+
+ if ((mode & CS_MODE_MIPS32R6) && (mode & CS_MODE_MIPS64)) {
+ // DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
+ Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn,
+ Address, MRI, mode);
+ if (Result != MCDisassembler_Fail) {
+ *Size = 4;
+ return Result;
+ }
+ }
+
+ if (mode & CS_MODE_MIPS32R6) {
+ // DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
+ Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn,
+ Address, MRI, mode);
+ if (Result != MCDisassembler_Fail) {
+ *Size = 4;
+ return Result;
+ }
+ }
+
+ if (mode & CS_MODE_MIPS64) {
+ // DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
+ Result = decodeInstruction(DecoderTableMips6432, instr, Insn,
+ Address, MRI, mode);
+ if (Result != MCDisassembler_Fail) {
+ *Size = 4;
+ return Result;
+ }
+ }
+
+ // DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
+ // Calling the auto-generated decoder function.
+ Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, MRI, mode);
+ if (Result != MCDisassembler_Fail) {
+ *Size = 4;
+ return Result;
+ }
+
+ return MCDisassembler_Fail;
+}
+
+bool Mips_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr,
+ uint16_t *size, uint64_t address, void *info)
+{
+ cs_struct *handle = (cs_struct *)(uintptr_t)ud;
+
+ DecodeStatus status = MipsDisassembler_getInstruction(handle->mode, instr,
+ code, code_len,
+ size,
+ address, MODE_IS_BIG_ENDIAN(handle->mode), (MCRegisterInfo *)info);
+
+ return status == MCDisassembler_Success;
+}
+
+static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
+{
+ const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
+ return rc->RegsBegin[RegNo];
+}
+
+static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, uint32_t insn,
+ uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ typedef DecodeStatus (*DecodeFN)(MCInst *, unsigned, uint64_t, const MCRegisterInfo *);
+ // The size of the n field depends on the element size
+ // The register class also depends on this.
+ uint32_t tmp = fieldFromInstruction(insn, 17, 5);
+ unsigned NSize = 0;
+ DecodeFN RegDecoder = NULL;
+
+ if ((tmp & 0x18) == 0x00) { // INSVE_B
+ NSize = 4;
+ RegDecoder = DecodeMSA128BRegisterClass;
+ } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
+ NSize = 3;
+ RegDecoder = DecodeMSA128HRegisterClass;
+ } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
+ NSize = 2;
+ RegDecoder = DecodeMSA128WRegisterClass;
+ } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
+ NSize = 1;
+ RegDecoder = DecodeMSA128DRegisterClass;
+ } //else llvm_unreachable("Invalid encoding");
+
+ //assert(NSize != 0 && RegDecoder != nullptr);
+ if (NSize == 0 || RegDecoder == NULL)
+ return MCDisassembler_Fail;
+
+ // $wd
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail)
+ return MCDisassembler_Fail;
+
+ // $wd_in
+ if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail)
+ return MCDisassembler_Fail;
+
+ // $n
+ tmp = fieldFromInstruction(insn, 16, NSize);
+ MCOperand_CreateImm0(MI, tmp);
+
+ // $ws
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail)
+ return MCDisassembler_Fail;
+
+ // $n2
+ MCOperand_CreateImm0(MI, 0);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, uint32_t insn,
+ uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
+ // (otherwise we would have matched the ADDI instruction from the earlier
+ // ISA's instead).
+ //
+ // We have:
+ // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
+ // BOVC if rs >= rt
+ // BEQZALC if rs == 0 && rt != 0
+ // BEQC if rs < rt && rs != 0
+
+ uint32_t Rs = fieldFromInstruction(insn, 21, 5);
+ uint32_t Rt = fieldFromInstruction(insn, 16, 5);
+ uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
+ bool HasRs = false;
+
+ if (Rs >= Rt) {
+ MCInst_setOpcode(MI, Mips_BOVC);
+ HasRs = true;
+ } else if (Rs != 0 && Rs < Rt) {
+ MCInst_setOpcode(MI, Mips_BEQC);
+ HasRs = true;
+ } else
+ MCInst_setOpcode(MI, Mips_BEQZALC);
+
+ if (HasRs)
+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
+
+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
+ MCOperand_CreateImm0(MI, Imm);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, uint32_t insn,
+ uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
+ // (otherwise we would have matched the ADDI instruction from the earlier
+ // ISA's instead).
+ //
+ // We have:
+ // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
+ // BNVC if rs >= rt
+ // BNEZALC if rs == 0 && rt != 0
+ // BNEC if rs < rt && rs != 0
+
+ uint32_t Rs = fieldFromInstruction(insn, 21, 5);
+ uint32_t Rt = fieldFromInstruction(insn, 16, 5);
+ uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
+ bool HasRs = false;
+
+ if (Rs >= Rt) {
+ MCInst_setOpcode(MI, Mips_BNVC);
+ HasRs = true;
+ } else if (Rs != 0 && Rs < Rt) {
+ MCInst_setOpcode(MI, Mips_BNEC);
+ HasRs = true;
+ } else
+ MCInst_setOpcode(MI, Mips_BNEZALC);
+
+ if (HasRs)
+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
+
+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
+ MCOperand_CreateImm0(MI, Imm);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, uint32_t insn,
+ uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
+ // (otherwise we would have matched the BLEZL instruction from the earlier
+ // ISA's instead).
+ //
+ // We have:
+ // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
+ // Invalid if rs == 0
+ // BLEZC if rs == 0 && rt != 0
+ // BGEZC if rs == rt && rt != 0
+ // BGEC if rs != rt && rs != 0 && rt != 0
+
+ uint32_t Rs = fieldFromInstruction(insn, 21, 5);
+ uint32_t Rt = fieldFromInstruction(insn, 16, 5);
+ uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
+ bool HasRs = false;
+
+ if (Rt == 0)
+ return MCDisassembler_Fail;
+ else if (Rs == 0)
+ MCInst_setOpcode(MI, Mips_BLEZC);
+ else if (Rs == Rt)
+ MCInst_setOpcode(MI, Mips_BGEZC);
+ else {
+ HasRs = true;
+ MCInst_setOpcode(MI, Mips_BGEC);
+ }
+
+ if (HasRs)
+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
+
+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
+
+ MCOperand_CreateImm0(MI, Imm);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, uint32_t insn,
+ uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
+ // (otherwise we would have matched the BGTZL instruction from the earlier
+ // ISA's instead).
+ //
+ // We have:
+ // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
+ // Invalid if rs == 0
+ // BGTZC if rs == 0 && rt != 0
+ // BLTZC if rs == rt && rt != 0
+ // BLTC if rs != rt && rs != 0 && rt != 0
+
+ bool HasRs = false;
+
+ uint32_t Rs = fieldFromInstruction(insn, 21, 5);
+ uint32_t Rt = fieldFromInstruction(insn, 16, 5);
+ uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
+
+ if (Rt == 0)
+ return MCDisassembler_Fail;
+ else if (Rs == 0)
+ MCInst_setOpcode(MI, Mips_BGTZC);
+ else if (Rs == Rt)
+ MCInst_setOpcode(MI, Mips_BLTZC);
+ else {
+ MCInst_setOpcode(MI, Mips_BLTC);
+ HasRs = true;
+ }
+
+ if (HasRs)
+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
+
+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
+ MCOperand_CreateImm0(MI, Imm);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, uint32_t insn,
+ uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
+ // (otherwise we would have matched the BGTZ instruction from the earlier
+ // ISA's instead).
+ //
+ // We have:
+ // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
+ // BGTZ if rt == 0
+ // BGTZALC if rs == 0 && rt != 0
+ // BLTZALC if rs != 0 && rs == rt
+ // BLTUC if rs != 0 && rs != rt
+
+ uint32_t Rs = fieldFromInstruction(insn, 21, 5);
+ uint32_t Rt = fieldFromInstruction(insn, 16, 5);
+ uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
+ bool HasRs = false;
+ bool HasRt = false;
+
+ if (Rt == 0) {
+ MCInst_setOpcode(MI, Mips_BGTZ);
+ HasRs = true;
+ } else if (Rs == 0) {
+ MCInst_setOpcode(MI, Mips_BGTZALC);
+ HasRt = true;
+ } else if (Rs == Rt) {
+ MCInst_setOpcode(MI, Mips_BLTZALC);
+ HasRs = true;
+ } else {
+ MCInst_setOpcode(MI, Mips_BLTUC);
+ HasRs = true;
+ HasRt = true;
+ }
+
+ if (HasRs)
+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
+
+ if (HasRt)
+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
+
+ MCOperand_CreateImm0(MI, Imm);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, uint32_t insn,
+ uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
+ // (otherwise we would have matched the BLEZL instruction from the earlier
+ // ISA's instead).
+ //
+ // We have:
+ // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
+ // Invalid if rs == 0
+ // BLEZALC if rs == 0 && rt != 0
+ // BGEZALC if rs == rt && rt != 0
+ // BGEUC if rs != rt && rs != 0 && rt != 0
+
+ uint32_t Rs = fieldFromInstruction(insn, 21, 5);
+ uint32_t Rt = fieldFromInstruction(insn, 16, 5);
+ uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
+ bool HasRs = false;
+
+ if (Rt == 0)
+ return MCDisassembler_Fail;
+ else if (Rs == 0)
+ MCInst_setOpcode(MI, Mips_BLEZALC);
+ else if (Rs == Rt)
+ MCInst_setOpcode(MI, Mips_BGEZALC);
+ else {
+ HasRs = true;
+ MCInst_setOpcode(MI, Mips_BGEUC);
+ }
+
+ if (HasRs)
+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
+
+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
+
+ MCOperand_CreateImm0(MI, Imm);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ return MCDisassembler_Fail;
+}
+
+static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ unsigned Reg;
+
+ if (RegNo > 31)
+ return MCDisassembler_Fail;
+
+ Reg = getReg(Decoder, Mips_GPR64RegClassID, RegNo);
+ MCOperand_CreateReg0(Inst, Reg);
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+{
+ unsigned Reg;
+
+ if (RegNo > 7)
+ return MCDisassembler_Fail;
+
+ Reg = getReg(Decoder, Mips_GPRMM16RegClassID, RegNo);
+ MCOperand_CreateReg0(Inst, Reg);
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+{
+ unsigned Reg;
+
+ if (RegNo > 7)
+ return MCDisassembler_Fail;
+
+ Reg = getReg(Decoder, Mips_GPRMM16ZeroRegClassID, RegNo);
+ MCOperand_CreateReg0(Inst, Reg);
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+{
+ unsigned Reg;
+
+ if (RegNo > 7)
+ return MCDisassembler_Fail;
+
+ Reg = getReg(Decoder, Mips_GPRMM16MovePRegClassID, RegNo);
+ MCOperand_CreateReg0(Inst, Reg);
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ unsigned Reg;
+
+ if (RegNo > 31)
+ return MCDisassembler_Fail;
+
+ Reg = getReg(Decoder, Mips_GPR32RegClassID, RegNo);
+ MCOperand_CreateReg0(Inst, Reg);
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodePtrRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ // if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
+ if (Inst->csh->mode & CS_MODE_MIPS64)
+ return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
+
+ return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
+}
+
+static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
+}
+
+static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ unsigned Reg;
+
+ if (RegNo > 31)
+ return MCDisassembler_Fail;
+
+ Reg = getReg(Decoder, Mips_FGR64RegClassID, RegNo);
+ MCOperand_CreateReg0(Inst, Reg);
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ unsigned Reg;
+
+ if (RegNo > 31)
+ return MCDisassembler_Fail;
+
+ Reg = getReg(Decoder, Mips_FGR32RegClassID, RegNo);
+ MCOperand_CreateReg0(Inst, Reg);
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ unsigned Reg;
+
+ if (RegNo > 31)
+ return MCDisassembler_Fail;
+
+ Reg = getReg(Decoder, Mips_CCRRegClassID, RegNo);
+ MCOperand_CreateReg0(Inst, Reg);
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ unsigned Reg;
+
+ if (RegNo > 7)
+ return MCDisassembler_Fail;
+
+ Reg = getReg(Decoder, Mips_FCCRegClassID, RegNo);
+ MCOperand_CreateReg0(Inst, Reg);
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeCCRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ unsigned Reg;
+
+ if (RegNo > 7)
+ return MCDisassembler_Fail;
+
+ Reg = getReg(Decoder, Mips_CCRegClassID, RegNo);
+ MCOperand_CreateReg0(Inst, Reg);
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ unsigned Reg;
+
+ if (RegNo > 31)
+ return MCDisassembler_Fail;
+
+ Reg = getReg(Decoder, Mips_FGRCCRegClassID, RegNo);
+ MCOperand_CreateReg0(Inst, Reg);
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeMem(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ int Offset = SignExtend32(Insn & 0xffff, 16);
+ unsigned Reg = fieldFromInstruction(Insn, 16, 5);
+ unsigned Base = fieldFromInstruction(Insn, 21, 5);
+ int opcode = MCInst_getOpcode(Inst);
+
+ Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
+
+ if (opcode == Mips_SC || opcode == Mips_SCD) {
+ MCOperand_CreateReg0(Inst, Reg);
+ }
+
+ MCOperand_CreateReg0(Inst, Reg);
+ MCOperand_CreateReg0(Inst, Base);
+ MCOperand_CreateImm0(Inst, Offset);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeCacheOp(MCInst *Inst,
+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+{
+ int Offset = SignExtend32(Insn & 0xffff, 16);
+ unsigned Hint = fieldFromInstruction(Insn, 16, 5);
+ unsigned Base = fieldFromInstruction(Insn, 21, 5);
+
+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
+
+ MCOperand_CreateReg0(Inst, Base);
+ MCOperand_CreateImm0(Inst, Offset);
+ MCOperand_CreateImm0(Inst, Hint);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeCacheOpMM(MCInst *Inst,
+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+{
+ int Offset = SignExtend32(Insn & 0xfff, 12);
+ unsigned Base = fieldFromInstruction(Insn, 16, 5);
+ unsigned Hint = fieldFromInstruction(Insn, 21, 5);
+
+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
+
+ MCOperand_CreateReg0(Inst, Base);
+ MCOperand_CreateImm0(Inst, Offset);
+ MCOperand_CreateImm0(Inst, Hint);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeCacheOpR6(MCInst *Inst,
+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+{
+ int Offset = fieldFromInstruction(Insn, 7, 9);
+ unsigned Hint = fieldFromInstruction(Insn, 16, 5);
+ unsigned Base = fieldFromInstruction(Insn, 21, 5);
+
+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
+
+ MCOperand_CreateReg0(Inst, Base);
+ MCOperand_CreateImm0(Inst, Offset);
+ MCOperand_CreateImm0(Inst, Hint);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSyncI(MCInst *Inst,
+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+{
+ int Offset = SignExtend32(Insn & 0xffff, 16);
+ unsigned Base = fieldFromInstruction(Insn, 21, 5);
+
+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
+
+ MCOperand_CreateReg0(Inst, Base);
+ MCOperand_CreateImm0(Inst, Offset);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn,
+ uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ int Offset = SignExtend32(fieldFromInstruction(Insn, 16, 10), 10);
+ unsigned Reg = fieldFromInstruction(Insn, 6, 5);
+ unsigned Base = fieldFromInstruction(Insn, 11, 5);
+
+ Reg = getReg(Decoder, Mips_MSA128BRegClassID, Reg);
+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
+
+ MCOperand_CreateReg0(Inst, Reg);
+ MCOperand_CreateReg0(Inst, Base);
+ // MCOperand_CreateImm0(Inst, Offset);
+
+ // The immediate field of an LD/ST instruction is scaled which means it must
+ // be multiplied (when decoding) by the size (in bytes) of the instructions'
+ // data format.
+ // .b - 1 byte
+ // .h - 2 bytes
+ // .w - 4 bytes
+ // .d - 8 bytes
+ switch(MCInst_getOpcode(Inst)) {
+ default:
+ //assert (0 && "Unexpected instruction");
+ return MCDisassembler_Fail;
+ break;
+ case Mips_LD_B:
+ case Mips_ST_B:
+ MCOperand_CreateImm0(Inst, Offset);
+ break;
+ case Mips_LD_H:
+ case Mips_ST_H:
+ MCOperand_CreateImm0(Inst, Offset * 2);
+ break;
+ case Mips_LD_W:
+ case Mips_ST_W:
+ MCOperand_CreateImm0(Inst, Offset * 4);
+ break;
+ case Mips_LD_D:
+ case Mips_ST_D:
+ MCOperand_CreateImm0(Inst, Offset * 8);
+ break;
+ }
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeMemMMImm4(MCInst *Inst,
+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+{
+ unsigned Offset = Insn & 0xf;
+ unsigned Reg = fieldFromInstruction(Insn, 7, 3);
+ unsigned Base = fieldFromInstruction(Insn, 4, 3);
+
+ switch (MCInst_getOpcode(Inst)) {
+ case Mips_LBU16_MM:
+ case Mips_LHU16_MM:
+ case Mips_LW16_MM:
+ if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
+ == MCDisassembler_Fail)
+ return MCDisassembler_Fail;
+ break;
+ case Mips_SB16_MM:
+ case Mips_SH16_MM:
+ case Mips_SW16_MM:
+ if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
+ == MCDisassembler_Fail)
+ return MCDisassembler_Fail;
+ break;
+ }
+
+ if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
+ == MCDisassembler_Fail)
+ return MCDisassembler_Fail;
+
+ switch (MCInst_getOpcode(Inst)) {
+ case Mips_LBU16_MM:
+ if (Offset == 0xf)
+ MCOperand_CreateImm0(Inst, -1);
+ else
+ MCOperand_CreateImm0(Inst, Offset);
+ break;
+ case Mips_SB16_MM:
+ MCOperand_CreateImm0(Inst, Offset);
+ break;
+ case Mips_LHU16_MM:
+ case Mips_SH16_MM:
+ MCOperand_CreateImm0(Inst, Offset << 1);
+ break;
+ case Mips_LW16_MM:
+ case Mips_SW16_MM:
+ MCOperand_CreateImm0(Inst, Offset << 2);
+ break;
+ }
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst,
+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+{
+ unsigned Offset = Insn & 0x1F;
+ unsigned Reg = fieldFromInstruction(Insn, 5, 5);
+
+ Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
+
+ MCOperand_CreateReg0(Inst, Reg);
+ MCOperand_CreateReg0(Inst, Mips_SP);
+ MCOperand_CreateImm0(Inst, Offset << 2);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst,
+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+{
+ unsigned Offset = Insn & 0x7F;
+ unsigned Reg = fieldFromInstruction(Insn, 7, 3);
+
+ Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
+
+ MCOperand_CreateReg0(Inst, Reg);
+ MCOperand_CreateReg0(Inst, Mips_GP);
+ MCOperand_CreateImm0(Inst, Offset << 2);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst,
+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+{
+ int Offset = SignExtend32(Insn & 0xf, 4);
+
+ if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) == MCDisassembler_Fail)
+ return MCDisassembler_Fail;
+
+ MCOperand_CreateReg0(Inst, Mips_SP);
+ MCOperand_CreateImm0(Inst, Offset * 4);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeMemMMImm12(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ int Offset = SignExtend32(Insn & 0x0fff, 12);
+ unsigned Reg = fieldFromInstruction(Insn, 21, 5);
+ unsigned Base = fieldFromInstruction(Insn, 16, 5);
+
+ Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
+
+ switch (MCInst_getOpcode(Inst)) {
+ case Mips_SWM32_MM:
+ case Mips_LWM32_MM:
+ if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
+ == MCDisassembler_Fail)
+ return MCDisassembler_Fail;
+ MCOperand_CreateReg0(Inst, Base);
+ MCOperand_CreateImm0(Inst, Offset);
+ break;
+ case Mips_SC_MM:
+ MCOperand_CreateReg0(Inst, Reg);
+ // fallthrough
+ default:
+ MCOperand_CreateReg0(Inst, Reg);
+ if (MCInst_getOpcode(Inst) == Mips_LWP_MM || MCInst_getOpcode(Inst) == Mips_SWP_MM)
+ MCOperand_CreateReg0(Inst, Reg + 1);
+
+ MCOperand_CreateReg0(Inst, Base);
+ MCOperand_CreateImm0(Inst, Offset);
+ }
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeMemMMImm16(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ int Offset = SignExtend32(Insn & 0xffff, 16);
+ unsigned Reg = fieldFromInstruction(Insn, 21, 5);
+ unsigned Base = fieldFromInstruction(Insn, 16, 5);
+
+ Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
+
+ MCOperand_CreateReg0(Inst, Reg);
+ MCOperand_CreateReg0(Inst, Base);
+ MCOperand_CreateImm0(Inst, Offset);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeFMem(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ int Offset = SignExtend32(Insn & 0xffff, 16);
+ unsigned Reg = fieldFromInstruction(Insn, 16, 5);
+ unsigned Base = fieldFromInstruction(Insn, 21, 5);
+
+ Reg = getReg(Decoder, Mips_FGR64RegClassID, Reg);
+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
+
+ MCOperand_CreateReg0(Inst, Reg);
+ MCOperand_CreateReg0(Inst, Base);
+ MCOperand_CreateImm0(Inst, Offset);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeFMem2(MCInst *Inst,
+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+{
+ int Offset = SignExtend32(Insn & 0xffff, 16);
+ unsigned Reg = fieldFromInstruction(Insn, 16, 5);
+ unsigned Base = fieldFromInstruction(Insn, 21, 5);
+
+ Reg = getReg(Decoder, Mips_COP2RegClassID, Reg);
+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
+
+ MCOperand_CreateReg0(Inst, Reg);
+ MCOperand_CreateReg0(Inst, Base);
+ MCOperand_CreateImm0(Inst, Offset);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeFMem3(MCInst *Inst,
+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+{
+ int Offset = SignExtend32(Insn & 0xffff, 16);
+ unsigned Reg = fieldFromInstruction(Insn, 16, 5);
+ unsigned Base = fieldFromInstruction(Insn, 21, 5);
+
+ Reg = getReg(Decoder, Mips_COP3RegClassID, Reg);
+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
+
+ MCOperand_CreateReg0(Inst, Reg);
+ MCOperand_CreateReg0(Inst, Base);
+ MCOperand_CreateImm0(Inst, Offset);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeFMemCop2R6(MCInst *Inst,
+ unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+{
+ int Offset = SignExtend32(Insn & 0x07ff, 11);
+ unsigned Reg = fieldFromInstruction(Insn, 16, 5);
+ unsigned Base = fieldFromInstruction(Insn, 11, 5);
+
+ Reg = getReg(Decoder, Mips_COP2RegClassID, Reg);
+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
+
+ MCOperand_CreateReg0(Inst, Reg);
+ MCOperand_CreateReg0(Inst, Base);
+ MCOperand_CreateImm0(Inst, Offset);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ int64_t Offset = SignExtend64((Insn >> 7) & 0x1ff, 9);
+ unsigned Rt = fieldFromInstruction(Insn, 16, 5);
+ unsigned Base = fieldFromInstruction(Insn, 21, 5);
+
+ Rt = getReg(Decoder, Mips_GPR32RegClassID, Rt);
+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
+
+ if (MCInst_getOpcode(Inst) == Mips_SC_R6 ||
+ MCInst_getOpcode(Inst) == Mips_SCD_R6) {
+ MCOperand_CreateReg0(Inst, Rt);
+ }
+
+ MCOperand_CreateReg0(Inst, Rt);
+ MCOperand_CreateReg0(Inst, Base);
+ MCOperand_CreateImm0(Inst, Offset);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ // Currently only hardware register 29 is supported.
+ if (RegNo != 29)
+ return MCDisassembler_Fail;
+
+ MCOperand_CreateReg0(Inst, Mips_HWR29);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ unsigned Reg;
+
+ if (RegNo > 30 || RegNo % 2)
+ return MCDisassembler_Fail;
+
+ Reg = getReg(Decoder, Mips_AFGR64RegClassID, RegNo /2);
+ MCOperand_CreateReg0(Inst, Reg);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ unsigned Reg;
+
+ if (RegNo >= 4)
+ return MCDisassembler_Fail;
+
+ Reg = getReg(Decoder, Mips_ACC64DSPRegClassID, RegNo);
+ MCOperand_CreateReg0(Inst, Reg);
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ unsigned Reg;
+
+ if (RegNo >= 4)
+ return MCDisassembler_Fail;
+
+ Reg = getReg(Decoder, Mips_HI32DSPRegClassID, RegNo);
+ MCOperand_CreateReg0(Inst, Reg);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ unsigned Reg;
+
+ if (RegNo >= 4)
+ return MCDisassembler_Fail;
+
+ Reg = getReg(Decoder, Mips_LO32DSPRegClassID, RegNo);
+ MCOperand_CreateReg0(Inst, Reg);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ unsigned Reg;
+
+ if (RegNo > 31)
+ return MCDisassembler_Fail;
+
+ Reg = getReg(Decoder, Mips_MSA128BRegClassID, RegNo);
+ MCOperand_CreateReg0(Inst, Reg);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ unsigned Reg;
+
+ if (RegNo > 31)
+ return MCDisassembler_Fail;
+
+ Reg = getReg(Decoder, Mips_MSA128HRegClassID, RegNo);
+ MCOperand_CreateReg0(Inst, Reg);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ unsigned Reg;
+
+ if (RegNo > 31)
+ return MCDisassembler_Fail;
+
+ Reg = getReg(Decoder, Mips_MSA128WRegClassID, RegNo);
+ MCOperand_CreateReg0(Inst, Reg);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ unsigned Reg;
+
+ if (RegNo > 31)
+ return MCDisassembler_Fail;
+
+ Reg = getReg(Decoder, Mips_MSA128DRegClassID, RegNo);
+ MCOperand_CreateReg0(Inst, Reg);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ unsigned Reg;
+
+ if (RegNo > 7)
+ return MCDisassembler_Fail;
+
+ Reg = getReg(Decoder, Mips_MSACtrlRegClassID, RegNo);
+ MCOperand_CreateReg0(Inst, Reg);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst,
+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ unsigned Reg;
+
+ if (RegNo > 31)
+ return MCDisassembler_Fail;
+
+ Reg = getReg(Decoder, Mips_COP2RegClassID, RegNo);
+ MCOperand_CreateReg0(Inst, Reg);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBranchTarget(MCInst *Inst,
+ unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ uint64_t TargetAddress = (SignExtend32(Offset, 16) * 4) + Address + 4;
+ MCOperand_CreateImm0(Inst, TargetAddress);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeJumpTarget(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ uint64_t TargetAddress = (fieldFromInstruction(Insn, 0, 26) << 2) | ((Address + 4) & ~0x0FFFFFFF);
+ MCOperand_CreateImm0(Inst, TargetAddress);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBranchTarget21(MCInst *Inst,
+ unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ int32_t BranchOffset = SignExtend32(Offset, 21) * 4;
+
+ MCOperand_CreateImm0(Inst, BranchOffset);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBranchTarget26(MCInst *Inst,
+ unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ int32_t BranchOffset = SignExtend32(Offset, 26) * 4;
+
+ MCOperand_CreateImm0(Inst, BranchOffset);
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst,
+ unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
+{
+ int32_t BranchOffset = SignExtend32(Offset, 7) * 2;
+ MCOperand_CreateImm0(Inst, BranchOffset);
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst,
+ unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
+{
+ int32_t BranchOffset = SignExtend32(Offset, 10) * 2;
+ MCOperand_CreateImm0(Inst, BranchOffset);
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBranchTargetMM(MCInst *Inst,
+ unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ int32_t BranchOffset = SignExtend32(Offset, 16) * 2;
+ MCOperand_CreateImm0(Inst, BranchOffset);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeJumpTargetMM(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
+ MCOperand_CreateImm0(Inst, JumpOffset);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst,
+ unsigned Value, uint64_t Address, MCRegisterInfo *Decoder)
+{
+ if (Value == 0)
+ MCOperand_CreateImm0(Inst, 1);
+ else if (Value == 0x7)
+ MCOperand_CreateImm0(Inst, -1);
+ else
+ MCOperand_CreateImm0(Inst, Value << 2);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst,
+ unsigned Value, uint64_t Address, MCRegisterInfo *Decoder)
+{
+ MCOperand_CreateImm0(Inst, Value << 2);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeLiSimm7(MCInst *Inst,
+ unsigned Value, uint64_t Address, MCRegisterInfo *Decoder)
+{
+ if (Value == 0x7F)
+ MCOperand_CreateImm0(Inst, -1);
+ else
+ MCOperand_CreateImm0(Inst, Value);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSimm4(MCInst *Inst,
+ unsigned Value, uint64_t Address, MCRegisterInfo *Decoder)
+{
+ MCOperand_CreateImm0(Inst, SignExtend32(Value, 4));
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSimm16(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ MCOperand_CreateImm0(Inst, SignExtend32(Insn, 16));
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeLSAImm(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ // We add one to the immediate field as it was encoded as 'imm - 1'.
+ MCOperand_CreateImm0(Inst, Insn + 1);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeInsSize(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ // First we need to grab the pos(lsb) from MCInst.
+ int Pos = (int)MCOperand_getImm(MCInst_getOperand(Inst, 2));
+ int Size = (int) Insn - Pos + 1;
+ MCOperand_CreateImm0(Inst, SignExtend32(Size, 16));
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeExtSize(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ int Size = (int)Insn + 1;
+
+ MCOperand_CreateImm0(Inst, SignExtend32(Size, 16));
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ MCOperand_CreateImm0(Inst, SignExtend32(Insn, 19) * 4);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst,
+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ MCOperand_CreateImm0(Inst, SignExtend32(Insn, 18) * 8);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSimm9SP(MCInst *Inst, unsigned Insn,
+ uint64_t Address, MCRegisterInfo *Decoder)
+{
+ int32_t DecodedValue;
+
+ switch (Insn) {
+ case 0: DecodedValue = 256; break;
+ case 1: DecodedValue = 257; break;
+ case 510: DecodedValue = -258; break;
+ case 511: DecodedValue = -257; break;
+ default: DecodedValue = SignExtend32(Insn, 9); break;
+ }
+ MCOperand_CreateImm0(Inst, DecodedValue * 4);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeANDI16Imm(MCInst *Inst, unsigned Insn,
+ uint64_t Address, MCRegisterInfo *Decoder)
+{
+ // Insn must be >= 0, since it is unsigned that condition is always true.
+ // assert(Insn < 16);
+ int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
+ 255, 32768, 65535};
+
+ if (Insn >= 16)
+ return MCDisassembler_Fail;
+
+ MCOperand_CreateImm0(Inst, DecodedValues[Insn]);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeUImm5lsl2(MCInst *Inst, unsigned Insn,
+ uint64_t Address, MCRegisterInfo *Decoder)
+{
+ MCOperand_CreateImm0(Inst, Insn << 2);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Insn,
+ uint64_t Address, const MCRegisterInfo *Decoder)
+{
+ unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5,
+ Mips_S6, Mips_FP};
+ unsigned RegNum;
+ unsigned int i;
+
+ unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
+ // Empty register lists are not allowed.
+ if (RegLst == 0)
+ return MCDisassembler_Fail;
+
+ RegNum = RegLst & 0xf;
+ for (i = 0; i < MIN(RegNum, ARR_SIZE(Regs)); i++)
+ MCOperand_CreateReg0(Inst, Regs[i]);
+
+ if (RegLst & 0x10)
+ MCOperand_CreateReg0(Inst, Mips_RA);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRegListOperand16(MCInst *Inst, unsigned Insn,
+ uint64_t Address, MCRegisterInfo *Decoder)
+{
+ unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3};
+ unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
+ unsigned RegNum = RegLst & 0x3;
+ unsigned int i;
+
+ for (i = 0; i <= RegNum; i++)
+ MCOperand_CreateReg0(Inst, Regs[i]);
+
+ MCOperand_CreateReg0(Inst, Mips_RA);
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeMovePRegPair(MCInst *Inst, unsigned Insn,
+ uint64_t Address, MCRegisterInfo *Decoder)
+{
+ unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
+
+ switch (RegPair) {
+ default:
+ return MCDisassembler_Fail;
+ case 0:
+ MCOperand_CreateReg0(Inst, Mips_A1);
+ MCOperand_CreateReg0(Inst, Mips_A2);
+ break;
+ case 1:
+ MCOperand_CreateReg0(Inst, Mips_A1);
+ MCOperand_CreateReg0(Inst, Mips_A3);
+ break;
+ case 2:
+ MCOperand_CreateReg0(Inst, Mips_A2);
+ MCOperand_CreateReg0(Inst, Mips_A3);
+ break;
+ case 3:
+ MCOperand_CreateReg0(Inst, Mips_A0);
+ MCOperand_CreateReg0(Inst, Mips_S5);
+ break;
+ case 4:
+ MCOperand_CreateReg0(Inst, Mips_A0);
+ MCOperand_CreateReg0(Inst, Mips_S6);
+ break;
+ case 5:
+ MCOperand_CreateReg0(Inst, Mips_A0);
+ MCOperand_CreateReg0(Inst, Mips_A1);
+ break;
+ case 6:
+ MCOperand_CreateReg0(Inst, Mips_A0);
+ MCOperand_CreateReg0(Inst, Mips_A2);
+ break;
+ case 7:
+ MCOperand_CreateReg0(Inst, Mips_A0);
+ MCOperand_CreateReg0(Inst, Mips_A3);
+ break;
+ }
+
+ return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, unsigned Insn,
+ uint64_t Address, MCRegisterInfo *Decoder)
+{
+ MCOperand_CreateImm0(Inst, SignExtend32(Insn, 23) * 4);
+ return MCDisassembler_Success;
+}
+
+#endif
diff --git a/capstone/arch/Mips/MipsDisassembler.h b/capstone/arch/Mips/MipsDisassembler.h
new file mode 100644
index 000000000..961c5f1ae
--- /dev/null
+++ b/capstone/arch/Mips/MipsDisassembler.h
@@ -0,0 +1,16 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_MIPSDISASSEMBLER_H
+#define CS_MIPSDISASSEMBLER_H
+
+#include "capstone/capstone.h"
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+
+void Mips_init(MCRegisterInfo *MRI);
+
+bool Mips_getInstruction(csh handle, const uint8_t *code, size_t code_len,
+ MCInst *instr, uint16_t *size, uint64_t address, void *info);
+
+#endif
diff --git a/capstone/arch/Mips/MipsGenAsmWriter.inc b/capstone/arch/Mips/MipsGenAsmWriter.inc
new file mode 100644
index 000000000..cd252131f
--- /dev/null
+++ b/capstone/arch/Mips/MipsGenAsmWriter.inc
@@ -0,0 +1,5725 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|*Assembly Writer Source Fragment *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+/// printInstruction - This method is automatically generated by tablegen
+/// from the instruction set description.
+static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)
+{
+ static const uint32_t OpInfo[] = {
+ 0U, // PHI
+ 0U, // INLINEASM
+ 0U, // CFI_INSTRUCTION
+ 0U, // EH_LABEL
+ 0U, // GC_LABEL
+ 0U, // KILL
+ 0U, // EXTRACT_SUBREG
+ 0U, // INSERT_SUBREG
+ 0U, // IMPLICIT_DEF
+ 0U, // SUBREG_TO_REG
+ 0U, // COPY_TO_REGCLASS
+ 9396U, // DBG_VALUE
+ 0U, // REG_SEQUENCE
+ 0U, // COPY
+ 9389U, // BUNDLE
+ 9406U, // LIFETIME_START
+ 9376U, // LIFETIME_END
+ 0U, // STACKMAP
+ 0U, // PATCHPOINT
+ 0U, // LOAD_STACK_GUARD
+ 0U, // STATEPOINT
+ 0U, // FRAME_ALLOC
+ 21660U, // ABSQ_S_PH
+ 18025U, // ABSQ_S_QB
+ 24850U, // ABSQ_S_W
+ 134237992U, // ADD
+ 18294U, // ADDIUPC
+ 18294U, // ADDIUPC_MM
+ 22527U, // ADDIUR1SP_MM
+ 134234410U, // ADDIUR2_MM
+ 8683851U, // ADDIUS5_MM
+ 546875U, // ADDIUSP_MM
+ 134239193U, // ADDQH_PH
+ 134239310U, // ADDQH_R_PH
+ 134242253U, // ADDQH_R_W
+ 134241856U, // ADDQH_W
+ 134239267U, // ADDQ_PH
+ 134239366U, // ADDQ_S_PH
+ 134242558U, // ADDQ_S_W
+ 134236055U, // ADDSC
+ 134234730U, // ADDS_A_B
+ 134236180U, // ADDS_A_D
+ 134238138U, // ADDS_A_H
+ 134241564U, // ADDS_A_W
+ 134235198U, // ADDS_S_B
+ 134237269U, // ADDS_S_D
+ 134238695U, // ADDS_S_H
+ 134242608U, // ADDS_S_W
+ 134235413U, // ADDS_U_B
+ 134237736U, // ADDS_U_D
+ 134238973U, // ADDS_U_H
+ 134243026U, // ADDS_U_W
+ 134234575U, // ADDU16_MM
+ 134235621U, // ADDUH_QB
+ 134235729U, // ADDUH_R_QB
+ 134239465U, // ADDU_PH
+ 134235834U, // ADDU_QB
+ 134239410U, // ADDU_S_PH
+ 134235775U, // ADDU_S_QB
+ 2281718627U, // ADDVI_B
+ 2281720348U, // ADDVI_D
+ 2281722002U, // ADDVI_H
+ 2281725637U, // ADDVI_W
+ 134235491U, // ADDV_B
+ 134237836U, // ADDV_D
+ 134239051U, // ADDV_H
+ 134243126U, // ADDV_W
+ 134236094U, // ADDWC
+ 134234712U, // ADD_A_B
+ 134236161U, // ADD_A_D
+ 134238120U, // ADD_A_H
+ 134241545U, // ADD_A_W
+ 134237992U, // ADD_MM
+ 134239685U, // ADDi
+ 134239685U, // ADDi_MM
+ 134241307U, // ADDiu
+ 134241307U, // ADDiu_MM
+ 134241261U, // ADDu
+ 134241261U, // ADDu_MM
+ 0U, // ADJCALLSTACKDOWN
+ 0U, // ADJCALLSTACKUP
+ 134240158U, // ALIGN
+ 18286U, // ALUIPC
+ 134238014U, // AND
+ 835930U, // AND16_MM
+ 134238014U, // AND64
+ 134234471U, // ANDI16_MM
+ 2281718486U, // ANDI_B
+ 134238014U, // AND_MM
+ 134241389U, // AND_V
+ 0U, // AND_V_D_PSEUDO
+ 0U, // AND_V_H_PSEUDO
+ 0U, // AND_V_W_PSEUDO
+ 134239691U, // ANDi
+ 134239691U, // ANDi64
+ 134239691U, // ANDi_MM
+ 134238028U, // APPEND
+ 134235092U, // ASUB_S_B
+ 134237099U, // ASUB_S_D
+ 134238527U, // ASUB_S_H
+ 134242388U, // ASUB_S_W
+ 134235307U, // ASUB_U_B
+ 134237566U, // ASUB_U_D
+ 134238815U, // ASUB_U_H
+ 134242856U, // ASUB_U_W
+ 0U, // ATOMIC_CMP_SWAP_I16
+ 0U, // ATOMIC_CMP_SWAP_I32
+ 0U, // ATOMIC_CMP_SWAP_I64
+ 0U, // ATOMIC_CMP_SWAP_I8
+ 0U, // ATOMIC_LOAD_ADD_I16
+ 0U, // ATOMIC_LOAD_ADD_I32
+ 0U, // ATOMIC_LOAD_ADD_I64
+ 0U, // ATOMIC_LOAD_ADD_I8
+ 0U, // ATOMIC_LOAD_AND_I16
+ 0U, // ATOMIC_LOAD_AND_I32
+ 0U, // ATOMIC_LOAD_AND_I64
+ 0U, // ATOMIC_LOAD_AND_I8
+ 0U, // ATOMIC_LOAD_NAND_I16
+ 0U, // ATOMIC_LOAD_NAND_I32
+ 0U, // ATOMIC_LOAD_NAND_I64
+ 0U, // ATOMIC_LOAD_NAND_I8
+ 0U, // ATOMIC_LOAD_OR_I16
+ 0U, // ATOMIC_LOAD_OR_I32
+ 0U, // ATOMIC_LOAD_OR_I64
+ 0U, // ATOMIC_LOAD_OR_I8
+ 0U, // ATOMIC_LOAD_SUB_I16
+ 0U, // ATOMIC_LOAD_SUB_I32
+ 0U, // ATOMIC_LOAD_SUB_I64
+ 0U, // ATOMIC_LOAD_SUB_I8
+ 0U, // ATOMIC_LOAD_XOR_I16
+ 0U, // ATOMIC_LOAD_XOR_I32
+ 0U, // ATOMIC_LOAD_XOR_I64
+ 0U, // ATOMIC_LOAD_XOR_I8
+ 0U, // ATOMIC_SWAP_I16
+ 0U, // ATOMIC_SWAP_I32
+ 0U, // ATOMIC_SWAP_I64
+ 0U, // ATOMIC_SWAP_I8
+ 134239795U, // AUI
+ 18279U, // AUIPC
+ 134235178U, // AVER_S_B
+ 134237249U, // AVER_S_D
+ 134238665U, // AVER_S_H
+ 134242588U, // AVER_S_W
+ 134235393U, // AVER_U_B
+ 134237716U, // AVER_U_D
+ 134238953U, // AVER_U_H
+ 134243006U, // AVER_U_W
+ 134235120U, // AVE_S_B
+ 134237181U, // AVE_S_D
+ 134238597U, // AVE_S_H
+ 134242470U, // AVE_S_W
+ 134235335U, // AVE_U_B
+ 134237648U, // AVE_U_D
+ 134238885U, // AVE_U_H
+ 134242938U, // AVE_U_W
+ 23579U, // AddiuRxImmX16
+ 1072155U, // AddiuRxPcImmX16
+ 285236251U, // AddiuRxRxImm16
+ 16800795U, // AddiuRxRxImmX16
+ 25189403U, // AddiuRxRyOffMemX16
+ 1336343U, // AddiuSpImm16
+ 549911U, // AddiuSpImmX16
+ 134241261U, // AdduRxRyRz16
+ 16797502U, // AndRxRxRy16
+ 0U, // B
+ 541013U, // B16_MM
+ 134241260U, // BADDu
+ 546393U, // BAL
+ 542494U, // BALC
+ 134240157U, // BALIGN
+ 0U, // BAL_BR
+ 167788585U, // BBIT0
+ 167788717U, // BBIT032
+ 167788710U, // BBIT1
+ 167788726U, // BBIT132
+ 542473U, // BC
+ 20351U, // BC0F
+ 22218U, // BC0FL
+ 23455U, // BC0T
+ 22347U, // BC0TL
+ 25733U, // BC1EQZ
+ 20357U, // BC1F
+ 22225U, // BC1FL
+ 20357U, // BC1F_MM
+ 25717U, // BC1NEZ
+ 23461U, // BC1T
+ 22354U, // BC1TL
+ 23461U, // BC1T_MM
+ 25741U, // BC2EQZ
+ 20363U, // BC2F
+ 22232U, // BC2FL
+ 25725U, // BC2NEZ
+ 23467U, // BC2T
+ 22361U, // BC2TL
+ 20369U, // BC3F
+ 22239U, // BC3FL
+ 23473U, // BC3T
+ 22368U, // BC3TL
+ 2281718555U, // BCLRI_B
+ 2281720292U, // BCLRI_D
+ 2281721946U, // BCLRI_H
+ 2281725581U, // BCLRI_W
+ 134235059U, // BCLR_B
+ 134237023U, // BCLR_D
+ 134238494U, // BCLR_H
+ 134242304U, // BCLR_W
+ 134240340U, // BEQ
+ 134240340U, // BEQ64
+ 134236044U, // BEQC
+ 134240063U, // BEQL
+ 16882U, // BEQZ16_MM
+ 18246U, // BEQZALC
+ 18394U, // BEQZC
+ 18394U, // BEQZC_MM
+ 134240340U, // BEQ_MM
+ 134235917U, // BGEC
+ 134236068U, // BGEUC
+ 25500U, // BGEZ
+ 25500U, // BGEZ64
+ 22115U, // BGEZAL
+ 18219U, // BGEZALC
+ 22311U, // BGEZALL
+ 23424U, // BGEZALS_MM
+ 22115U, // BGEZAL_MM
+ 18373U, // BGEZC
+ 22391U, // BGEZL
+ 25500U, // BGEZ_MM
+ 25560U, // BGTZ
+ 25560U, // BGTZ64
+ 18255U, // BGTZALC
+ 18401U, // BGTZC
+ 22405U, // BGTZL
+ 25560U, // BGTZ_MM
+ 2298495744U, // BINSLI_B
+ 2298497481U, // BINSLI_D
+ 2298499135U, // BINSLI_H
+ 2298502770U, // BINSLI_W
+ 151012243U, // BINSL_B
+ 151014033U, // BINSL_D
+ 151015601U, // BINSL_H
+ 151019280U, // BINSL_W
+ 2298495805U, // BINSRI_B
+ 2298497526U, // BINSRI_D
+ 2298499180U, // BINSRI_H
+ 2298502815U, // BINSRI_W
+ 151012291U, // BINSR_B
+ 151014289U, // BINSR_D
+ 151015726U, // BINSR_H
+ 151019570U, // BINSR_W
+ 23733U, // BITREV
+ 22477U, // BITSWAP
+ 25506U, // BLEZ
+ 25506U, // BLEZ64
+ 18228U, // BLEZALC
+ 18380U, // BLEZC
+ 22398U, // BLEZL
+ 25506U, // BLEZ_MM
+ 134236062U, // BLTC
+ 134236075U, // BLTUC
+ 25566U, // BLTZ
+ 25566U, // BLTZ64
+ 22123U, // BLTZAL
+ 18264U, // BLTZALC
+ 22320U, // BLTZALL
+ 23433U, // BLTZALS_MM
+ 22123U, // BLTZAL_MM
+ 18408U, // BLTZC
+ 22412U, // BLTZL
+ 25566U, // BLTZ_MM
+ 2298495860U, // BMNZI_B
+ 151018662U, // BMNZ_V
+ 2298495852U, // BMZI_B
+ 151018648U, // BMZ_V
+ 134238058U, // BNE
+ 134238058U, // BNE64
+ 134235923U, // BNEC
+ 2281718494U, // BNEGI_B
+ 2281720240U, // BNEGI_D
+ 2281721894U, // BNEGI_H
+ 2281725529U, // BNEGI_W
+ 134234814U, // BNEG_B
+ 134236568U, // BNEG_D
+ 134238222U, // BNEG_H
+ 134241776U, // BNEG_W
+ 134239940U, // BNEL
+ 16874U, // BNEZ16_MM
+ 18237U, // BNEZALC
+ 18387U, // BNEZC
+ 18387U, // BNEZC_MM
+ 134238058U, // BNE_MM
+ 134236082U, // BNVC
+ 17803U, // BNZ_B
+ 20233U, // BNZ_D
+ 21363U, // BNZ_H
+ 23711U, // BNZ_V
+ 25463U, // BNZ_W
+ 134236088U, // BOVC
+ 540871U, // BPOSGE32
+ 0U, // BPOSGE32_PSEUDO
+ 22080U, // BREAK
+ 65909U, // BREAK16_MM
+ 22080U, // BREAK_MM
+ 2298495719U, // BSELI_B
+ 0U, // BSEL_D_PSEUDO
+ 0U, // BSEL_FD_PSEUDO
+ 0U, // BSEL_FW_PSEUDO
+ 0U, // BSEL_H_PSEUDO
+ 151018620U, // BSEL_V
+ 0U, // BSEL_W_PSEUDO
+ 2281718609U, // BSETI_B
+ 2281720330U, // BSETI_D
+ 2281721984U, // BSETI_H
+ 2281725619U, // BSETI_W
+ 134235275U, // BSET_B
+ 134237385U, // BSET_D
+ 134238783U, // BSET_H
+ 134242762U, // BSET_W
+ 17797U, // BZ_B
+ 20217U, // BZ_D
+ 21357U, // BZ_H
+ 23698U, // BZ_V
+ 25457U, // BZ_W
+ 541278U, // B_MM_Pseudo
+ 402678723U, // BeqzRxImm16
+ 25539U, // BeqzRxImmX16
+ 1327710U, // Bimm16
+ 541278U, // BimmX16
+ 402678696U, // BnezRxImm16
+ 25512U, // BnezRxImmX16
+ 9368U, // Break16
+ 1598417U, // Bteqz16
+ 536893428U, // BteqzT8CmpX16
+ 536892936U, // BteqzT8CmpiX16
+ 536894397U, // BteqzT8SltX16
+ 536892966U, // BteqzT8SltiX16
+ 536894505U, // BteqzT8SltiuX16
+ 536894541U, // BteqzT8SltuX16
+ 549841U, // BteqzX16
+ 1598390U, // Btnez16
+ 671111156U, // BtnezT8CmpX16
+ 671110664U, // BtnezT8CmpiX16
+ 671112125U, // BtnezT8SltX16
+ 671110694U, // BtnezT8SltiX16
+ 671112233U, // BtnezT8SltiuX16
+ 671112269U, // BtnezT8SltuX16
+ 549814U, // BtnezX16
+ 0U, // BuildPairF64
+ 0U, // BuildPairF64_64
+ 85859U, // CACHE
+ 85859U, // CACHE_MM
+ 85859U, // CACHE_R6
+ 19003U, // CEIL_L_D64
+ 23031U, // CEIL_L_S
+ 20179U, // CEIL_W_D32
+ 20179U, // CEIL_W_D64
+ 20179U, // CEIL_W_MM
+ 23353U, // CEIL_W_S
+ 23353U, // CEIL_W_S_MM
+ 134234890U, // CEQI_B
+ 134236627U, // CEQI_D
+ 134238281U, // CEQI_H
+ 134241916U, // CEQI_W
+ 134235044U, // CEQ_B
+ 134236930U, // CEQ_D
+ 134238472U, // CEQ_H
+ 134242192U, // CEQ_W
+ 16444U, // CFC1
+ 16444U, // CFC1_MM
+ 16968U, // CFCMSA
+ 134243407U, // CINS
+ 134243363U, // CINS32
+ 19639U, // CLASS_D
+ 23205U, // CLASS_S
+ 134235129U, // CLEI_S_B
+ 134237190U, // CLEI_S_D
+ 134238606U, // CLEI_S_H
+ 134242479U, // CLEI_S_W
+ 2281718992U, // CLEI_U_B
+ 2281721305U, // CLEI_U_D
+ 2281722542U, // CLEI_U_H
+ 2281726595U, // CLEI_U_W
+ 134235111U, // CLE_S_B
+ 134237172U, // CLE_S_D
+ 134238588U, // CLE_S_H
+ 134242461U, // CLE_S_W
+ 134235326U, // CLE_U_B
+ 134237639U, // CLE_U_D
+ 134238876U, // CLE_U_H
+ 134242929U, // CLE_U_W
+ 22452U, // CLO
+ 22452U, // CLO_MM
+ 22452U, // CLO_R6
+ 134235149U, // CLTI_S_B
+ 134237210U, // CLTI_S_D
+ 134238626U, // CLTI_S_H
+ 134242499U, // CLTI_S_W
+ 2281719012U, // CLTI_U_B
+ 2281721325U, // CLTI_U_D
+ 2281722562U, // CLTI_U_H
+ 2281726615U, // CLTI_U_W
+ 134235217U, // CLT_S_B
+ 134237288U, // CLT_S_D
+ 134238714U, // CLT_S_H
+ 134242627U, // CLT_S_W
+ 134235444U, // CLT_U_B
+ 134237767U, // CLT_U_D
+ 134239004U, // CLT_U_H
+ 134243057U, // CLT_U_W
+ 25534U, // CLZ
+ 25534U, // CLZ_MM
+ 25534U, // CLZ_R6
+ 134235667U, // CMPGDU_EQ_QB
+ 134235572U, // CMPGDU_LE_QB
+ 134235786U, // CMPGDU_LT_QB
+ 134235681U, // CMPGU_EQ_QB
+ 134235586U, // CMPGU_LE_QB
+ 134235800U, // CMPGU_LT_QB
+ 17966U, // CMPU_EQ_QB
+ 17871U, // CMPU_LE_QB
+ 18085U, // CMPU_LT_QB
+ 134236919U, // CMP_EQ_D
+ 21548U, // CMP_EQ_PH
+ 134240864U, // CMP_EQ_S
+ 134236489U, // CMP_F_D
+ 134240675U, // CMP_F_S
+ 134236333U, // CMP_LE_D
+ 21444U, // CMP_LE_PH
+ 134240596U, // CMP_LE_S
+ 134237410U, // CMP_LT_D
+ 21717U, // CMP_LT_PH
+ 134240959U, // CMP_LT_S
+ 134236507U, // CMP_SAF_D
+ 134240685U, // CMP_SAF_S
+ 134236946U, // CMP_SEQ_D
+ 134240883U, // CMP_SEQ_S
+ 134236370U, // CMP_SLE_D
+ 134240625U, // CMP_SLE_S
+ 134237437U, // CMP_SLT_D
+ 134240978U, // CMP_SLT_S
+ 134236994U, // CMP_SUEQ_D
+ 134240914U, // CMP_SUEQ_S
+ 134236418U, // CMP_SULE_D
+ 134240656U, // CMP_SULE_S
+ 134237485U, // CMP_SULT_D
+ 134241009U, // CMP_SULT_S
+ 134236876U, // CMP_SUN_D
+ 134240837U, // CMP_SUN_S
+ 134236974U, // CMP_UEQ_D
+ 134240903U, // CMP_UEQ_S
+ 134236398U, // CMP_ULE_D
+ 134240645U, // CMP_ULE_S
+ 134237465U, // CMP_ULT_D
+ 134240998U, // CMP_ULT_S
+ 134236858U, // CMP_UN_D
+ 134240827U, // CMP_UN_S
+ 9454U, // CONSTPOOL_ENTRY
+ 0U, // COPY_FD_PSEUDO
+ 0U, // COPY_FW_PSEUDO
+ 2952807544U, // COPY_S_B
+ 2952809637U, // COPY_S_D
+ 2952811052U, // COPY_S_H
+ 2952814987U, // COPY_S_W
+ 2952807759U, // COPY_U_B
+ 2952810104U, // COPY_U_D
+ 2952811319U, // COPY_U_H
+ 2952815394U, // COPY_U_W
+ 1867863U, // CTC1
+ 1867863U, // CTC1_MM
+ 16976U, // CTCMSA
+ 22833U, // CVT_D32_S
+ 23896U, // CVT_D32_W
+ 23896U, // CVT_D32_W_MM
+ 22087U, // CVT_D64_L
+ 22833U, // CVT_D64_S
+ 23896U, // CVT_D64_W
+ 22833U, // CVT_D_S_MM
+ 19024U, // CVT_L_D64
+ 19024U, // CVT_L_D64_MM
+ 23052U, // CVT_L_S
+ 23052U, // CVT_L_S_MM
+ 19362U, // CVT_S_D32
+ 19362U, // CVT_S_D32_MM
+ 19362U, // CVT_S_D64
+ 22096U, // CVT_S_L
+ 24651U, // CVT_S_W
+ 24651U, // CVT_S_W_MM
+ 20200U, // CVT_W_D32
+ 20200U, // CVT_W_D64
+ 20200U, // CVT_W_MM
+ 23374U, // CVT_W_S
+ 23374U, // CVT_W_S_MM
+ 19183U, // C_EQ_D32
+ 19183U, // C_EQ_D64
+ 23128U, // C_EQ_S
+ 18754U, // C_F_D32
+ 18754U, // C_F_D64
+ 22940U, // C_F_S
+ 18597U, // C_LE_D32
+ 18597U, // C_LE_D64
+ 22860U, // C_LE_S
+ 19674U, // C_LT_D32
+ 19674U, // C_LT_D64
+ 23223U, // C_LT_S
+ 18588U, // C_NGE_D32
+ 18588U, // C_NGE_D64
+ 22851U, // C_NGE_S
+ 18623U, // C_NGLE_D32
+ 18623U, // C_NGLE_D64
+ 22878U, // C_NGLE_S
+ 19040U, // C_NGL_D32
+ 19040U, // C_NGL_D64
+ 23068U, // C_NGL_S
+ 19665U, // C_NGT_D32
+ 19665U, // C_NGT_D64
+ 23214U, // C_NGT_S
+ 18633U, // C_OLE_D32
+ 18633U, // C_OLE_D64
+ 22888U, // C_OLE_S
+ 19700U, // C_OLT_D32
+ 19700U, // C_OLT_D64
+ 23241U, // C_OLT_S
+ 19209U, // C_SEQ_D32
+ 19209U, // C_SEQ_D64
+ 23146U, // C_SEQ_S
+ 18824U, // C_SF_D32
+ 18824U, // C_SF_D64
+ 22986U, // C_SF_S
+ 19237U, // C_UEQ_D32
+ 19237U, // C_UEQ_D64
+ 23166U, // C_UEQ_S
+ 18661U, // C_ULE_D32
+ 18661U, // C_ULE_D64
+ 22908U, // C_ULE_S
+ 19728U, // C_ULT_D32
+ 19728U, // C_ULT_D64
+ 23261U, // C_ULT_S
+ 19122U, // C_UN_D32
+ 19122U, // C_UN_D64
+ 23091U, // C_UN_S
+ 22516U, // CmpRxRy16
+ 939546120U, // CmpiRxImm16
+ 22024U, // CmpiRxImmX16
+ 549945U, // Constant32
+ 134237991U, // DADD
+ 134239684U, // DADDi
+ 134241306U, // DADDiu
+ 134241267U, // DADDu
+ 8689123U, // DAHI
+ 134240165U, // DALIGN
+ 8689184U, // DATI
+ 134239794U, // DAUI
+ 22476U, // DBITSWAP
+ 22451U, // DCLO
+ 22451U, // DCLO_R6
+ 25533U, // DCLZ
+ 25533U, // DCLZ_R6
+ 134241469U, // DDIV
+ 134241377U, // DDIVU
+ 9480U, // DERET
+ 9480U, // DERET_MM
+ 134243425U, // DEXT
+ 134243400U, // DEXTM
+ 134243438U, // DEXTU
+ 546247U, // DI
+ 134243413U, // DINS
+ 134243393U, // DINSM
+ 134243431U, // DINSU
+ 134241470U, // DIV
+ 134241378U, // DIVU
+ 134235238U, // DIV_S_B
+ 134237331U, // DIV_S_D
+ 134238735U, // DIV_S_H
+ 134242670U, // DIV_S_W
+ 134235453U, // DIV_U_B
+ 134237798U, // DIV_U_D
+ 134239013U, // DIV_U_H
+ 134243088U, // DIV_U_W
+ 546247U, // DI_MM
+ 134234690U, // DLSA
+ 134234690U, // DLSA_R6
+ 134234121U, // DMFC0
+ 16450U, // DMFC1
+ 134234372U, // DMFC2
+ 134238036U, // DMOD
+ 134241281U, // DMODU
+ 134234128U, // DMTC0
+ 1867869U, // DMTC1
+ 134234379U, // DMTC2
+ 134239671U, // DMUH
+ 134241299U, // DMUHU
+ 134240103U, // DMUL
+ 23495U, // DMULT
+ 23641U, // DMULTu
+ 134241343U, // DMULU
+ 134240103U, // DMUL_R6
+ 134237239U, // DOTP_S_D
+ 134238655U, // DOTP_S_H
+ 134242538U, // DOTP_S_W
+ 134237706U, // DOTP_U_D
+ 134238943U, // DOTP_U_H
+ 134242996U, // DOTP_U_W
+ 151014368U, // DPADD_S_D
+ 151015784U, // DPADD_S_H
+ 151019657U, // DPADD_S_W
+ 151014835U, // DPADD_U_D
+ 151016072U, // DPADD_U_H
+ 151020125U, // DPADD_U_W
+ 134239524U, // DPAQX_SA_W_PH
+ 134239607U, // DPAQX_S_W_PH
+ 134241998U, // DPAQ_SA_L_W
+ 134239566U, // DPAQ_S_W_PH
+ 134239859U, // DPAU_H_QBL
+ 134240355U, // DPAU_H_QBR
+ 134239645U, // DPAX_W_PH
+ 134239514U, // DPA_W_PH
+ 22521U, // DPOP
+ 134239539U, // DPSQX_SA_W_PH
+ 134239621U, // DPSQX_S_W_PH
+ 134242011U, // DPSQ_SA_L_W
+ 134239594U, // DPSQ_S_W_PH
+ 151014335U, // DPSUB_S_D
+ 151015763U, // DPSUB_S_H
+ 151019624U, // DPSUB_S_W
+ 151014802U, // DPSUB_U_D
+ 151016051U, // DPSUB_U_H
+ 151020092U, // DPSUB_U_W
+ 134239871U, // DPSU_H_QBL
+ 134240367U, // DPSU_H_QBR
+ 134239656U, // DPSX_W_PH
+ 134239635U, // DPS_W_PH
+ 134240512U, // DROTR
+ 134234351U, // DROTR32
+ 134241513U, // DROTRV
+ 21370U, // DSBH
+ 25610U, // DSDIV
+ 20275U, // DSHD
+ 134240057U, // DSLL
+ 134234321U, // DSLL32
+ 1073764153U, // DSLL64_32
+ 134241475U, // DSLLV
+ 134234684U, // DSRA
+ 134234303U, // DSRA32
+ 134241454U, // DSRAV
+ 134240069U, // DSRL
+ 134234329U, // DSRL32
+ 134241482U, // DSRLV
+ 134235901U, // DSUB
+ 134241246U, // DSUBu
+ 25596U, // DUDIV
+ 25611U, // DivRxRy16
+ 25597U, // DivuRxRy16
+ 9438U, // EHB
+ 9438U, // EHB_MM
+ 546259U, // EI
+ 546259U, // EI_MM
+ 9481U, // ERET
+ 9481U, // ERET_MM
+ 134243426U, // EXT
+ 134240324U, // EXTP
+ 134240221U, // EXTPDP
+ 134241497U, // EXTPDPV
+ 134241506U, // EXTPV
+ 134242731U, // EXTRV_RS_W
+ 134242285U, // EXTRV_R_W
+ 134238744U, // EXTRV_S_H
+ 134243168U, // EXTRV_W
+ 134242720U, // EXTR_RS_W
+ 134242264U, // EXTR_R_W
+ 134238675U, // EXTR_S_H
+ 134242363U, // EXTR_W
+ 134243419U, // EXTS
+ 134243371U, // EXTS32
+ 134243426U, // EXT_MM
+ 0U, // ExtractElementF64
+ 0U, // ExtractElementF64_64
+ 0U, // FABS_D
+ 19631U, // FABS_D32
+ 19631U, // FABS_D64
+ 19631U, // FABS_MM
+ 23198U, // FABS_S
+ 23198U, // FABS_S_MM
+ 0U, // FABS_W
+ 134236265U, // FADD_D
+ 134236266U, // FADD_D32
+ 134236266U, // FADD_D64
+ 134236266U, // FADD_MM
+ 134240572U, // FADD_S
+ 134240572U, // FADD_S_MM
+ 134241633U, // FADD_W
+ 134236499U, // FCAF_D
+ 134241752U, // FCAF_W
+ 134236929U, // FCEQ_D
+ 134242191U, // FCEQ_W
+ 19638U, // FCLASS_D
+ 25015U, // FCLASS_W
+ 134236343U, // FCLE_D
+ 134241675U, // FCLE_W
+ 134237420U, // FCLT_D
+ 134242770U, // FCLT_W
+ 2204821U, // FCMP_D32
+ 2204821U, // FCMP_D32_MM
+ 2204821U, // FCMP_D64
+ 2466965U, // FCMP_S32
+ 2466965U, // FCMP_S32_MM
+ 134236439U, // FCNE_D
+ 134241709U, // FCNE_W
+ 134237039U, // FCOR_D
+ 134242320U, // FCOR_W
+ 134236985U, // FCUEQ_D
+ 134242207U, // FCUEQ_W
+ 134236409U, // FCULE_D
+ 134241691U, // FCULE_W
+ 134237476U, // FCULT_D
+ 134242786U, // FCULT_W
+ 134236455U, // FCUNE_D
+ 134241725U, // FCUNE_W
+ 134236868U, // FCUN_D
+ 134242097U, // FCUN_W
+ 134237862U, // FDIV_D
+ 134237863U, // FDIV_D32
+ 134237863U, // FDIV_D64
+ 134237863U, // FDIV_MM
+ 134241045U, // FDIV_S
+ 134241045U, // FDIV_S_MM
+ 134243152U, // FDIV_W
+ 134238402U, // FEXDO_H
+ 134242113U, // FEXDO_W
+ 134236152U, // FEXP2_D
+ 0U, // FEXP2_D_1_PSEUDO
+ 134241536U, // FEXP2_W
+ 0U, // FEXP2_W_1_PSEUDO
+ 19064U, // FEXUPL_D
+ 24311U, // FEXUPL_W
+ 19327U, // FEXUPR_D
+ 24608U, // FEXUPR_W
+ 19569U, // FFINT_S_D
+ 24908U, // FFINT_S_W
+ 20048U, // FFINT_U_D
+ 25338U, // FFINT_U_W
+ 19074U, // FFQL_D
+ 24321U, // FFQL_W
+ 19337U, // FFQR_D
+ 24618U, // FFQR_W
+ 17277U, // FILL_B
+ 19049U, // FILL_D
+ 0U, // FILL_FD_PSEUDO
+ 0U, // FILL_FW_PSEUDO
+ 20635U, // FILL_H
+ 24296U, // FILL_W
+ 18415U, // FLOG2_D
+ 23799U, // FLOG2_W
+ 19013U, // FLOOR_L_D64
+ 23041U, // FLOOR_L_S
+ 20189U, // FLOOR_W_D32
+ 20189U, // FLOOR_W_D64
+ 20189U, // FLOOR_W_MM
+ 23363U, // FLOOR_W_S
+ 23363U, // FLOOR_W_S_MM
+ 151013489U, // FMADD_D
+ 151018857U, // FMADD_W
+ 134236190U, // FMAX_A_D
+ 134241574U, // FMAX_A_W
+ 134237937U, // FMAX_D
+ 134243177U, // FMAX_W
+ 134236170U, // FMIN_A_D
+ 134241554U, // FMIN_A_W
+ 134236842U, // FMIN_D
+ 134242089U, // FMIN_W
+ 20150U, // FMOV_D32
+ 20150U, // FMOV_D32_MM
+ 20150U, // FMOV_D64
+ 23324U, // FMOV_S
+ 23324U, // FMOV_S_MM
+ 151013447U, // FMSUB_D
+ 151018815U, // FMSUB_W
+ 134236826U, // FMUL_D
+ 134236827U, // FMUL_D32
+ 134236827U, // FMUL_D64
+ 134236827U, // FMUL_MM
+ 134240805U, // FMUL_S
+ 134240805U, // FMUL_S_MM
+ 134242073U, // FMUL_W
+ 18841U, // FNEG_D32
+ 18841U, // FNEG_D64
+ 18841U, // FNEG_MM
+ 23002U, // FNEG_S
+ 23002U, // FNEG_S_MM
+ 19175U, // FRCP_D
+ 24394U, // FRCP_W
+ 19786U, // FRINT_D
+ 25084U, // FRINT_W
+ 19814U, // FRSQRT_D
+ 25112U, // FRSQRT_W
+ 134236518U, // FSAF_D
+ 134241760U, // FSAF_W
+ 134236957U, // FSEQ_D
+ 134242199U, // FSEQ_W
+ 134236381U, // FSLE_D
+ 134241683U, // FSLE_W
+ 134237448U, // FSLT_D
+ 134242778U, // FSLT_W
+ 134236447U, // FSNE_D
+ 134241717U, // FSNE_W
+ 134237047U, // FSOR_D
+ 134242328U, // FSOR_W
+ 19805U, // FSQRT_D
+ 19806U, // FSQRT_D32
+ 19806U, // FSQRT_D64
+ 19806U, // FSQRT_MM
+ 23301U, // FSQRT_S
+ 23301U, // FSQRT_S_MM
+ 25103U, // FSQRT_W
+ 134236223U, // FSUB_D
+ 134236224U, // FSUB_D32
+ 134236224U, // FSUB_D64
+ 134236224U, // FSUB_MM
+ 134240554U, // FSUB_S
+ 134240554U, // FSUB_S_MM
+ 134241591U, // FSUB_W
+ 134237006U, // FSUEQ_D
+ 134242216U, // FSUEQ_W
+ 134236430U, // FSULE_D
+ 134241700U, // FSULE_W
+ 134237497U, // FSULT_D
+ 134242795U, // FSULT_W
+ 134236464U, // FSUNE_D
+ 134241734U, // FSUNE_W
+ 134236887U, // FSUN_D
+ 134242105U, // FSUN_W
+ 19580U, // FTINT_S_D
+ 24919U, // FTINT_S_W
+ 20059U, // FTINT_U_D
+ 25349U, // FTINT_U_W
+ 134238479U, // FTQ_H
+ 134242225U, // FTQ_W
+ 19402U, // FTRUNC_S_D
+ 24691U, // FTRUNC_S_W
+ 19869U, // FTRUNC_U_D
+ 25159U, // FTRUNC_U_W
+ 1224758783U, // GotPrologue16
+ 134237142U, // HADD_S_D
+ 134238558U, // HADD_S_H
+ 134242431U, // HADD_S_W
+ 134237609U, // HADD_U_D
+ 134238846U, // HADD_U_H
+ 134242899U, // HADD_U_W
+ 134237109U, // HSUB_S_D
+ 134238537U, // HSUB_S_H
+ 134242398U, // HSUB_S_W
+ 134237576U, // HSUB_U_D
+ 134238825U, // HSUB_U_H
+ 134242866U, // HSUB_U_W
+ 134235508U, // ILVEV_B
+ 134237853U, // ILVEV_D
+ 134239068U, // ILVEV_H
+ 134243143U, // ILVEV_W
+ 134235036U, // ILVL_B
+ 134236834U, // ILVL_D
+ 134238394U, // ILVL_H
+ 134242081U, // ILVL_W
+ 134234788U, // ILVOD_B
+ 134236307U, // ILVOD_D
+ 134238196U, // ILVOD_H
+ 134241666U, // ILVOD_W
+ 134235084U, // ILVR_B
+ 134237082U, // ILVR_D
+ 134238519U, // ILVR_H
+ 134242371U, // ILVR_W
+ 134243408U, // INS
+ 44582043U, // INSERT_B
+ 0U, // INSERT_B_VIDX_PSEUDO
+ 44584275U, // INSERT_D
+ 0U, // INSERT_D_VIDX_PSEUDO
+ 0U, // INSERT_FD_PSEUDO
+ 0U, // INSERT_FD_VIDX_PSEUDO
+ 0U, // INSERT_FW_PSEUDO
+ 0U, // INSERT_FW_VIDX_PSEUDO
+ 44585551U, // INSERT_H
+ 0U, // INSERT_H_VIDX_PSEUDO
+ 44589573U, // INSERT_W
+ 0U, // INSERT_W_VIDX_PSEUDO
+ 16801009U, // INSV
+ 52970157U, // INSVE_B
+ 52971833U, // INSVE_D
+ 52973565U, // INSVE_H
+ 52977103U, // INSVE_W
+ 134243408U, // INS_MM
+ 546365U, // J
+ 546398U, // JAL
+ 22768U, // JALR
+ 547056U, // JALR16_MM
+ 22768U, // JALR64
+ 0U, // JALR64Pseudo
+ 0U, // JALRPseudo
+ 541104U, // JALRS16_MM
+ 23442U, // JALRS_MM
+ 17822U, // JALR_HB
+ 22768U, // JALR_MM
+ 547706U, // JALS_MM
+ 549771U, // JALX
+ 549771U, // JALX_MM
+ 546398U, // JAL_MM
+ 18212U, // JIALC
+ 18201U, // JIC
+ 547052U, // JR
+ 541091U, // JR16_MM
+ 547052U, // JR64
+ 546873U, // JRADDIUSP
+ 542610U, // JRC16_MM
+ 542103U, // JR_HB
+ 542103U, // JR_HB_R6
+ 547052U, // JR_MM
+ 546365U, // J_MM
+ 2905694U, // Jal16
+ 3167838U, // JalB16
+ 546398U, // JalOneReg
+ 22110U, // JalTwoReg
+ 9430U, // JrRa16
+ 9421U, // JrcRa16
+ 549872U, // JrcRx16
+ 540673U, // JumpLinkReg16
+ 58738087U, // LB
+ 58738087U, // LB64
+ 58737088U, // LBU16_MM
+ 1358979985U, // LBUX
+ 58738087U, // LB_MM
+ 58743769U, // LBu
+ 58743769U, // LBu64
+ 58743769U, // LBu_MM
+ 58740538U, // LD
+ 58736688U, // LDC1
+ 58736688U, // LDC164
+ 58736688U, // LDC1_MM
+ 58736888U, // LDC2
+ 58736888U, // LDC2_R6
+ 58736947U, // LDC3
+ 17103U, // LDI_B
+ 18857U, // LDI_D
+ 20511U, // LDI_H
+ 24146U, // LDI_W
+ 58742458U, // LDL
+ 18273U, // LDPC
+ 58742954U, // LDR
+ 1358970992U, // LDXC1
+ 1358970992U, // LDXC164
+ 58737301U, // LD_B
+ 58738820U, // LD_D
+ 58740709U, // LD_H
+ 58744179U, // LD_W
+ 25189403U, // LEA_ADDiu
+ 25189402U, // LEA_ADDiu64
+ 25189403U, // LEA_ADDiu_MM
+ 58741643U, // LH
+ 58741643U, // LH64
+ 58737111U, // LHU16_MM
+ 1358979974U, // LHX
+ 58741643U, // LH_MM
+ 58743822U, // LHu
+ 58743822U, // LHu64
+ 58743822U, // LHu_MM
+ 16751U, // LI16_MM
+ 58742563U, // LL
+ 58740537U, // LLD
+ 58740537U, // LLD_R6
+ 58742563U, // LL_MM
+ 58742563U, // LL_R6
+ 58736647U, // LOAD_ACC128
+ 58736647U, // LOAD_ACC64
+ 58736647U, // LOAD_ACC64DSP
+ 58742794U, // LOAD_CCOND_DSP
+ 0U, // LONG_BRANCH_ADDiu
+ 0U, // LONG_BRANCH_DADDiu
+ 0U, // LONG_BRANCH_LUi
+ 134234691U, // LSA
+ 134234691U, // LSA_R6
+ 1358971006U, // LUXC1
+ 1358971006U, // LUXC164
+ 1358971006U, // LUXC1_MM
+ 33576504U, // LUi
+ 33576504U, // LUi64
+ 33576504U, // LUi_MM
+ 58745726U, // LW
+ 58737118U, // LW16_MM
+ 58745726U, // LW64
+ 58736740U, // LWC1
+ 58736740U, // LWC1_MM
+ 58736914U, // LWC2
+ 58736914U, // LWC2_R6
+ 58736959U, // LWC3
+ 58745726U, // LWGP_MM
+ 58742637U, // LWL
+ 58742637U, // LWL64
+ 58742637U, // LWL_MM
+ 3522956U, // LWM16_MM
+ 3522785U, // LWM32_MM
+ 3528595U, // LWM_MM
+ 18310U, // LWPC
+ 137290U, // LWP_MM
+ 58743054U, // LWR
+ 58743054U, // LWR64
+ 58743054U, // LWR_MM
+ 58745726U, // LWSP_MM
+ 18303U, // LWUPC
+ 58743912U, // LWU_MM
+ 1358979991U, // LWX
+ 1358971020U, // LWXC1
+ 1358971020U, // LWXC1_MM
+ 1358977945U, // LWXS_MM
+ 58745726U, // LW_MM
+ 58743912U, // LWu
+ 58738087U, // LbRxRyOffMemX16
+ 58743769U, // LbuRxRyOffMemX16
+ 58741643U, // LhRxRyOffMemX16
+ 58743822U, // LhuRxRyOffMemX16
+ 939546111U, // LiRxImm16
+ 22005U, // LiRxImmAlignX16
+ 22015U, // LiRxImmX16
+ 33571334U, // LoadAddr32Imm
+ 58737158U, // LoadAddr32Reg
+ 33576447U, // LoadImm32Reg
+ 22019U, // LoadImm64Reg
+ 3695486U, // LwConstant32
+ 268460926U, // LwRxPcTcp16
+ 25470U, // LwRxPcTcpX16
+ 58745726U, // LwRxRyOffMemX16
+ 1493197694U, // LwRxSpImmX16
+ 20269U, // MADD
+ 151013751U, // MADDF_D
+ 151017921U, // MADDF_S
+ 151015667U, // MADDR_Q_H
+ 151019386U, // MADDR_Q_W
+ 23546U, // MADDU
+ 134241274U, // MADDU_DSP
+ 23546U, // MADDU_MM
+ 151012706U, // MADDV_B
+ 151015051U, // MADDV_D
+ 151016266U, // MADDV_H
+ 151020341U, // MADDV_W
+ 134236274U, // MADD_D32
+ 134236274U, // MADD_D32_MM
+ 134236274U, // MADD_D64
+ 134237997U, // MADD_DSP
+ 20269U, // MADD_MM
+ 151015637U, // MADD_Q_H
+ 151019356U, // MADD_Q_W
+ 134240571U, // MADD_S
+ 134240571U, // MADD_S_MM
+ 134239974U, // MAQ_SA_W_PHL
+ 134240436U, // MAQ_SA_W_PHR
+ 134240002U, // MAQ_S_W_PHL
+ 134240464U, // MAQ_S_W_PHR
+ 134236215U, // MAXA_D
+ 134240544U, // MAXA_S
+ 134235159U, // MAXI_S_B
+ 134237220U, // MAXI_S_D
+ 134238636U, // MAXI_S_H
+ 134242509U, // MAXI_S_W
+ 2281719022U, // MAXI_U_B
+ 2281721335U, // MAXI_U_D
+ 2281722572U, // MAXI_U_H
+ 2281726625U, // MAXI_U_W
+ 134234740U, // MAX_A_B
+ 134236191U, // MAX_A_D
+ 134238148U, // MAX_A_H
+ 134241575U, // MAX_A_W
+ 134237938U, // MAX_D
+ 134241111U, // MAX_S
+ 134235247U, // MAX_S_B
+ 134237340U, // MAX_S_D
+ 134238755U, // MAX_S_H
+ 134242690U, // MAX_S_W
+ 134235462U, // MAX_U_B
+ 134237807U, // MAX_U_D
+ 134239022U, // MAX_U_H
+ 134243097U, // MAX_U_W
+ 134234122U, // MFC0
+ 16451U, // MFC1
+ 16451U, // MFC1_MM
+ 134234373U, // MFC2
+ 16457U, // MFHC1_D32
+ 16457U, // MFHC1_D64
+ 16457U, // MFHC1_MM
+ 546281U, // MFHI
+ 546281U, // MFHI16_MM
+ 546281U, // MFHI64
+ 21993U, // MFHI_DSP
+ 546281U, // MFHI_MM
+ 546745U, // MFLO
+ 546745U, // MFLO16_MM
+ 546745U, // MFLO64
+ 22457U, // MFLO_DSP
+ 546745U, // MFLO_MM
+ 134236200U, // MINA_D
+ 134240536U, // MINA_S
+ 134235139U, // MINI_S_B
+ 134237200U, // MINI_S_D
+ 134238616U, // MINI_S_H
+ 134242489U, // MINI_S_W
+ 2281719002U, // MINI_U_B
+ 2281721315U, // MINI_U_D
+ 2281722552U, // MINI_U_H
+ 2281726605U, // MINI_U_W
+ 134234721U, // MIN_A_B
+ 134236171U, // MIN_A_D
+ 134238129U, // MIN_A_H
+ 134241555U, // MIN_A_W
+ 134236843U, // MIN_D
+ 134240812U, // MIN_S
+ 134235169U, // MIN_S_B
+ 134237230U, // MIN_S_D
+ 134238646U, // MIN_S_H
+ 134242529U, // MIN_S_W
+ 134235384U, // MIN_U_B
+ 134237697U, // MIN_U_D
+ 134238934U, // MIN_U_H
+ 134242987U, // MIN_U_W
+ 0U, // MIPSeh_return32
+ 0U, // MIPSeh_return64
+ 134238037U, // MOD
+ 134235899U, // MODSUB
+ 134241282U, // MODU
+ 134235102U, // MOD_S_B
+ 134237163U, // MOD_S_D
+ 134238579U, // MOD_S_H
+ 134242452U, // MOD_S_W
+ 134235317U, // MOD_U_B
+ 134237630U, // MOD_U_D
+ 134238867U, // MOD_U_H
+ 134242920U, // MOD_U_W
+ 20345U, // MOVE16_MM
+ 67491813U, // MOVEP_MM
+ 23668U, // MOVE_V
+ 134236560U, // MOVF_D32
+ 134236560U, // MOVF_D32_MM
+ 134236560U, // MOVF_D64
+ 134238109U, // MOVF_I
+ 134238109U, // MOVF_I64
+ 134238109U, // MOVF_I_MM
+ 134240722U, // MOVF_S
+ 134240722U, // MOVF_S_MM
+ 134236895U, // MOVN_I64_D64
+ 134240173U, // MOVN_I64_I
+ 134240173U, // MOVN_I64_I64
+ 134240848U, // MOVN_I64_S
+ 134236895U, // MOVN_I_D32
+ 134236895U, // MOVN_I_D32_MM
+ 134236895U, // MOVN_I_D64
+ 134240173U, // MOVN_I_I
+ 134240173U, // MOVN_I_I64
+ 134240173U, // MOVN_I_MM
+ 134240848U, // MOVN_I_S
+ 134240848U, // MOVN_I_S_MM
+ 134237558U, // MOVT_D32
+ 134237558U, // MOVT_D32_MM
+ 134237558U, // MOVT_D64
+ 134241235U, // MOVT_I
+ 134241235U, // MOVT_I64
+ 134241235U, // MOVT_I_MM
+ 134241037U, // MOVT_S
+ 134241037U, // MOVT_S_MM
+ 134237978U, // MOVZ_I64_D64
+ 134243300U, // MOVZ_I64_I
+ 134243300U, // MOVZ_I64_I64
+ 134241138U, // MOVZ_I64_S
+ 134237978U, // MOVZ_I_D32
+ 134237978U, // MOVZ_I_D32_MM
+ 134237978U, // MOVZ_I_D64
+ 134243300U, // MOVZ_I_I
+ 134243300U, // MOVZ_I_I64
+ 134243300U, // MOVZ_I_MM
+ 134241138U, // MOVZ_I_S
+ 134241138U, // MOVZ_I_S_MM
+ 18179U, // MSUB
+ 151013742U, // MSUBF_D
+ 151017912U, // MSUBF_S
+ 151015656U, // MSUBR_Q_H
+ 151019375U, // MSUBR_Q_W
+ 23525U, // MSUBU
+ 134241253U, // MSUBU_DSP
+ 23525U, // MSUBU_MM
+ 151012697U, // MSUBV_B
+ 151015042U, // MSUBV_D
+ 151016257U, // MSUBV_H
+ 151020332U, // MSUBV_W
+ 134236232U, // MSUB_D32
+ 134236232U, // MSUB_D32_MM
+ 134236232U, // MSUB_D64
+ 134235907U, // MSUB_DSP
+ 18179U, // MSUB_MM
+ 151015627U, // MSUB_Q_H
+ 151019346U, // MSUB_Q_W
+ 134240553U, // MSUB_S
+ 134240553U, // MSUB_S_MM
+ 134234129U, // MTC0
+ 1867870U, // MTC1
+ 1867870U, // MTC1_MM
+ 134234380U, // MTC2
+ 1884240U, // MTHC1_D32
+ 1884240U, // MTHC1_D64
+ 1884240U, // MTHC1_MM
+ 546287U, // MTHI
+ 546287U, // MTHI64
+ 1873391U, // MTHI_DSP
+ 546287U, // MTHI_MM
+ 1873900U, // MTHLIP
+ 546758U, // MTLO
+ 546758U, // MTLO64
+ 1873862U, // MTLO_DSP
+ 546758U, // MTLO_MM
+ 540701U, // MTM0
+ 540826U, // MTM1
+ 540958U, // MTM2
+ 540707U, // MTP0
+ 540832U, // MTP1
+ 540964U, // MTP2
+ 134239672U, // MUH
+ 134241300U, // MUHU
+ 134240104U, // MUL
+ 134240015U, // MULEQ_S_W_PHL
+ 134240477U, // MULEQ_S_W_PHR
+ 134239883U, // MULEU_S_PH_QBL
+ 134240379U, // MULEU_S_PH_QBR
+ 134239433U, // MULQ_RS_PH
+ 134242709U, // MULQ_RS_W
+ 134239377U, // MULQ_S_PH
+ 134242568U, // MULQ_S_W
+ 134238462U, // MULR_Q_H
+ 134242181U, // MULR_Q_W
+ 134239579U, // MULSAQ_S_W_PH
+ 134239554U, // MULSA_W_PH
+ 23496U, // MULT
+ 134241370U, // MULTU_DSP
+ 134241224U, // MULT_DSP
+ 23496U, // MULT_MM
+ 23642U, // MULTu
+ 23642U, // MULTu_MM
+ 134241337U, // MULU
+ 134235517U, // MULV_B
+ 134237870U, // MULV_D
+ 134239077U, // MULV_H
+ 134243160U, // MULV_W
+ 134240104U, // MUL_MM
+ 134239250U, // MUL_PH
+ 134238431U, // MUL_Q_H
+ 134242150U, // MUL_Q_W
+ 134240104U, // MUL_R6
+ 134239345U, // MUL_S_PH
+ 546281U, // Mfhi16
+ 546745U, // Mflo16
+ 20345U, // Move32R16
+ 20345U, // MoveR3216
+ 23496U, // MultRxRy16
+ 75799496U, // MultRxRyRz16
+ 23642U, // MultuRxRy16
+ 75799642U, // MultuRxRyRz16
+ 17028U, // NLOC_B
+ 18521U, // NLOC_D
+ 20436U, // NLOC_H
+ 23880U, // NLOC_W
+ 17036U, // NLZC_B
+ 18529U, // NLZC_D
+ 20444U, // NLZC_H
+ 23888U, // NLZC_W
+ 134236282U, // NMADD_D32
+ 134236282U, // NMADD_D32_MM
+ 134236282U, // NMADD_D64
+ 134240570U, // NMADD_S
+ 134240570U, // NMADD_S_MM
+ 134236240U, // NMSUB_D32
+ 134236240U, // NMSUB_D32_MM
+ 134236240U, // NMSUB_D64
+ 134240552U, // NMSUB_S
+ 134240552U, // NMSUB_S_MM
+ 0U, // NOP
+ 134240502U, // NOR
+ 134240502U, // NOR64
+ 2281718573U, // NORI_B
+ 134240502U, // NOR_MM
+ 134241412U, // NOR_V
+ 0U, // NOR_V_D_PSEUDO
+ 0U, // NOR_V_H_PSEUDO
+ 0U, // NOR_V_W_PSEUDO
+ 16825U, // NOT16_MM
+ 20387U, // NegRxRy16
+ 23502U, // NotRxRy16
+ 134240503U, // OR
+ 836010U, // OR16_MM
+ 134240503U, // OR64
+ 2281718574U, // ORI_B
+ 134240503U, // OR_MM
+ 134241413U, // OR_V
+ 0U, // OR_V_D_PSEUDO
+ 0U, // OR_V_H_PSEUDO
+ 0U, // OR_V_W_PSEUDO
+ 134239771U, // ORi
+ 134239771U, // ORi64
+ 134239771U, // ORi_MM
+ 16799991U, // OrRxRxRy16
+ 134239239U, // PACKRL_PH
+ 9442U, // PAUSE
+ 9442U, // PAUSE_MM
+ 134235499U, // PCKEV_B
+ 134237844U, // PCKEV_D
+ 134239059U, // PCKEV_H
+ 134243134U, // PCKEV_W
+ 134234779U, // PCKOD_B
+ 134236298U, // PCKOD_D
+ 134238187U, // PCKOD_H
+ 134241657U, // PCKOD_W
+ 17555U, // PCNT_B
+ 19778U, // PCNT_D
+ 21063U, // PCNT_H
+ 25076U, // PCNT_W
+ 134239203U, // PICK_PH
+ 134235631U, // PICK_QB
+ 22522U, // POP
+ 22186U, // PRECEQU_PH_QBL
+ 16906U, // PRECEQU_PH_QBLA
+ 22682U, // PRECEQU_PH_QBR
+ 16939U, // PRECEQU_PH_QBRA
+ 22260U, // PRECEQ_W_PHL
+ 22722U, // PRECEQ_W_PHR
+ 22171U, // PRECEU_PH_QBL
+ 16890U, // PRECEU_PH_QBLA
+ 22667U, // PRECEU_PH_QBR
+ 16923U, // PRECEU_PH_QBRA
+ 134239155U, // PRECRQU_S_QB_PH
+ 134241800U, // PRECRQ_PH_W
+ 134239128U, // PRECRQ_QB_PH
+ 134241831U, // PRECRQ_RS_PH_W
+ 134239142U, // PRECR_QB_PH
+ 134241784U, // PRECR_SRA_PH_W
+ 134241813U, // PRECR_SRA_R_PH_W
+ 85911U, // PREF
+ 85911U, // PREF_MM
+ 85911U, // PREF_R6
+ 134238019U, // PREPEND
+ 0U, // PseudoCMPU_EQ_QB
+ 0U, // PseudoCMPU_LE_QB
+ 0U, // PseudoCMPU_LT_QB
+ 0U, // PseudoCMP_EQ_PH
+ 0U, // PseudoCMP_LE_PH
+ 0U, // PseudoCMP_LT_PH
+ 16391U, // PseudoCVT_D32_W
+ 16391U, // PseudoCVT_D64_L
+ 16391U, // PseudoCVT_D64_W
+ 16391U, // PseudoCVT_S_L
+ 16391U, // PseudoCVT_S_W
+ 0U, // PseudoDMULT
+ 0U, // PseudoDMULTu
+ 0U, // PseudoDSDIV
+ 0U, // PseudoDUDIV
+ 0U, // PseudoIndirectBranch
+ 0U, // PseudoIndirectBranch64
+ 0U, // PseudoMADD
+ 0U, // PseudoMADDU
+ 0U, // PseudoMFHI
+ 0U, // PseudoMFHI64
+ 0U, // PseudoMFLO
+ 0U, // PseudoMFLO64
+ 0U, // PseudoMSUB
+ 0U, // PseudoMSUBU
+ 0U, // PseudoMTLOHI
+ 0U, // PseudoMTLOHI64
+ 0U, // PseudoMTLOHI_DSP
+ 0U, // PseudoMULT
+ 0U, // PseudoMULTu
+ 0U, // PseudoPICK_PH
+ 0U, // PseudoPICK_QB
+ 0U, // PseudoReturn
+ 0U, // PseudoReturn64
+ 0U, // PseudoSDIV
+ 0U, // PseudoSELECTFP_F_D32
+ 0U, // PseudoSELECTFP_F_D64
+ 0U, // PseudoSELECTFP_F_I
+ 0U, // PseudoSELECTFP_F_I64
+ 0U, // PseudoSELECTFP_F_S
+ 0U, // PseudoSELECTFP_T_D32
+ 0U, // PseudoSELECTFP_T_D64
+ 0U, // PseudoSELECTFP_T_I
+ 0U, // PseudoSELECTFP_T_I64
+ 0U, // PseudoSELECTFP_T_S
+ 0U, // PseudoSELECT_D32
+ 0U, // PseudoSELECT_D64
+ 0U, // PseudoSELECT_I
+ 0U, // PseudoSELECT_I64
+ 0U, // PseudoSELECT_S
+ 0U, // PseudoUDIV
+ 18155U, // RADDU_W_QB
+ 33577003U, // RDDSP
+ 22791U, // RDHWR
+ 22791U, // RDHWR64
+ 22791U, // RDHWR_MM
+ 21766U, // REPLV_PH
+ 18135U, // REPLV_QB
+ 33575925U, // REPL_PH
+ 33572353U, // REPL_QB
+ 19787U, // RINT_D
+ 23293U, // RINT_S
+ 134240513U, // ROTR
+ 134241514U, // ROTRV
+ 134241514U, // ROTRV_MM
+ 134240513U, // ROTR_MM
+ 18992U, // ROUND_L_D64
+ 23020U, // ROUND_L_S
+ 20168U, // ROUND_W_D32
+ 20168U, // ROUND_W_D64
+ 20168U, // ROUND_W_MM
+ 23342U, // ROUND_W_S
+ 23342U, // ROUND_W_S_MM
+ 0U, // Restore16
+ 0U, // RestoreX16
+ 0U, // RetRA
+ 0U, // RetRA16
+ 134235208U, // SAT_S_B
+ 134237279U, // SAT_S_D
+ 2281722353U, // SAT_S_H
+ 134242618U, // SAT_S_W
+ 134235435U, // SAT_U_B
+ 134237758U, // SAT_U_D
+ 2281722643U, // SAT_U_H
+ 134243048U, // SAT_U_W
+ 58738423U, // SB
+ 58736980U, // SB16_MM
+ 58738423U, // SB64
+ 58738423U, // SB_MM
+ 3966874U, // SC
+ 3968802U, // SCD
+ 3968802U, // SCD_R6
+ 3966874U, // SC_MM
+ 3966874U, // SC_R6
+ 58740570U, // SD
+ 546774U, // SDBBP
+ 65946U, // SDBBP16_MM
+ 546774U, // SDBBP_MM
+ 546774U, // SDBBP_R6
+ 58736694U, // SDC1
+ 58736694U, // SDC164
+ 58736694U, // SDC1_MM
+ 58736894U, // SDC2
+ 58736894U, // SDC2_R6
+ 58736953U, // SDC3
+ 25611U, // SDIV
+ 25611U, // SDIV_MM
+ 58742463U, // SDL
+ 58742959U, // SDR
+ 1358970999U, // SDXC1
+ 1358970999U, // SDXC164
+ 17810U, // SEB
+ 17810U, // SEB64
+ 17810U, // SEB_MM
+ 21382U, // SEH
+ 21382U, // SEH64
+ 21382U, // SEH_MM
+ 134243273U, // SELEQZ
+ 134243273U, // SELEQZ64
+ 134237968U, // SELEQZ_D
+ 134241128U, // SELEQZ_S
+ 134243246U, // SELNEZ
+ 134243246U, // SELNEZ64
+ 134237951U, // SELNEZ_D
+ 134241118U, // SELNEZ_S
+ 151013977U, // SEL_D
+ 151018005U, // SEL_S
+ 134240345U, // SEQ
+ 134239758U, // SEQi
+ 58742195U, // SH
+ 58736993U, // SH16_MM
+ 58742195U, // SH64
+ 2281718455U, // SHF_B
+ 2281721863U, // SHF_H
+ 2281725417U, // SHF_W
+ 22463U, // SHILO
+ 23761U, // SHILOV
+ 134239484U, // SHLLV_PH
+ 134235853U, // SHLLV_QB
+ 134239421U, // SHLLV_S_PH
+ 134242679U, // SHLLV_S_W
+ 134239212U, // SHLL_PH
+ 134235640U, // SHLL_QB
+ 134239334U, // SHLL_S_PH
+ 134242519U, // SHLL_S_W
+ 134239474U, // SHRAV_PH
+ 134235843U, // SHRAV_QB
+ 134239322U, // SHRAV_R_PH
+ 134235741U, // SHRAV_R_QB
+ 134242274U, // SHRAV_R_W
+ 134239119U, // SHRA_PH
+ 134235563U, // SHRA_QB
+ 134239287U, // SHRA_R_PH
+ 134235706U, // SHRA_R_QB
+ 134242232U, // SHRA_R_W
+ 134239504U, // SHRLV_PH
+ 134235873U, // SHRLV_QB
+ 134239230U, // SHRL_PH
+ 134235658U, // SHRL_QB
+ 58742195U, // SH_MM
+ 2969584334U, // SLDI_B
+ 2969586088U, // SLDI_D
+ 2969587742U, // SLDI_H
+ 2969591377U, // SLDI_W
+ 822100628U, // SLD_B
+ 822102147U, // SLD_D
+ 822104036U, // SLD_H
+ 822107506U, // SLD_W
+ 134240058U, // SLL
+ 134234494U, // SLL16_MM
+ 1610635066U, // SLL64_32
+ 1610635066U, // SLL64_64
+ 2281718512U, // SLLI_B
+ 2281720249U, // SLLI_D
+ 2281721903U, // SLLI_H
+ 2281725538U, // SLLI_W
+ 134241476U, // SLLV
+ 134241476U, // SLLV_MM
+ 134235013U, // SLL_B
+ 134236785U, // SLL_D
+ 134238371U, // SLL_H
+ 134240058U, // SLL_MM
+ 134242032U, // SLL_W
+ 134241213U, // SLT
+ 134241213U, // SLT64
+ 134241213U, // SLT_MM
+ 134239782U, // SLTi
+ 134239782U, // SLTi64
+ 134239782U, // SLTi_MM
+ 134241321U, // SLTiu
+ 134241321U, // SLTiu64
+ 134241321U, // SLTiu_MM
+ 134241357U, // SLTu
+ 134241357U, // SLTu64
+ 134241357U, // SLTu_MM
+ 134238063U, // SNE
+ 134239703U, // SNEi
+ 0U, // SNZ_B_PSEUDO
+ 0U, // SNZ_D_PSEUDO
+ 0U, // SNZ_H_PSEUDO
+ 0U, // SNZ_V_PSEUDO
+ 0U, // SNZ_W_PSEUDO
+ 2952807239U, // SPLATI_B
+ 2952808960U, // SPLATI_D
+ 2952810614U, // SPLATI_H
+ 2952814249U, // SPLATI_W
+ 805323906U, // SPLAT_B
+ 805326016U, // SPLAT_D
+ 805327414U, // SPLAT_H
+ 805331393U, // SPLAT_W
+ 134234685U, // SRA
+ 2281718470U, // SRAI_B
+ 2281720224U, // SRAI_D
+ 2281721878U, // SRAI_H
+ 2281725513U, // SRAI_W
+ 134234898U, // SRARI_B
+ 134236635U, // SRARI_D
+ 2281721937U, // SRARI_H
+ 134241924U, // SRARI_W
+ 134235051U, // SRAR_B
+ 134237015U, // SRAR_D
+ 134238486U, // SRAR_H
+ 134242296U, // SRAR_W
+ 134241455U, // SRAV
+ 134241455U, // SRAV_MM
+ 134234749U, // SRA_B
+ 134236208U, // SRA_D
+ 134238157U, // SRA_H
+ 134234685U, // SRA_MM
+ 134241584U, // SRA_W
+ 134240070U, // SRL
+ 134234501U, // SRL16_MM
+ 2281718520U, // SRLI_B
+ 2281720257U, // SRLI_D
+ 2281721911U, // SRLI_H
+ 2281725546U, // SRLI_W
+ 134234916U, // SRLRI_B
+ 134236653U, // SRLRI_D
+ 2281721955U, // SRLRI_H
+ 134241942U, // SRLRI_W
+ 134235067U, // SRLR_B
+ 134237031U, // SRLR_D
+ 134238502U, // SRLR_H
+ 134242312U, // SRLR_W
+ 134241483U, // SRLV
+ 134241483U, // SRLV_MM
+ 134235020U, // SRL_B
+ 134236810U, // SRL_D
+ 134238378U, // SRL_H
+ 134240070U, // SRL_MM
+ 134242057U, // SRL_W
+ 9463U, // SSNOP
+ 9463U, // SSNOP_MM
+ 58736647U, // STORE_ACC128
+ 58736647U, // STORE_ACC64
+ 58736647U, // STORE_ACC64DSP
+ 58742810U, // STORE_CCOND_DSP
+ 58737829U, // ST_B
+ 58740080U, // ST_D
+ 58741337U, // ST_H
+ 58745378U, // ST_W
+ 134235902U, // SUB
+ 134239183U, // SUBQH_PH
+ 134239298U, // SUBQH_R_PH
+ 134242242U, // SUBQH_R_W
+ 134241847U, // SUBQH_W
+ 134239258U, // SUBQ_PH
+ 134239355U, // SUBQ_S_PH
+ 134242548U, // SUBQ_S_W
+ 134235423U, // SUBSUS_U_B
+ 134237746U, // SUBSUS_U_D
+ 134238983U, // SUBSUS_U_H
+ 134243036U, // SUBSUS_U_W
+ 134235226U, // SUBSUU_S_B
+ 134237319U, // SUBSUU_S_D
+ 134238723U, // SUBSUU_S_H
+ 134242658U, // SUBSUU_S_W
+ 134235188U, // SUBS_S_B
+ 134237259U, // SUBS_S_D
+ 134238685U, // SUBS_S_H
+ 134242598U, // SUBS_S_W
+ 134235403U, // SUBS_U_B
+ 134237726U, // SUBS_U_D
+ 134238963U, // SUBS_U_H
+ 134243016U, // SUBS_U_W
+ 134234567U, // SUBU16_MM
+ 134235611U, // SUBUH_QB
+ 134235717U, // SUBUH_R_QB
+ 134239456U, // SUBU_PH
+ 134235825U, // SUBU_QB
+ 134239399U, // SUBU_S_PH
+ 134235764U, // SUBU_S_QB
+ 2281718618U, // SUBVI_B
+ 2281720339U, // SUBVI_D
+ 2281721993U, // SUBVI_H
+ 2281725628U, // SUBVI_W
+ 134235482U, // SUBV_B
+ 134237827U, // SUBV_D
+ 134239042U, // SUBV_H
+ 134243117U, // SUBV_W
+ 134235902U, // SUB_MM
+ 134241247U, // SUBu
+ 134241247U, // SUBu_MM
+ 1358971013U, // SUXC1
+ 1358971013U, // SUXC164
+ 1358971013U, // SUXC1_MM
+ 58745730U, // SW
+ 58737124U, // SW16_MM
+ 58745730U, // SW64
+ 58736746U, // SWC1
+ 58736746U, // SWC1_MM
+ 58736920U, // SWC2
+ 58736920U, // SWC2_R6
+ 58736965U, // SWC3
+ 58742642U, // SWL
+ 58742642U, // SWL64
+ 58742642U, // SWL_MM
+ 3522963U, // SWM16_MM
+ 3522792U, // SWM32_MM
+ 3528600U, // SWM_MM
+ 137295U, // SWP_MM
+ 58743059U, // SWR
+ 58743059U, // SWR64
+ 58743059U, // SWR_MM
+ 58745730U, // SWSP_MM
+ 1358971027U, // SWXC1
+ 1358971027U, // SWXC1_MM
+ 58745730U, // SW_MM
+ 549939U, // SYNC
+ 153021U, // SYNCI
+ 549939U, // SYNC_MM
+ 546590U, // SYSCALL
+ 546590U, // SYSCALL_MM
+ 0U, // SZ_B_PSEUDO
+ 0U, // SZ_D_PSEUDO
+ 0U, // SZ_H_PSEUDO
+ 0U, // SZ_V_PSEUDO
+ 0U, // SZ_W_PSEUDO
+ 0U, // Save16
+ 0U, // SaveX16
+ 58738423U, // SbRxRyOffMemX16
+ 549866U, // SebRx16
+ 549878U, // SehRx16
+ 4367299U, // SelBeqZ
+ 4367272U, // SelBneZ
+ 1828886516U, // SelTBteqZCmp
+ 1828886024U, // SelTBteqZCmpi
+ 1828887485U, // SelTBteqZSlt
+ 1828886054U, // SelTBteqZSlti
+ 1828887593U, // SelTBteqZSltiu
+ 1828887629U, // SelTBteqZSltu
+ 1963104244U, // SelTBtneZCmp
+ 1963103752U, // SelTBtneZCmpi
+ 1963105213U, // SelTBtneZSlt
+ 1963103782U, // SelTBtneZSlti
+ 1963105321U, // SelTBtneZSltiu
+ 1963105357U, // SelTBtneZSltu
+ 58742195U, // ShRxRyOffMemX16
+ 134240058U, // SllX16
+ 16800964U, // SllvRxRy16
+ 92576701U, // SltCCRxRy16
+ 23485U, // SltRxRy16
+ 92575270U, // SltiCCRxImmX16
+ 939546150U, // SltiRxImm16
+ 22054U, // SltiRxImmX16
+ 92576809U, // SltiuCCRxImmX16
+ 939547689U, // SltiuRxImm16
+ 23593U, // SltiuRxImmX16
+ 92576845U, // SltuCCRxRy16
+ 23629U, // SltuRxRy16
+ 92576845U, // SltuRxRyRz16
+ 134234685U, // SraX16
+ 16800943U, // SravRxRy16
+ 134240070U, // SrlX16
+ 16800971U, // SrlvRxRy16
+ 134241247U, // SubuRxRyRz16
+ 58745730U, // SwRxRyOffMemX16
+ 1493197698U, // SwRxSpImmX16
+ 0U, // TAILCALL
+ 0U, // TAILCALL64_R
+ 0U, // TAILCALL_R
+ 134240350U, // TEQ
+ 33576468U, // TEQI
+ 33576468U, // TEQI_MM
+ 134240350U, // TEQ_MM
+ 134238046U, // TGE
+ 33576401U, // TGEI
+ 33578018U, // TGEIU
+ 33578018U, // TGEIU_MM
+ 33576401U, // TGEI_MM
+ 134241288U, // TGEU
+ 134241288U, // TGEU_MM
+ 134238046U, // TGE_MM
+ 9458U, // TLBP
+ 9458U, // TLBP_MM
+ 9469U, // TLBR
+ 9469U, // TLBR_MM
+ 9448U, // TLBWI
+ 9448U, // TLBWI_MM
+ 9474U, // TLBWR
+ 9474U, // TLBWR_MM
+ 134241218U, // TLT
+ 33576492U, // TLTI
+ 33578032U, // TLTIU_MM
+ 33576492U, // TLTI_MM
+ 134241363U, // TLTU
+ 134241363U, // TLTU_MM
+ 134241218U, // TLT_MM
+ 134238068U, // TNE
+ 33576413U, // TNEI
+ 33576413U, // TNEI_MM
+ 134238068U, // TNE_MM
+ 0U, // TRAP
+ 18981U, // TRUNC_L_D64
+ 23009U, // TRUNC_L_S
+ 20157U, // TRUNC_W_D32
+ 20157U, // TRUNC_W_D64
+ 20157U, // TRUNC_W_MM
+ 23331U, // TRUNC_W_S
+ 23331U, // TRUNC_W_S_MM
+ 33578032U, // TTLTIU
+ 25597U, // UDIV
+ 25597U, // UDIV_MM
+ 134241335U, // V3MULU
+ 134234135U, // VMM0
+ 134241350U, // VMULU
+ 151012022U, // VSHF_B
+ 151013760U, // VSHF_D
+ 151015430U, // VSHF_H
+ 151018984U, // VSHF_W
+ 9486U, // WAIT
+ 547767U, // WAIT_MM
+ 33577010U, // WRDSP
+ 21376U, // WSBH
+ 21376U, // WSBH_MM
+ 134240507U, // XOR
+ 836009U, // XOR16_MM
+ 134240507U, // XOR64
+ 2281718581U, // XORI_B
+ 134240507U, // XOR_MM
+ 134241419U, // XOR_V
+ 0U, // XOR_V_D_PSEUDO
+ 0U, // XOR_V_H_PSEUDO
+ 0U, // XOR_V_W_PSEUDO
+ 134239770U, // XORi
+ 134239770U, // XORi64
+ 134239770U, // XORi_MM
+ 16799995U, // XorRxRxRy16
+ 0U
+ };
+
+ static const uint8_t OpInfo2[] = {
+ 0U, // PHI
+ 0U, // INLINEASM
+ 0U, // CFI_INSTRUCTION
+ 0U, // EH_LABEL
+ 0U, // GC_LABEL
+ 0U, // KILL
+ 0U, // EXTRACT_SUBREG
+ 0U, // INSERT_SUBREG
+ 0U, // IMPLICIT_DEF
+ 0U, // SUBREG_TO_REG
+ 0U, // COPY_TO_REGCLASS
+ 0U, // DBG_VALUE
+ 0U, // REG_SEQUENCE
+ 0U, // COPY
+ 0U, // BUNDLE
+ 0U, // LIFETIME_START
+ 0U, // LIFETIME_END
+ 0U, // STACKMAP
+ 0U, // PATCHPOINT
+ 0U, // LOAD_STACK_GUARD
+ 0U, // STATEPOINT
+ 0U, // FRAME_ALLOC
+ 0U, // ABSQ_S_PH
+ 0U, // ABSQ_S_QB
+ 0U, // ABSQ_S_W
+ 0U, // ADD
+ 0U, // ADDIUPC
+ 0U, // ADDIUPC_MM
+ 0U, // ADDIUR1SP_MM
+ 0U, // ADDIUR2_MM
+ 0U, // ADDIUS5_MM
+ 0U, // ADDIUSP_MM
+ 0U, // ADDQH_PH
+ 0U, // ADDQH_R_PH
+ 0U, // ADDQH_R_W
+ 0U, // ADDQH_W
+ 0U, // ADDQ_PH
+ 0U, // ADDQ_S_PH
+ 0U, // ADDQ_S_W
+ 0U, // ADDSC
+ 0U, // ADDS_A_B
+ 0U, // ADDS_A_D
+ 0U, // ADDS_A_H
+ 0U, // ADDS_A_W
+ 0U, // ADDS_S_B
+ 0U, // ADDS_S_D
+ 0U, // ADDS_S_H
+ 0U, // ADDS_S_W
+ 0U, // ADDS_U_B
+ 0U, // ADDS_U_D
+ 0U, // ADDS_U_H
+ 0U, // ADDS_U_W
+ 0U, // ADDU16_MM
+ 0U, // ADDUH_QB
+ 0U, // ADDUH_R_QB
+ 0U, // ADDU_PH
+ 0U, // ADDU_QB
+ 0U, // ADDU_S_PH
+ 0U, // ADDU_S_QB
+ 0U, // ADDVI_B
+ 0U, // ADDVI_D
+ 0U, // ADDVI_H
+ 0U, // ADDVI_W
+ 0U, // ADDV_B
+ 0U, // ADDV_D
+ 0U, // ADDV_H
+ 0U, // ADDV_W
+ 0U, // ADDWC
+ 0U, // ADD_A_B
+ 0U, // ADD_A_D
+ 0U, // ADD_A_H
+ 0U, // ADD_A_W
+ 0U, // ADD_MM
+ 0U, // ADDi
+ 0U, // ADDi_MM
+ 0U, // ADDiu
+ 0U, // ADDiu_MM
+ 0U, // ADDu
+ 0U, // ADDu_MM
+ 0U, // ADJCALLSTACKDOWN
+ 0U, // ADJCALLSTACKUP
+ 4U, // ALIGN
+ 0U, // ALUIPC
+ 0U, // AND
+ 0U, // AND16_MM
+ 0U, // AND64
+ 0U, // ANDI16_MM
+ 0U, // ANDI_B
+ 0U, // AND_MM
+ 0U, // AND_V
+ 0U, // AND_V_D_PSEUDO
+ 0U, // AND_V_H_PSEUDO
+ 0U, // AND_V_W_PSEUDO
+ 1U, // ANDi
+ 1U, // ANDi64
+ 1U, // ANDi_MM
+ 1U, // APPEND
+ 0U, // ASUB_S_B
+ 0U, // ASUB_S_D
+ 0U, // ASUB_S_H
+ 0U, // ASUB_S_W
+ 0U, // ASUB_U_B
+ 0U, // ASUB_U_D
+ 0U, // ASUB_U_H
+ 0U, // ASUB_U_W
+ 0U, // ATOMIC_CMP_SWAP_I16
+ 0U, // ATOMIC_CMP_SWAP_I32
+ 0U, // ATOMIC_CMP_SWAP_I64
+ 0U, // ATOMIC_CMP_SWAP_I8
+ 0U, // ATOMIC_LOAD_ADD_I16
+ 0U, // ATOMIC_LOAD_ADD_I32
+ 0U, // ATOMIC_LOAD_ADD_I64
+ 0U, // ATOMIC_LOAD_ADD_I8
+ 0U, // ATOMIC_LOAD_AND_I16
+ 0U, // ATOMIC_LOAD_AND_I32
+ 0U, // ATOMIC_LOAD_AND_I64
+ 0U, // ATOMIC_LOAD_AND_I8
+ 0U, // ATOMIC_LOAD_NAND_I16
+ 0U, // ATOMIC_LOAD_NAND_I32
+ 0U, // ATOMIC_LOAD_NAND_I64
+ 0U, // ATOMIC_LOAD_NAND_I8
+ 0U, // ATOMIC_LOAD_OR_I16
+ 0U, // ATOMIC_LOAD_OR_I32
+ 0U, // ATOMIC_LOAD_OR_I64
+ 0U, // ATOMIC_LOAD_OR_I8
+ 0U, // ATOMIC_LOAD_SUB_I16
+ 0U, // ATOMIC_LOAD_SUB_I32
+ 0U, // ATOMIC_LOAD_SUB_I64
+ 0U, // ATOMIC_LOAD_SUB_I8
+ 0U, // ATOMIC_LOAD_XOR_I16
+ 0U, // ATOMIC_LOAD_XOR_I32
+ 0U, // ATOMIC_LOAD_XOR_I64
+ 0U, // ATOMIC_LOAD_XOR_I8
+ 0U, // ATOMIC_SWAP_I16
+ 0U, // ATOMIC_SWAP_I32
+ 0U, // ATOMIC_SWAP_I64
+ 0U, // ATOMIC_SWAP_I8
+ 0U, // AUI
+ 0U, // AUIPC
+ 0U, // AVER_S_B
+ 0U, // AVER_S_D
+ 0U, // AVER_S_H
+ 0U, // AVER_S_W
+ 0U, // AVER_U_B
+ 0U, // AVER_U_D
+ 0U, // AVER_U_H
+ 0U, // AVER_U_W
+ 0U, // AVE_S_B
+ 0U, // AVE_S_D
+ 0U, // AVE_S_H
+ 0U, // AVE_S_W
+ 0U, // AVE_U_B
+ 0U, // AVE_U_D
+ 0U, // AVE_U_H
+ 0U, // AVE_U_W
+ 0U, // AddiuRxImmX16
+ 0U, // AddiuRxPcImmX16
+ 0U, // AddiuRxRxImm16
+ 0U, // AddiuRxRxImmX16
+ 0U, // AddiuRxRyOffMemX16
+ 0U, // AddiuSpImm16
+ 0U, // AddiuSpImmX16
+ 0U, // AdduRxRyRz16
+ 0U, // AndRxRxRy16
+ 0U, // B
+ 0U, // B16_MM
+ 0U, // BADDu
+ 0U, // BAL
+ 0U, // BALC
+ 1U, // BALIGN
+ 0U, // BAL_BR
+ 0U, // BBIT0
+ 0U, // BBIT032
+ 0U, // BBIT1
+ 0U, // BBIT132
+ 0U, // BC
+ 0U, // BC0F
+ 0U, // BC0FL
+ 0U, // BC0T
+ 0U, // BC0TL
+ 0U, // BC1EQZ
+ 0U, // BC1F
+ 0U, // BC1FL
+ 0U, // BC1F_MM
+ 0U, // BC1NEZ
+ 0U, // BC1T
+ 0U, // BC1TL
+ 0U, // BC1T_MM
+ 0U, // BC2EQZ
+ 0U, // BC2F
+ 0U, // BC2FL
+ 0U, // BC2NEZ
+ 0U, // BC2T
+ 0U, // BC2TL
+ 0U, // BC3F
+ 0U, // BC3FL
+ 0U, // BC3T
+ 0U, // BC3TL
+ 0U, // BCLRI_B
+ 0U, // BCLRI_D
+ 0U, // BCLRI_H
+ 0U, // BCLRI_W
+ 0U, // BCLR_B
+ 0U, // BCLR_D
+ 0U, // BCLR_H
+ 0U, // BCLR_W
+ 0U, // BEQ
+ 0U, // BEQ64
+ 0U, // BEQC
+ 0U, // BEQL
+ 0U, // BEQZ16_MM
+ 0U, // BEQZALC
+ 0U, // BEQZC
+ 0U, // BEQZC_MM
+ 0U, // BEQ_MM
+ 0U, // BGEC
+ 0U, // BGEUC
+ 0U, // BGEZ
+ 0U, // BGEZ64
+ 0U, // BGEZAL
+ 0U, // BGEZALC
+ 0U, // BGEZALL
+ 0U, // BGEZALS_MM
+ 0U, // BGEZAL_MM
+ 0U, // BGEZC
+ 0U, // BGEZL
+ 0U, // BGEZ_MM
+ 0U, // BGTZ
+ 0U, // BGTZ64
+ 0U, // BGTZALC
+ 0U, // BGTZC
+ 0U, // BGTZL
+ 0U, // BGTZ_MM
+ 1U, // BINSLI_B
+ 1U, // BINSLI_D
+ 1U, // BINSLI_H
+ 1U, // BINSLI_W
+ 2U, // BINSL_B
+ 2U, // BINSL_D
+ 2U, // BINSL_H
+ 2U, // BINSL_W
+ 1U, // BINSRI_B
+ 1U, // BINSRI_D
+ 1U, // BINSRI_H
+ 1U, // BINSRI_W
+ 2U, // BINSR_B
+ 2U, // BINSR_D
+ 2U, // BINSR_H
+ 2U, // BINSR_W
+ 0U, // BITREV
+ 0U, // BITSWAP
+ 0U, // BLEZ
+ 0U, // BLEZ64
+ 0U, // BLEZALC
+ 0U, // BLEZC
+ 0U, // BLEZL
+ 0U, // BLEZ_MM
+ 0U, // BLTC
+ 0U, // BLTUC
+ 0U, // BLTZ
+ 0U, // BLTZ64
+ 0U, // BLTZAL
+ 0U, // BLTZALC
+ 0U, // BLTZALL
+ 0U, // BLTZALS_MM
+ 0U, // BLTZAL_MM
+ 0U, // BLTZC
+ 0U, // BLTZL
+ 0U, // BLTZ_MM
+ 1U, // BMNZI_B
+ 2U, // BMNZ_V
+ 1U, // BMZI_B
+ 2U, // BMZ_V
+ 0U, // BNE
+ 0U, // BNE64
+ 0U, // BNEC
+ 0U, // BNEGI_B
+ 0U, // BNEGI_D
+ 0U, // BNEGI_H
+ 0U, // BNEGI_W
+ 0U, // BNEG_B
+ 0U, // BNEG_D
+ 0U, // BNEG_H
+ 0U, // BNEG_W
+ 0U, // BNEL
+ 0U, // BNEZ16_MM
+ 0U, // BNEZALC
+ 0U, // BNEZC
+ 0U, // BNEZC_MM
+ 0U, // BNE_MM
+ 0U, // BNVC
+ 0U, // BNZ_B
+ 0U, // BNZ_D
+ 0U, // BNZ_H
+ 0U, // BNZ_V
+ 0U, // BNZ_W
+ 0U, // BOVC
+ 0U, // BPOSGE32
+ 0U, // BPOSGE32_PSEUDO
+ 0U, // BREAK
+ 0U, // BREAK16_MM
+ 0U, // BREAK_MM
+ 1U, // BSELI_B
+ 0U, // BSEL_D_PSEUDO
+ 0U, // BSEL_FD_PSEUDO
+ 0U, // BSEL_FW_PSEUDO
+ 0U, // BSEL_H_PSEUDO
+ 2U, // BSEL_V
+ 0U, // BSEL_W_PSEUDO
+ 0U, // BSETI_B
+ 0U, // BSETI_D
+ 0U, // BSETI_H
+ 0U, // BSETI_W
+ 0U, // BSET_B
+ 0U, // BSET_D
+ 0U, // BSET_H
+ 0U, // BSET_W
+ 0U, // BZ_B
+ 0U, // BZ_D
+ 0U, // BZ_H
+ 0U, // BZ_V
+ 0U, // BZ_W
+ 0U, // B_MM_Pseudo
+ 0U, // BeqzRxImm16
+ 0U, // BeqzRxImmX16
+ 0U, // Bimm16
+ 0U, // BimmX16
+ 0U, // BnezRxImm16
+ 0U, // BnezRxImmX16
+ 0U, // Break16
+ 0U, // Bteqz16
+ 0U, // BteqzT8CmpX16
+ 0U, // BteqzT8CmpiX16
+ 0U, // BteqzT8SltX16
+ 0U, // BteqzT8SltiX16
+ 0U, // BteqzT8SltiuX16
+ 0U, // BteqzT8SltuX16
+ 0U, // BteqzX16
+ 0U, // Btnez16
+ 0U, // BtnezT8CmpX16
+ 0U, // BtnezT8CmpiX16
+ 0U, // BtnezT8SltX16
+ 0U, // BtnezT8SltiX16
+ 0U, // BtnezT8SltiuX16
+ 0U, // BtnezT8SltuX16
+ 0U, // BtnezX16
+ 0U, // BuildPairF64
+ 0U, // BuildPairF64_64
+ 0U, // CACHE
+ 0U, // CACHE_MM
+ 0U, // CACHE_R6
+ 0U, // CEIL_L_D64
+ 0U, // CEIL_L_S
+ 0U, // CEIL_W_D32
+ 0U, // CEIL_W_D64
+ 0U, // CEIL_W_MM
+ 0U, // CEIL_W_S
+ 0U, // CEIL_W_S_MM
+ 0U, // CEQI_B
+ 0U, // CEQI_D
+ 0U, // CEQI_H
+ 0U, // CEQI_W
+ 0U, // CEQ_B
+ 0U, // CEQ_D
+ 0U, // CEQ_H
+ 0U, // CEQ_W
+ 0U, // CFC1
+ 0U, // CFC1_MM
+ 0U, // CFCMSA
+ 5U, // CINS
+ 5U, // CINS32
+ 0U, // CLASS_D
+ 0U, // CLASS_S
+ 0U, // CLEI_S_B
+ 0U, // CLEI_S_D
+ 0U, // CLEI_S_H
+ 0U, // CLEI_S_W
+ 0U, // CLEI_U_B
+ 0U, // CLEI_U_D
+ 0U, // CLEI_U_H
+ 0U, // CLEI_U_W
+ 0U, // CLE_S_B
+ 0U, // CLE_S_D
+ 0U, // CLE_S_H
+ 0U, // CLE_S_W
+ 0U, // CLE_U_B
+ 0U, // CLE_U_D
+ 0U, // CLE_U_H
+ 0U, // CLE_U_W
+ 0U, // CLO
+ 0U, // CLO_MM
+ 0U, // CLO_R6
+ 0U, // CLTI_S_B
+ 0U, // CLTI_S_D
+ 0U, // CLTI_S_H
+ 0U, // CLTI_S_W
+ 0U, // CLTI_U_B
+ 0U, // CLTI_U_D
+ 0U, // CLTI_U_H
+ 0U, // CLTI_U_W
+ 0U, // CLT_S_B
+ 0U, // CLT_S_D
+ 0U, // CLT_S_H
+ 0U, // CLT_S_W
+ 0U, // CLT_U_B
+ 0U, // CLT_U_D
+ 0U, // CLT_U_H
+ 0U, // CLT_U_W
+ 0U, // CLZ
+ 0U, // CLZ_MM
+ 0U, // CLZ_R6
+ 0U, // CMPGDU_EQ_QB
+ 0U, // CMPGDU_LE_QB
+ 0U, // CMPGDU_LT_QB
+ 0U, // CMPGU_EQ_QB
+ 0U, // CMPGU_LE_QB
+ 0U, // CMPGU_LT_QB
+ 0U, // CMPU_EQ_QB
+ 0U, // CMPU_LE_QB
+ 0U, // CMPU_LT_QB
+ 0U, // CMP_EQ_D
+ 0U, // CMP_EQ_PH
+ 0U, // CMP_EQ_S
+ 0U, // CMP_F_D
+ 0U, // CMP_F_S
+ 0U, // CMP_LE_D
+ 0U, // CMP_LE_PH
+ 0U, // CMP_LE_S
+ 0U, // CMP_LT_D
+ 0U, // CMP_LT_PH
+ 0U, // CMP_LT_S
+ 0U, // CMP_SAF_D
+ 0U, // CMP_SAF_S
+ 0U, // CMP_SEQ_D
+ 0U, // CMP_SEQ_S
+ 0U, // CMP_SLE_D
+ 0U, // CMP_SLE_S
+ 0U, // CMP_SLT_D
+ 0U, // CMP_SLT_S
+ 0U, // CMP_SUEQ_D
+ 0U, // CMP_SUEQ_S
+ 0U, // CMP_SULE_D
+ 0U, // CMP_SULE_S
+ 0U, // CMP_SULT_D
+ 0U, // CMP_SULT_S
+ 0U, // CMP_SUN_D
+ 0U, // CMP_SUN_S
+ 0U, // CMP_UEQ_D
+ 0U, // CMP_UEQ_S
+ 0U, // CMP_ULE_D
+ 0U, // CMP_ULE_S
+ 0U, // CMP_ULT_D
+ 0U, // CMP_ULT_S
+ 0U, // CMP_UN_D
+ 0U, // CMP_UN_S
+ 0U, // CONSTPOOL_ENTRY
+ 0U, // COPY_FD_PSEUDO
+ 0U, // COPY_FW_PSEUDO
+ 8U, // COPY_S_B
+ 8U, // COPY_S_D
+ 8U, // COPY_S_H
+ 8U, // COPY_S_W
+ 8U, // COPY_U_B
+ 8U, // COPY_U_D
+ 8U, // COPY_U_H
+ 8U, // COPY_U_W
+ 0U, // CTC1
+ 0U, // CTC1_MM
+ 0U, // CTCMSA
+ 0U, // CVT_D32_S
+ 0U, // CVT_D32_W
+ 0U, // CVT_D32_W_MM
+ 0U, // CVT_D64_L
+ 0U, // CVT_D64_S
+ 0U, // CVT_D64_W
+ 0U, // CVT_D_S_MM
+ 0U, // CVT_L_D64
+ 0U, // CVT_L_D64_MM
+ 0U, // CVT_L_S
+ 0U, // CVT_L_S_MM
+ 0U, // CVT_S_D32
+ 0U, // CVT_S_D32_MM
+ 0U, // CVT_S_D64
+ 0U, // CVT_S_L
+ 0U, // CVT_S_W
+ 0U, // CVT_S_W_MM
+ 0U, // CVT_W_D32
+ 0U, // CVT_W_D64
+ 0U, // CVT_W_MM
+ 0U, // CVT_W_S
+ 0U, // CVT_W_S_MM
+ 0U, // C_EQ_D32
+ 0U, // C_EQ_D64
+ 0U, // C_EQ_S
+ 0U, // C_F_D32
+ 0U, // C_F_D64
+ 0U, // C_F_S
+ 0U, // C_LE_D32
+ 0U, // C_LE_D64
+ 0U, // C_LE_S
+ 0U, // C_LT_D32
+ 0U, // C_LT_D64
+ 0U, // C_LT_S
+ 0U, // C_NGE_D32
+ 0U, // C_NGE_D64
+ 0U, // C_NGE_S
+ 0U, // C_NGLE_D32
+ 0U, // C_NGLE_D64
+ 0U, // C_NGLE_S
+ 0U, // C_NGL_D32
+ 0U, // C_NGL_D64
+ 0U, // C_NGL_S
+ 0U, // C_NGT_D32
+ 0U, // C_NGT_D64
+ 0U, // C_NGT_S
+ 0U, // C_OLE_D32
+ 0U, // C_OLE_D64
+ 0U, // C_OLE_S
+ 0U, // C_OLT_D32
+ 0U, // C_OLT_D64
+ 0U, // C_OLT_S
+ 0U, // C_SEQ_D32
+ 0U, // C_SEQ_D64
+ 0U, // C_SEQ_S
+ 0U, // C_SF_D32
+ 0U, // C_SF_D64
+ 0U, // C_SF_S
+ 0U, // C_UEQ_D32
+ 0U, // C_UEQ_D64
+ 0U, // C_UEQ_S
+ 0U, // C_ULE_D32
+ 0U, // C_ULE_D64
+ 0U, // C_ULE_S
+ 0U, // C_ULT_D32
+ 0U, // C_ULT_D64
+ 0U, // C_ULT_S
+ 0U, // C_UN_D32
+ 0U, // C_UN_D64
+ 0U, // C_UN_S
+ 0U, // CmpRxRy16
+ 0U, // CmpiRxImm16
+ 0U, // CmpiRxImmX16
+ 0U, // Constant32
+ 0U, // DADD
+ 0U, // DADDi
+ 0U, // DADDiu
+ 0U, // DADDu
+ 0U, // DAHI
+ 4U, // DALIGN
+ 0U, // DATI
+ 0U, // DAUI
+ 0U, // DBITSWAP
+ 0U, // DCLO
+ 0U, // DCLO_R6
+ 0U, // DCLZ
+ 0U, // DCLZ_R6
+ 0U, // DDIV
+ 0U, // DDIVU
+ 0U, // DERET
+ 0U, // DERET_MM
+ 21U, // DEXT
+ 21U, // DEXTM
+ 21U, // DEXTU
+ 0U, // DI
+ 21U, // DINS
+ 21U, // DINSM
+ 21U, // DINSU
+ 0U, // DIV
+ 0U, // DIVU
+ 0U, // DIV_S_B
+ 0U, // DIV_S_D
+ 0U, // DIV_S_H
+ 0U, // DIV_S_W
+ 0U, // DIV_U_B
+ 0U, // DIV_U_D
+ 0U, // DIV_U_H
+ 0U, // DIV_U_W
+ 0U, // DI_MM
+ 4U, // DLSA
+ 4U, // DLSA_R6
+ 1U, // DMFC0
+ 0U, // DMFC1
+ 1U, // DMFC2
+ 0U, // DMOD
+ 0U, // DMODU
+ 1U, // DMTC0
+ 0U, // DMTC1
+ 1U, // DMTC2
+ 0U, // DMUH
+ 0U, // DMUHU
+ 0U, // DMUL
+ 0U, // DMULT
+ 0U, // DMULTu
+ 0U, // DMULU
+ 0U, // DMUL_R6
+ 0U, // DOTP_S_D
+ 0U, // DOTP_S_H
+ 0U, // DOTP_S_W
+ 0U, // DOTP_U_D
+ 0U, // DOTP_U_H
+ 0U, // DOTP_U_W
+ 2U, // DPADD_S_D
+ 2U, // DPADD_S_H
+ 2U, // DPADD_S_W
+ 2U, // DPADD_U_D
+ 2U, // DPADD_U_H
+ 2U, // DPADD_U_W
+ 0U, // DPAQX_SA_W_PH
+ 0U, // DPAQX_S_W_PH
+ 0U, // DPAQ_SA_L_W
+ 0U, // DPAQ_S_W_PH
+ 0U, // DPAU_H_QBL
+ 0U, // DPAU_H_QBR
+ 0U, // DPAX_W_PH
+ 0U, // DPA_W_PH
+ 0U, // DPOP
+ 0U, // DPSQX_SA_W_PH
+ 0U, // DPSQX_S_W_PH
+ 0U, // DPSQ_SA_L_W
+ 0U, // DPSQ_S_W_PH
+ 2U, // DPSUB_S_D
+ 2U, // DPSUB_S_H
+ 2U, // DPSUB_S_W
+ 2U, // DPSUB_U_D
+ 2U, // DPSUB_U_H
+ 2U, // DPSUB_U_W
+ 0U, // DPSU_H_QBL
+ 0U, // DPSU_H_QBR
+ 0U, // DPSX_W_PH
+ 0U, // DPS_W_PH
+ 1U, // DROTR
+ 1U, // DROTR32
+ 0U, // DROTRV
+ 0U, // DSBH
+ 0U, // DSDIV
+ 0U, // DSHD
+ 1U, // DSLL
+ 1U, // DSLL32
+ 0U, // DSLL64_32
+ 0U, // DSLLV
+ 1U, // DSRA
+ 1U, // DSRA32
+ 0U, // DSRAV
+ 1U, // DSRL
+ 1U, // DSRL32
+ 0U, // DSRLV
+ 0U, // DSUB
+ 0U, // DSUBu
+ 0U, // DUDIV
+ 0U, // DivRxRy16
+ 0U, // DivuRxRy16
+ 0U, // EHB
+ 0U, // EHB_MM
+ 0U, // EI
+ 0U, // EI_MM
+ 0U, // ERET
+ 0U, // ERET_MM
+ 21U, // EXT
+ 1U, // EXTP
+ 1U, // EXTPDP
+ 0U, // EXTPDPV
+ 0U, // EXTPV
+ 0U, // EXTRV_RS_W
+ 0U, // EXTRV_R_W
+ 0U, // EXTRV_S_H
+ 0U, // EXTRV_W
+ 1U, // EXTR_RS_W
+ 1U, // EXTR_R_W
+ 1U, // EXTR_S_H
+ 1U, // EXTR_W
+ 5U, // EXTS
+ 5U, // EXTS32
+ 21U, // EXT_MM
+ 0U, // ExtractElementF64
+ 0U, // ExtractElementF64_64
+ 0U, // FABS_D
+ 0U, // FABS_D32
+ 0U, // FABS_D64
+ 0U, // FABS_MM
+ 0U, // FABS_S
+ 0U, // FABS_S_MM
+ 0U, // FABS_W
+ 0U, // FADD_D
+ 0U, // FADD_D32
+ 0U, // FADD_D64
+ 0U, // FADD_MM
+ 0U, // FADD_S
+ 0U, // FADD_S_MM
+ 0U, // FADD_W
+ 0U, // FCAF_D
+ 0U, // FCAF_W
+ 0U, // FCEQ_D
+ 0U, // FCEQ_W
+ 0U, // FCLASS_D
+ 0U, // FCLASS_W
+ 0U, // FCLE_D
+ 0U, // FCLE_W
+ 0U, // FCLT_D
+ 0U, // FCLT_W
+ 0U, // FCMP_D32
+ 0U, // FCMP_D32_MM
+ 0U, // FCMP_D64
+ 0U, // FCMP_S32
+ 0U, // FCMP_S32_MM
+ 0U, // FCNE_D
+ 0U, // FCNE_W
+ 0U, // FCOR_D
+ 0U, // FCOR_W
+ 0U, // FCUEQ_D
+ 0U, // FCUEQ_W
+ 0U, // FCULE_D
+ 0U, // FCULE_W
+ 0U, // FCULT_D
+ 0U, // FCULT_W
+ 0U, // FCUNE_D
+ 0U, // FCUNE_W
+ 0U, // FCUN_D
+ 0U, // FCUN_W
+ 0U, // FDIV_D
+ 0U, // FDIV_D32
+ 0U, // FDIV_D64
+ 0U, // FDIV_MM
+ 0U, // FDIV_S
+ 0U, // FDIV_S_MM
+ 0U, // FDIV_W
+ 0U, // FEXDO_H
+ 0U, // FEXDO_W
+ 0U, // FEXP2_D
+ 0U, // FEXP2_D_1_PSEUDO
+ 0U, // FEXP2_W
+ 0U, // FEXP2_W_1_PSEUDO
+ 0U, // FEXUPL_D
+ 0U, // FEXUPL_W
+ 0U, // FEXUPR_D
+ 0U, // FEXUPR_W
+ 0U, // FFINT_S_D
+ 0U, // FFINT_S_W
+ 0U, // FFINT_U_D
+ 0U, // FFINT_U_W
+ 0U, // FFQL_D
+ 0U, // FFQL_W
+ 0U, // FFQR_D
+ 0U, // FFQR_W
+ 0U, // FILL_B
+ 0U, // FILL_D
+ 0U, // FILL_FD_PSEUDO
+ 0U, // FILL_FW_PSEUDO
+ 0U, // FILL_H
+ 0U, // FILL_W
+ 0U, // FLOG2_D
+ 0U, // FLOG2_W
+ 0U, // FLOOR_L_D64
+ 0U, // FLOOR_L_S
+ 0U, // FLOOR_W_D32
+ 0U, // FLOOR_W_D64
+ 0U, // FLOOR_W_MM
+ 0U, // FLOOR_W_S
+ 0U, // FLOOR_W_S_MM
+ 2U, // FMADD_D
+ 2U, // FMADD_W
+ 0U, // FMAX_A_D
+ 0U, // FMAX_A_W
+ 0U, // FMAX_D
+ 0U, // FMAX_W
+ 0U, // FMIN_A_D
+ 0U, // FMIN_A_W
+ 0U, // FMIN_D
+ 0U, // FMIN_W
+ 0U, // FMOV_D32
+ 0U, // FMOV_D32_MM
+ 0U, // FMOV_D64
+ 0U, // FMOV_S
+ 0U, // FMOV_S_MM
+ 2U, // FMSUB_D
+ 2U, // FMSUB_W
+ 0U, // FMUL_D
+ 0U, // FMUL_D32
+ 0U, // FMUL_D64
+ 0U, // FMUL_MM
+ 0U, // FMUL_S
+ 0U, // FMUL_S_MM
+ 0U, // FMUL_W
+ 0U, // FNEG_D32
+ 0U, // FNEG_D64
+ 0U, // FNEG_MM
+ 0U, // FNEG_S
+ 0U, // FNEG_S_MM
+ 0U, // FRCP_D
+ 0U, // FRCP_W
+ 0U, // FRINT_D
+ 0U, // FRINT_W
+ 0U, // FRSQRT_D
+ 0U, // FRSQRT_W
+ 0U, // FSAF_D
+ 0U, // FSAF_W
+ 0U, // FSEQ_D
+ 0U, // FSEQ_W
+ 0U, // FSLE_D
+ 0U, // FSLE_W
+ 0U, // FSLT_D
+ 0U, // FSLT_W
+ 0U, // FSNE_D
+ 0U, // FSNE_W
+ 0U, // FSOR_D
+ 0U, // FSOR_W
+ 0U, // FSQRT_D
+ 0U, // FSQRT_D32
+ 0U, // FSQRT_D64
+ 0U, // FSQRT_MM
+ 0U, // FSQRT_S
+ 0U, // FSQRT_S_MM
+ 0U, // FSQRT_W
+ 0U, // FSUB_D
+ 0U, // FSUB_D32
+ 0U, // FSUB_D64
+ 0U, // FSUB_MM
+ 0U, // FSUB_S
+ 0U, // FSUB_S_MM
+ 0U, // FSUB_W
+ 0U, // FSUEQ_D
+ 0U, // FSUEQ_W
+ 0U, // FSULE_D
+ 0U, // FSULE_W
+ 0U, // FSULT_D
+ 0U, // FSULT_W
+ 0U, // FSUNE_D
+ 0U, // FSUNE_W
+ 0U, // FSUN_D
+ 0U, // FSUN_W
+ 0U, // FTINT_S_D
+ 0U, // FTINT_S_W
+ 0U, // FTINT_U_D
+ 0U, // FTINT_U_W
+ 0U, // FTQ_H
+ 0U, // FTQ_W
+ 0U, // FTRUNC_S_D
+ 0U, // FTRUNC_S_W
+ 0U, // FTRUNC_U_D
+ 0U, // FTRUNC_U_W
+ 0U, // GotPrologue16
+ 0U, // HADD_S_D
+ 0U, // HADD_S_H
+ 0U, // HADD_S_W
+ 0U, // HADD_U_D
+ 0U, // HADD_U_H
+ 0U, // HADD_U_W
+ 0U, // HSUB_S_D
+ 0U, // HSUB_S_H
+ 0U, // HSUB_S_W
+ 0U, // HSUB_U_D
+ 0U, // HSUB_U_H
+ 0U, // HSUB_U_W
+ 0U, // ILVEV_B
+ 0U, // ILVEV_D
+ 0U, // ILVEV_H
+ 0U, // ILVEV_W
+ 0U, // ILVL_B
+ 0U, // ILVL_D
+ 0U, // ILVL_H
+ 0U, // ILVL_W
+ 0U, // ILVOD_B
+ 0U, // ILVOD_D
+ 0U, // ILVOD_H
+ 0U, // ILVOD_W
+ 0U, // ILVR_B
+ 0U, // ILVR_D
+ 0U, // ILVR_H
+ 0U, // ILVR_W
+ 21U, // INS
+ 0U, // INSERT_B
+ 0U, // INSERT_B_VIDX_PSEUDO
+ 0U, // INSERT_D
+ 0U, // INSERT_D_VIDX_PSEUDO
+ 0U, // INSERT_FD_PSEUDO
+ 0U, // INSERT_FD_VIDX_PSEUDO
+ 0U, // INSERT_FW_PSEUDO
+ 0U, // INSERT_FW_VIDX_PSEUDO
+ 0U, // INSERT_H
+ 0U, // INSERT_H_VIDX_PSEUDO
+ 0U, // INSERT_W
+ 0U, // INSERT_W_VIDX_PSEUDO
+ 0U, // INSV
+ 0U, // INSVE_B
+ 0U, // INSVE_D
+ 0U, // INSVE_H
+ 0U, // INSVE_W
+ 21U, // INS_MM
+ 0U, // J
+ 0U, // JAL
+ 0U, // JALR
+ 0U, // JALR16_MM
+ 0U, // JALR64
+ 0U, // JALR64Pseudo
+ 0U, // JALRPseudo
+ 0U, // JALRS16_MM
+ 0U, // JALRS_MM
+ 0U, // JALR_HB
+ 0U, // JALR_MM
+ 0U, // JALS_MM
+ 0U, // JALX
+ 0U, // JALX_MM
+ 0U, // JAL_MM
+ 0U, // JIALC
+ 0U, // JIC
+ 0U, // JR
+ 0U, // JR16_MM
+ 0U, // JR64
+ 0U, // JRADDIUSP
+ 0U, // JRC16_MM
+ 0U, // JR_HB
+ 0U, // JR_HB_R6
+ 0U, // JR_MM
+ 0U, // J_MM
+ 0U, // Jal16
+ 0U, // JalB16
+ 0U, // JalOneReg
+ 0U, // JalTwoReg
+ 0U, // JrRa16
+ 0U, // JrcRa16
+ 0U, // JrcRx16
+ 0U, // JumpLinkReg16
+ 0U, // LB
+ 0U, // LB64
+ 0U, // LBU16_MM
+ 0U, // LBUX
+ 0U, // LB_MM
+ 0U, // LBu
+ 0U, // LBu64
+ 0U, // LBu_MM
+ 0U, // LD
+ 0U, // LDC1
+ 0U, // LDC164
+ 0U, // LDC1_MM
+ 0U, // LDC2
+ 0U, // LDC2_R6
+ 0U, // LDC3
+ 0U, // LDI_B
+ 0U, // LDI_D
+ 0U, // LDI_H
+ 0U, // LDI_W
+ 0U, // LDL
+ 0U, // LDPC
+ 0U, // LDR
+ 0U, // LDXC1
+ 0U, // LDXC164
+ 0U, // LD_B
+ 0U, // LD_D
+ 0U, // LD_H
+ 0U, // LD_W
+ 0U, // LEA_ADDiu
+ 0U, // LEA_ADDiu64
+ 0U, // LEA_ADDiu_MM
+ 0U, // LH
+ 0U, // LH64
+ 0U, // LHU16_MM
+ 0U, // LHX
+ 0U, // LH_MM
+ 0U, // LHu
+ 0U, // LHu64
+ 0U, // LHu_MM
+ 0U, // LI16_MM
+ 0U, // LL
+ 0U, // LLD
+ 0U, // LLD_R6
+ 0U, // LL_MM
+ 0U, // LL_R6
+ 0U, // LOAD_ACC128
+ 0U, // LOAD_ACC64
+ 0U, // LOAD_ACC64DSP
+ 0U, // LOAD_CCOND_DSP
+ 0U, // LONG_BRANCH_ADDiu
+ 0U, // LONG_BRANCH_DADDiu
+ 0U, // LONG_BRANCH_LUi
+ 4U, // LSA
+ 4U, // LSA_R6
+ 0U, // LUXC1
+ 0U, // LUXC164
+ 0U, // LUXC1_MM
+ 0U, // LUi
+ 0U, // LUi64
+ 0U, // LUi_MM
+ 0U, // LW
+ 0U, // LW16_MM
+ 0U, // LW64
+ 0U, // LWC1
+ 0U, // LWC1_MM
+ 0U, // LWC2
+ 0U, // LWC2_R6
+ 0U, // LWC3
+ 0U, // LWGP_MM
+ 0U, // LWL
+ 0U, // LWL64
+ 0U, // LWL_MM
+ 0U, // LWM16_MM
+ 0U, // LWM32_MM
+ 0U, // LWM_MM
+ 0U, // LWPC
+ 0U, // LWP_MM
+ 0U, // LWR
+ 0U, // LWR64
+ 0U, // LWR_MM
+ 0U, // LWSP_MM
+ 0U, // LWUPC
+ 0U, // LWU_MM
+ 0U, // LWX
+ 0U, // LWXC1
+ 0U, // LWXC1_MM
+ 0U, // LWXS_MM
+ 0U, // LW_MM
+ 0U, // LWu
+ 0U, // LbRxRyOffMemX16
+ 0U, // LbuRxRyOffMemX16
+ 0U, // LhRxRyOffMemX16
+ 0U, // LhuRxRyOffMemX16
+ 0U, // LiRxImm16
+ 0U, // LiRxImmAlignX16
+ 0U, // LiRxImmX16
+ 0U, // LoadAddr32Imm
+ 0U, // LoadAddr32Reg
+ 0U, // LoadImm32Reg
+ 0U, // LoadImm64Reg
+ 0U, // LwConstant32
+ 0U, // LwRxPcTcp16
+ 0U, // LwRxPcTcpX16
+ 0U, // LwRxRyOffMemX16
+ 0U, // LwRxSpImmX16
+ 0U, // MADD
+ 2U, // MADDF_D
+ 2U, // MADDF_S
+ 2U, // MADDR_Q_H
+ 2U, // MADDR_Q_W
+ 0U, // MADDU
+ 0U, // MADDU_DSP
+ 0U, // MADDU_MM
+ 2U, // MADDV_B
+ 2U, // MADDV_D
+ 2U, // MADDV_H
+ 2U, // MADDV_W
+ 20U, // MADD_D32
+ 20U, // MADD_D32_MM
+ 20U, // MADD_D64
+ 0U, // MADD_DSP
+ 0U, // MADD_MM
+ 2U, // MADD_Q_H
+ 2U, // MADD_Q_W
+ 20U, // MADD_S
+ 20U, // MADD_S_MM
+ 0U, // MAQ_SA_W_PHL
+ 0U, // MAQ_SA_W_PHR
+ 0U, // MAQ_S_W_PHL
+ 0U, // MAQ_S_W_PHR
+ 0U, // MAXA_D
+ 0U, // MAXA_S
+ 0U, // MAXI_S_B
+ 0U, // MAXI_S_D
+ 0U, // MAXI_S_H
+ 0U, // MAXI_S_W
+ 0U, // MAXI_U_B
+ 0U, // MAXI_U_D
+ 0U, // MAXI_U_H
+ 0U, // MAXI_U_W
+ 0U, // MAX_A_B
+ 0U, // MAX_A_D
+ 0U, // MAX_A_H
+ 0U, // MAX_A_W
+ 0U, // MAX_D
+ 0U, // MAX_S
+ 0U, // MAX_S_B
+ 0U, // MAX_S_D
+ 0U, // MAX_S_H
+ 0U, // MAX_S_W
+ 0U, // MAX_U_B
+ 0U, // MAX_U_D
+ 0U, // MAX_U_H
+ 0U, // MAX_U_W
+ 1U, // MFC0
+ 0U, // MFC1
+ 0U, // MFC1_MM
+ 1U, // MFC2
+ 0U, // MFHC1_D32
+ 0U, // MFHC1_D64
+ 0U, // MFHC1_MM
+ 0U, // MFHI
+ 0U, // MFHI16_MM
+ 0U, // MFHI64
+ 0U, // MFHI_DSP
+ 0U, // MFHI_MM
+ 0U, // MFLO
+ 0U, // MFLO16_MM
+ 0U, // MFLO64
+ 0U, // MFLO_DSP
+ 0U, // MFLO_MM
+ 0U, // MINA_D
+ 0U, // MINA_S
+ 0U, // MINI_S_B
+ 0U, // MINI_S_D
+ 0U, // MINI_S_H
+ 0U, // MINI_S_W
+ 0U, // MINI_U_B
+ 0U, // MINI_U_D
+ 0U, // MINI_U_H
+ 0U, // MINI_U_W
+ 0U, // MIN_A_B
+ 0U, // MIN_A_D
+ 0U, // MIN_A_H
+ 0U, // MIN_A_W
+ 0U, // MIN_D
+ 0U, // MIN_S
+ 0U, // MIN_S_B
+ 0U, // MIN_S_D
+ 0U, // MIN_S_H
+ 0U, // MIN_S_W
+ 0U, // MIN_U_B
+ 0U, // MIN_U_D
+ 0U, // MIN_U_H
+ 0U, // MIN_U_W
+ 0U, // MIPSeh_return32
+ 0U, // MIPSeh_return64
+ 0U, // MOD
+ 0U, // MODSUB
+ 0U, // MODU
+ 0U, // MOD_S_B
+ 0U, // MOD_S_D
+ 0U, // MOD_S_H
+ 0U, // MOD_S_W
+ 0U, // MOD_U_B
+ 0U, // MOD_U_D
+ 0U, // MOD_U_H
+ 0U, // MOD_U_W
+ 0U, // MOVE16_MM
+ 0U, // MOVEP_MM
+ 0U, // MOVE_V
+ 0U, // MOVF_D32
+ 0U, // MOVF_D32_MM
+ 0U, // MOVF_D64
+ 0U, // MOVF_I
+ 0U, // MOVF_I64
+ 0U, // MOVF_I_MM
+ 0U, // MOVF_S
+ 0U, // MOVF_S_MM
+ 0U, // MOVN_I64_D64
+ 0U, // MOVN_I64_I
+ 0U, // MOVN_I64_I64
+ 0U, // MOVN_I64_S
+ 0U, // MOVN_I_D32
+ 0U, // MOVN_I_D32_MM
+ 0U, // MOVN_I_D64
+ 0U, // MOVN_I_I
+ 0U, // MOVN_I_I64
+ 0U, // MOVN_I_MM
+ 0U, // MOVN_I_S
+ 0U, // MOVN_I_S_MM
+ 0U, // MOVT_D32
+ 0U, // MOVT_D32_MM
+ 0U, // MOVT_D64
+ 0U, // MOVT_I
+ 0U, // MOVT_I64
+ 0U, // MOVT_I_MM
+ 0U, // MOVT_S
+ 0U, // MOVT_S_MM
+ 0U, // MOVZ_I64_D64
+ 0U, // MOVZ_I64_I
+ 0U, // MOVZ_I64_I64
+ 0U, // MOVZ_I64_S
+ 0U, // MOVZ_I_D32
+ 0U, // MOVZ_I_D32_MM
+ 0U, // MOVZ_I_D64
+ 0U, // MOVZ_I_I
+ 0U, // MOVZ_I_I64
+ 0U, // MOVZ_I_MM
+ 0U, // MOVZ_I_S
+ 0U, // MOVZ_I_S_MM
+ 0U, // MSUB
+ 2U, // MSUBF_D
+ 2U, // MSUBF_S
+ 2U, // MSUBR_Q_H
+ 2U, // MSUBR_Q_W
+ 0U, // MSUBU
+ 0U, // MSUBU_DSP
+ 0U, // MSUBU_MM
+ 2U, // MSUBV_B
+ 2U, // MSUBV_D
+ 2U, // MSUBV_H
+ 2U, // MSUBV_W
+ 20U, // MSUB_D32
+ 20U, // MSUB_D32_MM
+ 20U, // MSUB_D64
+ 0U, // MSUB_DSP
+ 0U, // MSUB_MM
+ 2U, // MSUB_Q_H
+ 2U, // MSUB_Q_W
+ 20U, // MSUB_S
+ 20U, // MSUB_S_MM
+ 1U, // MTC0
+ 0U, // MTC1
+ 0U, // MTC1_MM
+ 1U, // MTC2
+ 0U, // MTHC1_D32
+ 0U, // MTHC1_D64
+ 0U, // MTHC1_MM
+ 0U, // MTHI
+ 0U, // MTHI64
+ 0U, // MTHI_DSP
+ 0U, // MTHI_MM
+ 0U, // MTHLIP
+ 0U, // MTLO
+ 0U, // MTLO64
+ 0U, // MTLO_DSP
+ 0U, // MTLO_MM
+ 0U, // MTM0
+ 0U, // MTM1
+ 0U, // MTM2
+ 0U, // MTP0
+ 0U, // MTP1
+ 0U, // MTP2
+ 0U, // MUH
+ 0U, // MUHU
+ 0U, // MUL
+ 0U, // MULEQ_S_W_PHL
+ 0U, // MULEQ_S_W_PHR
+ 0U, // MULEU_S_PH_QBL
+ 0U, // MULEU_S_PH_QBR
+ 0U, // MULQ_RS_PH
+ 0U, // MULQ_RS_W
+ 0U, // MULQ_S_PH
+ 0U, // MULQ_S_W
+ 0U, // MULR_Q_H
+ 0U, // MULR_Q_W
+ 0U, // MULSAQ_S_W_PH
+ 0U, // MULSA_W_PH
+ 0U, // MULT
+ 0U, // MULTU_DSP
+ 0U, // MULT_DSP
+ 0U, // MULT_MM
+ 0U, // MULTu
+ 0U, // MULTu_MM
+ 0U, // MULU
+ 0U, // MULV_B
+ 0U, // MULV_D
+ 0U, // MULV_H
+ 0U, // MULV_W
+ 0U, // MUL_MM
+ 0U, // MUL_PH
+ 0U, // MUL_Q_H
+ 0U, // MUL_Q_W
+ 0U, // MUL_R6
+ 0U, // MUL_S_PH
+ 0U, // Mfhi16
+ 0U, // Mflo16
+ 0U, // Move32R16
+ 0U, // MoveR3216
+ 0U, // MultRxRy16
+ 0U, // MultRxRyRz16
+ 0U, // MultuRxRy16
+ 0U, // MultuRxRyRz16
+ 0U, // NLOC_B
+ 0U, // NLOC_D
+ 0U, // NLOC_H
+ 0U, // NLOC_W
+ 0U, // NLZC_B
+ 0U, // NLZC_D
+ 0U, // NLZC_H
+ 0U, // NLZC_W
+ 20U, // NMADD_D32
+ 20U, // NMADD_D32_MM
+ 20U, // NMADD_D64
+ 20U, // NMADD_S
+ 20U, // NMADD_S_MM
+ 20U, // NMSUB_D32
+ 20U, // NMSUB_D32_MM
+ 20U, // NMSUB_D64
+ 20U, // NMSUB_S
+ 20U, // NMSUB_S_MM
+ 0U, // NOP
+ 0U, // NOR
+ 0U, // NOR64
+ 0U, // NORI_B
+ 0U, // NOR_MM
+ 0U, // NOR_V
+ 0U, // NOR_V_D_PSEUDO
+ 0U, // NOR_V_H_PSEUDO
+ 0U, // NOR_V_W_PSEUDO
+ 0U, // NOT16_MM
+ 0U, // NegRxRy16
+ 0U, // NotRxRy16
+ 0U, // OR
+ 0U, // OR16_MM
+ 0U, // OR64
+ 0U, // ORI_B
+ 0U, // OR_MM
+ 0U, // OR_V
+ 0U, // OR_V_D_PSEUDO
+ 0U, // OR_V_H_PSEUDO
+ 0U, // OR_V_W_PSEUDO
+ 1U, // ORi
+ 1U, // ORi64
+ 1U, // ORi_MM
+ 0U, // OrRxRxRy16
+ 0U, // PACKRL_PH
+ 0U, // PAUSE
+ 0U, // PAUSE_MM
+ 0U, // PCKEV_B
+ 0U, // PCKEV_D
+ 0U, // PCKEV_H
+ 0U, // PCKEV_W
+ 0U, // PCKOD_B
+ 0U, // PCKOD_D
+ 0U, // PCKOD_H
+ 0U, // PCKOD_W
+ 0U, // PCNT_B
+ 0U, // PCNT_D
+ 0U, // PCNT_H
+ 0U, // PCNT_W
+ 0U, // PICK_PH
+ 0U, // PICK_QB
+ 0U, // POP
+ 0U, // PRECEQU_PH_QBL
+ 0U, // PRECEQU_PH_QBLA
+ 0U, // PRECEQU_PH_QBR
+ 0U, // PRECEQU_PH_QBRA
+ 0U, // PRECEQ_W_PHL
+ 0U, // PRECEQ_W_PHR
+ 0U, // PRECEU_PH_QBL
+ 0U, // PRECEU_PH_QBLA
+ 0U, // PRECEU_PH_QBR
+ 0U, // PRECEU_PH_QBRA
+ 0U, // PRECRQU_S_QB_PH
+ 0U, // PRECRQ_PH_W
+ 0U, // PRECRQ_QB_PH
+ 0U, // PRECRQ_RS_PH_W
+ 0U, // PRECR_QB_PH
+ 1U, // PRECR_SRA_PH_W
+ 1U, // PRECR_SRA_R_PH_W
+ 0U, // PREF
+ 0U, // PREF_MM
+ 0U, // PREF_R6
+ 1U, // PREPEND
+ 0U, // PseudoCMPU_EQ_QB
+ 0U, // PseudoCMPU_LE_QB
+ 0U, // PseudoCMPU_LT_QB
+ 0U, // PseudoCMP_EQ_PH
+ 0U, // PseudoCMP_LE_PH
+ 0U, // PseudoCMP_LT_PH
+ 0U, // PseudoCVT_D32_W
+ 0U, // PseudoCVT_D64_L
+ 0U, // PseudoCVT_D64_W
+ 0U, // PseudoCVT_S_L
+ 0U, // PseudoCVT_S_W
+ 0U, // PseudoDMULT
+ 0U, // PseudoDMULTu
+ 0U, // PseudoDSDIV
+ 0U, // PseudoDUDIV
+ 0U, // PseudoIndirectBranch
+ 0U, // PseudoIndirectBranch64
+ 0U, // PseudoMADD
+ 0U, // PseudoMADDU
+ 0U, // PseudoMFHI
+ 0U, // PseudoMFHI64
+ 0U, // PseudoMFLO
+ 0U, // PseudoMFLO64
+ 0U, // PseudoMSUB
+ 0U, // PseudoMSUBU
+ 0U, // PseudoMTLOHI
+ 0U, // PseudoMTLOHI64
+ 0U, // PseudoMTLOHI_DSP
+ 0U, // PseudoMULT
+ 0U, // PseudoMULTu
+ 0U, // PseudoPICK_PH
+ 0U, // PseudoPICK_QB
+ 0U, // PseudoReturn
+ 0U, // PseudoReturn64
+ 0U, // PseudoSDIV
+ 0U, // PseudoSELECTFP_F_D32
+ 0U, // PseudoSELECTFP_F_D64
+ 0U, // PseudoSELECTFP_F_I
+ 0U, // PseudoSELECTFP_F_I64
+ 0U, // PseudoSELECTFP_F_S
+ 0U, // PseudoSELECTFP_T_D32
+ 0U, // PseudoSELECTFP_T_D64
+ 0U, // PseudoSELECTFP_T_I
+ 0U, // PseudoSELECTFP_T_I64
+ 0U, // PseudoSELECTFP_T_S
+ 0U, // PseudoSELECT_D32
+ 0U, // PseudoSELECT_D64
+ 0U, // PseudoSELECT_I
+ 0U, // PseudoSELECT_I64
+ 0U, // PseudoSELECT_S
+ 0U, // PseudoUDIV
+ 0U, // RADDU_W_QB
+ 0U, // RDDSP
+ 0U, // RDHWR
+ 0U, // RDHWR64
+ 0U, // RDHWR_MM
+ 0U, // REPLV_PH
+ 0U, // REPLV_QB
+ 0U, // REPL_PH
+ 0U, // REPL_QB
+ 0U, // RINT_D
+ 0U, // RINT_S
+ 1U, // ROTR
+ 0U, // ROTRV
+ 0U, // ROTRV_MM
+ 1U, // ROTR_MM
+ 0U, // ROUND_L_D64
+ 0U, // ROUND_L_S
+ 0U, // ROUND_W_D32
+ 0U, // ROUND_W_D64
+ 0U, // ROUND_W_MM
+ 0U, // ROUND_W_S
+ 0U, // ROUND_W_S_MM
+ 0U, // Restore16
+ 0U, // RestoreX16
+ 0U, // RetRA
+ 0U, // RetRA16
+ 1U, // SAT_S_B
+ 1U, // SAT_S_D
+ 0U, // SAT_S_H
+ 1U, // SAT_S_W
+ 1U, // SAT_U_B
+ 1U, // SAT_U_D
+ 0U, // SAT_U_H
+ 1U, // SAT_U_W
+ 0U, // SB
+ 0U, // SB16_MM
+ 0U, // SB64
+ 0U, // SB_MM
+ 0U, // SC
+ 0U, // SCD
+ 0U, // SCD_R6
+ 0U, // SC_MM
+ 0U, // SC_R6
+ 0U, // SD
+ 0U, // SDBBP
+ 0U, // SDBBP16_MM
+ 0U, // SDBBP_MM
+ 0U, // SDBBP_R6
+ 0U, // SDC1
+ 0U, // SDC164
+ 0U, // SDC1_MM
+ 0U, // SDC2
+ 0U, // SDC2_R6
+ 0U, // SDC3
+ 0U, // SDIV
+ 0U, // SDIV_MM
+ 0U, // SDL
+ 0U, // SDR
+ 0U, // SDXC1
+ 0U, // SDXC164
+ 0U, // SEB
+ 0U, // SEB64
+ 0U, // SEB_MM
+ 0U, // SEH
+ 0U, // SEH64
+ 0U, // SEH_MM
+ 0U, // SELEQZ
+ 0U, // SELEQZ64
+ 0U, // SELEQZ_D
+ 0U, // SELEQZ_S
+ 0U, // SELNEZ
+ 0U, // SELNEZ64
+ 0U, // SELNEZ_D
+ 0U, // SELNEZ_S
+ 2U, // SEL_D
+ 2U, // SEL_S
+ 0U, // SEQ
+ 0U, // SEQi
+ 0U, // SH
+ 0U, // SH16_MM
+ 0U, // SH64
+ 0U, // SHF_B
+ 0U, // SHF_H
+ 0U, // SHF_W
+ 0U, // SHILO
+ 0U, // SHILOV
+ 0U, // SHLLV_PH
+ 0U, // SHLLV_QB
+ 0U, // SHLLV_S_PH
+ 0U, // SHLLV_S_W
+ 1U, // SHLL_PH
+ 1U, // SHLL_QB
+ 1U, // SHLL_S_PH
+ 1U, // SHLL_S_W
+ 0U, // SHRAV_PH
+ 0U, // SHRAV_QB
+ 0U, // SHRAV_R_PH
+ 0U, // SHRAV_R_QB
+ 0U, // SHRAV_R_W
+ 1U, // SHRA_PH
+ 1U, // SHRA_QB
+ 1U, // SHRA_R_PH
+ 1U, // SHRA_R_QB
+ 1U, // SHRA_R_W
+ 0U, // SHRLV_PH
+ 0U, // SHRLV_QB
+ 1U, // SHRL_PH
+ 1U, // SHRL_QB
+ 0U, // SH_MM
+ 9U, // SLDI_B
+ 9U, // SLDI_D
+ 9U, // SLDI_H
+ 9U, // SLDI_W
+ 10U, // SLD_B
+ 10U, // SLD_D
+ 10U, // SLD_H
+ 10U, // SLD_W
+ 1U, // SLL
+ 0U, // SLL16_MM
+ 0U, // SLL64_32
+ 0U, // SLL64_64
+ 0U, // SLLI_B
+ 0U, // SLLI_D
+ 0U, // SLLI_H
+ 0U, // SLLI_W
+ 0U, // SLLV
+ 0U, // SLLV_MM
+ 0U, // SLL_B
+ 0U, // SLL_D
+ 0U, // SLL_H
+ 1U, // SLL_MM
+ 0U, // SLL_W
+ 0U, // SLT
+ 0U, // SLT64
+ 0U, // SLT_MM
+ 0U, // SLTi
+ 0U, // SLTi64
+ 0U, // SLTi_MM
+ 0U, // SLTiu
+ 0U, // SLTiu64
+ 0U, // SLTiu_MM
+ 0U, // SLTu
+ 0U, // SLTu64
+ 0U, // SLTu_MM
+ 0U, // SNE
+ 0U, // SNEi
+ 0U, // SNZ_B_PSEUDO
+ 0U, // SNZ_D_PSEUDO
+ 0U, // SNZ_H_PSEUDO
+ 0U, // SNZ_V_PSEUDO
+ 0U, // SNZ_W_PSEUDO
+ 8U, // SPLATI_B
+ 8U, // SPLATI_D
+ 8U, // SPLATI_H
+ 8U, // SPLATI_W
+ 8U, // SPLAT_B
+ 8U, // SPLAT_D
+ 8U, // SPLAT_H
+ 8U, // SPLAT_W
+ 1U, // SRA
+ 0U, // SRAI_B
+ 0U, // SRAI_D
+ 0U, // SRAI_H
+ 0U, // SRAI_W
+ 1U, // SRARI_B
+ 1U, // SRARI_D
+ 0U, // SRARI_H
+ 1U, // SRARI_W
+ 0U, // SRAR_B
+ 0U, // SRAR_D
+ 0U, // SRAR_H
+ 0U, // SRAR_W
+ 0U, // SRAV
+ 0U, // SRAV_MM
+ 0U, // SRA_B
+ 0U, // SRA_D
+ 0U, // SRA_H
+ 1U, // SRA_MM
+ 0U, // SRA_W
+ 1U, // SRL
+ 0U, // SRL16_MM
+ 0U, // SRLI_B
+ 0U, // SRLI_D
+ 0U, // SRLI_H
+ 0U, // SRLI_W
+ 1U, // SRLRI_B
+ 1U, // SRLRI_D
+ 0U, // SRLRI_H
+ 1U, // SRLRI_W
+ 0U, // SRLR_B
+ 0U, // SRLR_D
+ 0U, // SRLR_H
+ 0U, // SRLR_W
+ 0U, // SRLV
+ 0U, // SRLV_MM
+ 0U, // SRL_B
+ 0U, // SRL_D
+ 0U, // SRL_H
+ 1U, // SRL_MM
+ 0U, // SRL_W
+ 0U, // SSNOP
+ 0U, // SSNOP_MM
+ 0U, // STORE_ACC128
+ 0U, // STORE_ACC64
+ 0U, // STORE_ACC64DSP
+ 0U, // STORE_CCOND_DSP
+ 0U, // ST_B
+ 0U, // ST_D
+ 0U, // ST_H
+ 0U, // ST_W
+ 0U, // SUB
+ 0U, // SUBQH_PH
+ 0U, // SUBQH_R_PH
+ 0U, // SUBQH_R_W
+ 0U, // SUBQH_W
+ 0U, // SUBQ_PH
+ 0U, // SUBQ_S_PH
+ 0U, // SUBQ_S_W
+ 0U, // SUBSUS_U_B
+ 0U, // SUBSUS_U_D
+ 0U, // SUBSUS_U_H
+ 0U, // SUBSUS_U_W
+ 0U, // SUBSUU_S_B
+ 0U, // SUBSUU_S_D
+ 0U, // SUBSUU_S_H
+ 0U, // SUBSUU_S_W
+ 0U, // SUBS_S_B
+ 0U, // SUBS_S_D
+ 0U, // SUBS_S_H
+ 0U, // SUBS_S_W
+ 0U, // SUBS_U_B
+ 0U, // SUBS_U_D
+ 0U, // SUBS_U_H
+ 0U, // SUBS_U_W
+ 0U, // SUBU16_MM
+ 0U, // SUBUH_QB
+ 0U, // SUBUH_R_QB
+ 0U, // SUBU_PH
+ 0U, // SUBU_QB
+ 0U, // SUBU_S_PH
+ 0U, // SUBU_S_QB
+ 0U, // SUBVI_B
+ 0U, // SUBVI_D
+ 0U, // SUBVI_H
+ 0U, // SUBVI_W
+ 0U, // SUBV_B
+ 0U, // SUBV_D
+ 0U, // SUBV_H
+ 0U, // SUBV_W
+ 0U, // SUB_MM
+ 0U, // SUBu
+ 0U, // SUBu_MM
+ 0U, // SUXC1
+ 0U, // SUXC164
+ 0U, // SUXC1_MM
+ 0U, // SW
+ 0U, // SW16_MM
+ 0U, // SW64
+ 0U, // SWC1
+ 0U, // SWC1_MM
+ 0U, // SWC2
+ 0U, // SWC2_R6
+ 0U, // SWC3
+ 0U, // SWL
+ 0U, // SWL64
+ 0U, // SWL_MM
+ 0U, // SWM16_MM
+ 0U, // SWM32_MM
+ 0U, // SWM_MM
+ 0U, // SWP_MM
+ 0U, // SWR
+ 0U, // SWR64
+ 0U, // SWR_MM
+ 0U, // SWSP_MM
+ 0U, // SWXC1
+ 0U, // SWXC1_MM
+ 0U, // SW_MM
+ 0U, // SYNC
+ 0U, // SYNCI
+ 0U, // SYNC_MM
+ 0U, // SYSCALL
+ 0U, // SYSCALL_MM
+ 0U, // SZ_B_PSEUDO
+ 0U, // SZ_D_PSEUDO
+ 0U, // SZ_H_PSEUDO
+ 0U, // SZ_V_PSEUDO
+ 0U, // SZ_W_PSEUDO
+ 0U, // Save16
+ 0U, // SaveX16
+ 0U, // SbRxRyOffMemX16
+ 0U, // SebRx16
+ 0U, // SehRx16
+ 0U, // SelBeqZ
+ 0U, // SelBneZ
+ 0U, // SelTBteqZCmp
+ 0U, // SelTBteqZCmpi
+ 0U, // SelTBteqZSlt
+ 0U, // SelTBteqZSlti
+ 0U, // SelTBteqZSltiu
+ 0U, // SelTBteqZSltu
+ 0U, // SelTBtneZCmp
+ 0U, // SelTBtneZCmpi
+ 0U, // SelTBtneZSlt
+ 0U, // SelTBtneZSlti
+ 0U, // SelTBtneZSltiu
+ 0U, // SelTBtneZSltu
+ 0U, // ShRxRyOffMemX16
+ 1U, // SllX16
+ 0U, // SllvRxRy16
+ 0U, // SltCCRxRy16
+ 0U, // SltRxRy16
+ 0U, // SltiCCRxImmX16
+ 0U, // SltiRxImm16
+ 0U, // SltiRxImmX16
+ 0U, // SltiuCCRxImmX16
+ 0U, // SltiuRxImm16
+ 0U, // SltiuRxImmX16
+ 0U, // SltuCCRxRy16
+ 0U, // SltuRxRy16
+ 0U, // SltuRxRyRz16
+ 1U, // SraX16
+ 0U, // SravRxRy16
+ 1U, // SrlX16
+ 0U, // SrlvRxRy16
+ 0U, // SubuRxRyRz16
+ 0U, // SwRxRyOffMemX16
+ 0U, // SwRxSpImmX16
+ 0U, // TAILCALL
+ 0U, // TAILCALL64_R
+ 0U, // TAILCALL_R
+ 1U, // TEQ
+ 0U, // TEQI
+ 0U, // TEQI_MM
+ 1U, // TEQ_MM
+ 1U, // TGE
+ 0U, // TGEI
+ 0U, // TGEIU
+ 0U, // TGEIU_MM
+ 0U, // TGEI_MM
+ 1U, // TGEU
+ 1U, // TGEU_MM
+ 1U, // TGE_MM
+ 0U, // TLBP
+ 0U, // TLBP_MM
+ 0U, // TLBR
+ 0U, // TLBR_MM
+ 0U, // TLBWI
+ 0U, // TLBWI_MM
+ 0U, // TLBWR
+ 0U, // TLBWR_MM
+ 1U, // TLT
+ 0U, // TLTI
+ 0U, // TLTIU_MM
+ 0U, // TLTI_MM
+ 1U, // TLTU
+ 1U, // TLTU_MM
+ 1U, // TLT_MM
+ 1U, // TNE
+ 0U, // TNEI
+ 0U, // TNEI_MM
+ 1U, // TNE_MM
+ 0U, // TRAP
+ 0U, // TRUNC_L_D64
+ 0U, // TRUNC_L_S
+ 0U, // TRUNC_W_D32
+ 0U, // TRUNC_W_D64
+ 0U, // TRUNC_W_MM
+ 0U, // TRUNC_W_S
+ 0U, // TRUNC_W_S_MM
+ 0U, // TTLTIU
+ 0U, // UDIV
+ 0U, // UDIV_MM
+ 0U, // V3MULU
+ 0U, // VMM0
+ 0U, // VMULU
+ 2U, // VSHF_B
+ 2U, // VSHF_D
+ 2U, // VSHF_H
+ 2U, // VSHF_W
+ 0U, // WAIT
+ 0U, // WAIT_MM
+ 0U, // WRDSP
+ 0U, // WSBH
+ 0U, // WSBH_MM
+ 0U, // XOR
+ 0U, // XOR16_MM
+ 0U, // XOR64
+ 0U, // XORI_B
+ 0U, // XOR_MM
+ 0U, // XOR_V
+ 0U, // XOR_V_D_PSEUDO
+ 0U, // XOR_V_H_PSEUDO
+ 0U, // XOR_V_W_PSEUDO
+ 1U, // XORi
+ 1U, // XORi64
+ 1U, // XORi_MM
+ 0U, // XorRxRxRy16
+ 0U
+ };
+
+#ifndef CAPSTONE_DIET
+ static const char AsmStrs[] = {
+ /* 0 */ 'j', 'a', 'l', 'r', 'c', 32, 9, 0,
+ /* 8 */ 'd', 'm', 'f', 'c', '0', 9, 0,
+ /* 15 */ 'd', 'm', 't', 'c', '0', 9, 0,
+ /* 22 */ 'v', 'm', 'm', '0', 9, 0,
+ /* 28 */ 'm', 't', 'm', '0', 9, 0,
+ /* 34 */ 'm', 't', 'p', '0', 9, 0,
+ /* 40 */ 'b', 'b', 'i', 't', '0', 9, 0,
+ /* 47 */ 'l', 'd', 'c', '1', 9, 0,
+ /* 53 */ 's', 'd', 'c', '1', 9, 0,
+ /* 59 */ 'c', 'f', 'c', '1', 9, 0,
+ /* 65 */ 'd', 'm', 'f', 'c', '1', 9, 0,
+ /* 72 */ 'm', 'f', 'h', 'c', '1', 9, 0,
+ /* 79 */ 'm', 't', 'h', 'c', '1', 9, 0,
+ /* 86 */ 'c', 't', 'c', '1', 9, 0,
+ /* 92 */ 'd', 'm', 't', 'c', '1', 9, 0,
+ /* 99 */ 'l', 'w', 'c', '1', 9, 0,
+ /* 105 */ 's', 'w', 'c', '1', 9, 0,
+ /* 111 */ 'l', 'd', 'x', 'c', '1', 9, 0,
+ /* 118 */ 's', 'd', 'x', 'c', '1', 9, 0,
+ /* 125 */ 'l', 'u', 'x', 'c', '1', 9, 0,
+ /* 132 */ 's', 'u', 'x', 'c', '1', 9, 0,
+ /* 139 */ 'l', 'w', 'x', 'c', '1', 9, 0,
+ /* 146 */ 's', 'w', 'x', 'c', '1', 9, 0,
+ /* 153 */ 'm', 't', 'm', '1', 9, 0,
+ /* 159 */ 'm', 't', 'p', '1', 9, 0,
+ /* 165 */ 'b', 'b', 'i', 't', '1', 9, 0,
+ /* 172 */ 'b', 'b', 'i', 't', '0', '3', '2', 9, 0,
+ /* 181 */ 'b', 'b', 'i', 't', '1', '3', '2', 9, 0,
+ /* 190 */ 'd', 's', 'r', 'a', '3', '2', 9, 0,
+ /* 198 */ 'b', 'p', 'o', 's', 'g', 'e', '3', '2', 9, 0,
+ /* 208 */ 'd', 's', 'l', 'l', '3', '2', 9, 0,
+ /* 216 */ 'd', 's', 'r', 'l', '3', '2', 9, 0,
+ /* 224 */ 'l', 'w', 'm', '3', '2', 9, 0,
+ /* 231 */ 's', 'w', 'm', '3', '2', 9, 0,
+ /* 238 */ 'd', 'r', 'o', 't', 'r', '3', '2', 9, 0,
+ /* 247 */ 'l', 'd', 'c', '2', 9, 0,
+ /* 253 */ 's', 'd', 'c', '2', 9, 0,
+ /* 259 */ 'd', 'm', 'f', 'c', '2', 9, 0,
+ /* 266 */ 'd', 'm', 't', 'c', '2', 9, 0,
+ /* 273 */ 'l', 'w', 'c', '2', 9, 0,
+ /* 279 */ 's', 'w', 'c', '2', 9, 0,
+ /* 285 */ 'm', 't', 'm', '2', 9, 0,
+ /* 291 */ 'm', 't', 'p', '2', 9, 0,
+ /* 297 */ 'a', 'd', 'd', 'i', 'u', 'r', '2', 9, 0,
+ /* 306 */ 'l', 'd', 'c', '3', 9, 0,
+ /* 312 */ 's', 'd', 'c', '3', 9, 0,
+ /* 318 */ 'l', 'w', 'c', '3', 9, 0,
+ /* 324 */ 's', 'w', 'c', '3', 9, 0,
+ /* 330 */ 'a', 'd', 'd', 'i', 'u', 's', '5', 9, 0,
+ /* 339 */ 's', 'b', '1', '6', 9, 0,
+ /* 345 */ 'a', 'n', 'd', '1', '6', 9, 0,
+ /* 352 */ 's', 'h', '1', '6', 9, 0,
+ /* 358 */ 'a', 'n', 'd', 'i', '1', '6', 9, 0,
+ /* 366 */ 'l', 'i', '1', '6', 9, 0,
+ /* 372 */ 'b', 'r', 'e', 'a', 'k', '1', '6', 9, 0,
+ /* 381 */ 's', 'l', 'l', '1', '6', 9, 0,
+ /* 388 */ 's', 'r', 'l', '1', '6', 9, 0,
+ /* 395 */ 'l', 'w', 'm', '1', '6', 9, 0,
+ /* 402 */ 's', 'w', 'm', '1', '6', 9, 0,
+ /* 409 */ 's', 'd', 'b', 'b', 'p', '1', '6', 9, 0,
+ /* 418 */ 'j', 'r', '1', '6', 9, 0,
+ /* 424 */ 'x', 'o', 'r', '1', '6', 9, 0,
+ /* 431 */ 'j', 'a', 'l', 'r', 's', '1', '6', 9, 0,
+ /* 440 */ 'n', 'o', 't', '1', '6', 9, 0,
+ /* 447 */ 'l', 'b', 'u', '1', '6', 9, 0,
+ /* 454 */ 's', 'u', 'b', 'u', '1', '6', 9, 0,
+ /* 462 */ 'a', 'd', 'd', 'u', '1', '6', 9, 0,
+ /* 470 */ 'l', 'h', 'u', '1', '6', 9, 0,
+ /* 477 */ 'l', 'w', '1', '6', 9, 0,
+ /* 483 */ 's', 'w', '1', '6', 9, 0,
+ /* 489 */ 'b', 'n', 'e', 'z', '1', '6', 9, 0,
+ /* 497 */ 'b', 'e', 'q', 'z', '1', '6', 9, 0,
+ /* 505 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 'a', 9, 0,
+ /* 521 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 'a', 9, 0,
+ /* 538 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 'a', 9, 0,
+ /* 554 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 'a', 9, 0,
+ /* 571 */ 'd', 's', 'r', 'a', 9, 0,
+ /* 577 */ 'd', 'l', 's', 'a', 9, 0,
+ /* 583 */ 'c', 'f', 'c', 'm', 's', 'a', 9, 0,
+ /* 591 */ 'c', 't', 'c', 'm', 's', 'a', 9, 0,
+ /* 599 */ 'a', 'd', 'd', '_', 'a', '.', 'b', 9, 0,
+ /* 608 */ 'm', 'i', 'n', '_', 'a', '.', 'b', 9, 0,
+ /* 617 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'b', 9, 0,
+ /* 627 */ 'm', 'a', 'x', '_', 'a', '.', 'b', 9, 0,
+ /* 636 */ 's', 'r', 'a', '.', 'b', 9, 0,
+ /* 643 */ 'n', 'l', 'o', 'c', '.', 'b', 9, 0,
+ /* 651 */ 'n', 'l', 'z', 'c', '.', 'b', 9, 0,
+ /* 659 */ 's', 'l', 'd', '.', 'b', 9, 0,
+ /* 666 */ 'p', 'c', 'k', 'o', 'd', '.', 'b', 9, 0,
+ /* 675 */ 'i', 'l', 'v', 'o', 'd', '.', 'b', 9, 0,
+ /* 684 */ 'i', 'n', 's', 'v', 'e', '.', 'b', 9, 0,
+ /* 693 */ 'v', 's', 'h', 'f', '.', 'b', 9, 0,
+ /* 701 */ 'b', 'n', 'e', 'g', '.', 'b', 9, 0,
+ /* 709 */ 's', 'r', 'a', 'i', '.', 'b', 9, 0,
+ /* 717 */ 's', 'l', 'd', 'i', '.', 'b', 9, 0,
+ /* 725 */ 'a', 'n', 'd', 'i', '.', 'b', 9, 0,
+ /* 733 */ 'b', 'n', 'e', 'g', 'i', '.', 'b', 9, 0,
+ /* 742 */ 'b', 's', 'e', 'l', 'i', '.', 'b', 9, 0,
+ /* 751 */ 's', 'l', 'l', 'i', '.', 'b', 9, 0,
+ /* 759 */ 's', 'r', 'l', 'i', '.', 'b', 9, 0,
+ /* 767 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'b', 9, 0,
+ /* 777 */ 'c', 'e', 'q', 'i', '.', 'b', 9, 0,
+ /* 785 */ 's', 'r', 'a', 'r', 'i', '.', 'b', 9, 0,
+ /* 794 */ 'b', 'c', 'l', 'r', 'i', '.', 'b', 9, 0,
+ /* 803 */ 's', 'r', 'l', 'r', 'i', '.', 'b', 9, 0,
+ /* 812 */ 'n', 'o', 'r', 'i', '.', 'b', 9, 0,
+ /* 820 */ 'x', 'o', 'r', 'i', '.', 'b', 9, 0,
+ /* 828 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'b', 9, 0,
+ /* 838 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'b', 9, 0,
+ /* 848 */ 'b', 's', 'e', 't', 'i', '.', 'b', 9, 0,
+ /* 857 */ 's', 'u', 'b', 'v', 'i', '.', 'b', 9, 0,
+ /* 866 */ 'a', 'd', 'd', 'v', 'i', '.', 'b', 9, 0,
+ /* 875 */ 'b', 'm', 'z', 'i', '.', 'b', 9, 0,
+ /* 883 */ 'b', 'm', 'n', 'z', 'i', '.', 'b', 9, 0,
+ /* 892 */ 'f', 'i', 'l', 'l', '.', 'b', 9, 0,
+ /* 900 */ 's', 'l', 'l', '.', 'b', 9, 0,
+ /* 907 */ 's', 'r', 'l', '.', 'b', 9, 0,
+ /* 914 */ 'b', 'i', 'n', 's', 'l', '.', 'b', 9, 0,
+ /* 923 */ 'i', 'l', 'v', 'l', '.', 'b', 9, 0,
+ /* 931 */ 'c', 'e', 'q', '.', 'b', 9, 0,
+ /* 938 */ 's', 'r', 'a', 'r', '.', 'b', 9, 0,
+ /* 946 */ 'b', 'c', 'l', 'r', '.', 'b', 9, 0,
+ /* 954 */ 's', 'r', 'l', 'r', '.', 'b', 9, 0,
+ /* 962 */ 'b', 'i', 'n', 's', 'r', '.', 'b', 9, 0,
+ /* 971 */ 'i', 'l', 'v', 'r', '.', 'b', 9, 0,
+ /* 979 */ 'a', 's', 'u', 'b', '_', 's', '.', 'b', 9, 0,
+ /* 989 */ 'm', 'o', 'd', '_', 's', '.', 'b', 9, 0,
+ /* 998 */ 'c', 'l', 'e', '_', 's', '.', 'b', 9, 0,
+ /* 1007 */ 'a', 'v', 'e', '_', 's', '.', 'b', 9, 0,
+ /* 1016 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'b', 9, 0,
+ /* 1026 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'b', 9, 0,
+ /* 1036 */ 'c', 'l', 't', 'i', '_', 's', '.', 'b', 9, 0,
+ /* 1046 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'b', 9, 0,
+ /* 1056 */ 'm', 'i', 'n', '_', 's', '.', 'b', 9, 0,
+ /* 1065 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'b', 9, 0,
+ /* 1075 */ 's', 'u', 'b', 's', '_', 's', '.', 'b', 9, 0,
+ /* 1085 */ 'a', 'd', 'd', 's', '_', 's', '.', 'b', 9, 0,
+ /* 1095 */ 's', 'a', 't', '_', 's', '.', 'b', 9, 0,
+ /* 1104 */ 'c', 'l', 't', '_', 's', '.', 'b', 9, 0,
+ /* 1113 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'b', 9, 0,
+ /* 1125 */ 'd', 'i', 'v', '_', 's', '.', 'b', 9, 0,
+ /* 1134 */ 'm', 'a', 'x', '_', 's', '.', 'b', 9, 0,
+ /* 1143 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'b', 9, 0,
+ /* 1153 */ 's', 'p', 'l', 'a', 't', '.', 'b', 9, 0,
+ /* 1162 */ 'b', 's', 'e', 't', '.', 'b', 9, 0,
+ /* 1170 */ 'p', 'c', 'n', 't', '.', 'b', 9, 0,
+ /* 1178 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'b', 9, 0,
+ /* 1188 */ 's', 't', '.', 'b', 9, 0,
+ /* 1194 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'b', 9, 0,
+ /* 1204 */ 'm', 'o', 'd', '_', 'u', '.', 'b', 9, 0,
+ /* 1213 */ 'c', 'l', 'e', '_', 'u', '.', 'b', 9, 0,
+ /* 1222 */ 'a', 'v', 'e', '_', 'u', '.', 'b', 9, 0,
+ /* 1231 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'b', 9, 0,
+ /* 1241 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'b', 9, 0,
+ /* 1251 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'b', 9, 0,
+ /* 1261 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'b', 9, 0,
+ /* 1271 */ 'm', 'i', 'n', '_', 'u', '.', 'b', 9, 0,
+ /* 1280 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'b', 9, 0,
+ /* 1290 */ 's', 'u', 'b', 's', '_', 'u', '.', 'b', 9, 0,
+ /* 1300 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'b', 9, 0,
+ /* 1310 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'b', 9, 0,
+ /* 1322 */ 's', 'a', 't', '_', 'u', '.', 'b', 9, 0,
+ /* 1331 */ 'c', 'l', 't', '_', 'u', '.', 'b', 9, 0,
+ /* 1340 */ 'd', 'i', 'v', '_', 'u', '.', 'b', 9, 0,
+ /* 1349 */ 'm', 'a', 'x', '_', 'u', '.', 'b', 9, 0,
+ /* 1358 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'b', 9, 0,
+ /* 1368 */ 'm', 's', 'u', 'b', 'v', '.', 'b', 9, 0,
+ /* 1377 */ 'm', 'a', 'd', 'd', 'v', '.', 'b', 9, 0,
+ /* 1386 */ 'p', 'c', 'k', 'e', 'v', '.', 'b', 9, 0,
+ /* 1395 */ 'i', 'l', 'v', 'e', 'v', '.', 'b', 9, 0,
+ /* 1404 */ 'm', 'u', 'l', 'v', '.', 'b', 9, 0,
+ /* 1412 */ 'b', 'z', '.', 'b', 9, 0,
+ /* 1418 */ 'b', 'n', 'z', '.', 'b', 9, 0,
+ /* 1425 */ 's', 'e', 'b', 9, 0,
+ /* 1430 */ 'j', 'r', '.', 'h', 'b', 9, 0,
+ /* 1437 */ 'j', 'a', 'l', 'r', '.', 'h', 'b', 9, 0,
+ /* 1446 */ 'l', 'b', 9, 0,
+ /* 1450 */ 's', 'h', 'r', 'a', '.', 'q', 'b', 9, 0,
+ /* 1459 */ 'c', 'm', 'p', 'g', 'd', 'u', '.', 'l', 'e', '.', 'q', 'b', 9, 0,
+ /* 1473 */ 'c', 'm', 'p', 'g', 'u', '.', 'l', 'e', '.', 'q', 'b', 9, 0,
+ /* 1486 */ 'c', 'm', 'p', 'u', '.', 'l', 'e', '.', 'q', 'b', 9, 0,
+ /* 1498 */ 's', 'u', 'b', 'u', 'h', '.', 'q', 'b', 9, 0,
+ /* 1508 */ 'a', 'd', 'd', 'u', 'h', '.', 'q', 'b', 9, 0,
+ /* 1518 */ 'p', 'i', 'c', 'k', '.', 'q', 'b', 9, 0,
+ /* 1527 */ 's', 'h', 'l', 'l', '.', 'q', 'b', 9, 0,
+ /* 1536 */ 'r', 'e', 'p', 'l', '.', 'q', 'b', 9, 0,
+ /* 1545 */ 's', 'h', 'r', 'l', '.', 'q', 'b', 9, 0,
+ /* 1554 */ 'c', 'm', 'p', 'g', 'd', 'u', '.', 'e', 'q', '.', 'q', 'b', 9, 0,
+ /* 1568 */ 'c', 'm', 'p', 'g', 'u', '.', 'e', 'q', '.', 'q', 'b', 9, 0,
+ /* 1581 */ 'c', 'm', 'p', 'u', '.', 'e', 'q', '.', 'q', 'b', 9, 0,
+ /* 1593 */ 's', 'h', 'r', 'a', '_', 'r', '.', 'q', 'b', 9, 0,
+ /* 1604 */ 's', 'u', 'b', 'u', 'h', '_', 'r', '.', 'q', 'b', 9, 0,
+ /* 1616 */ 'a', 'd', 'd', 'u', 'h', '_', 'r', '.', 'q', 'b', 9, 0,
+ /* 1628 */ 's', 'h', 'r', 'a', 'v', '_', 'r', '.', 'q', 'b', 9, 0,
+ /* 1640 */ 'a', 'b', 's', 'q', '_', 's', '.', 'q', 'b', 9, 0,
+ /* 1651 */ 's', 'u', 'b', 'u', '_', 's', '.', 'q', 'b', 9, 0,
+ /* 1662 */ 'a', 'd', 'd', 'u', '_', 's', '.', 'q', 'b', 9, 0,
+ /* 1673 */ 'c', 'm', 'p', 'g', 'd', 'u', '.', 'l', 't', '.', 'q', 'b', 9, 0,
+ /* 1687 */ 'c', 'm', 'p', 'g', 'u', '.', 'l', 't', '.', 'q', 'b', 9, 0,
+ /* 1700 */ 'c', 'm', 'p', 'u', '.', 'l', 't', '.', 'q', 'b', 9, 0,
+ /* 1712 */ 's', 'u', 'b', 'u', '.', 'q', 'b', 9, 0,
+ /* 1721 */ 'a', 'd', 'd', 'u', '.', 'q', 'b', 9, 0,
+ /* 1730 */ 's', 'h', 'r', 'a', 'v', '.', 'q', 'b', 9, 0,
+ /* 1740 */ 's', 'h', 'l', 'l', 'v', '.', 'q', 'b', 9, 0,
+ /* 1750 */ 'r', 'e', 'p', 'l', 'v', '.', 'q', 'b', 9, 0,
+ /* 1760 */ 's', 'h', 'r', 'l', 'v', '.', 'q', 'b', 9, 0,
+ /* 1770 */ 'r', 'a', 'd', 'd', 'u', '.', 'w', '.', 'q', 'b', 9, 0,
+ /* 1782 */ 's', 'b', 9, 0,
+ /* 1786 */ 'm', 'o', 'd', 's', 'u', 'b', 9, 0,
+ /* 1794 */ 'm', 's', 'u', 'b', 9, 0,
+ /* 1800 */ 'b', 'c', 9, 0,
+ /* 1804 */ 'b', 'g', 'e', 'c', 9, 0,
+ /* 1810 */ 'b', 'n', 'e', 'c', 9, 0,
+ /* 1816 */ 'j', 'i', 'c', 9, 0,
+ /* 1821 */ 'b', 'a', 'l', 'c', 9, 0,
+ /* 1827 */ 'j', 'i', 'a', 'l', 'c', 9, 0,
+ /* 1834 */ 'b', 'g', 'e', 'z', 'a', 'l', 'c', 9, 0,
+ /* 1843 */ 'b', 'l', 'e', 'z', 'a', 'l', 'c', 9, 0,
+ /* 1852 */ 'b', 'n', 'e', 'z', 'a', 'l', 'c', 9, 0,
+ /* 1861 */ 'b', 'e', 'q', 'z', 'a', 'l', 'c', 9, 0,
+ /* 1870 */ 'b', 'g', 't', 'z', 'a', 'l', 'c', 9, 0,
+ /* 1879 */ 'b', 'l', 't', 'z', 'a', 'l', 'c', 9, 0,
+ /* 1888 */ 'l', 'd', 'p', 'c', 9, 0,
+ /* 1894 */ 'a', 'u', 'i', 'p', 'c', 9, 0,
+ /* 1901 */ 'a', 'l', 'u', 'i', 'p', 'c', 9, 0,
+ /* 1909 */ 'a', 'd', 'd', 'i', 'u', 'p', 'c', 9, 0,
+ /* 1918 */ 'l', 'w', 'u', 'p', 'c', 9, 0,
+ /* 1925 */ 'l', 'w', 'p', 'c', 9, 0,
+ /* 1931 */ 'b', 'e', 'q', 'c', 9, 0,
+ /* 1937 */ 'j', 'r', 'c', 9, 0,
+ /* 1942 */ 'a', 'd', 'd', 's', 'c', 9, 0,
+ /* 1949 */ 'b', 'l', 't', 'c', 9, 0,
+ /* 1955 */ 'b', 'g', 'e', 'u', 'c', 9, 0,
+ /* 1962 */ 'b', 'l', 't', 'u', 'c', 9, 0,
+ /* 1969 */ 'b', 'n', 'v', 'c', 9, 0,
+ /* 1975 */ 'b', 'o', 'v', 'c', 9, 0,
+ /* 1981 */ 'a', 'd', 'd', 'w', 'c', 9, 0,
+ /* 1988 */ 'b', 'g', 'e', 'z', 'c', 9, 0,
+ /* 1995 */ 'b', 'l', 'e', 'z', 'c', 9, 0,
+ /* 2002 */ 'b', 'n', 'e', 'z', 'c', 9, 0,
+ /* 2009 */ 'b', 'e', 'q', 'z', 'c', 9, 0,
+ /* 2016 */ 'b', 'g', 't', 'z', 'c', 9, 0,
+ /* 2023 */ 'b', 'l', 't', 'z', 'c', 9, 0,
+ /* 2030 */ 'f', 'l', 'o', 'g', '2', '.', 'd', 9, 0,
+ /* 2039 */ 'f', 'e', 'x', 'p', '2', '.', 'd', 9, 0,
+ /* 2048 */ 'a', 'd', 'd', '_', 'a', '.', 'd', 9, 0,
+ /* 2057 */ 'f', 'm', 'i', 'n', '_', 'a', '.', 'd', 9, 0,
+ /* 2067 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'd', 9, 0,
+ /* 2077 */ 'f', 'm', 'a', 'x', '_', 'a', '.', 'd', 9, 0,
+ /* 2087 */ 'm', 'i', 'n', 'a', '.', 'd', 9, 0,
+ /* 2095 */ 's', 'r', 'a', '.', 'd', 9, 0,
+ /* 2102 */ 'm', 'a', 'x', 'a', '.', 'd', 9, 0,
+ /* 2110 */ 'f', 's', 'u', 'b', '.', 'd', 9, 0,
+ /* 2118 */ 'f', 'm', 's', 'u', 'b', '.', 'd', 9, 0,
+ /* 2127 */ 'n', 'm', 's', 'u', 'b', '.', 'd', 9, 0,
+ /* 2136 */ 'n', 'l', 'o', 'c', '.', 'd', 9, 0,
+ /* 2144 */ 'n', 'l', 'z', 'c', '.', 'd', 9, 0,
+ /* 2152 */ 'f', 'a', 'd', 'd', '.', 'd', 9, 0,
+ /* 2160 */ 'f', 'm', 'a', 'd', 'd', '.', 'd', 9, 0,
+ /* 2169 */ 'n', 'm', 'a', 'd', 'd', '.', 'd', 9, 0,
+ /* 2178 */ 's', 'l', 'd', '.', 'd', 9, 0,
+ /* 2185 */ 'p', 'c', 'k', 'o', 'd', '.', 'd', 9, 0,
+ /* 2194 */ 'i', 'l', 'v', 'o', 'd', '.', 'd', 9, 0,
+ /* 2203 */ 'c', '.', 'n', 'g', 'e', '.', 'd', 9, 0,
+ /* 2212 */ 'c', '.', 'l', 'e', '.', 'd', 9, 0,
+ /* 2220 */ 'c', 'm', 'p', '.', 'l', 'e', '.', 'd', 9, 0,
+ /* 2230 */ 'f', 'c', 'l', 'e', '.', 'd', 9, 0,
+ /* 2238 */ 'c', '.', 'n', 'g', 'l', 'e', '.', 'd', 9, 0,
+ /* 2248 */ 'c', '.', 'o', 'l', 'e', '.', 'd', 9, 0,
+ /* 2257 */ 'c', 'm', 'p', '.', 's', 'l', 'e', '.', 'd', 9, 0,
+ /* 2268 */ 'f', 's', 'l', 'e', '.', 'd', 9, 0,
+ /* 2276 */ 'c', '.', 'u', 'l', 'e', '.', 'd', 9, 0,
+ /* 2285 */ 'c', 'm', 'p', '.', 'u', 'l', 'e', '.', 'd', 9, 0,
+ /* 2296 */ 'f', 'c', 'u', 'l', 'e', '.', 'd', 9, 0,
+ /* 2305 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 'e', '.', 'd', 9, 0,
+ /* 2317 */ 'f', 's', 'u', 'l', 'e', '.', 'd', 9, 0,
+ /* 2326 */ 'f', 'c', 'n', 'e', '.', 'd', 9, 0,
+ /* 2334 */ 'f', 's', 'n', 'e', '.', 'd', 9, 0,
+ /* 2342 */ 'f', 'c', 'u', 'n', 'e', '.', 'd', 9, 0,
+ /* 2351 */ 'f', 's', 'u', 'n', 'e', '.', 'd', 9, 0,
+ /* 2360 */ 'i', 'n', 's', 'v', 'e', '.', 'd', 9, 0,
+ /* 2369 */ 'c', '.', 'f', '.', 'd', 9, 0,
+ /* 2376 */ 'c', 'm', 'p', '.', 'a', 'f', '.', 'd', 9, 0,
+ /* 2386 */ 'f', 'c', 'a', 'f', '.', 'd', 9, 0,
+ /* 2394 */ 'c', 'm', 'p', '.', 's', 'a', 'f', '.', 'd', 9, 0,
+ /* 2405 */ 'f', 's', 'a', 'f', '.', 'd', 9, 0,
+ /* 2413 */ 'm', 's', 'u', 'b', 'f', '.', 'd', 9, 0,
+ /* 2422 */ 'm', 'a', 'd', 'd', 'f', '.', 'd', 9, 0,
+ /* 2431 */ 'v', 's', 'h', 'f', '.', 'd', 9, 0,
+ /* 2439 */ 'c', '.', 's', 'f', '.', 'd', 9, 0,
+ /* 2447 */ 'm', 'o', 'v', 'f', '.', 'd', 9, 0,
+ /* 2455 */ 'b', 'n', 'e', 'g', '.', 'd', 9, 0,
+ /* 2463 */ 's', 'r', 'a', 'i', '.', 'd', 9, 0,
+ /* 2471 */ 's', 'l', 'd', 'i', '.', 'd', 9, 0,
+ /* 2479 */ 'b', 'n', 'e', 'g', 'i', '.', 'd', 9, 0,
+ /* 2488 */ 's', 'l', 'l', 'i', '.', 'd', 9, 0,
+ /* 2496 */ 's', 'r', 'l', 'i', '.', 'd', 9, 0,
+ /* 2504 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'd', 9, 0,
+ /* 2514 */ 'c', 'e', 'q', 'i', '.', 'd', 9, 0,
+ /* 2522 */ 's', 'r', 'a', 'r', 'i', '.', 'd', 9, 0,
+ /* 2531 */ 'b', 'c', 'l', 'r', 'i', '.', 'd', 9, 0,
+ /* 2540 */ 's', 'r', 'l', 'r', 'i', '.', 'd', 9, 0,
+ /* 2549 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'd', 9, 0,
+ /* 2559 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'd', 9, 0,
+ /* 2569 */ 'b', 's', 'e', 't', 'i', '.', 'd', 9, 0,
+ /* 2578 */ 's', 'u', 'b', 'v', 'i', '.', 'd', 9, 0,
+ /* 2587 */ 'a', 'd', 'd', 'v', 'i', '.', 'd', 9, 0,
+ /* 2596 */ 't', 'r', 'u', 'n', 'c', '.', 'l', '.', 'd', 9, 0,
+ /* 2607 */ 'r', 'o', 'u', 'n', 'd', '.', 'l', '.', 'd', 9, 0,
+ /* 2618 */ 'c', 'e', 'i', 'l', '.', 'l', '.', 'd', 9, 0,
+ /* 2628 */ 'f', 'l', 'o', 'o', 'r', '.', 'l', '.', 'd', 9, 0,
+ /* 2639 */ 'c', 'v', 't', '.', 'l', '.', 'd', 9, 0,
+ /* 2648 */ 's', 'e', 'l', '.', 'd', 9, 0,
+ /* 2655 */ 'c', '.', 'n', 'g', 'l', '.', 'd', 9, 0,
+ /* 2664 */ 'f', 'i', 'l', 'l', '.', 'd', 9, 0,
+ /* 2672 */ 's', 'l', 'l', '.', 'd', 9, 0,
+ /* 2679 */ 'f', 'e', 'x', 'u', 'p', 'l', '.', 'd', 9, 0,
+ /* 2689 */ 'f', 'f', 'q', 'l', '.', 'd', 9, 0,
+ /* 2697 */ 's', 'r', 'l', '.', 'd', 9, 0,
+ /* 2704 */ 'b', 'i', 'n', 's', 'l', '.', 'd', 9, 0,
+ /* 2713 */ 'f', 'm', 'u', 'l', '.', 'd', 9, 0,
+ /* 2721 */ 'i', 'l', 'v', 'l', '.', 'd', 9, 0,
+ /* 2729 */ 'f', 'm', 'i', 'n', '.', 'd', 9, 0,
+ /* 2737 */ 'c', '.', 'u', 'n', '.', 'd', 9, 0,
+ /* 2745 */ 'c', 'm', 'p', '.', 'u', 'n', '.', 'd', 9, 0,
+ /* 2755 */ 'f', 'c', 'u', 'n', '.', 'd', 9, 0,
+ /* 2763 */ 'c', 'm', 'p', '.', 's', 'u', 'n', '.', 'd', 9, 0,
+ /* 2774 */ 'f', 's', 'u', 'n', '.', 'd', 9, 0,
+ /* 2782 */ 'm', 'o', 'v', 'n', '.', 'd', 9, 0,
+ /* 2790 */ 'f', 'r', 'c', 'p', '.', 'd', 9, 0,
+ /* 2798 */ 'c', '.', 'e', 'q', '.', 'd', 9, 0,
+ /* 2806 */ 'c', 'm', 'p', '.', 'e', 'q', '.', 'd', 9, 0,
+ /* 2816 */ 'f', 'c', 'e', 'q', '.', 'd', 9, 0,
+ /* 2824 */ 'c', '.', 's', 'e', 'q', '.', 'd', 9, 0,
+ /* 2833 */ 'c', 'm', 'p', '.', 's', 'e', 'q', '.', 'd', 9, 0,
+ /* 2844 */ 'f', 's', 'e', 'q', '.', 'd', 9, 0,
+ /* 2852 */ 'c', '.', 'u', 'e', 'q', '.', 'd', 9, 0,
+ /* 2861 */ 'c', 'm', 'p', '.', 'u', 'e', 'q', '.', 'd', 9, 0,
+ /* 2872 */ 'f', 'c', 'u', 'e', 'q', '.', 'd', 9, 0,
+ /* 2881 */ 'c', 'm', 'p', '.', 's', 'u', 'e', 'q', '.', 'd', 9, 0,
+ /* 2893 */ 'f', 's', 'u', 'e', 'q', '.', 'd', 9, 0,
+ /* 2902 */ 's', 'r', 'a', 'r', '.', 'd', 9, 0,
+ /* 2910 */ 'b', 'c', 'l', 'r', '.', 'd', 9, 0,
+ /* 2918 */ 's', 'r', 'l', 'r', '.', 'd', 9, 0,
+ /* 2926 */ 'f', 'c', 'o', 'r', '.', 'd', 9, 0,
+ /* 2934 */ 'f', 's', 'o', 'r', '.', 'd', 9, 0,
+ /* 2942 */ 'f', 'e', 'x', 'u', 'p', 'r', '.', 'd', 9, 0,
+ /* 2952 */ 'f', 'f', 'q', 'r', '.', 'd', 9, 0,
+ /* 2960 */ 'b', 'i', 'n', 's', 'r', '.', 'd', 9, 0,
+ /* 2969 */ 'i', 'l', 'v', 'r', '.', 'd', 9, 0,
+ /* 2977 */ 'c', 'v', 't', '.', 's', '.', 'd', 9, 0,
+ /* 2986 */ 'a', 's', 'u', 'b', '_', 's', '.', 'd', 9, 0,
+ /* 2996 */ 'h', 's', 'u', 'b', '_', 's', '.', 'd', 9, 0,
+ /* 3006 */ 'd', 'p', 's', 'u', 'b', '_', 's', '.', 'd', 9, 0,
+ /* 3017 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 's', '.', 'd', 9, 0,
+ /* 3029 */ 'h', 'a', 'd', 'd', '_', 's', '.', 'd', 9, 0,
+ /* 3039 */ 'd', 'p', 'a', 'd', 'd', '_', 's', '.', 'd', 9, 0,
+ /* 3050 */ 'm', 'o', 'd', '_', 's', '.', 'd', 9, 0,
+ /* 3059 */ 'c', 'l', 'e', '_', 's', '.', 'd', 9, 0,
+ /* 3068 */ 'a', 'v', 'e', '_', 's', '.', 'd', 9, 0,
+ /* 3077 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'd', 9, 0,
+ /* 3087 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'd', 9, 0,
+ /* 3097 */ 'c', 'l', 't', 'i', '_', 's', '.', 'd', 9, 0,
+ /* 3107 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'd', 9, 0,
+ /* 3117 */ 'm', 'i', 'n', '_', 's', '.', 'd', 9, 0,
+ /* 3126 */ 'd', 'o', 't', 'p', '_', 's', '.', 'd', 9, 0,
+ /* 3136 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'd', 9, 0,
+ /* 3146 */ 's', 'u', 'b', 's', '_', 's', '.', 'd', 9, 0,
+ /* 3156 */ 'a', 'd', 'd', 's', '_', 's', '.', 'd', 9, 0,
+ /* 3166 */ 's', 'a', 't', '_', 's', '.', 'd', 9, 0,
+ /* 3175 */ 'c', 'l', 't', '_', 's', '.', 'd', 9, 0,
+ /* 3184 */ 'f', 'f', 'i', 'n', 't', '_', 's', '.', 'd', 9, 0,
+ /* 3195 */ 'f', 't', 'i', 'n', 't', '_', 's', '.', 'd', 9, 0,
+ /* 3206 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'd', 9, 0,
+ /* 3218 */ 'd', 'i', 'v', '_', 's', '.', 'd', 9, 0,
+ /* 3227 */ 'm', 'a', 'x', '_', 's', '.', 'd', 9, 0,
+ /* 3236 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'd', 9, 0,
+ /* 3246 */ 'a', 'b', 's', '.', 'd', 9, 0,
+ /* 3253 */ 'f', 'c', 'l', 'a', 's', 's', '.', 'd', 9, 0,
+ /* 3263 */ 's', 'p', 'l', 'a', 't', '.', 'd', 9, 0,
+ /* 3272 */ 'b', 's', 'e', 't', '.', 'd', 9, 0,
+ /* 3280 */ 'c', '.', 'n', 'g', 't', '.', 'd', 9, 0,
+ /* 3289 */ 'c', '.', 'l', 't', '.', 'd', 9, 0,
+ /* 3297 */ 'c', 'm', 'p', '.', 'l', 't', '.', 'd', 9, 0,
+ /* 3307 */ 'f', 'c', 'l', 't', '.', 'd', 9, 0,
+ /* 3315 */ 'c', '.', 'o', 'l', 't', '.', 'd', 9, 0,
+ /* 3324 */ 'c', 'm', 'p', '.', 's', 'l', 't', '.', 'd', 9, 0,
+ /* 3335 */ 'f', 's', 'l', 't', '.', 'd', 9, 0,
+ /* 3343 */ 'c', '.', 'u', 'l', 't', '.', 'd', 9, 0,
+ /* 3352 */ 'c', 'm', 'p', '.', 'u', 'l', 't', '.', 'd', 9, 0,
+ /* 3363 */ 'f', 'c', 'u', 'l', 't', '.', 'd', 9, 0,
+ /* 3372 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 't', '.', 'd', 9, 0,
+ /* 3384 */ 'f', 's', 'u', 'l', 't', '.', 'd', 9, 0,
+ /* 3393 */ 'p', 'c', 'n', 't', '.', 'd', 9, 0,
+ /* 3401 */ 'f', 'r', 'i', 'n', 't', '.', 'd', 9, 0,
+ /* 3410 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'd', 9, 0,
+ /* 3420 */ 'f', 's', 'q', 'r', 't', '.', 'd', 9, 0,
+ /* 3429 */ 'f', 'r', 's', 'q', 'r', 't', '.', 'd', 9, 0,
+ /* 3439 */ 's', 't', '.', 'd', 9, 0,
+ /* 3445 */ 'm', 'o', 'v', 't', '.', 'd', 9, 0,
+ /* 3453 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'd', 9, 0,
+ /* 3463 */ 'h', 's', 'u', 'b', '_', 'u', '.', 'd', 9, 0,
+ /* 3473 */ 'd', 'p', 's', 'u', 'b', '_', 'u', '.', 'd', 9, 0,
+ /* 3484 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 'u', '.', 'd', 9, 0,
+ /* 3496 */ 'h', 'a', 'd', 'd', '_', 'u', '.', 'd', 9, 0,
+ /* 3506 */ 'd', 'p', 'a', 'd', 'd', '_', 'u', '.', 'd', 9, 0,
+ /* 3517 */ 'm', 'o', 'd', '_', 'u', '.', 'd', 9, 0,
+ /* 3526 */ 'c', 'l', 'e', '_', 'u', '.', 'd', 9, 0,
+ /* 3535 */ 'a', 'v', 'e', '_', 'u', '.', 'd', 9, 0,
+ /* 3544 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'd', 9, 0,
+ /* 3554 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'd', 9, 0,
+ /* 3564 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'd', 9, 0,
+ /* 3574 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'd', 9, 0,
+ /* 3584 */ 'm', 'i', 'n', '_', 'u', '.', 'd', 9, 0,
+ /* 3593 */ 'd', 'o', 't', 'p', '_', 'u', '.', 'd', 9, 0,
+ /* 3603 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'd', 9, 0,
+ /* 3613 */ 's', 'u', 'b', 's', '_', 'u', '.', 'd', 9, 0,
+ /* 3623 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'd', 9, 0,
+ /* 3633 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'd', 9, 0,
+ /* 3645 */ 's', 'a', 't', '_', 'u', '.', 'd', 9, 0,
+ /* 3654 */ 'c', 'l', 't', '_', 'u', '.', 'd', 9, 0,
+ /* 3663 */ 'f', 'f', 'i', 'n', 't', '_', 'u', '.', 'd', 9, 0,
+ /* 3674 */ 'f', 't', 'i', 'n', 't', '_', 'u', '.', 'd', 9, 0,
+ /* 3685 */ 'd', 'i', 'v', '_', 'u', '.', 'd', 9, 0,
+ /* 3694 */ 'm', 'a', 'x', '_', 'u', '.', 'd', 9, 0,
+ /* 3703 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'd', 9, 0,
+ /* 3713 */ 'm', 's', 'u', 'b', 'v', '.', 'd', 9, 0,
+ /* 3722 */ 'm', 'a', 'd', 'd', 'v', '.', 'd', 9, 0,
+ /* 3731 */ 'p', 'c', 'k', 'e', 'v', '.', 'd', 9, 0,
+ /* 3740 */ 'i', 'l', 'v', 'e', 'v', '.', 'd', 9, 0,
+ /* 3749 */ 'f', 'd', 'i', 'v', '.', 'd', 9, 0,
+ /* 3757 */ 'm', 'u', 'l', 'v', '.', 'd', 9, 0,
+ /* 3765 */ 'm', 'o', 'v', '.', 'd', 9, 0,
+ /* 3772 */ 't', 'r', 'u', 'n', 'c', '.', 'w', '.', 'd', 9, 0,
+ /* 3783 */ 'r', 'o', 'u', 'n', 'd', '.', 'w', '.', 'd', 9, 0,
+ /* 3794 */ 'c', 'e', 'i', 'l', '.', 'w', '.', 'd', 9, 0,
+ /* 3804 */ 'f', 'l', 'o', 'o', 'r', '.', 'w', '.', 'd', 9, 0,
+ /* 3815 */ 'c', 'v', 't', '.', 'w', '.', 'd', 9, 0,
+ /* 3824 */ 'f', 'm', 'a', 'x', '.', 'd', 9, 0,
+ /* 3832 */ 'b', 'z', '.', 'd', 9, 0,
+ /* 3838 */ 's', 'e', 'l', 'n', 'e', 'z', '.', 'd', 9, 0,
+ /* 3848 */ 'b', 'n', 'z', '.', 'd', 9, 0,
+ /* 3855 */ 's', 'e', 'l', 'e', 'q', 'z', '.', 'd', 9, 0,
+ /* 3865 */ 'm', 'o', 'v', 'z', '.', 'd', 9, 0,
+ /* 3873 */ 's', 'c', 'd', 9, 0,
+ /* 3878 */ 'd', 'a', 'd', 'd', 9, 0,
+ /* 3884 */ 'm', 'a', 'd', 'd', 9, 0,
+ /* 3890 */ 'd', 's', 'h', 'd', 9, 0,
+ /* 3896 */ 'l', 'l', 'd', 9, 0,
+ /* 3901 */ 'a', 'n', 'd', 9, 0,
+ /* 3906 */ 'p', 'r', 'e', 'p', 'e', 'n', 'd', 9, 0,
+ /* 3915 */ 'a', 'p', 'p', 'e', 'n', 'd', 9, 0,
+ /* 3923 */ 'd', 'm', 'o', 'd', 9, 0,
+ /* 3929 */ 's', 'd', 9, 0,
+ /* 3933 */ 't', 'g', 'e', 9, 0,
+ /* 3938 */ 'c', 'a', 'c', 'h', 'e', 9, 0,
+ /* 3945 */ 'b', 'n', 'e', 9, 0,
+ /* 3950 */ 's', 'n', 'e', 9, 0,
+ /* 3955 */ 't', 'n', 'e', 9, 0,
+ /* 3960 */ 'm', 'o', 'v', 'e', 9, 0,
+ /* 3966 */ 'b', 'c', '0', 'f', 9, 0,
+ /* 3972 */ 'b', 'c', '1', 'f', 9, 0,
+ /* 3978 */ 'b', 'c', '2', 'f', 9, 0,
+ /* 3984 */ 'b', 'c', '3', 'f', 9, 0,
+ /* 3990 */ 'p', 'r', 'e', 'f', 9, 0,
+ /* 3996 */ 'm', 'o', 'v', 'f', 9, 0,
+ /* 4002 */ 'n', 'e', 'g', 9, 0,
+ /* 4007 */ 'a', 'd', 'd', '_', 'a', '.', 'h', 9, 0,
+ /* 4016 */ 'm', 'i', 'n', '_', 'a', '.', 'h', 9, 0,
+ /* 4025 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'h', 9, 0,
+ /* 4035 */ 'm', 'a', 'x', '_', 'a', '.', 'h', 9, 0,
+ /* 4044 */ 's', 'r', 'a', '.', 'h', 9, 0,
+ /* 4051 */ 'n', 'l', 'o', 'c', '.', 'h', 9, 0,
+ /* 4059 */ 'n', 'l', 'z', 'c', '.', 'h', 9, 0,
+ /* 4067 */ 's', 'l', 'd', '.', 'h', 9, 0,
+ /* 4074 */ 'p', 'c', 'k', 'o', 'd', '.', 'h', 9, 0,
+ /* 4083 */ 'i', 'l', 'v', 'o', 'd', '.', 'h', 9, 0,
+ /* 4092 */ 'i', 'n', 's', 'v', 'e', '.', 'h', 9, 0,
+ /* 4101 */ 'v', 's', 'h', 'f', '.', 'h', 9, 0,
+ /* 4109 */ 'b', 'n', 'e', 'g', '.', 'h', 9, 0,
+ /* 4117 */ 's', 'r', 'a', 'i', '.', 'h', 9, 0,
+ /* 4125 */ 's', 'l', 'd', 'i', '.', 'h', 9, 0,
+ /* 4133 */ 'b', 'n', 'e', 'g', 'i', '.', 'h', 9, 0,
+ /* 4142 */ 's', 'l', 'l', 'i', '.', 'h', 9, 0,
+ /* 4150 */ 's', 'r', 'l', 'i', '.', 'h', 9, 0,
+ /* 4158 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'h', 9, 0,
+ /* 4168 */ 'c', 'e', 'q', 'i', '.', 'h', 9, 0,
+ /* 4176 */ 's', 'r', 'a', 'r', 'i', '.', 'h', 9, 0,
+ /* 4185 */ 'b', 'c', 'l', 'r', 'i', '.', 'h', 9, 0,
+ /* 4194 */ 's', 'r', 'l', 'r', 'i', '.', 'h', 9, 0,
+ /* 4203 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'h', 9, 0,
+ /* 4213 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'h', 9, 0,
+ /* 4223 */ 'b', 's', 'e', 't', 'i', '.', 'h', 9, 0,
+ /* 4232 */ 's', 'u', 'b', 'v', 'i', '.', 'h', 9, 0,
+ /* 4241 */ 'a', 'd', 'd', 'v', 'i', '.', 'h', 9, 0,
+ /* 4250 */ 'f', 'i', 'l', 'l', '.', 'h', 9, 0,
+ /* 4258 */ 's', 'l', 'l', '.', 'h', 9, 0,
+ /* 4265 */ 's', 'r', 'l', '.', 'h', 9, 0,
+ /* 4272 */ 'b', 'i', 'n', 's', 'l', '.', 'h', 9, 0,
+ /* 4281 */ 'i', 'l', 'v', 'l', '.', 'h', 9, 0,
+ /* 4289 */ 'f', 'e', 'x', 'd', 'o', '.', 'h', 9, 0,
+ /* 4298 */ 'm', 's', 'u', 'b', '_', 'q', '.', 'h', 9, 0,
+ /* 4308 */ 'm', 'a', 'd', 'd', '_', 'q', '.', 'h', 9, 0,
+ /* 4318 */ 'm', 'u', 'l', '_', 'q', '.', 'h', 9, 0,
+ /* 4327 */ 'm', 's', 'u', 'b', 'r', '_', 'q', '.', 'h', 9, 0,
+ /* 4338 */ 'm', 'a', 'd', 'd', 'r', '_', 'q', '.', 'h', 9, 0,
+ /* 4349 */ 'm', 'u', 'l', 'r', '_', 'q', '.', 'h', 9, 0,
+ /* 4359 */ 'c', 'e', 'q', '.', 'h', 9, 0,
+ /* 4366 */ 'f', 't', 'q', '.', 'h', 9, 0,
+ /* 4373 */ 's', 'r', 'a', 'r', '.', 'h', 9, 0,
+ /* 4381 */ 'b', 'c', 'l', 'r', '.', 'h', 9, 0,
+ /* 4389 */ 's', 'r', 'l', 'r', '.', 'h', 9, 0,
+ /* 4397 */ 'b', 'i', 'n', 's', 'r', '.', 'h', 9, 0,
+ /* 4406 */ 'i', 'l', 'v', 'r', '.', 'h', 9, 0,
+ /* 4414 */ 'a', 's', 'u', 'b', '_', 's', '.', 'h', 9, 0,
+ /* 4424 */ 'h', 's', 'u', 'b', '_', 's', '.', 'h', 9, 0,
+ /* 4434 */ 'd', 'p', 's', 'u', 'b', '_', 's', '.', 'h', 9, 0,
+ /* 4445 */ 'h', 'a', 'd', 'd', '_', 's', '.', 'h', 9, 0,
+ /* 4455 */ 'd', 'p', 'a', 'd', 'd', '_', 's', '.', 'h', 9, 0,
+ /* 4466 */ 'm', 'o', 'd', '_', 's', '.', 'h', 9, 0,
+ /* 4475 */ 'c', 'l', 'e', '_', 's', '.', 'h', 9, 0,
+ /* 4484 */ 'a', 'v', 'e', '_', 's', '.', 'h', 9, 0,
+ /* 4493 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'h', 9, 0,
+ /* 4503 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'h', 9, 0,
+ /* 4513 */ 'c', 'l', 't', 'i', '_', 's', '.', 'h', 9, 0,
+ /* 4523 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'h', 9, 0,
+ /* 4533 */ 'm', 'i', 'n', '_', 's', '.', 'h', 9, 0,
+ /* 4542 */ 'd', 'o', 't', 'p', '_', 's', '.', 'h', 9, 0,
+ /* 4552 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'h', 9, 0,
+ /* 4562 */ 'e', 'x', 't', 'r', '_', 's', '.', 'h', 9, 0,
+ /* 4572 */ 's', 'u', 'b', 's', '_', 's', '.', 'h', 9, 0,
+ /* 4582 */ 'a', 'd', 'd', 's', '_', 's', '.', 'h', 9, 0,
+ /* 4592 */ 's', 'a', 't', '_', 's', '.', 'h', 9, 0,
+ /* 4601 */ 'c', 'l', 't', '_', 's', '.', 'h', 9, 0,
+ /* 4610 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'h', 9, 0,
+ /* 4622 */ 'd', 'i', 'v', '_', 's', '.', 'h', 9, 0,
+ /* 4631 */ 'e', 'x', 't', 'r', 'v', '_', 's', '.', 'h', 9, 0,
+ /* 4642 */ 'm', 'a', 'x', '_', 's', '.', 'h', 9, 0,
+ /* 4651 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'h', 9, 0,
+ /* 4661 */ 's', 'p', 'l', 'a', 't', '.', 'h', 9, 0,
+ /* 4670 */ 'b', 's', 'e', 't', '.', 'h', 9, 0,
+ /* 4678 */ 'p', 'c', 'n', 't', '.', 'h', 9, 0,
+ /* 4686 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'h', 9, 0,
+ /* 4696 */ 's', 't', '.', 'h', 9, 0,
+ /* 4702 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'h', 9, 0,
+ /* 4712 */ 'h', 's', 'u', 'b', '_', 'u', '.', 'h', 9, 0,
+ /* 4722 */ 'd', 'p', 's', 'u', 'b', '_', 'u', '.', 'h', 9, 0,
+ /* 4733 */ 'h', 'a', 'd', 'd', '_', 'u', '.', 'h', 9, 0,
+ /* 4743 */ 'd', 'p', 'a', 'd', 'd', '_', 'u', '.', 'h', 9, 0,
+ /* 4754 */ 'm', 'o', 'd', '_', 'u', '.', 'h', 9, 0,
+ /* 4763 */ 'c', 'l', 'e', '_', 'u', '.', 'h', 9, 0,
+ /* 4772 */ 'a', 'v', 'e', '_', 'u', '.', 'h', 9, 0,
+ /* 4781 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'h', 9, 0,
+ /* 4791 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'h', 9, 0,
+ /* 4801 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'h', 9, 0,
+ /* 4811 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'h', 9, 0,
+ /* 4821 */ 'm', 'i', 'n', '_', 'u', '.', 'h', 9, 0,
+ /* 4830 */ 'd', 'o', 't', 'p', '_', 'u', '.', 'h', 9, 0,
+ /* 4840 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'h', 9, 0,
+ /* 4850 */ 's', 'u', 'b', 's', '_', 'u', '.', 'h', 9, 0,
+ /* 4860 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'h', 9, 0,
+ /* 4870 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'h', 9, 0,
+ /* 4882 */ 's', 'a', 't', '_', 'u', '.', 'h', 9, 0,
+ /* 4891 */ 'c', 'l', 't', '_', 'u', '.', 'h', 9, 0,
+ /* 4900 */ 'd', 'i', 'v', '_', 'u', '.', 'h', 9, 0,
+ /* 4909 */ 'm', 'a', 'x', '_', 'u', '.', 'h', 9, 0,
+ /* 4918 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'h', 9, 0,
+ /* 4928 */ 'm', 's', 'u', 'b', 'v', '.', 'h', 9, 0,
+ /* 4937 */ 'm', 'a', 'd', 'd', 'v', '.', 'h', 9, 0,
+ /* 4946 */ 'p', 'c', 'k', 'e', 'v', '.', 'h', 9, 0,
+ /* 4955 */ 'i', 'l', 'v', 'e', 'v', '.', 'h', 9, 0,
+ /* 4964 */ 'm', 'u', 'l', 'v', '.', 'h', 9, 0,
+ /* 4972 */ 'b', 'z', '.', 'h', 9, 0,
+ /* 4978 */ 'b', 'n', 'z', '.', 'h', 9, 0,
+ /* 4985 */ 'd', 's', 'b', 'h', 9, 0,
+ /* 4991 */ 'w', 's', 'b', 'h', 9, 0,
+ /* 4997 */ 's', 'e', 'h', 9, 0,
+ /* 5002 */ 'l', 'h', 9, 0,
+ /* 5006 */ 's', 'h', 'r', 'a', '.', 'p', 'h', 9, 0,
+ /* 5015 */ 'p', 'r', 'e', 'c', 'r', 'q', '.', 'q', 'b', '.', 'p', 'h', 9, 0,
+ /* 5029 */ 'p', 'r', 'e', 'c', 'r', '.', 'q', 'b', '.', 'p', 'h', 9, 0,
+ /* 5042 */ 'p', 'r', 'e', 'c', 'r', 'q', 'u', '_', 's', '.', 'q', 'b', '.', 'p', 'h', 9, 0,
+ /* 5059 */ 'c', 'm', 'p', '.', 'l', 'e', '.', 'p', 'h', 9, 0,
+ /* 5070 */ 's', 'u', 'b', 'q', 'h', '.', 'p', 'h', 9, 0,
+ /* 5080 */ 'a', 'd', 'd', 'q', 'h', '.', 'p', 'h', 9, 0,
+ /* 5090 */ 'p', 'i', 'c', 'k', '.', 'p', 'h', 9, 0,
+ /* 5099 */ 's', 'h', 'l', 'l', '.', 'p', 'h', 9, 0,
+ /* 5108 */ 'r', 'e', 'p', 'l', '.', 'p', 'h', 9, 0,
+ /* 5117 */ 's', 'h', 'r', 'l', '.', 'p', 'h', 9, 0,
+ /* 5126 */ 'p', 'a', 'c', 'k', 'r', 'l', '.', 'p', 'h', 9, 0,
+ /* 5137 */ 'm', 'u', 'l', '.', 'p', 'h', 9, 0,
+ /* 5145 */ 's', 'u', 'b', 'q', '.', 'p', 'h', 9, 0,
+ /* 5154 */ 'a', 'd', 'd', 'q', '.', 'p', 'h', 9, 0,
+ /* 5163 */ 'c', 'm', 'p', '.', 'e', 'q', '.', 'p', 'h', 9, 0,
+ /* 5174 */ 's', 'h', 'r', 'a', '_', 'r', '.', 'p', 'h', 9, 0,
+ /* 5185 */ 's', 'u', 'b', 'q', 'h', '_', 'r', '.', 'p', 'h', 9, 0,
+ /* 5197 */ 'a', 'd', 'd', 'q', 'h', '_', 'r', '.', 'p', 'h', 9, 0,
+ /* 5209 */ 's', 'h', 'r', 'a', 'v', '_', 'r', '.', 'p', 'h', 9, 0,
+ /* 5221 */ 's', 'h', 'l', 'l', '_', 's', '.', 'p', 'h', 9, 0,
+ /* 5232 */ 'm', 'u', 'l', '_', 's', '.', 'p', 'h', 9, 0,
+ /* 5242 */ 's', 'u', 'b', 'q', '_', 's', '.', 'p', 'h', 9, 0,
+ /* 5253 */ 'a', 'd', 'd', 'q', '_', 's', '.', 'p', 'h', 9, 0,
+ /* 5264 */ 'm', 'u', 'l', 'q', '_', 's', '.', 'p', 'h', 9, 0,
+ /* 5275 */ 'a', 'b', 's', 'q', '_', 's', '.', 'p', 'h', 9, 0,
+ /* 5286 */ 's', 'u', 'b', 'u', '_', 's', '.', 'p', 'h', 9, 0,
+ /* 5297 */ 'a', 'd', 'd', 'u', '_', 's', '.', 'p', 'h', 9, 0,
+ /* 5308 */ 's', 'h', 'l', 'l', 'v', '_', 's', '.', 'p', 'h', 9, 0,
+ /* 5320 */ 'm', 'u', 'l', 'q', '_', 'r', 's', '.', 'p', 'h', 9, 0,
+ /* 5332 */ 'c', 'm', 'p', '.', 'l', 't', '.', 'p', 'h', 9, 0,
+ /* 5343 */ 's', 'u', 'b', 'u', '.', 'p', 'h', 9, 0,
+ /* 5352 */ 'a', 'd', 'd', 'u', '.', 'p', 'h', 9, 0,
+ /* 5361 */ 's', 'h', 'r', 'a', 'v', '.', 'p', 'h', 9, 0,
+ /* 5371 */ 's', 'h', 'l', 'l', 'v', '.', 'p', 'h', 9, 0,
+ /* 5381 */ 'r', 'e', 'p', 'l', 'v', '.', 'p', 'h', 9, 0,
+ /* 5391 */ 's', 'h', 'r', 'l', 'v', '.', 'p', 'h', 9, 0,
+ /* 5401 */ 'd', 'p', 'a', '.', 'w', '.', 'p', 'h', 9, 0,
+ /* 5411 */ 'd', 'p', 'a', 'q', 'x', '_', 's', 'a', '.', 'w', '.', 'p', 'h', 9, 0,
+ /* 5426 */ 'd', 'p', 's', 'q', 'x', '_', 's', 'a', '.', 'w', '.', 'p', 'h', 9, 0,
+ /* 5441 */ 'm', 'u', 'l', 's', 'a', '.', 'w', '.', 'p', 'h', 9, 0,
+ /* 5453 */ 'd', 'p', 'a', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0,
+ /* 5466 */ 'm', 'u', 'l', 's', 'a', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0,
+ /* 5481 */ 'd', 'p', 's', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0,
+ /* 5494 */ 'd', 'p', 'a', 'q', 'x', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0,
+ /* 5508 */ 'd', 'p', 's', 'q', 'x', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0,
+ /* 5522 */ 'd', 'p', 's', '.', 'w', '.', 'p', 'h', 9, 0,
+ /* 5532 */ 'd', 'p', 'a', 'x', '.', 'w', '.', 'p', 'h', 9, 0,
+ /* 5543 */ 'd', 'p', 's', 'x', '.', 'w', '.', 'p', 'h', 9, 0,
+ /* 5554 */ 's', 'h', 9, 0,
+ /* 5558 */ 'd', 'm', 'u', 'h', 9, 0,
+ /* 5564 */ 's', 'y', 'n', 'c', 'i', 9, 0,
+ /* 5571 */ 'd', 'a', 'd', 'd', 'i', 9, 0,
+ /* 5578 */ 'a', 'n', 'd', 'i', 9, 0,
+ /* 5584 */ 't', 'g', 'e', 'i', 9, 0,
+ /* 5590 */ 's', 'n', 'e', 'i', 9, 0,
+ /* 5596 */ 't', 'n', 'e', 'i', 9, 0,
+ /* 5602 */ 'd', 'a', 'h', 'i', 9, 0,
+ /* 5608 */ 'm', 'f', 'h', 'i', 9, 0,
+ /* 5614 */ 'm', 't', 'h', 'i', 9, 0,
+ /* 5620 */ '.', 'a', 'l', 'i', 'g', 'n', 32, '2', 10, 9, 'l', 'i', 9, 0,
+ /* 5634 */ 'd', 'l', 'i', 9, 0,
+ /* 5639 */ 'c', 'm', 'p', 'i', 9, 0,
+ /* 5645 */ 's', 'e', 'q', 'i', 9, 0,
+ /* 5651 */ 't', 'e', 'q', 'i', 9, 0,
+ /* 5657 */ 'x', 'o', 'r', 'i', 9, 0,
+ /* 5663 */ 'd', 'a', 't', 'i', 9, 0,
+ /* 5669 */ 's', 'l', 't', 'i', 9, 0,
+ /* 5675 */ 't', 'l', 't', 'i', 9, 0,
+ /* 5681 */ 'd', 'a', 'u', 'i', 9, 0,
+ /* 5687 */ 'l', 'u', 'i', 9, 0,
+ /* 5692 */ 'j', 9, 0,
+ /* 5695 */ 'b', 'r', 'e', 'a', 'k', 9, 0,
+ /* 5702 */ 'c', 'v', 't', '.', 'd', '.', 'l', 9, 0,
+ /* 5711 */ 'c', 'v', 't', '.', 's', '.', 'l', 9, 0,
+ /* 5720 */ 'b', 'a', 'l', 9, 0,
+ /* 5725 */ 'j', 'a', 'l', 9, 0,
+ /* 5730 */ 'b', 'g', 'e', 'z', 'a', 'l', 9, 0,
+ /* 5738 */ 'b', 'l', 't', 'z', 'a', 'l', 9, 0,
+ /* 5746 */ 'd', 'p', 'a', 'u', '.', 'h', '.', 'q', 'b', 'l', 9, 0,
+ /* 5758 */ 'd', 'p', 's', 'u', '.', 'h', '.', 'q', 'b', 'l', 9, 0,
+ /* 5770 */ 'm', 'u', 'l', 'e', 'u', '_', 's', '.', 'p', 'h', '.', 'q', 'b', 'l', 9, 0,
+ /* 5786 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 9, 0,
+ /* 5801 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 9, 0,
+ /* 5817 */ 'l', 'd', 'l', 9, 0,
+ /* 5822 */ 's', 'd', 'l', 9, 0,
+ /* 5827 */ 'b', 'n', 'e', 'l', 9, 0,
+ /* 5833 */ 'b', 'c', '0', 'f', 'l', 9, 0,
+ /* 5840 */ 'b', 'c', '1', 'f', 'l', 9, 0,
+ /* 5847 */ 'b', 'c', '2', 'f', 'l', 9, 0,
+ /* 5854 */ 'b', 'c', '3', 'f', 'l', 9, 0,
+ /* 5861 */ 'm', 'a', 'q', '_', 's', 'a', '.', 'w', '.', 'p', 'h', 'l', 9, 0,
+ /* 5875 */ 'p', 'r', 'e', 'c', 'e', 'q', '.', 'w', '.', 'p', 'h', 'l', 9, 0,
+ /* 5889 */ 'm', 'a', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 'l', 9, 0,
+ /* 5902 */ 'm', 'u', 'l', 'e', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 'l', 9, 0,
+ /* 5917 */ 's', 'y', 's', 'c', 'a', 'l', 'l', 9, 0,
+ /* 5926 */ 'b', 'g', 'e', 'z', 'a', 'l', 'l', 9, 0,
+ /* 5935 */ 'b', 'l', 't', 'z', 'a', 'l', 'l', 9, 0,
+ /* 5944 */ 'd', 's', 'l', 'l', 9, 0,
+ /* 5950 */ 'b', 'e', 'q', 'l', 9, 0,
+ /* 5956 */ 'd', 's', 'r', 'l', 9, 0,
+ /* 5962 */ 'b', 'c', '0', 't', 'l', 9, 0,
+ /* 5969 */ 'b', 'c', '1', 't', 'l', 9, 0,
+ /* 5976 */ 'b', 'c', '2', 't', 'l', 9, 0,
+ /* 5983 */ 'b', 'c', '3', 't', 'l', 9, 0,
+ /* 5990 */ 'd', 'm', 'u', 'l', 9, 0,
+ /* 5996 */ 'l', 'w', 'l', 9, 0,
+ /* 6001 */ 's', 'w', 'l', 9, 0,
+ /* 6006 */ 'b', 'g', 'e', 'z', 'l', 9, 0,
+ /* 6013 */ 'b', 'l', 'e', 'z', 'l', 9, 0,
+ /* 6020 */ 'b', 'g', 't', 'z', 'l', 9, 0,
+ /* 6027 */ 'b', 'l', 't', 'z', 'l', 9, 0,
+ /* 6034 */ 'l', 'w', 'm', 9, 0,
+ /* 6039 */ 's', 'w', 'm', 9, 0,
+ /* 6044 */ 'b', 'a', 'l', 'i', 'g', 'n', 9, 0,
+ /* 6052 */ 'd', 'a', 'l', 'i', 'g', 'n', 9, 0,
+ /* 6060 */ 'm', 'o', 'v', 'n', 9, 0,
+ /* 6066 */ 'd', 'c', 'l', 'o', 9, 0,
+ /* 6072 */ 'm', 'f', 'l', 'o', 9, 0,
+ /* 6078 */ 's', 'h', 'i', 'l', 'o', 9, 0,
+ /* 6085 */ 'm', 't', 'l', 'o', 9, 0,
+ /* 6091 */ 'd', 'b', 'i', 't', 's', 'w', 'a', 'p', 9, 0,
+ /* 6101 */ 's', 'd', 'b', 'b', 'p', 9, 0,
+ /* 6108 */ 'e', 'x', 't', 'p', 'd', 'p', 9, 0,
+ /* 6116 */ 'm', 'o', 'v', 'e', 'p', 9, 0,
+ /* 6123 */ 'm', 't', 'h', 'l', 'i', 'p', 9, 0,
+ /* 6131 */ 'c', 'm', 'p', 9, 0,
+ /* 6136 */ 'd', 'p', 'o', 'p', 9, 0,
+ /* 6142 */ 'a', 'd', 'd', 'i', 'u', 'r', '1', 's', 'p', 9, 0,
+ /* 6153 */ 'l', 'o', 'a', 'd', '_', 'c', 'c', 'o', 'n', 'd', '_', 'd', 's', 'p', 9, 0,
+ /* 6169 */ 's', 't', 'o', 'r', 'e', '_', 'c', 'c', 'o', 'n', 'd', '_', 'd', 's', 'p', 9, 0,
+ /* 6186 */ 'r', 'd', 'd', 's', 'p', 9, 0,
+ /* 6193 */ 'w', 'r', 'd', 's', 'p', 9, 0,
+ /* 6200 */ 'j', 'r', 'a', 'd', 'd', 'i', 'u', 's', 'p', 9, 0,
+ /* 6211 */ 'e', 'x', 't', 'p', 9, 0,
+ /* 6217 */ 'l', 'w', 'p', 9, 0,
+ /* 6222 */ 's', 'w', 'p', 9, 0,
+ /* 6227 */ 'b', 'e', 'q', 9, 0,
+ /* 6232 */ 's', 'e', 'q', 9, 0,
+ /* 6237 */ 't', 'e', 'q', 9, 0,
+ /* 6242 */ 'd', 'p', 'a', 'u', '.', 'h', '.', 'q', 'b', 'r', 9, 0,
+ /* 6254 */ 'd', 'p', 's', 'u', '.', 'h', '.', 'q', 'b', 'r', 9, 0,
+ /* 6266 */ 'm', 'u', 'l', 'e', 'u', '_', 's', '.', 'p', 'h', '.', 'q', 'b', 'r', 9, 0,
+ /* 6282 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 9, 0,
+ /* 6297 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 9, 0,
+ /* 6313 */ 'l', 'd', 'r', 9, 0,
+ /* 6318 */ 's', 'd', 'r', 9, 0,
+ /* 6323 */ 'm', 'a', 'q', '_', 's', 'a', '.', 'w', '.', 'p', 'h', 'r', 9, 0,
+ /* 6337 */ 'p', 'r', 'e', 'c', 'e', 'q', '.', 'w', '.', 'p', 'h', 'r', 9, 0,
+ /* 6351 */ 'm', 'a', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 'r', 9, 0,
+ /* 6364 */ 'm', 'u', 'l', 'e', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 'r', 9, 0,
+ /* 6379 */ 'j', 'r', 9, 0,
+ /* 6383 */ 'j', 'a', 'l', 'r', 9, 0,
+ /* 6389 */ 'n', 'o', 'r', 9, 0,
+ /* 6394 */ 'x', 'o', 'r', 9, 0,
+ /* 6399 */ 'd', 'r', 'o', 't', 'r', 9, 0,
+ /* 6406 */ 'r', 'd', 'h', 'w', 'r', 9, 0,
+ /* 6413 */ 'l', 'w', 'r', 9, 0,
+ /* 6418 */ 's', 'w', 'r', 9, 0,
+ /* 6423 */ 'm', 'i', 'n', 'a', '.', 's', 9, 0,
+ /* 6431 */ 'm', 'a', 'x', 'a', '.', 's', 9, 0,
+ /* 6439 */ 'n', 'm', 's', 'u', 'b', '.', 's', 9, 0,
+ /* 6448 */ 'c', 'v', 't', '.', 'd', '.', 's', 9, 0,
+ /* 6457 */ 'n', 'm', 'a', 'd', 'd', '.', 's', 9, 0,
+ /* 6466 */ 'c', '.', 'n', 'g', 'e', '.', 's', 9, 0,
+ /* 6475 */ 'c', '.', 'l', 'e', '.', 's', 9, 0,
+ /* 6483 */ 'c', 'm', 'p', '.', 'l', 'e', '.', 's', 9, 0,
+ /* 6493 */ 'c', '.', 'n', 'g', 'l', 'e', '.', 's', 9, 0,
+ /* 6503 */ 'c', '.', 'o', 'l', 'e', '.', 's', 9, 0,
+ /* 6512 */ 'c', 'm', 'p', '.', 's', 'l', 'e', '.', 's', 9, 0,
+ /* 6523 */ 'c', '.', 'u', 'l', 'e', '.', 's', 9, 0,
+ /* 6532 */ 'c', 'm', 'p', '.', 'u', 'l', 'e', '.', 's', 9, 0,
+ /* 6543 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 'e', '.', 's', 9, 0,
+ /* 6555 */ 'c', '.', 'f', '.', 's', 9, 0,
+ /* 6562 */ 'c', 'm', 'p', '.', 'a', 'f', '.', 's', 9, 0,
+ /* 6572 */ 'c', 'm', 'p', '.', 's', 'a', 'f', '.', 's', 9, 0,
+ /* 6583 */ 'm', 's', 'u', 'b', 'f', '.', 's', 9, 0,
+ /* 6592 */ 'm', 'a', 'd', 'd', 'f', '.', 's', 9, 0,
+ /* 6601 */ 'c', '.', 's', 'f', '.', 's', 9, 0,
+ /* 6609 */ 'm', 'o', 'v', 'f', '.', 's', 9, 0,
+ /* 6617 */ 'n', 'e', 'g', '.', 's', 9, 0,
+ /* 6624 */ 't', 'r', 'u', 'n', 'c', '.', 'l', '.', 's', 9, 0,
+ /* 6635 */ 'r', 'o', 'u', 'n', 'd', '.', 'l', '.', 's', 9, 0,
+ /* 6646 */ 'c', 'e', 'i', 'l', '.', 'l', '.', 's', 9, 0,
+ /* 6656 */ 'f', 'l', 'o', 'o', 'r', '.', 'l', '.', 's', 9, 0,
+ /* 6667 */ 'c', 'v', 't', '.', 'l', '.', 's', 9, 0,
+ /* 6676 */ 's', 'e', 'l', '.', 's', 9, 0,
+ /* 6683 */ 'c', '.', 'n', 'g', 'l', '.', 's', 9, 0,
+ /* 6692 */ 'm', 'u', 'l', '.', 's', 9, 0,
+ /* 6699 */ 'm', 'i', 'n', '.', 's', 9, 0,
+ /* 6706 */ 'c', '.', 'u', 'n', '.', 's', 9, 0,
+ /* 6714 */ 'c', 'm', 'p', '.', 'u', 'n', '.', 's', 9, 0,
+ /* 6724 */ 'c', 'm', 'p', '.', 's', 'u', 'n', '.', 's', 9, 0,
+ /* 6735 */ 'm', 'o', 'v', 'n', '.', 's', 9, 0,
+ /* 6743 */ 'c', '.', 'e', 'q', '.', 's', 9, 0,
+ /* 6751 */ 'c', 'm', 'p', '.', 'e', 'q', '.', 's', 9, 0,
+ /* 6761 */ 'c', '.', 's', 'e', 'q', '.', 's', 9, 0,
+ /* 6770 */ 'c', 'm', 'p', '.', 's', 'e', 'q', '.', 's', 9, 0,
+ /* 6781 */ 'c', '.', 'u', 'e', 'q', '.', 's', 9, 0,
+ /* 6790 */ 'c', 'm', 'p', '.', 'u', 'e', 'q', '.', 's', 9, 0,
+ /* 6801 */ 'c', 'm', 'p', '.', 's', 'u', 'e', 'q', '.', 's', 9, 0,
+ /* 6813 */ 'a', 'b', 's', '.', 's', 9, 0,
+ /* 6820 */ 'c', 'l', 'a', 's', 's', '.', 's', 9, 0,
+ /* 6829 */ 'c', '.', 'n', 'g', 't', '.', 's', 9, 0,
+ /* 6838 */ 'c', '.', 'l', 't', '.', 's', 9, 0,
+ /* 6846 */ 'c', 'm', 'p', '.', 'l', 't', '.', 's', 9, 0,
+ /* 6856 */ 'c', '.', 'o', 'l', 't', '.', 's', 9, 0,
+ /* 6865 */ 'c', 'm', 'p', '.', 's', 'l', 't', '.', 's', 9, 0,
+ /* 6876 */ 'c', '.', 'u', 'l', 't', '.', 's', 9, 0,
+ /* 6885 */ 'c', 'm', 'p', '.', 'u', 'l', 't', '.', 's', 9, 0,
+ /* 6896 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 't', '.', 's', 9, 0,
+ /* 6908 */ 'r', 'i', 'n', 't', '.', 's', 9, 0,
+ /* 6916 */ 's', 'q', 'r', 't', '.', 's', 9, 0,
+ /* 6924 */ 'm', 'o', 'v', 't', '.', 's', 9, 0,
+ /* 6932 */ 'd', 'i', 'v', '.', 's', 9, 0,
+ /* 6939 */ 'm', 'o', 'v', '.', 's', 9, 0,
+ /* 6946 */ 't', 'r', 'u', 'n', 'c', '.', 'w', '.', 's', 9, 0,
+ /* 6957 */ 'r', 'o', 'u', 'n', 'd', '.', 'w', '.', 's', 9, 0,
+ /* 6968 */ 'c', 'e', 'i', 'l', '.', 'w', '.', 's', 9, 0,
+ /* 6978 */ 'f', 'l', 'o', 'o', 'r', '.', 'w', '.', 's', 9, 0,
+ /* 6989 */ 'c', 'v', 't', '.', 'w', '.', 's', 9, 0,
+ /* 6998 */ 'm', 'a', 'x', '.', 's', 9, 0,
+ /* 7005 */ 's', 'e', 'l', 'n', 'e', 'z', '.', 's', 9, 0,
+ /* 7015 */ 's', 'e', 'l', 'e', 'q', 'z', '.', 's', 9, 0,
+ /* 7025 */ 'm', 'o', 'v', 'z', '.', 's', 9, 0,
+ /* 7033 */ 'j', 'a', 'l', 's', 9, 0,
+ /* 7039 */ 'b', 'g', 'e', 'z', 'a', 'l', 's', 9, 0,
+ /* 7048 */ 'b', 'l', 't', 'z', 'a', 'l', 's', 9, 0,
+ /* 7057 */ 'j', 'a', 'l', 'r', 's', 9, 0,
+ /* 7064 */ 'l', 'w', 'x', 's', 9, 0,
+ /* 7070 */ 'b', 'c', '0', 't', 9, 0,
+ /* 7076 */ 'b', 'c', '1', 't', 9, 0,
+ /* 7082 */ 'b', 'c', '2', 't', 9, 0,
+ /* 7088 */ 'b', 'c', '3', 't', 9, 0,
+ /* 7094 */ 'w', 'a', 'i', 't', 9, 0,
+ /* 7100 */ 's', 'l', 't', 9, 0,
+ /* 7105 */ 't', 'l', 't', 9, 0,
+ /* 7110 */ 'd', 'm', 'u', 'l', 't', 9, 0,
+ /* 7117 */ 'n', 'o', 't', 9, 0,
+ /* 7122 */ 'm', 'o', 'v', 't', 9, 0,
+ /* 7128 */ 'l', 'b', 'u', 9, 0,
+ /* 7133 */ 'd', 's', 'u', 'b', 'u', 9, 0,
+ /* 7140 */ 'm', 's', 'u', 'b', 'u', 9, 0,
+ /* 7147 */ 'b', 'a', 'd', 'd', 'u', 9, 0,
+ /* 7154 */ 'd', 'a', 'd', 'd', 'u', 9, 0,
+ /* 7161 */ 'm', 'a', 'd', 'd', 'u', 9, 0,
+ /* 7168 */ 'd', 'm', 'o', 'd', 'u', 9, 0,
+ /* 7175 */ 't', 'g', 'e', 'u', 9, 0,
+ /* 7181 */ 'l', 'h', 'u', 9, 0,
+ /* 7186 */ 'd', 'm', 'u', 'h', 'u', 9, 0,
+ /* 7193 */ 'd', 'a', 'd', 'd', 'i', 'u', 9, 0,
+ /* 7201 */ 't', 'g', 'e', 'i', 'u', 9, 0,
+ /* 7208 */ 's', 'l', 't', 'i', 'u', 9, 0,
+ /* 7215 */ 't', 'l', 't', 'i', 'u', 9, 0,
+ /* 7222 */ 'v', '3', 'm', 'u', 'l', 'u', 9, 0,
+ /* 7230 */ 'd', 'm', 'u', 'l', 'u', 9, 0,
+ /* 7237 */ 'v', 'm', 'u', 'l', 'u', 9, 0,
+ /* 7244 */ 's', 'l', 't', 'u', 9, 0,
+ /* 7250 */ 't', 'l', 't', 'u', 9, 0,
+ /* 7256 */ 'd', 'm', 'u', 'l', 't', 'u', 9, 0,
+ /* 7264 */ 'd', 'd', 'i', 'v', 'u', 9, 0,
+ /* 7271 */ 'l', 'w', 'u', 9, 0,
+ /* 7276 */ 'a', 'n', 'd', '.', 'v', 9, 0,
+ /* 7283 */ 'm', 'o', 'v', 'e', '.', 'v', 9, 0,
+ /* 7291 */ 'b', 's', 'e', 'l', '.', 'v', 9, 0,
+ /* 7299 */ 'n', 'o', 'r', '.', 'v', 9, 0,
+ /* 7306 */ 'x', 'o', 'r', '.', 'v', 9, 0,
+ /* 7313 */ 'b', 'z', '.', 'v', 9, 0,
+ /* 7319 */ 'b', 'm', 'z', '.', 'v', 9, 0,
+ /* 7326 */ 'b', 'n', 'z', '.', 'v', 9, 0,
+ /* 7333 */ 'b', 'm', 'n', 'z', '.', 'v', 9, 0,
+ /* 7341 */ 'd', 's', 'r', 'a', 'v', 9, 0,
+ /* 7348 */ 'b', 'i', 't', 'r', 'e', 'v', 9, 0,
+ /* 7356 */ 'd', 'd', 'i', 'v', 9, 0,
+ /* 7362 */ 'd', 's', 'l', 'l', 'v', 9, 0,
+ /* 7369 */ 'd', 's', 'r', 'l', 'v', 9, 0,
+ /* 7376 */ 's', 'h', 'i', 'l', 'o', 'v', 9, 0,
+ /* 7384 */ 'e', 'x', 't', 'p', 'd', 'p', 'v', 9, 0,
+ /* 7393 */ 'e', 'x', 't', 'p', 'v', 9, 0,
+ /* 7400 */ 'd', 'r', 'o', 't', 'r', 'v', 9, 0,
+ /* 7408 */ 'i', 'n', 's', 'v', 9, 0,
+ /* 7414 */ 'f', 'l', 'o', 'g', '2', '.', 'w', 9, 0,
+ /* 7423 */ 'f', 'e', 'x', 'p', '2', '.', 'w', 9, 0,
+ /* 7432 */ 'a', 'd', 'd', '_', 'a', '.', 'w', 9, 0,
+ /* 7441 */ 'f', 'm', 'i', 'n', '_', 'a', '.', 'w', 9, 0,
+ /* 7451 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'w', 9, 0,
+ /* 7461 */ 'f', 'm', 'a', 'x', '_', 'a', '.', 'w', 9, 0,
+ /* 7471 */ 's', 'r', 'a', '.', 'w', 9, 0,
+ /* 7478 */ 'f', 's', 'u', 'b', '.', 'w', 9, 0,
+ /* 7486 */ 'f', 'm', 's', 'u', 'b', '.', 'w', 9, 0,
+ /* 7495 */ 'n', 'l', 'o', 'c', '.', 'w', 9, 0,
+ /* 7503 */ 'n', 'l', 'z', 'c', '.', 'w', 9, 0,
+ /* 7511 */ 'c', 'v', 't', '.', 'd', '.', 'w', 9, 0,
+ /* 7520 */ 'f', 'a', 'd', 'd', '.', 'w', 9, 0,
+ /* 7528 */ 'f', 'm', 'a', 'd', 'd', '.', 'w', 9, 0,
+ /* 7537 */ 's', 'l', 'd', '.', 'w', 9, 0,
+ /* 7544 */ 'p', 'c', 'k', 'o', 'd', '.', 'w', 9, 0,
+ /* 7553 */ 'i', 'l', 'v', 'o', 'd', '.', 'w', 9, 0,
+ /* 7562 */ 'f', 'c', 'l', 'e', '.', 'w', 9, 0,
+ /* 7570 */ 'f', 's', 'l', 'e', '.', 'w', 9, 0,
+ /* 7578 */ 'f', 'c', 'u', 'l', 'e', '.', 'w', 9, 0,
+ /* 7587 */ 'f', 's', 'u', 'l', 'e', '.', 'w', 9, 0,
+ /* 7596 */ 'f', 'c', 'n', 'e', '.', 'w', 9, 0,
+ /* 7604 */ 'f', 's', 'n', 'e', '.', 'w', 9, 0,
+ /* 7612 */ 'f', 'c', 'u', 'n', 'e', '.', 'w', 9, 0,
+ /* 7621 */ 'f', 's', 'u', 'n', 'e', '.', 'w', 9, 0,
+ /* 7630 */ 'i', 'n', 's', 'v', 'e', '.', 'w', 9, 0,
+ /* 7639 */ 'f', 'c', 'a', 'f', '.', 'w', 9, 0,
+ /* 7647 */ 'f', 's', 'a', 'f', '.', 'w', 9, 0,
+ /* 7655 */ 'v', 's', 'h', 'f', '.', 'w', 9, 0,
+ /* 7663 */ 'b', 'n', 'e', 'g', '.', 'w', 9, 0,
+ /* 7671 */ 'p', 'r', 'e', 'c', 'r', '_', 's', 'r', 'a', '.', 'p', 'h', '.', 'w', 9, 0,
+ /* 7687 */ 'p', 'r', 'e', 'c', 'r', 'q', '.', 'p', 'h', '.', 'w', 9, 0,
+ /* 7700 */ 'p', 'r', 'e', 'c', 'r', '_', 's', 'r', 'a', '_', 'r', '.', 'p', 'h', '.', 'w', 9, 0,
+ /* 7718 */ 'p', 'r', 'e', 'c', 'r', 'q', '_', 'r', 's', '.', 'p', 'h', '.', 'w', 9, 0,
+ /* 7734 */ 's', 'u', 'b', 'q', 'h', '.', 'w', 9, 0,
+ /* 7743 */ 'a', 'd', 'd', 'q', 'h', '.', 'w', 9, 0,
+ /* 7752 */ 's', 'r', 'a', 'i', '.', 'w', 9, 0,
+ /* 7760 */ 's', 'l', 'd', 'i', '.', 'w', 9, 0,
+ /* 7768 */ 'b', 'n', 'e', 'g', 'i', '.', 'w', 9, 0,
+ /* 7777 */ 's', 'l', 'l', 'i', '.', 'w', 9, 0,
+ /* 7785 */ 's', 'r', 'l', 'i', '.', 'w', 9, 0,
+ /* 7793 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'w', 9, 0,
+ /* 7803 */ 'c', 'e', 'q', 'i', '.', 'w', 9, 0,
+ /* 7811 */ 's', 'r', 'a', 'r', 'i', '.', 'w', 9, 0,
+ /* 7820 */ 'b', 'c', 'l', 'r', 'i', '.', 'w', 9, 0,
+ /* 7829 */ 's', 'r', 'l', 'r', 'i', '.', 'w', 9, 0,
+ /* 7838 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'w', 9, 0,
+ /* 7848 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'w', 9, 0,
+ /* 7858 */ 'b', 's', 'e', 't', 'i', '.', 'w', 9, 0,
+ /* 7867 */ 's', 'u', 'b', 'v', 'i', '.', 'w', 9, 0,
+ /* 7876 */ 'a', 'd', 'd', 'v', 'i', '.', 'w', 9, 0,
+ /* 7885 */ 'd', 'p', 'a', 'q', '_', 's', 'a', '.', 'l', '.', 'w', 9, 0,
+ /* 7898 */ 'd', 'p', 's', 'q', '_', 's', 'a', '.', 'l', '.', 'w', 9, 0,
+ /* 7911 */ 'f', 'i', 'l', 'l', '.', 'w', 9, 0,
+ /* 7919 */ 's', 'l', 'l', '.', 'w', 9, 0,
+ /* 7926 */ 'f', 'e', 'x', 'u', 'p', 'l', '.', 'w', 9, 0,
+ /* 7936 */ 'f', 'f', 'q', 'l', '.', 'w', 9, 0,
+ /* 7944 */ 's', 'r', 'l', '.', 'w', 9, 0,
+ /* 7951 */ 'b', 'i', 'n', 's', 'l', '.', 'w', 9, 0,
+ /* 7960 */ 'f', 'm', 'u', 'l', '.', 'w', 9, 0,
+ /* 7968 */ 'i', 'l', 'v', 'l', '.', 'w', 9, 0,
+ /* 7976 */ 'f', 'm', 'i', 'n', '.', 'w', 9, 0,
+ /* 7984 */ 'f', 'c', 'u', 'n', '.', 'w', 9, 0,
+ /* 7992 */ 'f', 's', 'u', 'n', '.', 'w', 9, 0,
+ /* 8000 */ 'f', 'e', 'x', 'd', 'o', '.', 'w', 9, 0,
+ /* 8009 */ 'f', 'r', 'c', 'p', '.', 'w', 9, 0,
+ /* 8017 */ 'm', 's', 'u', 'b', '_', 'q', '.', 'w', 9, 0,
+ /* 8027 */ 'm', 'a', 'd', 'd', '_', 'q', '.', 'w', 9, 0,
+ /* 8037 */ 'm', 'u', 'l', '_', 'q', '.', 'w', 9, 0,
+ /* 8046 */ 'm', 's', 'u', 'b', 'r', '_', 'q', '.', 'w', 9, 0,
+ /* 8057 */ 'm', 'a', 'd', 'd', 'r', '_', 'q', '.', 'w', 9, 0,
+ /* 8068 */ 'm', 'u', 'l', 'r', '_', 'q', '.', 'w', 9, 0,
+ /* 8078 */ 'f', 'c', 'e', 'q', '.', 'w', 9, 0,
+ /* 8086 */ 'f', 's', 'e', 'q', '.', 'w', 9, 0,
+ /* 8094 */ 'f', 'c', 'u', 'e', 'q', '.', 'w', 9, 0,
+ /* 8103 */ 'f', 's', 'u', 'e', 'q', '.', 'w', 9, 0,
+ /* 8112 */ 'f', 't', 'q', '.', 'w', 9, 0,
+ /* 8119 */ 's', 'h', 'r', 'a', '_', 'r', '.', 'w', 9, 0,
+ /* 8129 */ 's', 'u', 'b', 'q', 'h', '_', 'r', '.', 'w', 9, 0,
+ /* 8140 */ 'a', 'd', 'd', 'q', 'h', '_', 'r', '.', 'w', 9, 0,
+ /* 8151 */ 'e', 'x', 't', 'r', '_', 'r', '.', 'w', 9, 0,
+ /* 8161 */ 's', 'h', 'r', 'a', 'v', '_', 'r', '.', 'w', 9, 0,
+ /* 8172 */ 'e', 'x', 't', 'r', 'v', '_', 'r', '.', 'w', 9, 0,
+ /* 8183 */ 's', 'r', 'a', 'r', '.', 'w', 9, 0,
+ /* 8191 */ 'b', 'c', 'l', 'r', '.', 'w', 9, 0,
+ /* 8199 */ 's', 'r', 'l', 'r', '.', 'w', 9, 0,
+ /* 8207 */ 'f', 'c', 'o', 'r', '.', 'w', 9, 0,
+ /* 8215 */ 'f', 's', 'o', 'r', '.', 'w', 9, 0,
+ /* 8223 */ 'f', 'e', 'x', 'u', 'p', 'r', '.', 'w', 9, 0,
+ /* 8233 */ 'f', 'f', 'q', 'r', '.', 'w', 9, 0,
+ /* 8241 */ 'b', 'i', 'n', 's', 'r', '.', 'w', 9, 0,
+ /* 8250 */ 'e', 'x', 't', 'r', '.', 'w', 9, 0,
+ /* 8258 */ 'i', 'l', 'v', 'r', '.', 'w', 9, 0,
+ /* 8266 */ 'c', 'v', 't', '.', 's', '.', 'w', 9, 0,
+ /* 8275 */ 'a', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0,
+ /* 8285 */ 'h', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0,
+ /* 8295 */ 'd', 'p', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0,
+ /* 8306 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 's', '.', 'w', 9, 0,
+ /* 8318 */ 'h', 'a', 'd', 'd', '_', 's', '.', 'w', 9, 0,
+ /* 8328 */ 'd', 'p', 'a', 'd', 'd', '_', 's', '.', 'w', 9, 0,
+ /* 8339 */ 'm', 'o', 'd', '_', 's', '.', 'w', 9, 0,
+ /* 8348 */ 'c', 'l', 'e', '_', 's', '.', 'w', 9, 0,
+ /* 8357 */ 'a', 'v', 'e', '_', 's', '.', 'w', 9, 0,
+ /* 8366 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'w', 9, 0,
+ /* 8376 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'w', 9, 0,
+ /* 8386 */ 'c', 'l', 't', 'i', '_', 's', '.', 'w', 9, 0,
+ /* 8396 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'w', 9, 0,
+ /* 8406 */ 's', 'h', 'l', 'l', '_', 's', '.', 'w', 9, 0,
+ /* 8416 */ 'm', 'i', 'n', '_', 's', '.', 'w', 9, 0,
+ /* 8425 */ 'd', 'o', 't', 'p', '_', 's', '.', 'w', 9, 0,
+ /* 8435 */ 's', 'u', 'b', 'q', '_', 's', '.', 'w', 9, 0,
+ /* 8445 */ 'a', 'd', 'd', 'q', '_', 's', '.', 'w', 9, 0,
+ /* 8455 */ 'm', 'u', 'l', 'q', '_', 's', '.', 'w', 9, 0,
+ /* 8465 */ 'a', 'b', 's', 'q', '_', 's', '.', 'w', 9, 0,
+ /* 8475 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'w', 9, 0,
+ /* 8485 */ 's', 'u', 'b', 's', '_', 's', '.', 'w', 9, 0,
+ /* 8495 */ 'a', 'd', 'd', 's', '_', 's', '.', 'w', 9, 0,
+ /* 8505 */ 's', 'a', 't', '_', 's', '.', 'w', 9, 0,
+ /* 8514 */ 'c', 'l', 't', '_', 's', '.', 'w', 9, 0,
+ /* 8523 */ 'f', 'f', 'i', 'n', 't', '_', 's', '.', 'w', 9, 0,
+ /* 8534 */ 'f', 't', 'i', 'n', 't', '_', 's', '.', 'w', 9, 0,
+ /* 8545 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'w', 9, 0,
+ /* 8557 */ 'd', 'i', 'v', '_', 's', '.', 'w', 9, 0,
+ /* 8566 */ 's', 'h', 'l', 'l', 'v', '_', 's', '.', 'w', 9, 0,
+ /* 8577 */ 'm', 'a', 'x', '_', 's', '.', 'w', 9, 0,
+ /* 8586 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'w', 9, 0,
+ /* 8596 */ 'm', 'u', 'l', 'q', '_', 'r', 's', '.', 'w', 9, 0,
+ /* 8607 */ 'e', 'x', 't', 'r', '_', 'r', 's', '.', 'w', 9, 0,
+ /* 8618 */ 'e', 'x', 't', 'r', 'v', '_', 'r', 's', '.', 'w', 9, 0,
+ /* 8630 */ 'f', 'c', 'l', 'a', 's', 's', '.', 'w', 9, 0,
+ /* 8640 */ 's', 'p', 'l', 'a', 't', '.', 'w', 9, 0,
+ /* 8649 */ 'b', 's', 'e', 't', '.', 'w', 9, 0,
+ /* 8657 */ 'f', 'c', 'l', 't', '.', 'w', 9, 0,
+ /* 8665 */ 'f', 's', 'l', 't', '.', 'w', 9, 0,
+ /* 8673 */ 'f', 'c', 'u', 'l', 't', '.', 'w', 9, 0,
+ /* 8682 */ 'f', 's', 'u', 'l', 't', '.', 'w', 9, 0,
+ /* 8691 */ 'p', 'c', 'n', 't', '.', 'w', 9, 0,
+ /* 8699 */ 'f', 'r', 'i', 'n', 't', '.', 'w', 9, 0,
+ /* 8708 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'w', 9, 0,
+ /* 8718 */ 'f', 's', 'q', 'r', 't', '.', 'w', 9, 0,
+ /* 8727 */ 'f', 'r', 's', 'q', 'r', 't', '.', 'w', 9, 0,
+ /* 8737 */ 's', 't', '.', 'w', 9, 0,
+ /* 8743 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0,
+ /* 8753 */ 'h', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0,
+ /* 8763 */ 'd', 'p', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0,
+ /* 8774 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 'u', '.', 'w', 9, 0,
+ /* 8786 */ 'h', 'a', 'd', 'd', '_', 'u', '.', 'w', 9, 0,
+ /* 8796 */ 'd', 'p', 'a', 'd', 'd', '_', 'u', '.', 'w', 9, 0,
+ /* 8807 */ 'm', 'o', 'd', '_', 'u', '.', 'w', 9, 0,
+ /* 8816 */ 'c', 'l', 'e', '_', 'u', '.', 'w', 9, 0,
+ /* 8825 */ 'a', 'v', 'e', '_', 'u', '.', 'w', 9, 0,
+ /* 8834 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'w', 9, 0,
+ /* 8844 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'w', 9, 0,
+ /* 8854 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'w', 9, 0,
+ /* 8864 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'w', 9, 0,
+ /* 8874 */ 'm', 'i', 'n', '_', 'u', '.', 'w', 9, 0,
+ /* 8883 */ 'd', 'o', 't', 'p', '_', 'u', '.', 'w', 9, 0,
+ /* 8893 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'w', 9, 0,
+ /* 8903 */ 's', 'u', 'b', 's', '_', 'u', '.', 'w', 9, 0,
+ /* 8913 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'w', 9, 0,
+ /* 8923 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'w', 9, 0,
+ /* 8935 */ 's', 'a', 't', '_', 'u', '.', 'w', 9, 0,
+ /* 8944 */ 'c', 'l', 't', '_', 'u', '.', 'w', 9, 0,
+ /* 8953 */ 'f', 'f', 'i', 'n', 't', '_', 'u', '.', 'w', 9, 0,
+ /* 8964 */ 'f', 't', 'i', 'n', 't', '_', 'u', '.', 'w', 9, 0,
+ /* 8975 */ 'd', 'i', 'v', '_', 'u', '.', 'w', 9, 0,
+ /* 8984 */ 'm', 'a', 'x', '_', 'u', '.', 'w', 9, 0,
+ /* 8993 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'w', 9, 0,
+ /* 9003 */ 'm', 's', 'u', 'b', 'v', '.', 'w', 9, 0,
+ /* 9012 */ 'm', 'a', 'd', 'd', 'v', '.', 'w', 9, 0,
+ /* 9021 */ 'p', 'c', 'k', 'e', 'v', '.', 'w', 9, 0,
+ /* 9030 */ 'i', 'l', 'v', 'e', 'v', '.', 'w', 9, 0,
+ /* 9039 */ 'f', 'd', 'i', 'v', '.', 'w', 9, 0,
+ /* 9047 */ 'm', 'u', 'l', 'v', '.', 'w', 9, 0,
+ /* 9055 */ 'e', 'x', 't', 'r', 'v', '.', 'w', 9, 0,
+ /* 9064 */ 'f', 'm', 'a', 'x', '.', 'w', 9, 0,
+ /* 9072 */ 'b', 'z', '.', 'w', 9, 0,
+ /* 9078 */ 'b', 'n', 'z', '.', 'w', 9, 0,
+ /* 9085 */ 'l', 'w', 9, 0,
+ /* 9089 */ 's', 'w', 9, 0,
+ /* 9093 */ 'l', 'h', 'x', 9, 0,
+ /* 9098 */ 'j', 'a', 'l', 'x', 9, 0,
+ /* 9104 */ 'l', 'b', 'u', 'x', 9, 0,
+ /* 9110 */ 'l', 'w', 'x', 9, 0,
+ /* 9115 */ 'b', 'g', 'e', 'z', 9, 0,
+ /* 9121 */ 'b', 'l', 'e', 'z', 9, 0,
+ /* 9127 */ 'b', 'n', 'e', 'z', 9, 0,
+ /* 9133 */ 's', 'e', 'l', 'n', 'e', 'z', 9, 0,
+ /* 9141 */ 'b', 't', 'n', 'e', 'z', 9, 0,
+ /* 9148 */ 'd', 'c', 'l', 'z', 9, 0,
+ /* 9154 */ 'b', 'e', 'q', 'z', 9, 0,
+ /* 9160 */ 's', 'e', 'l', 'e', 'q', 'z', 9, 0,
+ /* 9168 */ 'b', 't', 'e', 'q', 'z', 9, 0,
+ /* 9175 */ 'b', 'g', 't', 'z', 9, 0,
+ /* 9181 */ 'b', 'l', 't', 'z', 9, 0,
+ /* 9187 */ 'm', 'o', 'v', 'z', 9, 0,
+ /* 9193 */ 's', 'e', 'b', 9, 32, 0,
+ /* 9199 */ 'j', 'r', 'c', 9, 32, 0,
+ /* 9205 */ 's', 'e', 'h', 9, 32, 0,
+ /* 9211 */ 'd', 'd', 'i', 'v', 'u', 9, '$', 'z', 'e', 'r', 'o', ',', 32, 0,
+ /* 9225 */ 'd', 'd', 'i', 'v', 9, '$', 'z', 'e', 'r', 'o', ',', 32, 0,
+ /* 9238 */ 'a', 'd', 'd', 'i', 'u', 9, '$', 's', 'p', ',', 32, 0,
+ /* 9250 */ 'c', 'i', 'n', 's', '3', '2', 32, 0,
+ /* 9258 */ 'e', 'x', 't', 's', '3', '2', 32, 0,
+ /* 9266 */ 's', 'y', 'n', 'c', 32, 0,
+ /* 9272 */ 9, '.', 'w', 'o', 'r', 'd', 32, 0,
+ /* 9280 */ 'd', 'i', 'n', 's', 'm', 32, 0,
+ /* 9287 */ 'd', 'e', 'x', 't', 'm', 32, 0,
+ /* 9294 */ 'c', 'i', 'n', 's', 32, 0,
+ /* 9300 */ 'd', 'i', 'n', 's', 32, 0,
+ /* 9306 */ 'e', 'x', 't', 's', 32, 0,
+ /* 9312 */ 'd', 'e', 'x', 't', 32, 0,
+ /* 9318 */ 'd', 'i', 'n', 's', 'u', 32, 0,
+ /* 9325 */ 'd', 'e', 'x', 't', 'u', 32, 0,
+ /* 9332 */ 'b', 'c', '1', 'n', 'e', 'z', 32, 0,
+ /* 9340 */ 'b', 'c', '2', 'n', 'e', 'z', 32, 0,
+ /* 9348 */ 'b', 'c', '1', 'e', 'q', 'z', 32, 0,
+ /* 9356 */ 'b', 'c', '2', 'e', 'q', 'z', 32, 0,
+ /* 9364 */ 'c', '.', 0,
+ /* 9367 */ 'b', 'r', 'e', 'a', 'k', 32, '0', 0,
+ /* 9375 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
+ /* 9388 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
+ /* 9395 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
+ /* 9405 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
+ /* 9420 */ 'j', 'r', 'c', 9, 32, '$', 'r', 'a', 0,
+ /* 9429 */ 'j', 'r', 9, 32, '$', 'r', 'a', 0,
+ /* 9437 */ 'e', 'h', 'b', 0,
+ /* 9441 */ 'p', 'a', 'u', 's', 'e', 0,
+ /* 9447 */ 't', 'l', 'b', 'w', 'i', 0,
+ /* 9453 */ 'f', 'o', 'o', 0,
+ /* 9457 */ 't', 'l', 'b', 'p', 0,
+ /* 9462 */ 's', 's', 'n', 'o', 'p', 0,
+ /* 9468 */ 't', 'l', 'b', 'r', 0,
+ /* 9473 */ 't', 'l', 'b', 'w', 'r', 0,
+ /* 9479 */ 'd', 'e', 'r', 'e', 't', 0,
+ /* 9485 */ 'w', 'a', 'i', 't', 0,
+ };
+#endif
+
+ // Emit the opcode for the instruction.
+ uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)];
+ uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)];
+ uint64_t Bits = (Bits2 << 32) | Bits1;
+ // assert(Bits != 0 && "Cannot print this instruction.");
+#ifndef CAPSTONE_DIET
+ SStream_concat0(O, AsmStrs+(Bits & 16383)-1);
+#endif
+
+
+ // Fragment 0 encoded into 4 bits for 11 unique commands.
+ //printf("Frag-0: %"PRIu64"\n", (Bits >> 14) & 15);
+ switch ((Bits >> 14) & 15) {
+ default: // llvm_unreachable("Invalid command number.");
+ case 0:
+ // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, Break16, CONSTPOOL_EN...
+ return;
+ break;
+ case 1:
+ // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM...
+ printOperand(MI, 0, O);
+ break;
+ case 2:
+ // ADDIUS5_MM, CTC1, CTC1_MM, DAHI, DATI, DMTC1, MTC1, MTC1_MM, MTHI_DSP,...
+ printOperand(MI, 1, O);
+ SStream_concat0(O, ", ");
+ break;
+ case 3:
+ // AND16_MM, MTHC1_D32, MTHC1_D64, MTHC1_MM, OR16_MM, XOR16_MM
+ printOperand(MI, 2, O);
+ SStream_concat0(O, ", ");
+ break;
+ case 4:
+ // BREAK16_MM, SDBBP16_MM
+ printUnsignedImm8(MI, 0, O);
+ return;
+ break;
+ case 5:
+ // CACHE, CACHE_MM, CACHE_R6, PREF, PREF_MM, PREF_R6
+ printUnsignedImm(MI, 2, O);
+ SStream_concat0(O, ", ");
+ printMemOperand(MI, 0, O);
+ return;
+ break;
+ case 6:
+ // FCMP_D32, FCMP_D32_MM, FCMP_D64, FCMP_S32, FCMP_S32_MM
+ printFCCOperand(MI, 2, O);
+ break;
+ case 7:
+ // LWM16_MM, LWM32_MM, LWM_MM, MOVEP_MM, SWM16_MM, SWM32_MM, SWM_MM
+ printRegisterList(MI, 0, O);
+ SStream_concat0(O, ", ");
+ break;
+ case 8:
+ // LWP_MM, SWP_MM
+ printRegisterPair(MI, 0, O);
+ SStream_concat0(O, ", ");
+ printMemOperand(MI, 2, O);
+ return;
+ break;
+ case 9:
+ // SYNCI
+ printMemOperand(MI, 0, O);
+ return;
+ break;
+ case 10:
+ // SelBeqZ, SelBneZ, SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZ...
+ printOperand(MI, 3, O);
+ break;
+ }
+
+
+ // Fragment 1 encoded into 5 bits for 17 unique commands.
+ //printf("Frag-1: %"PRIu64"\n", (Bits >> 18) & 31);
+ switch ((Bits >> 18) & 31) {
+ default: // llvm_unreachable("Invalid command number.");
+ case 0:
+ // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM...
+ SStream_concat0(O, ", ");
+ break;
+ case 1:
+ // ADDIUS5_MM, DAHI, DATI, MOVEP_MM, MultRxRyRz16, MultuRxRyRz16, SltCCRx...
+ printOperand(MI, 2, O);
+ break;
+ case 2:
+ // ADDIUSP_MM, AddiuSpImmX16, B16_MM, BAL, BALC, BC, BPOSGE32, B_MM_Pseud...
+ return;
+ break;
+ case 3:
+ // AND16_MM, OR16_MM, XOR16_MM
+ printOperand(MI, 1, O);
+ return;
+ break;
+ case 4:
+ // AddiuRxPcImmX16
+ SStream_concat0(O, ", $pc, ");
+ printOperand(MI, 1, O);
+ return;
+ break;
+ case 5:
+ // AddiuSpImm16, Bimm16
+ SStream_concat0(O, " # 16 bit inst");
+ return;
+ break;
+ case 6:
+ // Bteqz16, Btnez16
+ SStream_concat0(O, " # 16 bit inst");
+ return;
+ break;
+ case 7:
+ // CTC1, CTC1_MM, DMTC1, MTC1, MTC1_MM, MTHC1_D32, MTHC1_D64, MTHC1_MM, M...
+ printOperand(MI, 0, O);
+ return;
+ break;
+ case 8:
+ // FCMP_D32, FCMP_D32_MM, FCMP_D64
+ SStream_concat0(O, ".d\t");
+ printOperand(MI, 0, O);
+ SStream_concat0(O, ", ");
+ printOperand(MI, 1, O);
+ return;
+ break;
+ case 9:
+ // FCMP_S32, FCMP_S32_MM
+ SStream_concat0(O, ".s\t");
+ printOperand(MI, 0, O);
+ SStream_concat0(O, ", ");
+ printOperand(MI, 1, O);
+ return;
+ break;
+ case 10:
+ // INSERT_B, INSERT_D, INSERT_H, INSERT_W, INSVE_B, INSVE_D, INSVE_H, INS...
+ SStream_concat0(O, "[");
+ break;
+ case 11:
+ // Jal16
+ SStream_concat0(O, "\n\tnop");
+ return;
+ break;
+ case 12:
+ // JalB16
+ SStream_concat0(O, "\t# branch\n\tnop");
+ return;
+ break;
+ case 13:
+ // LWM16_MM, LWM32_MM, LWM_MM, SWM16_MM, SWM32_MM, SWM_MM
+ printMemOperand(MI, 1, O);
+ return;
+ break;
+ case 14:
+ // LwConstant32
+ SStream_concat0(O, ", 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t");
+ printOperand(MI, 1, O);
+ SStream_concat0(O, "\n2:");
+ return;
+ break;
+ case 15:
+ // SC, SCD, SCD_R6, SC_MM, SC_R6
+ printMemOperand(MI, 2, O);
+ return;
+ break;
+ case 16:
+ // SelBeqZ, SelBneZ
+ SStream_concat0(O, ", .+4\n\t\n\tmove ");
+ printOperand(MI, 1, O);
+ SStream_concat0(O, ", ");
+ printOperand(MI, 2, O);
+ return;
+ break;
+ }
+
+
+ // Fragment 2 encoded into 4 bits for 12 unique commands.
+ //printf("Frag-2: %"PRIu64"\n", (Bits >> 23) & 15);
+ switch ((Bits >> 23) & 15) {
+ default: // llvm_unreachable("Invalid command number.");
+ case 0:
+ // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM...
+ printOperand(MI, 1, O);
+ break;
+ case 1:
+ // ADDIUS5_MM, DAHI, DATI
+ return;
+ break;
+ case 2:
+ // AddiuRxRxImm16, AddiuRxRxImmX16, AndRxRxRy16, BINSLI_B, BINSLI_D, BINS...
+ printOperand(MI, 2, O);
+ break;
+ case 3:
+ // AddiuRxRyOffMemX16, LEA_ADDiu, LEA_ADDiu64, LEA_ADDiu_MM
+ printMemOperandEA(MI, 1, O);
+ return;
+ break;
+ case 4:
+ // BBIT0, BBIT032, BBIT1, BBIT132, LUi, LUi64, LUi_MM, LoadAddr32Imm, Loa...
+ printUnsignedImm(MI, 1, O);
+ break;
+ case 5:
+ // INSERT_B, INSERT_D, INSERT_H, INSERT_W
+ printUnsignedImm(MI, 3, O);
+ SStream_concat0(O, "], ");
+ printOperand(MI, 2, O);
+ return;
+ break;
+ case 6:
+ // INSVE_B, INSVE_D, INSVE_H, INSVE_W
+ printUnsignedImm(MI, 2, O);
+ SStream_concat0(O, "], ");
+ printOperand(MI, 3, O);
+ SStream_concat0(O, "[");
+ printUnsignedImm(MI, 4, O);
+ SStream_concat0(O, "]");
+ return;
+ break;
+ case 7:
+ // LB, LB64, LBU16_MM, LB_MM, LBu, LBu64, LBu_MM, LD, LDC1, LDC164, LDC1_...
+ printMemOperand(MI, 1, O);
+ return;
+ break;
+ case 8:
+ // MOVEP_MM
+ SStream_concat0(O, ", ");
+ printOperand(MI, 3, O);
+ return;
+ break;
+ case 9:
+ // MultRxRyRz16, MultuRxRyRz16
+ SStream_concat0(O, "\n\tmflo\t");
+ printOperand(MI, 0, O);
+ return;
+ break;
+ case 10:
+ // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt...
+ printOperand(MI, 4, O);
+ break;
+ case 11:
+ // SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16, SltuRxRyRz...
+ SStream_concat0(O, "\n\tmove\t");
+ printOperand(MI, 0, O);
+ SStream_concat0(O, ", $t8");
+ return;
+ break;
+ }
+
+
+ // Fragment 3 encoded into 4 bits for 15 unique commands.
+ //printf("Frag-3: %"PRIu64"\n", (Bits >> 27) & 15);
+ switch ((Bits >> 27) & 15) {
+ default: // llvm_unreachable("Invalid command number.");
+ case 0:
+ // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM, ALU...
+ return;
+ break;
+ case 1:
+ // ADD, ADDIUR2_MM, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, AD...
+ SStream_concat0(O, ", ");
+ break;
+ case 2:
+ // AddiuRxRxImm16, LwRxPcTcp16
+ SStream_concat0(O, "\t# 16 bit inst");
+ return;
+ break;
+ case 3:
+ // BeqzRxImm16, BnezRxImm16
+ SStream_concat0(O, " # 16 bit inst");
+ return;
+ break;
+ case 4:
+ // BteqzT8CmpX16, BteqzT8CmpiX16, BteqzT8SltX16, BteqzT8SltiX16, BteqzT8S...
+ SStream_concat0(O, "\n\tbteqz\t");
+ printOperand(MI, 2, O);
+ return;
+ break;
+ case 5:
+ // BtnezT8CmpX16, BtnezT8CmpiX16, BtnezT8SltX16, BtnezT8SltiX16, BtnezT8S...
+ SStream_concat0(O, "\n\tbtnez\t");
+ printOperand(MI, 2, O);
+ return;
+ break;
+ case 6:
+ // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_D, COPY_U_H, ...
+ SStream_concat0(O, "[");
+ break;
+ case 7:
+ // CmpiRxImm16, LiRxImm16, SltiRxImm16, SltiuRxImm16
+ SStream_concat0(O, " \t# 16 bit inst");
+ return;
+ break;
+ case 8:
+ // DSLL64_32
+ SStream_concat0(O, ", 32");
+ return;
+ break;
+ case 9:
+ // GotPrologue16
+ SStream_concat0(O, "\n\taddiu\t");
+ printOperand(MI, 1, O);
+ SStream_concat0(O, ", $pc, ");
+ printOperand(MI, 3, O);
+ SStream_concat0(O, "\n ");
+ return;
+ break;
+ case 10:
+ // LBUX, LDXC1, LDXC164, LHX, LUXC1, LUXC164, LUXC1_MM, LWX, LWXC1, LWXC1...
+ SStream_concat0(O, "(");
+ printOperand(MI, 1, O);
+ SStream_concat0(O, ")");
+ return;
+ break;
+ case 11:
+ // LwRxSpImmX16, SwRxSpImmX16
+ SStream_concat0(O, " ( ");
+ printOperand(MI, 1, O);
+ SStream_concat0(O, " ); ");
+ return;
+ break;
+ case 12:
+ // SLL64_32, SLL64_64
+ SStream_concat0(O, ", 0");
+ return;
+ break;
+ case 13:
+ // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt...
+ SStream_concat0(O, "\n\tbteqz\t.+4\n\tmove ");
+ printOperand(MI, 1, O);
+ SStream_concat0(O, ", ");
+ printOperand(MI, 2, O);
+ return;
+ break;
+ case 14:
+ // SelTBtneZCmp, SelTBtneZCmpi, SelTBtneZSlt, SelTBtneZSlti, SelTBtneZSlt...
+ SStream_concat0(O, "\n\tbtnez\t.+4\n\tmove ");
+ printOperand(MI, 1, O);
+ SStream_concat0(O, ", ");
+ printOperand(MI, 2, O);
+ return;
+ break;
+ }
+
+
+ // Fragment 4 encoded into 3 bits for 5 unique commands.
+ //printf("Frag-4: %"PRIu64"\n", (Bits >> 31) & 7);
+ switch ((Bits >> 31) & 7) {
+ default: // llvm_unreachable("Invalid command number.");
+ case 0:
+ // ADD, ADDIUR2_MM, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, AD...
+ printOperand(MI, 2, O);
+ break;
+ case 1:
+ // ADDVI_B, ADDVI_D, ADDVI_H, ADDVI_W, ANDI_B, BCLRI_B, BCLRI_D, BCLRI_H,...
+ printUnsignedImm8(MI, 2, O);
+ break;
+ case 2:
+ // ANDi, ANDi64, ANDi_MM, APPEND, BALIGN, CINS, CINS32, DEXT, DEXTM, DEXT...
+ printUnsignedImm(MI, 2, O);
+ break;
+ case 3:
+ // BINSLI_B, BINSLI_D, BINSLI_H, BINSLI_W, BINSRI_B, BINSRI_D, BINSRI_H, ...
+ printUnsignedImm8(MI, 3, O);
+ break;
+ case 4:
+ // BINSL_B, BINSL_D, BINSL_H, BINSL_W, BINSR_B, BINSR_D, BINSR_H, BINSR_W...
+ printOperand(MI, 3, O);
+ break;
+ }
+
+
+ // Fragment 5 encoded into 2 bits for 3 unique commands.
+ //printf("Frag-5: %"PRIu64"\n", (Bits >> 34) & 3);
+ switch ((Bits >> 34) & 3) {
+ default: // llvm_unreachable("Invalid command number.");
+ case 0:
+ // ADD, ADDIUR2_MM, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, AD...
+ return;
+ break;
+ case 1:
+ // ALIGN, CINS, CINS32, DALIGN, DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, D...
+ SStream_concat0(O, ", ");
+ break;
+ case 2:
+ // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_D, COPY_U_H, ...
+ SStream_concat0(O, "]");
+ return;
+ break;
+ }
+
+
+ // Fragment 6 encoded into 1 bits for 2 unique commands.
+ //printf("Frag-6: %"PRIu64"\n", (Bits >> 36) & 1);
+ if ((Bits >> 36) & 1) {
+ // DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, EXT, EXT_MM, INS, INS_MM, MADD...
+ printOperand(MI, 3, O);
+ return;
+ } else {
+ // ALIGN, CINS, CINS32, DALIGN, DLSA, DLSA_R6, EXTS, EXTS32, LSA, LSA_R6
+ printUnsignedImm(MI, 3, O);
+ return;
+ }
+}
+
+
+/// getRegisterName - This method is automatically generated by tblgen
+/// from the register set description. This returns the assembler name
+/// for the specified register.
+static const char *getRegisterName(unsigned RegNo)
+{
+ // assert(RegNo && RegNo < 394 && "Invalid register number!");
+
+#ifndef CAPSTONE_DIET
+ static const char AsmStrs[] = {
+ /* 0 */ 'f', '1', '0', 0,
+ /* 4 */ 'w', '1', '0', 0,
+ /* 8 */ 'f', '2', '0', 0,
+ /* 12 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '0', 0,
+ /* 25 */ 'w', '2', '0', 0,
+ /* 29 */ 'f', '3', '0', 0,
+ /* 33 */ 'w', '3', '0', 0,
+ /* 37 */ 'a', '0', 0,
+ /* 40 */ 'a', 'c', '0', 0,
+ /* 44 */ 'f', 'c', 'c', '0', 0,
+ /* 49 */ 'f', '0', 0,
+ /* 52 */ 'k', '0', 0,
+ /* 55 */ 'm', 'p', 'l', '0', 0,
+ /* 60 */ 'p', '0', 0,
+ /* 63 */ 's', '0', 0,
+ /* 66 */ 't', '0', 0,
+ /* 69 */ 'v', '0', 0,
+ /* 72 */ 'w', '0', 0,
+ /* 75 */ 'f', '1', '1', 0,
+ /* 79 */ 'w', '1', '1', 0,
+ /* 83 */ 'f', '2', '1', 0,
+ /* 87 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '1', 0,
+ /* 100 */ 'w', '2', '1', 0,
+ /* 104 */ 'f', '3', '1', 0,
+ /* 108 */ 'w', '3', '1', 0,
+ /* 112 */ 'a', '1', 0,
+ /* 115 */ 'a', 'c', '1', 0,
+ /* 119 */ 'f', 'c', 'c', '1', 0,
+ /* 124 */ 'f', '1', 0,
+ /* 127 */ 'k', '1', 0,
+ /* 130 */ 'm', 'p', 'l', '1', 0,
+ /* 135 */ 'p', '1', 0,
+ /* 138 */ 's', '1', 0,
+ /* 141 */ 't', '1', 0,
+ /* 144 */ 'v', '1', 0,
+ /* 147 */ 'w', '1', 0,
+ /* 150 */ 'f', '1', '2', 0,
+ /* 154 */ 'w', '1', '2', 0,
+ /* 158 */ 'f', '2', '2', 0,
+ /* 162 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '2', 0,
+ /* 175 */ 'w', '2', '2', 0,
+ /* 179 */ 'a', '2', 0,
+ /* 182 */ 'a', 'c', '2', 0,
+ /* 186 */ 'f', 'c', 'c', '2', 0,
+ /* 191 */ 'f', '2', 0,
+ /* 194 */ 'm', 'p', 'l', '2', 0,
+ /* 199 */ 'p', '2', 0,
+ /* 202 */ 's', '2', 0,
+ /* 205 */ 't', '2', 0,
+ /* 208 */ 'w', '2', 0,
+ /* 211 */ 'f', '1', '3', 0,
+ /* 215 */ 'w', '1', '3', 0,
+ /* 219 */ 'f', '2', '3', 0,
+ /* 223 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '3', 0,
+ /* 236 */ 'w', '2', '3', 0,
+ /* 240 */ 'a', '3', 0,
+ /* 243 */ 'a', 'c', '3', 0,
+ /* 247 */ 'f', 'c', 'c', '3', 0,
+ /* 252 */ 'f', '3', 0,
+ /* 255 */ 's', '3', 0,
+ /* 258 */ 't', '3', 0,
+ /* 261 */ 'w', '3', 0,
+ /* 264 */ 'f', '1', '4', 0,
+ /* 268 */ 'w', '1', '4', 0,
+ /* 272 */ 'f', '2', '4', 0,
+ /* 276 */ 'w', '2', '4', 0,
+ /* 280 */ 'f', 'c', 'c', '4', 0,
+ /* 285 */ 'f', '4', 0,
+ /* 288 */ 's', '4', 0,
+ /* 291 */ 't', '4', 0,
+ /* 294 */ 'w', '4', 0,
+ /* 297 */ 'f', '1', '5', 0,
+ /* 301 */ 'w', '1', '5', 0,
+ /* 305 */ 'f', '2', '5', 0,
+ /* 309 */ 'w', '2', '5', 0,
+ /* 313 */ 'f', 'c', 'c', '5', 0,
+ /* 318 */ 'f', '5', 0,
+ /* 321 */ 's', '5', 0,
+ /* 324 */ 't', '5', 0,
+ /* 327 */ 'w', '5', 0,
+ /* 330 */ 'f', '1', '6', 0,
+ /* 334 */ 'w', '1', '6', 0,
+ /* 338 */ 'f', '2', '6', 0,
+ /* 342 */ 'w', '2', '6', 0,
+ /* 346 */ 'f', 'c', 'c', '6', 0,
+ /* 351 */ 'f', '6', 0,
+ /* 354 */ 's', '6', 0,
+ /* 357 */ 't', '6', 0,
+ /* 360 */ 'w', '6', 0,
+ /* 363 */ 'f', '1', '7', 0,
+ /* 367 */ 'w', '1', '7', 0,
+ /* 371 */ 'f', '2', '7', 0,
+ /* 375 */ 'w', '2', '7', 0,
+ /* 379 */ 'f', 'c', 'c', '7', 0,
+ /* 384 */ 'f', '7', 0,
+ /* 387 */ 's', '7', 0,
+ /* 390 */ 't', '7', 0,
+ /* 393 */ 'w', '7', 0,
+ /* 396 */ 'f', '1', '8', 0,
+ /* 400 */ 'w', '1', '8', 0,
+ /* 404 */ 'f', '2', '8', 0,
+ /* 408 */ 'w', '2', '8', 0,
+ /* 412 */ 'f', '8', 0,
+ /* 415 */ 't', '8', 0,
+ /* 418 */ 'w', '8', 0,
+ /* 421 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '1', '6', '_', '1', '9', 0,
+ /* 437 */ 'f', '1', '9', 0,
+ /* 441 */ 'w', '1', '9', 0,
+ /* 445 */ 'f', '2', '9', 0,
+ /* 449 */ 'w', '2', '9', 0,
+ /* 453 */ 'f', '9', 0,
+ /* 456 */ 't', '9', 0,
+ /* 459 */ 'w', '9', 0,
+ /* 462 */ 'D', 'S', 'P', 'E', 'F', 'I', 0,
+ /* 469 */ 'r', 'a', 0,
+ /* 472 */ 'h', 'w', 'r', '_', 'c', 'c', 0,
+ /* 479 */ 'p', 'c', 0,
+ /* 482 */ 'D', 'S', 'P', 'C', 'C', 'o', 'n', 'd', 0,
+ /* 491 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', 0,
+ /* 502 */ 'h', 'i', 0,
+ /* 505 */ 'h', 'w', 'r', '_', 'c', 'p', 'u', 'n', 'u', 'm', 0,
+ /* 516 */ 'l', 'o', 0,
+ /* 519 */ 'z', 'e', 'r', 'o', 0,
+ /* 524 */ 'h', 'w', 'r', '_', 's', 'y', 'n', 'c', 'i', '_', 's', 't', 'e', 'p', 0,
+ /* 539 */ 'f', 'p', 0,
+ /* 542 */ 'g', 'p', 0,
+ /* 545 */ 's', 'p', 0,
+ /* 548 */ 'h', 'w', 'r', '_', 'c', 'c', 'r', 'e', 's', 0,
+ /* 558 */ 'D', 'S', 'P', 'P', 'o', 's', 0,
+ /* 565 */ 'a', 't', 0,
+ /* 568 */ 'D', 'S', 'P', 'S', 'C', 'o', 'u', 'n', 't', 0,
+ /* 578 */ 'D', 'S', 'P', 'C', 'a', 'r', 'r', 'y', 0,
+ };
+
+ static const uint16_t RegAsmOffset[] = {
+ 565, 482, 578, 462, 491, 558, 568, 539, 542, 152, 77, 2, 332, 266,
+ 299, 213, 365, 479, 469, 545, 519, 37, 112, 179, 240, 40, 115, 182,
+ 243, 565, 45, 120, 187, 248, 281, 314, 347, 380, 2, 77, 152, 213,
+ 266, 299, 332, 365, 398, 435, 2, 77, 152, 213, 266, 299, 332, 365,
+ 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, 9, 84,
+ 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 1, 76, 151, 212,
+ 265, 298, 331, 364, 397, 434, 9, 84, 159, 220, 273, 306, 339, 372,
+ 405, 446, 30, 105, 49, 191, 285, 351, 412, 0, 150, 264, 330, 396,
+ 8, 158, 272, 338, 404, 29, 12, 87, 162, 223, 49, 124, 191, 252,
+ 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, 264, 297, 330, 363,
+ 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, 404, 445, 29, 104,
+ 44, 119, 186, 247, 280, 313, 346, 379, 2, 77, 152, 213, 266, 299,
+ 332, 365, 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434,
+ 9, 84, 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 539, 49,
+ 124, 191, 252, 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, 264,
+ 297, 330, 363, 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, 404,
+ 445, 29, 104, 542, 40, 115, 182, 243, 505, 524, 472, 548, 266, 299,
+ 332, 365, 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434,
+ 9, 84, 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 52, 127,
+ 40, 115, 182, 243, 55, 130, 194, 60, 135, 199, 469, 63, 138, 202,
+ 255, 288, 321, 354, 387, 545, 66, 141, 205, 258, 291, 324, 357, 390,
+ 415, 456, 69, 144, 72, 147, 208, 261, 294, 327, 360, 393, 418, 459,
+ 4, 79, 154, 215, 268, 301, 334, 367, 400, 441, 25, 100, 175, 236,
+ 276, 309, 342, 375, 408, 449, 33, 108, 519, 37, 112, 179, 240, 40,
+ 49, 124, 191, 252, 285, 318, 351, 384, 412, 453, 0, 75, 150, 211,
+ 264, 297, 330, 363, 396, 437, 8, 83, 158, 219, 272, 305, 338, 371,
+ 404, 445, 29, 104, 421, 502, 52, 127, 516, 63, 138, 202, 255, 288,
+ 321, 354, 387, 66, 141, 205, 258, 291, 324, 357, 390, 415, 456, 69,
+ 144,
+ };
+
+ //printf("==== RegNo = %u, id = %s\n", RegNo, AsmStrs+RegAsmOffset[RegNo-1]);
+ //int i;
+ //for (i = 0; i < sizeof(RegAsmOffset)/2; i++)
+ // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
+ //printf("-------------------------\n");
+ return AsmStrs+RegAsmOffset[RegNo-1];
+#else
+ return NULL;
+#endif
+}
+
+#ifdef PRINT_ALIAS_INSTR
+#undef PRINT_ALIAS_INSTR
+
+static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
+ unsigned PrintMethodIdx, SStream *OS)
+{
+}
+
+static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
+{
+ #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
+ const char *AsmString;
+ char *tmp, *AsmMnem, *AsmOps, *c;
+ int OpIdx, PrintMethodIdx;
+ MCRegisterInfo *MRI = (MCRegisterInfo *)info;
+ switch (MCInst_getOpcode(MI)) {
+ default: return NULL;
+ case Mips_ADDu:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) &&
+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == Mips_ZERO) {
+ // (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO)
+ AsmString = "move $\x01, $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_BC0F:
+ if (MCInst_getNumOperands(MI) == 2 &&
+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) {
+ // (BC0F CC0, brtarget:$offset)
+ AsmString = "bc0f $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_BC0FL:
+ if (MCInst_getNumOperands(MI) == 2 &&
+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) {
+ // (BC0FL CC0, brtarget:$offset)
+ AsmString = "bc0fl $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_BC0T:
+ if (MCInst_getNumOperands(MI) == 2 &&
+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) {
+ // (BC0T CC0, brtarget:$offset)
+ AsmString = "bc0t $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_BC0TL:
+ if (MCInst_getNumOperands(MI) == 2 &&
+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) {
+ // (BC0TL CC0, brtarget:$offset)
+ AsmString = "bc0tl $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_BC1F:
+ if (MCInst_getNumOperands(MI) == 2 &&
+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) {
+ // (BC1F FCC0, brtarget:$offset)
+ AsmString = "bc1f $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_BC1FL:
+ if (MCInst_getNumOperands(MI) == 2 &&
+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) {
+ // (BC1FL FCC0, brtarget:$offset)
+ AsmString = "bc1fl $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_BC1T:
+ if (MCInst_getNumOperands(MI) == 2 &&
+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) {
+ // (BC1T FCC0, brtarget:$offset)
+ AsmString = "bc1t $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_BC1TL:
+ if (MCInst_getNumOperands(MI) == 2 &&
+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) {
+ // (BC1TL FCC0, brtarget:$offset)
+ AsmString = "bc1tl $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_BC2F:
+ if (MCInst_getNumOperands(MI) == 2 &&
+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) {
+ // (BC2F CC0, brtarget:$offset)
+ AsmString = "bc2f $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_BC2FL:
+ if (MCInst_getNumOperands(MI) == 2 &&
+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) {
+ // (BC2FL CC0, brtarget:$offset)
+ AsmString = "bc2fl $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_BC2T:
+ if (MCInst_getNumOperands(MI) == 2 &&
+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) {
+ // (BC2T CC0, brtarget:$offset)
+ AsmString = "bc2t $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_BC2TL:
+ if (MCInst_getNumOperands(MI) == 2 &&
+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) {
+ // (BC2TL CC0, brtarget:$offset)
+ AsmString = "bc2tl $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_BC3F:
+ if (MCInst_getNumOperands(MI) == 2 &&
+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) {
+ // (BC3F CC0, brtarget:$offset)
+ AsmString = "bc3f $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_BC3FL:
+ if (MCInst_getNumOperands(MI) == 2 &&
+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) {
+ // (BC3FL CC0, brtarget:$offset)
+ AsmString = "bc3fl $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_BC3T:
+ if (MCInst_getNumOperands(MI) == 2 &&
+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) {
+ // (BC3T CC0, brtarget:$offset)
+ AsmString = "bc3t $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_BC3TL:
+ if (MCInst_getNumOperands(MI) == 2 &&
+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) {
+ // (BC3TL CC0, brtarget:$offset)
+ AsmString = "bc3tl $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_BREAK:
+ if (MCInst_getNumOperands(MI) == 2 &&
+ MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 &&
+ MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
+ // (BREAK 0, 0)
+ AsmString = "break";
+ break;
+ }
+ if (MCInst_getNumOperands(MI) == 2 &&
+ MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
+ // (BREAK uimm10:$imm, 0)
+ AsmString = "break $\x01";
+ break;
+ }
+ return NULL;
+ case Mips_DADDu:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ GETREGCLASS_CONTAIN(Mips_GPR64RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ GETREGCLASS_CONTAIN(Mips_GPR64RegClassID, 1) &&
+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == Mips_ZERO_64) {
+ // (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64)
+ AsmString = "move $\x01, $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_DI:
+ if (MCInst_getNumOperands(MI) == 1 &&
+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO) {
+ // (DI ZERO)
+ AsmString = "di";
+ break;
+ }
+ return NULL;
+ case Mips_EI:
+ if (MCInst_getNumOperands(MI) == 1 &&
+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO) {
+ // (EI ZERO)
+ AsmString = "ei";
+ break;
+ }
+ return NULL;
+ case Mips_JALR:
+ if (MCInst_getNumOperands(MI) == 2 &&
+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1)) {
+ // (JALR ZERO, GPR32Opnd:$rs)
+ AsmString = "jr $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_JALR64:
+ if (MCInst_getNumOperands(MI) == 2 &&
+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO_64 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ GETREGCLASS_CONTAIN(Mips_GPR64RegClassID, 1)) {
+ // (JALR64 ZERO_64, GPR64Opnd:$rs)
+ AsmString = "jr $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_JALR_HB:
+ if (MCInst_getNumOperands(MI) == 2 &&
+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_RA &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1)) {
+ // (JALR_HB RA, GPR32Opnd:$rs)
+ AsmString = "jalr.hb $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_MOVE16_MM:
+ if (MCInst_getNumOperands(MI) == 2 &&
+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO &&
+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO) {
+ // (MOVE16_MM ZERO, ZERO)
+ AsmString = "nop";
+ break;
+ }
+ return NULL;
+ case Mips_SDBBP:
+ if (MCInst_getNumOperands(MI) == 1 &&
+ MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) {
+ // (SDBBP 0)
+ AsmString = "sdbbp";
+ break;
+ }
+ return NULL;
+ case Mips_SDBBP_R6:
+ if (MCInst_getNumOperands(MI) == 1 &&
+ MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) {
+ // (SDBBP_R6 0)
+ AsmString = "sdbbp";
+ break;
+ }
+ return NULL;
+ case Mips_SLL:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO &&
+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (SLL ZERO, ZERO, 0)
+ AsmString = "nop";
+ break;
+ }
+ return NULL;
+ case Mips_SLL_MM:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO &&
+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (SLL_MM ZERO, ZERO, 0)
+ AsmString = "nop";
+ break;
+ }
+ return NULL;
+ case Mips_SUB:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) &&
+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 2)) {
+ // (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs)
+ AsmString = "neg $\x01, $\x03";
+ break;
+ }
+ return NULL;
+ case Mips_SUBu:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) &&
+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO &&
+ MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 2)) {
+ // (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs)
+ AsmString = "negu $\x01, $\x03";
+ break;
+ }
+ return NULL;
+ case Mips_SYNC:
+ if (MCInst_getNumOperands(MI) == 1 &&
+ MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) {
+ // (SYNC 0)
+ AsmString = "sync";
+ break;
+ }
+ return NULL;
+ case Mips_SYSCALL:
+ if (MCInst_getNumOperands(MI) == 1 &&
+ MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) {
+ // (SYSCALL 0)
+ AsmString = "syscall";
+ break;
+ }
+ return NULL;
+ case Mips_TEQ:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0)
+ AsmString = "teq $\x01, $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_TGE:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0)
+ AsmString = "tge $\x01, $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_TGEU:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0)
+ AsmString = "tgeu $\x01, $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_TLT:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0)
+ AsmString = "tlt $\x01, $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_TLTU:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0)
+ AsmString = "tltu $\x01, $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_TNE:
+ if (MCInst_getNumOperands(MI) == 3 &&
+ MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) &&
+ MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) &&
+ MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
+ // (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0)
+ AsmString = "tne $\x01, $\x02";
+ break;
+ }
+ return NULL;
+ case Mips_WAIT_MM:
+ if (MCInst_getNumOperands(MI) == 1 &&
+ MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) {
+ // (WAIT_MM 0)
+ AsmString = "wait";
+ break;
+ }
+ return NULL;
+ }
+
+ tmp = cs_strdup(AsmString);
+ AsmMnem = tmp;
+ for(AsmOps = tmp; *AsmOps; AsmOps++) {
+ if (*AsmOps == ' ' || *AsmOps == '\t') {
+ *AsmOps = '\0';
+ AsmOps++;
+ break;
+ }
+ }
+ SStream_concat0(OS, AsmMnem);
+ if (*AsmOps) {
+ SStream_concat0(OS, "\t");
+ for (c = AsmOps; *c; c++) {
+ if (*c == '$') {
+ c += 1;
+ if (*c == (char)0xff) {
+ c += 1;
+ OpIdx = *c - 1;
+ c += 1;
+ PrintMethodIdx = *c - 1;
+ printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
+ } else
+ printOperand(MI, *c - 1, OS);
+ } else {
+ SStream_concat(OS, "%c", *c);
+ }
+ }
+ }
+ return tmp;
+}
+
+#endif // PRINT_ALIAS_INSTR
diff --git a/capstone/arch/Mips/MipsGenDisassemblerTables.inc b/capstone/arch/Mips/MipsGenDisassemblerTables.inc
new file mode 100644
index 000000000..e926f7788
--- /dev/null
+++ b/capstone/arch/Mips/MipsGenDisassemblerTables.inc
@@ -0,0 +1,6942 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* * Mips Disassembler *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#include "../../MCInst.h"
+#include "../../LEB128.h"
+
+// Helper function for extracting fields from encoded instructions.
+#define FieldFromInstruction(fname, InsnType) \
+static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
+{ \
+ InsnType fieldMask; \
+ if (numBits == sizeof(InsnType)*8) \
+ fieldMask = (InsnType)(-1LL); \
+ else \
+ fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
+ return (insn & fieldMask) >> startBit; \
+}
+
+static const uint8_t DecoderTableCOP3_32[] = {
+/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ...
+/* 3 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 15
+/* 7 */ MCD_OPC_CheckPredicate, 1, 40, 0, // Skip to: 51
+/* 11 */ MCD_OPC_Decode, 220, 7, 10, // Opcode: LWC3
+/* 15 */ MCD_OPC_FilterValue, 55, 8, 0, // Skip to: 27
+/* 19 */ MCD_OPC_CheckPredicate, 2, 28, 0, // Skip to: 51
+/* 23 */ MCD_OPC_Decode, 167, 7, 10, // Opcode: LDC3
+/* 27 */ MCD_OPC_FilterValue, 59, 8, 0, // Skip to: 39
+/* 31 */ MCD_OPC_CheckPredicate, 1, 16, 0, // Skip to: 51
+/* 35 */ MCD_OPC_Decode, 242, 12, 10, // Opcode: SWC3
+/* 39 */ MCD_OPC_FilterValue, 63, 8, 0, // Skip to: 51
+/* 43 */ MCD_OPC_CheckPredicate, 2, 4, 0, // Skip to: 51
+/* 47 */ MCD_OPC_Decode, 161, 11, 10, // Opcode: SDC3
+/* 51 */ MCD_OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableMicroMips16[] = {
+/* 0 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ...
+/* 3 */ MCD_OPC_FilterValue, 1, 26, 0, // Skip to: 33
+/* 7 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ...
+/* 10 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 21
+/* 14 */ MCD_OPC_CheckPredicate, 3, 19, 2, // Skip to: 549
+/* 18 */ MCD_OPC_Decode, 52, 11, // Opcode: ADDU16_MM
+/* 21 */ MCD_OPC_FilterValue, 1, 12, 2, // Skip to: 549
+/* 25 */ MCD_OPC_CheckPredicate, 3, 8, 2, // Skip to: 549
+/* 29 */ MCD_OPC_Decode, 214, 12, 11, // Opcode: SUBU16_MM
+/* 33 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 45
+/* 37 */ MCD_OPC_CheckPredicate, 3, 252, 1, // Skip to: 549
+/* 41 */ MCD_OPC_Decode, 155, 7, 12, // Opcode: LBU16_MM
+/* 45 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 57
+/* 49 */ MCD_OPC_CheckPredicate, 3, 240, 1, // Skip to: 549
+/* 53 */ MCD_OPC_Decode, 233, 8, 13, // Opcode: MOVE16_MM
+/* 57 */ MCD_OPC_FilterValue, 9, 27, 0, // Skip to: 88
+/* 61 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ...
+/* 64 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 76
+/* 68 */ MCD_OPC_CheckPredicate, 3, 221, 1, // Skip to: 549
+/* 72 */ MCD_OPC_Decode, 226, 11, 14, // Opcode: SLL16_MM
+/* 76 */ MCD_OPC_FilterValue, 1, 213, 1, // Skip to: 549
+/* 80 */ MCD_OPC_CheckPredicate, 3, 209, 1, // Skip to: 549
+/* 84 */ MCD_OPC_Decode, 160, 12, 14, // Opcode: SRL16_MM
+/* 88 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 100
+/* 92 */ MCD_OPC_CheckPredicate, 3, 197, 1, // Skip to: 549
+/* 96 */ MCD_OPC_Decode, 186, 7, 12, // Opcode: LHU16_MM
+/* 100 */ MCD_OPC_FilterValue, 11, 7, 0, // Skip to: 111
+/* 104 */ MCD_OPC_CheckPredicate, 3, 185, 1, // Skip to: 549
+/* 108 */ MCD_OPC_Decode, 86, 15, // Opcode: ANDI16_MM
+/* 111 */ MCD_OPC_FilterValue, 17, 226, 0, // Skip to: 341
+/* 115 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ...
+/* 118 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 130
+/* 122 */ MCD_OPC_CheckPredicate, 3, 167, 1, // Skip to: 549
+/* 126 */ MCD_OPC_Decode, 130, 10, 16, // Opcode: NOT16_MM
+/* 130 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 142
+/* 134 */ MCD_OPC_CheckPredicate, 3, 155, 1, // Skip to: 549
+/* 138 */ MCD_OPC_Decode, 237, 13, 17, // Opcode: XOR16_MM
+/* 142 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 153
+/* 146 */ MCD_OPC_CheckPredicate, 3, 143, 1, // Skip to: 549
+/* 150 */ MCD_OPC_Decode, 84, 17, // Opcode: AND16_MM
+/* 153 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 165
+/* 157 */ MCD_OPC_CheckPredicate, 3, 132, 1, // Skip to: 549
+/* 161 */ MCD_OPC_Decode, 134, 10, 17, // Opcode: OR16_MM
+/* 165 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 177
+/* 169 */ MCD_OPC_CheckPredicate, 3, 120, 1, // Skip to: 549
+/* 173 */ MCD_OPC_Decode, 225, 7, 18, // Opcode: LWM16_MM
+/* 177 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 189
+/* 181 */ MCD_OPC_CheckPredicate, 3, 108, 1, // Skip to: 549
+/* 185 */ MCD_OPC_Decode, 246, 12, 18, // Opcode: SWM16_MM
+/* 189 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 220
+/* 193 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ...
+/* 196 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 208
+/* 200 */ MCD_OPC_CheckPredicate, 3, 89, 1, // Skip to: 549
+/* 204 */ MCD_OPC_Decode, 137, 7, 19, // Opcode: JR16_MM
+/* 208 */ MCD_OPC_FilterValue, 1, 81, 1, // Skip to: 549
+/* 212 */ MCD_OPC_CheckPredicate, 3, 77, 1, // Skip to: 549
+/* 216 */ MCD_OPC_Decode, 140, 7, 19, // Opcode: JRC16_MM
+/* 220 */ MCD_OPC_FilterValue, 7, 27, 0, // Skip to: 251
+/* 224 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ...
+/* 227 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 239
+/* 231 */ MCD_OPC_CheckPredicate, 3, 58, 1, // Skip to: 549
+/* 235 */ MCD_OPC_Decode, 250, 6, 19, // Opcode: JALR16_MM
+/* 239 */ MCD_OPC_FilterValue, 1, 50, 1, // Skip to: 549
+/* 243 */ MCD_OPC_CheckPredicate, 3, 46, 1, // Skip to: 549
+/* 247 */ MCD_OPC_Decode, 254, 6, 19, // Opcode: JALRS16_MM
+/* 251 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 269
+/* 255 */ MCD_OPC_CheckPredicate, 3, 34, 1, // Skip to: 549
+/* 259 */ MCD_OPC_CheckField, 5, 1, 0, 28, 1, // Skip to: 549
+/* 265 */ MCD_OPC_Decode, 187, 8, 19, // Opcode: MFHI16_MM
+/* 269 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 287
+/* 273 */ MCD_OPC_CheckPredicate, 3, 16, 1, // Skip to: 549
+/* 277 */ MCD_OPC_CheckField, 5, 1, 0, 10, 1, // Skip to: 549
+/* 283 */ MCD_OPC_Decode, 192, 8, 19, // Opcode: MFLO16_MM
+/* 287 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 305
+/* 291 */ MCD_OPC_CheckPredicate, 3, 254, 0, // Skip to: 549
+/* 295 */ MCD_OPC_CheckField, 4, 2, 0, 248, 0, // Skip to: 549
+/* 301 */ MCD_OPC_Decode, 172, 2, 20, // Opcode: BREAK16_MM
+/* 305 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 323
+/* 309 */ MCD_OPC_CheckPredicate, 3, 236, 0, // Skip to: 549
+/* 313 */ MCD_OPC_CheckField, 4, 2, 0, 230, 0, // Skip to: 549
+/* 319 */ MCD_OPC_Decode, 153, 11, 20, // Opcode: SDBBP16_MM
+/* 323 */ MCD_OPC_FilterValue, 12, 222, 0, // Skip to: 549
+/* 327 */ MCD_OPC_CheckPredicate, 3, 218, 0, // Skip to: 549
+/* 331 */ MCD_OPC_CheckField, 5, 1, 0, 212, 0, // Skip to: 549
+/* 337 */ MCD_OPC_Decode, 139, 7, 21, // Opcode: JRADDIUSP
+/* 341 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 353
+/* 345 */ MCD_OPC_CheckPredicate, 3, 200, 0, // Skip to: 549
+/* 349 */ MCD_OPC_Decode, 233, 7, 22, // Opcode: LWSP_MM
+/* 353 */ MCD_OPC_FilterValue, 19, 25, 0, // Skip to: 382
+/* 357 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ...
+/* 360 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 371
+/* 364 */ MCD_OPC_CheckPredicate, 3, 181, 0, // Skip to: 549
+/* 368 */ MCD_OPC_Decode, 30, 23, // Opcode: ADDIUS5_MM
+/* 371 */ MCD_OPC_FilterValue, 1, 174, 0, // Skip to: 549
+/* 375 */ MCD_OPC_CheckPredicate, 3, 170, 0, // Skip to: 549
+/* 379 */ MCD_OPC_Decode, 31, 24, // Opcode: ADDIUSP_MM
+/* 382 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 394
+/* 386 */ MCD_OPC_CheckPredicate, 3, 159, 0, // Skip to: 549
+/* 390 */ MCD_OPC_Decode, 221, 7, 25, // Opcode: LWGP_MM
+/* 394 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 406
+/* 398 */ MCD_OPC_CheckPredicate, 3, 147, 0, // Skip to: 549
+/* 402 */ MCD_OPC_Decode, 214, 7, 12, // Opcode: LW16_MM
+/* 406 */ MCD_OPC_FilterValue, 27, 25, 0, // Skip to: 435
+/* 410 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ...
+/* 413 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 424
+/* 417 */ MCD_OPC_CheckPredicate, 3, 128, 0, // Skip to: 549
+/* 421 */ MCD_OPC_Decode, 29, 26, // Opcode: ADDIUR2_MM
+/* 424 */ MCD_OPC_FilterValue, 1, 121, 0, // Skip to: 549
+/* 428 */ MCD_OPC_CheckPredicate, 3, 117, 0, // Skip to: 549
+/* 432 */ MCD_OPC_Decode, 28, 27, // Opcode: ADDIUR1SP_MM
+/* 435 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 453
+/* 439 */ MCD_OPC_CheckPredicate, 3, 106, 0, // Skip to: 549
+/* 443 */ MCD_OPC_CheckField, 0, 1, 0, 100, 0, // Skip to: 549
+/* 449 */ MCD_OPC_Decode, 234, 8, 28, // Opcode: MOVEP_MM
+/* 453 */ MCD_OPC_FilterValue, 34, 8, 0, // Skip to: 465
+/* 457 */ MCD_OPC_CheckPredicate, 3, 88, 0, // Skip to: 549
+/* 461 */ MCD_OPC_Decode, 143, 11, 12, // Opcode: SB16_MM
+/* 465 */ MCD_OPC_FilterValue, 35, 8, 0, // Skip to: 477
+/* 469 */ MCD_OPC_CheckPredicate, 3, 76, 0, // Skip to: 549
+/* 473 */ MCD_OPC_Decode, 210, 1, 29, // Opcode: BEQZ16_MM
+/* 477 */ MCD_OPC_FilterValue, 42, 8, 0, // Skip to: 489
+/* 481 */ MCD_OPC_CheckPredicate, 3, 64, 0, // Skip to: 549
+/* 485 */ MCD_OPC_Decode, 187, 11, 12, // Opcode: SH16_MM
+/* 489 */ MCD_OPC_FilterValue, 43, 8, 0, // Skip to: 501
+/* 493 */ MCD_OPC_CheckPredicate, 3, 52, 0, // Skip to: 549
+/* 497 */ MCD_OPC_Decode, 157, 2, 29, // Opcode: BNEZ16_MM
+/* 501 */ MCD_OPC_FilterValue, 50, 8, 0, // Skip to: 513
+/* 505 */ MCD_OPC_CheckPredicate, 3, 40, 0, // Skip to: 549
+/* 509 */ MCD_OPC_Decode, 253, 12, 22, // Opcode: SWSP_MM
+/* 513 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 525
+/* 517 */ MCD_OPC_CheckPredicate, 4, 28, 0, // Skip to: 549
+/* 521 */ MCD_OPC_Decode, 165, 1, 30, // Opcode: B16_MM
+/* 525 */ MCD_OPC_FilterValue, 58, 8, 0, // Skip to: 537
+/* 529 */ MCD_OPC_CheckPredicate, 3, 16, 0, // Skip to: 549
+/* 533 */ MCD_OPC_Decode, 236, 12, 12, // Opcode: SW16_MM
+/* 537 */ MCD_OPC_FilterValue, 59, 8, 0, // Skip to: 549
+/* 541 */ MCD_OPC_CheckPredicate, 3, 4, 0, // Skip to: 549
+/* 545 */ MCD_OPC_Decode, 192, 7, 31, // Opcode: LI16_MM
+/* 549 */ MCD_OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableMicroMips32[] = {
+/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ...
+/* 3 */ MCD_OPC_FilterValue, 0, 189, 3, // Skip to: 964
+/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 10 */ MCD_OPC_FilterValue, 0, 90, 0, // Skip to: 104
+/* 14 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 17 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 68
+/* 21 */ MCD_OPC_ExtractField, 11, 15, // Inst{25-11} ...
+/* 24 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 36
+/* 28 */ MCD_OPC_CheckPredicate, 3, 28, 0, // Skip to: 60
+/* 32 */ MCD_OPC_Decode, 181, 12, 0, // Opcode: SSNOP_MM
+/* 36 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 48
+/* 40 */ MCD_OPC_CheckPredicate, 3, 16, 0, // Skip to: 60
+/* 44 */ MCD_OPC_Decode, 140, 5, 0, // Opcode: EHB_MM
+/* 48 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 60
+/* 52 */ MCD_OPC_CheckPredicate, 3, 4, 0, // Skip to: 60
+/* 56 */ MCD_OPC_Decode, 148, 10, 0, // Opcode: PAUSE_MM
+/* 60 */ MCD_OPC_CheckPredicate, 3, 38, 6, // Skip to: 1638
+/* 64 */ MCD_OPC_Decode, 238, 11, 32, // Opcode: SLL_MM
+/* 68 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 80
+/* 72 */ MCD_OPC_CheckPredicate, 3, 26, 6, // Skip to: 1638
+/* 76 */ MCD_OPC_Decode, 178, 12, 32, // Opcode: SRL_MM
+/* 80 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 92
+/* 84 */ MCD_OPC_CheckPredicate, 3, 14, 6, // Skip to: 1638
+/* 88 */ MCD_OPC_Decode, 157, 12, 32, // Opcode: SRA_MM
+/* 92 */ MCD_OPC_FilterValue, 3, 6, 6, // Skip to: 1638
+/* 96 */ MCD_OPC_CheckPredicate, 3, 2, 6, // Skip to: 1638
+/* 100 */ MCD_OPC_Decode, 250, 10, 32, // Opcode: ROTR_MM
+/* 104 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 116
+/* 108 */ MCD_OPC_CheckPredicate, 3, 246, 5, // Skip to: 1638
+/* 112 */ MCD_OPC_Decode, 173, 2, 33, // Opcode: BREAK_MM
+/* 116 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 128
+/* 120 */ MCD_OPC_CheckPredicate, 3, 234, 5, // Skip to: 1638
+/* 124 */ MCD_OPC_Decode, 246, 6, 34, // Opcode: INS_MM
+/* 128 */ MCD_OPC_FilterValue, 16, 180, 0, // Skip to: 312
+/* 132 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 135 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 147
+/* 139 */ MCD_OPC_CheckPredicate, 3, 215, 5, // Skip to: 1638
+/* 143 */ MCD_OPC_Decode, 234, 11, 35, // Opcode: SLLV_MM
+/* 147 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 159
+/* 151 */ MCD_OPC_CheckPredicate, 3, 203, 5, // Skip to: 1638
+/* 155 */ MCD_OPC_Decode, 174, 12, 35, // Opcode: SRLV_MM
+/* 159 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 171
+/* 163 */ MCD_OPC_CheckPredicate, 3, 191, 5, // Skip to: 1638
+/* 167 */ MCD_OPC_Decode, 153, 12, 35, // Opcode: SRAV_MM
+/* 171 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 183
+/* 175 */ MCD_OPC_CheckPredicate, 3, 179, 5, // Skip to: 1638
+/* 179 */ MCD_OPC_Decode, 249, 10, 35, // Opcode: ROTRV_MM
+/* 183 */ MCD_OPC_FilterValue, 4, 7, 0, // Skip to: 194
+/* 187 */ MCD_OPC_CheckPredicate, 3, 167, 5, // Skip to: 1638
+/* 191 */ MCD_OPC_Decode, 72, 36, // Opcode: ADD_MM
+/* 194 */ MCD_OPC_FilterValue, 5, 7, 0, // Skip to: 205
+/* 198 */ MCD_OPC_CheckPredicate, 3, 156, 5, // Skip to: 1638
+/* 202 */ MCD_OPC_Decode, 78, 36, // Opcode: ADDu_MM
+/* 205 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 217
+/* 209 */ MCD_OPC_CheckPredicate, 3, 145, 5, // Skip to: 1638
+/* 213 */ MCD_OPC_Decode, 229, 12, 36, // Opcode: SUB_MM
+/* 217 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 229
+/* 221 */ MCD_OPC_CheckPredicate, 3, 133, 5, // Skip to: 1638
+/* 225 */ MCD_OPC_Decode, 231, 12, 36, // Opcode: SUBu_MM
+/* 229 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 241
+/* 233 */ MCD_OPC_CheckPredicate, 3, 121, 5, // Skip to: 1638
+/* 237 */ MCD_OPC_Decode, 217, 9, 36, // Opcode: MUL_MM
+/* 241 */ MCD_OPC_FilterValue, 9, 7, 0, // Skip to: 252
+/* 245 */ MCD_OPC_CheckPredicate, 3, 109, 5, // Skip to: 1638
+/* 249 */ MCD_OPC_Decode, 88, 36, // Opcode: AND_MM
+/* 252 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 264
+/* 256 */ MCD_OPC_CheckPredicate, 3, 98, 5, // Skip to: 1638
+/* 260 */ MCD_OPC_Decode, 137, 10, 36, // Opcode: OR_MM
+/* 264 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 276
+/* 268 */ MCD_OPC_CheckPredicate, 3, 86, 5, // Skip to: 1638
+/* 272 */ MCD_OPC_Decode, 253, 9, 36, // Opcode: NOR_MM
+/* 276 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 288
+/* 280 */ MCD_OPC_CheckPredicate, 3, 74, 5, // Skip to: 1638
+/* 284 */ MCD_OPC_Decode, 240, 13, 36, // Opcode: XOR_MM
+/* 288 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 300
+/* 292 */ MCD_OPC_CheckPredicate, 3, 62, 5, // Skip to: 1638
+/* 296 */ MCD_OPC_Decode, 242, 11, 36, // Opcode: SLT_MM
+/* 300 */ MCD_OPC_FilterValue, 14, 54, 5, // Skip to: 1638
+/* 304 */ MCD_OPC_CheckPredicate, 3, 50, 5, // Skip to: 1638
+/* 308 */ MCD_OPC_Decode, 251, 11, 36, // Opcode: SLTu_MM
+/* 312 */ MCD_OPC_FilterValue, 24, 39, 0, // Skip to: 355
+/* 316 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 319 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 331
+/* 323 */ MCD_OPC_CheckPredicate, 3, 31, 5, // Skip to: 1638
+/* 327 */ MCD_OPC_Decode, 253, 8, 37, // Opcode: MOVN_I_MM
+/* 331 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 343
+/* 335 */ MCD_OPC_CheckPredicate, 3, 19, 5, // Skip to: 1638
+/* 339 */ MCD_OPC_Decode, 145, 9, 37, // Opcode: MOVZ_I_MM
+/* 343 */ MCD_OPC_FilterValue, 4, 11, 5, // Skip to: 1638
+/* 347 */ MCD_OPC_CheckPredicate, 3, 7, 5, // Skip to: 1638
+/* 351 */ MCD_OPC_Decode, 239, 7, 38, // Opcode: LWXS_MM
+/* 355 */ MCD_OPC_FilterValue, 44, 8, 0, // Skip to: 367
+/* 359 */ MCD_OPC_CheckPredicate, 3, 251, 4, // Skip to: 1638
+/* 363 */ MCD_OPC_Decode, 160, 5, 39, // Opcode: EXT_MM
+/* 367 */ MCD_OPC_FilterValue, 60, 243, 4, // Skip to: 1638
+/* 371 */ MCD_OPC_ExtractField, 6, 6, // Inst{11-6} ...
+/* 374 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 386
+/* 378 */ MCD_OPC_CheckPredicate, 3, 232, 4, // Skip to: 1638
+/* 382 */ MCD_OPC_Decode, 185, 13, 40, // Opcode: TEQ_MM
+/* 386 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 398
+/* 390 */ MCD_OPC_CheckPredicate, 3, 220, 4, // Skip to: 1638
+/* 394 */ MCD_OPC_Decode, 193, 13, 40, // Opcode: TGE_MM
+/* 398 */ MCD_OPC_FilterValue, 13, 123, 0, // Skip to: 525
+/* 402 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ...
+/* 405 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 423
+/* 409 */ MCD_OPC_CheckPredicate, 3, 201, 4, // Skip to: 1638
+/* 413 */ MCD_OPC_CheckField, 16, 10, 0, 195, 4, // Skip to: 1638
+/* 419 */ MCD_OPC_Decode, 195, 13, 0, // Opcode: TLBP_MM
+/* 423 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 441
+/* 427 */ MCD_OPC_CheckPredicate, 3, 183, 4, // Skip to: 1638
+/* 431 */ MCD_OPC_CheckField, 16, 10, 0, 177, 4, // Skip to: 1638
+/* 437 */ MCD_OPC_Decode, 197, 13, 0, // Opcode: TLBR_MM
+/* 441 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 459
+/* 445 */ MCD_OPC_CheckPredicate, 3, 165, 4, // Skip to: 1638
+/* 449 */ MCD_OPC_CheckField, 16, 10, 0, 159, 4, // Skip to: 1638
+/* 455 */ MCD_OPC_Decode, 199, 13, 0, // Opcode: TLBWI_MM
+/* 459 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 477
+/* 463 */ MCD_OPC_CheckPredicate, 3, 147, 4, // Skip to: 1638
+/* 467 */ MCD_OPC_CheckField, 16, 10, 0, 141, 4, // Skip to: 1638
+/* 473 */ MCD_OPC_Decode, 201, 13, 0, // Opcode: TLBWR_MM
+/* 477 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 489
+/* 481 */ MCD_OPC_CheckPredicate, 3, 129, 4, // Skip to: 1638
+/* 485 */ MCD_OPC_Decode, 232, 13, 41, // Opcode: WAIT_MM
+/* 489 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 507
+/* 493 */ MCD_OPC_CheckPredicate, 3, 117, 4, // Skip to: 1638
+/* 497 */ MCD_OPC_CheckField, 16, 10, 0, 111, 4, // Skip to: 1638
+/* 503 */ MCD_OPC_Decode, 175, 4, 0, // Opcode: DERET_MM
+/* 507 */ MCD_OPC_FilterValue, 15, 103, 4, // Skip to: 1638
+/* 511 */ MCD_OPC_CheckPredicate, 3, 99, 4, // Skip to: 1638
+/* 515 */ MCD_OPC_CheckField, 16, 10, 0, 93, 4, // Skip to: 1638
+/* 521 */ MCD_OPC_Decode, 144, 5, 0, // Opcode: ERET_MM
+/* 525 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 537
+/* 529 */ MCD_OPC_CheckPredicate, 3, 81, 4, // Skip to: 1638
+/* 533 */ MCD_OPC_Decode, 192, 13, 40, // Opcode: TGEU_MM
+/* 537 */ MCD_OPC_FilterValue, 29, 39, 0, // Skip to: 580
+/* 541 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ...
+/* 544 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 562
+/* 548 */ MCD_OPC_CheckPredicate, 3, 62, 4, // Skip to: 1638
+/* 552 */ MCD_OPC_CheckField, 21, 5, 0, 56, 4, // Skip to: 1638
+/* 558 */ MCD_OPC_Decode, 193, 4, 42, // Opcode: DI_MM
+/* 562 */ MCD_OPC_FilterValue, 5, 48, 4, // Skip to: 1638
+/* 566 */ MCD_OPC_CheckPredicate, 3, 44, 4, // Skip to: 1638
+/* 570 */ MCD_OPC_CheckField, 21, 5, 0, 38, 4, // Skip to: 1638
+/* 576 */ MCD_OPC_Decode, 142, 5, 42, // Opcode: EI_MM
+/* 580 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 592
+/* 584 */ MCD_OPC_CheckPredicate, 3, 26, 4, // Skip to: 1638
+/* 588 */ MCD_OPC_Decode, 208, 13, 40, // Opcode: TLT_MM
+/* 592 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 604
+/* 596 */ MCD_OPC_CheckPredicate, 3, 14, 4, // Skip to: 1638
+/* 600 */ MCD_OPC_Decode, 207, 13, 40, // Opcode: TLTU_MM
+/* 604 */ MCD_OPC_FilterValue, 44, 171, 0, // Skip to: 779
+/* 608 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ...
+/* 611 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 623
+/* 615 */ MCD_OPC_CheckPredicate, 3, 251, 3, // Skip to: 1638
+/* 619 */ MCD_OPC_Decode, 170, 11, 43, // Opcode: SEB_MM
+/* 623 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 635
+/* 627 */ MCD_OPC_CheckPredicate, 3, 239, 3, // Skip to: 1638
+/* 631 */ MCD_OPC_Decode, 173, 11, 43, // Opcode: SEH_MM
+/* 635 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 647
+/* 639 */ MCD_OPC_CheckPredicate, 3, 227, 3, // Skip to: 1638
+/* 643 */ MCD_OPC_Decode, 134, 3, 43, // Opcode: CLO_MM
+/* 647 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 659
+/* 651 */ MCD_OPC_CheckPredicate, 3, 215, 3, // Skip to: 1638
+/* 655 */ MCD_OPC_Decode, 153, 3, 43, // Opcode: CLZ_MM
+/* 659 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 671
+/* 663 */ MCD_OPC_CheckPredicate, 3, 203, 3, // Skip to: 1638
+/* 667 */ MCD_OPC_Decode, 240, 10, 44, // Opcode: RDHWR_MM
+/* 671 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 683
+/* 675 */ MCD_OPC_CheckPredicate, 3, 191, 3, // Skip to: 1638
+/* 679 */ MCD_OPC_Decode, 235, 13, 43, // Opcode: WSBH_MM
+/* 683 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 695
+/* 687 */ MCD_OPC_CheckPredicate, 3, 179, 3, // Skip to: 1638
+/* 691 */ MCD_OPC_Decode, 209, 9, 45, // Opcode: MULT_MM
+/* 695 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 707
+/* 699 */ MCD_OPC_CheckPredicate, 3, 167, 3, // Skip to: 1638
+/* 703 */ MCD_OPC_Decode, 211, 9, 45, // Opcode: MULTu_MM
+/* 707 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 719
+/* 711 */ MCD_OPC_CheckPredicate, 3, 155, 3, // Skip to: 1638
+/* 715 */ MCD_OPC_Decode, 163, 11, 45, // Opcode: SDIV_MM
+/* 719 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 731
+/* 723 */ MCD_OPC_CheckPredicate, 3, 143, 3, // Skip to: 1638
+/* 727 */ MCD_OPC_Decode, 223, 13, 45, // Opcode: UDIV_MM
+/* 731 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 743
+/* 735 */ MCD_OPC_CheckPredicate, 3, 131, 3, // Skip to: 1638
+/* 739 */ MCD_OPC_Decode, 146, 8, 45, // Opcode: MADD_MM
+/* 743 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 755
+/* 747 */ MCD_OPC_CheckPredicate, 3, 119, 3, // Skip to: 1638
+/* 751 */ MCD_OPC_Decode, 137, 8, 45, // Opcode: MADDU_MM
+/* 755 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 767
+/* 759 */ MCD_OPC_CheckPredicate, 3, 107, 3, // Skip to: 1638
+/* 763 */ MCD_OPC_Decode, 164, 9, 45, // Opcode: MSUB_MM
+/* 767 */ MCD_OPC_FilterValue, 15, 99, 3, // Skip to: 1638
+/* 771 */ MCD_OPC_CheckPredicate, 3, 95, 3, // Skip to: 1638
+/* 775 */ MCD_OPC_Decode, 155, 9, 45, // Opcode: MSUBU_MM
+/* 779 */ MCD_OPC_FilterValue, 45, 45, 0, // Skip to: 828
+/* 783 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ...
+/* 786 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 804
+/* 790 */ MCD_OPC_CheckPredicate, 3, 76, 3, // Skip to: 1638
+/* 794 */ MCD_OPC_CheckField, 21, 5, 0, 70, 3, // Skip to: 1638
+/* 800 */ MCD_OPC_Decode, 131, 13, 46, // Opcode: SYNC_MM
+/* 804 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 816
+/* 808 */ MCD_OPC_CheckPredicate, 3, 58, 3, // Skip to: 1638
+/* 812 */ MCD_OPC_Decode, 133, 13, 41, // Opcode: SYSCALL_MM
+/* 816 */ MCD_OPC_FilterValue, 13, 50, 3, // Skip to: 1638
+/* 820 */ MCD_OPC_CheckPredicate, 3, 46, 3, // Skip to: 1638
+/* 824 */ MCD_OPC_Decode, 154, 11, 41, // Opcode: SDBBP_MM
+/* 828 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 840
+/* 832 */ MCD_OPC_CheckPredicate, 3, 34, 3, // Skip to: 1638
+/* 836 */ MCD_OPC_Decode, 212, 13, 40, // Opcode: TNE_MM
+/* 840 */ MCD_OPC_FilterValue, 53, 75, 0, // Skip to: 919
+/* 844 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ...
+/* 847 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 865
+/* 851 */ MCD_OPC_CheckPredicate, 3, 15, 3, // Skip to: 1638
+/* 855 */ MCD_OPC_CheckField, 21, 5, 0, 9, 3, // Skip to: 1638
+/* 861 */ MCD_OPC_Decode, 190, 8, 42, // Opcode: MFHI_MM
+/* 865 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 883
+/* 869 */ MCD_OPC_CheckPredicate, 3, 253, 2, // Skip to: 1638
+/* 873 */ MCD_OPC_CheckField, 21, 5, 0, 247, 2, // Skip to: 1638
+/* 879 */ MCD_OPC_Decode, 195, 8, 42, // Opcode: MFLO_MM
+/* 883 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 901
+/* 887 */ MCD_OPC_CheckPredicate, 3, 235, 2, // Skip to: 1638
+/* 891 */ MCD_OPC_CheckField, 21, 5, 0, 229, 2, // Skip to: 1638
+/* 897 */ MCD_OPC_Decode, 179, 9, 42, // Opcode: MTHI_MM
+/* 901 */ MCD_OPC_FilterValue, 3, 221, 2, // Skip to: 1638
+/* 905 */ MCD_OPC_CheckPredicate, 3, 217, 2, // Skip to: 1638
+/* 909 */ MCD_OPC_CheckField, 21, 5, 0, 211, 2, // Skip to: 1638
+/* 915 */ MCD_OPC_Decode, 184, 9, 42, // Opcode: MTLO_MM
+/* 919 */ MCD_OPC_FilterValue, 60, 203, 2, // Skip to: 1638
+/* 923 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ...
+/* 926 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 952
+/* 930 */ MCD_OPC_CheckPredicate, 3, 10, 0, // Skip to: 944
+/* 934 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 944
+/* 940 */ MCD_OPC_Decode, 143, 7, 42, // Opcode: JR_MM
+/* 944 */ MCD_OPC_CheckPredicate, 3, 178, 2, // Skip to: 1638
+/* 948 */ MCD_OPC_Decode, 129, 7, 43, // Opcode: JALR_MM
+/* 952 */ MCD_OPC_FilterValue, 4, 170, 2, // Skip to: 1638
+/* 956 */ MCD_OPC_CheckPredicate, 3, 166, 2, // Skip to: 1638
+/* 960 */ MCD_OPC_Decode, 255, 6, 43, // Opcode: JALRS_MM
+/* 964 */ MCD_OPC_FilterValue, 4, 7, 0, // Skip to: 975
+/* 968 */ MCD_OPC_CheckPredicate, 3, 154, 2, // Skip to: 1638
+/* 972 */ MCD_OPC_Decode, 74, 47, // Opcode: ADDi_MM
+/* 975 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 987
+/* 979 */ MCD_OPC_CheckPredicate, 3, 143, 2, // Skip to: 1638
+/* 983 */ MCD_OPC_Decode, 160, 7, 48, // Opcode: LBu_MM
+/* 987 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 999
+/* 991 */ MCD_OPC_CheckPredicate, 3, 131, 2, // Skip to: 1638
+/* 995 */ MCD_OPC_Decode, 145, 11, 48, // Opcode: SB_MM
+/* 999 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 1011
+/* 1003 */ MCD_OPC_CheckPredicate, 3, 119, 2, // Skip to: 1638
+/* 1007 */ MCD_OPC_Decode, 157, 7, 48, // Opcode: LB_MM
+/* 1011 */ MCD_OPC_FilterValue, 8, 63, 0, // Skip to: 1078
+/* 1015 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ...
+/* 1018 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1030
+/* 1022 */ MCD_OPC_CheckPredicate, 3, 100, 2, // Skip to: 1638
+/* 1026 */ MCD_OPC_Decode, 229, 7, 49, // Opcode: LWP_MM
+/* 1030 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1042
+/* 1034 */ MCD_OPC_CheckPredicate, 3, 88, 2, // Skip to: 1638
+/* 1038 */ MCD_OPC_Decode, 226, 7, 49, // Opcode: LWM32_MM
+/* 1042 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1054
+/* 1046 */ MCD_OPC_CheckPredicate, 3, 76, 2, // Skip to: 1638
+/* 1050 */ MCD_OPC_Decode, 221, 2, 50, // Opcode: CACHE_MM
+/* 1054 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1066
+/* 1058 */ MCD_OPC_CheckPredicate, 3, 64, 2, // Skip to: 1638
+/* 1062 */ MCD_OPC_Decode, 249, 12, 49, // Opcode: SWP_MM
+/* 1066 */ MCD_OPC_FilterValue, 13, 56, 2, // Skip to: 1638
+/* 1070 */ MCD_OPC_CheckPredicate, 3, 52, 2, // Skip to: 1638
+/* 1074 */ MCD_OPC_Decode, 247, 12, 49, // Opcode: SWM32_MM
+/* 1078 */ MCD_OPC_FilterValue, 12, 7, 0, // Skip to: 1089
+/* 1082 */ MCD_OPC_CheckPredicate, 3, 40, 2, // Skip to: 1638
+/* 1086 */ MCD_OPC_Decode, 76, 47, // Opcode: ADDiu_MM
+/* 1089 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1101
+/* 1093 */ MCD_OPC_CheckPredicate, 3, 29, 2, // Skip to: 1638
+/* 1097 */ MCD_OPC_Decode, 191, 7, 48, // Opcode: LHu_MM
+/* 1101 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1113
+/* 1105 */ MCD_OPC_CheckPredicate, 3, 17, 2, // Skip to: 1638
+/* 1109 */ MCD_OPC_Decode, 216, 11, 48, // Opcode: SH_MM
+/* 1113 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 1125
+/* 1117 */ MCD_OPC_CheckPredicate, 3, 5, 2, // Skip to: 1638
+/* 1121 */ MCD_OPC_Decode, 188, 7, 48, // Opcode: LH_MM
+/* 1125 */ MCD_OPC_FilterValue, 16, 207, 0, // Skip to: 1336
+/* 1129 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 1132 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1144
+/* 1136 */ MCD_OPC_CheckPredicate, 3, 242, 1, // Skip to: 1638
+/* 1140 */ MCD_OPC_Decode, 140, 2, 51, // Opcode: BLTZ_MM
+/* 1144 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1156
+/* 1148 */ MCD_OPC_CheckPredicate, 3, 230, 1, // Skip to: 1638
+/* 1152 */ MCD_OPC_Decode, 137, 2, 51, // Opcode: BLTZAL_MM
+/* 1156 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1168
+/* 1160 */ MCD_OPC_CheckPredicate, 3, 218, 1, // Skip to: 1638
+/* 1164 */ MCD_OPC_Decode, 226, 1, 51, // Opcode: BGEZ_MM
+/* 1168 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1180
+/* 1172 */ MCD_OPC_CheckPredicate, 3, 206, 1, // Skip to: 1638
+/* 1176 */ MCD_OPC_Decode, 223, 1, 51, // Opcode: BGEZAL_MM
+/* 1180 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 1192
+/* 1184 */ MCD_OPC_CheckPredicate, 3, 194, 1, // Skip to: 1638
+/* 1188 */ MCD_OPC_Decode, 128, 2, 51, // Opcode: BLEZ_MM
+/* 1192 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1204
+/* 1196 */ MCD_OPC_CheckPredicate, 3, 182, 1, // Skip to: 1638
+/* 1200 */ MCD_OPC_Decode, 160, 2, 51, // Opcode: BNEZC_MM
+/* 1204 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1216
+/* 1208 */ MCD_OPC_CheckPredicate, 3, 170, 1, // Skip to: 1638
+/* 1212 */ MCD_OPC_Decode, 232, 1, 51, // Opcode: BGTZ_MM
+/* 1216 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 1228
+/* 1220 */ MCD_OPC_CheckPredicate, 3, 158, 1, // Skip to: 1638
+/* 1224 */ MCD_OPC_Decode, 213, 1, 51, // Opcode: BEQZC_MM
+/* 1228 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1240
+/* 1232 */ MCD_OPC_CheckPredicate, 3, 146, 1, // Skip to: 1638
+/* 1236 */ MCD_OPC_Decode, 205, 13, 52, // Opcode: TLTI_MM
+/* 1240 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1252
+/* 1244 */ MCD_OPC_CheckPredicate, 3, 134, 1, // Skip to: 1638
+/* 1248 */ MCD_OPC_Decode, 190, 13, 52, // Opcode: TGEI_MM
+/* 1252 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1264
+/* 1256 */ MCD_OPC_CheckPredicate, 3, 122, 1, // Skip to: 1638
+/* 1260 */ MCD_OPC_Decode, 204, 13, 52, // Opcode: TLTIU_MM
+/* 1264 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1276
+/* 1268 */ MCD_OPC_CheckPredicate, 3, 110, 1, // Skip to: 1638
+/* 1272 */ MCD_OPC_Decode, 189, 13, 52, // Opcode: TGEIU_MM
+/* 1276 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 1288
+/* 1280 */ MCD_OPC_CheckPredicate, 3, 98, 1, // Skip to: 1638
+/* 1284 */ MCD_OPC_Decode, 211, 13, 52, // Opcode: TNEI_MM
+/* 1288 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1300
+/* 1292 */ MCD_OPC_CheckPredicate, 3, 86, 1, // Skip to: 1638
+/* 1296 */ MCD_OPC_Decode, 212, 7, 52, // Opcode: LUi_MM
+/* 1300 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1312
+/* 1304 */ MCD_OPC_CheckPredicate, 3, 74, 1, // Skip to: 1638
+/* 1308 */ MCD_OPC_Decode, 184, 13, 52, // Opcode: TEQI_MM
+/* 1312 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1324
+/* 1316 */ MCD_OPC_CheckPredicate, 3, 62, 1, // Skip to: 1638
+/* 1320 */ MCD_OPC_Decode, 136, 2, 51, // Opcode: BLTZALS_MM
+/* 1324 */ MCD_OPC_FilterValue, 19, 54, 1, // Skip to: 1638
+/* 1328 */ MCD_OPC_CheckPredicate, 3, 50, 1, // Skip to: 1638
+/* 1332 */ MCD_OPC_Decode, 222, 1, 51, // Opcode: BGEZALS_MM
+/* 1336 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 1348
+/* 1340 */ MCD_OPC_CheckPredicate, 3, 38, 1, // Skip to: 1638
+/* 1344 */ MCD_OPC_Decode, 144, 10, 53, // Opcode: ORi_MM
+/* 1348 */ MCD_OPC_FilterValue, 21, 29, 0, // Skip to: 1381
+/* 1352 */ MCD_OPC_ExtractField, 0, 13, // Inst{12-0} ...
+/* 1355 */ MCD_OPC_FilterValue, 251, 2, 8, 0, // Skip to: 1368
+/* 1360 */ MCD_OPC_CheckPredicate, 3, 18, 1, // Skip to: 1638
+/* 1364 */ MCD_OPC_Decode, 241, 8, 54, // Opcode: MOVF_I_MM
+/* 1368 */ MCD_OPC_FilterValue, 251, 18, 9, 1, // Skip to: 1638
+/* 1373 */ MCD_OPC_CheckPredicate, 3, 5, 1, // Skip to: 1638
+/* 1377 */ MCD_OPC_Decode, 133, 9, 54, // Opcode: MOVT_I_MM
+/* 1381 */ MCD_OPC_FilterValue, 24, 99, 0, // Skip to: 1484
+/* 1385 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ...
+/* 1388 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1400
+/* 1392 */ MCD_OPC_CheckPredicate, 3, 242, 0, // Skip to: 1638
+/* 1396 */ MCD_OPC_Decode, 224, 7, 49, // Opcode: LWL_MM
+/* 1400 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1412
+/* 1404 */ MCD_OPC_CheckPredicate, 3, 230, 0, // Skip to: 1638
+/* 1408 */ MCD_OPC_Decode, 232, 7, 49, // Opcode: LWR_MM
+/* 1412 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1424
+/* 1416 */ MCD_OPC_CheckPredicate, 3, 218, 0, // Skip to: 1638
+/* 1420 */ MCD_OPC_Decode, 182, 10, 50, // Opcode: PREF_MM
+/* 1424 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1436
+/* 1428 */ MCD_OPC_CheckPredicate, 3, 206, 0, // Skip to: 1638
+/* 1432 */ MCD_OPC_Decode, 196, 7, 49, // Opcode: LL_MM
+/* 1436 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1448
+/* 1440 */ MCD_OPC_CheckPredicate, 3, 194, 0, // Skip to: 1638
+/* 1444 */ MCD_OPC_Decode, 245, 12, 49, // Opcode: SWL_MM
+/* 1448 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1460
+/* 1452 */ MCD_OPC_CheckPredicate, 3, 182, 0, // Skip to: 1638
+/* 1456 */ MCD_OPC_Decode, 252, 12, 49, // Opcode: SWR_MM
+/* 1460 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1472
+/* 1464 */ MCD_OPC_CheckPredicate, 3, 170, 0, // Skip to: 1638
+/* 1468 */ MCD_OPC_Decode, 149, 11, 49, // Opcode: SC_MM
+/* 1472 */ MCD_OPC_FilterValue, 14, 162, 0, // Skip to: 1638
+/* 1476 */ MCD_OPC_CheckPredicate, 3, 158, 0, // Skip to: 1638
+/* 1480 */ MCD_OPC_Decode, 235, 7, 49, // Opcode: LWU_MM
+/* 1484 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 1496
+/* 1488 */ MCD_OPC_CheckPredicate, 3, 146, 0, // Skip to: 1638
+/* 1492 */ MCD_OPC_Decode, 247, 13, 53, // Opcode: XORi_MM
+/* 1496 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 1508
+/* 1500 */ MCD_OPC_CheckPredicate, 3, 134, 0, // Skip to: 1638
+/* 1504 */ MCD_OPC_Decode, 130, 7, 55, // Opcode: JALS_MM
+/* 1508 */ MCD_OPC_FilterValue, 30, 7, 0, // Skip to: 1519
+/* 1512 */ MCD_OPC_CheckPredicate, 3, 122, 0, // Skip to: 1638
+/* 1516 */ MCD_OPC_Decode, 27, 56, // Opcode: ADDIUPC_MM
+/* 1519 */ MCD_OPC_FilterValue, 36, 8, 0, // Skip to: 1531
+/* 1523 */ MCD_OPC_CheckPredicate, 3, 111, 0, // Skip to: 1638
+/* 1527 */ MCD_OPC_Decode, 245, 11, 47, // Opcode: SLTi_MM
+/* 1531 */ MCD_OPC_FilterValue, 37, 8, 0, // Skip to: 1543
+/* 1535 */ MCD_OPC_CheckPredicate, 3, 99, 0, // Skip to: 1638
+/* 1539 */ MCD_OPC_Decode, 214, 1, 57, // Opcode: BEQ_MM
+/* 1543 */ MCD_OPC_FilterValue, 44, 8, 0, // Skip to: 1555
+/* 1547 */ MCD_OPC_CheckPredicate, 3, 87, 0, // Skip to: 1638
+/* 1551 */ MCD_OPC_Decode, 248, 11, 47, // Opcode: SLTiu_MM
+/* 1555 */ MCD_OPC_FilterValue, 45, 8, 0, // Skip to: 1567
+/* 1559 */ MCD_OPC_CheckPredicate, 3, 75, 0, // Skip to: 1638
+/* 1563 */ MCD_OPC_Decode, 161, 2, 57, // Opcode: BNE_MM
+/* 1567 */ MCD_OPC_FilterValue, 52, 7, 0, // Skip to: 1578
+/* 1571 */ MCD_OPC_CheckPredicate, 3, 63, 0, // Skip to: 1638
+/* 1575 */ MCD_OPC_Decode, 95, 53, // Opcode: ANDi_MM
+/* 1578 */ MCD_OPC_FilterValue, 53, 8, 0, // Skip to: 1590
+/* 1582 */ MCD_OPC_CheckPredicate, 3, 52, 0, // Skip to: 1638
+/* 1586 */ MCD_OPC_Decode, 144, 7, 55, // Opcode: J_MM
+/* 1590 */ MCD_OPC_FilterValue, 60, 8, 0, // Skip to: 1602
+/* 1594 */ MCD_OPC_CheckPredicate, 3, 40, 0, // Skip to: 1638
+/* 1598 */ MCD_OPC_Decode, 132, 7, 55, // Opcode: JALX_MM
+/* 1602 */ MCD_OPC_FilterValue, 61, 8, 0, // Skip to: 1614
+/* 1606 */ MCD_OPC_CheckPredicate, 3, 28, 0, // Skip to: 1638
+/* 1610 */ MCD_OPC_Decode, 133, 7, 55, // Opcode: JAL_MM
+/* 1614 */ MCD_OPC_FilterValue, 62, 8, 0, // Skip to: 1626
+/* 1618 */ MCD_OPC_CheckPredicate, 3, 16, 0, // Skip to: 1638
+/* 1622 */ MCD_OPC_Decode, 128, 13, 48, // Opcode: SW_MM
+/* 1626 */ MCD_OPC_FilterValue, 63, 8, 0, // Skip to: 1638
+/* 1630 */ MCD_OPC_CheckPredicate, 3, 4, 0, // Skip to: 1638
+/* 1634 */ MCD_OPC_Decode, 240, 7, 48, // Opcode: LW_MM
+/* 1638 */ MCD_OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableMips32[] = {
+/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ...
+/* 3 */ MCD_OPC_FilterValue, 0, 173, 3, // Skip to: 948
+/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 10 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 68
+/* 14 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 17 */ MCD_OPC_FilterValue, 0, 137, 53, // Skip to: 13726
+/* 21 */ MCD_OPC_ExtractField, 6, 15, // Inst{20-6} ...
+/* 24 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 36
+/* 28 */ MCD_OPC_CheckPredicate, 5, 28, 0, // Skip to: 60
+/* 32 */ MCD_OPC_Decode, 180, 12, 0, // Opcode: SSNOP
+/* 36 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 48
+/* 40 */ MCD_OPC_CheckPredicate, 5, 16, 0, // Skip to: 60
+/* 44 */ MCD_OPC_Decode, 139, 5, 0, // Opcode: EHB
+/* 48 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 60
+/* 52 */ MCD_OPC_CheckPredicate, 6, 4, 0, // Skip to: 60
+/* 56 */ MCD_OPC_Decode, 147, 10, 0, // Opcode: PAUSE
+/* 60 */ MCD_OPC_CheckPredicate, 1, 94, 53, // Skip to: 13726
+/* 64 */ MCD_OPC_Decode, 225, 11, 58, // Opcode: SLL
+/* 68 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 111
+/* 72 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ...
+/* 75 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 93
+/* 79 */ MCD_OPC_CheckPredicate, 7, 75, 53, // Skip to: 13726
+/* 83 */ MCD_OPC_CheckField, 6, 5, 0, 69, 53, // Skip to: 13726
+/* 89 */ MCD_OPC_Decode, 239, 8, 59, // Opcode: MOVF_I
+/* 93 */ MCD_OPC_FilterValue, 1, 61, 53, // Skip to: 13726
+/* 97 */ MCD_OPC_CheckPredicate, 7, 57, 53, // Skip to: 13726
+/* 101 */ MCD_OPC_CheckField, 6, 5, 0, 51, 53, // Skip to: 13726
+/* 107 */ MCD_OPC_Decode, 131, 9, 59, // Opcode: MOVT_I
+/* 111 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 142
+/* 115 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 118 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 130
+/* 122 */ MCD_OPC_CheckPredicate, 1, 32, 53, // Skip to: 13726
+/* 126 */ MCD_OPC_Decode, 159, 12, 58, // Opcode: SRL
+/* 130 */ MCD_OPC_FilterValue, 1, 24, 53, // Skip to: 13726
+/* 134 */ MCD_OPC_CheckPredicate, 6, 20, 53, // Skip to: 13726
+/* 138 */ MCD_OPC_Decode, 247, 10, 58, // Opcode: ROTR
+/* 142 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 160
+/* 146 */ MCD_OPC_CheckPredicate, 5, 8, 53, // Skip to: 13726
+/* 150 */ MCD_OPC_CheckField, 21, 5, 0, 2, 53, // Skip to: 13726
+/* 156 */ MCD_OPC_Decode, 139, 12, 58, // Opcode: SRA
+/* 160 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 178
+/* 164 */ MCD_OPC_CheckPredicate, 5, 246, 52, // Skip to: 13726
+/* 168 */ MCD_OPC_CheckField, 6, 5, 0, 240, 52, // Skip to: 13726
+/* 174 */ MCD_OPC_Decode, 233, 11, 36, // Opcode: SLLV
+/* 178 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 196
+/* 182 */ MCD_OPC_CheckPredicate, 8, 228, 52, // Skip to: 13726
+/* 186 */ MCD_OPC_CheckField, 8, 3, 0, 222, 52, // Skip to: 13726
+/* 192 */ MCD_OPC_Decode, 205, 7, 60, // Opcode: LSA
+/* 196 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 227
+/* 200 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 203 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 215
+/* 207 */ MCD_OPC_CheckPredicate, 5, 203, 52, // Skip to: 13726
+/* 211 */ MCD_OPC_Decode, 173, 12, 36, // Opcode: SRLV
+/* 215 */ MCD_OPC_FilterValue, 1, 195, 52, // Skip to: 13726
+/* 219 */ MCD_OPC_CheckPredicate, 6, 191, 52, // Skip to: 13726
+/* 223 */ MCD_OPC_Decode, 248, 10, 36, // Opcode: ROTRV
+/* 227 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 245
+/* 231 */ MCD_OPC_CheckPredicate, 5, 179, 52, // Skip to: 13726
+/* 235 */ MCD_OPC_CheckField, 6, 5, 0, 173, 52, // Skip to: 13726
+/* 241 */ MCD_OPC_Decode, 152, 12, 36, // Opcode: SRAV
+/* 245 */ MCD_OPC_FilterValue, 8, 27, 0, // Skip to: 276
+/* 249 */ MCD_OPC_ExtractField, 6, 15, // Inst{20-6} ...
+/* 252 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 264
+/* 256 */ MCD_OPC_CheckPredicate, 5, 154, 52, // Skip to: 13726
+/* 260 */ MCD_OPC_Decode, 136, 7, 61, // Opcode: JR
+/* 264 */ MCD_OPC_FilterValue, 16, 146, 52, // Skip to: 13726
+/* 268 */ MCD_OPC_CheckPredicate, 9, 142, 52, // Skip to: 13726
+/* 272 */ MCD_OPC_Decode, 141, 7, 61, // Opcode: JR_HB
+/* 276 */ MCD_OPC_FilterValue, 9, 39, 0, // Skip to: 319
+/* 280 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 283 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 301
+/* 287 */ MCD_OPC_CheckPredicate, 1, 123, 52, // Skip to: 13726
+/* 291 */ MCD_OPC_CheckField, 16, 5, 0, 117, 52, // Skip to: 13726
+/* 297 */ MCD_OPC_Decode, 249, 6, 62, // Opcode: JALR
+/* 301 */ MCD_OPC_FilterValue, 16, 109, 52, // Skip to: 13726
+/* 305 */ MCD_OPC_CheckPredicate, 10, 105, 52, // Skip to: 13726
+/* 309 */ MCD_OPC_CheckField, 16, 5, 0, 99, 52, // Skip to: 13726
+/* 315 */ MCD_OPC_Decode, 128, 7, 62, // Opcode: JALR_HB
+/* 319 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 337
+/* 323 */ MCD_OPC_CheckPredicate, 7, 87, 52, // Skip to: 13726
+/* 327 */ MCD_OPC_CheckField, 6, 5, 0, 81, 52, // Skip to: 13726
+/* 333 */ MCD_OPC_Decode, 143, 9, 63, // Opcode: MOVZ_I_I
+/* 337 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 355
+/* 341 */ MCD_OPC_CheckPredicate, 7, 69, 52, // Skip to: 13726
+/* 345 */ MCD_OPC_CheckField, 6, 5, 0, 63, 52, // Skip to: 13726
+/* 351 */ MCD_OPC_Decode, 251, 8, 63, // Opcode: MOVN_I_I
+/* 355 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 367
+/* 359 */ MCD_OPC_CheckPredicate, 5, 51, 52, // Skip to: 13726
+/* 363 */ MCD_OPC_Decode, 132, 13, 64, // Opcode: SYSCALL
+/* 367 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 379
+/* 371 */ MCD_OPC_CheckPredicate, 5, 39, 52, // Skip to: 13726
+/* 375 */ MCD_OPC_Decode, 171, 2, 33, // Opcode: BREAK
+/* 379 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 391
+/* 383 */ MCD_OPC_CheckPredicate, 10, 27, 52, // Skip to: 13726
+/* 387 */ MCD_OPC_Decode, 129, 13, 65, // Opcode: SYNC
+/* 391 */ MCD_OPC_FilterValue, 16, 43, 0, // Skip to: 438
+/* 395 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 398 */ MCD_OPC_FilterValue, 0, 12, 52, // Skip to: 13726
+/* 402 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ...
+/* 405 */ MCD_OPC_FilterValue, 0, 5, 52, // Skip to: 13726
+/* 409 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ...
+/* 412 */ MCD_OPC_FilterValue, 0, 254, 51, // Skip to: 13726
+/* 416 */ MCD_OPC_CheckPredicate, 11, 10, 0, // Skip to: 430
+/* 420 */ MCD_OPC_CheckField, 21, 2, 0, 4, 0, // Skip to: 430
+/* 426 */ MCD_OPC_Decode, 186, 8, 66, // Opcode: MFHI
+/* 430 */ MCD_OPC_CheckPredicate, 12, 236, 51, // Skip to: 13726
+/* 434 */ MCD_OPC_Decode, 189, 8, 67, // Opcode: MFHI_DSP
+/* 438 */ MCD_OPC_FilterValue, 17, 36, 0, // Skip to: 478
+/* 442 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 445 */ MCD_OPC_FilterValue, 0, 221, 51, // Skip to: 13726
+/* 449 */ MCD_OPC_ExtractField, 13, 8, // Inst{20-13} ...
+/* 452 */ MCD_OPC_FilterValue, 0, 214, 51, // Skip to: 13726
+/* 456 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 470
+/* 460 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 470
+/* 466 */ MCD_OPC_Decode, 176, 9, 61, // Opcode: MTHI
+/* 470 */ MCD_OPC_CheckPredicate, 12, 196, 51, // Skip to: 13726
+/* 474 */ MCD_OPC_Decode, 178, 9, 68, // Opcode: MTHI_DSP
+/* 478 */ MCD_OPC_FilterValue, 18, 43, 0, // Skip to: 525
+/* 482 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 485 */ MCD_OPC_FilterValue, 0, 181, 51, // Skip to: 13726
+/* 489 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ...
+/* 492 */ MCD_OPC_FilterValue, 0, 174, 51, // Skip to: 13726
+/* 496 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ...
+/* 499 */ MCD_OPC_FilterValue, 0, 167, 51, // Skip to: 13726
+/* 503 */ MCD_OPC_CheckPredicate, 11, 10, 0, // Skip to: 517
+/* 507 */ MCD_OPC_CheckField, 21, 2, 0, 4, 0, // Skip to: 517
+/* 513 */ MCD_OPC_Decode, 191, 8, 66, // Opcode: MFLO
+/* 517 */ MCD_OPC_CheckPredicate, 12, 149, 51, // Skip to: 13726
+/* 521 */ MCD_OPC_Decode, 194, 8, 67, // Opcode: MFLO_DSP
+/* 525 */ MCD_OPC_FilterValue, 19, 36, 0, // Skip to: 565
+/* 529 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 532 */ MCD_OPC_FilterValue, 0, 134, 51, // Skip to: 13726
+/* 536 */ MCD_OPC_ExtractField, 13, 8, // Inst{20-13} ...
+/* 539 */ MCD_OPC_FilterValue, 0, 127, 51, // Skip to: 13726
+/* 543 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 557
+/* 547 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 557
+/* 553 */ MCD_OPC_Decode, 181, 9, 61, // Opcode: MTLO
+/* 557 */ MCD_OPC_CheckPredicate, 12, 109, 51, // Skip to: 13726
+/* 561 */ MCD_OPC_Decode, 183, 9, 69, // Opcode: MTLO_DSP
+/* 565 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 583
+/* 569 */ MCD_OPC_CheckPredicate, 14, 97, 51, // Skip to: 13726
+/* 573 */ MCD_OPC_CheckField, 8, 3, 0, 91, 51, // Skip to: 13726
+/* 579 */ MCD_OPC_Decode, 194, 4, 70, // Opcode: DLSA
+/* 583 */ MCD_OPC_FilterValue, 24, 36, 0, // Skip to: 623
+/* 587 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 590 */ MCD_OPC_FilterValue, 0, 76, 51, // Skip to: 13726
+/* 594 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 597 */ MCD_OPC_FilterValue, 0, 69, 51, // Skip to: 13726
+/* 601 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 615
+/* 605 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 615
+/* 611 */ MCD_OPC_Decode, 206, 9, 43, // Opcode: MULT
+/* 615 */ MCD_OPC_CheckPredicate, 12, 51, 51, // Skip to: 13726
+/* 619 */ MCD_OPC_Decode, 208, 9, 71, // Opcode: MULT_DSP
+/* 623 */ MCD_OPC_FilterValue, 25, 36, 0, // Skip to: 663
+/* 627 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 630 */ MCD_OPC_FilterValue, 0, 36, 51, // Skip to: 13726
+/* 634 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 637 */ MCD_OPC_FilterValue, 0, 29, 51, // Skip to: 13726
+/* 641 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 655
+/* 645 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 655
+/* 651 */ MCD_OPC_Decode, 210, 9, 43, // Opcode: MULTu
+/* 655 */ MCD_OPC_CheckPredicate, 12, 11, 51, // Skip to: 13726
+/* 659 */ MCD_OPC_Decode, 207, 9, 71, // Opcode: MULTU_DSP
+/* 663 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 681
+/* 667 */ MCD_OPC_CheckPredicate, 13, 255, 50, // Skip to: 13726
+/* 671 */ MCD_OPC_CheckField, 6, 10, 0, 249, 50, // Skip to: 13726
+/* 677 */ MCD_OPC_Decode, 162, 11, 43, // Opcode: SDIV
+/* 681 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 699
+/* 685 */ MCD_OPC_CheckPredicate, 13, 237, 50, // Skip to: 13726
+/* 689 */ MCD_OPC_CheckField, 6, 10, 0, 231, 50, // Skip to: 13726
+/* 695 */ MCD_OPC_Decode, 222, 13, 43, // Opcode: UDIV
+/* 699 */ MCD_OPC_FilterValue, 32, 13, 0, // Skip to: 716
+/* 703 */ MCD_OPC_CheckPredicate, 5, 219, 50, // Skip to: 13726
+/* 707 */ MCD_OPC_CheckField, 6, 5, 0, 213, 50, // Skip to: 13726
+/* 713 */ MCD_OPC_Decode, 25, 35, // Opcode: ADD
+/* 716 */ MCD_OPC_FilterValue, 33, 13, 0, // Skip to: 733
+/* 720 */ MCD_OPC_CheckPredicate, 5, 202, 50, // Skip to: 13726
+/* 724 */ MCD_OPC_CheckField, 6, 5, 0, 196, 50, // Skip to: 13726
+/* 730 */ MCD_OPC_Decode, 77, 35, // Opcode: ADDu
+/* 733 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 751
+/* 737 */ MCD_OPC_CheckPredicate, 5, 185, 50, // Skip to: 13726
+/* 741 */ MCD_OPC_CheckField, 6, 5, 0, 179, 50, // Skip to: 13726
+/* 747 */ MCD_OPC_Decode, 190, 12, 35, // Opcode: SUB
+/* 751 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 769
+/* 755 */ MCD_OPC_CheckPredicate, 5, 167, 50, // Skip to: 13726
+/* 759 */ MCD_OPC_CheckField, 6, 5, 0, 161, 50, // Skip to: 13726
+/* 765 */ MCD_OPC_Decode, 230, 12, 35, // Opcode: SUBu
+/* 769 */ MCD_OPC_FilterValue, 36, 13, 0, // Skip to: 786
+/* 773 */ MCD_OPC_CheckPredicate, 1, 149, 50, // Skip to: 13726
+/* 777 */ MCD_OPC_CheckField, 6, 5, 0, 143, 50, // Skip to: 13726
+/* 783 */ MCD_OPC_Decode, 83, 35, // Opcode: AND
+/* 786 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 804
+/* 790 */ MCD_OPC_CheckPredicate, 1, 132, 50, // Skip to: 13726
+/* 794 */ MCD_OPC_CheckField, 6, 5, 0, 126, 50, // Skip to: 13726
+/* 800 */ MCD_OPC_Decode, 133, 10, 35, // Opcode: OR
+/* 804 */ MCD_OPC_FilterValue, 38, 14, 0, // Skip to: 822
+/* 808 */ MCD_OPC_CheckPredicate, 1, 114, 50, // Skip to: 13726
+/* 812 */ MCD_OPC_CheckField, 6, 5, 0, 108, 50, // Skip to: 13726
+/* 818 */ MCD_OPC_Decode, 236, 13, 35, // Opcode: XOR
+/* 822 */ MCD_OPC_FilterValue, 39, 14, 0, // Skip to: 840
+/* 826 */ MCD_OPC_CheckPredicate, 5, 96, 50, // Skip to: 13726
+/* 830 */ MCD_OPC_CheckField, 6, 5, 0, 90, 50, // Skip to: 13726
+/* 836 */ MCD_OPC_Decode, 250, 9, 35, // Opcode: NOR
+/* 840 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 858
+/* 844 */ MCD_OPC_CheckPredicate, 5, 78, 50, // Skip to: 13726
+/* 848 */ MCD_OPC_CheckField, 6, 5, 0, 72, 50, // Skip to: 13726
+/* 854 */ MCD_OPC_Decode, 240, 11, 35, // Opcode: SLT
+/* 858 */ MCD_OPC_FilterValue, 43, 14, 0, // Skip to: 876
+/* 862 */ MCD_OPC_CheckPredicate, 5, 60, 50, // Skip to: 13726
+/* 866 */ MCD_OPC_CheckField, 6, 5, 0, 54, 50, // Skip to: 13726
+/* 872 */ MCD_OPC_Decode, 249, 11, 35, // Opcode: SLTu
+/* 876 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 888
+/* 880 */ MCD_OPC_CheckPredicate, 15, 42, 50, // Skip to: 13726
+/* 884 */ MCD_OPC_Decode, 186, 13, 72, // Opcode: TGE
+/* 888 */ MCD_OPC_FilterValue, 49, 8, 0, // Skip to: 900
+/* 892 */ MCD_OPC_CheckPredicate, 15, 30, 50, // Skip to: 13726
+/* 896 */ MCD_OPC_Decode, 191, 13, 72, // Opcode: TGEU
+/* 900 */ MCD_OPC_FilterValue, 50, 8, 0, // Skip to: 912
+/* 904 */ MCD_OPC_CheckPredicate, 15, 18, 50, // Skip to: 13726
+/* 908 */ MCD_OPC_Decode, 202, 13, 72, // Opcode: TLT
+/* 912 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 924
+/* 916 */ MCD_OPC_CheckPredicate, 15, 6, 50, // Skip to: 13726
+/* 920 */ MCD_OPC_Decode, 206, 13, 72, // Opcode: TLTU
+/* 924 */ MCD_OPC_FilterValue, 52, 8, 0, // Skip to: 936
+/* 928 */ MCD_OPC_CheckPredicate, 15, 250, 49, // Skip to: 13726
+/* 932 */ MCD_OPC_Decode, 182, 13, 72, // Opcode: TEQ
+/* 936 */ MCD_OPC_FilterValue, 54, 242, 49, // Skip to: 13726
+/* 940 */ MCD_OPC_CheckPredicate, 15, 238, 49, // Skip to: 13726
+/* 944 */ MCD_OPC_Decode, 209, 13, 72, // Opcode: TNE
+/* 948 */ MCD_OPC_FilterValue, 1, 201, 0, // Skip to: 1153
+/* 952 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ...
+/* 955 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 967
+/* 959 */ MCD_OPC_CheckPredicate, 5, 219, 49, // Skip to: 13726
+/* 963 */ MCD_OPC_Decode, 131, 2, 73, // Opcode: BLTZ
+/* 967 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 979
+/* 971 */ MCD_OPC_CheckPredicate, 5, 207, 49, // Skip to: 13726
+/* 975 */ MCD_OPC_Decode, 217, 1, 73, // Opcode: BGEZ
+/* 979 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 991
+/* 983 */ MCD_OPC_CheckPredicate, 16, 195, 49, // Skip to: 13726
+/* 987 */ MCD_OPC_Decode, 139, 2, 73, // Opcode: BLTZL
+/* 991 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1003
+/* 995 */ MCD_OPC_CheckPredicate, 16, 183, 49, // Skip to: 13726
+/* 999 */ MCD_OPC_Decode, 225, 1, 73, // Opcode: BGEZL
+/* 1003 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1015
+/* 1007 */ MCD_OPC_CheckPredicate, 16, 171, 49, // Skip to: 13726
+/* 1011 */ MCD_OPC_Decode, 187, 13, 74, // Opcode: TGEI
+/* 1015 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1027
+/* 1019 */ MCD_OPC_CheckPredicate, 16, 159, 49, // Skip to: 13726
+/* 1023 */ MCD_OPC_Decode, 188, 13, 74, // Opcode: TGEIU
+/* 1027 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1039
+/* 1031 */ MCD_OPC_CheckPredicate, 16, 147, 49, // Skip to: 13726
+/* 1035 */ MCD_OPC_Decode, 203, 13, 74, // Opcode: TLTI
+/* 1039 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1051
+/* 1043 */ MCD_OPC_CheckPredicate, 16, 135, 49, // Skip to: 13726
+/* 1047 */ MCD_OPC_Decode, 221, 13, 74, // Opcode: TTLTIU
+/* 1051 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 1063
+/* 1055 */ MCD_OPC_CheckPredicate, 16, 123, 49, // Skip to: 13726
+/* 1059 */ MCD_OPC_Decode, 183, 13, 74, // Opcode: TEQI
+/* 1063 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1075
+/* 1067 */ MCD_OPC_CheckPredicate, 16, 111, 49, // Skip to: 13726
+/* 1071 */ MCD_OPC_Decode, 210, 13, 74, // Opcode: TNEI
+/* 1075 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 1087
+/* 1079 */ MCD_OPC_CheckPredicate, 13, 99, 49, // Skip to: 13726
+/* 1083 */ MCD_OPC_Decode, 133, 2, 73, // Opcode: BLTZAL
+/* 1087 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1099
+/* 1091 */ MCD_OPC_CheckPredicate, 13, 87, 49, // Skip to: 13726
+/* 1095 */ MCD_OPC_Decode, 219, 1, 73, // Opcode: BGEZAL
+/* 1099 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 1111
+/* 1103 */ MCD_OPC_CheckPredicate, 16, 75, 49, // Skip to: 13726
+/* 1107 */ MCD_OPC_Decode, 135, 2, 73, // Opcode: BLTZALL
+/* 1111 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 1123
+/* 1115 */ MCD_OPC_CheckPredicate, 16, 63, 49, // Skip to: 13726
+/* 1119 */ MCD_OPC_Decode, 221, 1, 73, // Opcode: BGEZALL
+/* 1123 */ MCD_OPC_FilterValue, 28, 14, 0, // Skip to: 1141
+/* 1127 */ MCD_OPC_CheckPredicate, 12, 51, 49, // Skip to: 13726
+/* 1131 */ MCD_OPC_CheckField, 21, 5, 0, 45, 49, // Skip to: 13726
+/* 1137 */ MCD_OPC_Decode, 169, 2, 75, // Opcode: BPOSGE32
+/* 1141 */ MCD_OPC_FilterValue, 31, 37, 49, // Skip to: 13726
+/* 1145 */ MCD_OPC_CheckPredicate, 6, 33, 49, // Skip to: 13726
+/* 1149 */ MCD_OPC_Decode, 130, 13, 76, // Opcode: SYNCI
+/* 1153 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1165
+/* 1157 */ MCD_OPC_CheckPredicate, 10, 21, 49, // Skip to: 13726
+/* 1161 */ MCD_OPC_Decode, 247, 6, 77, // Opcode: J
+/* 1165 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1177
+/* 1169 */ MCD_OPC_CheckPredicate, 5, 9, 49, // Skip to: 13726
+/* 1173 */ MCD_OPC_Decode, 248, 6, 77, // Opcode: JAL
+/* 1177 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 1189
+/* 1181 */ MCD_OPC_CheckPredicate, 5, 253, 48, // Skip to: 13726
+/* 1185 */ MCD_OPC_Decode, 206, 1, 78, // Opcode: BEQ
+/* 1189 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1201
+/* 1193 */ MCD_OPC_CheckPredicate, 5, 241, 48, // Skip to: 13726
+/* 1197 */ MCD_OPC_Decode, 145, 2, 78, // Opcode: BNE
+/* 1201 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1219
+/* 1205 */ MCD_OPC_CheckPredicate, 5, 229, 48, // Skip to: 13726
+/* 1209 */ MCD_OPC_CheckField, 16, 5, 0, 223, 48, // Skip to: 13726
+/* 1215 */ MCD_OPC_Decode, 251, 1, 73, // Opcode: BLEZ
+/* 1219 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1237
+/* 1223 */ MCD_OPC_CheckPredicate, 5, 211, 48, // Skip to: 13726
+/* 1227 */ MCD_OPC_CheckField, 16, 5, 0, 205, 48, // Skip to: 13726
+/* 1233 */ MCD_OPC_Decode, 227, 1, 73, // Opcode: BGTZ
+/* 1237 */ MCD_OPC_FilterValue, 8, 7, 0, // Skip to: 1248
+/* 1241 */ MCD_OPC_CheckPredicate, 13, 193, 48, // Skip to: 13726
+/* 1245 */ MCD_OPC_Decode, 73, 79, // Opcode: ADDi
+/* 1248 */ MCD_OPC_FilterValue, 9, 7, 0, // Skip to: 1259
+/* 1252 */ MCD_OPC_CheckPredicate, 1, 182, 48, // Skip to: 13726
+/* 1256 */ MCD_OPC_Decode, 75, 79, // Opcode: ADDiu
+/* 1259 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1271
+/* 1263 */ MCD_OPC_CheckPredicate, 5, 171, 48, // Skip to: 13726
+/* 1267 */ MCD_OPC_Decode, 243, 11, 79, // Opcode: SLTi
+/* 1271 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1283
+/* 1275 */ MCD_OPC_CheckPredicate, 5, 159, 48, // Skip to: 13726
+/* 1279 */ MCD_OPC_Decode, 246, 11, 79, // Opcode: SLTiu
+/* 1283 */ MCD_OPC_FilterValue, 12, 7, 0, // Skip to: 1294
+/* 1287 */ MCD_OPC_CheckPredicate, 1, 147, 48, // Skip to: 13726
+/* 1291 */ MCD_OPC_Decode, 93, 80, // Opcode: ANDi
+/* 1294 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1306
+/* 1298 */ MCD_OPC_CheckPredicate, 5, 136, 48, // Skip to: 13726
+/* 1302 */ MCD_OPC_Decode, 142, 10, 80, // Opcode: ORi
+/* 1306 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1318
+/* 1310 */ MCD_OPC_CheckPredicate, 5, 124, 48, // Skip to: 13726
+/* 1314 */ MCD_OPC_Decode, 245, 13, 80, // Opcode: XORi
+/* 1318 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 1336
+/* 1322 */ MCD_OPC_CheckPredicate, 5, 112, 48, // Skip to: 13726
+/* 1326 */ MCD_OPC_CheckField, 21, 5, 0, 106, 48, // Skip to: 13726
+/* 1332 */ MCD_OPC_Decode, 210, 7, 52, // Opcode: LUi
+/* 1336 */ MCD_OPC_FilterValue, 16, 220, 0, // Skip to: 1560
+/* 1340 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 1343 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1361
+/* 1347 */ MCD_OPC_CheckPredicate, 10, 87, 48, // Skip to: 13726
+/* 1351 */ MCD_OPC_CheckField, 3, 8, 0, 81, 48, // Skip to: 13726
+/* 1357 */ MCD_OPC_Decode, 179, 8, 81, // Opcode: MFC0
+/* 1361 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1379
+/* 1365 */ MCD_OPC_CheckPredicate, 10, 69, 48, // Skip to: 13726
+/* 1369 */ MCD_OPC_CheckField, 3, 8, 0, 63, 48, // Skip to: 13726
+/* 1375 */ MCD_OPC_Decode, 169, 9, 81, // Opcode: MTC0
+/* 1379 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 1434
+/* 1383 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ...
+/* 1386 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1398
+/* 1390 */ MCD_OPC_CheckPredicate, 13, 44, 48, // Skip to: 13726
+/* 1394 */ MCD_OPC_Decode, 176, 1, 82, // Opcode: BC0F
+/* 1398 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1410
+/* 1402 */ MCD_OPC_CheckPredicate, 13, 32, 48, // Skip to: 13726
+/* 1406 */ MCD_OPC_Decode, 178, 1, 82, // Opcode: BC0T
+/* 1410 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1422
+/* 1414 */ MCD_OPC_CheckPredicate, 13, 20, 48, // Skip to: 13726
+/* 1418 */ MCD_OPC_Decode, 177, 1, 82, // Opcode: BC0FL
+/* 1422 */ MCD_OPC_FilterValue, 3, 12, 48, // Skip to: 13726
+/* 1426 */ MCD_OPC_CheckPredicate, 13, 8, 48, // Skip to: 13726
+/* 1430 */ MCD_OPC_Decode, 179, 1, 82, // Opcode: BC0TL
+/* 1434 */ MCD_OPC_FilterValue, 11, 31, 0, // Skip to: 1469
+/* 1438 */ MCD_OPC_ExtractField, 0, 16, // Inst{15-0} ...
+/* 1441 */ MCD_OPC_FilterValue, 128, 192, 1, 8, 0, // Skip to: 1455
+/* 1447 */ MCD_OPC_CheckPredicate, 6, 243, 47, // Skip to: 13726
+/* 1451 */ MCD_OPC_Decode, 179, 4, 42, // Opcode: DI
+/* 1455 */ MCD_OPC_FilterValue, 160, 192, 1, 233, 47, // Skip to: 13726
+/* 1461 */ MCD_OPC_CheckPredicate, 6, 229, 47, // Skip to: 13726
+/* 1465 */ MCD_OPC_Decode, 141, 5, 42, // Opcode: EI
+/* 1469 */ MCD_OPC_FilterValue, 16, 221, 47, // Skip to: 13726
+/* 1473 */ MCD_OPC_ExtractField, 0, 21, // Inst{20-0} ...
+/* 1476 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1488
+/* 1480 */ MCD_OPC_CheckPredicate, 5, 210, 47, // Skip to: 13726
+/* 1484 */ MCD_OPC_Decode, 196, 13, 0, // Opcode: TLBR
+/* 1488 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1500
+/* 1492 */ MCD_OPC_CheckPredicate, 5, 198, 47, // Skip to: 13726
+/* 1496 */ MCD_OPC_Decode, 198, 13, 0, // Opcode: TLBWI
+/* 1500 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1512
+/* 1504 */ MCD_OPC_CheckPredicate, 5, 186, 47, // Skip to: 13726
+/* 1508 */ MCD_OPC_Decode, 200, 13, 0, // Opcode: TLBWR
+/* 1512 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1524
+/* 1516 */ MCD_OPC_CheckPredicate, 5, 174, 47, // Skip to: 13726
+/* 1520 */ MCD_OPC_Decode, 194, 13, 0, // Opcode: TLBP
+/* 1524 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 1536
+/* 1528 */ MCD_OPC_CheckPredicate, 17, 162, 47, // Skip to: 13726
+/* 1532 */ MCD_OPC_Decode, 143, 5, 0, // Opcode: ERET
+/* 1536 */ MCD_OPC_FilterValue, 31, 8, 0, // Skip to: 1548
+/* 1540 */ MCD_OPC_CheckPredicate, 10, 150, 47, // Skip to: 13726
+/* 1544 */ MCD_OPC_Decode, 174, 4, 0, // Opcode: DERET
+/* 1548 */ MCD_OPC_FilterValue, 32, 142, 47, // Skip to: 13726
+/* 1552 */ MCD_OPC_CheckPredicate, 18, 138, 47, // Skip to: 13726
+/* 1556 */ MCD_OPC_Decode, 231, 13, 0, // Opcode: WAIT
+/* 1560 */ MCD_OPC_FilterValue, 17, 21, 6, // Skip to: 3121
+/* 1564 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 1567 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1585
+/* 1571 */ MCD_OPC_CheckPredicate, 5, 119, 47, // Skip to: 13726
+/* 1575 */ MCD_OPC_CheckField, 0, 11, 0, 113, 47, // Skip to: 13726
+/* 1581 */ MCD_OPC_Decode, 180, 8, 83, // Opcode: MFC1
+/* 1585 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 1603
+/* 1589 */ MCD_OPC_CheckPredicate, 19, 101, 47, // Skip to: 13726
+/* 1593 */ MCD_OPC_CheckField, 0, 11, 0, 95, 47, // Skip to: 13726
+/* 1599 */ MCD_OPC_Decode, 197, 4, 84, // Opcode: DMFC1
+/* 1603 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 1621
+/* 1607 */ MCD_OPC_CheckPredicate, 5, 83, 47, // Skip to: 13726
+/* 1611 */ MCD_OPC_CheckField, 0, 11, 0, 77, 47, // Skip to: 13726
+/* 1617 */ MCD_OPC_Decode, 238, 2, 85, // Opcode: CFC1
+/* 1621 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 1639
+/* 1625 */ MCD_OPC_CheckPredicate, 20, 65, 47, // Skip to: 13726
+/* 1629 */ MCD_OPC_CheckField, 0, 11, 0, 59, 47, // Skip to: 13726
+/* 1635 */ MCD_OPC_Decode, 183, 8, 86, // Opcode: MFHC1_D32
+/* 1639 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1657
+/* 1643 */ MCD_OPC_CheckPredicate, 5, 47, 47, // Skip to: 13726
+/* 1647 */ MCD_OPC_CheckField, 0, 11, 0, 41, 47, // Skip to: 13726
+/* 1653 */ MCD_OPC_Decode, 170, 9, 87, // Opcode: MTC1
+/* 1657 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 1675
+/* 1661 */ MCD_OPC_CheckPredicate, 19, 29, 47, // Skip to: 13726
+/* 1665 */ MCD_OPC_CheckField, 0, 11, 0, 23, 47, // Skip to: 13726
+/* 1671 */ MCD_OPC_Decode, 202, 4, 88, // Opcode: DMTC1
+/* 1675 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1693
+/* 1679 */ MCD_OPC_CheckPredicate, 5, 11, 47, // Skip to: 13726
+/* 1683 */ MCD_OPC_CheckField, 0, 11, 0, 5, 47, // Skip to: 13726
+/* 1689 */ MCD_OPC_Decode, 210, 3, 89, // Opcode: CTC1
+/* 1693 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1711
+/* 1697 */ MCD_OPC_CheckPredicate, 20, 249, 46, // Skip to: 13726
+/* 1701 */ MCD_OPC_CheckField, 0, 11, 0, 243, 46, // Skip to: 13726
+/* 1707 */ MCD_OPC_Decode, 173, 9, 90, // Opcode: MTHC1_D32
+/* 1711 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 1766
+/* 1715 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ...
+/* 1718 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1730
+/* 1722 */ MCD_OPC_CheckPredicate, 13, 224, 46, // Skip to: 13726
+/* 1726 */ MCD_OPC_Decode, 181, 1, 91, // Opcode: BC1F
+/* 1730 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1742
+/* 1734 */ MCD_OPC_CheckPredicate, 13, 212, 46, // Skip to: 13726
+/* 1738 */ MCD_OPC_Decode, 185, 1, 91, // Opcode: BC1T
+/* 1742 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1754
+/* 1746 */ MCD_OPC_CheckPredicate, 16, 200, 46, // Skip to: 13726
+/* 1750 */ MCD_OPC_Decode, 182, 1, 91, // Opcode: BC1FL
+/* 1754 */ MCD_OPC_FilterValue, 3, 192, 46, // Skip to: 13726
+/* 1758 */ MCD_OPC_CheckPredicate, 16, 188, 46, // Skip to: 13726
+/* 1762 */ MCD_OPC_Decode, 186, 1, 91, // Opcode: BC1TL
+/* 1766 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1778
+/* 1770 */ MCD_OPC_CheckPredicate, 8, 176, 46, // Skip to: 13726
+/* 1774 */ MCD_OPC_Decode, 192, 2, 92, // Opcode: BZ_V
+/* 1778 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 1790
+/* 1782 */ MCD_OPC_CheckPredicate, 8, 164, 46, // Skip to: 13726
+/* 1786 */ MCD_OPC_Decode, 166, 2, 92, // Opcode: BNZ_V
+/* 1790 */ MCD_OPC_FilterValue, 16, 80, 2, // Skip to: 2386
+/* 1794 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 1797 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1809
+/* 1801 */ MCD_OPC_CheckPredicate, 5, 145, 46, // Skip to: 13726
+/* 1805 */ MCD_OPC_Decode, 174, 5, 93, // Opcode: FADD_S
+/* 1809 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1821
+/* 1813 */ MCD_OPC_CheckPredicate, 5, 133, 46, // Skip to: 13726
+/* 1817 */ MCD_OPC_Decode, 176, 6, 93, // Opcode: FSUB_S
+/* 1821 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1833
+/* 1825 */ MCD_OPC_CheckPredicate, 5, 121, 46, // Skip to: 13726
+/* 1829 */ MCD_OPC_Decode, 139, 6, 93, // Opcode: FMUL_S
+/* 1833 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1845
+/* 1837 */ MCD_OPC_CheckPredicate, 5, 109, 46, // Skip to: 13726
+/* 1841 */ MCD_OPC_Decode, 210, 5, 93, // Opcode: FDIV_S
+/* 1845 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1863
+/* 1849 */ MCD_OPC_CheckPredicate, 15, 97, 46, // Skip to: 13726
+/* 1853 */ MCD_OPC_CheckField, 16, 5, 0, 91, 46, // Skip to: 13726
+/* 1859 */ MCD_OPC_Decode, 169, 6, 94, // Opcode: FSQRT_S
+/* 1863 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 1881
+/* 1867 */ MCD_OPC_CheckPredicate, 5, 79, 46, // Skip to: 13726
+/* 1871 */ MCD_OPC_CheckField, 16, 5, 0, 73, 46, // Skip to: 13726
+/* 1877 */ MCD_OPC_Decode, 167, 5, 94, // Opcode: FABS_S
+/* 1881 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1899
+/* 1885 */ MCD_OPC_CheckPredicate, 5, 61, 46, // Skip to: 13726
+/* 1889 */ MCD_OPC_CheckField, 16, 5, 0, 55, 46, // Skip to: 13726
+/* 1895 */ MCD_OPC_Decode, 131, 6, 94, // Opcode: FMOV_S
+/* 1899 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1917
+/* 1903 */ MCD_OPC_CheckPredicate, 5, 43, 46, // Skip to: 13726
+/* 1907 */ MCD_OPC_CheckField, 16, 5, 0, 37, 46, // Skip to: 13726
+/* 1913 */ MCD_OPC_Decode, 145, 6, 94, // Opcode: FNEG_S
+/* 1917 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 1935
+/* 1921 */ MCD_OPC_CheckPredicate, 15, 25, 46, // Skip to: 13726
+/* 1925 */ MCD_OPC_CheckField, 16, 5, 0, 19, 46, // Skip to: 13726
+/* 1931 */ MCD_OPC_Decode, 128, 11, 94, // Opcode: ROUND_W_S
+/* 1935 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 1953
+/* 1939 */ MCD_OPC_CheckPredicate, 15, 7, 46, // Skip to: 13726
+/* 1943 */ MCD_OPC_CheckField, 16, 5, 0, 1, 46, // Skip to: 13726
+/* 1949 */ MCD_OPC_Decode, 219, 13, 94, // Opcode: TRUNC_W_S
+/* 1953 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 1971
+/* 1957 */ MCD_OPC_CheckPredicate, 15, 245, 45, // Skip to: 13726
+/* 1961 */ MCD_OPC_CheckField, 16, 5, 0, 239, 45, // Skip to: 13726
+/* 1967 */ MCD_OPC_Decode, 228, 2, 94, // Opcode: CEIL_W_S
+/* 1971 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 1989
+/* 1975 */ MCD_OPC_CheckPredicate, 15, 227, 45, // Skip to: 13726
+/* 1979 */ MCD_OPC_CheckField, 16, 5, 0, 221, 45, // Skip to: 13726
+/* 1985 */ MCD_OPC_Decode, 244, 5, 94, // Opcode: FLOOR_W_S
+/* 1989 */ MCD_OPC_FilterValue, 17, 27, 0, // Skip to: 2020
+/* 1993 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ...
+/* 1996 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2008
+/* 2000 */ MCD_OPC_CheckPredicate, 7, 202, 45, // Skip to: 13726
+/* 2004 */ MCD_OPC_Decode, 242, 8, 95, // Opcode: MOVF_S
+/* 2008 */ MCD_OPC_FilterValue, 1, 194, 45, // Skip to: 13726
+/* 2012 */ MCD_OPC_CheckPredicate, 7, 190, 45, // Skip to: 13726
+/* 2016 */ MCD_OPC_Decode, 134, 9, 95, // Opcode: MOVT_S
+/* 2020 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 2032
+/* 2024 */ MCD_OPC_CheckPredicate, 7, 178, 45, // Skip to: 13726
+/* 2028 */ MCD_OPC_Decode, 146, 9, 96, // Opcode: MOVZ_I_S
+/* 2032 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 2044
+/* 2036 */ MCD_OPC_CheckPredicate, 7, 166, 45, // Skip to: 13726
+/* 2040 */ MCD_OPC_Decode, 254, 8, 96, // Opcode: MOVN_I_S
+/* 2044 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 2062
+/* 2048 */ MCD_OPC_CheckPredicate, 21, 154, 45, // Skip to: 13726
+/* 2052 */ MCD_OPC_CheckField, 16, 5, 0, 148, 45, // Skip to: 13726
+/* 2058 */ MCD_OPC_Decode, 213, 3, 97, // Opcode: CVT_D32_S
+/* 2062 */ MCD_OPC_FilterValue, 36, 14, 0, // Skip to: 2080
+/* 2066 */ MCD_OPC_CheckPredicate, 5, 136, 45, // Skip to: 13726
+/* 2070 */ MCD_OPC_CheckField, 16, 5, 0, 130, 45, // Skip to: 13726
+/* 2076 */ MCD_OPC_Decode, 233, 3, 94, // Opcode: CVT_W_S
+/* 2080 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 2098
+/* 2084 */ MCD_OPC_CheckPredicate, 22, 118, 45, // Skip to: 13726
+/* 2088 */ MCD_OPC_CheckField, 16, 5, 0, 112, 45, // Skip to: 13726
+/* 2094 */ MCD_OPC_Decode, 222, 3, 98, // Opcode: CVT_L_S
+/* 2098 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 2116
+/* 2102 */ MCD_OPC_CheckPredicate, 13, 100, 45, // Skip to: 13726
+/* 2106 */ MCD_OPC_CheckField, 6, 5, 0, 94, 45, // Skip to: 13726
+/* 2112 */ MCD_OPC_Decode, 240, 3, 99, // Opcode: C_F_S
+/* 2116 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 2134
+/* 2120 */ MCD_OPC_CheckPredicate, 13, 82, 45, // Skip to: 13726
+/* 2124 */ MCD_OPC_CheckField, 6, 5, 0, 76, 45, // Skip to: 13726
+/* 2130 */ MCD_OPC_Decode, 154, 4, 99, // Opcode: C_UN_S
+/* 2134 */ MCD_OPC_FilterValue, 50, 14, 0, // Skip to: 2152
+/* 2138 */ MCD_OPC_CheckPredicate, 13, 64, 45, // Skip to: 13726
+/* 2142 */ MCD_OPC_CheckField, 6, 5, 0, 58, 45, // Skip to: 13726
+/* 2148 */ MCD_OPC_Decode, 237, 3, 99, // Opcode: C_EQ_S
+/* 2152 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 2170
+/* 2156 */ MCD_OPC_CheckPredicate, 13, 46, 45, // Skip to: 13726
+/* 2160 */ MCD_OPC_CheckField, 6, 5, 0, 40, 45, // Skip to: 13726
+/* 2166 */ MCD_OPC_Decode, 145, 4, 99, // Opcode: C_UEQ_S
+/* 2170 */ MCD_OPC_FilterValue, 52, 14, 0, // Skip to: 2188
+/* 2174 */ MCD_OPC_CheckPredicate, 13, 28, 45, // Skip to: 13726
+/* 2178 */ MCD_OPC_CheckField, 6, 5, 0, 22, 45, // Skip to: 13726
+/* 2184 */ MCD_OPC_Decode, 136, 4, 99, // Opcode: C_OLT_S
+/* 2188 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 2206
+/* 2192 */ MCD_OPC_CheckPredicate, 13, 10, 45, // Skip to: 13726
+/* 2196 */ MCD_OPC_CheckField, 6, 5, 0, 4, 45, // Skip to: 13726
+/* 2202 */ MCD_OPC_Decode, 151, 4, 99, // Opcode: C_ULT_S
+/* 2206 */ MCD_OPC_FilterValue, 54, 14, 0, // Skip to: 2224
+/* 2210 */ MCD_OPC_CheckPredicate, 13, 248, 44, // Skip to: 13726
+/* 2214 */ MCD_OPC_CheckField, 6, 5, 0, 242, 44, // Skip to: 13726
+/* 2220 */ MCD_OPC_Decode, 133, 4, 99, // Opcode: C_OLE_S
+/* 2224 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 2242
+/* 2228 */ MCD_OPC_CheckPredicate, 13, 230, 44, // Skip to: 13726
+/* 2232 */ MCD_OPC_CheckField, 6, 5, 0, 224, 44, // Skip to: 13726
+/* 2238 */ MCD_OPC_Decode, 148, 4, 99, // Opcode: C_ULE_S
+/* 2242 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 2260
+/* 2246 */ MCD_OPC_CheckPredicate, 13, 212, 44, // Skip to: 13726
+/* 2250 */ MCD_OPC_CheckField, 6, 5, 0, 206, 44, // Skip to: 13726
+/* 2256 */ MCD_OPC_Decode, 142, 4, 99, // Opcode: C_SF_S
+/* 2260 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 2278
+/* 2264 */ MCD_OPC_CheckPredicate, 13, 194, 44, // Skip to: 13726
+/* 2268 */ MCD_OPC_CheckField, 6, 5, 0, 188, 44, // Skip to: 13726
+/* 2274 */ MCD_OPC_Decode, 252, 3, 99, // Opcode: C_NGLE_S
+/* 2278 */ MCD_OPC_FilterValue, 58, 14, 0, // Skip to: 2296
+/* 2282 */ MCD_OPC_CheckPredicate, 13, 176, 44, // Skip to: 13726
+/* 2286 */ MCD_OPC_CheckField, 6, 5, 0, 170, 44, // Skip to: 13726
+/* 2292 */ MCD_OPC_Decode, 139, 4, 99, // Opcode: C_SEQ_S
+/* 2296 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 2314
+/* 2300 */ MCD_OPC_CheckPredicate, 13, 158, 44, // Skip to: 13726
+/* 2304 */ MCD_OPC_CheckField, 6, 5, 0, 152, 44, // Skip to: 13726
+/* 2310 */ MCD_OPC_Decode, 255, 3, 99, // Opcode: C_NGL_S
+/* 2314 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 2332
+/* 2318 */ MCD_OPC_CheckPredicate, 13, 140, 44, // Skip to: 13726
+/* 2322 */ MCD_OPC_CheckField, 6, 5, 0, 134, 44, // Skip to: 13726
+/* 2328 */ MCD_OPC_Decode, 246, 3, 99, // Opcode: C_LT_S
+/* 2332 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 2350
+/* 2336 */ MCD_OPC_CheckPredicate, 13, 122, 44, // Skip to: 13726
+/* 2340 */ MCD_OPC_CheckField, 6, 5, 0, 116, 44, // Skip to: 13726
+/* 2346 */ MCD_OPC_Decode, 249, 3, 99, // Opcode: C_NGE_S
+/* 2350 */ MCD_OPC_FilterValue, 62, 14, 0, // Skip to: 2368
+/* 2354 */ MCD_OPC_CheckPredicate, 13, 104, 44, // Skip to: 13726
+/* 2358 */ MCD_OPC_CheckField, 6, 5, 0, 98, 44, // Skip to: 13726
+/* 2364 */ MCD_OPC_Decode, 243, 3, 99, // Opcode: C_LE_S
+/* 2368 */ MCD_OPC_FilterValue, 63, 90, 44, // Skip to: 13726
+/* 2372 */ MCD_OPC_CheckPredicate, 13, 86, 44, // Skip to: 13726
+/* 2376 */ MCD_OPC_CheckField, 6, 5, 0, 80, 44, // Skip to: 13726
+/* 2382 */ MCD_OPC_Decode, 130, 4, 99, // Opcode: C_NGT_S
+/* 2386 */ MCD_OPC_FilterValue, 17, 80, 2, // Skip to: 2982
+/* 2390 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 2393 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2405
+/* 2397 */ MCD_OPC_CheckPredicate, 21, 61, 44, // Skip to: 13726
+/* 2401 */ MCD_OPC_Decode, 171, 5, 100, // Opcode: FADD_D32
+/* 2405 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 2417
+/* 2409 */ MCD_OPC_CheckPredicate, 21, 49, 44, // Skip to: 13726
+/* 2413 */ MCD_OPC_Decode, 173, 6, 100, // Opcode: FSUB_D32
+/* 2417 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 2429
+/* 2421 */ MCD_OPC_CheckPredicate, 21, 37, 44, // Skip to: 13726
+/* 2425 */ MCD_OPC_Decode, 136, 6, 100, // Opcode: FMUL_D32
+/* 2429 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 2441
+/* 2433 */ MCD_OPC_CheckPredicate, 21, 25, 44, // Skip to: 13726
+/* 2437 */ MCD_OPC_Decode, 207, 5, 100, // Opcode: FDIV_D32
+/* 2441 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 2459
+/* 2445 */ MCD_OPC_CheckPredicate, 23, 13, 44, // Skip to: 13726
+/* 2449 */ MCD_OPC_CheckField, 16, 5, 0, 7, 44, // Skip to: 13726
+/* 2455 */ MCD_OPC_Decode, 166, 6, 101, // Opcode: FSQRT_D32
+/* 2459 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 2477
+/* 2463 */ MCD_OPC_CheckPredicate, 21, 251, 43, // Skip to: 13726
+/* 2467 */ MCD_OPC_CheckField, 16, 5, 0, 245, 43, // Skip to: 13726
+/* 2473 */ MCD_OPC_Decode, 164, 5, 101, // Opcode: FABS_D32
+/* 2477 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 2495
+/* 2481 */ MCD_OPC_CheckPredicate, 21, 233, 43, // Skip to: 13726
+/* 2485 */ MCD_OPC_CheckField, 16, 5, 0, 227, 43, // Skip to: 13726
+/* 2491 */ MCD_OPC_Decode, 128, 6, 101, // Opcode: FMOV_D32
+/* 2495 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 2513
+/* 2499 */ MCD_OPC_CheckPredicate, 21, 215, 43, // Skip to: 13726
+/* 2503 */ MCD_OPC_CheckField, 16, 5, 0, 209, 43, // Skip to: 13726
+/* 2509 */ MCD_OPC_Decode, 142, 6, 101, // Opcode: FNEG_D32
+/* 2513 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 2531
+/* 2517 */ MCD_OPC_CheckPredicate, 23, 197, 43, // Skip to: 13726
+/* 2521 */ MCD_OPC_CheckField, 16, 5, 0, 191, 43, // Skip to: 13726
+/* 2527 */ MCD_OPC_Decode, 253, 10, 102, // Opcode: ROUND_W_D32
+/* 2531 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 2549
+/* 2535 */ MCD_OPC_CheckPredicate, 23, 179, 43, // Skip to: 13726
+/* 2539 */ MCD_OPC_CheckField, 16, 5, 0, 173, 43, // Skip to: 13726
+/* 2545 */ MCD_OPC_Decode, 216, 13, 102, // Opcode: TRUNC_W_D32
+/* 2549 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 2567
+/* 2553 */ MCD_OPC_CheckPredicate, 23, 161, 43, // Skip to: 13726
+/* 2557 */ MCD_OPC_CheckField, 16, 5, 0, 155, 43, // Skip to: 13726
+/* 2563 */ MCD_OPC_Decode, 225, 2, 102, // Opcode: CEIL_W_D32
+/* 2567 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 2585
+/* 2571 */ MCD_OPC_CheckPredicate, 23, 143, 43, // Skip to: 13726
+/* 2575 */ MCD_OPC_CheckField, 16, 5, 0, 137, 43, // Skip to: 13726
+/* 2581 */ MCD_OPC_Decode, 241, 5, 102, // Opcode: FLOOR_W_D32
+/* 2585 */ MCD_OPC_FilterValue, 17, 27, 0, // Skip to: 2616
+/* 2589 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ...
+/* 2592 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2604
+/* 2596 */ MCD_OPC_CheckPredicate, 24, 118, 43, // Skip to: 13726
+/* 2600 */ MCD_OPC_Decode, 236, 8, 103, // Opcode: MOVF_D32
+/* 2604 */ MCD_OPC_FilterValue, 1, 110, 43, // Skip to: 13726
+/* 2608 */ MCD_OPC_CheckPredicate, 24, 106, 43, // Skip to: 13726
+/* 2612 */ MCD_OPC_Decode, 128, 9, 103, // Opcode: MOVT_D32
+/* 2616 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 2628
+/* 2620 */ MCD_OPC_CheckPredicate, 24, 94, 43, // Skip to: 13726
+/* 2624 */ MCD_OPC_Decode, 140, 9, 104, // Opcode: MOVZ_I_D32
+/* 2628 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 2640
+/* 2632 */ MCD_OPC_CheckPredicate, 24, 82, 43, // Skip to: 13726
+/* 2636 */ MCD_OPC_Decode, 248, 8, 104, // Opcode: MOVN_I_D32
+/* 2640 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 2658
+/* 2644 */ MCD_OPC_CheckPredicate, 21, 70, 43, // Skip to: 13726
+/* 2648 */ MCD_OPC_CheckField, 16, 5, 0, 64, 43, // Skip to: 13726
+/* 2654 */ MCD_OPC_Decode, 224, 3, 102, // Opcode: CVT_S_D32
+/* 2658 */ MCD_OPC_FilterValue, 36, 14, 0, // Skip to: 2676
+/* 2662 */ MCD_OPC_CheckPredicate, 21, 52, 43, // Skip to: 13726
+/* 2666 */ MCD_OPC_CheckField, 16, 5, 0, 46, 43, // Skip to: 13726
+/* 2672 */ MCD_OPC_Decode, 230, 3, 102, // Opcode: CVT_W_D32
+/* 2676 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 2694
+/* 2680 */ MCD_OPC_CheckPredicate, 22, 34, 43, // Skip to: 13726
+/* 2684 */ MCD_OPC_CheckField, 16, 5, 0, 28, 43, // Skip to: 13726
+/* 2690 */ MCD_OPC_Decode, 220, 3, 105, // Opcode: CVT_L_D64
+/* 2694 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 2712
+/* 2698 */ MCD_OPC_CheckPredicate, 25, 16, 43, // Skip to: 13726
+/* 2702 */ MCD_OPC_CheckField, 6, 5, 0, 10, 43, // Skip to: 13726
+/* 2708 */ MCD_OPC_Decode, 238, 3, 106, // Opcode: C_F_D32
+/* 2712 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 2730
+/* 2716 */ MCD_OPC_CheckPredicate, 25, 254, 42, // Skip to: 13726
+/* 2720 */ MCD_OPC_CheckField, 6, 5, 0, 248, 42, // Skip to: 13726
+/* 2726 */ MCD_OPC_Decode, 152, 4, 106, // Opcode: C_UN_D32
+/* 2730 */ MCD_OPC_FilterValue, 50, 14, 0, // Skip to: 2748
+/* 2734 */ MCD_OPC_CheckPredicate, 25, 236, 42, // Skip to: 13726
+/* 2738 */ MCD_OPC_CheckField, 6, 5, 0, 230, 42, // Skip to: 13726
+/* 2744 */ MCD_OPC_Decode, 235, 3, 106, // Opcode: C_EQ_D32
+/* 2748 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 2766
+/* 2752 */ MCD_OPC_CheckPredicate, 25, 218, 42, // Skip to: 13726
+/* 2756 */ MCD_OPC_CheckField, 6, 5, 0, 212, 42, // Skip to: 13726
+/* 2762 */ MCD_OPC_Decode, 143, 4, 106, // Opcode: C_UEQ_D32
+/* 2766 */ MCD_OPC_FilterValue, 52, 14, 0, // Skip to: 2784
+/* 2770 */ MCD_OPC_CheckPredicate, 25, 200, 42, // Skip to: 13726
+/* 2774 */ MCD_OPC_CheckField, 6, 5, 0, 194, 42, // Skip to: 13726
+/* 2780 */ MCD_OPC_Decode, 134, 4, 106, // Opcode: C_OLT_D32
+/* 2784 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 2802
+/* 2788 */ MCD_OPC_CheckPredicate, 25, 182, 42, // Skip to: 13726
+/* 2792 */ MCD_OPC_CheckField, 6, 5, 0, 176, 42, // Skip to: 13726
+/* 2798 */ MCD_OPC_Decode, 149, 4, 106, // Opcode: C_ULT_D32
+/* 2802 */ MCD_OPC_FilterValue, 54, 14, 0, // Skip to: 2820
+/* 2806 */ MCD_OPC_CheckPredicate, 25, 164, 42, // Skip to: 13726
+/* 2810 */ MCD_OPC_CheckField, 6, 5, 0, 158, 42, // Skip to: 13726
+/* 2816 */ MCD_OPC_Decode, 131, 4, 106, // Opcode: C_OLE_D32
+/* 2820 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 2838
+/* 2824 */ MCD_OPC_CheckPredicate, 25, 146, 42, // Skip to: 13726
+/* 2828 */ MCD_OPC_CheckField, 6, 5, 0, 140, 42, // Skip to: 13726
+/* 2834 */ MCD_OPC_Decode, 146, 4, 106, // Opcode: C_ULE_D32
+/* 2838 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 2856
+/* 2842 */ MCD_OPC_CheckPredicate, 25, 128, 42, // Skip to: 13726
+/* 2846 */ MCD_OPC_CheckField, 6, 5, 0, 122, 42, // Skip to: 13726
+/* 2852 */ MCD_OPC_Decode, 140, 4, 106, // Opcode: C_SF_D32
+/* 2856 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 2874
+/* 2860 */ MCD_OPC_CheckPredicate, 25, 110, 42, // Skip to: 13726
+/* 2864 */ MCD_OPC_CheckField, 6, 5, 0, 104, 42, // Skip to: 13726
+/* 2870 */ MCD_OPC_Decode, 250, 3, 106, // Opcode: C_NGLE_D32
+/* 2874 */ MCD_OPC_FilterValue, 58, 14, 0, // Skip to: 2892
+/* 2878 */ MCD_OPC_CheckPredicate, 25, 92, 42, // Skip to: 13726
+/* 2882 */ MCD_OPC_CheckField, 6, 5, 0, 86, 42, // Skip to: 13726
+/* 2888 */ MCD_OPC_Decode, 137, 4, 106, // Opcode: C_SEQ_D32
+/* 2892 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 2910
+/* 2896 */ MCD_OPC_CheckPredicate, 25, 74, 42, // Skip to: 13726
+/* 2900 */ MCD_OPC_CheckField, 6, 5, 0, 68, 42, // Skip to: 13726
+/* 2906 */ MCD_OPC_Decode, 253, 3, 106, // Opcode: C_NGL_D32
+/* 2910 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 2928
+/* 2914 */ MCD_OPC_CheckPredicate, 25, 56, 42, // Skip to: 13726
+/* 2918 */ MCD_OPC_CheckField, 6, 5, 0, 50, 42, // Skip to: 13726
+/* 2924 */ MCD_OPC_Decode, 244, 3, 106, // Opcode: C_LT_D32
+/* 2928 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 2946
+/* 2932 */ MCD_OPC_CheckPredicate, 25, 38, 42, // Skip to: 13726
+/* 2936 */ MCD_OPC_CheckField, 6, 5, 0, 32, 42, // Skip to: 13726
+/* 2942 */ MCD_OPC_Decode, 247, 3, 106, // Opcode: C_NGE_D32
+/* 2946 */ MCD_OPC_FilterValue, 62, 14, 0, // Skip to: 2964
+/* 2950 */ MCD_OPC_CheckPredicate, 25, 20, 42, // Skip to: 13726
+/* 2954 */ MCD_OPC_CheckField, 6, 5, 0, 14, 42, // Skip to: 13726
+/* 2960 */ MCD_OPC_Decode, 241, 3, 106, // Opcode: C_LE_D32
+/* 2964 */ MCD_OPC_FilterValue, 63, 6, 42, // Skip to: 13726
+/* 2968 */ MCD_OPC_CheckPredicate, 25, 2, 42, // Skip to: 13726
+/* 2972 */ MCD_OPC_CheckField, 6, 5, 0, 252, 41, // Skip to: 13726
+/* 2978 */ MCD_OPC_Decode, 128, 4, 106, // Opcode: C_NGT_D32
+/* 2982 */ MCD_OPC_FilterValue, 20, 39, 0, // Skip to: 3025
+/* 2986 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 2989 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 3007
+/* 2993 */ MCD_OPC_CheckPredicate, 5, 233, 41, // Skip to: 13726
+/* 2997 */ MCD_OPC_CheckField, 16, 5, 0, 227, 41, // Skip to: 13726
+/* 3003 */ MCD_OPC_Decode, 228, 3, 94, // Opcode: CVT_S_W
+/* 3007 */ MCD_OPC_FilterValue, 33, 219, 41, // Skip to: 13726
+/* 3011 */ MCD_OPC_CheckPredicate, 21, 215, 41, // Skip to: 13726
+/* 3015 */ MCD_OPC_CheckField, 16, 5, 0, 209, 41, // Skip to: 13726
+/* 3021 */ MCD_OPC_Decode, 214, 3, 97, // Opcode: CVT_D32_W
+/* 3025 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 3037
+/* 3029 */ MCD_OPC_CheckPredicate, 8, 197, 41, // Skip to: 13726
+/* 3033 */ MCD_OPC_Decode, 189, 2, 92, // Opcode: BZ_B
+/* 3037 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 3049
+/* 3041 */ MCD_OPC_CheckPredicate, 8, 185, 41, // Skip to: 13726
+/* 3045 */ MCD_OPC_Decode, 191, 2, 107, // Opcode: BZ_H
+/* 3049 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 3061
+/* 3053 */ MCD_OPC_CheckPredicate, 8, 173, 41, // Skip to: 13726
+/* 3057 */ MCD_OPC_Decode, 193, 2, 108, // Opcode: BZ_W
+/* 3061 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 3073
+/* 3065 */ MCD_OPC_CheckPredicate, 8, 161, 41, // Skip to: 13726
+/* 3069 */ MCD_OPC_Decode, 190, 2, 109, // Opcode: BZ_D
+/* 3073 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 3085
+/* 3077 */ MCD_OPC_CheckPredicate, 8, 149, 41, // Skip to: 13726
+/* 3081 */ MCD_OPC_Decode, 163, 2, 92, // Opcode: BNZ_B
+/* 3085 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 3097
+/* 3089 */ MCD_OPC_CheckPredicate, 8, 137, 41, // Skip to: 13726
+/* 3093 */ MCD_OPC_Decode, 165, 2, 107, // Opcode: BNZ_H
+/* 3097 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 3109
+/* 3101 */ MCD_OPC_CheckPredicate, 8, 125, 41, // Skip to: 13726
+/* 3105 */ MCD_OPC_Decode, 167, 2, 108, // Opcode: BNZ_W
+/* 3109 */ MCD_OPC_FilterValue, 31, 117, 41, // Skip to: 13726
+/* 3113 */ MCD_OPC_CheckPredicate, 8, 113, 41, // Skip to: 13726
+/* 3117 */ MCD_OPC_Decode, 164, 2, 109, // Opcode: BNZ_D
+/* 3121 */ MCD_OPC_FilterValue, 18, 94, 0, // Skip to: 3219
+/* 3125 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 3128 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3146
+/* 3132 */ MCD_OPC_CheckPredicate, 5, 94, 41, // Skip to: 13726
+/* 3136 */ MCD_OPC_CheckField, 3, 8, 0, 88, 41, // Skip to: 13726
+/* 3142 */ MCD_OPC_Decode, 182, 8, 81, // Opcode: MFC2
+/* 3146 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 3164
+/* 3150 */ MCD_OPC_CheckPredicate, 5, 76, 41, // Skip to: 13726
+/* 3154 */ MCD_OPC_CheckField, 3, 8, 0, 70, 41, // Skip to: 13726
+/* 3160 */ MCD_OPC_Decode, 172, 9, 81, // Opcode: MTC2
+/* 3164 */ MCD_OPC_FilterValue, 8, 62, 41, // Skip to: 13726
+/* 3168 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ...
+/* 3171 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3183
+/* 3175 */ MCD_OPC_CheckPredicate, 13, 51, 41, // Skip to: 13726
+/* 3179 */ MCD_OPC_Decode, 189, 1, 82, // Opcode: BC2F
+/* 3183 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3195
+/* 3187 */ MCD_OPC_CheckPredicate, 13, 39, 41, // Skip to: 13726
+/* 3191 */ MCD_OPC_Decode, 192, 1, 82, // Opcode: BC2T
+/* 3195 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3207
+/* 3199 */ MCD_OPC_CheckPredicate, 13, 27, 41, // Skip to: 13726
+/* 3203 */ MCD_OPC_Decode, 190, 1, 82, // Opcode: BC2FL
+/* 3207 */ MCD_OPC_FilterValue, 3, 19, 41, // Skip to: 13726
+/* 3211 */ MCD_OPC_CheckPredicate, 13, 15, 41, // Skip to: 13726
+/* 3215 */ MCD_OPC_Decode, 193, 1, 82, // Opcode: BC2TL
+/* 3219 */ MCD_OPC_FilterValue, 19, 9, 1, // Skip to: 3488
+/* 3223 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 3226 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 3281
+/* 3230 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ...
+/* 3233 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3245
+/* 3237 */ MCD_OPC_CheckPredicate, 13, 40, 0, // Skip to: 3281
+/* 3241 */ MCD_OPC_Decode, 194, 1, 82, // Opcode: BC3F
+/* 3245 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3257
+/* 3249 */ MCD_OPC_CheckPredicate, 13, 28, 0, // Skip to: 3281
+/* 3253 */ MCD_OPC_Decode, 196, 1, 82, // Opcode: BC3T
+/* 3257 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3269
+/* 3261 */ MCD_OPC_CheckPredicate, 13, 16, 0, // Skip to: 3281
+/* 3265 */ MCD_OPC_Decode, 195, 1, 82, // Opcode: BC3FL
+/* 3269 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 3281
+/* 3273 */ MCD_OPC_CheckPredicate, 13, 4, 0, // Skip to: 3281
+/* 3277 */ MCD_OPC_Decode, 197, 1, 82, // Opcode: BC3TL
+/* 3281 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 3284 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3302
+/* 3288 */ MCD_OPC_CheckPredicate, 26, 194, 40, // Skip to: 13726
+/* 3292 */ MCD_OPC_CheckField, 11, 5, 0, 188, 40, // Skip to: 13726
+/* 3298 */ MCD_OPC_Decode, 237, 7, 110, // Opcode: LWXC1
+/* 3302 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 3320
+/* 3306 */ MCD_OPC_CheckPredicate, 27, 176, 40, // Skip to: 13726
+/* 3310 */ MCD_OPC_CheckField, 11, 5, 0, 170, 40, // Skip to: 13726
+/* 3316 */ MCD_OPC_Decode, 175, 7, 111, // Opcode: LDXC1
+/* 3320 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 3338
+/* 3324 */ MCD_OPC_CheckPredicate, 28, 158, 40, // Skip to: 13726
+/* 3328 */ MCD_OPC_CheckField, 11, 5, 0, 152, 40, // Skip to: 13726
+/* 3334 */ MCD_OPC_Decode, 207, 7, 111, // Opcode: LUXC1
+/* 3338 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 3356
+/* 3342 */ MCD_OPC_CheckPredicate, 26, 140, 40, // Skip to: 13726
+/* 3346 */ MCD_OPC_CheckField, 6, 5, 0, 134, 40, // Skip to: 13726
+/* 3352 */ MCD_OPC_Decode, 254, 12, 112, // Opcode: SWXC1
+/* 3356 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 3374
+/* 3360 */ MCD_OPC_CheckPredicate, 27, 122, 40, // Skip to: 13726
+/* 3364 */ MCD_OPC_CheckField, 6, 5, 0, 116, 40, // Skip to: 13726
+/* 3370 */ MCD_OPC_Decode, 166, 11, 113, // Opcode: SDXC1
+/* 3374 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 3392
+/* 3378 */ MCD_OPC_CheckPredicate, 28, 104, 40, // Skip to: 13726
+/* 3382 */ MCD_OPC_CheckField, 6, 5, 0, 98, 40, // Skip to: 13726
+/* 3388 */ MCD_OPC_Decode, 232, 12, 113, // Opcode: SUXC1
+/* 3392 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 3404
+/* 3396 */ MCD_OPC_CheckPredicate, 26, 86, 40, // Skip to: 13726
+/* 3400 */ MCD_OPC_Decode, 149, 8, 114, // Opcode: MADD_S
+/* 3404 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 3416
+/* 3408 */ MCD_OPC_CheckPredicate, 29, 74, 40, // Skip to: 13726
+/* 3412 */ MCD_OPC_Decode, 142, 8, 115, // Opcode: MADD_D32
+/* 3416 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 3428
+/* 3420 */ MCD_OPC_CheckPredicate, 26, 62, 40, // Skip to: 13726
+/* 3424 */ MCD_OPC_Decode, 167, 9, 114, // Opcode: MSUB_S
+/* 3428 */ MCD_OPC_FilterValue, 41, 8, 0, // Skip to: 3440
+/* 3432 */ MCD_OPC_CheckPredicate, 29, 50, 40, // Skip to: 13726
+/* 3436 */ MCD_OPC_Decode, 160, 9, 115, // Opcode: MSUB_D32
+/* 3440 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 3452
+/* 3444 */ MCD_OPC_CheckPredicate, 26, 38, 40, // Skip to: 13726
+/* 3448 */ MCD_OPC_Decode, 242, 9, 114, // Opcode: NMADD_S
+/* 3452 */ MCD_OPC_FilterValue, 49, 8, 0, // Skip to: 3464
+/* 3456 */ MCD_OPC_CheckPredicate, 29, 26, 40, // Skip to: 13726
+/* 3460 */ MCD_OPC_Decode, 239, 9, 115, // Opcode: NMADD_D32
+/* 3464 */ MCD_OPC_FilterValue, 56, 8, 0, // Skip to: 3476
+/* 3468 */ MCD_OPC_CheckPredicate, 26, 14, 40, // Skip to: 13726
+/* 3472 */ MCD_OPC_Decode, 247, 9, 114, // Opcode: NMSUB_S
+/* 3476 */ MCD_OPC_FilterValue, 57, 6, 40, // Skip to: 13726
+/* 3480 */ MCD_OPC_CheckPredicate, 29, 2, 40, // Skip to: 13726
+/* 3484 */ MCD_OPC_Decode, 244, 9, 115, // Opcode: NMSUB_D32
+/* 3488 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 3500
+/* 3492 */ MCD_OPC_CheckPredicate, 16, 246, 39, // Skip to: 13726
+/* 3496 */ MCD_OPC_Decode, 209, 1, 78, // Opcode: BEQL
+/* 3500 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 3512
+/* 3504 */ MCD_OPC_CheckPredicate, 16, 234, 39, // Skip to: 13726
+/* 3508 */ MCD_OPC_Decode, 156, 2, 78, // Opcode: BNEL
+/* 3512 */ MCD_OPC_FilterValue, 22, 14, 0, // Skip to: 3530
+/* 3516 */ MCD_OPC_CheckPredicate, 16, 222, 39, // Skip to: 13726
+/* 3520 */ MCD_OPC_CheckField, 16, 5, 0, 216, 39, // Skip to: 13726
+/* 3526 */ MCD_OPC_Decode, 255, 1, 73, // Opcode: BLEZL
+/* 3530 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 3548
+/* 3534 */ MCD_OPC_CheckPredicate, 16, 204, 39, // Skip to: 13726
+/* 3538 */ MCD_OPC_CheckField, 16, 5, 0, 198, 39, // Skip to: 13726
+/* 3544 */ MCD_OPC_Decode, 231, 1, 73, // Opcode: BGTZL
+/* 3548 */ MCD_OPC_FilterValue, 28, 229, 0, // Skip to: 3781
+/* 3552 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 3555 */ MCD_OPC_FilterValue, 0, 36, 0, // Skip to: 3595
+/* 3559 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 3562 */ MCD_OPC_FilterValue, 0, 176, 39, // Skip to: 13726
+/* 3566 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 3569 */ MCD_OPC_FilterValue, 0, 169, 39, // Skip to: 13726
+/* 3573 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3587
+/* 3577 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3587
+/* 3583 */ MCD_OPC_Decode, 130, 8, 43, // Opcode: MADD
+/* 3587 */ MCD_OPC_CheckPredicate, 12, 151, 39, // Skip to: 13726
+/* 3591 */ MCD_OPC_Decode, 145, 8, 116, // Opcode: MADD_DSP
+/* 3595 */ MCD_OPC_FilterValue, 1, 36, 0, // Skip to: 3635
+/* 3599 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 3602 */ MCD_OPC_FilterValue, 0, 136, 39, // Skip to: 13726
+/* 3606 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 3609 */ MCD_OPC_FilterValue, 0, 129, 39, // Skip to: 13726
+/* 3613 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3627
+/* 3617 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3627
+/* 3623 */ MCD_OPC_Decode, 135, 8, 43, // Opcode: MADDU
+/* 3627 */ MCD_OPC_CheckPredicate, 12, 111, 39, // Skip to: 13726
+/* 3631 */ MCD_OPC_Decode, 136, 8, 116, // Opcode: MADDU_DSP
+/* 3635 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 3653
+/* 3639 */ MCD_OPC_CheckPredicate, 9, 99, 39, // Skip to: 13726
+/* 3643 */ MCD_OPC_CheckField, 6, 5, 0, 93, 39, // Skip to: 13726
+/* 3649 */ MCD_OPC_Decode, 193, 9, 35, // Opcode: MUL
+/* 3653 */ MCD_OPC_FilterValue, 4, 36, 0, // Skip to: 3693
+/* 3657 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 3660 */ MCD_OPC_FilterValue, 0, 78, 39, // Skip to: 13726
+/* 3664 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 3667 */ MCD_OPC_FilterValue, 0, 71, 39, // Skip to: 13726
+/* 3671 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3685
+/* 3675 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3685
+/* 3681 */ MCD_OPC_Decode, 148, 9, 43, // Opcode: MSUB
+/* 3685 */ MCD_OPC_CheckPredicate, 12, 53, 39, // Skip to: 13726
+/* 3689 */ MCD_OPC_Decode, 163, 9, 116, // Opcode: MSUB_DSP
+/* 3693 */ MCD_OPC_FilterValue, 5, 36, 0, // Skip to: 3733
+/* 3697 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 3700 */ MCD_OPC_FilterValue, 0, 38, 39, // Skip to: 13726
+/* 3704 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 3707 */ MCD_OPC_FilterValue, 0, 31, 39, // Skip to: 13726
+/* 3711 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3725
+/* 3715 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3725
+/* 3721 */ MCD_OPC_Decode, 153, 9, 43, // Opcode: MSUBU
+/* 3725 */ MCD_OPC_CheckPredicate, 12, 13, 39, // Skip to: 13726
+/* 3729 */ MCD_OPC_Decode, 154, 9, 116, // Opcode: MSUBU_DSP
+/* 3733 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 3751
+/* 3737 */ MCD_OPC_CheckPredicate, 9, 1, 39, // Skip to: 13726
+/* 3741 */ MCD_OPC_CheckField, 6, 5, 0, 251, 38, // Skip to: 13726
+/* 3747 */ MCD_OPC_Decode, 152, 3, 117, // Opcode: CLZ
+/* 3751 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 3769
+/* 3755 */ MCD_OPC_CheckPredicate, 9, 239, 38, // Skip to: 13726
+/* 3759 */ MCD_OPC_CheckField, 6, 5, 0, 233, 38, // Skip to: 13726
+/* 3765 */ MCD_OPC_Decode, 133, 3, 117, // Opcode: CLO
+/* 3769 */ MCD_OPC_FilterValue, 63, 225, 38, // Skip to: 13726
+/* 3773 */ MCD_OPC_CheckPredicate, 9, 221, 38, // Skip to: 13726
+/* 3777 */ MCD_OPC_Decode, 152, 11, 64, // Opcode: SDBBP
+/* 3781 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 3793
+/* 3785 */ MCD_OPC_CheckPredicate, 9, 209, 38, // Skip to: 13726
+/* 3789 */ MCD_OPC_Decode, 131, 7, 77, // Opcode: JALX
+/* 3793 */ MCD_OPC_FilterValue, 30, 28, 28, // Skip to: 10993
+/* 3797 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 3800 */ MCD_OPC_FilterValue, 0, 50, 0, // Skip to: 3854
+/* 3804 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ...
+/* 3807 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 3818
+/* 3811 */ MCD_OPC_CheckPredicate, 8, 183, 38, // Skip to: 13726
+/* 3815 */ MCD_OPC_Decode, 87, 118, // Opcode: ANDI_B
+/* 3818 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3830
+/* 3822 */ MCD_OPC_CheckPredicate, 8, 172, 38, // Skip to: 13726
+/* 3826 */ MCD_OPC_Decode, 136, 10, 118, // Opcode: ORI_B
+/* 3830 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3842
+/* 3834 */ MCD_OPC_CheckPredicate, 8, 160, 38, // Skip to: 13726
+/* 3838 */ MCD_OPC_Decode, 252, 9, 118, // Opcode: NORI_B
+/* 3842 */ MCD_OPC_FilterValue, 3, 152, 38, // Skip to: 13726
+/* 3846 */ MCD_OPC_CheckPredicate, 8, 148, 38, // Skip to: 13726
+/* 3850 */ MCD_OPC_Decode, 239, 13, 118, // Opcode: XORI_B
+/* 3854 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 3897
+/* 3858 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ...
+/* 3861 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3873
+/* 3865 */ MCD_OPC_CheckPredicate, 8, 129, 38, // Skip to: 13726
+/* 3869 */ MCD_OPC_Decode, 141, 2, 119, // Opcode: BMNZI_B
+/* 3873 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3885
+/* 3877 */ MCD_OPC_CheckPredicate, 8, 117, 38, // Skip to: 13726
+/* 3881 */ MCD_OPC_Decode, 143, 2, 119, // Opcode: BMZI_B
+/* 3885 */ MCD_OPC_FilterValue, 2, 109, 38, // Skip to: 13726
+/* 3889 */ MCD_OPC_CheckPredicate, 8, 105, 38, // Skip to: 13726
+/* 3893 */ MCD_OPC_Decode, 174, 2, 119, // Opcode: BSELI_B
+/* 3897 */ MCD_OPC_FilterValue, 2, 39, 0, // Skip to: 3940
+/* 3901 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ...
+/* 3904 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3916
+/* 3908 */ MCD_OPC_CheckPredicate, 8, 86, 38, // Skip to: 13726
+/* 3912 */ MCD_OPC_Decode, 189, 11, 118, // Opcode: SHF_B
+/* 3916 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3928
+/* 3920 */ MCD_OPC_CheckPredicate, 8, 74, 38, // Skip to: 13726
+/* 3924 */ MCD_OPC_Decode, 190, 11, 120, // Opcode: SHF_H
+/* 3928 */ MCD_OPC_FilterValue, 2, 66, 38, // Skip to: 13726
+/* 3932 */ MCD_OPC_CheckPredicate, 8, 62, 38, // Skip to: 13726
+/* 3936 */ MCD_OPC_Decode, 191, 11, 121, // Opcode: SHF_W
+/* 3940 */ MCD_OPC_FilterValue, 6, 31, 1, // Skip to: 4231
+/* 3944 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 3947 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 3958
+/* 3951 */ MCD_OPC_CheckPredicate, 8, 43, 38, // Skip to: 13726
+/* 3955 */ MCD_OPC_Decode, 59, 122, // Opcode: ADDVI_B
+/* 3958 */ MCD_OPC_FilterValue, 1, 7, 0, // Skip to: 3969
+/* 3962 */ MCD_OPC_CheckPredicate, 8, 32, 38, // Skip to: 13726
+/* 3966 */ MCD_OPC_Decode, 61, 123, // Opcode: ADDVI_H
+/* 3969 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 3980
+/* 3973 */ MCD_OPC_CheckPredicate, 8, 21, 38, // Skip to: 13726
+/* 3977 */ MCD_OPC_Decode, 62, 124, // Opcode: ADDVI_W
+/* 3980 */ MCD_OPC_FilterValue, 3, 7, 0, // Skip to: 3991
+/* 3984 */ MCD_OPC_CheckPredicate, 8, 10, 38, // Skip to: 13726
+/* 3988 */ MCD_OPC_Decode, 60, 125, // Opcode: ADDVI_D
+/* 3991 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 4003
+/* 3995 */ MCD_OPC_CheckPredicate, 8, 255, 37, // Skip to: 13726
+/* 3999 */ MCD_OPC_Decode, 221, 12, 122, // Opcode: SUBVI_B
+/* 4003 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 4015
+/* 4007 */ MCD_OPC_CheckPredicate, 8, 243, 37, // Skip to: 13726
+/* 4011 */ MCD_OPC_Decode, 223, 12, 123, // Opcode: SUBVI_H
+/* 4015 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 4027
+/* 4019 */ MCD_OPC_CheckPredicate, 8, 231, 37, // Skip to: 13726
+/* 4023 */ MCD_OPC_Decode, 224, 12, 124, // Opcode: SUBVI_W
+/* 4027 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 4039
+/* 4031 */ MCD_OPC_CheckPredicate, 8, 219, 37, // Skip to: 13726
+/* 4035 */ MCD_OPC_Decode, 222, 12, 125, // Opcode: SUBVI_D
+/* 4039 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 4051
+/* 4043 */ MCD_OPC_CheckPredicate, 8, 207, 37, // Skip to: 13726
+/* 4047 */ MCD_OPC_Decode, 157, 8, 122, // Opcode: MAXI_S_B
+/* 4051 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 4063
+/* 4055 */ MCD_OPC_CheckPredicate, 8, 195, 37, // Skip to: 13726
+/* 4059 */ MCD_OPC_Decode, 159, 8, 123, // Opcode: MAXI_S_H
+/* 4063 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 4075
+/* 4067 */ MCD_OPC_CheckPredicate, 8, 183, 37, // Skip to: 13726
+/* 4071 */ MCD_OPC_Decode, 160, 8, 124, // Opcode: MAXI_S_W
+/* 4075 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 4087
+/* 4079 */ MCD_OPC_CheckPredicate, 8, 171, 37, // Skip to: 13726
+/* 4083 */ MCD_OPC_Decode, 158, 8, 125, // Opcode: MAXI_S_D
+/* 4087 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 4099
+/* 4091 */ MCD_OPC_CheckPredicate, 8, 159, 37, // Skip to: 13726
+/* 4095 */ MCD_OPC_Decode, 161, 8, 122, // Opcode: MAXI_U_B
+/* 4099 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 4111
+/* 4103 */ MCD_OPC_CheckPredicate, 8, 147, 37, // Skip to: 13726
+/* 4107 */ MCD_OPC_Decode, 163, 8, 123, // Opcode: MAXI_U_H
+/* 4111 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 4123
+/* 4115 */ MCD_OPC_CheckPredicate, 8, 135, 37, // Skip to: 13726
+/* 4119 */ MCD_OPC_Decode, 164, 8, 124, // Opcode: MAXI_U_W
+/* 4123 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 4135
+/* 4127 */ MCD_OPC_CheckPredicate, 8, 123, 37, // Skip to: 13726
+/* 4131 */ MCD_OPC_Decode, 162, 8, 125, // Opcode: MAXI_U_D
+/* 4135 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 4147
+/* 4139 */ MCD_OPC_CheckPredicate, 8, 111, 37, // Skip to: 13726
+/* 4143 */ MCD_OPC_Decode, 198, 8, 122, // Opcode: MINI_S_B
+/* 4147 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 4159
+/* 4151 */ MCD_OPC_CheckPredicate, 8, 99, 37, // Skip to: 13726
+/* 4155 */ MCD_OPC_Decode, 200, 8, 123, // Opcode: MINI_S_H
+/* 4159 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 4171
+/* 4163 */ MCD_OPC_CheckPredicate, 8, 87, 37, // Skip to: 13726
+/* 4167 */ MCD_OPC_Decode, 201, 8, 124, // Opcode: MINI_S_W
+/* 4171 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 4183
+/* 4175 */ MCD_OPC_CheckPredicate, 8, 75, 37, // Skip to: 13726
+/* 4179 */ MCD_OPC_Decode, 199, 8, 125, // Opcode: MINI_S_D
+/* 4183 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 4195
+/* 4187 */ MCD_OPC_CheckPredicate, 8, 63, 37, // Skip to: 13726
+/* 4191 */ MCD_OPC_Decode, 202, 8, 122, // Opcode: MINI_U_B
+/* 4195 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 4207
+/* 4199 */ MCD_OPC_CheckPredicate, 8, 51, 37, // Skip to: 13726
+/* 4203 */ MCD_OPC_Decode, 204, 8, 123, // Opcode: MINI_U_H
+/* 4207 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 4219
+/* 4211 */ MCD_OPC_CheckPredicate, 8, 39, 37, // Skip to: 13726
+/* 4215 */ MCD_OPC_Decode, 205, 8, 124, // Opcode: MINI_U_W
+/* 4219 */ MCD_OPC_FilterValue, 23, 31, 37, // Skip to: 13726
+/* 4223 */ MCD_OPC_CheckPredicate, 8, 27, 37, // Skip to: 13726
+/* 4227 */ MCD_OPC_Decode, 203, 8, 125, // Opcode: MINI_U_D
+/* 4231 */ MCD_OPC_FilterValue, 7, 37, 1, // Skip to: 4528
+/* 4235 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 4238 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4250
+/* 4242 */ MCD_OPC_CheckPredicate, 8, 8, 37, // Skip to: 13726
+/* 4246 */ MCD_OPC_Decode, 230, 2, 122, // Opcode: CEQI_B
+/* 4250 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 4262
+/* 4254 */ MCD_OPC_CheckPredicate, 8, 252, 36, // Skip to: 13726
+/* 4258 */ MCD_OPC_Decode, 232, 2, 123, // Opcode: CEQI_H
+/* 4262 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 4274
+/* 4266 */ MCD_OPC_CheckPredicate, 8, 240, 36, // Skip to: 13726
+/* 4270 */ MCD_OPC_Decode, 233, 2, 124, // Opcode: CEQI_W
+/* 4274 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 4286
+/* 4278 */ MCD_OPC_CheckPredicate, 8, 228, 36, // Skip to: 13726
+/* 4282 */ MCD_OPC_Decode, 231, 2, 125, // Opcode: CEQI_D
+/* 4286 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 4298
+/* 4290 */ MCD_OPC_CheckPredicate, 8, 216, 36, // Skip to: 13726
+/* 4294 */ MCD_OPC_Decode, 136, 3, 122, // Opcode: CLTI_S_B
+/* 4298 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 4310
+/* 4302 */ MCD_OPC_CheckPredicate, 8, 204, 36, // Skip to: 13726
+/* 4306 */ MCD_OPC_Decode, 138, 3, 123, // Opcode: CLTI_S_H
+/* 4310 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 4322
+/* 4314 */ MCD_OPC_CheckPredicate, 8, 192, 36, // Skip to: 13726
+/* 4318 */ MCD_OPC_Decode, 139, 3, 124, // Opcode: CLTI_S_W
+/* 4322 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 4334
+/* 4326 */ MCD_OPC_CheckPredicate, 8, 180, 36, // Skip to: 13726
+/* 4330 */ MCD_OPC_Decode, 137, 3, 125, // Opcode: CLTI_S_D
+/* 4334 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 4346
+/* 4338 */ MCD_OPC_CheckPredicate, 8, 168, 36, // Skip to: 13726
+/* 4342 */ MCD_OPC_Decode, 140, 3, 122, // Opcode: CLTI_U_B
+/* 4346 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 4358
+/* 4350 */ MCD_OPC_CheckPredicate, 8, 156, 36, // Skip to: 13726
+/* 4354 */ MCD_OPC_Decode, 142, 3, 123, // Opcode: CLTI_U_H
+/* 4358 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 4370
+/* 4362 */ MCD_OPC_CheckPredicate, 8, 144, 36, // Skip to: 13726
+/* 4366 */ MCD_OPC_Decode, 143, 3, 124, // Opcode: CLTI_U_W
+/* 4370 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 4382
+/* 4374 */ MCD_OPC_CheckPredicate, 8, 132, 36, // Skip to: 13726
+/* 4378 */ MCD_OPC_Decode, 141, 3, 125, // Opcode: CLTI_U_D
+/* 4382 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 4394
+/* 4386 */ MCD_OPC_CheckPredicate, 8, 120, 36, // Skip to: 13726
+/* 4390 */ MCD_OPC_Decode, 245, 2, 122, // Opcode: CLEI_S_B
+/* 4394 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 4406
+/* 4398 */ MCD_OPC_CheckPredicate, 8, 108, 36, // Skip to: 13726
+/* 4402 */ MCD_OPC_Decode, 247, 2, 123, // Opcode: CLEI_S_H
+/* 4406 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 4418
+/* 4410 */ MCD_OPC_CheckPredicate, 8, 96, 36, // Skip to: 13726
+/* 4414 */ MCD_OPC_Decode, 248, 2, 124, // Opcode: CLEI_S_W
+/* 4418 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 4430
+/* 4422 */ MCD_OPC_CheckPredicate, 8, 84, 36, // Skip to: 13726
+/* 4426 */ MCD_OPC_Decode, 246, 2, 125, // Opcode: CLEI_S_D
+/* 4430 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 4442
+/* 4434 */ MCD_OPC_CheckPredicate, 8, 72, 36, // Skip to: 13726
+/* 4438 */ MCD_OPC_Decode, 249, 2, 122, // Opcode: CLEI_U_B
+/* 4442 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 4454
+/* 4446 */ MCD_OPC_CheckPredicate, 8, 60, 36, // Skip to: 13726
+/* 4450 */ MCD_OPC_Decode, 251, 2, 123, // Opcode: CLEI_U_H
+/* 4454 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 4466
+/* 4458 */ MCD_OPC_CheckPredicate, 8, 48, 36, // Skip to: 13726
+/* 4462 */ MCD_OPC_Decode, 252, 2, 124, // Opcode: CLEI_U_W
+/* 4466 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 4478
+/* 4470 */ MCD_OPC_CheckPredicate, 8, 36, 36, // Skip to: 13726
+/* 4474 */ MCD_OPC_Decode, 250, 2, 125, // Opcode: CLEI_U_D
+/* 4478 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 4490
+/* 4482 */ MCD_OPC_CheckPredicate, 8, 24, 36, // Skip to: 13726
+/* 4486 */ MCD_OPC_Decode, 168, 7, 126, // Opcode: LDI_B
+/* 4490 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 4502
+/* 4494 */ MCD_OPC_CheckPredicate, 8, 12, 36, // Skip to: 13726
+/* 4498 */ MCD_OPC_Decode, 170, 7, 127, // Opcode: LDI_H
+/* 4502 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 4515
+/* 4506 */ MCD_OPC_CheckPredicate, 8, 0, 36, // Skip to: 13726
+/* 4510 */ MCD_OPC_Decode, 171, 7, 128, 1, // Opcode: LDI_W
+/* 4515 */ MCD_OPC_FilterValue, 27, 247, 35, // Skip to: 13726
+/* 4519 */ MCD_OPC_CheckPredicate, 8, 243, 35, // Skip to: 13726
+/* 4523 */ MCD_OPC_Decode, 169, 7, 129, 1, // Opcode: LDI_D
+/* 4528 */ MCD_OPC_FilterValue, 9, 61, 2, // Skip to: 5105
+/* 4532 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ...
+/* 4535 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4548
+/* 4539 */ MCD_OPC_CheckPredicate, 8, 223, 35, // Skip to: 13726
+/* 4543 */ MCD_OPC_Decode, 230, 11, 130, 1, // Opcode: SLLI_D
+/* 4548 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 4606
+/* 4552 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 4555 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4567
+/* 4559 */ MCD_OPC_CheckPredicate, 8, 203, 35, // Skip to: 13726
+/* 4563 */ MCD_OPC_Decode, 232, 11, 124, // Opcode: SLLI_W
+/* 4567 */ MCD_OPC_FilterValue, 1, 195, 35, // Skip to: 13726
+/* 4571 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 4574 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4587
+/* 4578 */ MCD_OPC_CheckPredicate, 8, 184, 35, // Skip to: 13726
+/* 4582 */ MCD_OPC_Decode, 231, 11, 131, 1, // Opcode: SLLI_H
+/* 4587 */ MCD_OPC_FilterValue, 1, 175, 35, // Skip to: 13726
+/* 4591 */ MCD_OPC_CheckPredicate, 8, 171, 35, // Skip to: 13726
+/* 4595 */ MCD_OPC_CheckField, 19, 1, 0, 165, 35, // Skip to: 13726
+/* 4601 */ MCD_OPC_Decode, 229, 11, 132, 1, // Opcode: SLLI_B
+/* 4606 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4619
+/* 4610 */ MCD_OPC_CheckPredicate, 8, 152, 35, // Skip to: 13726
+/* 4614 */ MCD_OPC_Decode, 141, 12, 130, 1, // Opcode: SRAI_D
+/* 4619 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 4677
+/* 4623 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 4626 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4638
+/* 4630 */ MCD_OPC_CheckPredicate, 8, 132, 35, // Skip to: 13726
+/* 4634 */ MCD_OPC_Decode, 143, 12, 124, // Opcode: SRAI_W
+/* 4638 */ MCD_OPC_FilterValue, 1, 124, 35, // Skip to: 13726
+/* 4642 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 4645 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4658
+/* 4649 */ MCD_OPC_CheckPredicate, 8, 113, 35, // Skip to: 13726
+/* 4653 */ MCD_OPC_Decode, 142, 12, 131, 1, // Opcode: SRAI_H
+/* 4658 */ MCD_OPC_FilterValue, 1, 104, 35, // Skip to: 13726
+/* 4662 */ MCD_OPC_CheckPredicate, 8, 100, 35, // Skip to: 13726
+/* 4666 */ MCD_OPC_CheckField, 19, 1, 0, 94, 35, // Skip to: 13726
+/* 4672 */ MCD_OPC_Decode, 140, 12, 132, 1, // Opcode: SRAI_B
+/* 4677 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 4690
+/* 4681 */ MCD_OPC_CheckPredicate, 8, 81, 35, // Skip to: 13726
+/* 4685 */ MCD_OPC_Decode, 162, 12, 130, 1, // Opcode: SRLI_D
+/* 4690 */ MCD_OPC_FilterValue, 5, 54, 0, // Skip to: 4748
+/* 4694 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 4697 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4709
+/* 4701 */ MCD_OPC_CheckPredicate, 8, 61, 35, // Skip to: 13726
+/* 4705 */ MCD_OPC_Decode, 164, 12, 124, // Opcode: SRLI_W
+/* 4709 */ MCD_OPC_FilterValue, 1, 53, 35, // Skip to: 13726
+/* 4713 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 4716 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4729
+/* 4720 */ MCD_OPC_CheckPredicate, 8, 42, 35, // Skip to: 13726
+/* 4724 */ MCD_OPC_Decode, 163, 12, 131, 1, // Opcode: SRLI_H
+/* 4729 */ MCD_OPC_FilterValue, 1, 33, 35, // Skip to: 13726
+/* 4733 */ MCD_OPC_CheckPredicate, 8, 29, 35, // Skip to: 13726
+/* 4737 */ MCD_OPC_CheckField, 19, 1, 0, 23, 35, // Skip to: 13726
+/* 4743 */ MCD_OPC_Decode, 161, 12, 132, 1, // Opcode: SRLI_B
+/* 4748 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 4761
+/* 4752 */ MCD_OPC_CheckPredicate, 8, 10, 35, // Skip to: 13726
+/* 4756 */ MCD_OPC_Decode, 199, 1, 130, 1, // Opcode: BCLRI_D
+/* 4761 */ MCD_OPC_FilterValue, 7, 54, 0, // Skip to: 4819
+/* 4765 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 4768 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4780
+/* 4772 */ MCD_OPC_CheckPredicate, 8, 246, 34, // Skip to: 13726
+/* 4776 */ MCD_OPC_Decode, 201, 1, 124, // Opcode: BCLRI_W
+/* 4780 */ MCD_OPC_FilterValue, 1, 238, 34, // Skip to: 13726
+/* 4784 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 4787 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4800
+/* 4791 */ MCD_OPC_CheckPredicate, 8, 227, 34, // Skip to: 13726
+/* 4795 */ MCD_OPC_Decode, 200, 1, 131, 1, // Opcode: BCLRI_H
+/* 4800 */ MCD_OPC_FilterValue, 1, 218, 34, // Skip to: 13726
+/* 4804 */ MCD_OPC_CheckPredicate, 8, 214, 34, // Skip to: 13726
+/* 4808 */ MCD_OPC_CheckField, 19, 1, 0, 208, 34, // Skip to: 13726
+/* 4814 */ MCD_OPC_Decode, 198, 1, 132, 1, // Opcode: BCLRI_B
+/* 4819 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 4832
+/* 4823 */ MCD_OPC_CheckPredicate, 8, 195, 34, // Skip to: 13726
+/* 4827 */ MCD_OPC_Decode, 182, 2, 130, 1, // Opcode: BSETI_D
+/* 4832 */ MCD_OPC_FilterValue, 9, 54, 0, // Skip to: 4890
+/* 4836 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 4839 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4851
+/* 4843 */ MCD_OPC_CheckPredicate, 8, 175, 34, // Skip to: 13726
+/* 4847 */ MCD_OPC_Decode, 184, 2, 124, // Opcode: BSETI_W
+/* 4851 */ MCD_OPC_FilterValue, 1, 167, 34, // Skip to: 13726
+/* 4855 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 4858 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4871
+/* 4862 */ MCD_OPC_CheckPredicate, 8, 156, 34, // Skip to: 13726
+/* 4866 */ MCD_OPC_Decode, 183, 2, 131, 1, // Opcode: BSETI_H
+/* 4871 */ MCD_OPC_FilterValue, 1, 147, 34, // Skip to: 13726
+/* 4875 */ MCD_OPC_CheckPredicate, 8, 143, 34, // Skip to: 13726
+/* 4879 */ MCD_OPC_CheckField, 19, 1, 0, 137, 34, // Skip to: 13726
+/* 4885 */ MCD_OPC_Decode, 181, 2, 132, 1, // Opcode: BSETI_B
+/* 4890 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 4903
+/* 4894 */ MCD_OPC_CheckPredicate, 8, 124, 34, // Skip to: 13726
+/* 4898 */ MCD_OPC_Decode, 149, 2, 130, 1, // Opcode: BNEGI_D
+/* 4903 */ MCD_OPC_FilterValue, 11, 54, 0, // Skip to: 4961
+/* 4907 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 4910 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4922
+/* 4914 */ MCD_OPC_CheckPredicate, 8, 104, 34, // Skip to: 13726
+/* 4918 */ MCD_OPC_Decode, 151, 2, 124, // Opcode: BNEGI_W
+/* 4922 */ MCD_OPC_FilterValue, 1, 96, 34, // Skip to: 13726
+/* 4926 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 4929 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4942
+/* 4933 */ MCD_OPC_CheckPredicate, 8, 85, 34, // Skip to: 13726
+/* 4937 */ MCD_OPC_Decode, 150, 2, 131, 1, // Opcode: BNEGI_H
+/* 4942 */ MCD_OPC_FilterValue, 1, 76, 34, // Skip to: 13726
+/* 4946 */ MCD_OPC_CheckPredicate, 8, 72, 34, // Skip to: 13726
+/* 4950 */ MCD_OPC_CheckField, 19, 1, 0, 66, 34, // Skip to: 13726
+/* 4956 */ MCD_OPC_Decode, 148, 2, 132, 1, // Opcode: BNEGI_B
+/* 4961 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 4974
+/* 4965 */ MCD_OPC_CheckPredicate, 8, 53, 34, // Skip to: 13726
+/* 4969 */ MCD_OPC_Decode, 234, 1, 133, 1, // Opcode: BINSLI_D
+/* 4974 */ MCD_OPC_FilterValue, 13, 55, 0, // Skip to: 5033
+/* 4978 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 4981 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4994
+/* 4985 */ MCD_OPC_CheckPredicate, 8, 33, 34, // Skip to: 13726
+/* 4989 */ MCD_OPC_Decode, 236, 1, 134, 1, // Opcode: BINSLI_W
+/* 4994 */ MCD_OPC_FilterValue, 1, 24, 34, // Skip to: 13726
+/* 4998 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 5001 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5014
+/* 5005 */ MCD_OPC_CheckPredicate, 8, 13, 34, // Skip to: 13726
+/* 5009 */ MCD_OPC_Decode, 235, 1, 135, 1, // Opcode: BINSLI_H
+/* 5014 */ MCD_OPC_FilterValue, 1, 4, 34, // Skip to: 13726
+/* 5018 */ MCD_OPC_CheckPredicate, 8, 0, 34, // Skip to: 13726
+/* 5022 */ MCD_OPC_CheckField, 19, 1, 0, 250, 33, // Skip to: 13726
+/* 5028 */ MCD_OPC_Decode, 233, 1, 136, 1, // Opcode: BINSLI_B
+/* 5033 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 5046
+/* 5037 */ MCD_OPC_CheckPredicate, 8, 237, 33, // Skip to: 13726
+/* 5041 */ MCD_OPC_Decode, 242, 1, 133, 1, // Opcode: BINSRI_D
+/* 5046 */ MCD_OPC_FilterValue, 15, 228, 33, // Skip to: 13726
+/* 5050 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 5053 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5066
+/* 5057 */ MCD_OPC_CheckPredicate, 8, 217, 33, // Skip to: 13726
+/* 5061 */ MCD_OPC_Decode, 244, 1, 134, 1, // Opcode: BINSRI_W
+/* 5066 */ MCD_OPC_FilterValue, 1, 208, 33, // Skip to: 13726
+/* 5070 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 5073 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5086
+/* 5077 */ MCD_OPC_CheckPredicate, 8, 197, 33, // Skip to: 13726
+/* 5081 */ MCD_OPC_Decode, 243, 1, 135, 1, // Opcode: BINSRI_H
+/* 5086 */ MCD_OPC_FilterValue, 1, 188, 33, // Skip to: 13726
+/* 5090 */ MCD_OPC_CheckPredicate, 8, 184, 33, // Skip to: 13726
+/* 5094 */ MCD_OPC_CheckField, 19, 1, 0, 178, 33, // Skip to: 13726
+/* 5100 */ MCD_OPC_Decode, 241, 1, 136, 1, // Opcode: BINSRI_B
+/* 5105 */ MCD_OPC_FilterValue, 10, 31, 1, // Skip to: 5396
+/* 5109 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ...
+/* 5112 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5125
+/* 5116 */ MCD_OPC_CheckPredicate, 8, 158, 33, // Skip to: 13726
+/* 5120 */ MCD_OPC_Decode, 135, 11, 130, 1, // Opcode: SAT_S_D
+/* 5125 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 5183
+/* 5129 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 5132 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5144
+/* 5136 */ MCD_OPC_CheckPredicate, 8, 138, 33, // Skip to: 13726
+/* 5140 */ MCD_OPC_Decode, 137, 11, 124, // Opcode: SAT_S_W
+/* 5144 */ MCD_OPC_FilterValue, 1, 130, 33, // Skip to: 13726
+/* 5148 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 5151 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5164
+/* 5155 */ MCD_OPC_CheckPredicate, 8, 119, 33, // Skip to: 13726
+/* 5159 */ MCD_OPC_Decode, 136, 11, 131, 1, // Opcode: SAT_S_H
+/* 5164 */ MCD_OPC_FilterValue, 1, 110, 33, // Skip to: 13726
+/* 5168 */ MCD_OPC_CheckPredicate, 8, 106, 33, // Skip to: 13726
+/* 5172 */ MCD_OPC_CheckField, 19, 1, 0, 100, 33, // Skip to: 13726
+/* 5178 */ MCD_OPC_Decode, 134, 11, 132, 1, // Opcode: SAT_S_B
+/* 5183 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5196
+/* 5187 */ MCD_OPC_CheckPredicate, 8, 87, 33, // Skip to: 13726
+/* 5191 */ MCD_OPC_Decode, 139, 11, 130, 1, // Opcode: SAT_U_D
+/* 5196 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 5254
+/* 5200 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 5203 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5215
+/* 5207 */ MCD_OPC_CheckPredicate, 8, 67, 33, // Skip to: 13726
+/* 5211 */ MCD_OPC_Decode, 141, 11, 124, // Opcode: SAT_U_W
+/* 5215 */ MCD_OPC_FilterValue, 1, 59, 33, // Skip to: 13726
+/* 5219 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 5222 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5235
+/* 5226 */ MCD_OPC_CheckPredicate, 8, 48, 33, // Skip to: 13726
+/* 5230 */ MCD_OPC_Decode, 140, 11, 131, 1, // Opcode: SAT_U_H
+/* 5235 */ MCD_OPC_FilterValue, 1, 39, 33, // Skip to: 13726
+/* 5239 */ MCD_OPC_CheckPredicate, 8, 35, 33, // Skip to: 13726
+/* 5243 */ MCD_OPC_CheckField, 19, 1, 0, 29, 33, // Skip to: 13726
+/* 5249 */ MCD_OPC_Decode, 138, 11, 132, 1, // Opcode: SAT_U_B
+/* 5254 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 5267
+/* 5258 */ MCD_OPC_CheckPredicate, 8, 16, 33, // Skip to: 13726
+/* 5262 */ MCD_OPC_Decode, 145, 12, 130, 1, // Opcode: SRARI_D
+/* 5267 */ MCD_OPC_FilterValue, 5, 54, 0, // Skip to: 5325
+/* 5271 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 5274 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5286
+/* 5278 */ MCD_OPC_CheckPredicate, 8, 252, 32, // Skip to: 13726
+/* 5282 */ MCD_OPC_Decode, 147, 12, 124, // Opcode: SRARI_W
+/* 5286 */ MCD_OPC_FilterValue, 1, 244, 32, // Skip to: 13726
+/* 5290 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 5293 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5306
+/* 5297 */ MCD_OPC_CheckPredicate, 8, 233, 32, // Skip to: 13726
+/* 5301 */ MCD_OPC_Decode, 146, 12, 131, 1, // Opcode: SRARI_H
+/* 5306 */ MCD_OPC_FilterValue, 1, 224, 32, // Skip to: 13726
+/* 5310 */ MCD_OPC_CheckPredicate, 8, 220, 32, // Skip to: 13726
+/* 5314 */ MCD_OPC_CheckField, 19, 1, 0, 214, 32, // Skip to: 13726
+/* 5320 */ MCD_OPC_Decode, 144, 12, 132, 1, // Opcode: SRARI_B
+/* 5325 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 5338
+/* 5329 */ MCD_OPC_CheckPredicate, 8, 201, 32, // Skip to: 13726
+/* 5333 */ MCD_OPC_Decode, 166, 12, 130, 1, // Opcode: SRLRI_D
+/* 5338 */ MCD_OPC_FilterValue, 7, 192, 32, // Skip to: 13726
+/* 5342 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 5345 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5357
+/* 5349 */ MCD_OPC_CheckPredicate, 8, 181, 32, // Skip to: 13726
+/* 5353 */ MCD_OPC_Decode, 168, 12, 124, // Opcode: SRLRI_W
+/* 5357 */ MCD_OPC_FilterValue, 1, 173, 32, // Skip to: 13726
+/* 5361 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 5364 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5377
+/* 5368 */ MCD_OPC_CheckPredicate, 8, 162, 32, // Skip to: 13726
+/* 5372 */ MCD_OPC_Decode, 167, 12, 131, 1, // Opcode: SRLRI_H
+/* 5377 */ MCD_OPC_FilterValue, 1, 153, 32, // Skip to: 13726
+/* 5381 */ MCD_OPC_CheckPredicate, 8, 149, 32, // Skip to: 13726
+/* 5385 */ MCD_OPC_CheckField, 19, 1, 0, 143, 32, // Skip to: 13726
+/* 5391 */ MCD_OPC_Decode, 165, 12, 132, 1, // Opcode: SRLRI_B
+/* 5396 */ MCD_OPC_FilterValue, 13, 163, 1, // Skip to: 5819
+/* 5400 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 5403 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5416
+/* 5407 */ MCD_OPC_CheckPredicate, 8, 123, 32, // Skip to: 13726
+/* 5411 */ MCD_OPC_Decode, 235, 11, 137, 1, // Opcode: SLL_B
+/* 5416 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5429
+/* 5420 */ MCD_OPC_CheckPredicate, 8, 110, 32, // Skip to: 13726
+/* 5424 */ MCD_OPC_Decode, 237, 11, 138, 1, // Opcode: SLL_H
+/* 5429 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5442
+/* 5433 */ MCD_OPC_CheckPredicate, 8, 97, 32, // Skip to: 13726
+/* 5437 */ MCD_OPC_Decode, 239, 11, 139, 1, // Opcode: SLL_W
+/* 5442 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5455
+/* 5446 */ MCD_OPC_CheckPredicate, 8, 84, 32, // Skip to: 13726
+/* 5450 */ MCD_OPC_Decode, 236, 11, 140, 1, // Opcode: SLL_D
+/* 5455 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 5468
+/* 5459 */ MCD_OPC_CheckPredicate, 8, 71, 32, // Skip to: 13726
+/* 5463 */ MCD_OPC_Decode, 154, 12, 137, 1, // Opcode: SRA_B
+/* 5468 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 5481
+/* 5472 */ MCD_OPC_CheckPredicate, 8, 58, 32, // Skip to: 13726
+/* 5476 */ MCD_OPC_Decode, 156, 12, 138, 1, // Opcode: SRA_H
+/* 5481 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 5494
+/* 5485 */ MCD_OPC_CheckPredicate, 8, 45, 32, // Skip to: 13726
+/* 5489 */ MCD_OPC_Decode, 158, 12, 139, 1, // Opcode: SRA_W
+/* 5494 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 5507
+/* 5498 */ MCD_OPC_CheckPredicate, 8, 32, 32, // Skip to: 13726
+/* 5502 */ MCD_OPC_Decode, 155, 12, 140, 1, // Opcode: SRA_D
+/* 5507 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 5520
+/* 5511 */ MCD_OPC_CheckPredicate, 8, 19, 32, // Skip to: 13726
+/* 5515 */ MCD_OPC_Decode, 175, 12, 137, 1, // Opcode: SRL_B
+/* 5520 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 5533
+/* 5524 */ MCD_OPC_CheckPredicate, 8, 6, 32, // Skip to: 13726
+/* 5528 */ MCD_OPC_Decode, 177, 12, 138, 1, // Opcode: SRL_H
+/* 5533 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 5546
+/* 5537 */ MCD_OPC_CheckPredicate, 8, 249, 31, // Skip to: 13726
+/* 5541 */ MCD_OPC_Decode, 179, 12, 139, 1, // Opcode: SRL_W
+/* 5546 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 5559
+/* 5550 */ MCD_OPC_CheckPredicate, 8, 236, 31, // Skip to: 13726
+/* 5554 */ MCD_OPC_Decode, 176, 12, 140, 1, // Opcode: SRL_D
+/* 5559 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 5572
+/* 5563 */ MCD_OPC_CheckPredicate, 8, 223, 31, // Skip to: 13726
+/* 5567 */ MCD_OPC_Decode, 202, 1, 137, 1, // Opcode: BCLR_B
+/* 5572 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 5585
+/* 5576 */ MCD_OPC_CheckPredicate, 8, 210, 31, // Skip to: 13726
+/* 5580 */ MCD_OPC_Decode, 204, 1, 138, 1, // Opcode: BCLR_H
+/* 5585 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 5598
+/* 5589 */ MCD_OPC_CheckPredicate, 8, 197, 31, // Skip to: 13726
+/* 5593 */ MCD_OPC_Decode, 205, 1, 139, 1, // Opcode: BCLR_W
+/* 5598 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 5611
+/* 5602 */ MCD_OPC_CheckPredicate, 8, 184, 31, // Skip to: 13726
+/* 5606 */ MCD_OPC_Decode, 203, 1, 140, 1, // Opcode: BCLR_D
+/* 5611 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 5624
+/* 5615 */ MCD_OPC_CheckPredicate, 8, 171, 31, // Skip to: 13726
+/* 5619 */ MCD_OPC_Decode, 185, 2, 137, 1, // Opcode: BSET_B
+/* 5624 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 5637
+/* 5628 */ MCD_OPC_CheckPredicate, 8, 158, 31, // Skip to: 13726
+/* 5632 */ MCD_OPC_Decode, 187, 2, 138, 1, // Opcode: BSET_H
+/* 5637 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 5650
+/* 5641 */ MCD_OPC_CheckPredicate, 8, 145, 31, // Skip to: 13726
+/* 5645 */ MCD_OPC_Decode, 188, 2, 139, 1, // Opcode: BSET_W
+/* 5650 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 5663
+/* 5654 */ MCD_OPC_CheckPredicate, 8, 132, 31, // Skip to: 13726
+/* 5658 */ MCD_OPC_Decode, 186, 2, 140, 1, // Opcode: BSET_D
+/* 5663 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 5676
+/* 5667 */ MCD_OPC_CheckPredicate, 8, 119, 31, // Skip to: 13726
+/* 5671 */ MCD_OPC_Decode, 152, 2, 137, 1, // Opcode: BNEG_B
+/* 5676 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 5689
+/* 5680 */ MCD_OPC_CheckPredicate, 8, 106, 31, // Skip to: 13726
+/* 5684 */ MCD_OPC_Decode, 154, 2, 138, 1, // Opcode: BNEG_H
+/* 5689 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 5702
+/* 5693 */ MCD_OPC_CheckPredicate, 8, 93, 31, // Skip to: 13726
+/* 5697 */ MCD_OPC_Decode, 155, 2, 139, 1, // Opcode: BNEG_W
+/* 5702 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 5715
+/* 5706 */ MCD_OPC_CheckPredicate, 8, 80, 31, // Skip to: 13726
+/* 5710 */ MCD_OPC_Decode, 153, 2, 140, 1, // Opcode: BNEG_D
+/* 5715 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 5728
+/* 5719 */ MCD_OPC_CheckPredicate, 8, 67, 31, // Skip to: 13726
+/* 5723 */ MCD_OPC_Decode, 237, 1, 141, 1, // Opcode: BINSL_B
+/* 5728 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 5741
+/* 5732 */ MCD_OPC_CheckPredicate, 8, 54, 31, // Skip to: 13726
+/* 5736 */ MCD_OPC_Decode, 239, 1, 142, 1, // Opcode: BINSL_H
+/* 5741 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 5754
+/* 5745 */ MCD_OPC_CheckPredicate, 8, 41, 31, // Skip to: 13726
+/* 5749 */ MCD_OPC_Decode, 240, 1, 143, 1, // Opcode: BINSL_W
+/* 5754 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 5767
+/* 5758 */ MCD_OPC_CheckPredicate, 8, 28, 31, // Skip to: 13726
+/* 5762 */ MCD_OPC_Decode, 238, 1, 144, 1, // Opcode: BINSL_D
+/* 5767 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 5780
+/* 5771 */ MCD_OPC_CheckPredicate, 8, 15, 31, // Skip to: 13726
+/* 5775 */ MCD_OPC_Decode, 245, 1, 141, 1, // Opcode: BINSR_B
+/* 5780 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 5793
+/* 5784 */ MCD_OPC_CheckPredicate, 8, 2, 31, // Skip to: 13726
+/* 5788 */ MCD_OPC_Decode, 247, 1, 142, 1, // Opcode: BINSR_H
+/* 5793 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 5806
+/* 5797 */ MCD_OPC_CheckPredicate, 8, 245, 30, // Skip to: 13726
+/* 5801 */ MCD_OPC_Decode, 248, 1, 143, 1, // Opcode: BINSR_W
+/* 5806 */ MCD_OPC_FilterValue, 31, 236, 30, // Skip to: 13726
+/* 5810 */ MCD_OPC_CheckPredicate, 8, 232, 30, // Skip to: 13726
+/* 5814 */ MCD_OPC_Decode, 246, 1, 144, 1, // Opcode: BINSR_D
+/* 5819 */ MCD_OPC_FilterValue, 14, 159, 1, // Skip to: 6238
+/* 5823 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 5826 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5838
+/* 5830 */ MCD_OPC_CheckPredicate, 8, 212, 30, // Skip to: 13726
+/* 5834 */ MCD_OPC_Decode, 63, 137, 1, // Opcode: ADDV_B
+/* 5838 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5850
+/* 5842 */ MCD_OPC_CheckPredicate, 8, 200, 30, // Skip to: 13726
+/* 5846 */ MCD_OPC_Decode, 65, 138, 1, // Opcode: ADDV_H
+/* 5850 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5862
+/* 5854 */ MCD_OPC_CheckPredicate, 8, 188, 30, // Skip to: 13726
+/* 5858 */ MCD_OPC_Decode, 66, 139, 1, // Opcode: ADDV_W
+/* 5862 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 5874
+/* 5866 */ MCD_OPC_CheckPredicate, 8, 176, 30, // Skip to: 13726
+/* 5870 */ MCD_OPC_Decode, 64, 140, 1, // Opcode: ADDV_D
+/* 5874 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 5887
+/* 5878 */ MCD_OPC_CheckPredicate, 8, 164, 30, // Skip to: 13726
+/* 5882 */ MCD_OPC_Decode, 225, 12, 137, 1, // Opcode: SUBV_B
+/* 5887 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 5900
+/* 5891 */ MCD_OPC_CheckPredicate, 8, 151, 30, // Skip to: 13726
+/* 5895 */ MCD_OPC_Decode, 227, 12, 138, 1, // Opcode: SUBV_H
+/* 5900 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 5913
+/* 5904 */ MCD_OPC_CheckPredicate, 8, 138, 30, // Skip to: 13726
+/* 5908 */ MCD_OPC_Decode, 228, 12, 139, 1, // Opcode: SUBV_W
+/* 5913 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 5926
+/* 5917 */ MCD_OPC_CheckPredicate, 8, 125, 30, // Skip to: 13726
+/* 5921 */ MCD_OPC_Decode, 226, 12, 140, 1, // Opcode: SUBV_D
+/* 5926 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 5939
+/* 5930 */ MCD_OPC_CheckPredicate, 8, 112, 30, // Skip to: 13726
+/* 5934 */ MCD_OPC_Decode, 171, 8, 137, 1, // Opcode: MAX_S_B
+/* 5939 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 5952
+/* 5943 */ MCD_OPC_CheckPredicate, 8, 99, 30, // Skip to: 13726
+/* 5947 */ MCD_OPC_Decode, 173, 8, 138, 1, // Opcode: MAX_S_H
+/* 5952 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 5965
+/* 5956 */ MCD_OPC_CheckPredicate, 8, 86, 30, // Skip to: 13726
+/* 5960 */ MCD_OPC_Decode, 174, 8, 139, 1, // Opcode: MAX_S_W
+/* 5965 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 5978
+/* 5969 */ MCD_OPC_CheckPredicate, 8, 73, 30, // Skip to: 13726
+/* 5973 */ MCD_OPC_Decode, 172, 8, 140, 1, // Opcode: MAX_S_D
+/* 5978 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 5991
+/* 5982 */ MCD_OPC_CheckPredicate, 8, 60, 30, // Skip to: 13726
+/* 5986 */ MCD_OPC_Decode, 175, 8, 137, 1, // Opcode: MAX_U_B
+/* 5991 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 6004
+/* 5995 */ MCD_OPC_CheckPredicate, 8, 47, 30, // Skip to: 13726
+/* 5999 */ MCD_OPC_Decode, 177, 8, 138, 1, // Opcode: MAX_U_H
+/* 6004 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 6017
+/* 6008 */ MCD_OPC_CheckPredicate, 8, 34, 30, // Skip to: 13726
+/* 6012 */ MCD_OPC_Decode, 178, 8, 139, 1, // Opcode: MAX_U_W
+/* 6017 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 6030
+/* 6021 */ MCD_OPC_CheckPredicate, 8, 21, 30, // Skip to: 13726
+/* 6025 */ MCD_OPC_Decode, 176, 8, 140, 1, // Opcode: MAX_U_D
+/* 6030 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 6043
+/* 6034 */ MCD_OPC_CheckPredicate, 8, 8, 30, // Skip to: 13726
+/* 6038 */ MCD_OPC_Decode, 212, 8, 137, 1, // Opcode: MIN_S_B
+/* 6043 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 6056
+/* 6047 */ MCD_OPC_CheckPredicate, 8, 251, 29, // Skip to: 13726
+/* 6051 */ MCD_OPC_Decode, 214, 8, 138, 1, // Opcode: MIN_S_H
+/* 6056 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 6069
+/* 6060 */ MCD_OPC_CheckPredicate, 8, 238, 29, // Skip to: 13726
+/* 6064 */ MCD_OPC_Decode, 215, 8, 139, 1, // Opcode: MIN_S_W
+/* 6069 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 6082
+/* 6073 */ MCD_OPC_CheckPredicate, 8, 225, 29, // Skip to: 13726
+/* 6077 */ MCD_OPC_Decode, 213, 8, 140, 1, // Opcode: MIN_S_D
+/* 6082 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 6095
+/* 6086 */ MCD_OPC_CheckPredicate, 8, 212, 29, // Skip to: 13726
+/* 6090 */ MCD_OPC_Decode, 216, 8, 137, 1, // Opcode: MIN_U_B
+/* 6095 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 6108
+/* 6099 */ MCD_OPC_CheckPredicate, 8, 199, 29, // Skip to: 13726
+/* 6103 */ MCD_OPC_Decode, 218, 8, 138, 1, // Opcode: MIN_U_H
+/* 6108 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 6121
+/* 6112 */ MCD_OPC_CheckPredicate, 8, 186, 29, // Skip to: 13726
+/* 6116 */ MCD_OPC_Decode, 219, 8, 139, 1, // Opcode: MIN_U_W
+/* 6121 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 6134
+/* 6125 */ MCD_OPC_CheckPredicate, 8, 173, 29, // Skip to: 13726
+/* 6129 */ MCD_OPC_Decode, 217, 8, 140, 1, // Opcode: MIN_U_D
+/* 6134 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 6147
+/* 6138 */ MCD_OPC_CheckPredicate, 8, 160, 29, // Skip to: 13726
+/* 6142 */ MCD_OPC_Decode, 165, 8, 137, 1, // Opcode: MAX_A_B
+/* 6147 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 6160
+/* 6151 */ MCD_OPC_CheckPredicate, 8, 147, 29, // Skip to: 13726
+/* 6155 */ MCD_OPC_Decode, 167, 8, 138, 1, // Opcode: MAX_A_H
+/* 6160 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 6173
+/* 6164 */ MCD_OPC_CheckPredicate, 8, 134, 29, // Skip to: 13726
+/* 6168 */ MCD_OPC_Decode, 168, 8, 139, 1, // Opcode: MAX_A_W
+/* 6173 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 6186
+/* 6177 */ MCD_OPC_CheckPredicate, 8, 121, 29, // Skip to: 13726
+/* 6181 */ MCD_OPC_Decode, 166, 8, 140, 1, // Opcode: MAX_A_D
+/* 6186 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 6199
+/* 6190 */ MCD_OPC_CheckPredicate, 8, 108, 29, // Skip to: 13726
+/* 6194 */ MCD_OPC_Decode, 206, 8, 137, 1, // Opcode: MIN_A_B
+/* 6199 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 6212
+/* 6203 */ MCD_OPC_CheckPredicate, 8, 95, 29, // Skip to: 13726
+/* 6207 */ MCD_OPC_Decode, 208, 8, 138, 1, // Opcode: MIN_A_H
+/* 6212 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 6225
+/* 6216 */ MCD_OPC_CheckPredicate, 8, 82, 29, // Skip to: 13726
+/* 6220 */ MCD_OPC_Decode, 209, 8, 139, 1, // Opcode: MIN_A_W
+/* 6225 */ MCD_OPC_FilterValue, 31, 73, 29, // Skip to: 13726
+/* 6229 */ MCD_OPC_CheckPredicate, 8, 69, 29, // Skip to: 13726
+/* 6233 */ MCD_OPC_Decode, 207, 8, 140, 1, // Opcode: MIN_A_D
+/* 6238 */ MCD_OPC_FilterValue, 15, 7, 1, // Skip to: 6505
+/* 6242 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 6245 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6258
+/* 6249 */ MCD_OPC_CheckPredicate, 8, 49, 29, // Skip to: 13726
+/* 6253 */ MCD_OPC_Decode, 234, 2, 137, 1, // Opcode: CEQ_B
+/* 6258 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6271
+/* 6262 */ MCD_OPC_CheckPredicate, 8, 36, 29, // Skip to: 13726
+/* 6266 */ MCD_OPC_Decode, 236, 2, 138, 1, // Opcode: CEQ_H
+/* 6271 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6284
+/* 6275 */ MCD_OPC_CheckPredicate, 8, 23, 29, // Skip to: 13726
+/* 6279 */ MCD_OPC_Decode, 237, 2, 139, 1, // Opcode: CEQ_W
+/* 6284 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6297
+/* 6288 */ MCD_OPC_CheckPredicate, 8, 10, 29, // Skip to: 13726
+/* 6292 */ MCD_OPC_Decode, 235, 2, 140, 1, // Opcode: CEQ_D
+/* 6297 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 6310
+/* 6301 */ MCD_OPC_CheckPredicate, 8, 253, 28, // Skip to: 13726
+/* 6305 */ MCD_OPC_Decode, 144, 3, 137, 1, // Opcode: CLT_S_B
+/* 6310 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 6323
+/* 6314 */ MCD_OPC_CheckPredicate, 8, 240, 28, // Skip to: 13726
+/* 6318 */ MCD_OPC_Decode, 146, 3, 138, 1, // Opcode: CLT_S_H
+/* 6323 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 6336
+/* 6327 */ MCD_OPC_CheckPredicate, 8, 227, 28, // Skip to: 13726
+/* 6331 */ MCD_OPC_Decode, 147, 3, 139, 1, // Opcode: CLT_S_W
+/* 6336 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 6349
+/* 6340 */ MCD_OPC_CheckPredicate, 8, 214, 28, // Skip to: 13726
+/* 6344 */ MCD_OPC_Decode, 145, 3, 140, 1, // Opcode: CLT_S_D
+/* 6349 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 6362
+/* 6353 */ MCD_OPC_CheckPredicate, 8, 201, 28, // Skip to: 13726
+/* 6357 */ MCD_OPC_Decode, 148, 3, 137, 1, // Opcode: CLT_U_B
+/* 6362 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 6375
+/* 6366 */ MCD_OPC_CheckPredicate, 8, 188, 28, // Skip to: 13726
+/* 6370 */ MCD_OPC_Decode, 150, 3, 138, 1, // Opcode: CLT_U_H
+/* 6375 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 6388
+/* 6379 */ MCD_OPC_CheckPredicate, 8, 175, 28, // Skip to: 13726
+/* 6383 */ MCD_OPC_Decode, 151, 3, 139, 1, // Opcode: CLT_U_W
+/* 6388 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 6401
+/* 6392 */ MCD_OPC_CheckPredicate, 8, 162, 28, // Skip to: 13726
+/* 6396 */ MCD_OPC_Decode, 149, 3, 140, 1, // Opcode: CLT_U_D
+/* 6401 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 6414
+/* 6405 */ MCD_OPC_CheckPredicate, 8, 149, 28, // Skip to: 13726
+/* 6409 */ MCD_OPC_Decode, 253, 2, 137, 1, // Opcode: CLE_S_B
+/* 6414 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 6427
+/* 6418 */ MCD_OPC_CheckPredicate, 8, 136, 28, // Skip to: 13726
+/* 6422 */ MCD_OPC_Decode, 255, 2, 138, 1, // Opcode: CLE_S_H
+/* 6427 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 6440
+/* 6431 */ MCD_OPC_CheckPredicate, 8, 123, 28, // Skip to: 13726
+/* 6435 */ MCD_OPC_Decode, 128, 3, 139, 1, // Opcode: CLE_S_W
+/* 6440 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 6453
+/* 6444 */ MCD_OPC_CheckPredicate, 8, 110, 28, // Skip to: 13726
+/* 6448 */ MCD_OPC_Decode, 254, 2, 140, 1, // Opcode: CLE_S_D
+/* 6453 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 6466
+/* 6457 */ MCD_OPC_CheckPredicate, 8, 97, 28, // Skip to: 13726
+/* 6461 */ MCD_OPC_Decode, 129, 3, 137, 1, // Opcode: CLE_U_B
+/* 6466 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 6479
+/* 6470 */ MCD_OPC_CheckPredicate, 8, 84, 28, // Skip to: 13726
+/* 6474 */ MCD_OPC_Decode, 131, 3, 138, 1, // Opcode: CLE_U_H
+/* 6479 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 6492
+/* 6483 */ MCD_OPC_CheckPredicate, 8, 71, 28, // Skip to: 13726
+/* 6487 */ MCD_OPC_Decode, 132, 3, 139, 1, // Opcode: CLE_U_W
+/* 6492 */ MCD_OPC_FilterValue, 23, 62, 28, // Skip to: 13726
+/* 6496 */ MCD_OPC_CheckPredicate, 8, 58, 28, // Skip to: 13726
+/* 6500 */ MCD_OPC_Decode, 130, 3, 140, 1, // Opcode: CLE_U_D
+/* 6505 */ MCD_OPC_FilterValue, 16, 147, 1, // Skip to: 6912
+/* 6509 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 6512 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6524
+/* 6516 */ MCD_OPC_CheckPredicate, 8, 38, 28, // Skip to: 13726
+/* 6520 */ MCD_OPC_Decode, 68, 137, 1, // Opcode: ADD_A_B
+/* 6524 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6536
+/* 6528 */ MCD_OPC_CheckPredicate, 8, 26, 28, // Skip to: 13726
+/* 6532 */ MCD_OPC_Decode, 70, 138, 1, // Opcode: ADD_A_H
+/* 6536 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6548
+/* 6540 */ MCD_OPC_CheckPredicate, 8, 14, 28, // Skip to: 13726
+/* 6544 */ MCD_OPC_Decode, 71, 139, 1, // Opcode: ADD_A_W
+/* 6548 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 6560
+/* 6552 */ MCD_OPC_CheckPredicate, 8, 2, 28, // Skip to: 13726
+/* 6556 */ MCD_OPC_Decode, 69, 140, 1, // Opcode: ADD_A_D
+/* 6560 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 6572
+/* 6564 */ MCD_OPC_CheckPredicate, 8, 246, 27, // Skip to: 13726
+/* 6568 */ MCD_OPC_Decode, 40, 137, 1, // Opcode: ADDS_A_B
+/* 6572 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 6584
+/* 6576 */ MCD_OPC_CheckPredicate, 8, 234, 27, // Skip to: 13726
+/* 6580 */ MCD_OPC_Decode, 42, 138, 1, // Opcode: ADDS_A_H
+/* 6584 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 6596
+/* 6588 */ MCD_OPC_CheckPredicate, 8, 222, 27, // Skip to: 13726
+/* 6592 */ MCD_OPC_Decode, 43, 139, 1, // Opcode: ADDS_A_W
+/* 6596 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 6608
+/* 6600 */ MCD_OPC_CheckPredicate, 8, 210, 27, // Skip to: 13726
+/* 6604 */ MCD_OPC_Decode, 41, 140, 1, // Opcode: ADDS_A_D
+/* 6608 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 6620
+/* 6612 */ MCD_OPC_CheckPredicate, 8, 198, 27, // Skip to: 13726
+/* 6616 */ MCD_OPC_Decode, 44, 137, 1, // Opcode: ADDS_S_B
+/* 6620 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 6632
+/* 6624 */ MCD_OPC_CheckPredicate, 8, 186, 27, // Skip to: 13726
+/* 6628 */ MCD_OPC_Decode, 46, 138, 1, // Opcode: ADDS_S_H
+/* 6632 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 6644
+/* 6636 */ MCD_OPC_CheckPredicate, 8, 174, 27, // Skip to: 13726
+/* 6640 */ MCD_OPC_Decode, 47, 139, 1, // Opcode: ADDS_S_W
+/* 6644 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 6656
+/* 6648 */ MCD_OPC_CheckPredicate, 8, 162, 27, // Skip to: 13726
+/* 6652 */ MCD_OPC_Decode, 45, 140, 1, // Opcode: ADDS_S_D
+/* 6656 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 6668
+/* 6660 */ MCD_OPC_CheckPredicate, 8, 150, 27, // Skip to: 13726
+/* 6664 */ MCD_OPC_Decode, 48, 137, 1, // Opcode: ADDS_U_B
+/* 6668 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 6680
+/* 6672 */ MCD_OPC_CheckPredicate, 8, 138, 27, // Skip to: 13726
+/* 6676 */ MCD_OPC_Decode, 50, 138, 1, // Opcode: ADDS_U_H
+/* 6680 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 6692
+/* 6684 */ MCD_OPC_CheckPredicate, 8, 126, 27, // Skip to: 13726
+/* 6688 */ MCD_OPC_Decode, 51, 139, 1, // Opcode: ADDS_U_W
+/* 6692 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 6704
+/* 6696 */ MCD_OPC_CheckPredicate, 8, 114, 27, // Skip to: 13726
+/* 6700 */ MCD_OPC_Decode, 49, 140, 1, // Opcode: ADDS_U_D
+/* 6704 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 6717
+/* 6708 */ MCD_OPC_CheckPredicate, 8, 102, 27, // Skip to: 13726
+/* 6712 */ MCD_OPC_Decode, 147, 1, 137, 1, // Opcode: AVE_S_B
+/* 6717 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 6730
+/* 6721 */ MCD_OPC_CheckPredicate, 8, 89, 27, // Skip to: 13726
+/* 6725 */ MCD_OPC_Decode, 149, 1, 138, 1, // Opcode: AVE_S_H
+/* 6730 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 6743
+/* 6734 */ MCD_OPC_CheckPredicate, 8, 76, 27, // Skip to: 13726
+/* 6738 */ MCD_OPC_Decode, 150, 1, 139, 1, // Opcode: AVE_S_W
+/* 6743 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 6756
+/* 6747 */ MCD_OPC_CheckPredicate, 8, 63, 27, // Skip to: 13726
+/* 6751 */ MCD_OPC_Decode, 148, 1, 140, 1, // Opcode: AVE_S_D
+/* 6756 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 6769
+/* 6760 */ MCD_OPC_CheckPredicate, 8, 50, 27, // Skip to: 13726
+/* 6764 */ MCD_OPC_Decode, 151, 1, 137, 1, // Opcode: AVE_U_B
+/* 6769 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 6782
+/* 6773 */ MCD_OPC_CheckPredicate, 8, 37, 27, // Skip to: 13726
+/* 6777 */ MCD_OPC_Decode, 153, 1, 138, 1, // Opcode: AVE_U_H
+/* 6782 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 6795
+/* 6786 */ MCD_OPC_CheckPredicate, 8, 24, 27, // Skip to: 13726
+/* 6790 */ MCD_OPC_Decode, 154, 1, 139, 1, // Opcode: AVE_U_W
+/* 6795 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 6808
+/* 6799 */ MCD_OPC_CheckPredicate, 8, 11, 27, // Skip to: 13726
+/* 6803 */ MCD_OPC_Decode, 152, 1, 140, 1, // Opcode: AVE_U_D
+/* 6808 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 6821
+/* 6812 */ MCD_OPC_CheckPredicate, 8, 254, 26, // Skip to: 13726
+/* 6816 */ MCD_OPC_Decode, 139, 1, 137, 1, // Opcode: AVER_S_B
+/* 6821 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 6834
+/* 6825 */ MCD_OPC_CheckPredicate, 8, 241, 26, // Skip to: 13726
+/* 6829 */ MCD_OPC_Decode, 141, 1, 138, 1, // Opcode: AVER_S_H
+/* 6834 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 6847
+/* 6838 */ MCD_OPC_CheckPredicate, 8, 228, 26, // Skip to: 13726
+/* 6842 */ MCD_OPC_Decode, 142, 1, 139, 1, // Opcode: AVER_S_W
+/* 6847 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 6860
+/* 6851 */ MCD_OPC_CheckPredicate, 8, 215, 26, // Skip to: 13726
+/* 6855 */ MCD_OPC_Decode, 140, 1, 140, 1, // Opcode: AVER_S_D
+/* 6860 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 6873
+/* 6864 */ MCD_OPC_CheckPredicate, 8, 202, 26, // Skip to: 13726
+/* 6868 */ MCD_OPC_Decode, 143, 1, 137, 1, // Opcode: AVER_U_B
+/* 6873 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 6886
+/* 6877 */ MCD_OPC_CheckPredicate, 8, 189, 26, // Skip to: 13726
+/* 6881 */ MCD_OPC_Decode, 145, 1, 138, 1, // Opcode: AVER_U_H
+/* 6886 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 6899
+/* 6890 */ MCD_OPC_CheckPredicate, 8, 176, 26, // Skip to: 13726
+/* 6894 */ MCD_OPC_Decode, 146, 1, 139, 1, // Opcode: AVER_U_W
+/* 6899 */ MCD_OPC_FilterValue, 31, 167, 26, // Skip to: 13726
+/* 6903 */ MCD_OPC_CheckPredicate, 8, 163, 26, // Skip to: 13726
+/* 6907 */ MCD_OPC_Decode, 144, 1, 140, 1, // Opcode: AVER_U_D
+/* 6912 */ MCD_OPC_FilterValue, 17, 51, 1, // Skip to: 7223
+/* 6916 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 6919 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6932
+/* 6923 */ MCD_OPC_CheckPredicate, 8, 143, 26, // Skip to: 13726
+/* 6927 */ MCD_OPC_Decode, 206, 12, 137, 1, // Opcode: SUBS_S_B
+/* 6932 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6945
+/* 6936 */ MCD_OPC_CheckPredicate, 8, 130, 26, // Skip to: 13726
+/* 6940 */ MCD_OPC_Decode, 208, 12, 138, 1, // Opcode: SUBS_S_H
+/* 6945 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6958
+/* 6949 */ MCD_OPC_CheckPredicate, 8, 117, 26, // Skip to: 13726
+/* 6953 */ MCD_OPC_Decode, 209, 12, 139, 1, // Opcode: SUBS_S_W
+/* 6958 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6971
+/* 6962 */ MCD_OPC_CheckPredicate, 8, 104, 26, // Skip to: 13726
+/* 6966 */ MCD_OPC_Decode, 207, 12, 140, 1, // Opcode: SUBS_S_D
+/* 6971 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 6984
+/* 6975 */ MCD_OPC_CheckPredicate, 8, 91, 26, // Skip to: 13726
+/* 6979 */ MCD_OPC_Decode, 210, 12, 137, 1, // Opcode: SUBS_U_B
+/* 6984 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 6997
+/* 6988 */ MCD_OPC_CheckPredicate, 8, 78, 26, // Skip to: 13726
+/* 6992 */ MCD_OPC_Decode, 212, 12, 138, 1, // Opcode: SUBS_U_H
+/* 6997 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7010
+/* 7001 */ MCD_OPC_CheckPredicate, 8, 65, 26, // Skip to: 13726
+/* 7005 */ MCD_OPC_Decode, 213, 12, 139, 1, // Opcode: SUBS_U_W
+/* 7010 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7023
+/* 7014 */ MCD_OPC_CheckPredicate, 8, 52, 26, // Skip to: 13726
+/* 7018 */ MCD_OPC_Decode, 211, 12, 140, 1, // Opcode: SUBS_U_D
+/* 7023 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7036
+/* 7027 */ MCD_OPC_CheckPredicate, 8, 39, 26, // Skip to: 13726
+/* 7031 */ MCD_OPC_Decode, 198, 12, 137, 1, // Opcode: SUBSUS_U_B
+/* 7036 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7049
+/* 7040 */ MCD_OPC_CheckPredicate, 8, 26, 26, // Skip to: 13726
+/* 7044 */ MCD_OPC_Decode, 200, 12, 138, 1, // Opcode: SUBSUS_U_H
+/* 7049 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7062
+/* 7053 */ MCD_OPC_CheckPredicate, 8, 13, 26, // Skip to: 13726
+/* 7057 */ MCD_OPC_Decode, 201, 12, 139, 1, // Opcode: SUBSUS_U_W
+/* 7062 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7075
+/* 7066 */ MCD_OPC_CheckPredicate, 8, 0, 26, // Skip to: 13726
+/* 7070 */ MCD_OPC_Decode, 199, 12, 140, 1, // Opcode: SUBSUS_U_D
+/* 7075 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 7088
+/* 7079 */ MCD_OPC_CheckPredicate, 8, 243, 25, // Skip to: 13726
+/* 7083 */ MCD_OPC_Decode, 202, 12, 137, 1, // Opcode: SUBSUU_S_B
+/* 7088 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 7101
+/* 7092 */ MCD_OPC_CheckPredicate, 8, 230, 25, // Skip to: 13726
+/* 7096 */ MCD_OPC_Decode, 204, 12, 138, 1, // Opcode: SUBSUU_S_H
+/* 7101 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 7114
+/* 7105 */ MCD_OPC_CheckPredicate, 8, 217, 25, // Skip to: 13726
+/* 7109 */ MCD_OPC_Decode, 205, 12, 139, 1, // Opcode: SUBSUU_S_W
+/* 7114 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 7127
+/* 7118 */ MCD_OPC_CheckPredicate, 8, 204, 25, // Skip to: 13726
+/* 7122 */ MCD_OPC_Decode, 203, 12, 140, 1, // Opcode: SUBSUU_S_D
+/* 7127 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 7139
+/* 7131 */ MCD_OPC_CheckPredicate, 8, 191, 25, // Skip to: 13726
+/* 7135 */ MCD_OPC_Decode, 97, 137, 1, // Opcode: ASUB_S_B
+/* 7139 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 7151
+/* 7143 */ MCD_OPC_CheckPredicate, 8, 179, 25, // Skip to: 13726
+/* 7147 */ MCD_OPC_Decode, 99, 138, 1, // Opcode: ASUB_S_H
+/* 7151 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 7163
+/* 7155 */ MCD_OPC_CheckPredicate, 8, 167, 25, // Skip to: 13726
+/* 7159 */ MCD_OPC_Decode, 100, 139, 1, // Opcode: ASUB_S_W
+/* 7163 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 7175
+/* 7167 */ MCD_OPC_CheckPredicate, 8, 155, 25, // Skip to: 13726
+/* 7171 */ MCD_OPC_Decode, 98, 140, 1, // Opcode: ASUB_S_D
+/* 7175 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 7187
+/* 7179 */ MCD_OPC_CheckPredicate, 8, 143, 25, // Skip to: 13726
+/* 7183 */ MCD_OPC_Decode, 101, 137, 1, // Opcode: ASUB_U_B
+/* 7187 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 7199
+/* 7191 */ MCD_OPC_CheckPredicate, 8, 131, 25, // Skip to: 13726
+/* 7195 */ MCD_OPC_Decode, 103, 138, 1, // Opcode: ASUB_U_H
+/* 7199 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 7211
+/* 7203 */ MCD_OPC_CheckPredicate, 8, 119, 25, // Skip to: 13726
+/* 7207 */ MCD_OPC_Decode, 104, 139, 1, // Opcode: ASUB_U_W
+/* 7211 */ MCD_OPC_FilterValue, 23, 111, 25, // Skip to: 13726
+/* 7215 */ MCD_OPC_CheckPredicate, 8, 107, 25, // Skip to: 13726
+/* 7219 */ MCD_OPC_Decode, 102, 140, 1, // Opcode: ASUB_U_D
+/* 7223 */ MCD_OPC_FilterValue, 18, 111, 1, // Skip to: 7594
+/* 7227 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 7230 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7243
+/* 7234 */ MCD_OPC_CheckPredicate, 8, 88, 25, // Skip to: 13726
+/* 7238 */ MCD_OPC_Decode, 213, 9, 137, 1, // Opcode: MULV_B
+/* 7243 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7256
+/* 7247 */ MCD_OPC_CheckPredicate, 8, 75, 25, // Skip to: 13726
+/* 7251 */ MCD_OPC_Decode, 215, 9, 138, 1, // Opcode: MULV_H
+/* 7256 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7269
+/* 7260 */ MCD_OPC_CheckPredicate, 8, 62, 25, // Skip to: 13726
+/* 7264 */ MCD_OPC_Decode, 216, 9, 139, 1, // Opcode: MULV_W
+/* 7269 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7282
+/* 7273 */ MCD_OPC_CheckPredicate, 8, 49, 25, // Skip to: 13726
+/* 7277 */ MCD_OPC_Decode, 214, 9, 140, 1, // Opcode: MULV_D
+/* 7282 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 7295
+/* 7286 */ MCD_OPC_CheckPredicate, 8, 36, 25, // Skip to: 13726
+/* 7290 */ MCD_OPC_Decode, 138, 8, 141, 1, // Opcode: MADDV_B
+/* 7295 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7308
+/* 7299 */ MCD_OPC_CheckPredicate, 8, 23, 25, // Skip to: 13726
+/* 7303 */ MCD_OPC_Decode, 140, 8, 142, 1, // Opcode: MADDV_H
+/* 7308 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7321
+/* 7312 */ MCD_OPC_CheckPredicate, 8, 10, 25, // Skip to: 13726
+/* 7316 */ MCD_OPC_Decode, 141, 8, 143, 1, // Opcode: MADDV_W
+/* 7321 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7334
+/* 7325 */ MCD_OPC_CheckPredicate, 8, 253, 24, // Skip to: 13726
+/* 7329 */ MCD_OPC_Decode, 139, 8, 144, 1, // Opcode: MADDV_D
+/* 7334 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7347
+/* 7338 */ MCD_OPC_CheckPredicate, 8, 240, 24, // Skip to: 13726
+/* 7342 */ MCD_OPC_Decode, 156, 9, 141, 1, // Opcode: MSUBV_B
+/* 7347 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7360
+/* 7351 */ MCD_OPC_CheckPredicate, 8, 227, 24, // Skip to: 13726
+/* 7355 */ MCD_OPC_Decode, 158, 9, 142, 1, // Opcode: MSUBV_H
+/* 7360 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7373
+/* 7364 */ MCD_OPC_CheckPredicate, 8, 214, 24, // Skip to: 13726
+/* 7368 */ MCD_OPC_Decode, 159, 9, 143, 1, // Opcode: MSUBV_W
+/* 7373 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7386
+/* 7377 */ MCD_OPC_CheckPredicate, 8, 201, 24, // Skip to: 13726
+/* 7381 */ MCD_OPC_Decode, 157, 9, 144, 1, // Opcode: MSUBV_D
+/* 7386 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 7399
+/* 7390 */ MCD_OPC_CheckPredicate, 8, 188, 24, // Skip to: 13726
+/* 7394 */ MCD_OPC_Decode, 185, 4, 137, 1, // Opcode: DIV_S_B
+/* 7399 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 7412
+/* 7403 */ MCD_OPC_CheckPredicate, 8, 175, 24, // Skip to: 13726
+/* 7407 */ MCD_OPC_Decode, 187, 4, 138, 1, // Opcode: DIV_S_H
+/* 7412 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 7425
+/* 7416 */ MCD_OPC_CheckPredicate, 8, 162, 24, // Skip to: 13726
+/* 7420 */ MCD_OPC_Decode, 188, 4, 139, 1, // Opcode: DIV_S_W
+/* 7425 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 7438
+/* 7429 */ MCD_OPC_CheckPredicate, 8, 149, 24, // Skip to: 13726
+/* 7433 */ MCD_OPC_Decode, 186, 4, 140, 1, // Opcode: DIV_S_D
+/* 7438 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 7451
+/* 7442 */ MCD_OPC_CheckPredicate, 8, 136, 24, // Skip to: 13726
+/* 7446 */ MCD_OPC_Decode, 189, 4, 137, 1, // Opcode: DIV_U_B
+/* 7451 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 7464
+/* 7455 */ MCD_OPC_CheckPredicate, 8, 123, 24, // Skip to: 13726
+/* 7459 */ MCD_OPC_Decode, 191, 4, 138, 1, // Opcode: DIV_U_H
+/* 7464 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 7477
+/* 7468 */ MCD_OPC_CheckPredicate, 8, 110, 24, // Skip to: 13726
+/* 7472 */ MCD_OPC_Decode, 192, 4, 139, 1, // Opcode: DIV_U_W
+/* 7477 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 7490
+/* 7481 */ MCD_OPC_CheckPredicate, 8, 97, 24, // Skip to: 13726
+/* 7485 */ MCD_OPC_Decode, 190, 4, 140, 1, // Opcode: DIV_U_D
+/* 7490 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 7503
+/* 7494 */ MCD_OPC_CheckPredicate, 8, 84, 24, // Skip to: 13726
+/* 7498 */ MCD_OPC_Decode, 225, 8, 137, 1, // Opcode: MOD_S_B
+/* 7503 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 7516
+/* 7507 */ MCD_OPC_CheckPredicate, 8, 71, 24, // Skip to: 13726
+/* 7511 */ MCD_OPC_Decode, 227, 8, 138, 1, // Opcode: MOD_S_H
+/* 7516 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 7529
+/* 7520 */ MCD_OPC_CheckPredicate, 8, 58, 24, // Skip to: 13726
+/* 7524 */ MCD_OPC_Decode, 228, 8, 139, 1, // Opcode: MOD_S_W
+/* 7529 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 7542
+/* 7533 */ MCD_OPC_CheckPredicate, 8, 45, 24, // Skip to: 13726
+/* 7537 */ MCD_OPC_Decode, 226, 8, 140, 1, // Opcode: MOD_S_D
+/* 7542 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 7555
+/* 7546 */ MCD_OPC_CheckPredicate, 8, 32, 24, // Skip to: 13726
+/* 7550 */ MCD_OPC_Decode, 229, 8, 137, 1, // Opcode: MOD_U_B
+/* 7555 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 7568
+/* 7559 */ MCD_OPC_CheckPredicate, 8, 19, 24, // Skip to: 13726
+/* 7563 */ MCD_OPC_Decode, 231, 8, 138, 1, // Opcode: MOD_U_H
+/* 7568 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 7581
+/* 7572 */ MCD_OPC_CheckPredicate, 8, 6, 24, // Skip to: 13726
+/* 7576 */ MCD_OPC_Decode, 232, 8, 139, 1, // Opcode: MOD_U_W
+/* 7581 */ MCD_OPC_FilterValue, 31, 253, 23, // Skip to: 13726
+/* 7585 */ MCD_OPC_CheckPredicate, 8, 249, 23, // Skip to: 13726
+/* 7589 */ MCD_OPC_Decode, 230, 8, 140, 1, // Opcode: MOD_U_D
+/* 7594 */ MCD_OPC_FilterValue, 19, 237, 0, // Skip to: 7835
+/* 7598 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 7601 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7614
+/* 7605 */ MCD_OPC_CheckPredicate, 8, 229, 23, // Skip to: 13726
+/* 7609 */ MCD_OPC_Decode, 212, 4, 145, 1, // Opcode: DOTP_S_H
+/* 7614 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7627
+/* 7618 */ MCD_OPC_CheckPredicate, 8, 216, 23, // Skip to: 13726
+/* 7622 */ MCD_OPC_Decode, 213, 4, 146, 1, // Opcode: DOTP_S_W
+/* 7627 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7640
+/* 7631 */ MCD_OPC_CheckPredicate, 8, 203, 23, // Skip to: 13726
+/* 7635 */ MCD_OPC_Decode, 211, 4, 147, 1, // Opcode: DOTP_S_D
+/* 7640 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7653
+/* 7644 */ MCD_OPC_CheckPredicate, 8, 190, 23, // Skip to: 13726
+/* 7648 */ MCD_OPC_Decode, 215, 4, 145, 1, // Opcode: DOTP_U_H
+/* 7653 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7666
+/* 7657 */ MCD_OPC_CheckPredicate, 8, 177, 23, // Skip to: 13726
+/* 7661 */ MCD_OPC_Decode, 216, 4, 146, 1, // Opcode: DOTP_U_W
+/* 7666 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7679
+/* 7670 */ MCD_OPC_CheckPredicate, 8, 164, 23, // Skip to: 13726
+/* 7674 */ MCD_OPC_Decode, 214, 4, 147, 1, // Opcode: DOTP_U_D
+/* 7679 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7692
+/* 7683 */ MCD_OPC_CheckPredicate, 8, 151, 23, // Skip to: 13726
+/* 7687 */ MCD_OPC_Decode, 218, 4, 148, 1, // Opcode: DPADD_S_H
+/* 7692 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7705
+/* 7696 */ MCD_OPC_CheckPredicate, 8, 138, 23, // Skip to: 13726
+/* 7700 */ MCD_OPC_Decode, 219, 4, 149, 1, // Opcode: DPADD_S_W
+/* 7705 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7718
+/* 7709 */ MCD_OPC_CheckPredicate, 8, 125, 23, // Skip to: 13726
+/* 7713 */ MCD_OPC_Decode, 217, 4, 150, 1, // Opcode: DPADD_S_D
+/* 7718 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 7731
+/* 7722 */ MCD_OPC_CheckPredicate, 8, 112, 23, // Skip to: 13726
+/* 7726 */ MCD_OPC_Decode, 221, 4, 148, 1, // Opcode: DPADD_U_H
+/* 7731 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 7744
+/* 7735 */ MCD_OPC_CheckPredicate, 8, 99, 23, // Skip to: 13726
+/* 7739 */ MCD_OPC_Decode, 222, 4, 149, 1, // Opcode: DPADD_U_W
+/* 7744 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 7757
+/* 7748 */ MCD_OPC_CheckPredicate, 8, 86, 23, // Skip to: 13726
+/* 7752 */ MCD_OPC_Decode, 220, 4, 150, 1, // Opcode: DPADD_U_D
+/* 7757 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 7770
+/* 7761 */ MCD_OPC_CheckPredicate, 8, 73, 23, // Skip to: 13726
+/* 7765 */ MCD_OPC_Decode, 237, 4, 148, 1, // Opcode: DPSUB_S_H
+/* 7770 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 7783
+/* 7774 */ MCD_OPC_CheckPredicate, 8, 60, 23, // Skip to: 13726
+/* 7778 */ MCD_OPC_Decode, 238, 4, 149, 1, // Opcode: DPSUB_S_W
+/* 7783 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 7796
+/* 7787 */ MCD_OPC_CheckPredicate, 8, 47, 23, // Skip to: 13726
+/* 7791 */ MCD_OPC_Decode, 236, 4, 150, 1, // Opcode: DPSUB_S_D
+/* 7796 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 7809
+/* 7800 */ MCD_OPC_CheckPredicate, 8, 34, 23, // Skip to: 13726
+/* 7804 */ MCD_OPC_Decode, 240, 4, 148, 1, // Opcode: DPSUB_U_H
+/* 7809 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 7822
+/* 7813 */ MCD_OPC_CheckPredicate, 8, 21, 23, // Skip to: 13726
+/* 7817 */ MCD_OPC_Decode, 241, 4, 149, 1, // Opcode: DPSUB_U_W
+/* 7822 */ MCD_OPC_FilterValue, 23, 12, 23, // Skip to: 13726
+/* 7826 */ MCD_OPC_CheckPredicate, 8, 8, 23, // Skip to: 13726
+/* 7830 */ MCD_OPC_Decode, 239, 4, 150, 1, // Opcode: DPSUB_U_D
+/* 7835 */ MCD_OPC_FilterValue, 20, 163, 1, // Skip to: 8258
+/* 7839 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 7842 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7855
+/* 7846 */ MCD_OPC_CheckPredicate, 8, 244, 22, // Skip to: 13726
+/* 7850 */ MCD_OPC_Decode, 221, 11, 151, 1, // Opcode: SLD_B
+/* 7855 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7868
+/* 7859 */ MCD_OPC_CheckPredicate, 8, 231, 22, // Skip to: 13726
+/* 7863 */ MCD_OPC_Decode, 223, 11, 152, 1, // Opcode: SLD_H
+/* 7868 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7881
+/* 7872 */ MCD_OPC_CheckPredicate, 8, 218, 22, // Skip to: 13726
+/* 7876 */ MCD_OPC_Decode, 224, 11, 153, 1, // Opcode: SLD_W
+/* 7881 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7894
+/* 7885 */ MCD_OPC_CheckPredicate, 8, 205, 22, // Skip to: 13726
+/* 7889 */ MCD_OPC_Decode, 222, 11, 154, 1, // Opcode: SLD_D
+/* 7894 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 7907
+/* 7898 */ MCD_OPC_CheckPredicate, 8, 192, 22, // Skip to: 13726
+/* 7902 */ MCD_OPC_Decode, 135, 12, 155, 1, // Opcode: SPLAT_B
+/* 7907 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7920
+/* 7911 */ MCD_OPC_CheckPredicate, 8, 179, 22, // Skip to: 13726
+/* 7915 */ MCD_OPC_Decode, 137, 12, 156, 1, // Opcode: SPLAT_H
+/* 7920 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7933
+/* 7924 */ MCD_OPC_CheckPredicate, 8, 166, 22, // Skip to: 13726
+/* 7928 */ MCD_OPC_Decode, 138, 12, 157, 1, // Opcode: SPLAT_W
+/* 7933 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7946
+/* 7937 */ MCD_OPC_CheckPredicate, 8, 153, 22, // Skip to: 13726
+/* 7941 */ MCD_OPC_Decode, 136, 12, 158, 1, // Opcode: SPLAT_D
+/* 7946 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7959
+/* 7950 */ MCD_OPC_CheckPredicate, 8, 140, 22, // Skip to: 13726
+/* 7954 */ MCD_OPC_Decode, 149, 10, 137, 1, // Opcode: PCKEV_B
+/* 7959 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7972
+/* 7963 */ MCD_OPC_CheckPredicate, 8, 127, 22, // Skip to: 13726
+/* 7967 */ MCD_OPC_Decode, 151, 10, 138, 1, // Opcode: PCKEV_H
+/* 7972 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7985
+/* 7976 */ MCD_OPC_CheckPredicate, 8, 114, 22, // Skip to: 13726
+/* 7980 */ MCD_OPC_Decode, 152, 10, 139, 1, // Opcode: PCKEV_W
+/* 7985 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7998
+/* 7989 */ MCD_OPC_CheckPredicate, 8, 101, 22, // Skip to: 13726
+/* 7993 */ MCD_OPC_Decode, 150, 10, 140, 1, // Opcode: PCKEV_D
+/* 7998 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 8011
+/* 8002 */ MCD_OPC_CheckPredicate, 8, 88, 22, // Skip to: 13726
+/* 8006 */ MCD_OPC_Decode, 153, 10, 137, 1, // Opcode: PCKOD_B
+/* 8011 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 8024
+/* 8015 */ MCD_OPC_CheckPredicate, 8, 75, 22, // Skip to: 13726
+/* 8019 */ MCD_OPC_Decode, 155, 10, 138, 1, // Opcode: PCKOD_H
+/* 8024 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 8037
+/* 8028 */ MCD_OPC_CheckPredicate, 8, 62, 22, // Skip to: 13726
+/* 8032 */ MCD_OPC_Decode, 156, 10, 139, 1, // Opcode: PCKOD_W
+/* 8037 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 8050
+/* 8041 */ MCD_OPC_CheckPredicate, 8, 49, 22, // Skip to: 13726
+/* 8045 */ MCD_OPC_Decode, 154, 10, 140, 1, // Opcode: PCKOD_D
+/* 8050 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 8063
+/* 8054 */ MCD_OPC_CheckPredicate, 8, 36, 22, // Skip to: 13726
+/* 8058 */ MCD_OPC_Decode, 216, 6, 137, 1, // Opcode: ILVL_B
+/* 8063 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 8076
+/* 8067 */ MCD_OPC_CheckPredicate, 8, 23, 22, // Skip to: 13726
+/* 8071 */ MCD_OPC_Decode, 218, 6, 138, 1, // Opcode: ILVL_H
+/* 8076 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 8089
+/* 8080 */ MCD_OPC_CheckPredicate, 8, 10, 22, // Skip to: 13726
+/* 8084 */ MCD_OPC_Decode, 219, 6, 139, 1, // Opcode: ILVL_W
+/* 8089 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 8102
+/* 8093 */ MCD_OPC_CheckPredicate, 8, 253, 21, // Skip to: 13726
+/* 8097 */ MCD_OPC_Decode, 217, 6, 140, 1, // Opcode: ILVL_D
+/* 8102 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 8115
+/* 8106 */ MCD_OPC_CheckPredicate, 8, 240, 21, // Skip to: 13726
+/* 8110 */ MCD_OPC_Decode, 224, 6, 137, 1, // Opcode: ILVR_B
+/* 8115 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 8128
+/* 8119 */ MCD_OPC_CheckPredicate, 8, 227, 21, // Skip to: 13726
+/* 8123 */ MCD_OPC_Decode, 226, 6, 138, 1, // Opcode: ILVR_H
+/* 8128 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 8141
+/* 8132 */ MCD_OPC_CheckPredicate, 8, 214, 21, // Skip to: 13726
+/* 8136 */ MCD_OPC_Decode, 227, 6, 139, 1, // Opcode: ILVR_W
+/* 8141 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 8154
+/* 8145 */ MCD_OPC_CheckPredicate, 8, 201, 21, // Skip to: 13726
+/* 8149 */ MCD_OPC_Decode, 225, 6, 140, 1, // Opcode: ILVR_D
+/* 8154 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 8167
+/* 8158 */ MCD_OPC_CheckPredicate, 8, 188, 21, // Skip to: 13726
+/* 8162 */ MCD_OPC_Decode, 212, 6, 137, 1, // Opcode: ILVEV_B
+/* 8167 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 8180
+/* 8171 */ MCD_OPC_CheckPredicate, 8, 175, 21, // Skip to: 13726
+/* 8175 */ MCD_OPC_Decode, 214, 6, 138, 1, // Opcode: ILVEV_H
+/* 8180 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 8193
+/* 8184 */ MCD_OPC_CheckPredicate, 8, 162, 21, // Skip to: 13726
+/* 8188 */ MCD_OPC_Decode, 215, 6, 139, 1, // Opcode: ILVEV_W
+/* 8193 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 8206
+/* 8197 */ MCD_OPC_CheckPredicate, 8, 149, 21, // Skip to: 13726
+/* 8201 */ MCD_OPC_Decode, 213, 6, 140, 1, // Opcode: ILVEV_D
+/* 8206 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 8219
+/* 8210 */ MCD_OPC_CheckPredicate, 8, 136, 21, // Skip to: 13726
+/* 8214 */ MCD_OPC_Decode, 220, 6, 137, 1, // Opcode: ILVOD_B
+/* 8219 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 8232
+/* 8223 */ MCD_OPC_CheckPredicate, 8, 123, 21, // Skip to: 13726
+/* 8227 */ MCD_OPC_Decode, 222, 6, 138, 1, // Opcode: ILVOD_H
+/* 8232 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 8245
+/* 8236 */ MCD_OPC_CheckPredicate, 8, 110, 21, // Skip to: 13726
+/* 8240 */ MCD_OPC_Decode, 223, 6, 139, 1, // Opcode: ILVOD_W
+/* 8245 */ MCD_OPC_FilterValue, 31, 101, 21, // Skip to: 13726
+/* 8249 */ MCD_OPC_CheckPredicate, 8, 97, 21, // Skip to: 13726
+/* 8253 */ MCD_OPC_Decode, 221, 6, 140, 1, // Opcode: ILVOD_D
+/* 8258 */ MCD_OPC_FilterValue, 21, 59, 1, // Skip to: 8577
+/* 8262 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 8265 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8278
+/* 8269 */ MCD_OPC_CheckPredicate, 8, 77, 21, // Skip to: 13726
+/* 8273 */ MCD_OPC_Decode, 227, 13, 141, 1, // Opcode: VSHF_B
+/* 8278 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8291
+/* 8282 */ MCD_OPC_CheckPredicate, 8, 64, 21, // Skip to: 13726
+/* 8286 */ MCD_OPC_Decode, 229, 13, 142, 1, // Opcode: VSHF_H
+/* 8291 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8304
+/* 8295 */ MCD_OPC_CheckPredicate, 8, 51, 21, // Skip to: 13726
+/* 8299 */ MCD_OPC_Decode, 230, 13, 143, 1, // Opcode: VSHF_W
+/* 8304 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 8317
+/* 8308 */ MCD_OPC_CheckPredicate, 8, 38, 21, // Skip to: 13726
+/* 8312 */ MCD_OPC_Decode, 228, 13, 144, 1, // Opcode: VSHF_D
+/* 8317 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 8330
+/* 8321 */ MCD_OPC_CheckPredicate, 8, 25, 21, // Skip to: 13726
+/* 8325 */ MCD_OPC_Decode, 148, 12, 137, 1, // Opcode: SRAR_B
+/* 8330 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 8343
+/* 8334 */ MCD_OPC_CheckPredicate, 8, 12, 21, // Skip to: 13726
+/* 8338 */ MCD_OPC_Decode, 150, 12, 138, 1, // Opcode: SRAR_H
+/* 8343 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 8356
+/* 8347 */ MCD_OPC_CheckPredicate, 8, 255, 20, // Skip to: 13726
+/* 8351 */ MCD_OPC_Decode, 151, 12, 139, 1, // Opcode: SRAR_W
+/* 8356 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 8369
+/* 8360 */ MCD_OPC_CheckPredicate, 8, 242, 20, // Skip to: 13726
+/* 8364 */ MCD_OPC_Decode, 149, 12, 140, 1, // Opcode: SRAR_D
+/* 8369 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 8382
+/* 8373 */ MCD_OPC_CheckPredicate, 8, 229, 20, // Skip to: 13726
+/* 8377 */ MCD_OPC_Decode, 169, 12, 137, 1, // Opcode: SRLR_B
+/* 8382 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 8395
+/* 8386 */ MCD_OPC_CheckPredicate, 8, 216, 20, // Skip to: 13726
+/* 8390 */ MCD_OPC_Decode, 171, 12, 138, 1, // Opcode: SRLR_H
+/* 8395 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 8408
+/* 8399 */ MCD_OPC_CheckPredicate, 8, 203, 20, // Skip to: 13726
+/* 8403 */ MCD_OPC_Decode, 172, 12, 139, 1, // Opcode: SRLR_W
+/* 8408 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 8421
+/* 8412 */ MCD_OPC_CheckPredicate, 8, 190, 20, // Skip to: 13726
+/* 8416 */ MCD_OPC_Decode, 170, 12, 140, 1, // Opcode: SRLR_D
+/* 8421 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 8434
+/* 8425 */ MCD_OPC_CheckPredicate, 8, 177, 20, // Skip to: 13726
+/* 8429 */ MCD_OPC_Decode, 201, 6, 145, 1, // Opcode: HADD_S_H
+/* 8434 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 8447
+/* 8438 */ MCD_OPC_CheckPredicate, 8, 164, 20, // Skip to: 13726
+/* 8442 */ MCD_OPC_Decode, 202, 6, 146, 1, // Opcode: HADD_S_W
+/* 8447 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 8460
+/* 8451 */ MCD_OPC_CheckPredicate, 8, 151, 20, // Skip to: 13726
+/* 8455 */ MCD_OPC_Decode, 200, 6, 147, 1, // Opcode: HADD_S_D
+/* 8460 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 8473
+/* 8464 */ MCD_OPC_CheckPredicate, 8, 138, 20, // Skip to: 13726
+/* 8468 */ MCD_OPC_Decode, 204, 6, 145, 1, // Opcode: HADD_U_H
+/* 8473 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 8486
+/* 8477 */ MCD_OPC_CheckPredicate, 8, 125, 20, // Skip to: 13726
+/* 8481 */ MCD_OPC_Decode, 205, 6, 146, 1, // Opcode: HADD_U_W
+/* 8486 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 8499
+/* 8490 */ MCD_OPC_CheckPredicate, 8, 112, 20, // Skip to: 13726
+/* 8494 */ MCD_OPC_Decode, 203, 6, 147, 1, // Opcode: HADD_U_D
+/* 8499 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 8512
+/* 8503 */ MCD_OPC_CheckPredicate, 8, 99, 20, // Skip to: 13726
+/* 8507 */ MCD_OPC_Decode, 207, 6, 145, 1, // Opcode: HSUB_S_H
+/* 8512 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 8525
+/* 8516 */ MCD_OPC_CheckPredicate, 8, 86, 20, // Skip to: 13726
+/* 8520 */ MCD_OPC_Decode, 208, 6, 146, 1, // Opcode: HSUB_S_W
+/* 8525 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 8538
+/* 8529 */ MCD_OPC_CheckPredicate, 8, 73, 20, // Skip to: 13726
+/* 8533 */ MCD_OPC_Decode, 206, 6, 147, 1, // Opcode: HSUB_S_D
+/* 8538 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 8551
+/* 8542 */ MCD_OPC_CheckPredicate, 8, 60, 20, // Skip to: 13726
+/* 8546 */ MCD_OPC_Decode, 210, 6, 145, 1, // Opcode: HSUB_U_H
+/* 8551 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 8564
+/* 8555 */ MCD_OPC_CheckPredicate, 8, 47, 20, // Skip to: 13726
+/* 8559 */ MCD_OPC_Decode, 211, 6, 146, 1, // Opcode: HSUB_U_W
+/* 8564 */ MCD_OPC_FilterValue, 31, 38, 20, // Skip to: 13726
+/* 8568 */ MCD_OPC_CheckPredicate, 8, 34, 20, // Skip to: 13726
+/* 8572 */ MCD_OPC_Decode, 209, 6, 147, 1, // Opcode: HSUB_U_D
+/* 8577 */ MCD_OPC_FilterValue, 25, 230, 1, // Skip to: 9067
+/* 8581 */ MCD_OPC_ExtractField, 20, 6, // Inst{25-20} ...
+/* 8584 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8597
+/* 8588 */ MCD_OPC_CheckPredicate, 8, 14, 20, // Skip to: 13726
+/* 8592 */ MCD_OPC_Decode, 217, 11, 159, 1, // Opcode: SLDI_B
+/* 8597 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8616
+/* 8601 */ MCD_OPC_CheckPredicate, 8, 1, 20, // Skip to: 13726
+/* 8605 */ MCD_OPC_CheckField, 19, 1, 0, 251, 19, // Skip to: 13726
+/* 8611 */ MCD_OPC_Decode, 219, 11, 160, 1, // Opcode: SLDI_H
+/* 8616 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 8674
+/* 8620 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ...
+/* 8623 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8636
+/* 8627 */ MCD_OPC_CheckPredicate, 8, 231, 19, // Skip to: 13726
+/* 8631 */ MCD_OPC_Decode, 220, 11, 161, 1, // Opcode: SLDI_W
+/* 8636 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8655
+/* 8640 */ MCD_OPC_CheckPredicate, 8, 218, 19, // Skip to: 13726
+/* 8644 */ MCD_OPC_CheckField, 17, 1, 0, 212, 19, // Skip to: 13726
+/* 8650 */ MCD_OPC_Decode, 218, 11, 162, 1, // Opcode: SLDI_D
+/* 8655 */ MCD_OPC_FilterValue, 3, 203, 19, // Skip to: 13726
+/* 8659 */ MCD_OPC_CheckPredicate, 8, 199, 19, // Skip to: 13726
+/* 8663 */ MCD_OPC_CheckField, 16, 2, 2, 193, 19, // Skip to: 13726
+/* 8669 */ MCD_OPC_Decode, 212, 3, 163, 1, // Opcode: CTCMSA
+/* 8674 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 8687
+/* 8678 */ MCD_OPC_CheckPredicate, 8, 180, 19, // Skip to: 13726
+/* 8682 */ MCD_OPC_Decode, 131, 12, 164, 1, // Opcode: SPLATI_B
+/* 8687 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 8706
+/* 8691 */ MCD_OPC_CheckPredicate, 8, 167, 19, // Skip to: 13726
+/* 8695 */ MCD_OPC_CheckField, 19, 1, 0, 161, 19, // Skip to: 13726
+/* 8701 */ MCD_OPC_Decode, 133, 12, 165, 1, // Opcode: SPLATI_H
+/* 8706 */ MCD_OPC_FilterValue, 7, 54, 0, // Skip to: 8764
+/* 8710 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ...
+/* 8713 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8726
+/* 8717 */ MCD_OPC_CheckPredicate, 8, 141, 19, // Skip to: 13726
+/* 8721 */ MCD_OPC_Decode, 134, 12, 166, 1, // Opcode: SPLATI_W
+/* 8726 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8745
+/* 8730 */ MCD_OPC_CheckPredicate, 8, 128, 19, // Skip to: 13726
+/* 8734 */ MCD_OPC_CheckField, 17, 1, 0, 122, 19, // Skip to: 13726
+/* 8740 */ MCD_OPC_Decode, 132, 12, 167, 1, // Opcode: SPLATI_D
+/* 8745 */ MCD_OPC_FilterValue, 3, 113, 19, // Skip to: 13726
+/* 8749 */ MCD_OPC_CheckPredicate, 8, 109, 19, // Skip to: 13726
+/* 8753 */ MCD_OPC_CheckField, 16, 2, 2, 103, 19, // Skip to: 13726
+/* 8759 */ MCD_OPC_Decode, 240, 2, 168, 1, // Opcode: CFCMSA
+/* 8764 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 8777
+/* 8768 */ MCD_OPC_CheckPredicate, 8, 90, 19, // Skip to: 13726
+/* 8772 */ MCD_OPC_Decode, 202, 3, 169, 1, // Opcode: COPY_S_B
+/* 8777 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 8796
+/* 8781 */ MCD_OPC_CheckPredicate, 8, 77, 19, // Skip to: 13726
+/* 8785 */ MCD_OPC_CheckField, 19, 1, 0, 71, 19, // Skip to: 13726
+/* 8791 */ MCD_OPC_Decode, 204, 3, 170, 1, // Opcode: COPY_S_H
+/* 8796 */ MCD_OPC_FilterValue, 11, 54, 0, // Skip to: 8854
+/* 8800 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ...
+/* 8803 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8816
+/* 8807 */ MCD_OPC_CheckPredicate, 8, 51, 19, // Skip to: 13726
+/* 8811 */ MCD_OPC_Decode, 205, 3, 171, 1, // Opcode: COPY_S_W
+/* 8816 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8835
+/* 8820 */ MCD_OPC_CheckPredicate, 14, 38, 19, // Skip to: 13726
+/* 8824 */ MCD_OPC_CheckField, 17, 1, 0, 32, 19, // Skip to: 13726
+/* 8830 */ MCD_OPC_Decode, 203, 3, 172, 1, // Opcode: COPY_S_D
+/* 8835 */ MCD_OPC_FilterValue, 3, 23, 19, // Skip to: 13726
+/* 8839 */ MCD_OPC_CheckPredicate, 8, 19, 19, // Skip to: 13726
+/* 8843 */ MCD_OPC_CheckField, 16, 2, 2, 13, 19, // Skip to: 13726
+/* 8849 */ MCD_OPC_Decode, 235, 8, 173, 1, // Opcode: MOVE_V
+/* 8854 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 8867
+/* 8858 */ MCD_OPC_CheckPredicate, 8, 0, 19, // Skip to: 13726
+/* 8862 */ MCD_OPC_Decode, 206, 3, 169, 1, // Opcode: COPY_U_B
+/* 8867 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 8886
+/* 8871 */ MCD_OPC_CheckPredicate, 8, 243, 18, // Skip to: 13726
+/* 8875 */ MCD_OPC_CheckField, 19, 1, 0, 237, 18, // Skip to: 13726
+/* 8881 */ MCD_OPC_Decode, 208, 3, 170, 1, // Opcode: COPY_U_H
+/* 8886 */ MCD_OPC_FilterValue, 15, 35, 0, // Skip to: 8925
+/* 8890 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ...
+/* 8893 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8906
+/* 8897 */ MCD_OPC_CheckPredicate, 8, 217, 18, // Skip to: 13726
+/* 8901 */ MCD_OPC_Decode, 209, 3, 171, 1, // Opcode: COPY_U_W
+/* 8906 */ MCD_OPC_FilterValue, 2, 208, 18, // Skip to: 13726
+/* 8910 */ MCD_OPC_CheckPredicate, 14, 204, 18, // Skip to: 13726
+/* 8914 */ MCD_OPC_CheckField, 17, 1, 0, 198, 18, // Skip to: 13726
+/* 8920 */ MCD_OPC_Decode, 207, 3, 172, 1, // Opcode: COPY_U_D
+/* 8925 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 8938
+/* 8929 */ MCD_OPC_CheckPredicate, 8, 185, 18, // Skip to: 13726
+/* 8933 */ MCD_OPC_Decode, 229, 6, 174, 1, // Opcode: INSERT_B
+/* 8938 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 8957
+/* 8942 */ MCD_OPC_CheckPredicate, 8, 172, 18, // Skip to: 13726
+/* 8946 */ MCD_OPC_CheckField, 19, 1, 0, 166, 18, // Skip to: 13726
+/* 8952 */ MCD_OPC_Decode, 237, 6, 175, 1, // Opcode: INSERT_H
+/* 8957 */ MCD_OPC_FilterValue, 19, 35, 0, // Skip to: 8996
+/* 8961 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ...
+/* 8964 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8977
+/* 8968 */ MCD_OPC_CheckPredicate, 8, 146, 18, // Skip to: 13726
+/* 8972 */ MCD_OPC_Decode, 239, 6, 176, 1, // Opcode: INSERT_W
+/* 8977 */ MCD_OPC_FilterValue, 2, 137, 18, // Skip to: 13726
+/* 8981 */ MCD_OPC_CheckPredicate, 14, 133, 18, // Skip to: 13726
+/* 8985 */ MCD_OPC_CheckField, 17, 1, 0, 127, 18, // Skip to: 13726
+/* 8991 */ MCD_OPC_Decode, 231, 6, 177, 1, // Opcode: INSERT_D
+/* 8996 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 9009
+/* 9000 */ MCD_OPC_CheckPredicate, 8, 114, 18, // Skip to: 13726
+/* 9004 */ MCD_OPC_Decode, 242, 6, 178, 1, // Opcode: INSVE_B
+/* 9009 */ MCD_OPC_FilterValue, 22, 15, 0, // Skip to: 9028
+/* 9013 */ MCD_OPC_CheckPredicate, 8, 101, 18, // Skip to: 13726
+/* 9017 */ MCD_OPC_CheckField, 19, 1, 0, 95, 18, // Skip to: 13726
+/* 9023 */ MCD_OPC_Decode, 244, 6, 178, 1, // Opcode: INSVE_H
+/* 9028 */ MCD_OPC_FilterValue, 23, 86, 18, // Skip to: 13726
+/* 9032 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ...
+/* 9035 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9048
+/* 9039 */ MCD_OPC_CheckPredicate, 8, 75, 18, // Skip to: 13726
+/* 9043 */ MCD_OPC_Decode, 245, 6, 178, 1, // Opcode: INSVE_W
+/* 9048 */ MCD_OPC_FilterValue, 2, 66, 18, // Skip to: 13726
+/* 9052 */ MCD_OPC_CheckPredicate, 8, 62, 18, // Skip to: 13726
+/* 9056 */ MCD_OPC_CheckField, 17, 1, 0, 56, 18, // Skip to: 13726
+/* 9062 */ MCD_OPC_Decode, 243, 6, 178, 1, // Opcode: INSVE_D
+/* 9067 */ MCD_OPC_FilterValue, 26, 163, 1, // Skip to: 9490
+/* 9071 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 9074 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9087
+/* 9078 */ MCD_OPC_CheckPredicate, 8, 36, 18, // Skip to: 13726
+/* 9082 */ MCD_OPC_Decode, 178, 5, 139, 1, // Opcode: FCAF_W
+/* 9087 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 9100
+/* 9091 */ MCD_OPC_CheckPredicate, 8, 23, 18, // Skip to: 13726
+/* 9095 */ MCD_OPC_Decode, 177, 5, 140, 1, // Opcode: FCAF_D
+/* 9100 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9113
+/* 9104 */ MCD_OPC_CheckPredicate, 8, 10, 18, // Skip to: 13726
+/* 9108 */ MCD_OPC_Decode, 205, 5, 139, 1, // Opcode: FCUN_W
+/* 9113 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9126
+/* 9117 */ MCD_OPC_CheckPredicate, 8, 253, 17, // Skip to: 13726
+/* 9121 */ MCD_OPC_Decode, 204, 5, 140, 1, // Opcode: FCUN_D
+/* 9126 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9139
+/* 9130 */ MCD_OPC_CheckPredicate, 8, 240, 17, // Skip to: 13726
+/* 9134 */ MCD_OPC_Decode, 180, 5, 139, 1, // Opcode: FCEQ_W
+/* 9139 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 9152
+/* 9143 */ MCD_OPC_CheckPredicate, 8, 227, 17, // Skip to: 13726
+/* 9147 */ MCD_OPC_Decode, 179, 5, 140, 1, // Opcode: FCEQ_D
+/* 9152 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 9165
+/* 9156 */ MCD_OPC_CheckPredicate, 8, 214, 17, // Skip to: 13726
+/* 9160 */ MCD_OPC_Decode, 197, 5, 139, 1, // Opcode: FCUEQ_W
+/* 9165 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 9178
+/* 9169 */ MCD_OPC_CheckPredicate, 8, 201, 17, // Skip to: 13726
+/* 9173 */ MCD_OPC_Decode, 196, 5, 140, 1, // Opcode: FCUEQ_D
+/* 9178 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 9191
+/* 9182 */ MCD_OPC_CheckPredicate, 8, 188, 17, // Skip to: 13726
+/* 9186 */ MCD_OPC_Decode, 186, 5, 139, 1, // Opcode: FCLT_W
+/* 9191 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 9204
+/* 9195 */ MCD_OPC_CheckPredicate, 8, 175, 17, // Skip to: 13726
+/* 9199 */ MCD_OPC_Decode, 185, 5, 140, 1, // Opcode: FCLT_D
+/* 9204 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 9217
+/* 9208 */ MCD_OPC_CheckPredicate, 8, 162, 17, // Skip to: 13726
+/* 9212 */ MCD_OPC_Decode, 201, 5, 139, 1, // Opcode: FCULT_W
+/* 9217 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 9230
+/* 9221 */ MCD_OPC_CheckPredicate, 8, 149, 17, // Skip to: 13726
+/* 9225 */ MCD_OPC_Decode, 200, 5, 140, 1, // Opcode: FCULT_D
+/* 9230 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 9243
+/* 9234 */ MCD_OPC_CheckPredicate, 8, 136, 17, // Skip to: 13726
+/* 9238 */ MCD_OPC_Decode, 184, 5, 139, 1, // Opcode: FCLE_W
+/* 9243 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 9256
+/* 9247 */ MCD_OPC_CheckPredicate, 8, 123, 17, // Skip to: 13726
+/* 9251 */ MCD_OPC_Decode, 183, 5, 140, 1, // Opcode: FCLE_D
+/* 9256 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 9269
+/* 9260 */ MCD_OPC_CheckPredicate, 8, 110, 17, // Skip to: 13726
+/* 9264 */ MCD_OPC_Decode, 199, 5, 139, 1, // Opcode: FCULE_W
+/* 9269 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 9282
+/* 9273 */ MCD_OPC_CheckPredicate, 8, 97, 17, // Skip to: 13726
+/* 9277 */ MCD_OPC_Decode, 198, 5, 140, 1, // Opcode: FCULE_D
+/* 9282 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 9295
+/* 9286 */ MCD_OPC_CheckPredicate, 8, 84, 17, // Skip to: 13726
+/* 9290 */ MCD_OPC_Decode, 154, 6, 139, 1, // Opcode: FSAF_W
+/* 9295 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 9308
+/* 9299 */ MCD_OPC_CheckPredicate, 8, 71, 17, // Skip to: 13726
+/* 9303 */ MCD_OPC_Decode, 153, 6, 140, 1, // Opcode: FSAF_D
+/* 9308 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 9321
+/* 9312 */ MCD_OPC_CheckPredicate, 8, 58, 17, // Skip to: 13726
+/* 9316 */ MCD_OPC_Decode, 188, 6, 139, 1, // Opcode: FSUN_W
+/* 9321 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 9334
+/* 9325 */ MCD_OPC_CheckPredicate, 8, 45, 17, // Skip to: 13726
+/* 9329 */ MCD_OPC_Decode, 187, 6, 140, 1, // Opcode: FSUN_D
+/* 9334 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 9347
+/* 9338 */ MCD_OPC_CheckPredicate, 8, 32, 17, // Skip to: 13726
+/* 9342 */ MCD_OPC_Decode, 156, 6, 139, 1, // Opcode: FSEQ_W
+/* 9347 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 9360
+/* 9351 */ MCD_OPC_CheckPredicate, 8, 19, 17, // Skip to: 13726
+/* 9355 */ MCD_OPC_Decode, 155, 6, 140, 1, // Opcode: FSEQ_D
+/* 9360 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 9373
+/* 9364 */ MCD_OPC_CheckPredicate, 8, 6, 17, // Skip to: 13726
+/* 9368 */ MCD_OPC_Decode, 180, 6, 139, 1, // Opcode: FSUEQ_W
+/* 9373 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 9386
+/* 9377 */ MCD_OPC_CheckPredicate, 8, 249, 16, // Skip to: 13726
+/* 9381 */ MCD_OPC_Decode, 179, 6, 140, 1, // Opcode: FSUEQ_D
+/* 9386 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 9399
+/* 9390 */ MCD_OPC_CheckPredicate, 8, 236, 16, // Skip to: 13726
+/* 9394 */ MCD_OPC_Decode, 160, 6, 139, 1, // Opcode: FSLT_W
+/* 9399 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 9412
+/* 9403 */ MCD_OPC_CheckPredicate, 8, 223, 16, // Skip to: 13726
+/* 9407 */ MCD_OPC_Decode, 159, 6, 140, 1, // Opcode: FSLT_D
+/* 9412 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 9425
+/* 9416 */ MCD_OPC_CheckPredicate, 8, 210, 16, // Skip to: 13726
+/* 9420 */ MCD_OPC_Decode, 184, 6, 139, 1, // Opcode: FSULT_W
+/* 9425 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 9438
+/* 9429 */ MCD_OPC_CheckPredicate, 8, 197, 16, // Skip to: 13726
+/* 9433 */ MCD_OPC_Decode, 183, 6, 140, 1, // Opcode: FSULT_D
+/* 9438 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 9451
+/* 9442 */ MCD_OPC_CheckPredicate, 8, 184, 16, // Skip to: 13726
+/* 9446 */ MCD_OPC_Decode, 158, 6, 139, 1, // Opcode: FSLE_W
+/* 9451 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 9464
+/* 9455 */ MCD_OPC_CheckPredicate, 8, 171, 16, // Skip to: 13726
+/* 9459 */ MCD_OPC_Decode, 157, 6, 140, 1, // Opcode: FSLE_D
+/* 9464 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 9477
+/* 9468 */ MCD_OPC_CheckPredicate, 8, 158, 16, // Skip to: 13726
+/* 9472 */ MCD_OPC_Decode, 182, 6, 139, 1, // Opcode: FSULE_W
+/* 9477 */ MCD_OPC_FilterValue, 31, 149, 16, // Skip to: 13726
+/* 9481 */ MCD_OPC_CheckPredicate, 8, 145, 16, // Skip to: 13726
+/* 9485 */ MCD_OPC_Decode, 181, 6, 140, 1, // Opcode: FSULE_D
+/* 9490 */ MCD_OPC_FilterValue, 27, 85, 1, // Skip to: 9835
+/* 9494 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 9497 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9510
+/* 9501 */ MCD_OPC_CheckPredicate, 8, 125, 16, // Skip to: 13726
+/* 9505 */ MCD_OPC_Decode, 176, 5, 139, 1, // Opcode: FADD_W
+/* 9510 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 9523
+/* 9514 */ MCD_OPC_CheckPredicate, 8, 112, 16, // Skip to: 13726
+/* 9518 */ MCD_OPC_Decode, 170, 5, 140, 1, // Opcode: FADD_D
+/* 9523 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9536
+/* 9527 */ MCD_OPC_CheckPredicate, 8, 99, 16, // Skip to: 13726
+/* 9531 */ MCD_OPC_Decode, 178, 6, 139, 1, // Opcode: FSUB_W
+/* 9536 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9549
+/* 9540 */ MCD_OPC_CheckPredicate, 8, 86, 16, // Skip to: 13726
+/* 9544 */ MCD_OPC_Decode, 172, 6, 140, 1, // Opcode: FSUB_D
+/* 9549 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9562
+/* 9553 */ MCD_OPC_CheckPredicate, 8, 73, 16, // Skip to: 13726
+/* 9557 */ MCD_OPC_Decode, 141, 6, 139, 1, // Opcode: FMUL_W
+/* 9562 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 9575
+/* 9566 */ MCD_OPC_CheckPredicate, 8, 60, 16, // Skip to: 13726
+/* 9570 */ MCD_OPC_Decode, 135, 6, 140, 1, // Opcode: FMUL_D
+/* 9575 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 9588
+/* 9579 */ MCD_OPC_CheckPredicate, 8, 47, 16, // Skip to: 13726
+/* 9583 */ MCD_OPC_Decode, 212, 5, 139, 1, // Opcode: FDIV_W
+/* 9588 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 9601
+/* 9592 */ MCD_OPC_CheckPredicate, 8, 34, 16, // Skip to: 13726
+/* 9596 */ MCD_OPC_Decode, 206, 5, 140, 1, // Opcode: FDIV_D
+/* 9601 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 9614
+/* 9605 */ MCD_OPC_CheckPredicate, 8, 21, 16, // Skip to: 13726
+/* 9609 */ MCD_OPC_Decode, 247, 5, 143, 1, // Opcode: FMADD_W
+/* 9614 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 9627
+/* 9618 */ MCD_OPC_CheckPredicate, 8, 8, 16, // Skip to: 13726
+/* 9622 */ MCD_OPC_Decode, 246, 5, 144, 1, // Opcode: FMADD_D
+/* 9627 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 9640
+/* 9631 */ MCD_OPC_CheckPredicate, 8, 251, 15, // Skip to: 13726
+/* 9635 */ MCD_OPC_Decode, 134, 6, 143, 1, // Opcode: FMSUB_W
+/* 9640 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 9653
+/* 9644 */ MCD_OPC_CheckPredicate, 8, 238, 15, // Skip to: 13726
+/* 9648 */ MCD_OPC_Decode, 133, 6, 144, 1, // Opcode: FMSUB_D
+/* 9653 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 9666
+/* 9657 */ MCD_OPC_CheckPredicate, 8, 225, 15, // Skip to: 13726
+/* 9661 */ MCD_OPC_Decode, 217, 5, 139, 1, // Opcode: FEXP2_W
+/* 9666 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 9679
+/* 9670 */ MCD_OPC_CheckPredicate, 8, 212, 15, // Skip to: 13726
+/* 9674 */ MCD_OPC_Decode, 215, 5, 140, 1, // Opcode: FEXP2_D
+/* 9679 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 9692
+/* 9683 */ MCD_OPC_CheckPredicate, 8, 199, 15, // Skip to: 13726
+/* 9687 */ MCD_OPC_Decode, 213, 5, 179, 1, // Opcode: FEXDO_H
+/* 9692 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 9705
+/* 9696 */ MCD_OPC_CheckPredicate, 8, 186, 15, // Skip to: 13726
+/* 9700 */ MCD_OPC_Decode, 214, 5, 180, 1, // Opcode: FEXDO_W
+/* 9705 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 9718
+/* 9709 */ MCD_OPC_CheckPredicate, 8, 173, 15, // Skip to: 13726
+/* 9713 */ MCD_OPC_Decode, 193, 6, 179, 1, // Opcode: FTQ_H
+/* 9718 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 9731
+/* 9722 */ MCD_OPC_CheckPredicate, 8, 160, 15, // Skip to: 13726
+/* 9726 */ MCD_OPC_Decode, 194, 6, 180, 1, // Opcode: FTQ_W
+/* 9731 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 9744
+/* 9735 */ MCD_OPC_CheckPredicate, 8, 147, 15, // Skip to: 13726
+/* 9739 */ MCD_OPC_Decode, 255, 5, 139, 1, // Opcode: FMIN_W
+/* 9744 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 9757
+/* 9748 */ MCD_OPC_CheckPredicate, 8, 134, 15, // Skip to: 13726
+/* 9752 */ MCD_OPC_Decode, 254, 5, 140, 1, // Opcode: FMIN_D
+/* 9757 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 9770
+/* 9761 */ MCD_OPC_CheckPredicate, 8, 121, 15, // Skip to: 13726
+/* 9765 */ MCD_OPC_Decode, 253, 5, 139, 1, // Opcode: FMIN_A_W
+/* 9770 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 9783
+/* 9774 */ MCD_OPC_CheckPredicate, 8, 108, 15, // Skip to: 13726
+/* 9778 */ MCD_OPC_Decode, 252, 5, 140, 1, // Opcode: FMIN_A_D
+/* 9783 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 9796
+/* 9787 */ MCD_OPC_CheckPredicate, 8, 95, 15, // Skip to: 13726
+/* 9791 */ MCD_OPC_Decode, 251, 5, 139, 1, // Opcode: FMAX_W
+/* 9796 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 9809
+/* 9800 */ MCD_OPC_CheckPredicate, 8, 82, 15, // Skip to: 13726
+/* 9804 */ MCD_OPC_Decode, 250, 5, 140, 1, // Opcode: FMAX_D
+/* 9809 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 9822
+/* 9813 */ MCD_OPC_CheckPredicate, 8, 69, 15, // Skip to: 13726
+/* 9817 */ MCD_OPC_Decode, 249, 5, 139, 1, // Opcode: FMAX_A_W
+/* 9822 */ MCD_OPC_FilterValue, 31, 60, 15, // Skip to: 13726
+/* 9826 */ MCD_OPC_CheckPredicate, 8, 56, 15, // Skip to: 13726
+/* 9830 */ MCD_OPC_Decode, 248, 5, 140, 1, // Opcode: FMAX_A_D
+/* 9835 */ MCD_OPC_FilterValue, 28, 59, 1, // Skip to: 10154
+/* 9839 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 9842 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9855
+/* 9846 */ MCD_OPC_CheckPredicate, 8, 36, 15, // Skip to: 13726
+/* 9850 */ MCD_OPC_Decode, 195, 5, 139, 1, // Opcode: FCOR_W
+/* 9855 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9868
+/* 9859 */ MCD_OPC_CheckPredicate, 8, 23, 15, // Skip to: 13726
+/* 9863 */ MCD_OPC_Decode, 194, 5, 140, 1, // Opcode: FCOR_D
+/* 9868 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9881
+/* 9872 */ MCD_OPC_CheckPredicate, 8, 10, 15, // Skip to: 13726
+/* 9876 */ MCD_OPC_Decode, 203, 5, 139, 1, // Opcode: FCUNE_W
+/* 9881 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 9894
+/* 9885 */ MCD_OPC_CheckPredicate, 8, 253, 14, // Skip to: 13726
+/* 9889 */ MCD_OPC_Decode, 202, 5, 140, 1, // Opcode: FCUNE_D
+/* 9894 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 9907
+/* 9898 */ MCD_OPC_CheckPredicate, 8, 240, 14, // Skip to: 13726
+/* 9902 */ MCD_OPC_Decode, 193, 5, 139, 1, // Opcode: FCNE_W
+/* 9907 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 9920
+/* 9911 */ MCD_OPC_CheckPredicate, 8, 227, 14, // Skip to: 13726
+/* 9915 */ MCD_OPC_Decode, 192, 5, 140, 1, // Opcode: FCNE_D
+/* 9920 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 9933
+/* 9924 */ MCD_OPC_CheckPredicate, 8, 214, 14, // Skip to: 13726
+/* 9928 */ MCD_OPC_Decode, 219, 9, 138, 1, // Opcode: MUL_Q_H
+/* 9933 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 9946
+/* 9937 */ MCD_OPC_CheckPredicate, 8, 201, 14, // Skip to: 13726
+/* 9941 */ MCD_OPC_Decode, 220, 9, 139, 1, // Opcode: MUL_Q_W
+/* 9946 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 9959
+/* 9950 */ MCD_OPC_CheckPredicate, 8, 188, 14, // Skip to: 13726
+/* 9954 */ MCD_OPC_Decode, 147, 8, 142, 1, // Opcode: MADD_Q_H
+/* 9959 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 9972
+/* 9963 */ MCD_OPC_CheckPredicate, 8, 175, 14, // Skip to: 13726
+/* 9967 */ MCD_OPC_Decode, 148, 8, 143, 1, // Opcode: MADD_Q_W
+/* 9972 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 9985
+/* 9976 */ MCD_OPC_CheckPredicate, 8, 162, 14, // Skip to: 13726
+/* 9980 */ MCD_OPC_Decode, 165, 9, 142, 1, // Opcode: MSUB_Q_H
+/* 9985 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 9998
+/* 9989 */ MCD_OPC_CheckPredicate, 8, 149, 14, // Skip to: 13726
+/* 9993 */ MCD_OPC_Decode, 166, 9, 143, 1, // Opcode: MSUB_Q_W
+/* 9998 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 10011
+/* 10002 */ MCD_OPC_CheckPredicate, 8, 136, 14, // Skip to: 13726
+/* 10006 */ MCD_OPC_Decode, 164, 6, 139, 1, // Opcode: FSOR_W
+/* 10011 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 10024
+/* 10015 */ MCD_OPC_CheckPredicate, 8, 123, 14, // Skip to: 13726
+/* 10019 */ MCD_OPC_Decode, 163, 6, 140, 1, // Opcode: FSOR_D
+/* 10024 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 10037
+/* 10028 */ MCD_OPC_CheckPredicate, 8, 110, 14, // Skip to: 13726
+/* 10032 */ MCD_OPC_Decode, 186, 6, 139, 1, // Opcode: FSUNE_W
+/* 10037 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 10050
+/* 10041 */ MCD_OPC_CheckPredicate, 8, 97, 14, // Skip to: 13726
+/* 10045 */ MCD_OPC_Decode, 185, 6, 140, 1, // Opcode: FSUNE_D
+/* 10050 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 10063
+/* 10054 */ MCD_OPC_CheckPredicate, 8, 84, 14, // Skip to: 13726
+/* 10058 */ MCD_OPC_Decode, 162, 6, 139, 1, // Opcode: FSNE_W
+/* 10063 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 10076
+/* 10067 */ MCD_OPC_CheckPredicate, 8, 71, 14, // Skip to: 13726
+/* 10071 */ MCD_OPC_Decode, 161, 6, 140, 1, // Opcode: FSNE_D
+/* 10076 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 10089
+/* 10080 */ MCD_OPC_CheckPredicate, 8, 58, 14, // Skip to: 13726
+/* 10084 */ MCD_OPC_Decode, 202, 9, 138, 1, // Opcode: MULR_Q_H
+/* 10089 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 10102
+/* 10093 */ MCD_OPC_CheckPredicate, 8, 45, 14, // Skip to: 13726
+/* 10097 */ MCD_OPC_Decode, 203, 9, 139, 1, // Opcode: MULR_Q_W
+/* 10102 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 10115
+/* 10106 */ MCD_OPC_CheckPredicate, 8, 32, 14, // Skip to: 13726
+/* 10110 */ MCD_OPC_Decode, 133, 8, 142, 1, // Opcode: MADDR_Q_H
+/* 10115 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 10128
+/* 10119 */ MCD_OPC_CheckPredicate, 8, 19, 14, // Skip to: 13726
+/* 10123 */ MCD_OPC_Decode, 134, 8, 143, 1, // Opcode: MADDR_Q_W
+/* 10128 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 10141
+/* 10132 */ MCD_OPC_CheckPredicate, 8, 6, 14, // Skip to: 13726
+/* 10136 */ MCD_OPC_Decode, 151, 9, 142, 1, // Opcode: MSUBR_Q_H
+/* 10141 */ MCD_OPC_FilterValue, 29, 253, 13, // Skip to: 13726
+/* 10145 */ MCD_OPC_CheckPredicate, 8, 249, 13, // Skip to: 13726
+/* 10149 */ MCD_OPC_Decode, 152, 9, 143, 1, // Opcode: MSUBR_Q_W
+/* 10154 */ MCD_OPC_FilterValue, 30, 219, 2, // Skip to: 10889
+/* 10158 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 10161 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10173
+/* 10165 */ MCD_OPC_CheckPredicate, 8, 229, 13, // Skip to: 13726
+/* 10169 */ MCD_OPC_Decode, 89, 137, 1, // Opcode: AND_V
+/* 10173 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10186
+/* 10177 */ MCD_OPC_CheckPredicate, 8, 217, 13, // Skip to: 13726
+/* 10181 */ MCD_OPC_Decode, 138, 10, 137, 1, // Opcode: OR_V
+/* 10186 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10199
+/* 10190 */ MCD_OPC_CheckPredicate, 8, 204, 13, // Skip to: 13726
+/* 10194 */ MCD_OPC_Decode, 254, 9, 137, 1, // Opcode: NOR_V
+/* 10199 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10212
+/* 10203 */ MCD_OPC_CheckPredicate, 8, 191, 13, // Skip to: 13726
+/* 10207 */ MCD_OPC_Decode, 241, 13, 137, 1, // Opcode: XOR_V
+/* 10212 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10225
+/* 10216 */ MCD_OPC_CheckPredicate, 8, 178, 13, // Skip to: 13726
+/* 10220 */ MCD_OPC_Decode, 142, 2, 141, 1, // Opcode: BMNZ_V
+/* 10225 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10238
+/* 10229 */ MCD_OPC_CheckPredicate, 8, 165, 13, // Skip to: 13726
+/* 10233 */ MCD_OPC_Decode, 144, 2, 141, 1, // Opcode: BMZ_V
+/* 10238 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10251
+/* 10242 */ MCD_OPC_CheckPredicate, 8, 152, 13, // Skip to: 13726
+/* 10246 */ MCD_OPC_Decode, 179, 2, 141, 1, // Opcode: BSEL_V
+/* 10251 */ MCD_OPC_FilterValue, 24, 211, 0, // Skip to: 10466
+/* 10255 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ...
+/* 10258 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10271
+/* 10262 */ MCD_OPC_CheckPredicate, 8, 132, 13, // Skip to: 13726
+/* 10266 */ MCD_OPC_Decode, 231, 5, 181, 1, // Opcode: FILL_B
+/* 10271 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10284
+/* 10275 */ MCD_OPC_CheckPredicate, 8, 119, 13, // Skip to: 13726
+/* 10279 */ MCD_OPC_Decode, 235, 5, 182, 1, // Opcode: FILL_H
+/* 10284 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10297
+/* 10288 */ MCD_OPC_CheckPredicate, 8, 106, 13, // Skip to: 13726
+/* 10292 */ MCD_OPC_Decode, 236, 5, 183, 1, // Opcode: FILL_W
+/* 10297 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10310
+/* 10301 */ MCD_OPC_CheckPredicate, 14, 93, 13, // Skip to: 13726
+/* 10305 */ MCD_OPC_Decode, 232, 5, 184, 1, // Opcode: FILL_D
+/* 10310 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10323
+/* 10314 */ MCD_OPC_CheckPredicate, 8, 80, 13, // Skip to: 13726
+/* 10318 */ MCD_OPC_Decode, 157, 10, 173, 1, // Opcode: PCNT_B
+/* 10323 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10336
+/* 10327 */ MCD_OPC_CheckPredicate, 8, 67, 13, // Skip to: 13726
+/* 10331 */ MCD_OPC_Decode, 159, 10, 185, 1, // Opcode: PCNT_H
+/* 10336 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10349
+/* 10340 */ MCD_OPC_CheckPredicate, 8, 54, 13, // Skip to: 13726
+/* 10344 */ MCD_OPC_Decode, 160, 10, 186, 1, // Opcode: PCNT_W
+/* 10349 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 10362
+/* 10353 */ MCD_OPC_CheckPredicate, 8, 41, 13, // Skip to: 13726
+/* 10357 */ MCD_OPC_Decode, 158, 10, 187, 1, // Opcode: PCNT_D
+/* 10362 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 10375
+/* 10366 */ MCD_OPC_CheckPredicate, 8, 28, 13, // Skip to: 13726
+/* 10370 */ MCD_OPC_Decode, 231, 9, 173, 1, // Opcode: NLOC_B
+/* 10375 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 10388
+/* 10379 */ MCD_OPC_CheckPredicate, 8, 15, 13, // Skip to: 13726
+/* 10383 */ MCD_OPC_Decode, 233, 9, 185, 1, // Opcode: NLOC_H
+/* 10388 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 10401
+/* 10392 */ MCD_OPC_CheckPredicate, 8, 2, 13, // Skip to: 13726
+/* 10396 */ MCD_OPC_Decode, 234, 9, 186, 1, // Opcode: NLOC_W
+/* 10401 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 10414
+/* 10405 */ MCD_OPC_CheckPredicate, 8, 245, 12, // Skip to: 13726
+/* 10409 */ MCD_OPC_Decode, 232, 9, 187, 1, // Opcode: NLOC_D
+/* 10414 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 10427
+/* 10418 */ MCD_OPC_CheckPredicate, 8, 232, 12, // Skip to: 13726
+/* 10422 */ MCD_OPC_Decode, 235, 9, 173, 1, // Opcode: NLZC_B
+/* 10427 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 10440
+/* 10431 */ MCD_OPC_CheckPredicate, 8, 219, 12, // Skip to: 13726
+/* 10435 */ MCD_OPC_Decode, 237, 9, 185, 1, // Opcode: NLZC_H
+/* 10440 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 10453
+/* 10444 */ MCD_OPC_CheckPredicate, 8, 206, 12, // Skip to: 13726
+/* 10448 */ MCD_OPC_Decode, 238, 9, 186, 1, // Opcode: NLZC_W
+/* 10453 */ MCD_OPC_FilterValue, 15, 197, 12, // Skip to: 13726
+/* 10457 */ MCD_OPC_CheckPredicate, 8, 193, 12, // Skip to: 13726
+/* 10461 */ MCD_OPC_Decode, 236, 9, 187, 1, // Opcode: NLZC_D
+/* 10466 */ MCD_OPC_FilterValue, 25, 184, 12, // Skip to: 13726
+/* 10470 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ...
+/* 10473 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10486
+/* 10477 */ MCD_OPC_CheckPredicate, 8, 173, 12, // Skip to: 13726
+/* 10481 */ MCD_OPC_Decode, 182, 5, 186, 1, // Opcode: FCLASS_W
+/* 10486 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10499
+/* 10490 */ MCD_OPC_CheckPredicate, 8, 160, 12, // Skip to: 13726
+/* 10494 */ MCD_OPC_Decode, 181, 5, 187, 1, // Opcode: FCLASS_D
+/* 10499 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10512
+/* 10503 */ MCD_OPC_CheckPredicate, 8, 147, 12, // Skip to: 13726
+/* 10507 */ MCD_OPC_Decode, 196, 6, 186, 1, // Opcode: FTRUNC_S_W
+/* 10512 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10525
+/* 10516 */ MCD_OPC_CheckPredicate, 8, 134, 12, // Skip to: 13726
+/* 10520 */ MCD_OPC_Decode, 195, 6, 187, 1, // Opcode: FTRUNC_S_D
+/* 10525 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10538
+/* 10529 */ MCD_OPC_CheckPredicate, 8, 121, 12, // Skip to: 13726
+/* 10533 */ MCD_OPC_Decode, 198, 6, 186, 1, // Opcode: FTRUNC_U_W
+/* 10538 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10551
+/* 10542 */ MCD_OPC_CheckPredicate, 8, 108, 12, // Skip to: 13726
+/* 10546 */ MCD_OPC_Decode, 197, 6, 187, 1, // Opcode: FTRUNC_U_D
+/* 10551 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10564
+/* 10555 */ MCD_OPC_CheckPredicate, 8, 95, 12, // Skip to: 13726
+/* 10559 */ MCD_OPC_Decode, 171, 6, 186, 1, // Opcode: FSQRT_W
+/* 10564 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 10577
+/* 10568 */ MCD_OPC_CheckPredicate, 8, 82, 12, // Skip to: 13726
+/* 10572 */ MCD_OPC_Decode, 165, 6, 187, 1, // Opcode: FSQRT_D
+/* 10577 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 10590
+/* 10581 */ MCD_OPC_CheckPredicate, 8, 69, 12, // Skip to: 13726
+/* 10585 */ MCD_OPC_Decode, 152, 6, 186, 1, // Opcode: FRSQRT_W
+/* 10590 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 10603
+/* 10594 */ MCD_OPC_CheckPredicate, 8, 56, 12, // Skip to: 13726
+/* 10598 */ MCD_OPC_Decode, 151, 6, 187, 1, // Opcode: FRSQRT_D
+/* 10603 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 10616
+/* 10607 */ MCD_OPC_CheckPredicate, 8, 43, 12, // Skip to: 13726
+/* 10611 */ MCD_OPC_Decode, 148, 6, 186, 1, // Opcode: FRCP_W
+/* 10616 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 10629
+/* 10620 */ MCD_OPC_CheckPredicate, 8, 30, 12, // Skip to: 13726
+/* 10624 */ MCD_OPC_Decode, 147, 6, 187, 1, // Opcode: FRCP_D
+/* 10629 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 10642
+/* 10633 */ MCD_OPC_CheckPredicate, 8, 17, 12, // Skip to: 13726
+/* 10637 */ MCD_OPC_Decode, 150, 6, 186, 1, // Opcode: FRINT_W
+/* 10642 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 10655
+/* 10646 */ MCD_OPC_CheckPredicate, 8, 4, 12, // Skip to: 13726
+/* 10650 */ MCD_OPC_Decode, 149, 6, 187, 1, // Opcode: FRINT_D
+/* 10655 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 10668
+/* 10659 */ MCD_OPC_CheckPredicate, 8, 247, 11, // Skip to: 13726
+/* 10663 */ MCD_OPC_Decode, 238, 5, 186, 1, // Opcode: FLOG2_W
+/* 10668 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 10681
+/* 10672 */ MCD_OPC_CheckPredicate, 8, 234, 11, // Skip to: 13726
+/* 10676 */ MCD_OPC_Decode, 237, 5, 187, 1, // Opcode: FLOG2_D
+/* 10681 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 10694
+/* 10685 */ MCD_OPC_CheckPredicate, 8, 221, 11, // Skip to: 13726
+/* 10689 */ MCD_OPC_Decode, 220, 5, 188, 1, // Opcode: FEXUPL_W
+/* 10694 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 10707
+/* 10698 */ MCD_OPC_CheckPredicate, 8, 208, 11, // Skip to: 13726
+/* 10702 */ MCD_OPC_Decode, 219, 5, 189, 1, // Opcode: FEXUPL_D
+/* 10707 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 10720
+/* 10711 */ MCD_OPC_CheckPredicate, 8, 195, 11, // Skip to: 13726
+/* 10715 */ MCD_OPC_Decode, 222, 5, 188, 1, // Opcode: FEXUPR_W
+/* 10720 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 10733
+/* 10724 */ MCD_OPC_CheckPredicate, 8, 182, 11, // Skip to: 13726
+/* 10728 */ MCD_OPC_Decode, 221, 5, 189, 1, // Opcode: FEXUPR_D
+/* 10733 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 10746
+/* 10737 */ MCD_OPC_CheckPredicate, 8, 169, 11, // Skip to: 13726
+/* 10741 */ MCD_OPC_Decode, 228, 5, 188, 1, // Opcode: FFQL_W
+/* 10746 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 10759
+/* 10750 */ MCD_OPC_CheckPredicate, 8, 156, 11, // Skip to: 13726
+/* 10754 */ MCD_OPC_Decode, 227, 5, 189, 1, // Opcode: FFQL_D
+/* 10759 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 10772
+/* 10763 */ MCD_OPC_CheckPredicate, 8, 143, 11, // Skip to: 13726
+/* 10767 */ MCD_OPC_Decode, 230, 5, 188, 1, // Opcode: FFQR_W
+/* 10772 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 10785
+/* 10776 */ MCD_OPC_CheckPredicate, 8, 130, 11, // Skip to: 13726
+/* 10780 */ MCD_OPC_Decode, 229, 5, 189, 1, // Opcode: FFQR_D
+/* 10785 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 10798
+/* 10789 */ MCD_OPC_CheckPredicate, 8, 117, 11, // Skip to: 13726
+/* 10793 */ MCD_OPC_Decode, 190, 6, 186, 1, // Opcode: FTINT_S_W
+/* 10798 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 10811
+/* 10802 */ MCD_OPC_CheckPredicate, 8, 104, 11, // Skip to: 13726
+/* 10806 */ MCD_OPC_Decode, 189, 6, 187, 1, // Opcode: FTINT_S_D
+/* 10811 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 10824
+/* 10815 */ MCD_OPC_CheckPredicate, 8, 91, 11, // Skip to: 13726
+/* 10819 */ MCD_OPC_Decode, 192, 6, 186, 1, // Opcode: FTINT_U_W
+/* 10824 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 10837
+/* 10828 */ MCD_OPC_CheckPredicate, 8, 78, 11, // Skip to: 13726
+/* 10832 */ MCD_OPC_Decode, 191, 6, 187, 1, // Opcode: FTINT_U_D
+/* 10837 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 10850
+/* 10841 */ MCD_OPC_CheckPredicate, 8, 65, 11, // Skip to: 13726
+/* 10845 */ MCD_OPC_Decode, 224, 5, 186, 1, // Opcode: FFINT_S_W
+/* 10850 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 10863
+/* 10854 */ MCD_OPC_CheckPredicate, 8, 52, 11, // Skip to: 13726
+/* 10858 */ MCD_OPC_Decode, 223, 5, 187, 1, // Opcode: FFINT_S_D
+/* 10863 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 10876
+/* 10867 */ MCD_OPC_CheckPredicate, 8, 39, 11, // Skip to: 13726
+/* 10871 */ MCD_OPC_Decode, 226, 5, 186, 1, // Opcode: FFINT_U_W
+/* 10876 */ MCD_OPC_FilterValue, 31, 30, 11, // Skip to: 13726
+/* 10880 */ MCD_OPC_CheckPredicate, 8, 26, 11, // Skip to: 13726
+/* 10884 */ MCD_OPC_Decode, 225, 5, 187, 1, // Opcode: FFINT_U_D
+/* 10889 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 10902
+/* 10893 */ MCD_OPC_CheckPredicate, 8, 13, 11, // Skip to: 13726
+/* 10897 */ MCD_OPC_Decode, 177, 7, 190, 1, // Opcode: LD_B
+/* 10902 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 10915
+/* 10906 */ MCD_OPC_CheckPredicate, 8, 0, 11, // Skip to: 13726
+/* 10910 */ MCD_OPC_Decode, 179, 7, 190, 1, // Opcode: LD_H
+/* 10915 */ MCD_OPC_FilterValue, 34, 9, 0, // Skip to: 10928
+/* 10919 */ MCD_OPC_CheckPredicate, 8, 243, 10, // Skip to: 13726
+/* 10923 */ MCD_OPC_Decode, 180, 7, 190, 1, // Opcode: LD_W
+/* 10928 */ MCD_OPC_FilterValue, 35, 9, 0, // Skip to: 10941
+/* 10932 */ MCD_OPC_CheckPredicate, 8, 230, 10, // Skip to: 13726
+/* 10936 */ MCD_OPC_Decode, 178, 7, 190, 1, // Opcode: LD_D
+/* 10941 */ MCD_OPC_FilterValue, 36, 9, 0, // Skip to: 10954
+/* 10945 */ MCD_OPC_CheckPredicate, 8, 217, 10, // Skip to: 13726
+/* 10949 */ MCD_OPC_Decode, 186, 12, 190, 1, // Opcode: ST_B
+/* 10954 */ MCD_OPC_FilterValue, 37, 9, 0, // Skip to: 10967
+/* 10958 */ MCD_OPC_CheckPredicate, 8, 204, 10, // Skip to: 13726
+/* 10962 */ MCD_OPC_Decode, 188, 12, 190, 1, // Opcode: ST_H
+/* 10967 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 10980
+/* 10971 */ MCD_OPC_CheckPredicate, 8, 191, 10, // Skip to: 13726
+/* 10975 */ MCD_OPC_Decode, 189, 12, 190, 1, // Opcode: ST_W
+/* 10980 */ MCD_OPC_FilterValue, 39, 182, 10, // Skip to: 13726
+/* 10984 */ MCD_OPC_CheckPredicate, 8, 178, 10, // Skip to: 13726
+/* 10988 */ MCD_OPC_Decode, 187, 12, 190, 1, // Opcode: ST_D
+/* 10993 */ MCD_OPC_FilterValue, 31, 113, 9, // Skip to: 13414
+/* 10997 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 11000 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11013
+/* 11004 */ MCD_OPC_CheckPredicate, 6, 158, 10, // Skip to: 13726
+/* 11008 */ MCD_OPC_Decode, 145, 5, 191, 1, // Opcode: EXT
+/* 11013 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11026
+/* 11017 */ MCD_OPC_CheckPredicate, 6, 145, 10, // Skip to: 13726
+/* 11021 */ MCD_OPC_Decode, 228, 6, 192, 1, // Opcode: INS
+/* 11026 */ MCD_OPC_FilterValue, 10, 42, 0, // Skip to: 11072
+/* 11030 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 11033 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11046
+/* 11037 */ MCD_OPC_CheckPredicate, 12, 125, 10, // Skip to: 13726
+/* 11041 */ MCD_OPC_Decode, 236, 7, 193, 1, // Opcode: LWX
+/* 11046 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11059
+/* 11050 */ MCD_OPC_CheckPredicate, 12, 112, 10, // Skip to: 13726
+/* 11054 */ MCD_OPC_Decode, 187, 7, 193, 1, // Opcode: LHX
+/* 11059 */ MCD_OPC_FilterValue, 6, 103, 10, // Skip to: 13726
+/* 11063 */ MCD_OPC_CheckPredicate, 12, 99, 10, // Skip to: 13726
+/* 11067 */ MCD_OPC_Decode, 156, 7, 193, 1, // Opcode: LBUX
+/* 11072 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 11091
+/* 11076 */ MCD_OPC_CheckPredicate, 12, 86, 10, // Skip to: 13726
+/* 11080 */ MCD_OPC_CheckField, 6, 10, 0, 80, 10, // Skip to: 13726
+/* 11086 */ MCD_OPC_Decode, 241, 6, 194, 1, // Opcode: INSV
+/* 11091 */ MCD_OPC_FilterValue, 16, 51, 1, // Skip to: 11402
+/* 11095 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 11098 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11110
+/* 11102 */ MCD_OPC_CheckPredicate, 12, 60, 10, // Skip to: 13726
+/* 11106 */ MCD_OPC_Decode, 56, 195, 1, // Opcode: ADDU_QB
+/* 11110 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 11123
+/* 11114 */ MCD_OPC_CheckPredicate, 12, 48, 10, // Skip to: 13726
+/* 11118 */ MCD_OPC_Decode, 218, 12, 195, 1, // Opcode: SUBU_QB
+/* 11123 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 11135
+/* 11127 */ MCD_OPC_CheckPredicate, 12, 35, 10, // Skip to: 13726
+/* 11131 */ MCD_OPC_Decode, 58, 195, 1, // Opcode: ADDU_S_QB
+/* 11135 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 11148
+/* 11139 */ MCD_OPC_CheckPredicate, 12, 23, 10, // Skip to: 13726
+/* 11143 */ MCD_OPC_Decode, 220, 12, 195, 1, // Opcode: SUBU_S_QB
+/* 11148 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 11161
+/* 11152 */ MCD_OPC_CheckPredicate, 12, 10, 10, // Skip to: 13726
+/* 11156 */ MCD_OPC_Decode, 196, 9, 195, 1, // Opcode: MULEU_S_PH_QBL
+/* 11161 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 11174
+/* 11165 */ MCD_OPC_CheckPredicate, 12, 253, 9, // Skip to: 13726
+/* 11169 */ MCD_OPC_Decode, 197, 9, 195, 1, // Opcode: MULEU_S_PH_QBR
+/* 11174 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 11186
+/* 11178 */ MCD_OPC_CheckPredicate, 30, 240, 9, // Skip to: 13726
+/* 11182 */ MCD_OPC_Decode, 55, 195, 1, // Opcode: ADDU_PH
+/* 11186 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 11199
+/* 11190 */ MCD_OPC_CheckPredicate, 30, 228, 9, // Skip to: 13726
+/* 11194 */ MCD_OPC_Decode, 217, 12, 195, 1, // Opcode: SUBU_PH
+/* 11199 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 11211
+/* 11203 */ MCD_OPC_CheckPredicate, 12, 215, 9, // Skip to: 13726
+/* 11207 */ MCD_OPC_Decode, 36, 195, 1, // Opcode: ADDQ_PH
+/* 11211 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 11224
+/* 11215 */ MCD_OPC_CheckPredicate, 12, 203, 9, // Skip to: 13726
+/* 11219 */ MCD_OPC_Decode, 195, 12, 195, 1, // Opcode: SUBQ_PH
+/* 11224 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 11236
+/* 11228 */ MCD_OPC_CheckPredicate, 30, 190, 9, // Skip to: 13726
+/* 11232 */ MCD_OPC_Decode, 57, 195, 1, // Opcode: ADDU_S_PH
+/* 11236 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 11249
+/* 11240 */ MCD_OPC_CheckPredicate, 30, 178, 9, // Skip to: 13726
+/* 11244 */ MCD_OPC_Decode, 219, 12, 195, 1, // Opcode: SUBU_S_PH
+/* 11249 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 11261
+/* 11253 */ MCD_OPC_CheckPredicate, 12, 165, 9, // Skip to: 13726
+/* 11257 */ MCD_OPC_Decode, 37, 195, 1, // Opcode: ADDQ_S_PH
+/* 11261 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 11274
+/* 11265 */ MCD_OPC_CheckPredicate, 12, 153, 9, // Skip to: 13726
+/* 11269 */ MCD_OPC_Decode, 196, 12, 195, 1, // Opcode: SUBQ_S_PH
+/* 11274 */ MCD_OPC_FilterValue, 16, 7, 0, // Skip to: 11285
+/* 11278 */ MCD_OPC_CheckPredicate, 12, 140, 9, // Skip to: 13726
+/* 11282 */ MCD_OPC_Decode, 39, 35, // Opcode: ADDSC
+/* 11285 */ MCD_OPC_FilterValue, 17, 7, 0, // Skip to: 11296
+/* 11289 */ MCD_OPC_CheckPredicate, 12, 129, 9, // Skip to: 13726
+/* 11293 */ MCD_OPC_Decode, 67, 35, // Opcode: ADDWC
+/* 11296 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 11308
+/* 11300 */ MCD_OPC_CheckPredicate, 12, 118, 9, // Skip to: 13726
+/* 11304 */ MCD_OPC_Decode, 223, 8, 35, // Opcode: MODSUB
+/* 11308 */ MCD_OPC_FilterValue, 20, 15, 0, // Skip to: 11327
+/* 11312 */ MCD_OPC_CheckPredicate, 12, 106, 9, // Skip to: 13726
+/* 11316 */ MCD_OPC_CheckField, 16, 5, 0, 100, 9, // Skip to: 13726
+/* 11322 */ MCD_OPC_Decode, 236, 10, 196, 1, // Opcode: RADDU_W_QB
+/* 11327 */ MCD_OPC_FilterValue, 22, 7, 0, // Skip to: 11338
+/* 11331 */ MCD_OPC_CheckPredicate, 12, 87, 9, // Skip to: 13726
+/* 11335 */ MCD_OPC_Decode, 38, 35, // Opcode: ADDQ_S_W
+/* 11338 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 11350
+/* 11342 */ MCD_OPC_CheckPredicate, 12, 76, 9, // Skip to: 13726
+/* 11346 */ MCD_OPC_Decode, 197, 12, 35, // Opcode: SUBQ_S_W
+/* 11350 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 11363
+/* 11354 */ MCD_OPC_CheckPredicate, 12, 64, 9, // Skip to: 13726
+/* 11358 */ MCD_OPC_Decode, 194, 9, 197, 1, // Opcode: MULEQ_S_W_PHL
+/* 11363 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 11376
+/* 11367 */ MCD_OPC_CheckPredicate, 12, 51, 9, // Skip to: 13726
+/* 11371 */ MCD_OPC_Decode, 195, 9, 197, 1, // Opcode: MULEQ_S_W_PHR
+/* 11376 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 11389
+/* 11380 */ MCD_OPC_CheckPredicate, 30, 38, 9, // Skip to: 13726
+/* 11384 */ MCD_OPC_Decode, 200, 9, 195, 1, // Opcode: MULQ_S_PH
+/* 11389 */ MCD_OPC_FilterValue, 31, 29, 9, // Skip to: 13726
+/* 11393 */ MCD_OPC_CheckPredicate, 12, 25, 9, // Skip to: 13726
+/* 11397 */ MCD_OPC_Decode, 198, 9, 195, 1, // Opcode: MULQ_RS_PH
+/* 11402 */ MCD_OPC_FilterValue, 17, 69, 1, // Skip to: 11731
+/* 11406 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 11409 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 11428
+/* 11413 */ MCD_OPC_CheckPredicate, 12, 5, 9, // Skip to: 13726
+/* 11417 */ MCD_OPC_CheckField, 11, 5, 0, 255, 8, // Skip to: 13726
+/* 11423 */ MCD_OPC_Decode, 161, 3, 198, 1, // Opcode: CMPU_EQ_QB
+/* 11428 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 11447
+/* 11432 */ MCD_OPC_CheckPredicate, 12, 242, 8, // Skip to: 13726
+/* 11436 */ MCD_OPC_CheckField, 11, 5, 0, 236, 8, // Skip to: 13726
+/* 11442 */ MCD_OPC_Decode, 163, 3, 198, 1, // Opcode: CMPU_LT_QB
+/* 11447 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 11466
+/* 11451 */ MCD_OPC_CheckPredicate, 12, 223, 8, // Skip to: 13726
+/* 11455 */ MCD_OPC_CheckField, 11, 5, 0, 217, 8, // Skip to: 13726
+/* 11461 */ MCD_OPC_Decode, 162, 3, 198, 1, // Opcode: CMPU_LE_QB
+/* 11466 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11479
+/* 11470 */ MCD_OPC_CheckPredicate, 12, 204, 8, // Skip to: 13726
+/* 11474 */ MCD_OPC_Decode, 162, 10, 195, 1, // Opcode: PICK_QB
+/* 11479 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11492
+/* 11483 */ MCD_OPC_CheckPredicate, 12, 191, 8, // Skip to: 13726
+/* 11487 */ MCD_OPC_Decode, 158, 3, 197, 1, // Opcode: CMPGU_EQ_QB
+/* 11492 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 11505
+/* 11496 */ MCD_OPC_CheckPredicate, 12, 178, 8, // Skip to: 13726
+/* 11500 */ MCD_OPC_Decode, 160, 3, 197, 1, // Opcode: CMPGU_LT_QB
+/* 11505 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 11518
+/* 11509 */ MCD_OPC_CheckPredicate, 12, 165, 8, // Skip to: 13726
+/* 11513 */ MCD_OPC_Decode, 159, 3, 197, 1, // Opcode: CMPGU_LE_QB
+/* 11518 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 11537
+/* 11522 */ MCD_OPC_CheckPredicate, 12, 152, 8, // Skip to: 13726
+/* 11526 */ MCD_OPC_CheckField, 11, 5, 0, 146, 8, // Skip to: 13726
+/* 11532 */ MCD_OPC_Decode, 165, 3, 198, 1, // Opcode: CMP_EQ_PH
+/* 11537 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 11556
+/* 11541 */ MCD_OPC_CheckPredicate, 12, 133, 8, // Skip to: 13726
+/* 11545 */ MCD_OPC_CheckField, 11, 5, 0, 127, 8, // Skip to: 13726
+/* 11551 */ MCD_OPC_Decode, 173, 3, 198, 1, // Opcode: CMP_LT_PH
+/* 11556 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 11575
+/* 11560 */ MCD_OPC_CheckPredicate, 12, 114, 8, // Skip to: 13726
+/* 11564 */ MCD_OPC_CheckField, 11, 5, 0, 108, 8, // Skip to: 13726
+/* 11570 */ MCD_OPC_Decode, 170, 3, 198, 1, // Opcode: CMP_LE_PH
+/* 11575 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 11588
+/* 11579 */ MCD_OPC_CheckPredicate, 12, 95, 8, // Skip to: 13726
+/* 11583 */ MCD_OPC_Decode, 161, 10, 195, 1, // Opcode: PICK_PH
+/* 11588 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 11601
+/* 11592 */ MCD_OPC_CheckPredicate, 12, 82, 8, // Skip to: 13726
+/* 11596 */ MCD_OPC_Decode, 176, 10, 195, 1, // Opcode: PRECRQ_QB_PH
+/* 11601 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 11614
+/* 11605 */ MCD_OPC_CheckPredicate, 30, 69, 8, // Skip to: 13726
+/* 11609 */ MCD_OPC_Decode, 178, 10, 195, 1, // Opcode: PRECR_QB_PH
+/* 11614 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 11627
+/* 11618 */ MCD_OPC_CheckPredicate, 12, 56, 8, // Skip to: 13726
+/* 11622 */ MCD_OPC_Decode, 146, 10, 195, 1, // Opcode: PACKRL_PH
+/* 11627 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 11640
+/* 11631 */ MCD_OPC_CheckPredicate, 12, 43, 8, // Skip to: 13726
+/* 11635 */ MCD_OPC_Decode, 174, 10, 195, 1, // Opcode: PRECRQU_S_QB_PH
+/* 11640 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 11653
+/* 11644 */ MCD_OPC_CheckPredicate, 12, 30, 8, // Skip to: 13726
+/* 11648 */ MCD_OPC_Decode, 175, 10, 199, 1, // Opcode: PRECRQ_PH_W
+/* 11653 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 11666
+/* 11657 */ MCD_OPC_CheckPredicate, 12, 17, 8, // Skip to: 13726
+/* 11661 */ MCD_OPC_Decode, 177, 10, 199, 1, // Opcode: PRECRQ_RS_PH_W
+/* 11666 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 11679
+/* 11670 */ MCD_OPC_CheckPredicate, 30, 4, 8, // Skip to: 13726
+/* 11674 */ MCD_OPC_Decode, 155, 3, 197, 1, // Opcode: CMPGDU_EQ_QB
+/* 11679 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 11692
+/* 11683 */ MCD_OPC_CheckPredicate, 30, 247, 7, // Skip to: 13726
+/* 11687 */ MCD_OPC_Decode, 157, 3, 197, 1, // Opcode: CMPGDU_LT_QB
+/* 11692 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 11705
+/* 11696 */ MCD_OPC_CheckPredicate, 30, 234, 7, // Skip to: 13726
+/* 11700 */ MCD_OPC_Decode, 156, 3, 197, 1, // Opcode: CMPGDU_LE_QB
+/* 11705 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 11718
+/* 11709 */ MCD_OPC_CheckPredicate, 30, 221, 7, // Skip to: 13726
+/* 11713 */ MCD_OPC_Decode, 179, 10, 200, 1, // Opcode: PRECR_SRA_PH_W
+/* 11718 */ MCD_OPC_FilterValue, 31, 212, 7, // Skip to: 13726
+/* 11722 */ MCD_OPC_CheckPredicate, 30, 208, 7, // Skip to: 13726
+/* 11726 */ MCD_OPC_Decode, 180, 10, 200, 1, // Opcode: PRECR_SRA_R_PH_W
+/* 11731 */ MCD_OPC_FilterValue, 18, 74, 1, // Skip to: 12065
+/* 11735 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 11738 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 11756
+/* 11742 */ MCD_OPC_CheckPredicate, 30, 188, 7, // Skip to: 13726
+/* 11746 */ MCD_OPC_CheckField, 21, 5, 0, 182, 7, // Skip to: 13726
+/* 11752 */ MCD_OPC_Decode, 23, 201, 1, // Opcode: ABSQ_S_QB
+/* 11756 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11769
+/* 11760 */ MCD_OPC_CheckPredicate, 12, 170, 7, // Skip to: 13726
+/* 11764 */ MCD_OPC_Decode, 244, 10, 202, 1, // Opcode: REPL_QB
+/* 11769 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 11788
+/* 11773 */ MCD_OPC_CheckPredicate, 12, 157, 7, // Skip to: 13726
+/* 11777 */ MCD_OPC_CheckField, 21, 5, 0, 151, 7, // Skip to: 13726
+/* 11783 */ MCD_OPC_Decode, 242, 10, 203, 1, // Opcode: REPLV_QB
+/* 11788 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 11807
+/* 11792 */ MCD_OPC_CheckPredicate, 12, 138, 7, // Skip to: 13726
+/* 11796 */ MCD_OPC_CheckField, 21, 5, 0, 132, 7, // Skip to: 13726
+/* 11802 */ MCD_OPC_Decode, 164, 10, 201, 1, // Opcode: PRECEQU_PH_QBL
+/* 11807 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 11826
+/* 11811 */ MCD_OPC_CheckPredicate, 12, 119, 7, // Skip to: 13726
+/* 11815 */ MCD_OPC_CheckField, 21, 5, 0, 113, 7, // Skip to: 13726
+/* 11821 */ MCD_OPC_Decode, 166, 10, 201, 1, // Opcode: PRECEQU_PH_QBR
+/* 11826 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 11845
+/* 11830 */ MCD_OPC_CheckPredicate, 12, 100, 7, // Skip to: 13726
+/* 11834 */ MCD_OPC_CheckField, 21, 5, 0, 94, 7, // Skip to: 13726
+/* 11840 */ MCD_OPC_Decode, 165, 10, 201, 1, // Opcode: PRECEQU_PH_QBLA
+/* 11845 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 11864
+/* 11849 */ MCD_OPC_CheckPredicate, 12, 81, 7, // Skip to: 13726
+/* 11853 */ MCD_OPC_CheckField, 21, 5, 0, 75, 7, // Skip to: 13726
+/* 11859 */ MCD_OPC_Decode, 167, 10, 201, 1, // Opcode: PRECEQU_PH_QBRA
+/* 11864 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 11882
+/* 11868 */ MCD_OPC_CheckPredicate, 12, 62, 7, // Skip to: 13726
+/* 11872 */ MCD_OPC_CheckField, 21, 5, 0, 56, 7, // Skip to: 13726
+/* 11878 */ MCD_OPC_Decode, 22, 201, 1, // Opcode: ABSQ_S_PH
+/* 11882 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 11895
+/* 11886 */ MCD_OPC_CheckPredicate, 12, 44, 7, // Skip to: 13726
+/* 11890 */ MCD_OPC_Decode, 243, 10, 202, 1, // Opcode: REPL_PH
+/* 11895 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 11914
+/* 11899 */ MCD_OPC_CheckPredicate, 12, 31, 7, // Skip to: 13726
+/* 11903 */ MCD_OPC_CheckField, 21, 5, 0, 25, 7, // Skip to: 13726
+/* 11909 */ MCD_OPC_Decode, 241, 10, 203, 1, // Opcode: REPLV_PH
+/* 11914 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 11933
+/* 11918 */ MCD_OPC_CheckPredicate, 12, 12, 7, // Skip to: 13726
+/* 11922 */ MCD_OPC_CheckField, 21, 5, 0, 6, 7, // Skip to: 13726
+/* 11928 */ MCD_OPC_Decode, 168, 10, 204, 1, // Opcode: PRECEQ_W_PHL
+/* 11933 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 11952
+/* 11937 */ MCD_OPC_CheckPredicate, 12, 249, 6, // Skip to: 13726
+/* 11941 */ MCD_OPC_CheckField, 21, 5, 0, 243, 6, // Skip to: 13726
+/* 11947 */ MCD_OPC_Decode, 169, 10, 204, 1, // Opcode: PRECEQ_W_PHR
+/* 11952 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 11970
+/* 11956 */ MCD_OPC_CheckPredicate, 12, 230, 6, // Skip to: 13726
+/* 11960 */ MCD_OPC_CheckField, 21, 5, 0, 224, 6, // Skip to: 13726
+/* 11966 */ MCD_OPC_Decode, 24, 205, 1, // Opcode: ABSQ_S_W
+/* 11970 */ MCD_OPC_FilterValue, 27, 15, 0, // Skip to: 11989
+/* 11974 */ MCD_OPC_CheckPredicate, 12, 212, 6, // Skip to: 13726
+/* 11978 */ MCD_OPC_CheckField, 21, 5, 0, 206, 6, // Skip to: 13726
+/* 11984 */ MCD_OPC_Decode, 249, 1, 205, 1, // Opcode: BITREV
+/* 11989 */ MCD_OPC_FilterValue, 28, 15, 0, // Skip to: 12008
+/* 11993 */ MCD_OPC_CheckPredicate, 12, 193, 6, // Skip to: 13726
+/* 11997 */ MCD_OPC_CheckField, 21, 5, 0, 187, 6, // Skip to: 13726
+/* 12003 */ MCD_OPC_Decode, 170, 10, 201, 1, // Opcode: PRECEU_PH_QBL
+/* 12008 */ MCD_OPC_FilterValue, 29, 15, 0, // Skip to: 12027
+/* 12012 */ MCD_OPC_CheckPredicate, 12, 174, 6, // Skip to: 13726
+/* 12016 */ MCD_OPC_CheckField, 21, 5, 0, 168, 6, // Skip to: 13726
+/* 12022 */ MCD_OPC_Decode, 172, 10, 201, 1, // Opcode: PRECEU_PH_QBR
+/* 12027 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 12046
+/* 12031 */ MCD_OPC_CheckPredicate, 12, 155, 6, // Skip to: 13726
+/* 12035 */ MCD_OPC_CheckField, 21, 5, 0, 149, 6, // Skip to: 13726
+/* 12041 */ MCD_OPC_Decode, 171, 10, 201, 1, // Opcode: PRECEU_PH_QBLA
+/* 12046 */ MCD_OPC_FilterValue, 31, 140, 6, // Skip to: 13726
+/* 12050 */ MCD_OPC_CheckPredicate, 12, 136, 6, // Skip to: 13726
+/* 12054 */ MCD_OPC_CheckField, 21, 5, 0, 130, 6, // Skip to: 13726
+/* 12060 */ MCD_OPC_Decode, 173, 10, 201, 1, // Opcode: PRECEU_PH_QBRA
+/* 12065 */ MCD_OPC_FilterValue, 19, 31, 1, // Skip to: 12356
+/* 12069 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 12072 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12085
+/* 12076 */ MCD_OPC_CheckPredicate, 12, 110, 6, // Skip to: 13726
+/* 12080 */ MCD_OPC_Decode, 199, 11, 206, 1, // Opcode: SHLL_QB
+/* 12085 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12098
+/* 12089 */ MCD_OPC_CheckPredicate, 12, 97, 6, // Skip to: 13726
+/* 12093 */ MCD_OPC_Decode, 215, 11, 206, 1, // Opcode: SHRL_QB
+/* 12098 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12111
+/* 12102 */ MCD_OPC_CheckPredicate, 12, 84, 6, // Skip to: 13726
+/* 12106 */ MCD_OPC_Decode, 195, 11, 207, 1, // Opcode: SHLLV_QB
+/* 12111 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12124
+/* 12115 */ MCD_OPC_CheckPredicate, 12, 71, 6, // Skip to: 13726
+/* 12119 */ MCD_OPC_Decode, 213, 11, 207, 1, // Opcode: SHRLV_QB
+/* 12124 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 12137
+/* 12128 */ MCD_OPC_CheckPredicate, 30, 58, 6, // Skip to: 13726
+/* 12132 */ MCD_OPC_Decode, 208, 11, 206, 1, // Opcode: SHRA_QB
+/* 12137 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 12150
+/* 12141 */ MCD_OPC_CheckPredicate, 30, 45, 6, // Skip to: 13726
+/* 12145 */ MCD_OPC_Decode, 210, 11, 206, 1, // Opcode: SHRA_R_QB
+/* 12150 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 12163
+/* 12154 */ MCD_OPC_CheckPredicate, 30, 32, 6, // Skip to: 13726
+/* 12158 */ MCD_OPC_Decode, 203, 11, 207, 1, // Opcode: SHRAV_QB
+/* 12163 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 12176
+/* 12167 */ MCD_OPC_CheckPredicate, 30, 19, 6, // Skip to: 13726
+/* 12171 */ MCD_OPC_Decode, 205, 11, 207, 1, // Opcode: SHRAV_R_QB
+/* 12176 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 12189
+/* 12180 */ MCD_OPC_CheckPredicate, 12, 6, 6, // Skip to: 13726
+/* 12184 */ MCD_OPC_Decode, 198, 11, 206, 1, // Opcode: SHLL_PH
+/* 12189 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 12202
+/* 12193 */ MCD_OPC_CheckPredicate, 12, 249, 5, // Skip to: 13726
+/* 12197 */ MCD_OPC_Decode, 207, 11, 206, 1, // Opcode: SHRA_PH
+/* 12202 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 12215
+/* 12206 */ MCD_OPC_CheckPredicate, 12, 236, 5, // Skip to: 13726
+/* 12210 */ MCD_OPC_Decode, 194, 11, 207, 1, // Opcode: SHLLV_PH
+/* 12215 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 12228
+/* 12219 */ MCD_OPC_CheckPredicate, 12, 223, 5, // Skip to: 13726
+/* 12223 */ MCD_OPC_Decode, 202, 11, 207, 1, // Opcode: SHRAV_PH
+/* 12228 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 12241
+/* 12232 */ MCD_OPC_CheckPredicate, 12, 210, 5, // Skip to: 13726
+/* 12236 */ MCD_OPC_Decode, 200, 11, 206, 1, // Opcode: SHLL_S_PH
+/* 12241 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 12254
+/* 12245 */ MCD_OPC_CheckPredicate, 12, 197, 5, // Skip to: 13726
+/* 12249 */ MCD_OPC_Decode, 209, 11, 206, 1, // Opcode: SHRA_R_PH
+/* 12254 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 12267
+/* 12258 */ MCD_OPC_CheckPredicate, 12, 184, 5, // Skip to: 13726
+/* 12262 */ MCD_OPC_Decode, 196, 11, 207, 1, // Opcode: SHLLV_S_PH
+/* 12267 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 12280
+/* 12271 */ MCD_OPC_CheckPredicate, 12, 171, 5, // Skip to: 13726
+/* 12275 */ MCD_OPC_Decode, 204, 11, 207, 1, // Opcode: SHRAV_R_PH
+/* 12280 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 12293
+/* 12284 */ MCD_OPC_CheckPredicate, 12, 158, 5, // Skip to: 13726
+/* 12288 */ MCD_OPC_Decode, 201, 11, 208, 1, // Opcode: SHLL_S_W
+/* 12293 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 12306
+/* 12297 */ MCD_OPC_CheckPredicate, 12, 145, 5, // Skip to: 13726
+/* 12301 */ MCD_OPC_Decode, 211, 11, 208, 1, // Opcode: SHRA_R_W
+/* 12306 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 12318
+/* 12310 */ MCD_OPC_CheckPredicate, 12, 132, 5, // Skip to: 13726
+/* 12314 */ MCD_OPC_Decode, 197, 11, 36, // Opcode: SHLLV_S_W
+/* 12318 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 12330
+/* 12322 */ MCD_OPC_CheckPredicate, 12, 120, 5, // Skip to: 13726
+/* 12326 */ MCD_OPC_Decode, 206, 11, 36, // Opcode: SHRAV_R_W
+/* 12330 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 12343
+/* 12334 */ MCD_OPC_CheckPredicate, 30, 108, 5, // Skip to: 13726
+/* 12338 */ MCD_OPC_Decode, 214, 11, 206, 1, // Opcode: SHRL_PH
+/* 12343 */ MCD_OPC_FilterValue, 27, 99, 5, // Skip to: 13726
+/* 12347 */ MCD_OPC_CheckPredicate, 30, 95, 5, // Skip to: 13726
+/* 12351 */ MCD_OPC_Decode, 212, 11, 207, 1, // Opcode: SHRLV_PH
+/* 12356 */ MCD_OPC_FilterValue, 24, 199, 0, // Skip to: 12559
+/* 12360 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 12363 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 12375
+/* 12367 */ MCD_OPC_CheckPredicate, 30, 75, 5, // Skip to: 13726
+/* 12371 */ MCD_OPC_Decode, 53, 195, 1, // Opcode: ADDUH_QB
+/* 12375 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12388
+/* 12379 */ MCD_OPC_CheckPredicate, 30, 63, 5, // Skip to: 13726
+/* 12383 */ MCD_OPC_Decode, 215, 12, 195, 1, // Opcode: SUBUH_QB
+/* 12388 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 12400
+/* 12392 */ MCD_OPC_CheckPredicate, 30, 50, 5, // Skip to: 13726
+/* 12396 */ MCD_OPC_Decode, 54, 195, 1, // Opcode: ADDUH_R_QB
+/* 12400 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12413
+/* 12404 */ MCD_OPC_CheckPredicate, 30, 38, 5, // Skip to: 13726
+/* 12408 */ MCD_OPC_Decode, 216, 12, 195, 1, // Opcode: SUBUH_R_QB
+/* 12413 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 12425
+/* 12417 */ MCD_OPC_CheckPredicate, 30, 25, 5, // Skip to: 13726
+/* 12421 */ MCD_OPC_Decode, 32, 195, 1, // Opcode: ADDQH_PH
+/* 12425 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 12438
+/* 12429 */ MCD_OPC_CheckPredicate, 30, 13, 5, // Skip to: 13726
+/* 12433 */ MCD_OPC_Decode, 191, 12, 195, 1, // Opcode: SUBQH_PH
+/* 12438 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 12450
+/* 12442 */ MCD_OPC_CheckPredicate, 30, 0, 5, // Skip to: 13726
+/* 12446 */ MCD_OPC_Decode, 33, 195, 1, // Opcode: ADDQH_R_PH
+/* 12450 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 12463
+/* 12454 */ MCD_OPC_CheckPredicate, 30, 244, 4, // Skip to: 13726
+/* 12458 */ MCD_OPC_Decode, 192, 12, 195, 1, // Opcode: SUBQH_R_PH
+/* 12463 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 12476
+/* 12467 */ MCD_OPC_CheckPredicate, 30, 231, 4, // Skip to: 13726
+/* 12471 */ MCD_OPC_Decode, 218, 9, 195, 1, // Opcode: MUL_PH
+/* 12476 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 12489
+/* 12480 */ MCD_OPC_CheckPredicate, 30, 218, 4, // Skip to: 13726
+/* 12484 */ MCD_OPC_Decode, 222, 9, 195, 1, // Opcode: MUL_S_PH
+/* 12489 */ MCD_OPC_FilterValue, 16, 7, 0, // Skip to: 12500
+/* 12493 */ MCD_OPC_CheckPredicate, 30, 205, 4, // Skip to: 13726
+/* 12497 */ MCD_OPC_Decode, 35, 35, // Opcode: ADDQH_W
+/* 12500 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 12512
+/* 12504 */ MCD_OPC_CheckPredicate, 30, 194, 4, // Skip to: 13726
+/* 12508 */ MCD_OPC_Decode, 194, 12, 35, // Opcode: SUBQH_W
+/* 12512 */ MCD_OPC_FilterValue, 18, 7, 0, // Skip to: 12523
+/* 12516 */ MCD_OPC_CheckPredicate, 30, 182, 4, // Skip to: 13726
+/* 12520 */ MCD_OPC_Decode, 34, 35, // Opcode: ADDQH_R_W
+/* 12523 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 12535
+/* 12527 */ MCD_OPC_CheckPredicate, 30, 171, 4, // Skip to: 13726
+/* 12531 */ MCD_OPC_Decode, 193, 12, 35, // Opcode: SUBQH_R_W
+/* 12535 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 12547
+/* 12539 */ MCD_OPC_CheckPredicate, 30, 159, 4, // Skip to: 13726
+/* 12543 */ MCD_OPC_Decode, 201, 9, 35, // Opcode: MULQ_S_W
+/* 12547 */ MCD_OPC_FilterValue, 23, 151, 4, // Skip to: 13726
+/* 12551 */ MCD_OPC_CheckPredicate, 30, 147, 4, // Skip to: 13726
+/* 12555 */ MCD_OPC_Decode, 199, 9, 35, // Opcode: MULQ_RS_W
+/* 12559 */ MCD_OPC_FilterValue, 32, 60, 0, // Skip to: 12623
+/* 12563 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 12566 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 12585
+/* 12570 */ MCD_OPC_CheckPredicate, 6, 128, 4, // Skip to: 13726
+/* 12574 */ MCD_OPC_CheckField, 21, 5, 0, 122, 4, // Skip to: 13726
+/* 12580 */ MCD_OPC_Decode, 234, 13, 205, 1, // Opcode: WSBH
+/* 12585 */ MCD_OPC_FilterValue, 16, 15, 0, // Skip to: 12604
+/* 12589 */ MCD_OPC_CheckPredicate, 6, 109, 4, // Skip to: 13726
+/* 12593 */ MCD_OPC_CheckField, 21, 5, 0, 103, 4, // Skip to: 13726
+/* 12599 */ MCD_OPC_Decode, 168, 11, 205, 1, // Opcode: SEB
+/* 12604 */ MCD_OPC_FilterValue, 24, 94, 4, // Skip to: 13726
+/* 12608 */ MCD_OPC_CheckPredicate, 6, 90, 4, // Skip to: 13726
+/* 12612 */ MCD_OPC_CheckField, 21, 5, 0, 84, 4, // Skip to: 13726
+/* 12618 */ MCD_OPC_Decode, 171, 11, 205, 1, // Opcode: SEH
+/* 12623 */ MCD_OPC_FilterValue, 48, 143, 1, // Skip to: 13026
+/* 12627 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 12630 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12648
+/* 12634 */ MCD_OPC_CheckPredicate, 30, 64, 4, // Skip to: 13726
+/* 12638 */ MCD_OPC_CheckField, 13, 3, 0, 58, 4, // Skip to: 13726
+/* 12644 */ MCD_OPC_Decode, 230, 4, 116, // Opcode: DPA_W_PH
+/* 12648 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12666
+/* 12652 */ MCD_OPC_CheckPredicate, 30, 46, 4, // Skip to: 13726
+/* 12656 */ MCD_OPC_CheckField, 13, 3, 0, 40, 4, // Skip to: 13726
+/* 12662 */ MCD_OPC_Decode, 245, 4, 116, // Opcode: DPS_W_PH
+/* 12666 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 12684
+/* 12670 */ MCD_OPC_CheckPredicate, 30, 28, 4, // Skip to: 13726
+/* 12674 */ MCD_OPC_CheckField, 13, 3, 0, 22, 4, // Skip to: 13726
+/* 12680 */ MCD_OPC_Decode, 205, 9, 116, // Opcode: MULSA_W_PH
+/* 12684 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 12702
+/* 12688 */ MCD_OPC_CheckPredicate, 12, 10, 4, // Skip to: 13726
+/* 12692 */ MCD_OPC_CheckField, 13, 3, 0, 4, 4, // Skip to: 13726
+/* 12698 */ MCD_OPC_Decode, 227, 4, 116, // Opcode: DPAU_H_QBL
+/* 12702 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 12720
+/* 12706 */ MCD_OPC_CheckPredicate, 12, 248, 3, // Skip to: 13726
+/* 12710 */ MCD_OPC_CheckField, 13, 3, 0, 242, 3, // Skip to: 13726
+/* 12716 */ MCD_OPC_Decode, 226, 4, 116, // Opcode: DPAQ_S_W_PH
+/* 12720 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 12738
+/* 12724 */ MCD_OPC_CheckPredicate, 12, 230, 3, // Skip to: 13726
+/* 12728 */ MCD_OPC_CheckField, 13, 3, 0, 224, 3, // Skip to: 13726
+/* 12734 */ MCD_OPC_Decode, 235, 4, 116, // Opcode: DPSQ_S_W_PH
+/* 12738 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 12756
+/* 12742 */ MCD_OPC_CheckPredicate, 12, 212, 3, // Skip to: 13726
+/* 12746 */ MCD_OPC_CheckField, 13, 3, 0, 206, 3, // Skip to: 13726
+/* 12752 */ MCD_OPC_Decode, 204, 9, 116, // Opcode: MULSAQ_S_W_PH
+/* 12756 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 12774
+/* 12760 */ MCD_OPC_CheckPredicate, 12, 194, 3, // Skip to: 13726
+/* 12764 */ MCD_OPC_CheckField, 13, 3, 0, 188, 3, // Skip to: 13726
+/* 12770 */ MCD_OPC_Decode, 228, 4, 116, // Opcode: DPAU_H_QBR
+/* 12774 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 12792
+/* 12778 */ MCD_OPC_CheckPredicate, 30, 176, 3, // Skip to: 13726
+/* 12782 */ MCD_OPC_CheckField, 13, 3, 0, 170, 3, // Skip to: 13726
+/* 12788 */ MCD_OPC_Decode, 229, 4, 116, // Opcode: DPAX_W_PH
+/* 12792 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 12810
+/* 12796 */ MCD_OPC_CheckPredicate, 30, 158, 3, // Skip to: 13726
+/* 12800 */ MCD_OPC_CheckField, 13, 3, 0, 152, 3, // Skip to: 13726
+/* 12806 */ MCD_OPC_Decode, 244, 4, 116, // Opcode: DPSX_W_PH
+/* 12810 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 12828
+/* 12814 */ MCD_OPC_CheckPredicate, 12, 140, 3, // Skip to: 13726
+/* 12818 */ MCD_OPC_CheckField, 13, 3, 0, 134, 3, // Skip to: 13726
+/* 12824 */ MCD_OPC_Decode, 242, 4, 116, // Opcode: DPSU_H_QBL
+/* 12828 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 12846
+/* 12832 */ MCD_OPC_CheckPredicate, 12, 122, 3, // Skip to: 13726
+/* 12836 */ MCD_OPC_CheckField, 13, 3, 0, 116, 3, // Skip to: 13726
+/* 12842 */ MCD_OPC_Decode, 225, 4, 116, // Opcode: DPAQ_SA_L_W
+/* 12846 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 12864
+/* 12850 */ MCD_OPC_CheckPredicate, 12, 104, 3, // Skip to: 13726
+/* 12854 */ MCD_OPC_CheckField, 13, 3, 0, 98, 3, // Skip to: 13726
+/* 12860 */ MCD_OPC_Decode, 234, 4, 116, // Opcode: DPSQ_SA_L_W
+/* 12864 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 12882
+/* 12868 */ MCD_OPC_CheckPredicate, 12, 86, 3, // Skip to: 13726
+/* 12872 */ MCD_OPC_CheckField, 13, 3, 0, 80, 3, // Skip to: 13726
+/* 12878 */ MCD_OPC_Decode, 243, 4, 116, // Opcode: DPSU_H_QBR
+/* 12882 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 12900
+/* 12886 */ MCD_OPC_CheckPredicate, 12, 68, 3, // Skip to: 13726
+/* 12890 */ MCD_OPC_CheckField, 13, 3, 0, 62, 3, // Skip to: 13726
+/* 12896 */ MCD_OPC_Decode, 151, 8, 116, // Opcode: MAQ_SA_W_PHL
+/* 12900 */ MCD_OPC_FilterValue, 18, 14, 0, // Skip to: 12918
+/* 12904 */ MCD_OPC_CheckPredicate, 12, 50, 3, // Skip to: 13726
+/* 12908 */ MCD_OPC_CheckField, 13, 3, 0, 44, 3, // Skip to: 13726
+/* 12914 */ MCD_OPC_Decode, 152, 8, 116, // Opcode: MAQ_SA_W_PHR
+/* 12918 */ MCD_OPC_FilterValue, 20, 14, 0, // Skip to: 12936
+/* 12922 */ MCD_OPC_CheckPredicate, 12, 32, 3, // Skip to: 13726
+/* 12926 */ MCD_OPC_CheckField, 13, 3, 0, 26, 3, // Skip to: 13726
+/* 12932 */ MCD_OPC_Decode, 153, 8, 116, // Opcode: MAQ_S_W_PHL
+/* 12936 */ MCD_OPC_FilterValue, 22, 14, 0, // Skip to: 12954
+/* 12940 */ MCD_OPC_CheckPredicate, 12, 14, 3, // Skip to: 13726
+/* 12944 */ MCD_OPC_CheckField, 13, 3, 0, 8, 3, // Skip to: 13726
+/* 12950 */ MCD_OPC_Decode, 154, 8, 116, // Opcode: MAQ_S_W_PHR
+/* 12954 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 12972
+/* 12958 */ MCD_OPC_CheckPredicate, 30, 252, 2, // Skip to: 13726
+/* 12962 */ MCD_OPC_CheckField, 13, 3, 0, 246, 2, // Skip to: 13726
+/* 12968 */ MCD_OPC_Decode, 224, 4, 116, // Opcode: DPAQX_S_W_PH
+/* 12972 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 12990
+/* 12976 */ MCD_OPC_CheckPredicate, 30, 234, 2, // Skip to: 13726
+/* 12980 */ MCD_OPC_CheckField, 13, 3, 0, 228, 2, // Skip to: 13726
+/* 12986 */ MCD_OPC_Decode, 233, 4, 116, // Opcode: DPSQX_S_W_PH
+/* 12990 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 13008
+/* 12994 */ MCD_OPC_CheckPredicate, 30, 216, 2, // Skip to: 13726
+/* 12998 */ MCD_OPC_CheckField, 13, 3, 0, 210, 2, // Skip to: 13726
+/* 13004 */ MCD_OPC_Decode, 223, 4, 116, // Opcode: DPAQX_SA_W_PH
+/* 13008 */ MCD_OPC_FilterValue, 27, 202, 2, // Skip to: 13726
+/* 13012 */ MCD_OPC_CheckPredicate, 30, 198, 2, // Skip to: 13726
+/* 13016 */ MCD_OPC_CheckField, 13, 3, 0, 192, 2, // Skip to: 13726
+/* 13022 */ MCD_OPC_Decode, 232, 4, 116, // Opcode: DPSQX_SA_W_PH
+/* 13026 */ MCD_OPC_FilterValue, 49, 41, 0, // Skip to: 13071
+/* 13030 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 13033 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 13045
+/* 13037 */ MCD_OPC_CheckPredicate, 30, 173, 2, // Skip to: 13726
+/* 13041 */ MCD_OPC_Decode, 96, 209, 1, // Opcode: APPEND
+/* 13045 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13058
+/* 13049 */ MCD_OPC_CheckPredicate, 30, 161, 2, // Skip to: 13726
+/* 13053 */ MCD_OPC_Decode, 184, 10, 209, 1, // Opcode: PREPEND
+/* 13058 */ MCD_OPC_FilterValue, 16, 152, 2, // Skip to: 13726
+/* 13062 */ MCD_OPC_CheckPredicate, 30, 148, 2, // Skip to: 13726
+/* 13066 */ MCD_OPC_Decode, 169, 1, 209, 1, // Opcode: BALIGN
+/* 13071 */ MCD_OPC_FilterValue, 56, 58, 1, // Skip to: 13389
+/* 13075 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 13078 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 13097
+/* 13082 */ MCD_OPC_CheckPredicate, 12, 128, 2, // Skip to: 13726
+/* 13086 */ MCD_OPC_CheckField, 13, 3, 0, 122, 2, // Skip to: 13726
+/* 13092 */ MCD_OPC_Decode, 157, 5, 210, 1, // Opcode: EXTR_W
+/* 13097 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 13116
+/* 13101 */ MCD_OPC_CheckPredicate, 12, 109, 2, // Skip to: 13726
+/* 13105 */ MCD_OPC_CheckField, 13, 3, 0, 103, 2, // Skip to: 13726
+/* 13111 */ MCD_OPC_Decode, 153, 5, 211, 1, // Opcode: EXTRV_W
+/* 13116 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 13135
+/* 13120 */ MCD_OPC_CheckPredicate, 12, 90, 2, // Skip to: 13726
+/* 13124 */ MCD_OPC_CheckField, 13, 3, 0, 84, 2, // Skip to: 13726
+/* 13130 */ MCD_OPC_Decode, 146, 5, 210, 1, // Opcode: EXTP
+/* 13135 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 13154
+/* 13139 */ MCD_OPC_CheckPredicate, 12, 71, 2, // Skip to: 13726
+/* 13143 */ MCD_OPC_CheckField, 13, 3, 0, 65, 2, // Skip to: 13726
+/* 13149 */ MCD_OPC_Decode, 149, 5, 211, 1, // Opcode: EXTPV
+/* 13154 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 13173
+/* 13158 */ MCD_OPC_CheckPredicate, 12, 52, 2, // Skip to: 13726
+/* 13162 */ MCD_OPC_CheckField, 13, 3, 0, 46, 2, // Skip to: 13726
+/* 13168 */ MCD_OPC_Decode, 155, 5, 210, 1, // Opcode: EXTR_R_W
+/* 13173 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 13192
+/* 13177 */ MCD_OPC_CheckPredicate, 12, 33, 2, // Skip to: 13726
+/* 13181 */ MCD_OPC_CheckField, 13, 3, 0, 27, 2, // Skip to: 13726
+/* 13187 */ MCD_OPC_Decode, 151, 5, 211, 1, // Opcode: EXTRV_R_W
+/* 13192 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 13211
+/* 13196 */ MCD_OPC_CheckPredicate, 12, 14, 2, // Skip to: 13726
+/* 13200 */ MCD_OPC_CheckField, 13, 3, 0, 8, 2, // Skip to: 13726
+/* 13206 */ MCD_OPC_Decode, 154, 5, 210, 1, // Opcode: EXTR_RS_W
+/* 13211 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 13230
+/* 13215 */ MCD_OPC_CheckPredicate, 12, 251, 1, // Skip to: 13726
+/* 13219 */ MCD_OPC_CheckField, 13, 3, 0, 245, 1, // Skip to: 13726
+/* 13225 */ MCD_OPC_Decode, 150, 5, 211, 1, // Opcode: EXTRV_RS_W
+/* 13230 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 13249
+/* 13234 */ MCD_OPC_CheckPredicate, 12, 232, 1, // Skip to: 13726
+/* 13238 */ MCD_OPC_CheckField, 13, 3, 0, 226, 1, // Skip to: 13726
+/* 13244 */ MCD_OPC_Decode, 147, 5, 210, 1, // Opcode: EXTPDP
+/* 13249 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 13268
+/* 13253 */ MCD_OPC_CheckPredicate, 12, 213, 1, // Skip to: 13726
+/* 13257 */ MCD_OPC_CheckField, 13, 3, 0, 207, 1, // Skip to: 13726
+/* 13263 */ MCD_OPC_Decode, 148, 5, 211, 1, // Opcode: EXTPDPV
+/* 13268 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 13287
+/* 13272 */ MCD_OPC_CheckPredicate, 12, 194, 1, // Skip to: 13726
+/* 13276 */ MCD_OPC_CheckField, 13, 3, 0, 188, 1, // Skip to: 13726
+/* 13282 */ MCD_OPC_Decode, 156, 5, 210, 1, // Opcode: EXTR_S_H
+/* 13287 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 13306
+/* 13291 */ MCD_OPC_CheckPredicate, 12, 175, 1, // Skip to: 13726
+/* 13295 */ MCD_OPC_CheckField, 13, 3, 0, 169, 1, // Skip to: 13726
+/* 13301 */ MCD_OPC_Decode, 152, 5, 211, 1, // Opcode: EXTRV_S_H
+/* 13306 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 13319
+/* 13310 */ MCD_OPC_CheckPredicate, 12, 156, 1, // Skip to: 13726
+/* 13314 */ MCD_OPC_Decode, 237, 10, 212, 1, // Opcode: RDDSP
+/* 13319 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 13332
+/* 13323 */ MCD_OPC_CheckPredicate, 12, 143, 1, // Skip to: 13726
+/* 13327 */ MCD_OPC_Decode, 233, 13, 213, 1, // Opcode: WRDSP
+/* 13332 */ MCD_OPC_FilterValue, 26, 15, 0, // Skip to: 13351
+/* 13336 */ MCD_OPC_CheckPredicate, 12, 130, 1, // Skip to: 13726
+/* 13340 */ MCD_OPC_CheckField, 13, 7, 0, 124, 1, // Skip to: 13726
+/* 13346 */ MCD_OPC_Decode, 192, 11, 214, 1, // Opcode: SHILO
+/* 13351 */ MCD_OPC_FilterValue, 27, 15, 0, // Skip to: 13370
+/* 13355 */ MCD_OPC_CheckPredicate, 12, 111, 1, // Skip to: 13726
+/* 13359 */ MCD_OPC_CheckField, 13, 8, 0, 105, 1, // Skip to: 13726
+/* 13365 */ MCD_OPC_Decode, 193, 11, 215, 1, // Opcode: SHILOV
+/* 13370 */ MCD_OPC_FilterValue, 31, 96, 1, // Skip to: 13726
+/* 13374 */ MCD_OPC_CheckPredicate, 12, 92, 1, // Skip to: 13726
+/* 13378 */ MCD_OPC_CheckField, 13, 8, 0, 86, 1, // Skip to: 13726
+/* 13384 */ MCD_OPC_Decode, 180, 9, 215, 1, // Opcode: MTHLIP
+/* 13389 */ MCD_OPC_FilterValue, 59, 77, 1, // Skip to: 13726
+/* 13393 */ MCD_OPC_CheckPredicate, 5, 73, 1, // Skip to: 13726
+/* 13397 */ MCD_OPC_CheckField, 21, 5, 0, 67, 1, // Skip to: 13726
+/* 13403 */ MCD_OPC_CheckField, 6, 5, 0, 61, 1, // Skip to: 13726
+/* 13409 */ MCD_OPC_Decode, 238, 10, 216, 1, // Opcode: RDHWR
+/* 13414 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 13427
+/* 13418 */ MCD_OPC_CheckPredicate, 5, 48, 1, // Skip to: 13726
+/* 13422 */ MCD_OPC_Decode, 153, 7, 217, 1, // Opcode: LB
+/* 13427 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 13440
+/* 13431 */ MCD_OPC_CheckPredicate, 5, 35, 1, // Skip to: 13726
+/* 13435 */ MCD_OPC_Decode, 184, 7, 217, 1, // Opcode: LH
+/* 13440 */ MCD_OPC_FilterValue, 34, 9, 0, // Skip to: 13453
+/* 13444 */ MCD_OPC_CheckPredicate, 11, 22, 1, // Skip to: 13726
+/* 13448 */ MCD_OPC_Decode, 222, 7, 217, 1, // Opcode: LWL
+/* 13453 */ MCD_OPC_FilterValue, 35, 9, 0, // Skip to: 13466
+/* 13457 */ MCD_OPC_CheckPredicate, 1, 9, 1, // Skip to: 13726
+/* 13461 */ MCD_OPC_Decode, 213, 7, 217, 1, // Opcode: LW
+/* 13466 */ MCD_OPC_FilterValue, 36, 9, 0, // Skip to: 13479
+/* 13470 */ MCD_OPC_CheckPredicate, 5, 252, 0, // Skip to: 13726
+/* 13474 */ MCD_OPC_Decode, 158, 7, 217, 1, // Opcode: LBu
+/* 13479 */ MCD_OPC_FilterValue, 37, 9, 0, // Skip to: 13492
+/* 13483 */ MCD_OPC_CheckPredicate, 5, 239, 0, // Skip to: 13726
+/* 13487 */ MCD_OPC_Decode, 189, 7, 217, 1, // Opcode: LHu
+/* 13492 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 13505
+/* 13496 */ MCD_OPC_CheckPredicate, 11, 226, 0, // Skip to: 13726
+/* 13500 */ MCD_OPC_Decode, 230, 7, 217, 1, // Opcode: LWR
+/* 13505 */ MCD_OPC_FilterValue, 40, 9, 0, // Skip to: 13518
+/* 13509 */ MCD_OPC_CheckPredicate, 5, 213, 0, // Skip to: 13726
+/* 13513 */ MCD_OPC_Decode, 142, 11, 217, 1, // Opcode: SB
+/* 13518 */ MCD_OPC_FilterValue, 41, 9, 0, // Skip to: 13531
+/* 13522 */ MCD_OPC_CheckPredicate, 5, 200, 0, // Skip to: 13726
+/* 13526 */ MCD_OPC_Decode, 186, 11, 217, 1, // Opcode: SH
+/* 13531 */ MCD_OPC_FilterValue, 42, 9, 0, // Skip to: 13544
+/* 13535 */ MCD_OPC_CheckPredicate, 11, 187, 0, // Skip to: 13726
+/* 13539 */ MCD_OPC_Decode, 243, 12, 217, 1, // Opcode: SWL
+/* 13544 */ MCD_OPC_FilterValue, 43, 9, 0, // Skip to: 13557
+/* 13548 */ MCD_OPC_CheckPredicate, 1, 174, 0, // Skip to: 13726
+/* 13552 */ MCD_OPC_Decode, 235, 12, 217, 1, // Opcode: SW
+/* 13557 */ MCD_OPC_FilterValue, 46, 9, 0, // Skip to: 13570
+/* 13561 */ MCD_OPC_CheckPredicate, 11, 161, 0, // Skip to: 13726
+/* 13565 */ MCD_OPC_Decode, 250, 12, 217, 1, // Opcode: SWR
+/* 13570 */ MCD_OPC_FilterValue, 47, 9, 0, // Skip to: 13583
+/* 13574 */ MCD_OPC_CheckPredicate, 31, 148, 0, // Skip to: 13726
+/* 13578 */ MCD_OPC_Decode, 220, 2, 218, 1, // Opcode: CACHE
+/* 13583 */ MCD_OPC_FilterValue, 48, 9, 0, // Skip to: 13596
+/* 13587 */ MCD_OPC_CheckPredicate, 32, 135, 0, // Skip to: 13726
+/* 13591 */ MCD_OPC_Decode, 193, 7, 217, 1, // Opcode: LL
+/* 13596 */ MCD_OPC_FilterValue, 49, 9, 0, // Skip to: 13609
+/* 13600 */ MCD_OPC_CheckPredicate, 5, 122, 0, // Skip to: 13726
+/* 13604 */ MCD_OPC_Decode, 216, 7, 219, 1, // Opcode: LWC1
+/* 13609 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 13622
+/* 13613 */ MCD_OPC_CheckPredicate, 33, 109, 0, // Skip to: 13726
+/* 13617 */ MCD_OPC_Decode, 218, 7, 220, 1, // Opcode: LWC2
+/* 13622 */ MCD_OPC_FilterValue, 51, 9, 0, // Skip to: 13635
+/* 13626 */ MCD_OPC_CheckPredicate, 31, 96, 0, // Skip to: 13726
+/* 13630 */ MCD_OPC_Decode, 181, 10, 218, 1, // Opcode: PREF
+/* 13635 */ MCD_OPC_FilterValue, 53, 9, 0, // Skip to: 13648
+/* 13639 */ MCD_OPC_CheckPredicate, 34, 83, 0, // Skip to: 13726
+/* 13643 */ MCD_OPC_Decode, 162, 7, 219, 1, // Opcode: LDC1
+/* 13648 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 13661
+/* 13652 */ MCD_OPC_CheckPredicate, 35, 70, 0, // Skip to: 13726
+/* 13656 */ MCD_OPC_Decode, 165, 7, 220, 1, // Opcode: LDC2
+/* 13661 */ MCD_OPC_FilterValue, 56, 9, 0, // Skip to: 13674
+/* 13665 */ MCD_OPC_CheckPredicate, 32, 57, 0, // Skip to: 13726
+/* 13669 */ MCD_OPC_Decode, 146, 11, 217, 1, // Opcode: SC
+/* 13674 */ MCD_OPC_FilterValue, 57, 9, 0, // Skip to: 13687
+/* 13678 */ MCD_OPC_CheckPredicate, 5, 44, 0, // Skip to: 13726
+/* 13682 */ MCD_OPC_Decode, 238, 12, 219, 1, // Opcode: SWC1
+/* 13687 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 13700
+/* 13691 */ MCD_OPC_CheckPredicate, 33, 31, 0, // Skip to: 13726
+/* 13695 */ MCD_OPC_Decode, 240, 12, 220, 1, // Opcode: SWC2
+/* 13700 */ MCD_OPC_FilterValue, 61, 9, 0, // Skip to: 13713
+/* 13704 */ MCD_OPC_CheckPredicate, 34, 18, 0, // Skip to: 13726
+/* 13708 */ MCD_OPC_Decode, 156, 11, 219, 1, // Opcode: SDC1
+/* 13713 */ MCD_OPC_FilterValue, 62, 9, 0, // Skip to: 13726
+/* 13717 */ MCD_OPC_CheckPredicate, 35, 5, 0, // Skip to: 13726
+/* 13721 */ MCD_OPC_Decode, 159, 11, 220, 1, // Opcode: SDC2
+/* 13726 */ MCD_OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableMips32r6_64r632[] = {
+/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ...
+/* 3 */ MCD_OPC_FilterValue, 0, 205, 1, // Skip to: 468
+/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 10 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 29
+/* 14 */ MCD_OPC_CheckPredicate, 36, 37, 7, // Skip to: 1847
+/* 18 */ MCD_OPC_CheckField, 8, 3, 0, 31, 7, // Skip to: 1847
+/* 24 */ MCD_OPC_Decode, 206, 7, 221, 1, // Opcode: LSA_R6
+/* 29 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 47
+/* 33 */ MCD_OPC_CheckPredicate, 36, 18, 7, // Skip to: 1847
+/* 37 */ MCD_OPC_CheckField, 6, 15, 16, 12, 7, // Skip to: 1847
+/* 43 */ MCD_OPC_Decode, 142, 7, 61, // Opcode: JR_HB_R6
+/* 47 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 59
+/* 51 */ MCD_OPC_CheckPredicate, 36, 0, 7, // Skip to: 1847
+/* 55 */ MCD_OPC_Decode, 155, 11, 64, // Opcode: SDBBP_R6
+/* 59 */ MCD_OPC_FilterValue, 16, 20, 0, // Skip to: 83
+/* 63 */ MCD_OPC_CheckPredicate, 36, 244, 6, // Skip to: 1847
+/* 67 */ MCD_OPC_CheckField, 16, 5, 0, 238, 6, // Skip to: 1847
+/* 73 */ MCD_OPC_CheckField, 6, 5, 1, 232, 6, // Skip to: 1847
+/* 79 */ MCD_OPC_Decode, 154, 3, 62, // Opcode: CLZ_R6
+/* 83 */ MCD_OPC_FilterValue, 17, 20, 0, // Skip to: 107
+/* 87 */ MCD_OPC_CheckPredicate, 36, 220, 6, // Skip to: 1847
+/* 91 */ MCD_OPC_CheckField, 16, 5, 0, 214, 6, // Skip to: 1847
+/* 97 */ MCD_OPC_CheckField, 6, 5, 1, 208, 6, // Skip to: 1847
+/* 103 */ MCD_OPC_Decode, 135, 3, 62, // Opcode: CLO_R6
+/* 107 */ MCD_OPC_FilterValue, 18, 21, 0, // Skip to: 132
+/* 111 */ MCD_OPC_CheckPredicate, 37, 196, 6, // Skip to: 1847
+/* 115 */ MCD_OPC_CheckField, 16, 5, 0, 190, 6, // Skip to: 1847
+/* 121 */ MCD_OPC_CheckField, 6, 5, 1, 184, 6, // Skip to: 1847
+/* 127 */ MCD_OPC_Decode, 171, 4, 222, 1, // Opcode: DCLZ_R6
+/* 132 */ MCD_OPC_FilterValue, 19, 21, 0, // Skip to: 157
+/* 136 */ MCD_OPC_CheckPredicate, 37, 171, 6, // Skip to: 1847
+/* 140 */ MCD_OPC_CheckField, 16, 5, 0, 165, 6, // Skip to: 1847
+/* 146 */ MCD_OPC_CheckField, 6, 5, 1, 159, 6, // Skip to: 1847
+/* 152 */ MCD_OPC_Decode, 169, 4, 222, 1, // Opcode: DCLO_R6
+/* 157 */ MCD_OPC_FilterValue, 21, 15, 0, // Skip to: 176
+/* 161 */ MCD_OPC_CheckPredicate, 37, 146, 6, // Skip to: 1847
+/* 165 */ MCD_OPC_CheckField, 8, 3, 0, 140, 6, // Skip to: 1847
+/* 171 */ MCD_OPC_Decode, 195, 4, 223, 1, // Opcode: DLSA_R6
+/* 176 */ MCD_OPC_FilterValue, 24, 27, 0, // Skip to: 207
+/* 180 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 183 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 195
+/* 187 */ MCD_OPC_CheckPredicate, 36, 120, 6, // Skip to: 1847
+/* 191 */ MCD_OPC_Decode, 221, 9, 35, // Opcode: MUL_R6
+/* 195 */ MCD_OPC_FilterValue, 3, 112, 6, // Skip to: 1847
+/* 199 */ MCD_OPC_CheckPredicate, 36, 108, 6, // Skip to: 1847
+/* 203 */ MCD_OPC_Decode, 191, 9, 35, // Opcode: MUH
+/* 207 */ MCD_OPC_FilterValue, 25, 27, 0, // Skip to: 238
+/* 211 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 214 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 226
+/* 218 */ MCD_OPC_CheckPredicate, 36, 89, 6, // Skip to: 1847
+/* 222 */ MCD_OPC_Decode, 212, 9, 35, // Opcode: MULU
+/* 226 */ MCD_OPC_FilterValue, 3, 81, 6, // Skip to: 1847
+/* 230 */ MCD_OPC_CheckPredicate, 36, 77, 6, // Skip to: 1847
+/* 234 */ MCD_OPC_Decode, 192, 9, 35, // Opcode: MUHU
+/* 238 */ MCD_OPC_FilterValue, 26, 27, 0, // Skip to: 269
+/* 242 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 245 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 257
+/* 249 */ MCD_OPC_CheckPredicate, 36, 58, 6, // Skip to: 1847
+/* 253 */ MCD_OPC_Decode, 183, 4, 35, // Opcode: DIV
+/* 257 */ MCD_OPC_FilterValue, 3, 50, 6, // Skip to: 1847
+/* 261 */ MCD_OPC_CheckPredicate, 36, 46, 6, // Skip to: 1847
+/* 265 */ MCD_OPC_Decode, 222, 8, 35, // Opcode: MOD
+/* 269 */ MCD_OPC_FilterValue, 27, 27, 0, // Skip to: 300
+/* 273 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 276 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 288
+/* 280 */ MCD_OPC_CheckPredicate, 36, 27, 6, // Skip to: 1847
+/* 284 */ MCD_OPC_Decode, 184, 4, 35, // Opcode: DIVU
+/* 288 */ MCD_OPC_FilterValue, 3, 19, 6, // Skip to: 1847
+/* 292 */ MCD_OPC_CheckPredicate, 36, 15, 6, // Skip to: 1847
+/* 296 */ MCD_OPC_Decode, 224, 8, 35, // Opcode: MODU
+/* 300 */ MCD_OPC_FilterValue, 28, 29, 0, // Skip to: 333
+/* 304 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 307 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 320
+/* 311 */ MCD_OPC_CheckPredicate, 37, 252, 5, // Skip to: 1847
+/* 315 */ MCD_OPC_Decode, 210, 4, 224, 1, // Opcode: DMUL_R6
+/* 320 */ MCD_OPC_FilterValue, 3, 243, 5, // Skip to: 1847
+/* 324 */ MCD_OPC_CheckPredicate, 37, 239, 5, // Skip to: 1847
+/* 328 */ MCD_OPC_Decode, 204, 4, 224, 1, // Opcode: DMUH
+/* 333 */ MCD_OPC_FilterValue, 29, 29, 0, // Skip to: 366
+/* 337 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 340 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 353
+/* 344 */ MCD_OPC_CheckPredicate, 37, 219, 5, // Skip to: 1847
+/* 348 */ MCD_OPC_Decode, 209, 4, 224, 1, // Opcode: DMULU
+/* 353 */ MCD_OPC_FilterValue, 3, 210, 5, // Skip to: 1847
+/* 357 */ MCD_OPC_CheckPredicate, 37, 206, 5, // Skip to: 1847
+/* 361 */ MCD_OPC_Decode, 205, 4, 224, 1, // Opcode: DMUHU
+/* 366 */ MCD_OPC_FilterValue, 30, 29, 0, // Skip to: 399
+/* 370 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 373 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 386
+/* 377 */ MCD_OPC_CheckPredicate, 37, 186, 5, // Skip to: 1847
+/* 381 */ MCD_OPC_Decode, 172, 4, 224, 1, // Opcode: DDIV
+/* 386 */ MCD_OPC_FilterValue, 3, 177, 5, // Skip to: 1847
+/* 390 */ MCD_OPC_CheckPredicate, 37, 173, 5, // Skip to: 1847
+/* 394 */ MCD_OPC_Decode, 199, 4, 224, 1, // Opcode: DMOD
+/* 399 */ MCD_OPC_FilterValue, 31, 29, 0, // Skip to: 432
+/* 403 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 406 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 419
+/* 410 */ MCD_OPC_CheckPredicate, 37, 153, 5, // Skip to: 1847
+/* 414 */ MCD_OPC_Decode, 173, 4, 224, 1, // Opcode: DDIVU
+/* 419 */ MCD_OPC_FilterValue, 3, 144, 5, // Skip to: 1847
+/* 423 */ MCD_OPC_CheckPredicate, 37, 140, 5, // Skip to: 1847
+/* 427 */ MCD_OPC_Decode, 200, 4, 224, 1, // Opcode: DMODU
+/* 432 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 450
+/* 436 */ MCD_OPC_CheckPredicate, 38, 127, 5, // Skip to: 1847
+/* 440 */ MCD_OPC_CheckField, 6, 5, 0, 121, 5, // Skip to: 1847
+/* 446 */ MCD_OPC_Decode, 174, 11, 35, // Opcode: SELEQZ
+/* 450 */ MCD_OPC_FilterValue, 55, 113, 5, // Skip to: 1847
+/* 454 */ MCD_OPC_CheckPredicate, 38, 109, 5, // Skip to: 1847
+/* 458 */ MCD_OPC_CheckField, 6, 5, 0, 103, 5, // Skip to: 1847
+/* 464 */ MCD_OPC_Decode, 178, 11, 35, // Opcode: SELNEZ
+/* 468 */ MCD_OPC_FilterValue, 1, 47, 0, // Skip to: 519
+/* 472 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ...
+/* 475 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 488
+/* 479 */ MCD_OPC_CheckPredicate, 37, 84, 5, // Skip to: 1847
+/* 483 */ MCD_OPC_Decode, 163, 4, 225, 1, // Opcode: DAHI
+/* 488 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 506
+/* 492 */ MCD_OPC_CheckPredicate, 36, 71, 5, // Skip to: 1847
+/* 496 */ MCD_OPC_CheckField, 21, 5, 0, 65, 5, // Skip to: 1847
+/* 502 */ MCD_OPC_Decode, 167, 1, 75, // Opcode: BAL
+/* 506 */ MCD_OPC_FilterValue, 30, 57, 5, // Skip to: 1847
+/* 510 */ MCD_OPC_CheckPredicate, 37, 53, 5, // Skip to: 1847
+/* 514 */ MCD_OPC_Decode, 165, 4, 225, 1, // Opcode: DATI
+/* 519 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 532
+/* 523 */ MCD_OPC_CheckPredicate, 36, 40, 5, // Skip to: 1847
+/* 527 */ MCD_OPC_Decode, 220, 1, 226, 1, // Opcode: BGEZALC
+/* 532 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 545
+/* 536 */ MCD_OPC_CheckPredicate, 36, 27, 5, // Skip to: 1847
+/* 540 */ MCD_OPC_Decode, 134, 2, 227, 1, // Opcode: BLTZALC
+/* 545 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 558
+/* 549 */ MCD_OPC_CheckPredicate, 36, 14, 5, // Skip to: 1847
+/* 553 */ MCD_OPC_Decode, 208, 1, 228, 1, // Opcode: BEQC
+/* 558 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 570
+/* 562 */ MCD_OPC_CheckPredicate, 36, 1, 5, // Skip to: 1847
+/* 566 */ MCD_OPC_Decode, 137, 1, 47, // Opcode: AUI
+/* 570 */ MCD_OPC_FilterValue, 17, 5, 3, // Skip to: 1347
+/* 574 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 577 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 590
+/* 581 */ MCD_OPC_CheckPredicate, 36, 238, 4, // Skip to: 1847
+/* 585 */ MCD_OPC_Decode, 180, 1, 229, 1, // Opcode: BC1EQZ
+/* 590 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 603
+/* 594 */ MCD_OPC_CheckPredicate, 36, 225, 4, // Skip to: 1847
+/* 598 */ MCD_OPC_Decode, 184, 1, 229, 1, // Opcode: BC1NEZ
+/* 603 */ MCD_OPC_FilterValue, 16, 150, 0, // Skip to: 757
+/* 607 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 610 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 623
+/* 614 */ MCD_OPC_CheckPredicate, 36, 205, 4, // Skip to: 1847
+/* 618 */ MCD_OPC_Decode, 183, 11, 230, 1, // Opcode: SEL_S
+/* 623 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 635
+/* 627 */ MCD_OPC_CheckPredicate, 36, 192, 4, // Skip to: 1847
+/* 631 */ MCD_OPC_Decode, 177, 11, 93, // Opcode: SELEQZ_S
+/* 635 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 647
+/* 639 */ MCD_OPC_CheckPredicate, 36, 180, 4, // Skip to: 1847
+/* 643 */ MCD_OPC_Decode, 181, 11, 93, // Opcode: SELNEZ_S
+/* 647 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 660
+/* 651 */ MCD_OPC_CheckPredicate, 36, 168, 4, // Skip to: 1847
+/* 655 */ MCD_OPC_Decode, 132, 8, 231, 1, // Opcode: MADDF_S
+/* 660 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 673
+/* 664 */ MCD_OPC_CheckPredicate, 36, 155, 4, // Skip to: 1847
+/* 668 */ MCD_OPC_Decode, 150, 9, 231, 1, // Opcode: MSUBF_S
+/* 673 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 691
+/* 677 */ MCD_OPC_CheckPredicate, 36, 142, 4, // Skip to: 1847
+/* 681 */ MCD_OPC_CheckField, 16, 5, 0, 136, 4, // Skip to: 1847
+/* 687 */ MCD_OPC_Decode, 246, 10, 94, // Opcode: RINT_S
+/* 691 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 709
+/* 695 */ MCD_OPC_CheckPredicate, 36, 124, 4, // Skip to: 1847
+/* 699 */ MCD_OPC_CheckField, 16, 5, 0, 118, 4, // Skip to: 1847
+/* 705 */ MCD_OPC_Decode, 244, 2, 94, // Opcode: CLASS_S
+/* 709 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 721
+/* 713 */ MCD_OPC_CheckPredicate, 36, 106, 4, // Skip to: 1847
+/* 717 */ MCD_OPC_Decode, 211, 8, 93, // Opcode: MIN_S
+/* 721 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 733
+/* 725 */ MCD_OPC_CheckPredicate, 36, 94, 4, // Skip to: 1847
+/* 729 */ MCD_OPC_Decode, 170, 8, 93, // Opcode: MAX_S
+/* 733 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 745
+/* 737 */ MCD_OPC_CheckPredicate, 36, 82, 4, // Skip to: 1847
+/* 741 */ MCD_OPC_Decode, 197, 8, 93, // Opcode: MINA_S
+/* 745 */ MCD_OPC_FilterValue, 31, 74, 4, // Skip to: 1847
+/* 749 */ MCD_OPC_CheckPredicate, 36, 70, 4, // Skip to: 1847
+/* 753 */ MCD_OPC_Decode, 156, 8, 93, // Opcode: MAXA_S
+/* 757 */ MCD_OPC_FilterValue, 17, 156, 0, // Skip to: 917
+/* 761 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 764 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 777
+/* 768 */ MCD_OPC_CheckPredicate, 36, 51, 4, // Skip to: 1847
+/* 772 */ MCD_OPC_Decode, 182, 11, 232, 1, // Opcode: SEL_D
+/* 777 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 790
+/* 781 */ MCD_OPC_CheckPredicate, 36, 38, 4, // Skip to: 1847
+/* 785 */ MCD_OPC_Decode, 176, 11, 233, 1, // Opcode: SELEQZ_D
+/* 790 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 803
+/* 794 */ MCD_OPC_CheckPredicate, 36, 25, 4, // Skip to: 1847
+/* 798 */ MCD_OPC_Decode, 180, 11, 233, 1, // Opcode: SELNEZ_D
+/* 803 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 816
+/* 807 */ MCD_OPC_CheckPredicate, 36, 12, 4, // Skip to: 1847
+/* 811 */ MCD_OPC_Decode, 131, 8, 234, 1, // Opcode: MADDF_D
+/* 816 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 829
+/* 820 */ MCD_OPC_CheckPredicate, 36, 255, 3, // Skip to: 1847
+/* 824 */ MCD_OPC_Decode, 149, 9, 234, 1, // Opcode: MSUBF_D
+/* 829 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 847
+/* 833 */ MCD_OPC_CheckPredicate, 36, 242, 3, // Skip to: 1847
+/* 837 */ MCD_OPC_CheckField, 16, 5, 0, 236, 3, // Skip to: 1847
+/* 843 */ MCD_OPC_Decode, 245, 10, 105, // Opcode: RINT_D
+/* 847 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 865
+/* 851 */ MCD_OPC_CheckPredicate, 36, 224, 3, // Skip to: 1847
+/* 855 */ MCD_OPC_CheckField, 16, 5, 0, 218, 3, // Skip to: 1847
+/* 861 */ MCD_OPC_Decode, 243, 2, 105, // Opcode: CLASS_D
+/* 865 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 878
+/* 869 */ MCD_OPC_CheckPredicate, 36, 206, 3, // Skip to: 1847
+/* 873 */ MCD_OPC_Decode, 210, 8, 233, 1, // Opcode: MIN_D
+/* 878 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 891
+/* 882 */ MCD_OPC_CheckPredicate, 36, 193, 3, // Skip to: 1847
+/* 886 */ MCD_OPC_Decode, 169, 8, 233, 1, // Opcode: MAX_D
+/* 891 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 904
+/* 895 */ MCD_OPC_CheckPredicate, 36, 180, 3, // Skip to: 1847
+/* 899 */ MCD_OPC_Decode, 196, 8, 233, 1, // Opcode: MINA_D
+/* 904 */ MCD_OPC_FilterValue, 31, 171, 3, // Skip to: 1847
+/* 908 */ MCD_OPC_CheckPredicate, 36, 167, 3, // Skip to: 1847
+/* 912 */ MCD_OPC_Decode, 155, 8, 233, 1, // Opcode: MAXA_D
+/* 917 */ MCD_OPC_FilterValue, 20, 211, 0, // Skip to: 1132
+/* 921 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 924 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 937
+/* 928 */ MCD_OPC_CheckPredicate, 36, 147, 3, // Skip to: 1847
+/* 932 */ MCD_OPC_Decode, 168, 3, 235, 1, // Opcode: CMP_F_S
+/* 937 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 950
+/* 941 */ MCD_OPC_CheckPredicate, 36, 134, 3, // Skip to: 1847
+/* 945 */ MCD_OPC_Decode, 198, 3, 235, 1, // Opcode: CMP_UN_S
+/* 950 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 963
+/* 954 */ MCD_OPC_CheckPredicate, 36, 121, 3, // Skip to: 1847
+/* 958 */ MCD_OPC_Decode, 166, 3, 235, 1, // Opcode: CMP_EQ_S
+/* 963 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 976
+/* 967 */ MCD_OPC_CheckPredicate, 36, 108, 3, // Skip to: 1847
+/* 971 */ MCD_OPC_Decode, 192, 3, 235, 1, // Opcode: CMP_UEQ_S
+/* 976 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 989
+/* 980 */ MCD_OPC_CheckPredicate, 36, 95, 3, // Skip to: 1847
+/* 984 */ MCD_OPC_Decode, 174, 3, 235, 1, // Opcode: CMP_LT_S
+/* 989 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 1002
+/* 993 */ MCD_OPC_CheckPredicate, 36, 82, 3, // Skip to: 1847
+/* 997 */ MCD_OPC_Decode, 196, 3, 235, 1, // Opcode: CMP_ULT_S
+/* 1002 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 1015
+/* 1006 */ MCD_OPC_CheckPredicate, 36, 69, 3, // Skip to: 1847
+/* 1010 */ MCD_OPC_Decode, 171, 3, 235, 1, // Opcode: CMP_LE_S
+/* 1015 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 1028
+/* 1019 */ MCD_OPC_CheckPredicate, 36, 56, 3, // Skip to: 1847
+/* 1023 */ MCD_OPC_Decode, 194, 3, 235, 1, // Opcode: CMP_ULE_S
+/* 1028 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 1041
+/* 1032 */ MCD_OPC_CheckPredicate, 36, 43, 3, // Skip to: 1847
+/* 1036 */ MCD_OPC_Decode, 176, 3, 235, 1, // Opcode: CMP_SAF_S
+/* 1041 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1054
+/* 1045 */ MCD_OPC_CheckPredicate, 36, 30, 3, // Skip to: 1847
+/* 1049 */ MCD_OPC_Decode, 190, 3, 235, 1, // Opcode: CMP_SUN_S
+/* 1054 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1067
+/* 1058 */ MCD_OPC_CheckPredicate, 36, 17, 3, // Skip to: 1847
+/* 1062 */ MCD_OPC_Decode, 178, 3, 235, 1, // Opcode: CMP_SEQ_S
+/* 1067 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1080
+/* 1071 */ MCD_OPC_CheckPredicate, 36, 4, 3, // Skip to: 1847
+/* 1075 */ MCD_OPC_Decode, 184, 3, 235, 1, // Opcode: CMP_SUEQ_S
+/* 1080 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 1093
+/* 1084 */ MCD_OPC_CheckPredicate, 36, 247, 2, // Skip to: 1847
+/* 1088 */ MCD_OPC_Decode, 182, 3, 235, 1, // Opcode: CMP_SLT_S
+/* 1093 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1106
+/* 1097 */ MCD_OPC_CheckPredicate, 36, 234, 2, // Skip to: 1847
+/* 1101 */ MCD_OPC_Decode, 188, 3, 235, 1, // Opcode: CMP_SULT_S
+/* 1106 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1119
+/* 1110 */ MCD_OPC_CheckPredicate, 36, 221, 2, // Skip to: 1847
+/* 1114 */ MCD_OPC_Decode, 180, 3, 235, 1, // Opcode: CMP_SLE_S
+/* 1119 */ MCD_OPC_FilterValue, 15, 212, 2, // Skip to: 1847
+/* 1123 */ MCD_OPC_CheckPredicate, 36, 208, 2, // Skip to: 1847
+/* 1127 */ MCD_OPC_Decode, 186, 3, 235, 1, // Opcode: CMP_SULE_S
+/* 1132 */ MCD_OPC_FilterValue, 21, 199, 2, // Skip to: 1847
+/* 1136 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 1139 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1152
+/* 1143 */ MCD_OPC_CheckPredicate, 36, 188, 2, // Skip to: 1847
+/* 1147 */ MCD_OPC_Decode, 167, 3, 236, 1, // Opcode: CMP_F_D
+/* 1152 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 1165
+/* 1156 */ MCD_OPC_CheckPredicate, 36, 175, 2, // Skip to: 1847
+/* 1160 */ MCD_OPC_Decode, 197, 3, 236, 1, // Opcode: CMP_UN_D
+/* 1165 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1178
+/* 1169 */ MCD_OPC_CheckPredicate, 36, 162, 2, // Skip to: 1847
+/* 1173 */ MCD_OPC_Decode, 164, 3, 236, 1, // Opcode: CMP_EQ_D
+/* 1178 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 1191
+/* 1182 */ MCD_OPC_CheckPredicate, 36, 149, 2, // Skip to: 1847
+/* 1186 */ MCD_OPC_Decode, 191, 3, 236, 1, // Opcode: CMP_UEQ_D
+/* 1191 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 1204
+/* 1195 */ MCD_OPC_CheckPredicate, 36, 136, 2, // Skip to: 1847
+/* 1199 */ MCD_OPC_Decode, 172, 3, 236, 1, // Opcode: CMP_LT_D
+/* 1204 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 1217
+/* 1208 */ MCD_OPC_CheckPredicate, 36, 123, 2, // Skip to: 1847
+/* 1212 */ MCD_OPC_Decode, 195, 3, 236, 1, // Opcode: CMP_ULT_D
+/* 1217 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 1230
+/* 1221 */ MCD_OPC_CheckPredicate, 36, 110, 2, // Skip to: 1847
+/* 1225 */ MCD_OPC_Decode, 169, 3, 236, 1, // Opcode: CMP_LE_D
+/* 1230 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 1243
+/* 1234 */ MCD_OPC_CheckPredicate, 36, 97, 2, // Skip to: 1847
+/* 1238 */ MCD_OPC_Decode, 193, 3, 236, 1, // Opcode: CMP_ULE_D
+/* 1243 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 1256
+/* 1247 */ MCD_OPC_CheckPredicate, 36, 84, 2, // Skip to: 1847
+/* 1251 */ MCD_OPC_Decode, 175, 3, 236, 1, // Opcode: CMP_SAF_D
+/* 1256 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1269
+/* 1260 */ MCD_OPC_CheckPredicate, 36, 71, 2, // Skip to: 1847
+/* 1264 */ MCD_OPC_Decode, 189, 3, 236, 1, // Opcode: CMP_SUN_D
+/* 1269 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1282
+/* 1273 */ MCD_OPC_CheckPredicate, 36, 58, 2, // Skip to: 1847
+/* 1277 */ MCD_OPC_Decode, 177, 3, 236, 1, // Opcode: CMP_SEQ_D
+/* 1282 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1295
+/* 1286 */ MCD_OPC_CheckPredicate, 36, 45, 2, // Skip to: 1847
+/* 1290 */ MCD_OPC_Decode, 183, 3, 236, 1, // Opcode: CMP_SUEQ_D
+/* 1295 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 1308
+/* 1299 */ MCD_OPC_CheckPredicate, 36, 32, 2, // Skip to: 1847
+/* 1303 */ MCD_OPC_Decode, 181, 3, 236, 1, // Opcode: CMP_SLT_D
+/* 1308 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1321
+/* 1312 */ MCD_OPC_CheckPredicate, 36, 19, 2, // Skip to: 1847
+/* 1316 */ MCD_OPC_Decode, 187, 3, 236, 1, // Opcode: CMP_SULT_D
+/* 1321 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1334
+/* 1325 */ MCD_OPC_CheckPredicate, 36, 6, 2, // Skip to: 1847
+/* 1329 */ MCD_OPC_Decode, 179, 3, 236, 1, // Opcode: CMP_SLE_D
+/* 1334 */ MCD_OPC_FilterValue, 15, 253, 1, // Skip to: 1847
+/* 1338 */ MCD_OPC_CheckPredicate, 36, 249, 1, // Skip to: 1847
+/* 1342 */ MCD_OPC_Decode, 185, 3, 236, 1, // Opcode: CMP_SULE_D
+/* 1347 */ MCD_OPC_FilterValue, 18, 81, 0, // Skip to: 1432
+/* 1351 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 1354 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1367
+/* 1358 */ MCD_OPC_CheckPredicate, 36, 229, 1, // Skip to: 1847
+/* 1362 */ MCD_OPC_Decode, 188, 1, 237, 1, // Opcode: BC2EQZ
+/* 1367 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1380
+/* 1371 */ MCD_OPC_CheckPredicate, 36, 216, 1, // Skip to: 1847
+/* 1375 */ MCD_OPC_Decode, 219, 7, 238, 1, // Opcode: LWC2_R6
+/* 1380 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1393
+/* 1384 */ MCD_OPC_CheckPredicate, 36, 203, 1, // Skip to: 1847
+/* 1388 */ MCD_OPC_Decode, 241, 12, 238, 1, // Opcode: SWC2_R6
+/* 1393 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1406
+/* 1397 */ MCD_OPC_CheckPredicate, 36, 190, 1, // Skip to: 1847
+/* 1401 */ MCD_OPC_Decode, 191, 1, 237, 1, // Opcode: BC2NEZ
+/* 1406 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1419
+/* 1410 */ MCD_OPC_CheckPredicate, 36, 177, 1, // Skip to: 1847
+/* 1414 */ MCD_OPC_Decode, 166, 7, 238, 1, // Opcode: LDC2_R6
+/* 1419 */ MCD_OPC_FilterValue, 15, 168, 1, // Skip to: 1847
+/* 1423 */ MCD_OPC_CheckPredicate, 36, 164, 1, // Skip to: 1847
+/* 1427 */ MCD_OPC_Decode, 160, 11, 238, 1, // Opcode: SDC2_R6
+/* 1432 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 1445
+/* 1436 */ MCD_OPC_CheckPredicate, 36, 151, 1, // Skip to: 1847
+/* 1440 */ MCD_OPC_Decode, 224, 1, 239, 1, // Opcode: BGEZC
+/* 1445 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 1458
+/* 1449 */ MCD_OPC_CheckPredicate, 36, 138, 1, // Skip to: 1847
+/* 1453 */ MCD_OPC_Decode, 138, 2, 240, 1, // Opcode: BLTZC
+/* 1458 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 1471
+/* 1462 */ MCD_OPC_CheckPredicate, 36, 125, 1, // Skip to: 1847
+/* 1466 */ MCD_OPC_Decode, 147, 2, 241, 1, // Opcode: BNEC
+/* 1471 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 1484
+/* 1475 */ MCD_OPC_CheckPredicate, 37, 112, 1, // Skip to: 1847
+/* 1479 */ MCD_OPC_Decode, 166, 4, 242, 1, // Opcode: DAUI
+/* 1484 */ MCD_OPC_FilterValue, 31, 182, 0, // Skip to: 1670
+/* 1488 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 1491 */ MCD_OPC_FilterValue, 32, 40, 0, // Skip to: 1535
+/* 1495 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ...
+/* 1498 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 1523
+/* 1502 */ MCD_OPC_CheckPredicate, 36, 85, 1, // Skip to: 1847
+/* 1506 */ MCD_OPC_CheckField, 21, 5, 0, 79, 1, // Skip to: 1847
+/* 1512 */ MCD_OPC_CheckField, 6, 2, 0, 73, 1, // Skip to: 1847
+/* 1518 */ MCD_OPC_Decode, 250, 1, 205, 1, // Opcode: BITSWAP
+/* 1523 */ MCD_OPC_FilterValue, 2, 64, 1, // Skip to: 1847
+/* 1527 */ MCD_OPC_CheckPredicate, 36, 60, 1, // Skip to: 1847
+/* 1531 */ MCD_OPC_Decode, 81, 221, 1, // Opcode: ALIGN
+/* 1535 */ MCD_OPC_FilterValue, 36, 41, 0, // Skip to: 1580
+/* 1539 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ...
+/* 1542 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 1567
+/* 1546 */ MCD_OPC_CheckPredicate, 37, 41, 1, // Skip to: 1847
+/* 1550 */ MCD_OPC_CheckField, 21, 5, 0, 35, 1, // Skip to: 1847
+/* 1556 */ MCD_OPC_CheckField, 6, 3, 0, 29, 1, // Skip to: 1847
+/* 1562 */ MCD_OPC_Decode, 167, 4, 243, 1, // Opcode: DBITSWAP
+/* 1567 */ MCD_OPC_FilterValue, 1, 20, 1, // Skip to: 1847
+/* 1571 */ MCD_OPC_CheckPredicate, 37, 16, 1, // Skip to: 1847
+/* 1575 */ MCD_OPC_Decode, 164, 4, 244, 1, // Opcode: DALIGN
+/* 1580 */ MCD_OPC_FilterValue, 37, 15, 0, // Skip to: 1599
+/* 1584 */ MCD_OPC_CheckPredicate, 36, 3, 1, // Skip to: 1847
+/* 1588 */ MCD_OPC_CheckField, 6, 1, 0, 253, 0, // Skip to: 1847
+/* 1594 */ MCD_OPC_Decode, 222, 2, 245, 1, // Opcode: CACHE_R6
+/* 1599 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 1612
+/* 1603 */ MCD_OPC_CheckPredicate, 36, 240, 0, // Skip to: 1847
+/* 1607 */ MCD_OPC_Decode, 150, 11, 246, 1, // Opcode: SC_R6
+/* 1612 */ MCD_OPC_FilterValue, 39, 9, 0, // Skip to: 1625
+/* 1616 */ MCD_OPC_CheckPredicate, 36, 227, 0, // Skip to: 1847
+/* 1620 */ MCD_OPC_Decode, 148, 11, 246, 1, // Opcode: SCD_R6
+/* 1625 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 1644
+/* 1629 */ MCD_OPC_CheckPredicate, 36, 214, 0, // Skip to: 1847
+/* 1633 */ MCD_OPC_CheckField, 6, 1, 0, 208, 0, // Skip to: 1847
+/* 1639 */ MCD_OPC_Decode, 183, 10, 245, 1, // Opcode: PREF_R6
+/* 1644 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 1657
+/* 1648 */ MCD_OPC_CheckPredicate, 36, 195, 0, // Skip to: 1847
+/* 1652 */ MCD_OPC_Decode, 197, 7, 246, 1, // Opcode: LL_R6
+/* 1657 */ MCD_OPC_FilterValue, 55, 186, 0, // Skip to: 1847
+/* 1661 */ MCD_OPC_CheckPredicate, 36, 182, 0, // Skip to: 1847
+/* 1665 */ MCD_OPC_Decode, 195, 7, 246, 1, // Opcode: LLD_R6
+/* 1670 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 1683
+/* 1674 */ MCD_OPC_CheckPredicate, 36, 169, 0, // Skip to: 1847
+/* 1678 */ MCD_OPC_Decode, 175, 1, 247, 1, // Opcode: BC
+/* 1683 */ MCD_OPC_FilterValue, 54, 23, 0, // Skip to: 1710
+/* 1687 */ MCD_OPC_CheckPredicate, 36, 10, 0, // Skip to: 1701
+/* 1691 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 1701
+/* 1697 */ MCD_OPC_Decode, 135, 7, 52, // Opcode: JIC
+/* 1701 */ MCD_OPC_CheckPredicate, 36, 142, 0, // Skip to: 1847
+/* 1705 */ MCD_OPC_Decode, 212, 1, 248, 1, // Opcode: BEQZC
+/* 1710 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 1723
+/* 1714 */ MCD_OPC_CheckPredicate, 36, 129, 0, // Skip to: 1847
+/* 1718 */ MCD_OPC_Decode, 168, 1, 247, 1, // Opcode: BALC
+/* 1723 */ MCD_OPC_FilterValue, 59, 93, 0, // Skip to: 1820
+/* 1727 */ MCD_OPC_ExtractField, 19, 2, // Inst{20-19} ...
+/* 1730 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1742
+/* 1734 */ MCD_OPC_CheckPredicate, 36, 109, 0, // Skip to: 1847
+/* 1738 */ MCD_OPC_Decode, 26, 249, 1, // Opcode: ADDIUPC
+/* 1742 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 1755
+/* 1746 */ MCD_OPC_CheckPredicate, 36, 97, 0, // Skip to: 1847
+/* 1750 */ MCD_OPC_Decode, 228, 7, 249, 1, // Opcode: LWPC
+/* 1755 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1768
+/* 1759 */ MCD_OPC_CheckPredicate, 36, 84, 0, // Skip to: 1847
+/* 1763 */ MCD_OPC_Decode, 234, 7, 249, 1, // Opcode: LWUPC
+/* 1768 */ MCD_OPC_FilterValue, 3, 75, 0, // Skip to: 1847
+/* 1772 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ...
+/* 1775 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1788
+/* 1779 */ MCD_OPC_CheckPredicate, 37, 64, 0, // Skip to: 1847
+/* 1783 */ MCD_OPC_Decode, 173, 7, 250, 1, // Opcode: LDPC
+/* 1788 */ MCD_OPC_FilterValue, 1, 55, 0, // Skip to: 1847
+/* 1792 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ...
+/* 1795 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1808
+/* 1799 */ MCD_OPC_CheckPredicate, 36, 44, 0, // Skip to: 1847
+/* 1803 */ MCD_OPC_Decode, 138, 1, 251, 1, // Opcode: AUIPC
+/* 1808 */ MCD_OPC_FilterValue, 3, 35, 0, // Skip to: 1847
+/* 1812 */ MCD_OPC_CheckPredicate, 36, 31, 0, // Skip to: 1847
+/* 1816 */ MCD_OPC_Decode, 82, 251, 1, // Opcode: ALUIPC
+/* 1820 */ MCD_OPC_FilterValue, 62, 23, 0, // Skip to: 1847
+/* 1824 */ MCD_OPC_CheckPredicate, 36, 10, 0, // Skip to: 1838
+/* 1828 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 1838
+/* 1834 */ MCD_OPC_Decode, 134, 7, 52, // Opcode: JIALC
+/* 1838 */ MCD_OPC_CheckPredicate, 36, 5, 0, // Skip to: 1847
+/* 1842 */ MCD_OPC_Decode, 159, 2, 248, 1, // Opcode: BNEZC
+/* 1847 */ MCD_OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableMips32r6_64r6_GP6432[] = {
+/* 0 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ...
+/* 3 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 22
+/* 7 */ MCD_OPC_CheckPredicate, 39, 30, 0, // Skip to: 41
+/* 11 */ MCD_OPC_CheckField, 26, 6, 0, 24, 0, // Skip to: 41
+/* 17 */ MCD_OPC_Decode, 175, 11, 224, 1, // Opcode: SELEQZ64
+/* 22 */ MCD_OPC_FilterValue, 55, 15, 0, // Skip to: 41
+/* 26 */ MCD_OPC_CheckPredicate, 39, 11, 0, // Skip to: 41
+/* 30 */ MCD_OPC_CheckField, 26, 6, 0, 5, 0, // Skip to: 41
+/* 36 */ MCD_OPC_Decode, 179, 11, 224, 1, // Opcode: SELNEZ64
+/* 41 */ MCD_OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableMips6432[] = {
+/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ...
+/* 3 */ MCD_OPC_FilterValue, 0, 112, 1, // Skip to: 375
+/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 10 */ MCD_OPC_FilterValue, 20, 15, 0, // Skip to: 29
+/* 14 */ MCD_OPC_CheckPredicate, 19, 42, 9, // Skip to: 2364
+/* 18 */ MCD_OPC_CheckField, 6, 5, 0, 36, 9, // Skip to: 2364
+/* 24 */ MCD_OPC_Decode, 255, 4, 252, 1, // Opcode: DSLLV
+/* 29 */ MCD_OPC_FilterValue, 22, 29, 0, // Skip to: 62
+/* 33 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 36 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 49
+/* 40 */ MCD_OPC_CheckPredicate, 19, 16, 9, // Skip to: 2364
+/* 44 */ MCD_OPC_Decode, 133, 5, 252, 1, // Opcode: DSRLV
+/* 49 */ MCD_OPC_FilterValue, 1, 7, 9, // Skip to: 2364
+/* 53 */ MCD_OPC_CheckPredicate, 40, 3, 9, // Skip to: 2364
+/* 57 */ MCD_OPC_Decode, 248, 4, 252, 1, // Opcode: DROTRV
+/* 62 */ MCD_OPC_FilterValue, 23, 15, 0, // Skip to: 81
+/* 66 */ MCD_OPC_CheckPredicate, 19, 246, 8, // Skip to: 2364
+/* 70 */ MCD_OPC_CheckField, 6, 5, 0, 240, 8, // Skip to: 2364
+/* 76 */ MCD_OPC_Decode, 130, 5, 252, 1, // Opcode: DSRAV
+/* 81 */ MCD_OPC_FilterValue, 28, 15, 0, // Skip to: 100
+/* 85 */ MCD_OPC_CheckPredicate, 41, 227, 8, // Skip to: 2364
+/* 89 */ MCD_OPC_CheckField, 6, 10, 0, 221, 8, // Skip to: 2364
+/* 95 */ MCD_OPC_Decode, 207, 4, 253, 1, // Opcode: DMULT
+/* 100 */ MCD_OPC_FilterValue, 29, 15, 0, // Skip to: 119
+/* 104 */ MCD_OPC_CheckPredicate, 41, 208, 8, // Skip to: 2364
+/* 108 */ MCD_OPC_CheckField, 6, 10, 0, 202, 8, // Skip to: 2364
+/* 114 */ MCD_OPC_Decode, 208, 4, 253, 1, // Opcode: DMULTu
+/* 119 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 138
+/* 123 */ MCD_OPC_CheckPredicate, 41, 189, 8, // Skip to: 2364
+/* 127 */ MCD_OPC_CheckField, 6, 10, 0, 183, 8, // Skip to: 2364
+/* 133 */ MCD_OPC_Decode, 250, 4, 253, 1, // Opcode: DSDIV
+/* 138 */ MCD_OPC_FilterValue, 31, 15, 0, // Skip to: 157
+/* 142 */ MCD_OPC_CheckPredicate, 41, 170, 8, // Skip to: 2364
+/* 146 */ MCD_OPC_CheckField, 6, 10, 0, 164, 8, // Skip to: 2364
+/* 152 */ MCD_OPC_Decode, 136, 5, 253, 1, // Opcode: DUDIV
+/* 157 */ MCD_OPC_FilterValue, 44, 15, 0, // Skip to: 176
+/* 161 */ MCD_OPC_CheckPredicate, 19, 151, 8, // Skip to: 2364
+/* 165 */ MCD_OPC_CheckField, 6, 5, 0, 145, 8, // Skip to: 2364
+/* 171 */ MCD_OPC_Decode, 159, 4, 224, 1, // Opcode: DADD
+/* 176 */ MCD_OPC_FilterValue, 45, 15, 0, // Skip to: 195
+/* 180 */ MCD_OPC_CheckPredicate, 19, 132, 8, // Skip to: 2364
+/* 184 */ MCD_OPC_CheckField, 6, 5, 0, 126, 8, // Skip to: 2364
+/* 190 */ MCD_OPC_Decode, 162, 4, 224, 1, // Opcode: DADDu
+/* 195 */ MCD_OPC_FilterValue, 46, 15, 0, // Skip to: 214
+/* 199 */ MCD_OPC_CheckPredicate, 19, 113, 8, // Skip to: 2364
+/* 203 */ MCD_OPC_CheckField, 6, 5, 0, 107, 8, // Skip to: 2364
+/* 209 */ MCD_OPC_Decode, 134, 5, 224, 1, // Opcode: DSUB
+/* 214 */ MCD_OPC_FilterValue, 47, 15, 0, // Skip to: 233
+/* 218 */ MCD_OPC_CheckPredicate, 19, 94, 8, // Skip to: 2364
+/* 222 */ MCD_OPC_CheckField, 6, 5, 0, 88, 8, // Skip to: 2364
+/* 228 */ MCD_OPC_Decode, 135, 5, 224, 1, // Opcode: DSUBu
+/* 233 */ MCD_OPC_FilterValue, 56, 15, 0, // Skip to: 252
+/* 237 */ MCD_OPC_CheckPredicate, 19, 75, 8, // Skip to: 2364
+/* 241 */ MCD_OPC_CheckField, 21, 5, 0, 69, 8, // Skip to: 2364
+/* 247 */ MCD_OPC_Decode, 252, 4, 254, 1, // Opcode: DSLL
+/* 252 */ MCD_OPC_FilterValue, 58, 29, 0, // Skip to: 285
+/* 256 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 259 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 272
+/* 263 */ MCD_OPC_CheckPredicate, 19, 49, 8, // Skip to: 2364
+/* 267 */ MCD_OPC_Decode, 131, 5, 254, 1, // Opcode: DSRL
+/* 272 */ MCD_OPC_FilterValue, 1, 40, 8, // Skip to: 2364
+/* 276 */ MCD_OPC_CheckPredicate, 40, 36, 8, // Skip to: 2364
+/* 280 */ MCD_OPC_Decode, 246, 4, 254, 1, // Opcode: DROTR
+/* 285 */ MCD_OPC_FilterValue, 59, 15, 0, // Skip to: 304
+/* 289 */ MCD_OPC_CheckPredicate, 19, 23, 8, // Skip to: 2364
+/* 293 */ MCD_OPC_CheckField, 21, 5, 0, 17, 8, // Skip to: 2364
+/* 299 */ MCD_OPC_Decode, 128, 5, 254, 1, // Opcode: DSRA
+/* 304 */ MCD_OPC_FilterValue, 60, 15, 0, // Skip to: 323
+/* 308 */ MCD_OPC_CheckPredicate, 19, 4, 8, // Skip to: 2364
+/* 312 */ MCD_OPC_CheckField, 21, 5, 0, 254, 7, // Skip to: 2364
+/* 318 */ MCD_OPC_Decode, 253, 4, 254, 1, // Opcode: DSLL32
+/* 323 */ MCD_OPC_FilterValue, 62, 29, 0, // Skip to: 356
+/* 327 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 330 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 343
+/* 334 */ MCD_OPC_CheckPredicate, 19, 234, 7, // Skip to: 2364
+/* 338 */ MCD_OPC_Decode, 132, 5, 254, 1, // Opcode: DSRL32
+/* 343 */ MCD_OPC_FilterValue, 1, 225, 7, // Skip to: 2364
+/* 347 */ MCD_OPC_CheckPredicate, 40, 221, 7, // Skip to: 2364
+/* 351 */ MCD_OPC_Decode, 247, 4, 254, 1, // Opcode: DROTR32
+/* 356 */ MCD_OPC_FilterValue, 63, 212, 7, // Skip to: 2364
+/* 360 */ MCD_OPC_CheckPredicate, 19, 208, 7, // Skip to: 2364
+/* 364 */ MCD_OPC_CheckField, 21, 5, 0, 202, 7, // Skip to: 2364
+/* 370 */ MCD_OPC_Decode, 129, 5, 254, 1, // Opcode: DSRA32
+/* 375 */ MCD_OPC_FilterValue, 16, 41, 0, // Skip to: 420
+/* 379 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 382 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 401
+/* 386 */ MCD_OPC_CheckPredicate, 42, 182, 7, // Skip to: 2364
+/* 390 */ MCD_OPC_CheckField, 3, 8, 0, 176, 7, // Skip to: 2364
+/* 396 */ MCD_OPC_Decode, 196, 4, 255, 1, // Opcode: DMFC0
+/* 401 */ MCD_OPC_FilterValue, 5, 167, 7, // Skip to: 2364
+/* 405 */ MCD_OPC_CheckPredicate, 42, 163, 7, // Skip to: 2364
+/* 409 */ MCD_OPC_CheckField, 3, 8, 0, 157, 7, // Skip to: 2364
+/* 415 */ MCD_OPC_Decode, 201, 4, 255, 1, // Opcode: DMTC0
+/* 420 */ MCD_OPC_FilterValue, 17, 222, 3, // Skip to: 1414
+/* 424 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 427 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 485
+/* 431 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 434 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 453
+/* 438 */ MCD_OPC_CheckPredicate, 43, 130, 7, // Skip to: 2364
+/* 442 */ MCD_OPC_CheckField, 6, 5, 0, 124, 7, // Skip to: 2364
+/* 448 */ MCD_OPC_Decode, 184, 8, 128, 2, // Opcode: MFHC1_D64
+/* 453 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 472
+/* 457 */ MCD_OPC_CheckPredicate, 43, 111, 7, // Skip to: 2364
+/* 461 */ MCD_OPC_CheckField, 6, 5, 0, 105, 7, // Skip to: 2364
+/* 467 */ MCD_OPC_Decode, 174, 9, 129, 2, // Opcode: MTHC1_D64
+/* 472 */ MCD_OPC_FilterValue, 17, 96, 7, // Skip to: 2364
+/* 476 */ MCD_OPC_CheckPredicate, 44, 92, 7, // Skip to: 2364
+/* 480 */ MCD_OPC_Decode, 172, 5, 233, 1, // Opcode: FADD_D64
+/* 485 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 504
+/* 489 */ MCD_OPC_CheckPredicate, 44, 79, 7, // Skip to: 2364
+/* 493 */ MCD_OPC_CheckField, 21, 5, 17, 73, 7, // Skip to: 2364
+/* 499 */ MCD_OPC_Decode, 174, 6, 233, 1, // Opcode: FSUB_D64
+/* 504 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 523
+/* 508 */ MCD_OPC_CheckPredicate, 44, 60, 7, // Skip to: 2364
+/* 512 */ MCD_OPC_CheckField, 21, 5, 17, 54, 7, // Skip to: 2364
+/* 518 */ MCD_OPC_Decode, 137, 6, 233, 1, // Opcode: FMUL_D64
+/* 523 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 542
+/* 527 */ MCD_OPC_CheckPredicate, 44, 41, 7, // Skip to: 2364
+/* 531 */ MCD_OPC_CheckField, 21, 5, 17, 35, 7, // Skip to: 2364
+/* 537 */ MCD_OPC_Decode, 208, 5, 233, 1, // Opcode: FDIV_D64
+/* 542 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 561
+/* 546 */ MCD_OPC_CheckPredicate, 45, 22, 7, // Skip to: 2364
+/* 550 */ MCD_OPC_CheckField, 16, 10, 160, 4, 15, 7, // Skip to: 2364
+/* 557 */ MCD_OPC_Decode, 167, 6, 105, // Opcode: FSQRT_D64
+/* 561 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 580
+/* 565 */ MCD_OPC_CheckPredicate, 44, 3, 7, // Skip to: 2364
+/* 569 */ MCD_OPC_CheckField, 16, 10, 160, 4, 252, 6, // Skip to: 2364
+/* 576 */ MCD_OPC_Decode, 165, 5, 105, // Opcode: FABS_D64
+/* 580 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 599
+/* 584 */ MCD_OPC_CheckPredicate, 44, 240, 6, // Skip to: 2364
+/* 588 */ MCD_OPC_CheckField, 16, 10, 160, 4, 233, 6, // Skip to: 2364
+/* 595 */ MCD_OPC_Decode, 130, 6, 105, // Opcode: FMOV_D64
+/* 599 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 618
+/* 603 */ MCD_OPC_CheckPredicate, 44, 221, 6, // Skip to: 2364
+/* 607 */ MCD_OPC_CheckField, 16, 10, 160, 4, 214, 6, // Skip to: 2364
+/* 614 */ MCD_OPC_Decode, 143, 6, 105, // Opcode: FNEG_D64
+/* 618 */ MCD_OPC_FilterValue, 8, 29, 0, // Skip to: 651
+/* 622 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ...
+/* 625 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 638
+/* 630 */ MCD_OPC_CheckPredicate, 44, 194, 6, // Skip to: 2364
+/* 634 */ MCD_OPC_Decode, 252, 10, 98, // Opcode: ROUND_L_S
+/* 638 */ MCD_OPC_FilterValue, 160, 4, 185, 6, // Skip to: 2364
+/* 643 */ MCD_OPC_CheckPredicate, 44, 181, 6, // Skip to: 2364
+/* 647 */ MCD_OPC_Decode, 251, 10, 105, // Opcode: ROUND_L_D64
+/* 651 */ MCD_OPC_FilterValue, 9, 29, 0, // Skip to: 684
+/* 655 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ...
+/* 658 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 671
+/* 663 */ MCD_OPC_CheckPredicate, 44, 161, 6, // Skip to: 2364
+/* 667 */ MCD_OPC_Decode, 215, 13, 98, // Opcode: TRUNC_L_S
+/* 671 */ MCD_OPC_FilterValue, 160, 4, 152, 6, // Skip to: 2364
+/* 676 */ MCD_OPC_CheckPredicate, 44, 148, 6, // Skip to: 2364
+/* 680 */ MCD_OPC_Decode, 214, 13, 105, // Opcode: TRUNC_L_D64
+/* 684 */ MCD_OPC_FilterValue, 10, 29, 0, // Skip to: 717
+/* 688 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ...
+/* 691 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 704
+/* 696 */ MCD_OPC_CheckPredicate, 44, 128, 6, // Skip to: 2364
+/* 700 */ MCD_OPC_Decode, 224, 2, 98, // Opcode: CEIL_L_S
+/* 704 */ MCD_OPC_FilterValue, 160, 4, 119, 6, // Skip to: 2364
+/* 709 */ MCD_OPC_CheckPredicate, 44, 115, 6, // Skip to: 2364
+/* 713 */ MCD_OPC_Decode, 223, 2, 105, // Opcode: CEIL_L_D64
+/* 717 */ MCD_OPC_FilterValue, 11, 29, 0, // Skip to: 750
+/* 721 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ...
+/* 724 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 737
+/* 729 */ MCD_OPC_CheckPredicate, 44, 95, 6, // Skip to: 2364
+/* 733 */ MCD_OPC_Decode, 240, 5, 98, // Opcode: FLOOR_L_S
+/* 737 */ MCD_OPC_FilterValue, 160, 4, 86, 6, // Skip to: 2364
+/* 742 */ MCD_OPC_CheckPredicate, 44, 82, 6, // Skip to: 2364
+/* 746 */ MCD_OPC_Decode, 239, 5, 105, // Opcode: FLOOR_L_D64
+/* 750 */ MCD_OPC_FilterValue, 12, 16, 0, // Skip to: 770
+/* 754 */ MCD_OPC_CheckPredicate, 45, 70, 6, // Skip to: 2364
+/* 758 */ MCD_OPC_CheckField, 16, 10, 160, 4, 63, 6, // Skip to: 2364
+/* 765 */ MCD_OPC_Decode, 254, 10, 130, 2, // Opcode: ROUND_W_D64
+/* 770 */ MCD_OPC_FilterValue, 13, 16, 0, // Skip to: 790
+/* 774 */ MCD_OPC_CheckPredicate, 45, 50, 6, // Skip to: 2364
+/* 778 */ MCD_OPC_CheckField, 16, 10, 160, 4, 43, 6, // Skip to: 2364
+/* 785 */ MCD_OPC_Decode, 217, 13, 130, 2, // Opcode: TRUNC_W_D64
+/* 790 */ MCD_OPC_FilterValue, 14, 16, 0, // Skip to: 810
+/* 794 */ MCD_OPC_CheckPredicate, 45, 30, 6, // Skip to: 2364
+/* 798 */ MCD_OPC_CheckField, 16, 10, 160, 4, 23, 6, // Skip to: 2364
+/* 805 */ MCD_OPC_Decode, 226, 2, 130, 2, // Opcode: CEIL_W_D64
+/* 810 */ MCD_OPC_FilterValue, 15, 16, 0, // Skip to: 830
+/* 814 */ MCD_OPC_CheckPredicate, 45, 10, 6, // Skip to: 2364
+/* 818 */ MCD_OPC_CheckField, 16, 10, 160, 4, 3, 6, // Skip to: 2364
+/* 825 */ MCD_OPC_Decode, 242, 5, 130, 2, // Opcode: FLOOR_W_D64
+/* 830 */ MCD_OPC_FilterValue, 17, 41, 0, // Skip to: 875
+/* 834 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ...
+/* 837 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 856
+/* 841 */ MCD_OPC_CheckPredicate, 46, 239, 5, // Skip to: 2364
+/* 845 */ MCD_OPC_CheckField, 21, 5, 17, 233, 5, // Skip to: 2364
+/* 851 */ MCD_OPC_Decode, 238, 8, 131, 2, // Opcode: MOVF_D64
+/* 856 */ MCD_OPC_FilterValue, 1, 224, 5, // Skip to: 2364
+/* 860 */ MCD_OPC_CheckPredicate, 46, 220, 5, // Skip to: 2364
+/* 864 */ MCD_OPC_CheckField, 21, 5, 17, 214, 5, // Skip to: 2364
+/* 870 */ MCD_OPC_Decode, 130, 9, 131, 2, // Opcode: MOVT_D64
+/* 875 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 894
+/* 879 */ MCD_OPC_CheckPredicate, 46, 201, 5, // Skip to: 2364
+/* 883 */ MCD_OPC_CheckField, 21, 5, 17, 195, 5, // Skip to: 2364
+/* 889 */ MCD_OPC_Decode, 142, 9, 132, 2, // Opcode: MOVZ_I_D64
+/* 894 */ MCD_OPC_FilterValue, 19, 15, 0, // Skip to: 913
+/* 898 */ MCD_OPC_CheckPredicate, 46, 182, 5, // Skip to: 2364
+/* 902 */ MCD_OPC_CheckField, 21, 5, 17, 176, 5, // Skip to: 2364
+/* 908 */ MCD_OPC_Decode, 250, 8, 132, 2, // Opcode: MOVN_I_D64
+/* 913 */ MCD_OPC_FilterValue, 32, 31, 0, // Skip to: 948
+/* 917 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ...
+/* 920 */ MCD_OPC_FilterValue, 160, 4, 9, 0, // Skip to: 934
+/* 925 */ MCD_OPC_CheckPredicate, 44, 155, 5, // Skip to: 2364
+/* 929 */ MCD_OPC_Decode, 226, 3, 130, 2, // Opcode: CVT_S_D64
+/* 934 */ MCD_OPC_FilterValue, 160, 5, 145, 5, // Skip to: 2364
+/* 939 */ MCD_OPC_CheckPredicate, 44, 141, 5, // Skip to: 2364
+/* 943 */ MCD_OPC_Decode, 227, 3, 130, 2, // Opcode: CVT_S_L
+/* 948 */ MCD_OPC_FilterValue, 33, 42, 0, // Skip to: 994
+/* 952 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ...
+/* 955 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 968
+/* 960 */ MCD_OPC_CheckPredicate, 44, 120, 5, // Skip to: 2364
+/* 964 */ MCD_OPC_Decode, 217, 3, 98, // Opcode: CVT_D64_S
+/* 968 */ MCD_OPC_FilterValue, 128, 5, 8, 0, // Skip to: 981
+/* 973 */ MCD_OPC_CheckPredicate, 44, 107, 5, // Skip to: 2364
+/* 977 */ MCD_OPC_Decode, 218, 3, 98, // Opcode: CVT_D64_W
+/* 981 */ MCD_OPC_FilterValue, 160, 5, 98, 5, // Skip to: 2364
+/* 986 */ MCD_OPC_CheckPredicate, 44, 94, 5, // Skip to: 2364
+/* 990 */ MCD_OPC_Decode, 216, 3, 105, // Opcode: CVT_D64_L
+/* 994 */ MCD_OPC_FilterValue, 36, 16, 0, // Skip to: 1014
+/* 998 */ MCD_OPC_CheckPredicate, 44, 82, 5, // Skip to: 2364
+/* 1002 */ MCD_OPC_CheckField, 16, 10, 160, 4, 75, 5, // Skip to: 2364
+/* 1009 */ MCD_OPC_Decode, 231, 3, 130, 2, // Opcode: CVT_W_D64
+/* 1014 */ MCD_OPC_FilterValue, 48, 21, 0, // Skip to: 1039
+/* 1018 */ MCD_OPC_CheckPredicate, 47, 62, 5, // Skip to: 2364
+/* 1022 */ MCD_OPC_CheckField, 21, 5, 17, 56, 5, // Skip to: 2364
+/* 1028 */ MCD_OPC_CheckField, 6, 5, 0, 50, 5, // Skip to: 2364
+/* 1034 */ MCD_OPC_Decode, 239, 3, 133, 2, // Opcode: C_F_D64
+/* 1039 */ MCD_OPC_FilterValue, 49, 21, 0, // Skip to: 1064
+/* 1043 */ MCD_OPC_CheckPredicate, 47, 37, 5, // Skip to: 2364
+/* 1047 */ MCD_OPC_CheckField, 21, 5, 17, 31, 5, // Skip to: 2364
+/* 1053 */ MCD_OPC_CheckField, 6, 5, 0, 25, 5, // Skip to: 2364
+/* 1059 */ MCD_OPC_Decode, 153, 4, 133, 2, // Opcode: C_UN_D64
+/* 1064 */ MCD_OPC_FilterValue, 50, 21, 0, // Skip to: 1089
+/* 1068 */ MCD_OPC_CheckPredicate, 47, 12, 5, // Skip to: 2364
+/* 1072 */ MCD_OPC_CheckField, 21, 5, 17, 6, 5, // Skip to: 2364
+/* 1078 */ MCD_OPC_CheckField, 6, 5, 0, 0, 5, // Skip to: 2364
+/* 1084 */ MCD_OPC_Decode, 236, 3, 133, 2, // Opcode: C_EQ_D64
+/* 1089 */ MCD_OPC_FilterValue, 51, 21, 0, // Skip to: 1114
+/* 1093 */ MCD_OPC_CheckPredicate, 47, 243, 4, // Skip to: 2364
+/* 1097 */ MCD_OPC_CheckField, 21, 5, 17, 237, 4, // Skip to: 2364
+/* 1103 */ MCD_OPC_CheckField, 6, 5, 0, 231, 4, // Skip to: 2364
+/* 1109 */ MCD_OPC_Decode, 144, 4, 133, 2, // Opcode: C_UEQ_D64
+/* 1114 */ MCD_OPC_FilterValue, 52, 21, 0, // Skip to: 1139
+/* 1118 */ MCD_OPC_CheckPredicate, 47, 218, 4, // Skip to: 2364
+/* 1122 */ MCD_OPC_CheckField, 21, 5, 17, 212, 4, // Skip to: 2364
+/* 1128 */ MCD_OPC_CheckField, 6, 5, 0, 206, 4, // Skip to: 2364
+/* 1134 */ MCD_OPC_Decode, 135, 4, 133, 2, // Opcode: C_OLT_D64
+/* 1139 */ MCD_OPC_FilterValue, 53, 21, 0, // Skip to: 1164
+/* 1143 */ MCD_OPC_CheckPredicate, 47, 193, 4, // Skip to: 2364
+/* 1147 */ MCD_OPC_CheckField, 21, 5, 17, 187, 4, // Skip to: 2364
+/* 1153 */ MCD_OPC_CheckField, 6, 5, 0, 181, 4, // Skip to: 2364
+/* 1159 */ MCD_OPC_Decode, 150, 4, 133, 2, // Opcode: C_ULT_D64
+/* 1164 */ MCD_OPC_FilterValue, 54, 21, 0, // Skip to: 1189
+/* 1168 */ MCD_OPC_CheckPredicate, 47, 168, 4, // Skip to: 2364
+/* 1172 */ MCD_OPC_CheckField, 21, 5, 17, 162, 4, // Skip to: 2364
+/* 1178 */ MCD_OPC_CheckField, 6, 5, 0, 156, 4, // Skip to: 2364
+/* 1184 */ MCD_OPC_Decode, 132, 4, 133, 2, // Opcode: C_OLE_D64
+/* 1189 */ MCD_OPC_FilterValue, 55, 21, 0, // Skip to: 1214
+/* 1193 */ MCD_OPC_CheckPredicate, 47, 143, 4, // Skip to: 2364
+/* 1197 */ MCD_OPC_CheckField, 21, 5, 17, 137, 4, // Skip to: 2364
+/* 1203 */ MCD_OPC_CheckField, 6, 5, 0, 131, 4, // Skip to: 2364
+/* 1209 */ MCD_OPC_Decode, 147, 4, 133, 2, // Opcode: C_ULE_D64
+/* 1214 */ MCD_OPC_FilterValue, 56, 21, 0, // Skip to: 1239
+/* 1218 */ MCD_OPC_CheckPredicate, 47, 118, 4, // Skip to: 2364
+/* 1222 */ MCD_OPC_CheckField, 21, 5, 17, 112, 4, // Skip to: 2364
+/* 1228 */ MCD_OPC_CheckField, 6, 5, 0, 106, 4, // Skip to: 2364
+/* 1234 */ MCD_OPC_Decode, 141, 4, 133, 2, // Opcode: C_SF_D64
+/* 1239 */ MCD_OPC_FilterValue, 57, 21, 0, // Skip to: 1264
+/* 1243 */ MCD_OPC_CheckPredicate, 47, 93, 4, // Skip to: 2364
+/* 1247 */ MCD_OPC_CheckField, 21, 5, 17, 87, 4, // Skip to: 2364
+/* 1253 */ MCD_OPC_CheckField, 6, 5, 0, 81, 4, // Skip to: 2364
+/* 1259 */ MCD_OPC_Decode, 251, 3, 133, 2, // Opcode: C_NGLE_D64
+/* 1264 */ MCD_OPC_FilterValue, 58, 21, 0, // Skip to: 1289
+/* 1268 */ MCD_OPC_CheckPredicate, 47, 68, 4, // Skip to: 2364
+/* 1272 */ MCD_OPC_CheckField, 21, 5, 17, 62, 4, // Skip to: 2364
+/* 1278 */ MCD_OPC_CheckField, 6, 5, 0, 56, 4, // Skip to: 2364
+/* 1284 */ MCD_OPC_Decode, 138, 4, 133, 2, // Opcode: C_SEQ_D64
+/* 1289 */ MCD_OPC_FilterValue, 59, 21, 0, // Skip to: 1314
+/* 1293 */ MCD_OPC_CheckPredicate, 47, 43, 4, // Skip to: 2364
+/* 1297 */ MCD_OPC_CheckField, 21, 5, 17, 37, 4, // Skip to: 2364
+/* 1303 */ MCD_OPC_CheckField, 6, 5, 0, 31, 4, // Skip to: 2364
+/* 1309 */ MCD_OPC_Decode, 254, 3, 133, 2, // Opcode: C_NGL_D64
+/* 1314 */ MCD_OPC_FilterValue, 60, 21, 0, // Skip to: 1339
+/* 1318 */ MCD_OPC_CheckPredicate, 47, 18, 4, // Skip to: 2364
+/* 1322 */ MCD_OPC_CheckField, 21, 5, 17, 12, 4, // Skip to: 2364
+/* 1328 */ MCD_OPC_CheckField, 6, 5, 0, 6, 4, // Skip to: 2364
+/* 1334 */ MCD_OPC_Decode, 245, 3, 133, 2, // Opcode: C_LT_D64
+/* 1339 */ MCD_OPC_FilterValue, 61, 21, 0, // Skip to: 1364
+/* 1343 */ MCD_OPC_CheckPredicate, 47, 249, 3, // Skip to: 2364
+/* 1347 */ MCD_OPC_CheckField, 21, 5, 17, 243, 3, // Skip to: 2364
+/* 1353 */ MCD_OPC_CheckField, 6, 5, 0, 237, 3, // Skip to: 2364
+/* 1359 */ MCD_OPC_Decode, 248, 3, 133, 2, // Opcode: C_NGE_D64
+/* 1364 */ MCD_OPC_FilterValue, 62, 21, 0, // Skip to: 1389
+/* 1368 */ MCD_OPC_CheckPredicate, 47, 224, 3, // Skip to: 2364
+/* 1372 */ MCD_OPC_CheckField, 21, 5, 17, 218, 3, // Skip to: 2364
+/* 1378 */ MCD_OPC_CheckField, 6, 5, 0, 212, 3, // Skip to: 2364
+/* 1384 */ MCD_OPC_Decode, 242, 3, 133, 2, // Opcode: C_LE_D64
+/* 1389 */ MCD_OPC_FilterValue, 63, 203, 3, // Skip to: 2364
+/* 1393 */ MCD_OPC_CheckPredicate, 47, 199, 3, // Skip to: 2364
+/* 1397 */ MCD_OPC_CheckField, 21, 5, 17, 193, 3, // Skip to: 2364
+/* 1403 */ MCD_OPC_CheckField, 6, 5, 0, 187, 3, // Skip to: 2364
+/* 1409 */ MCD_OPC_Decode, 129, 4, 133, 2, // Opcode: C_NGT_D64
+/* 1414 */ MCD_OPC_FilterValue, 18, 41, 0, // Skip to: 1459
+/* 1418 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 1421 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 1440
+/* 1425 */ MCD_OPC_CheckPredicate, 42, 167, 3, // Skip to: 2364
+/* 1429 */ MCD_OPC_CheckField, 3, 8, 0, 161, 3, // Skip to: 2364
+/* 1435 */ MCD_OPC_Decode, 198, 4, 255, 1, // Opcode: DMFC2
+/* 1440 */ MCD_OPC_FilterValue, 5, 152, 3, // Skip to: 2364
+/* 1444 */ MCD_OPC_CheckPredicate, 42, 148, 3, // Skip to: 2364
+/* 1448 */ MCD_OPC_CheckField, 3, 8, 0, 142, 3, // Skip to: 2364
+/* 1454 */ MCD_OPC_Decode, 203, 4, 255, 1, // Opcode: DMTC2
+/* 1459 */ MCD_OPC_FilterValue, 19, 131, 0, // Skip to: 1594
+/* 1463 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 1466 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 1485
+/* 1470 */ MCD_OPC_CheckPredicate, 48, 122, 3, // Skip to: 2364
+/* 1474 */ MCD_OPC_CheckField, 11, 5, 0, 116, 3, // Skip to: 2364
+/* 1480 */ MCD_OPC_Decode, 176, 7, 134, 2, // Opcode: LDXC164
+/* 1485 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 1504
+/* 1489 */ MCD_OPC_CheckPredicate, 49, 103, 3, // Skip to: 2364
+/* 1493 */ MCD_OPC_CheckField, 11, 5, 0, 97, 3, // Skip to: 2364
+/* 1499 */ MCD_OPC_Decode, 208, 7, 134, 2, // Opcode: LUXC164
+/* 1504 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 1523
+/* 1508 */ MCD_OPC_CheckPredicate, 48, 84, 3, // Skip to: 2364
+/* 1512 */ MCD_OPC_CheckField, 6, 5, 0, 78, 3, // Skip to: 2364
+/* 1518 */ MCD_OPC_Decode, 167, 11, 135, 2, // Opcode: SDXC164
+/* 1523 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 1542
+/* 1527 */ MCD_OPC_CheckPredicate, 49, 65, 3, // Skip to: 2364
+/* 1531 */ MCD_OPC_CheckField, 6, 5, 0, 59, 3, // Skip to: 2364
+/* 1537 */ MCD_OPC_Decode, 233, 12, 135, 2, // Opcode: SUXC164
+/* 1542 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 1555
+/* 1546 */ MCD_OPC_CheckPredicate, 48, 46, 3, // Skip to: 2364
+/* 1550 */ MCD_OPC_Decode, 144, 8, 136, 2, // Opcode: MADD_D64
+/* 1555 */ MCD_OPC_FilterValue, 41, 9, 0, // Skip to: 1568
+/* 1559 */ MCD_OPC_CheckPredicate, 48, 33, 3, // Skip to: 2364
+/* 1563 */ MCD_OPC_Decode, 162, 9, 136, 2, // Opcode: MSUB_D64
+/* 1568 */ MCD_OPC_FilterValue, 49, 9, 0, // Skip to: 1581
+/* 1572 */ MCD_OPC_CheckPredicate, 48, 20, 3, // Skip to: 2364
+/* 1576 */ MCD_OPC_Decode, 241, 9, 136, 2, // Opcode: NMADD_D64
+/* 1581 */ MCD_OPC_FilterValue, 57, 11, 3, // Skip to: 2364
+/* 1585 */ MCD_OPC_CheckPredicate, 48, 7, 3, // Skip to: 2364
+/* 1589 */ MCD_OPC_Decode, 246, 9, 136, 2, // Opcode: NMSUB_D64
+/* 1594 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 1607
+/* 1598 */ MCD_OPC_CheckPredicate, 41, 250, 2, // Skip to: 2364
+/* 1602 */ MCD_OPC_Decode, 160, 4, 137, 2, // Opcode: DADDi
+/* 1607 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 1620
+/* 1611 */ MCD_OPC_CheckPredicate, 19, 237, 2, // Skip to: 2364
+/* 1615 */ MCD_OPC_Decode, 161, 4, 137, 2, // Opcode: DADDiu
+/* 1620 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 1633
+/* 1624 */ MCD_OPC_CheckPredicate, 41, 224, 2, // Skip to: 2364
+/* 1628 */ MCD_OPC_Decode, 172, 7, 217, 1, // Opcode: LDL
+/* 1633 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 1646
+/* 1637 */ MCD_OPC_CheckPredicate, 41, 211, 2, // Skip to: 2364
+/* 1641 */ MCD_OPC_Decode, 174, 7, 217, 1, // Opcode: LDR
+/* 1646 */ MCD_OPC_FilterValue, 28, 159, 1, // Skip to: 2065
+/* 1650 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 1653 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 1672
+/* 1657 */ MCD_OPC_CheckPredicate, 50, 191, 2, // Skip to: 2364
+/* 1661 */ MCD_OPC_CheckField, 6, 5, 0, 185, 2, // Skip to: 2364
+/* 1667 */ MCD_OPC_Decode, 206, 4, 224, 1, // Opcode: DMUL
+/* 1672 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 1691
+/* 1676 */ MCD_OPC_CheckPredicate, 50, 172, 2, // Skip to: 2364
+/* 1680 */ MCD_OPC_CheckField, 6, 15, 0, 166, 2, // Skip to: 2364
+/* 1686 */ MCD_OPC_Decode, 185, 9, 138, 2, // Opcode: MTM0
+/* 1691 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 1710
+/* 1695 */ MCD_OPC_CheckPredicate, 50, 153, 2, // Skip to: 2364
+/* 1699 */ MCD_OPC_CheckField, 6, 15, 0, 147, 2, // Skip to: 2364
+/* 1705 */ MCD_OPC_Decode, 188, 9, 138, 2, // Opcode: MTP0
+/* 1710 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 1729
+/* 1714 */ MCD_OPC_CheckPredicate, 50, 134, 2, // Skip to: 2364
+/* 1718 */ MCD_OPC_CheckField, 6, 15, 0, 128, 2, // Skip to: 2364
+/* 1724 */ MCD_OPC_Decode, 189, 9, 138, 2, // Opcode: MTP1
+/* 1729 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 1748
+/* 1733 */ MCD_OPC_CheckPredicate, 50, 115, 2, // Skip to: 2364
+/* 1737 */ MCD_OPC_CheckField, 6, 15, 0, 109, 2, // Skip to: 2364
+/* 1743 */ MCD_OPC_Decode, 190, 9, 138, 2, // Opcode: MTP2
+/* 1748 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 1767
+/* 1752 */ MCD_OPC_CheckPredicate, 50, 96, 2, // Skip to: 2364
+/* 1756 */ MCD_OPC_CheckField, 6, 15, 0, 90, 2, // Skip to: 2364
+/* 1762 */ MCD_OPC_Decode, 186, 9, 138, 2, // Opcode: MTM1
+/* 1767 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 1786
+/* 1771 */ MCD_OPC_CheckPredicate, 50, 77, 2, // Skip to: 2364
+/* 1775 */ MCD_OPC_CheckField, 6, 15, 0, 71, 2, // Skip to: 2364
+/* 1781 */ MCD_OPC_Decode, 187, 9, 138, 2, // Opcode: MTM2
+/* 1786 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 1805
+/* 1790 */ MCD_OPC_CheckPredicate, 50, 58, 2, // Skip to: 2364
+/* 1794 */ MCD_OPC_CheckField, 6, 5, 0, 52, 2, // Skip to: 2364
+/* 1800 */ MCD_OPC_Decode, 226, 13, 224, 1, // Opcode: VMULU
+/* 1805 */ MCD_OPC_FilterValue, 16, 15, 0, // Skip to: 1824
+/* 1809 */ MCD_OPC_CheckPredicate, 50, 39, 2, // Skip to: 2364
+/* 1813 */ MCD_OPC_CheckField, 6, 5, 0, 33, 2, // Skip to: 2364
+/* 1819 */ MCD_OPC_Decode, 225, 13, 224, 1, // Opcode: VMM0
+/* 1824 */ MCD_OPC_FilterValue, 17, 15, 0, // Skip to: 1843
+/* 1828 */ MCD_OPC_CheckPredicate, 50, 20, 2, // Skip to: 2364
+/* 1832 */ MCD_OPC_CheckField, 6, 5, 0, 14, 2, // Skip to: 2364
+/* 1838 */ MCD_OPC_Decode, 224, 13, 224, 1, // Opcode: V3MULU
+/* 1843 */ MCD_OPC_FilterValue, 36, 15, 0, // Skip to: 1862
+/* 1847 */ MCD_OPC_CheckPredicate, 51, 1, 2, // Skip to: 2364
+/* 1851 */ MCD_OPC_CheckField, 6, 5, 0, 251, 1, // Skip to: 2364
+/* 1857 */ MCD_OPC_Decode, 170, 4, 139, 2, // Opcode: DCLZ
+/* 1862 */ MCD_OPC_FilterValue, 37, 15, 0, // Skip to: 1881
+/* 1866 */ MCD_OPC_CheckPredicate, 51, 238, 1, // Skip to: 2364
+/* 1870 */ MCD_OPC_CheckField, 6, 5, 0, 232, 1, // Skip to: 2364
+/* 1876 */ MCD_OPC_Decode, 168, 4, 139, 2, // Opcode: DCLO
+/* 1881 */ MCD_OPC_FilterValue, 40, 15, 0, // Skip to: 1900
+/* 1885 */ MCD_OPC_CheckPredicate, 50, 219, 1, // Skip to: 2364
+/* 1889 */ MCD_OPC_CheckField, 6, 5, 0, 213, 1, // Skip to: 2364
+/* 1895 */ MCD_OPC_Decode, 166, 1, 224, 1, // Opcode: BADDu
+/* 1900 */ MCD_OPC_FilterValue, 42, 15, 0, // Skip to: 1919
+/* 1904 */ MCD_OPC_CheckPredicate, 50, 200, 1, // Skip to: 2364
+/* 1908 */ MCD_OPC_CheckField, 6, 5, 0, 194, 1, // Skip to: 2364
+/* 1914 */ MCD_OPC_Decode, 184, 11, 224, 1, // Opcode: SEQ
+/* 1919 */ MCD_OPC_FilterValue, 43, 15, 0, // Skip to: 1938
+/* 1923 */ MCD_OPC_CheckPredicate, 50, 181, 1, // Skip to: 2364
+/* 1927 */ MCD_OPC_CheckField, 6, 5, 0, 175, 1, // Skip to: 2364
+/* 1933 */ MCD_OPC_Decode, 252, 11, 224, 1, // Opcode: SNE
+/* 1938 */ MCD_OPC_FilterValue, 44, 20, 0, // Skip to: 1962
+/* 1942 */ MCD_OPC_CheckPredicate, 50, 162, 1, // Skip to: 2364
+/* 1946 */ MCD_OPC_CheckField, 16, 5, 0, 156, 1, // Skip to: 2364
+/* 1952 */ MCD_OPC_CheckField, 6, 5, 0, 150, 1, // Skip to: 2364
+/* 1958 */ MCD_OPC_Decode, 163, 10, 62, // Opcode: POP
+/* 1962 */ MCD_OPC_FilterValue, 45, 21, 0, // Skip to: 1987
+/* 1966 */ MCD_OPC_CheckPredicate, 50, 138, 1, // Skip to: 2364
+/* 1970 */ MCD_OPC_CheckField, 16, 5, 0, 132, 1, // Skip to: 2364
+/* 1976 */ MCD_OPC_CheckField, 6, 5, 0, 126, 1, // Skip to: 2364
+/* 1982 */ MCD_OPC_Decode, 231, 4, 222, 1, // Opcode: DPOP
+/* 1987 */ MCD_OPC_FilterValue, 46, 9, 0, // Skip to: 2000
+/* 1991 */ MCD_OPC_CheckPredicate, 50, 113, 1, // Skip to: 2364
+/* 1995 */ MCD_OPC_Decode, 185, 11, 140, 2, // Opcode: SEQi
+/* 2000 */ MCD_OPC_FilterValue, 47, 9, 0, // Skip to: 2013
+/* 2004 */ MCD_OPC_CheckPredicate, 50, 100, 1, // Skip to: 2364
+/* 2008 */ MCD_OPC_Decode, 253, 11, 140, 2, // Opcode: SNEi
+/* 2013 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 2026
+/* 2017 */ MCD_OPC_CheckPredicate, 50, 87, 1, // Skip to: 2364
+/* 2021 */ MCD_OPC_Decode, 241, 2, 141, 2, // Opcode: CINS
+/* 2026 */ MCD_OPC_FilterValue, 51, 9, 0, // Skip to: 2039
+/* 2030 */ MCD_OPC_CheckPredicate, 50, 74, 1, // Skip to: 2364
+/* 2034 */ MCD_OPC_Decode, 242, 2, 141, 2, // Opcode: CINS32
+/* 2039 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 2052
+/* 2043 */ MCD_OPC_CheckPredicate, 50, 61, 1, // Skip to: 2364
+/* 2047 */ MCD_OPC_Decode, 158, 5, 141, 2, // Opcode: EXTS
+/* 2052 */ MCD_OPC_FilterValue, 59, 52, 1, // Skip to: 2364
+/* 2056 */ MCD_OPC_CheckPredicate, 50, 48, 1, // Skip to: 2364
+/* 2060 */ MCD_OPC_Decode, 159, 5, 141, 2, // Opcode: EXTS32
+/* 2065 */ MCD_OPC_FilterValue, 31, 126, 0, // Skip to: 2195
+/* 2069 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 2072 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 2085
+/* 2076 */ MCD_OPC_CheckPredicate, 6, 28, 1, // Skip to: 2364
+/* 2080 */ MCD_OPC_Decode, 177, 4, 142, 2, // Opcode: DEXTM
+/* 2085 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 2098
+/* 2089 */ MCD_OPC_CheckPredicate, 6, 15, 1, // Skip to: 2364
+/* 2093 */ MCD_OPC_Decode, 178, 4, 142, 2, // Opcode: DEXTU
+/* 2098 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 2111
+/* 2102 */ MCD_OPC_CheckPredicate, 6, 2, 1, // Skip to: 2364
+/* 2106 */ MCD_OPC_Decode, 176, 4, 142, 2, // Opcode: DEXT
+/* 2111 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 2124
+/* 2115 */ MCD_OPC_CheckPredicate, 6, 245, 0, // Skip to: 2364
+/* 2119 */ MCD_OPC_Decode, 181, 4, 143, 2, // Opcode: DINSM
+/* 2124 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 2137
+/* 2128 */ MCD_OPC_CheckPredicate, 6, 232, 0, // Skip to: 2364
+/* 2132 */ MCD_OPC_Decode, 182, 4, 143, 2, // Opcode: DINSU
+/* 2137 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 2150
+/* 2141 */ MCD_OPC_CheckPredicate, 6, 219, 0, // Skip to: 2364
+/* 2145 */ MCD_OPC_Decode, 180, 4, 143, 2, // Opcode: DINS
+/* 2150 */ MCD_OPC_FilterValue, 36, 210, 0, // Skip to: 2364
+/* 2154 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 2157 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 2176
+/* 2161 */ MCD_OPC_CheckPredicate, 40, 199, 0, // Skip to: 2364
+/* 2165 */ MCD_OPC_CheckField, 21, 5, 0, 193, 0, // Skip to: 2364
+/* 2171 */ MCD_OPC_Decode, 249, 4, 243, 1, // Opcode: DSBH
+/* 2176 */ MCD_OPC_FilterValue, 5, 184, 0, // Skip to: 2364
+/* 2180 */ MCD_OPC_CheckPredicate, 40, 180, 0, // Skip to: 2364
+/* 2184 */ MCD_OPC_CheckField, 21, 5, 0, 174, 0, // Skip to: 2364
+/* 2190 */ MCD_OPC_Decode, 251, 4, 243, 1, // Opcode: DSHD
+/* 2195 */ MCD_OPC_FilterValue, 39, 9, 0, // Skip to: 2208
+/* 2199 */ MCD_OPC_CheckPredicate, 19, 161, 0, // Skip to: 2364
+/* 2203 */ MCD_OPC_Decode, 241, 7, 217, 1, // Opcode: LWu
+/* 2208 */ MCD_OPC_FilterValue, 44, 9, 0, // Skip to: 2221
+/* 2212 */ MCD_OPC_CheckPredicate, 41, 148, 0, // Skip to: 2364
+/* 2216 */ MCD_OPC_Decode, 164, 11, 217, 1, // Opcode: SDL
+/* 2221 */ MCD_OPC_FilterValue, 45, 9, 0, // Skip to: 2234
+/* 2225 */ MCD_OPC_CheckPredicate, 41, 135, 0, // Skip to: 2364
+/* 2229 */ MCD_OPC_Decode, 165, 11, 217, 1, // Opcode: SDR
+/* 2234 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 2247
+/* 2238 */ MCD_OPC_CheckPredicate, 50, 122, 0, // Skip to: 2364
+/* 2242 */ MCD_OPC_Decode, 171, 1, 144, 2, // Opcode: BBIT0
+/* 2247 */ MCD_OPC_FilterValue, 52, 9, 0, // Skip to: 2260
+/* 2251 */ MCD_OPC_CheckPredicate, 41, 109, 0, // Skip to: 2364
+/* 2255 */ MCD_OPC_Decode, 194, 7, 217, 1, // Opcode: LLD
+/* 2260 */ MCD_OPC_FilterValue, 53, 9, 0, // Skip to: 2273
+/* 2264 */ MCD_OPC_CheckPredicate, 52, 96, 0, // Skip to: 2364
+/* 2268 */ MCD_OPC_Decode, 163, 7, 219, 1, // Opcode: LDC164
+/* 2273 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 2286
+/* 2277 */ MCD_OPC_CheckPredicate, 50, 83, 0, // Skip to: 2364
+/* 2281 */ MCD_OPC_Decode, 172, 1, 144, 2, // Opcode: BBIT032
+/* 2286 */ MCD_OPC_FilterValue, 55, 9, 0, // Skip to: 2299
+/* 2290 */ MCD_OPC_CheckPredicate, 19, 70, 0, // Skip to: 2364
+/* 2294 */ MCD_OPC_Decode, 161, 7, 217, 1, // Opcode: LD
+/* 2299 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 2312
+/* 2303 */ MCD_OPC_CheckPredicate, 50, 57, 0, // Skip to: 2364
+/* 2307 */ MCD_OPC_Decode, 173, 1, 144, 2, // Opcode: BBIT1
+/* 2312 */ MCD_OPC_FilterValue, 60, 9, 0, // Skip to: 2325
+/* 2316 */ MCD_OPC_CheckPredicate, 41, 44, 0, // Skip to: 2364
+/* 2320 */ MCD_OPC_Decode, 147, 11, 217, 1, // Opcode: SCD
+/* 2325 */ MCD_OPC_FilterValue, 61, 9, 0, // Skip to: 2338
+/* 2329 */ MCD_OPC_CheckPredicate, 52, 31, 0, // Skip to: 2364
+/* 2333 */ MCD_OPC_Decode, 157, 11, 219, 1, // Opcode: SDC164
+/* 2338 */ MCD_OPC_FilterValue, 62, 9, 0, // Skip to: 2351
+/* 2342 */ MCD_OPC_CheckPredicate, 50, 18, 0, // Skip to: 2364
+/* 2346 */ MCD_OPC_Decode, 174, 1, 144, 2, // Opcode: BBIT132
+/* 2351 */ MCD_OPC_FilterValue, 63, 9, 0, // Skip to: 2364
+/* 2355 */ MCD_OPC_CheckPredicate, 19, 5, 0, // Skip to: 2364
+/* 2359 */ MCD_OPC_Decode, 151, 11, 217, 1, // Opcode: SD
+/* 2364 */ MCD_OPC_Fail,
+ 0
+};
+
+static bool getbool(uint64_t b)
+{
+ return b != 0;
+}
+
+static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits)
+{
+ switch (Idx) {
+ default: // llvm_unreachable("Invalid index!");
+ case 0:
+ return getbool((Bits & Mips_FeatureMips16));
+ case 1:
+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMicroMips));
+ case 2:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMicroMips));
+ case 3:
+ return getbool((Bits & Mips_FeatureMicroMips));
+ case 4:
+ return getbool((Bits & Mips_FeatureMips32) && (Bits & Mips_FeatureMicroMips));
+ case 5:
+ return getbool(!(Bits & Mips_FeatureMips16));
+ case 6:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2));
+ case 7:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6));
+ case 8:
+ return getbool((Bits & Mips_FeatureMSA));
+ case 9:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6));
+ case 10:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32));
+ case 11:
+ return getbool(!(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips));
+ case 12:
+ return getbool((Bits & Mips_FeatureDSP));
+ case 13:
+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6));
+ case 14:
+ return getbool((Bits & Mips_FeatureMSA) && (Bits & Mips_FeatureMips64));
+ case 15:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2));
+ case 16:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6));
+ case 17:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32));
+ case 18:
+ return getbool(!(Bits & Mips_FeatureMicroMips));
+ case 19:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3));
+ case 20:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2) && !(Bits & Mips_FeatureFP64Bit));
+ case 21:
+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit));
+ case 22:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32r2));
+ case 23:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureFP64Bit));
+ case 24:
+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6));
+ case 25:
+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureFP64Bit));
+ case 26:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6));
+ case 27:
+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips));
+ case 28:
+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips5_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6));
+ case 29:
+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6));
+ case 30:
+ return getbool((Bits & Mips_FeatureDSPR2));
+ case 31:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6));
+ case 32:
+ return getbool((Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips));
+ case 33:
+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips));
+ case 34:
+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips2));
+ case 35:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips));
+ case 36:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r6));
+ case 37:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64r6));
+ case 38:
+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureGP64Bit) && (Bits & Mips_FeatureMips32r6));
+ case 39:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureGP64Bit) && (Bits & Mips_FeatureMips32r6));
+ case 40:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64r2));
+ case 41:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6));
+ case 42:
+ return getbool((Bits & Mips_FeatureMips64));
+ case 43:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2) && (Bits & Mips_FeatureFP64Bit));
+ case 44:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit));
+ case 45:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && (Bits & Mips_FeatureFP64Bit));
+ case 46:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6));
+ case 47:
+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && (Bits & Mips_FeatureFP64Bit));
+ case 48:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6));
+ case 49:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips5_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6));
+ case 50:
+ return getbool((Bits & Mips_FeatureCnMips));
+ case 51:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64) && !(Bits & Mips_FeatureMips64r6));
+ case 52:
+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips2));
+ }
+}
+
+#define DecodeToMCInst(fname,fieldname, InsnType) \
+static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \
+ uint64_t Address, void *Decoder) \
+{ \
+ InsnType tmp; \
+ switch (Idx) { \
+ default: \
+ case 0: \
+ return S; \
+ case 1: \
+ tmp = fieldname(insn, 8, 3); \
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 2: \
+ tmp = fieldname(insn, 8, 3); \
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 8, 3); \
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 3: \
+ tmp = 0; \
+ tmp |= fieldname(insn, 3, 2) << 3; \
+ tmp |= fieldname(insn, 5, 3) << 0; \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 3); \
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 4: \
+ tmp = fieldname(insn, 0, 4); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 5: \
+ tmp = fieldname(insn, 2, 3); \
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 8, 3); \
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 5, 3); \
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 6: \
+ tmp = fieldname(insn, 8, 3); \
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 5, 3); \
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 7: \
+ tmp = fieldname(insn, 8, 3); \
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 8, 3); \
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 5, 3); \
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 8: \
+ tmp = 0; \
+ tmp |= fieldname(insn, 0, 5) << 0; \
+ tmp |= fieldname(insn, 16, 5) << 11; \
+ tmp |= fieldname(insn, 21, 6) << 5; \
+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 9: \
+ tmp = fieldname(insn, 5, 3); \
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 10: \
+ if (DecodeFMem3(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 11: \
+ tmp = fieldname(insn, 7, 3); \
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 1, 3); \
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 4, 3); \
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 12: \
+ if (DecodeMemMMImm4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 13: \
+ tmp = fieldname(insn, 5, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 14: \
+ tmp = fieldname(insn, 7, 3); \
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 4, 3); \
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 1, 3); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 15: \
+ tmp = fieldname(insn, 7, 3); \
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 4, 3); \
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 4); \
+ if (DecodeANDI16Imm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 16: \
+ tmp = fieldname(insn, 3, 3); \
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 3); \
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 17: \
+ tmp = fieldname(insn, 3, 3); \
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 3); \
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 3, 3); \
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 18: \
+ if (DecodeMemMMReglistImm4Lsl2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 19: \
+ tmp = fieldname(insn, 0, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 20: \
+ tmp = fieldname(insn, 0, 4); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 21: \
+ tmp = fieldname(insn, 0, 5); \
+ if (DecodeUImm5lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 22: \
+ if (DecodeMemMMSPImm5Lsl2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 23: \
+ tmp = fieldname(insn, 5, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 5, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 1, 4); \
+ if (DecodeSimm4(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 24: \
+ tmp = fieldname(insn, 1, 9); \
+ if (DecodeSimm9SP(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 25: \
+ if (DecodeMemMMGPImm7Lsl2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 26: \
+ tmp = fieldname(insn, 7, 3); \
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 4, 3); \
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 1, 3); \
+ if (DecodeAddiur2Simm7(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 27: \
+ tmp = fieldname(insn, 7, 3); \
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 1, 6); \
+ if (DecodeUImm6Lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 28: \
+ tmp = fieldname(insn, 7, 3); \
+ if (DecodeMovePRegPair(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 1, 3); \
+ if (DecodeGPRMM16MovePRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 4, 3); \
+ if (DecodeGPRMM16MovePRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 29: \
+ tmp = fieldname(insn, 7, 3); \
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 7); \
+ if (DecodeBranchTarget7MM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 30: \
+ tmp = fieldname(insn, 0, 10); \
+ if (DecodeBranchTarget10MM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 31: \
+ tmp = fieldname(insn, 7, 3); \
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 7); \
+ if (DecodeLiSimm7(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 32: \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 33: \
+ tmp = fieldname(insn, 16, 10); \
+ MCOperand_CreateImm0(MI, tmp); \
+ tmp = fieldname(insn, 6, 10); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 34: \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ MCOperand_CreateImm0(MI, tmp); \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 35: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 36: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 37: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 38: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 39: \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ MCOperand_CreateImm0(MI, tmp); \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 40: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 12, 4); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 41: \
+ tmp = fieldname(insn, 16, 10); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 42: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 43: \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 44: \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 45: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 46: \
+ tmp = fieldname(insn, 16, 5); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 47: \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 16); \
+ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 48: \
+ if (DecodeMemMMImm16(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 49: \
+ if (DecodeMemMMImm12(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 50: \
+ if (DecodeCacheOpMM(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 51: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 16); \
+ if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 52: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 16); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 53: \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 16); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 54: \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 13, 3); \
+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 55: \
+ if (DecodeJumpTargetMM(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 56: \
+ tmp = fieldname(insn, 23, 3); \
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 23); \
+ if (DecodeSimm23Lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 57: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 16); \
+ if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 58: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 59: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 18, 3); \
+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 60: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 2); \
+ if (DecodeLSAImm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 61: \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 62: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 63: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 64: \
+ tmp = fieldname(insn, 6, 20); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 65: \
+ tmp = fieldname(insn, 6, 5); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 66: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 67: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 2); \
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 68: \
+ tmp = fieldname(insn, 11, 2); \
+ if (DecodeHI32DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 69: \
+ tmp = fieldname(insn, 11, 2); \
+ if (DecodeLO32DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 70: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 2); \
+ if (DecodeLSAImm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 71: \
+ tmp = fieldname(insn, 11, 2); \
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 72: \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 10); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 73: \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 16); \
+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 74: \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 16); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 75: \
+ tmp = fieldname(insn, 0, 16); \
+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 76: \
+ if (DecodeSyncI(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 77: \
+ if (DecodeJumpTarget(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 78: \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 16); \
+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 79: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 16); \
+ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 80: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 16); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 81: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 3); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 82: \
+ tmp = fieldname(insn, 18, 3); \
+ if (DecodeCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 16); \
+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 83: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 84: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 85: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 86: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 87: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 88: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 89: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 90: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 91: \
+ tmp = fieldname(insn, 18, 3); \
+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 16); \
+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 92: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 16); \
+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 93: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 94: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 95: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 18, 3); \
+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 96: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 97: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 98: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 99: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 100: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 101: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 102: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 103: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 18, 3); \
+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 104: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 105: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 106: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 107: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 16); \
+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 108: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 16); \
+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 109: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 16); \
+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 110: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 111: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 112: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 113: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 114: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 115: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 116: \
+ tmp = fieldname(insn, 11, 2); \
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 2); \
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 117: \
+ tmp = 0; \
+ tmp |= fieldname(insn, 11, 5) << 0; \
+ tmp |= fieldname(insn, 16, 5) << 0; \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 118: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 8); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 119: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 8); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 120: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 8); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 121: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 8); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 122: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 123: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 124: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 125: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 126: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 10); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 127: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 10); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 128: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 10); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 129: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 10); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 130: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 6); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 131: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 4); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 132: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 3); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 133: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 6); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 134: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 135: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 4); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 136: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 3); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 137: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 138: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 139: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 140: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 141: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 142: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 143: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 144: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 145: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 146: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 147: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 148: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 149: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 150: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 151: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 152: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 153: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 154: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 155: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 156: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 157: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 158: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 159: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 4); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 160: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 3); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 161: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 2); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 162: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 1); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 163: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 164: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 4); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 165: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 3); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 166: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 2); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 167: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 1); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 168: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 169: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 4); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 170: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 3); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 171: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 2); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 172: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 1); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 173: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 174: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 4); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 175: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 3); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 176: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 2); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 177: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 1); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 178: \
+ if (DecodeINSVE_DF_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 179: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 180: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 181: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 182: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 183: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 184: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 185: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 186: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 187: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 188: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 189: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 190: \
+ if (DecodeMSA128Mem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 191: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ MCOperand_CreateImm0(MI, tmp); \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 192: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ MCOperand_CreateImm0(MI, tmp); \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 193: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 194: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 195: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 196: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 197: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 198: \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 199: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 200: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ MCOperand_CreateImm0(MI, tmp); \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 201: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 202: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 10); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 203: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 204: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 205: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 206: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 207: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 208: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 209: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ MCOperand_CreateImm0(MI, tmp); \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 210: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 2); \
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 211: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 2); \
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 212: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 10); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 213: \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 10); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 214: \
+ tmp = fieldname(insn, 11, 2); \
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 20, 6); \
+ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 2); \
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 215: \
+ tmp = fieldname(insn, 11, 2); \
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 2); \
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 216: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 217: \
+ if (DecodeMem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 218: \
+ if (DecodeCacheOp(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 219: \
+ if (DecodeFMem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 220: \
+ if (DecodeFMem2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 221: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 2); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 222: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 223: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 2); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 224: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 225: \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 16); \
+ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 226: \
+ if (DecodeBlezGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 227: \
+ if (DecodeBgtzGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 228: \
+ if (DecodeAddiGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 229: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 16); \
+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 230: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 231: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 232: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 233: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 234: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 235: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 236: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 237: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 16); \
+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 238: \
+ if (DecodeFMemCop2R6(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 239: \
+ if (DecodeBlezlGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 240: \
+ if (DecodeBgtzlGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 241: \
+ if (DecodeDaddiGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 242: \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 16); \
+ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 243: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 244: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 3); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 245: \
+ if (DecodeCacheOpR6(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 246: \
+ if (DecodeSpecial3LlSc(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 247: \
+ tmp = fieldname(insn, 0, 26); \
+ if (DecodeBranchTarget26(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 248: \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 21); \
+ if (DecodeBranchTarget21(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 249: \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 19); \
+ if (DecodeSimm19Lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 250: \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 18); \
+ if (DecodeSimm18Lsl3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 251: \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 16); \
+ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 252: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 253: \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 254: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 255: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 3); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 256: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 257: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 258: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 259: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 18, 3); \
+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 260: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 261: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 262: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 263: \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 264: \
+ tmp = fieldname(insn, 6, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 265: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 0, 16); \
+ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 266: \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 267: \
+ tmp = 0; \
+ tmp |= fieldname(insn, 11, 5) << 0; \
+ tmp |= fieldname(insn, 16, 5) << 0; \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 268: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 10); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 269: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ MCOperand_CreateImm0(MI, tmp); \
+ tmp = fieldname(insn, 11, 5); \
+ MCOperand_CreateImm0(MI, tmp); \
+ return S; \
+ case 270: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ MCOperand_CreateImm0(MI, tmp); \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 271: \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 6, 5); \
+ MCOperand_CreateImm0(MI, tmp); \
+ tmp = fieldname(insn, 11, 5); \
+ if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ case 272: \
+ tmp = fieldname(insn, 21, 5); \
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ tmp = fieldname(insn, 16, 5); \
+ MCOperand_CreateImm0(MI, tmp); \
+ tmp = fieldname(insn, 0, 16); \
+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+ return S; \
+ } \
+}
+
+#define DecodeInstruction(fname, fieldname, decoder, InsnType) \
+static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
+ InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \
+{ \
+ uint64_t Bits = getFeatureBits(feature); \
+ const uint8_t *Ptr = DecodeTable; \
+ uint32_t CurFieldValue = 0, ExpectedValue; \
+ DecodeStatus S = MCDisassembler_Success; \
+ unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
+ InsnType Val, FieldValue, PositiveMask, NegativeMask; \
+ bool Pred, Fail; \
+ for (;;) { \
+ switch (*Ptr) { \
+ default: \
+ return MCDisassembler_Fail; \
+ case MCD_OPC_ExtractField: { \
+ Start = *++Ptr; \
+ Len = *++Ptr; \
+ ++Ptr; \
+ CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \
+ break; \
+ } \
+ case MCD_OPC_FilterValue: { \
+ Val = (InsnType)decodeULEB128(++Ptr, &Len); \
+ Ptr += Len; \
+ NumToSkip = *Ptr++; \
+ NumToSkip |= (*Ptr++) << 8; \
+ if (Val != CurFieldValue) \
+ Ptr += NumToSkip; \
+ break; \
+ } \
+ case MCD_OPC_CheckField: { \
+ Start = *++Ptr; \
+ Len = *++Ptr; \
+ FieldValue = fieldname(insn, Start, Len); \
+ ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \
+ Ptr += Len; \
+ NumToSkip = *Ptr++; \
+ NumToSkip |= (*Ptr++) << 8; \
+ if (ExpectedValue != FieldValue) \
+ Ptr += NumToSkip; \
+ break; \
+ } \
+ case MCD_OPC_CheckPredicate: { \
+ PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \
+ Ptr += Len; \
+ NumToSkip = *Ptr++; \
+ NumToSkip |= (*Ptr++) << 8; \
+ Pred = checkDecoderPredicate(PIdx, Bits); \
+ if (!Pred) \
+ Ptr += NumToSkip; \
+ (void)Pred; \
+ break; \
+ } \
+ case MCD_OPC_Decode: { \
+ Opc = (unsigned)decodeULEB128(++Ptr, &Len); \
+ Ptr += Len; \
+ DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \
+ Ptr += Len; \
+ MCInst_setOpcode(MI, Opc); \
+ return decoder(S, DecodeIdx, insn, MI, Address, MRI); \
+ } \
+ case MCD_OPC_SoftFail: { \
+ PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \
+ Ptr += Len; \
+ NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \
+ Ptr += Len; \
+ Fail = (insn & PositiveMask) || (~insn & NegativeMask); \
+ if (Fail) \
+ S = MCDisassembler_SoftFail; \
+ break; \
+ } \
+ case MCD_OPC_Fail: { \
+ return MCDisassembler_Fail; \
+ } \
+ } \
+ } \
+}
+
+FieldFromInstruction(fieldFromInstruction, uint32_t)
+DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t)
+DecodeInstruction(decodeInstruction, fieldFromInstruction, decodeToMCInst, uint32_t)
diff --git a/capstone/arch/Mips/MipsGenInstrInfo.inc b/capstone/arch/Mips/MipsGenInstrInfo.inc
new file mode 100644
index 000000000..b6e8983ed
--- /dev/null
+++ b/capstone/arch/Mips/MipsGenInstrInfo.inc
@@ -0,0 +1,1805 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|*Target Instruction Enum Values *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+
+#ifdef GET_INSTRINFO_ENUM
+#undef GET_INSTRINFO_ENUM
+
+enum {
+ Mips_PHI = 0,
+ Mips_INLINEASM = 1,
+ Mips_CFI_INSTRUCTION = 2,
+ Mips_EH_LABEL = 3,
+ Mips_GC_LABEL = 4,
+ Mips_KILL = 5,
+ Mips_EXTRACT_SUBREG = 6,
+ Mips_INSERT_SUBREG = 7,
+ Mips_IMPLICIT_DEF = 8,
+ Mips_SUBREG_TO_REG = 9,
+ Mips_COPY_TO_REGCLASS = 10,
+ Mips_DBG_VALUE = 11,
+ Mips_REG_SEQUENCE = 12,
+ Mips_COPY = 13,
+ Mips_BUNDLE = 14,
+ Mips_LIFETIME_START = 15,
+ Mips_LIFETIME_END = 16,
+ Mips_STACKMAP = 17,
+ Mips_PATCHPOINT = 18,
+ Mips_LOAD_STACK_GUARD = 19,
+ Mips_STATEPOINT = 20,
+ Mips_FRAME_ALLOC = 21,
+ Mips_ABSQ_S_PH = 22,
+ Mips_ABSQ_S_QB = 23,
+ Mips_ABSQ_S_W = 24,
+ Mips_ADD = 25,
+ Mips_ADDIUPC = 26,
+ Mips_ADDIUPC_MM = 27,
+ Mips_ADDIUR1SP_MM = 28,
+ Mips_ADDIUR2_MM = 29,
+ Mips_ADDIUS5_MM = 30,
+ Mips_ADDIUSP_MM = 31,
+ Mips_ADDQH_PH = 32,
+ Mips_ADDQH_R_PH = 33,
+ Mips_ADDQH_R_W = 34,
+ Mips_ADDQH_W = 35,
+ Mips_ADDQ_PH = 36,
+ Mips_ADDQ_S_PH = 37,
+ Mips_ADDQ_S_W = 38,
+ Mips_ADDSC = 39,
+ Mips_ADDS_A_B = 40,
+ Mips_ADDS_A_D = 41,
+ Mips_ADDS_A_H = 42,
+ Mips_ADDS_A_W = 43,
+ Mips_ADDS_S_B = 44,
+ Mips_ADDS_S_D = 45,
+ Mips_ADDS_S_H = 46,
+ Mips_ADDS_S_W = 47,
+ Mips_ADDS_U_B = 48,
+ Mips_ADDS_U_D = 49,
+ Mips_ADDS_U_H = 50,
+ Mips_ADDS_U_W = 51,
+ Mips_ADDU16_MM = 52,
+ Mips_ADDUH_QB = 53,
+ Mips_ADDUH_R_QB = 54,
+ Mips_ADDU_PH = 55,
+ Mips_ADDU_QB = 56,
+ Mips_ADDU_S_PH = 57,
+ Mips_ADDU_S_QB = 58,
+ Mips_ADDVI_B = 59,
+ Mips_ADDVI_D = 60,
+ Mips_ADDVI_H = 61,
+ Mips_ADDVI_W = 62,
+ Mips_ADDV_B = 63,
+ Mips_ADDV_D = 64,
+ Mips_ADDV_H = 65,
+ Mips_ADDV_W = 66,
+ Mips_ADDWC = 67,
+ Mips_ADD_A_B = 68,
+ Mips_ADD_A_D = 69,
+ Mips_ADD_A_H = 70,
+ Mips_ADD_A_W = 71,
+ Mips_ADD_MM = 72,
+ Mips_ADDi = 73,
+ Mips_ADDi_MM = 74,
+ Mips_ADDiu = 75,
+ Mips_ADDiu_MM = 76,
+ Mips_ADDu = 77,
+ Mips_ADDu_MM = 78,
+ Mips_ADJCALLSTACKDOWN = 79,
+ Mips_ADJCALLSTACKUP = 80,
+ Mips_ALIGN = 81,
+ Mips_ALUIPC = 82,
+ Mips_AND = 83,
+ Mips_AND16_MM = 84,
+ Mips_AND64 = 85,
+ Mips_ANDI16_MM = 86,
+ Mips_ANDI_B = 87,
+ Mips_AND_MM = 88,
+ Mips_AND_V = 89,
+ Mips_AND_V_D_PSEUDO = 90,
+ Mips_AND_V_H_PSEUDO = 91,
+ Mips_AND_V_W_PSEUDO = 92,
+ Mips_ANDi = 93,
+ Mips_ANDi64 = 94,
+ Mips_ANDi_MM = 95,
+ Mips_APPEND = 96,
+ Mips_ASUB_S_B = 97,
+ Mips_ASUB_S_D = 98,
+ Mips_ASUB_S_H = 99,
+ Mips_ASUB_S_W = 100,
+ Mips_ASUB_U_B = 101,
+ Mips_ASUB_U_D = 102,
+ Mips_ASUB_U_H = 103,
+ Mips_ASUB_U_W = 104,
+ Mips_ATOMIC_CMP_SWAP_I16 = 105,
+ Mips_ATOMIC_CMP_SWAP_I32 = 106,
+ Mips_ATOMIC_CMP_SWAP_I64 = 107,
+ Mips_ATOMIC_CMP_SWAP_I8 = 108,
+ Mips_ATOMIC_LOAD_ADD_I16 = 109,
+ Mips_ATOMIC_LOAD_ADD_I32 = 110,
+ Mips_ATOMIC_LOAD_ADD_I64 = 111,
+ Mips_ATOMIC_LOAD_ADD_I8 = 112,
+ Mips_ATOMIC_LOAD_AND_I16 = 113,
+ Mips_ATOMIC_LOAD_AND_I32 = 114,
+ Mips_ATOMIC_LOAD_AND_I64 = 115,
+ Mips_ATOMIC_LOAD_AND_I8 = 116,
+ Mips_ATOMIC_LOAD_NAND_I16 = 117,
+ Mips_ATOMIC_LOAD_NAND_I32 = 118,
+ Mips_ATOMIC_LOAD_NAND_I64 = 119,
+ Mips_ATOMIC_LOAD_NAND_I8 = 120,
+ Mips_ATOMIC_LOAD_OR_I16 = 121,
+ Mips_ATOMIC_LOAD_OR_I32 = 122,
+ Mips_ATOMIC_LOAD_OR_I64 = 123,
+ Mips_ATOMIC_LOAD_OR_I8 = 124,
+ Mips_ATOMIC_LOAD_SUB_I16 = 125,
+ Mips_ATOMIC_LOAD_SUB_I32 = 126,
+ Mips_ATOMIC_LOAD_SUB_I64 = 127,
+ Mips_ATOMIC_LOAD_SUB_I8 = 128,
+ Mips_ATOMIC_LOAD_XOR_I16 = 129,
+ Mips_ATOMIC_LOAD_XOR_I32 = 130,
+ Mips_ATOMIC_LOAD_XOR_I64 = 131,
+ Mips_ATOMIC_LOAD_XOR_I8 = 132,
+ Mips_ATOMIC_SWAP_I16 = 133,
+ Mips_ATOMIC_SWAP_I32 = 134,
+ Mips_ATOMIC_SWAP_I64 = 135,
+ Mips_ATOMIC_SWAP_I8 = 136,
+ Mips_AUI = 137,
+ Mips_AUIPC = 138,
+ Mips_AVER_S_B = 139,
+ Mips_AVER_S_D = 140,
+ Mips_AVER_S_H = 141,
+ Mips_AVER_S_W = 142,
+ Mips_AVER_U_B = 143,
+ Mips_AVER_U_D = 144,
+ Mips_AVER_U_H = 145,
+ Mips_AVER_U_W = 146,
+ Mips_AVE_S_B = 147,
+ Mips_AVE_S_D = 148,
+ Mips_AVE_S_H = 149,
+ Mips_AVE_S_W = 150,
+ Mips_AVE_U_B = 151,
+ Mips_AVE_U_D = 152,
+ Mips_AVE_U_H = 153,
+ Mips_AVE_U_W = 154,
+ Mips_AddiuRxImmX16 = 155,
+ Mips_AddiuRxPcImmX16 = 156,
+ Mips_AddiuRxRxImm16 = 157,
+ Mips_AddiuRxRxImmX16 = 158,
+ Mips_AddiuRxRyOffMemX16 = 159,
+ Mips_AddiuSpImm16 = 160,
+ Mips_AddiuSpImmX16 = 161,
+ Mips_AdduRxRyRz16 = 162,
+ Mips_AndRxRxRy16 = 163,
+ Mips_B = 164,
+ Mips_B16_MM = 165,
+ Mips_BADDu = 166,
+ Mips_BAL = 167,
+ Mips_BALC = 168,
+ Mips_BALIGN = 169,
+ Mips_BAL_BR = 170,
+ Mips_BBIT0 = 171,
+ Mips_BBIT032 = 172,
+ Mips_BBIT1 = 173,
+ Mips_BBIT132 = 174,
+ Mips_BC = 175,
+ Mips_BC0F = 176,
+ Mips_BC0FL = 177,
+ Mips_BC0T = 178,
+ Mips_BC0TL = 179,
+ Mips_BC1EQZ = 180,
+ Mips_BC1F = 181,
+ Mips_BC1FL = 182,
+ Mips_BC1F_MM = 183,
+ Mips_BC1NEZ = 184,
+ Mips_BC1T = 185,
+ Mips_BC1TL = 186,
+ Mips_BC1T_MM = 187,
+ Mips_BC2EQZ = 188,
+ Mips_BC2F = 189,
+ Mips_BC2FL = 190,
+ Mips_BC2NEZ = 191,
+ Mips_BC2T = 192,
+ Mips_BC2TL = 193,
+ Mips_BC3F = 194,
+ Mips_BC3FL = 195,
+ Mips_BC3T = 196,
+ Mips_BC3TL = 197,
+ Mips_BCLRI_B = 198,
+ Mips_BCLRI_D = 199,
+ Mips_BCLRI_H = 200,
+ Mips_BCLRI_W = 201,
+ Mips_BCLR_B = 202,
+ Mips_BCLR_D = 203,
+ Mips_BCLR_H = 204,
+ Mips_BCLR_W = 205,
+ Mips_BEQ = 206,
+ Mips_BEQ64 = 207,
+ Mips_BEQC = 208,
+ Mips_BEQL = 209,
+ Mips_BEQZ16_MM = 210,
+ Mips_BEQZALC = 211,
+ Mips_BEQZC = 212,
+ Mips_BEQZC_MM = 213,
+ Mips_BEQ_MM = 214,
+ Mips_BGEC = 215,
+ Mips_BGEUC = 216,
+ Mips_BGEZ = 217,
+ Mips_BGEZ64 = 218,
+ Mips_BGEZAL = 219,
+ Mips_BGEZALC = 220,
+ Mips_BGEZALL = 221,
+ Mips_BGEZALS_MM = 222,
+ Mips_BGEZAL_MM = 223,
+ Mips_BGEZC = 224,
+ Mips_BGEZL = 225,
+ Mips_BGEZ_MM = 226,
+ Mips_BGTZ = 227,
+ Mips_BGTZ64 = 228,
+ Mips_BGTZALC = 229,
+ Mips_BGTZC = 230,
+ Mips_BGTZL = 231,
+ Mips_BGTZ_MM = 232,
+ Mips_BINSLI_B = 233,
+ Mips_BINSLI_D = 234,
+ Mips_BINSLI_H = 235,
+ Mips_BINSLI_W = 236,
+ Mips_BINSL_B = 237,
+ Mips_BINSL_D = 238,
+ Mips_BINSL_H = 239,
+ Mips_BINSL_W = 240,
+ Mips_BINSRI_B = 241,
+ Mips_BINSRI_D = 242,
+ Mips_BINSRI_H = 243,
+ Mips_BINSRI_W = 244,
+ Mips_BINSR_B = 245,
+ Mips_BINSR_D = 246,
+ Mips_BINSR_H = 247,
+ Mips_BINSR_W = 248,
+ Mips_BITREV = 249,
+ Mips_BITSWAP = 250,
+ Mips_BLEZ = 251,
+ Mips_BLEZ64 = 252,
+ Mips_BLEZALC = 253,
+ Mips_BLEZC = 254,
+ Mips_BLEZL = 255,
+ Mips_BLEZ_MM = 256,
+ Mips_BLTC = 257,
+ Mips_BLTUC = 258,
+ Mips_BLTZ = 259,
+ Mips_BLTZ64 = 260,
+ Mips_BLTZAL = 261,
+ Mips_BLTZALC = 262,
+ Mips_BLTZALL = 263,
+ Mips_BLTZALS_MM = 264,
+ Mips_BLTZAL_MM = 265,
+ Mips_BLTZC = 266,
+ Mips_BLTZL = 267,
+ Mips_BLTZ_MM = 268,
+ Mips_BMNZI_B = 269,
+ Mips_BMNZ_V = 270,
+ Mips_BMZI_B = 271,
+ Mips_BMZ_V = 272,
+ Mips_BNE = 273,
+ Mips_BNE64 = 274,
+ Mips_BNEC = 275,
+ Mips_BNEGI_B = 276,
+ Mips_BNEGI_D = 277,
+ Mips_BNEGI_H = 278,
+ Mips_BNEGI_W = 279,
+ Mips_BNEG_B = 280,
+ Mips_BNEG_D = 281,
+ Mips_BNEG_H = 282,
+ Mips_BNEG_W = 283,
+ Mips_BNEL = 284,
+ Mips_BNEZ16_MM = 285,
+ Mips_BNEZALC = 286,
+ Mips_BNEZC = 287,
+ Mips_BNEZC_MM = 288,
+ Mips_BNE_MM = 289,
+ Mips_BNVC = 290,
+ Mips_BNZ_B = 291,
+ Mips_BNZ_D = 292,
+ Mips_BNZ_H = 293,
+ Mips_BNZ_V = 294,
+ Mips_BNZ_W = 295,
+ Mips_BOVC = 296,
+ Mips_BPOSGE32 = 297,
+ Mips_BPOSGE32_PSEUDO = 298,
+ Mips_BREAK = 299,
+ Mips_BREAK16_MM = 300,
+ Mips_BREAK_MM = 301,
+ Mips_BSELI_B = 302,
+ Mips_BSEL_D_PSEUDO = 303,
+ Mips_BSEL_FD_PSEUDO = 304,
+ Mips_BSEL_FW_PSEUDO = 305,
+ Mips_BSEL_H_PSEUDO = 306,
+ Mips_BSEL_V = 307,
+ Mips_BSEL_W_PSEUDO = 308,
+ Mips_BSETI_B = 309,
+ Mips_BSETI_D = 310,
+ Mips_BSETI_H = 311,
+ Mips_BSETI_W = 312,
+ Mips_BSET_B = 313,
+ Mips_BSET_D = 314,
+ Mips_BSET_H = 315,
+ Mips_BSET_W = 316,
+ Mips_BZ_B = 317,
+ Mips_BZ_D = 318,
+ Mips_BZ_H = 319,
+ Mips_BZ_V = 320,
+ Mips_BZ_W = 321,
+ Mips_B_MM_Pseudo = 322,
+ Mips_BeqzRxImm16 = 323,
+ Mips_BeqzRxImmX16 = 324,
+ Mips_Bimm16 = 325,
+ Mips_BimmX16 = 326,
+ Mips_BnezRxImm16 = 327,
+ Mips_BnezRxImmX16 = 328,
+ Mips_Break16 = 329,
+ Mips_Bteqz16 = 330,
+ Mips_BteqzT8CmpX16 = 331,
+ Mips_BteqzT8CmpiX16 = 332,
+ Mips_BteqzT8SltX16 = 333,
+ Mips_BteqzT8SltiX16 = 334,
+ Mips_BteqzT8SltiuX16 = 335,
+ Mips_BteqzT8SltuX16 = 336,
+ Mips_BteqzX16 = 337,
+ Mips_Btnez16 = 338,
+ Mips_BtnezT8CmpX16 = 339,
+ Mips_BtnezT8CmpiX16 = 340,
+ Mips_BtnezT8SltX16 = 341,
+ Mips_BtnezT8SltiX16 = 342,
+ Mips_BtnezT8SltiuX16 = 343,
+ Mips_BtnezT8SltuX16 = 344,
+ Mips_BtnezX16 = 345,
+ Mips_BuildPairF64 = 346,
+ Mips_BuildPairF64_64 = 347,
+ Mips_CACHE = 348,
+ Mips_CACHE_MM = 349,
+ Mips_CACHE_R6 = 350,
+ Mips_CEIL_L_D64 = 351,
+ Mips_CEIL_L_S = 352,
+ Mips_CEIL_W_D32 = 353,
+ Mips_CEIL_W_D64 = 354,
+ Mips_CEIL_W_MM = 355,
+ Mips_CEIL_W_S = 356,
+ Mips_CEIL_W_S_MM = 357,
+ Mips_CEQI_B = 358,
+ Mips_CEQI_D = 359,
+ Mips_CEQI_H = 360,
+ Mips_CEQI_W = 361,
+ Mips_CEQ_B = 362,
+ Mips_CEQ_D = 363,
+ Mips_CEQ_H = 364,
+ Mips_CEQ_W = 365,
+ Mips_CFC1 = 366,
+ Mips_CFC1_MM = 367,
+ Mips_CFCMSA = 368,
+ Mips_CINS = 369,
+ Mips_CINS32 = 370,
+ Mips_CLASS_D = 371,
+ Mips_CLASS_S = 372,
+ Mips_CLEI_S_B = 373,
+ Mips_CLEI_S_D = 374,
+ Mips_CLEI_S_H = 375,
+ Mips_CLEI_S_W = 376,
+ Mips_CLEI_U_B = 377,
+ Mips_CLEI_U_D = 378,
+ Mips_CLEI_U_H = 379,
+ Mips_CLEI_U_W = 380,
+ Mips_CLE_S_B = 381,
+ Mips_CLE_S_D = 382,
+ Mips_CLE_S_H = 383,
+ Mips_CLE_S_W = 384,
+ Mips_CLE_U_B = 385,
+ Mips_CLE_U_D = 386,
+ Mips_CLE_U_H = 387,
+ Mips_CLE_U_W = 388,
+ Mips_CLO = 389,
+ Mips_CLO_MM = 390,
+ Mips_CLO_R6 = 391,
+ Mips_CLTI_S_B = 392,
+ Mips_CLTI_S_D = 393,
+ Mips_CLTI_S_H = 394,
+ Mips_CLTI_S_W = 395,
+ Mips_CLTI_U_B = 396,
+ Mips_CLTI_U_D = 397,
+ Mips_CLTI_U_H = 398,
+ Mips_CLTI_U_W = 399,
+ Mips_CLT_S_B = 400,
+ Mips_CLT_S_D = 401,
+ Mips_CLT_S_H = 402,
+ Mips_CLT_S_W = 403,
+ Mips_CLT_U_B = 404,
+ Mips_CLT_U_D = 405,
+ Mips_CLT_U_H = 406,
+ Mips_CLT_U_W = 407,
+ Mips_CLZ = 408,
+ Mips_CLZ_MM = 409,
+ Mips_CLZ_R6 = 410,
+ Mips_CMPGDU_EQ_QB = 411,
+ Mips_CMPGDU_LE_QB = 412,
+ Mips_CMPGDU_LT_QB = 413,
+ Mips_CMPGU_EQ_QB = 414,
+ Mips_CMPGU_LE_QB = 415,
+ Mips_CMPGU_LT_QB = 416,
+ Mips_CMPU_EQ_QB = 417,
+ Mips_CMPU_LE_QB = 418,
+ Mips_CMPU_LT_QB = 419,
+ Mips_CMP_EQ_D = 420,
+ Mips_CMP_EQ_PH = 421,
+ Mips_CMP_EQ_S = 422,
+ Mips_CMP_F_D = 423,
+ Mips_CMP_F_S = 424,
+ Mips_CMP_LE_D = 425,
+ Mips_CMP_LE_PH = 426,
+ Mips_CMP_LE_S = 427,
+ Mips_CMP_LT_D = 428,
+ Mips_CMP_LT_PH = 429,
+ Mips_CMP_LT_S = 430,
+ Mips_CMP_SAF_D = 431,
+ Mips_CMP_SAF_S = 432,
+ Mips_CMP_SEQ_D = 433,
+ Mips_CMP_SEQ_S = 434,
+ Mips_CMP_SLE_D = 435,
+ Mips_CMP_SLE_S = 436,
+ Mips_CMP_SLT_D = 437,
+ Mips_CMP_SLT_S = 438,
+ Mips_CMP_SUEQ_D = 439,
+ Mips_CMP_SUEQ_S = 440,
+ Mips_CMP_SULE_D = 441,
+ Mips_CMP_SULE_S = 442,
+ Mips_CMP_SULT_D = 443,
+ Mips_CMP_SULT_S = 444,
+ Mips_CMP_SUN_D = 445,
+ Mips_CMP_SUN_S = 446,
+ Mips_CMP_UEQ_D = 447,
+ Mips_CMP_UEQ_S = 448,
+ Mips_CMP_ULE_D = 449,
+ Mips_CMP_ULE_S = 450,
+ Mips_CMP_ULT_D = 451,
+ Mips_CMP_ULT_S = 452,
+ Mips_CMP_UN_D = 453,
+ Mips_CMP_UN_S = 454,
+ Mips_CONSTPOOL_ENTRY = 455,
+ Mips_COPY_FD_PSEUDO = 456,
+ Mips_COPY_FW_PSEUDO = 457,
+ Mips_COPY_S_B = 458,
+ Mips_COPY_S_D = 459,
+ Mips_COPY_S_H = 460,
+ Mips_COPY_S_W = 461,
+ Mips_COPY_U_B = 462,
+ Mips_COPY_U_D = 463,
+ Mips_COPY_U_H = 464,
+ Mips_COPY_U_W = 465,
+ Mips_CTC1 = 466,
+ Mips_CTC1_MM = 467,
+ Mips_CTCMSA = 468,
+ Mips_CVT_D32_S = 469,
+ Mips_CVT_D32_W = 470,
+ Mips_CVT_D32_W_MM = 471,
+ Mips_CVT_D64_L = 472,
+ Mips_CVT_D64_S = 473,
+ Mips_CVT_D64_W = 474,
+ Mips_CVT_D_S_MM = 475,
+ Mips_CVT_L_D64 = 476,
+ Mips_CVT_L_D64_MM = 477,
+ Mips_CVT_L_S = 478,
+ Mips_CVT_L_S_MM = 479,
+ Mips_CVT_S_D32 = 480,
+ Mips_CVT_S_D32_MM = 481,
+ Mips_CVT_S_D64 = 482,
+ Mips_CVT_S_L = 483,
+ Mips_CVT_S_W = 484,
+ Mips_CVT_S_W_MM = 485,
+ Mips_CVT_W_D32 = 486,
+ Mips_CVT_W_D64 = 487,
+ Mips_CVT_W_MM = 488,
+ Mips_CVT_W_S = 489,
+ Mips_CVT_W_S_MM = 490,
+ Mips_C_EQ_D32 = 491,
+ Mips_C_EQ_D64 = 492,
+ Mips_C_EQ_S = 493,
+ Mips_C_F_D32 = 494,
+ Mips_C_F_D64 = 495,
+ Mips_C_F_S = 496,
+ Mips_C_LE_D32 = 497,
+ Mips_C_LE_D64 = 498,
+ Mips_C_LE_S = 499,
+ Mips_C_LT_D32 = 500,
+ Mips_C_LT_D64 = 501,
+ Mips_C_LT_S = 502,
+ Mips_C_NGE_D32 = 503,
+ Mips_C_NGE_D64 = 504,
+ Mips_C_NGE_S = 505,
+ Mips_C_NGLE_D32 = 506,
+ Mips_C_NGLE_D64 = 507,
+ Mips_C_NGLE_S = 508,
+ Mips_C_NGL_D32 = 509,
+ Mips_C_NGL_D64 = 510,
+ Mips_C_NGL_S = 511,
+ Mips_C_NGT_D32 = 512,
+ Mips_C_NGT_D64 = 513,
+ Mips_C_NGT_S = 514,
+ Mips_C_OLE_D32 = 515,
+ Mips_C_OLE_D64 = 516,
+ Mips_C_OLE_S = 517,
+ Mips_C_OLT_D32 = 518,
+ Mips_C_OLT_D64 = 519,
+ Mips_C_OLT_S = 520,
+ Mips_C_SEQ_D32 = 521,
+ Mips_C_SEQ_D64 = 522,
+ Mips_C_SEQ_S = 523,
+ Mips_C_SF_D32 = 524,
+ Mips_C_SF_D64 = 525,
+ Mips_C_SF_S = 526,
+ Mips_C_UEQ_D32 = 527,
+ Mips_C_UEQ_D64 = 528,
+ Mips_C_UEQ_S = 529,
+ Mips_C_ULE_D32 = 530,
+ Mips_C_ULE_D64 = 531,
+ Mips_C_ULE_S = 532,
+ Mips_C_ULT_D32 = 533,
+ Mips_C_ULT_D64 = 534,
+ Mips_C_ULT_S = 535,
+ Mips_C_UN_D32 = 536,
+ Mips_C_UN_D64 = 537,
+ Mips_C_UN_S = 538,
+ Mips_CmpRxRy16 = 539,
+ Mips_CmpiRxImm16 = 540,
+ Mips_CmpiRxImmX16 = 541,
+ Mips_Constant32 = 542,
+ Mips_DADD = 543,
+ Mips_DADDi = 544,
+ Mips_DADDiu = 545,
+ Mips_DADDu = 546,
+ Mips_DAHI = 547,
+ Mips_DALIGN = 548,
+ Mips_DATI = 549,
+ Mips_DAUI = 550,
+ Mips_DBITSWAP = 551,
+ Mips_DCLO = 552,
+ Mips_DCLO_R6 = 553,
+ Mips_DCLZ = 554,
+ Mips_DCLZ_R6 = 555,
+ Mips_DDIV = 556,
+ Mips_DDIVU = 557,
+ Mips_DERET = 558,
+ Mips_DERET_MM = 559,
+ Mips_DEXT = 560,
+ Mips_DEXTM = 561,
+ Mips_DEXTU = 562,
+ Mips_DI = 563,
+ Mips_DINS = 564,
+ Mips_DINSM = 565,
+ Mips_DINSU = 566,
+ Mips_DIV = 567,
+ Mips_DIVU = 568,
+ Mips_DIV_S_B = 569,
+ Mips_DIV_S_D = 570,
+ Mips_DIV_S_H = 571,
+ Mips_DIV_S_W = 572,
+ Mips_DIV_U_B = 573,
+ Mips_DIV_U_D = 574,
+ Mips_DIV_U_H = 575,
+ Mips_DIV_U_W = 576,
+ Mips_DI_MM = 577,
+ Mips_DLSA = 578,
+ Mips_DLSA_R6 = 579,
+ Mips_DMFC0 = 580,
+ Mips_DMFC1 = 581,
+ Mips_DMFC2 = 582,
+ Mips_DMOD = 583,
+ Mips_DMODU = 584,
+ Mips_DMTC0 = 585,
+ Mips_DMTC1 = 586,
+ Mips_DMTC2 = 587,
+ Mips_DMUH = 588,
+ Mips_DMUHU = 589,
+ Mips_DMUL = 590,
+ Mips_DMULT = 591,
+ Mips_DMULTu = 592,
+ Mips_DMULU = 593,
+ Mips_DMUL_R6 = 594,
+ Mips_DOTP_S_D = 595,
+ Mips_DOTP_S_H = 596,
+ Mips_DOTP_S_W = 597,
+ Mips_DOTP_U_D = 598,
+ Mips_DOTP_U_H = 599,
+ Mips_DOTP_U_W = 600,
+ Mips_DPADD_S_D = 601,
+ Mips_DPADD_S_H = 602,
+ Mips_DPADD_S_W = 603,
+ Mips_DPADD_U_D = 604,
+ Mips_DPADD_U_H = 605,
+ Mips_DPADD_U_W = 606,
+ Mips_DPAQX_SA_W_PH = 607,
+ Mips_DPAQX_S_W_PH = 608,
+ Mips_DPAQ_SA_L_W = 609,
+ Mips_DPAQ_S_W_PH = 610,
+ Mips_DPAU_H_QBL = 611,
+ Mips_DPAU_H_QBR = 612,
+ Mips_DPAX_W_PH = 613,
+ Mips_DPA_W_PH = 614,
+ Mips_DPOP = 615,
+ Mips_DPSQX_SA_W_PH = 616,
+ Mips_DPSQX_S_W_PH = 617,
+ Mips_DPSQ_SA_L_W = 618,
+ Mips_DPSQ_S_W_PH = 619,
+ Mips_DPSUB_S_D = 620,
+ Mips_DPSUB_S_H = 621,
+ Mips_DPSUB_S_W = 622,
+ Mips_DPSUB_U_D = 623,
+ Mips_DPSUB_U_H = 624,
+ Mips_DPSUB_U_W = 625,
+ Mips_DPSU_H_QBL = 626,
+ Mips_DPSU_H_QBR = 627,
+ Mips_DPSX_W_PH = 628,
+ Mips_DPS_W_PH = 629,
+ Mips_DROTR = 630,
+ Mips_DROTR32 = 631,
+ Mips_DROTRV = 632,
+ Mips_DSBH = 633,
+ Mips_DSDIV = 634,
+ Mips_DSHD = 635,
+ Mips_DSLL = 636,
+ Mips_DSLL32 = 637,
+ Mips_DSLL64_32 = 638,
+ Mips_DSLLV = 639,
+ Mips_DSRA = 640,
+ Mips_DSRA32 = 641,
+ Mips_DSRAV = 642,
+ Mips_DSRL = 643,
+ Mips_DSRL32 = 644,
+ Mips_DSRLV = 645,
+ Mips_DSUB = 646,
+ Mips_DSUBu = 647,
+ Mips_DUDIV = 648,
+ Mips_DivRxRy16 = 649,
+ Mips_DivuRxRy16 = 650,
+ Mips_EHB = 651,
+ Mips_EHB_MM = 652,
+ Mips_EI = 653,
+ Mips_EI_MM = 654,
+ Mips_ERET = 655,
+ Mips_ERET_MM = 656,
+ Mips_EXT = 657,
+ Mips_EXTP = 658,
+ Mips_EXTPDP = 659,
+ Mips_EXTPDPV = 660,
+ Mips_EXTPV = 661,
+ Mips_EXTRV_RS_W = 662,
+ Mips_EXTRV_R_W = 663,
+ Mips_EXTRV_S_H = 664,
+ Mips_EXTRV_W = 665,
+ Mips_EXTR_RS_W = 666,
+ Mips_EXTR_R_W = 667,
+ Mips_EXTR_S_H = 668,
+ Mips_EXTR_W = 669,
+ Mips_EXTS = 670,
+ Mips_EXTS32 = 671,
+ Mips_EXT_MM = 672,
+ Mips_ExtractElementF64 = 673,
+ Mips_ExtractElementF64_64 = 674,
+ Mips_FABS_D = 675,
+ Mips_FABS_D32 = 676,
+ Mips_FABS_D64 = 677,
+ Mips_FABS_MM = 678,
+ Mips_FABS_S = 679,
+ Mips_FABS_S_MM = 680,
+ Mips_FABS_W = 681,
+ Mips_FADD_D = 682,
+ Mips_FADD_D32 = 683,
+ Mips_FADD_D64 = 684,
+ Mips_FADD_MM = 685,
+ Mips_FADD_S = 686,
+ Mips_FADD_S_MM = 687,
+ Mips_FADD_W = 688,
+ Mips_FCAF_D = 689,
+ Mips_FCAF_W = 690,
+ Mips_FCEQ_D = 691,
+ Mips_FCEQ_W = 692,
+ Mips_FCLASS_D = 693,
+ Mips_FCLASS_W = 694,
+ Mips_FCLE_D = 695,
+ Mips_FCLE_W = 696,
+ Mips_FCLT_D = 697,
+ Mips_FCLT_W = 698,
+ Mips_FCMP_D32 = 699,
+ Mips_FCMP_D32_MM = 700,
+ Mips_FCMP_D64 = 701,
+ Mips_FCMP_S32 = 702,
+ Mips_FCMP_S32_MM = 703,
+ Mips_FCNE_D = 704,
+ Mips_FCNE_W = 705,
+ Mips_FCOR_D = 706,
+ Mips_FCOR_W = 707,
+ Mips_FCUEQ_D = 708,
+ Mips_FCUEQ_W = 709,
+ Mips_FCULE_D = 710,
+ Mips_FCULE_W = 711,
+ Mips_FCULT_D = 712,
+ Mips_FCULT_W = 713,
+ Mips_FCUNE_D = 714,
+ Mips_FCUNE_W = 715,
+ Mips_FCUN_D = 716,
+ Mips_FCUN_W = 717,
+ Mips_FDIV_D = 718,
+ Mips_FDIV_D32 = 719,
+ Mips_FDIV_D64 = 720,
+ Mips_FDIV_MM = 721,
+ Mips_FDIV_S = 722,
+ Mips_FDIV_S_MM = 723,
+ Mips_FDIV_W = 724,
+ Mips_FEXDO_H = 725,
+ Mips_FEXDO_W = 726,
+ Mips_FEXP2_D = 727,
+ Mips_FEXP2_D_1_PSEUDO = 728,
+ Mips_FEXP2_W = 729,
+ Mips_FEXP2_W_1_PSEUDO = 730,
+ Mips_FEXUPL_D = 731,
+ Mips_FEXUPL_W = 732,
+ Mips_FEXUPR_D = 733,
+ Mips_FEXUPR_W = 734,
+ Mips_FFINT_S_D = 735,
+ Mips_FFINT_S_W = 736,
+ Mips_FFINT_U_D = 737,
+ Mips_FFINT_U_W = 738,
+ Mips_FFQL_D = 739,
+ Mips_FFQL_W = 740,
+ Mips_FFQR_D = 741,
+ Mips_FFQR_W = 742,
+ Mips_FILL_B = 743,
+ Mips_FILL_D = 744,
+ Mips_FILL_FD_PSEUDO = 745,
+ Mips_FILL_FW_PSEUDO = 746,
+ Mips_FILL_H = 747,
+ Mips_FILL_W = 748,
+ Mips_FLOG2_D = 749,
+ Mips_FLOG2_W = 750,
+ Mips_FLOOR_L_D64 = 751,
+ Mips_FLOOR_L_S = 752,
+ Mips_FLOOR_W_D32 = 753,
+ Mips_FLOOR_W_D64 = 754,
+ Mips_FLOOR_W_MM = 755,
+ Mips_FLOOR_W_S = 756,
+ Mips_FLOOR_W_S_MM = 757,
+ Mips_FMADD_D = 758,
+ Mips_FMADD_W = 759,
+ Mips_FMAX_A_D = 760,
+ Mips_FMAX_A_W = 761,
+ Mips_FMAX_D = 762,
+ Mips_FMAX_W = 763,
+ Mips_FMIN_A_D = 764,
+ Mips_FMIN_A_W = 765,
+ Mips_FMIN_D = 766,
+ Mips_FMIN_W = 767,
+ Mips_FMOV_D32 = 768,
+ Mips_FMOV_D32_MM = 769,
+ Mips_FMOV_D64 = 770,
+ Mips_FMOV_S = 771,
+ Mips_FMOV_S_MM = 772,
+ Mips_FMSUB_D = 773,
+ Mips_FMSUB_W = 774,
+ Mips_FMUL_D = 775,
+ Mips_FMUL_D32 = 776,
+ Mips_FMUL_D64 = 777,
+ Mips_FMUL_MM = 778,
+ Mips_FMUL_S = 779,
+ Mips_FMUL_S_MM = 780,
+ Mips_FMUL_W = 781,
+ Mips_FNEG_D32 = 782,
+ Mips_FNEG_D64 = 783,
+ Mips_FNEG_MM = 784,
+ Mips_FNEG_S = 785,
+ Mips_FNEG_S_MM = 786,
+ Mips_FRCP_D = 787,
+ Mips_FRCP_W = 788,
+ Mips_FRINT_D = 789,
+ Mips_FRINT_W = 790,
+ Mips_FRSQRT_D = 791,
+ Mips_FRSQRT_W = 792,
+ Mips_FSAF_D = 793,
+ Mips_FSAF_W = 794,
+ Mips_FSEQ_D = 795,
+ Mips_FSEQ_W = 796,
+ Mips_FSLE_D = 797,
+ Mips_FSLE_W = 798,
+ Mips_FSLT_D = 799,
+ Mips_FSLT_W = 800,
+ Mips_FSNE_D = 801,
+ Mips_FSNE_W = 802,
+ Mips_FSOR_D = 803,
+ Mips_FSOR_W = 804,
+ Mips_FSQRT_D = 805,
+ Mips_FSQRT_D32 = 806,
+ Mips_FSQRT_D64 = 807,
+ Mips_FSQRT_MM = 808,
+ Mips_FSQRT_S = 809,
+ Mips_FSQRT_S_MM = 810,
+ Mips_FSQRT_W = 811,
+ Mips_FSUB_D = 812,
+ Mips_FSUB_D32 = 813,
+ Mips_FSUB_D64 = 814,
+ Mips_FSUB_MM = 815,
+ Mips_FSUB_S = 816,
+ Mips_FSUB_S_MM = 817,
+ Mips_FSUB_W = 818,
+ Mips_FSUEQ_D = 819,
+ Mips_FSUEQ_W = 820,
+ Mips_FSULE_D = 821,
+ Mips_FSULE_W = 822,
+ Mips_FSULT_D = 823,
+ Mips_FSULT_W = 824,
+ Mips_FSUNE_D = 825,
+ Mips_FSUNE_W = 826,
+ Mips_FSUN_D = 827,
+ Mips_FSUN_W = 828,
+ Mips_FTINT_S_D = 829,
+ Mips_FTINT_S_W = 830,
+ Mips_FTINT_U_D = 831,
+ Mips_FTINT_U_W = 832,
+ Mips_FTQ_H = 833,
+ Mips_FTQ_W = 834,
+ Mips_FTRUNC_S_D = 835,
+ Mips_FTRUNC_S_W = 836,
+ Mips_FTRUNC_U_D = 837,
+ Mips_FTRUNC_U_W = 838,
+ Mips_GotPrologue16 = 839,
+ Mips_HADD_S_D = 840,
+ Mips_HADD_S_H = 841,
+ Mips_HADD_S_W = 842,
+ Mips_HADD_U_D = 843,
+ Mips_HADD_U_H = 844,
+ Mips_HADD_U_W = 845,
+ Mips_HSUB_S_D = 846,
+ Mips_HSUB_S_H = 847,
+ Mips_HSUB_S_W = 848,
+ Mips_HSUB_U_D = 849,
+ Mips_HSUB_U_H = 850,
+ Mips_HSUB_U_W = 851,
+ Mips_ILVEV_B = 852,
+ Mips_ILVEV_D = 853,
+ Mips_ILVEV_H = 854,
+ Mips_ILVEV_W = 855,
+ Mips_ILVL_B = 856,
+ Mips_ILVL_D = 857,
+ Mips_ILVL_H = 858,
+ Mips_ILVL_W = 859,
+ Mips_ILVOD_B = 860,
+ Mips_ILVOD_D = 861,
+ Mips_ILVOD_H = 862,
+ Mips_ILVOD_W = 863,
+ Mips_ILVR_B = 864,
+ Mips_ILVR_D = 865,
+ Mips_ILVR_H = 866,
+ Mips_ILVR_W = 867,
+ Mips_INS = 868,
+ Mips_INSERT_B = 869,
+ Mips_INSERT_B_VIDX_PSEUDO = 870,
+ Mips_INSERT_D = 871,
+ Mips_INSERT_D_VIDX_PSEUDO = 872,
+ Mips_INSERT_FD_PSEUDO = 873,
+ Mips_INSERT_FD_VIDX_PSEUDO = 874,
+ Mips_INSERT_FW_PSEUDO = 875,
+ Mips_INSERT_FW_VIDX_PSEUDO = 876,
+ Mips_INSERT_H = 877,
+ Mips_INSERT_H_VIDX_PSEUDO = 878,
+ Mips_INSERT_W = 879,
+ Mips_INSERT_W_VIDX_PSEUDO = 880,
+ Mips_INSV = 881,
+ Mips_INSVE_B = 882,
+ Mips_INSVE_D = 883,
+ Mips_INSVE_H = 884,
+ Mips_INSVE_W = 885,
+ Mips_INS_MM = 886,
+ Mips_J = 887,
+ Mips_JAL = 888,
+ Mips_JALR = 889,
+ Mips_JALR16_MM = 890,
+ Mips_JALR64 = 891,
+ Mips_JALR64Pseudo = 892,
+ Mips_JALRPseudo = 893,
+ Mips_JALRS16_MM = 894,
+ Mips_JALRS_MM = 895,
+ Mips_JALR_HB = 896,
+ Mips_JALR_MM = 897,
+ Mips_JALS_MM = 898,
+ Mips_JALX = 899,
+ Mips_JALX_MM = 900,
+ Mips_JAL_MM = 901,
+ Mips_JIALC = 902,
+ Mips_JIC = 903,
+ Mips_JR = 904,
+ Mips_JR16_MM = 905,
+ Mips_JR64 = 906,
+ Mips_JRADDIUSP = 907,
+ Mips_JRC16_MM = 908,
+ Mips_JR_HB = 909,
+ Mips_JR_HB_R6 = 910,
+ Mips_JR_MM = 911,
+ Mips_J_MM = 912,
+ Mips_Jal16 = 913,
+ Mips_JalB16 = 914,
+ Mips_JalOneReg = 915,
+ Mips_JalTwoReg = 916,
+ Mips_JrRa16 = 917,
+ Mips_JrcRa16 = 918,
+ Mips_JrcRx16 = 919,
+ Mips_JumpLinkReg16 = 920,
+ Mips_LB = 921,
+ Mips_LB64 = 922,
+ Mips_LBU16_MM = 923,
+ Mips_LBUX = 924,
+ Mips_LB_MM = 925,
+ Mips_LBu = 926,
+ Mips_LBu64 = 927,
+ Mips_LBu_MM = 928,
+ Mips_LD = 929,
+ Mips_LDC1 = 930,
+ Mips_LDC164 = 931,
+ Mips_LDC1_MM = 932,
+ Mips_LDC2 = 933,
+ Mips_LDC2_R6 = 934,
+ Mips_LDC3 = 935,
+ Mips_LDI_B = 936,
+ Mips_LDI_D = 937,
+ Mips_LDI_H = 938,
+ Mips_LDI_W = 939,
+ Mips_LDL = 940,
+ Mips_LDPC = 941,
+ Mips_LDR = 942,
+ Mips_LDXC1 = 943,
+ Mips_LDXC164 = 944,
+ Mips_LD_B = 945,
+ Mips_LD_D = 946,
+ Mips_LD_H = 947,
+ Mips_LD_W = 948,
+ Mips_LEA_ADDiu = 949,
+ Mips_LEA_ADDiu64 = 950,
+ Mips_LEA_ADDiu_MM = 951,
+ Mips_LH = 952,
+ Mips_LH64 = 953,
+ Mips_LHU16_MM = 954,
+ Mips_LHX = 955,
+ Mips_LH_MM = 956,
+ Mips_LHu = 957,
+ Mips_LHu64 = 958,
+ Mips_LHu_MM = 959,
+ Mips_LI16_MM = 960,
+ Mips_LL = 961,
+ Mips_LLD = 962,
+ Mips_LLD_R6 = 963,
+ Mips_LL_MM = 964,
+ Mips_LL_R6 = 965,
+ Mips_LOAD_ACC128 = 966,
+ Mips_LOAD_ACC64 = 967,
+ Mips_LOAD_ACC64DSP = 968,
+ Mips_LOAD_CCOND_DSP = 969,
+ Mips_LONG_BRANCH_ADDiu = 970,
+ Mips_LONG_BRANCH_DADDiu = 971,
+ Mips_LONG_BRANCH_LUi = 972,
+ Mips_LSA = 973,
+ Mips_LSA_R6 = 974,
+ Mips_LUXC1 = 975,
+ Mips_LUXC164 = 976,
+ Mips_LUXC1_MM = 977,
+ Mips_LUi = 978,
+ Mips_LUi64 = 979,
+ Mips_LUi_MM = 980,
+ Mips_LW = 981,
+ Mips_LW16_MM = 982,
+ Mips_LW64 = 983,
+ Mips_LWC1 = 984,
+ Mips_LWC1_MM = 985,
+ Mips_LWC2 = 986,
+ Mips_LWC2_R6 = 987,
+ Mips_LWC3 = 988,
+ Mips_LWGP_MM = 989,
+ Mips_LWL = 990,
+ Mips_LWL64 = 991,
+ Mips_LWL_MM = 992,
+ Mips_LWM16_MM = 993,
+ Mips_LWM32_MM = 994,
+ Mips_LWM_MM = 995,
+ Mips_LWPC = 996,
+ Mips_LWP_MM = 997,
+ Mips_LWR = 998,
+ Mips_LWR64 = 999,
+ Mips_LWR_MM = 1000,
+ Mips_LWSP_MM = 1001,
+ Mips_LWUPC = 1002,
+ Mips_LWU_MM = 1003,
+ Mips_LWX = 1004,
+ Mips_LWXC1 = 1005,
+ Mips_LWXC1_MM = 1006,
+ Mips_LWXS_MM = 1007,
+ Mips_LW_MM = 1008,
+ Mips_LWu = 1009,
+ Mips_LbRxRyOffMemX16 = 1010,
+ Mips_LbuRxRyOffMemX16 = 1011,
+ Mips_LhRxRyOffMemX16 = 1012,
+ Mips_LhuRxRyOffMemX16 = 1013,
+ Mips_LiRxImm16 = 1014,
+ Mips_LiRxImmAlignX16 = 1015,
+ Mips_LiRxImmX16 = 1016,
+ Mips_LoadAddr32Imm = 1017,
+ Mips_LoadAddr32Reg = 1018,
+ Mips_LoadImm32Reg = 1019,
+ Mips_LoadImm64Reg = 1020,
+ Mips_LwConstant32 = 1021,
+ Mips_LwRxPcTcp16 = 1022,
+ Mips_LwRxPcTcpX16 = 1023,
+ Mips_LwRxRyOffMemX16 = 1024,
+ Mips_LwRxSpImmX16 = 1025,
+ Mips_MADD = 1026,
+ Mips_MADDF_D = 1027,
+ Mips_MADDF_S = 1028,
+ Mips_MADDR_Q_H = 1029,
+ Mips_MADDR_Q_W = 1030,
+ Mips_MADDU = 1031,
+ Mips_MADDU_DSP = 1032,
+ Mips_MADDU_MM = 1033,
+ Mips_MADDV_B = 1034,
+ Mips_MADDV_D = 1035,
+ Mips_MADDV_H = 1036,
+ Mips_MADDV_W = 1037,
+ Mips_MADD_D32 = 1038,
+ Mips_MADD_D32_MM = 1039,
+ Mips_MADD_D64 = 1040,
+ Mips_MADD_DSP = 1041,
+ Mips_MADD_MM = 1042,
+ Mips_MADD_Q_H = 1043,
+ Mips_MADD_Q_W = 1044,
+ Mips_MADD_S = 1045,
+ Mips_MADD_S_MM = 1046,
+ Mips_MAQ_SA_W_PHL = 1047,
+ Mips_MAQ_SA_W_PHR = 1048,
+ Mips_MAQ_S_W_PHL = 1049,
+ Mips_MAQ_S_W_PHR = 1050,
+ Mips_MAXA_D = 1051,
+ Mips_MAXA_S = 1052,
+ Mips_MAXI_S_B = 1053,
+ Mips_MAXI_S_D = 1054,
+ Mips_MAXI_S_H = 1055,
+ Mips_MAXI_S_W = 1056,
+ Mips_MAXI_U_B = 1057,
+ Mips_MAXI_U_D = 1058,
+ Mips_MAXI_U_H = 1059,
+ Mips_MAXI_U_W = 1060,
+ Mips_MAX_A_B = 1061,
+ Mips_MAX_A_D = 1062,
+ Mips_MAX_A_H = 1063,
+ Mips_MAX_A_W = 1064,
+ Mips_MAX_D = 1065,
+ Mips_MAX_S = 1066,
+ Mips_MAX_S_B = 1067,
+ Mips_MAX_S_D = 1068,
+ Mips_MAX_S_H = 1069,
+ Mips_MAX_S_W = 1070,
+ Mips_MAX_U_B = 1071,
+ Mips_MAX_U_D = 1072,
+ Mips_MAX_U_H = 1073,
+ Mips_MAX_U_W = 1074,
+ Mips_MFC0 = 1075,
+ Mips_MFC1 = 1076,
+ Mips_MFC1_MM = 1077,
+ Mips_MFC2 = 1078,
+ Mips_MFHC1_D32 = 1079,
+ Mips_MFHC1_D64 = 1080,
+ Mips_MFHC1_MM = 1081,
+ Mips_MFHI = 1082,
+ Mips_MFHI16_MM = 1083,
+ Mips_MFHI64 = 1084,
+ Mips_MFHI_DSP = 1085,
+ Mips_MFHI_MM = 1086,
+ Mips_MFLO = 1087,
+ Mips_MFLO16_MM = 1088,
+ Mips_MFLO64 = 1089,
+ Mips_MFLO_DSP = 1090,
+ Mips_MFLO_MM = 1091,
+ Mips_MINA_D = 1092,
+ Mips_MINA_S = 1093,
+ Mips_MINI_S_B = 1094,
+ Mips_MINI_S_D = 1095,
+ Mips_MINI_S_H = 1096,
+ Mips_MINI_S_W = 1097,
+ Mips_MINI_U_B = 1098,
+ Mips_MINI_U_D = 1099,
+ Mips_MINI_U_H = 1100,
+ Mips_MINI_U_W = 1101,
+ Mips_MIN_A_B = 1102,
+ Mips_MIN_A_D = 1103,
+ Mips_MIN_A_H = 1104,
+ Mips_MIN_A_W = 1105,
+ Mips_MIN_D = 1106,
+ Mips_MIN_S = 1107,
+ Mips_MIN_S_B = 1108,
+ Mips_MIN_S_D = 1109,
+ Mips_MIN_S_H = 1110,
+ Mips_MIN_S_W = 1111,
+ Mips_MIN_U_B = 1112,
+ Mips_MIN_U_D = 1113,
+ Mips_MIN_U_H = 1114,
+ Mips_MIN_U_W = 1115,
+ Mips_MIPSeh_return32 = 1116,
+ Mips_MIPSeh_return64 = 1117,
+ Mips_MOD = 1118,
+ Mips_MODSUB = 1119,
+ Mips_MODU = 1120,
+ Mips_MOD_S_B = 1121,
+ Mips_MOD_S_D = 1122,
+ Mips_MOD_S_H = 1123,
+ Mips_MOD_S_W = 1124,
+ Mips_MOD_U_B = 1125,
+ Mips_MOD_U_D = 1126,
+ Mips_MOD_U_H = 1127,
+ Mips_MOD_U_W = 1128,
+ Mips_MOVE16_MM = 1129,
+ Mips_MOVEP_MM = 1130,
+ Mips_MOVE_V = 1131,
+ Mips_MOVF_D32 = 1132,
+ Mips_MOVF_D32_MM = 1133,
+ Mips_MOVF_D64 = 1134,
+ Mips_MOVF_I = 1135,
+ Mips_MOVF_I64 = 1136,
+ Mips_MOVF_I_MM = 1137,
+ Mips_MOVF_S = 1138,
+ Mips_MOVF_S_MM = 1139,
+ Mips_MOVN_I64_D64 = 1140,
+ Mips_MOVN_I64_I = 1141,
+ Mips_MOVN_I64_I64 = 1142,
+ Mips_MOVN_I64_S = 1143,
+ Mips_MOVN_I_D32 = 1144,
+ Mips_MOVN_I_D32_MM = 1145,
+ Mips_MOVN_I_D64 = 1146,
+ Mips_MOVN_I_I = 1147,
+ Mips_MOVN_I_I64 = 1148,
+ Mips_MOVN_I_MM = 1149,
+ Mips_MOVN_I_S = 1150,
+ Mips_MOVN_I_S_MM = 1151,
+ Mips_MOVT_D32 = 1152,
+ Mips_MOVT_D32_MM = 1153,
+ Mips_MOVT_D64 = 1154,
+ Mips_MOVT_I = 1155,
+ Mips_MOVT_I64 = 1156,
+ Mips_MOVT_I_MM = 1157,
+ Mips_MOVT_S = 1158,
+ Mips_MOVT_S_MM = 1159,
+ Mips_MOVZ_I64_D64 = 1160,
+ Mips_MOVZ_I64_I = 1161,
+ Mips_MOVZ_I64_I64 = 1162,
+ Mips_MOVZ_I64_S = 1163,
+ Mips_MOVZ_I_D32 = 1164,
+ Mips_MOVZ_I_D32_MM = 1165,
+ Mips_MOVZ_I_D64 = 1166,
+ Mips_MOVZ_I_I = 1167,
+ Mips_MOVZ_I_I64 = 1168,
+ Mips_MOVZ_I_MM = 1169,
+ Mips_MOVZ_I_S = 1170,
+ Mips_MOVZ_I_S_MM = 1171,
+ Mips_MSUB = 1172,
+ Mips_MSUBF_D = 1173,
+ Mips_MSUBF_S = 1174,
+ Mips_MSUBR_Q_H = 1175,
+ Mips_MSUBR_Q_W = 1176,
+ Mips_MSUBU = 1177,
+ Mips_MSUBU_DSP = 1178,
+ Mips_MSUBU_MM = 1179,
+ Mips_MSUBV_B = 1180,
+ Mips_MSUBV_D = 1181,
+ Mips_MSUBV_H = 1182,
+ Mips_MSUBV_W = 1183,
+ Mips_MSUB_D32 = 1184,
+ Mips_MSUB_D32_MM = 1185,
+ Mips_MSUB_D64 = 1186,
+ Mips_MSUB_DSP = 1187,
+ Mips_MSUB_MM = 1188,
+ Mips_MSUB_Q_H = 1189,
+ Mips_MSUB_Q_W = 1190,
+ Mips_MSUB_S = 1191,
+ Mips_MSUB_S_MM = 1192,
+ Mips_MTC0 = 1193,
+ Mips_MTC1 = 1194,
+ Mips_MTC1_MM = 1195,
+ Mips_MTC2 = 1196,
+ Mips_MTHC1_D32 = 1197,
+ Mips_MTHC1_D64 = 1198,
+ Mips_MTHC1_MM = 1199,
+ Mips_MTHI = 1200,
+ Mips_MTHI64 = 1201,
+ Mips_MTHI_DSP = 1202,
+ Mips_MTHI_MM = 1203,
+ Mips_MTHLIP = 1204,
+ Mips_MTLO = 1205,
+ Mips_MTLO64 = 1206,
+ Mips_MTLO_DSP = 1207,
+ Mips_MTLO_MM = 1208,
+ Mips_MTM0 = 1209,
+ Mips_MTM1 = 1210,
+ Mips_MTM2 = 1211,
+ Mips_MTP0 = 1212,
+ Mips_MTP1 = 1213,
+ Mips_MTP2 = 1214,
+ Mips_MUH = 1215,
+ Mips_MUHU = 1216,
+ Mips_MUL = 1217,
+ Mips_MULEQ_S_W_PHL = 1218,
+ Mips_MULEQ_S_W_PHR = 1219,
+ Mips_MULEU_S_PH_QBL = 1220,
+ Mips_MULEU_S_PH_QBR = 1221,
+ Mips_MULQ_RS_PH = 1222,
+ Mips_MULQ_RS_W = 1223,
+ Mips_MULQ_S_PH = 1224,
+ Mips_MULQ_S_W = 1225,
+ Mips_MULR_Q_H = 1226,
+ Mips_MULR_Q_W = 1227,
+ Mips_MULSAQ_S_W_PH = 1228,
+ Mips_MULSA_W_PH = 1229,
+ Mips_MULT = 1230,
+ Mips_MULTU_DSP = 1231,
+ Mips_MULT_DSP = 1232,
+ Mips_MULT_MM = 1233,
+ Mips_MULTu = 1234,
+ Mips_MULTu_MM = 1235,
+ Mips_MULU = 1236,
+ Mips_MULV_B = 1237,
+ Mips_MULV_D = 1238,
+ Mips_MULV_H = 1239,
+ Mips_MULV_W = 1240,
+ Mips_MUL_MM = 1241,
+ Mips_MUL_PH = 1242,
+ Mips_MUL_Q_H = 1243,
+ Mips_MUL_Q_W = 1244,
+ Mips_MUL_R6 = 1245,
+ Mips_MUL_S_PH = 1246,
+ Mips_Mfhi16 = 1247,
+ Mips_Mflo16 = 1248,
+ Mips_Move32R16 = 1249,
+ Mips_MoveR3216 = 1250,
+ Mips_MultRxRy16 = 1251,
+ Mips_MultRxRyRz16 = 1252,
+ Mips_MultuRxRy16 = 1253,
+ Mips_MultuRxRyRz16 = 1254,
+ Mips_NLOC_B = 1255,
+ Mips_NLOC_D = 1256,
+ Mips_NLOC_H = 1257,
+ Mips_NLOC_W = 1258,
+ Mips_NLZC_B = 1259,
+ Mips_NLZC_D = 1260,
+ Mips_NLZC_H = 1261,
+ Mips_NLZC_W = 1262,
+ Mips_NMADD_D32 = 1263,
+ Mips_NMADD_D32_MM = 1264,
+ Mips_NMADD_D64 = 1265,
+ Mips_NMADD_S = 1266,
+ Mips_NMADD_S_MM = 1267,
+ Mips_NMSUB_D32 = 1268,
+ Mips_NMSUB_D32_MM = 1269,
+ Mips_NMSUB_D64 = 1270,
+ Mips_NMSUB_S = 1271,
+ Mips_NMSUB_S_MM = 1272,
+ Mips_NOP = 1273,
+ Mips_NOR = 1274,
+ Mips_NOR64 = 1275,
+ Mips_NORI_B = 1276,
+ Mips_NOR_MM = 1277,
+ Mips_NOR_V = 1278,
+ Mips_NOR_V_D_PSEUDO = 1279,
+ Mips_NOR_V_H_PSEUDO = 1280,
+ Mips_NOR_V_W_PSEUDO = 1281,
+ Mips_NOT16_MM = 1282,
+ Mips_NegRxRy16 = 1283,
+ Mips_NotRxRy16 = 1284,
+ Mips_OR = 1285,
+ Mips_OR16_MM = 1286,
+ Mips_OR64 = 1287,
+ Mips_ORI_B = 1288,
+ Mips_OR_MM = 1289,
+ Mips_OR_V = 1290,
+ Mips_OR_V_D_PSEUDO = 1291,
+ Mips_OR_V_H_PSEUDO = 1292,
+ Mips_OR_V_W_PSEUDO = 1293,
+ Mips_ORi = 1294,
+ Mips_ORi64 = 1295,
+ Mips_ORi_MM = 1296,
+ Mips_OrRxRxRy16 = 1297,
+ Mips_PACKRL_PH = 1298,
+ Mips_PAUSE = 1299,
+ Mips_PAUSE_MM = 1300,
+ Mips_PCKEV_B = 1301,
+ Mips_PCKEV_D = 1302,
+ Mips_PCKEV_H = 1303,
+ Mips_PCKEV_W = 1304,
+ Mips_PCKOD_B = 1305,
+ Mips_PCKOD_D = 1306,
+ Mips_PCKOD_H = 1307,
+ Mips_PCKOD_W = 1308,
+ Mips_PCNT_B = 1309,
+ Mips_PCNT_D = 1310,
+ Mips_PCNT_H = 1311,
+ Mips_PCNT_W = 1312,
+ Mips_PICK_PH = 1313,
+ Mips_PICK_QB = 1314,
+ Mips_POP = 1315,
+ Mips_PRECEQU_PH_QBL = 1316,
+ Mips_PRECEQU_PH_QBLA = 1317,
+ Mips_PRECEQU_PH_QBR = 1318,
+ Mips_PRECEQU_PH_QBRA = 1319,
+ Mips_PRECEQ_W_PHL = 1320,
+ Mips_PRECEQ_W_PHR = 1321,
+ Mips_PRECEU_PH_QBL = 1322,
+ Mips_PRECEU_PH_QBLA = 1323,
+ Mips_PRECEU_PH_QBR = 1324,
+ Mips_PRECEU_PH_QBRA = 1325,
+ Mips_PRECRQU_S_QB_PH = 1326,
+ Mips_PRECRQ_PH_W = 1327,
+ Mips_PRECRQ_QB_PH = 1328,
+ Mips_PRECRQ_RS_PH_W = 1329,
+ Mips_PRECR_QB_PH = 1330,
+ Mips_PRECR_SRA_PH_W = 1331,
+ Mips_PRECR_SRA_R_PH_W = 1332,
+ Mips_PREF = 1333,
+ Mips_PREF_MM = 1334,
+ Mips_PREF_R6 = 1335,
+ Mips_PREPEND = 1336,
+ Mips_PseudoCMPU_EQ_QB = 1337,
+ Mips_PseudoCMPU_LE_QB = 1338,
+ Mips_PseudoCMPU_LT_QB = 1339,
+ Mips_PseudoCMP_EQ_PH = 1340,
+ Mips_PseudoCMP_LE_PH = 1341,
+ Mips_PseudoCMP_LT_PH = 1342,
+ Mips_PseudoCVT_D32_W = 1343,
+ Mips_PseudoCVT_D64_L = 1344,
+ Mips_PseudoCVT_D64_W = 1345,
+ Mips_PseudoCVT_S_L = 1346,
+ Mips_PseudoCVT_S_W = 1347,
+ Mips_PseudoDMULT = 1348,
+ Mips_PseudoDMULTu = 1349,
+ Mips_PseudoDSDIV = 1350,
+ Mips_PseudoDUDIV = 1351,
+ Mips_PseudoIndirectBranch = 1352,
+ Mips_PseudoIndirectBranch64 = 1353,
+ Mips_PseudoMADD = 1354,
+ Mips_PseudoMADDU = 1355,
+ Mips_PseudoMFHI = 1356,
+ Mips_PseudoMFHI64 = 1357,
+ Mips_PseudoMFLO = 1358,
+ Mips_PseudoMFLO64 = 1359,
+ Mips_PseudoMSUB = 1360,
+ Mips_PseudoMSUBU = 1361,
+ Mips_PseudoMTLOHI = 1362,
+ Mips_PseudoMTLOHI64 = 1363,
+ Mips_PseudoMTLOHI_DSP = 1364,
+ Mips_PseudoMULT = 1365,
+ Mips_PseudoMULTu = 1366,
+ Mips_PseudoPICK_PH = 1367,
+ Mips_PseudoPICK_QB = 1368,
+ Mips_PseudoReturn = 1369,
+ Mips_PseudoReturn64 = 1370,
+ Mips_PseudoSDIV = 1371,
+ Mips_PseudoSELECTFP_F_D32 = 1372,
+ Mips_PseudoSELECTFP_F_D64 = 1373,
+ Mips_PseudoSELECTFP_F_I = 1374,
+ Mips_PseudoSELECTFP_F_I64 = 1375,
+ Mips_PseudoSELECTFP_F_S = 1376,
+ Mips_PseudoSELECTFP_T_D32 = 1377,
+ Mips_PseudoSELECTFP_T_D64 = 1378,
+ Mips_PseudoSELECTFP_T_I = 1379,
+ Mips_PseudoSELECTFP_T_I64 = 1380,
+ Mips_PseudoSELECTFP_T_S = 1381,
+ Mips_PseudoSELECT_D32 = 1382,
+ Mips_PseudoSELECT_D64 = 1383,
+ Mips_PseudoSELECT_I = 1384,
+ Mips_PseudoSELECT_I64 = 1385,
+ Mips_PseudoSELECT_S = 1386,
+ Mips_PseudoUDIV = 1387,
+ Mips_RADDU_W_QB = 1388,
+ Mips_RDDSP = 1389,
+ Mips_RDHWR = 1390,
+ Mips_RDHWR64 = 1391,
+ Mips_RDHWR_MM = 1392,
+ Mips_REPLV_PH = 1393,
+ Mips_REPLV_QB = 1394,
+ Mips_REPL_PH = 1395,
+ Mips_REPL_QB = 1396,
+ Mips_RINT_D = 1397,
+ Mips_RINT_S = 1398,
+ Mips_ROTR = 1399,
+ Mips_ROTRV = 1400,
+ Mips_ROTRV_MM = 1401,
+ Mips_ROTR_MM = 1402,
+ Mips_ROUND_L_D64 = 1403,
+ Mips_ROUND_L_S = 1404,
+ Mips_ROUND_W_D32 = 1405,
+ Mips_ROUND_W_D64 = 1406,
+ Mips_ROUND_W_MM = 1407,
+ Mips_ROUND_W_S = 1408,
+ Mips_ROUND_W_S_MM = 1409,
+ Mips_Restore16 = 1410,
+ Mips_RestoreX16 = 1411,
+ Mips_RetRA = 1412,
+ Mips_RetRA16 = 1413,
+ Mips_SAT_S_B = 1414,
+ Mips_SAT_S_D = 1415,
+ Mips_SAT_S_H = 1416,
+ Mips_SAT_S_W = 1417,
+ Mips_SAT_U_B = 1418,
+ Mips_SAT_U_D = 1419,
+ Mips_SAT_U_H = 1420,
+ Mips_SAT_U_W = 1421,
+ Mips_SB = 1422,
+ Mips_SB16_MM = 1423,
+ Mips_SB64 = 1424,
+ Mips_SB_MM = 1425,
+ Mips_SC = 1426,
+ Mips_SCD = 1427,
+ Mips_SCD_R6 = 1428,
+ Mips_SC_MM = 1429,
+ Mips_SC_R6 = 1430,
+ Mips_SD = 1431,
+ Mips_SDBBP = 1432,
+ Mips_SDBBP16_MM = 1433,
+ Mips_SDBBP_MM = 1434,
+ Mips_SDBBP_R6 = 1435,
+ Mips_SDC1 = 1436,
+ Mips_SDC164 = 1437,
+ Mips_SDC1_MM = 1438,
+ Mips_SDC2 = 1439,
+ Mips_SDC2_R6 = 1440,
+ Mips_SDC3 = 1441,
+ Mips_SDIV = 1442,
+ Mips_SDIV_MM = 1443,
+ Mips_SDL = 1444,
+ Mips_SDR = 1445,
+ Mips_SDXC1 = 1446,
+ Mips_SDXC164 = 1447,
+ Mips_SEB = 1448,
+ Mips_SEB64 = 1449,
+ Mips_SEB_MM = 1450,
+ Mips_SEH = 1451,
+ Mips_SEH64 = 1452,
+ Mips_SEH_MM = 1453,
+ Mips_SELEQZ = 1454,
+ Mips_SELEQZ64 = 1455,
+ Mips_SELEQZ_D = 1456,
+ Mips_SELEQZ_S = 1457,
+ Mips_SELNEZ = 1458,
+ Mips_SELNEZ64 = 1459,
+ Mips_SELNEZ_D = 1460,
+ Mips_SELNEZ_S = 1461,
+ Mips_SEL_D = 1462,
+ Mips_SEL_S = 1463,
+ Mips_SEQ = 1464,
+ Mips_SEQi = 1465,
+ Mips_SH = 1466,
+ Mips_SH16_MM = 1467,
+ Mips_SH64 = 1468,
+ Mips_SHF_B = 1469,
+ Mips_SHF_H = 1470,
+ Mips_SHF_W = 1471,
+ Mips_SHILO = 1472,
+ Mips_SHILOV = 1473,
+ Mips_SHLLV_PH = 1474,
+ Mips_SHLLV_QB = 1475,
+ Mips_SHLLV_S_PH = 1476,
+ Mips_SHLLV_S_W = 1477,
+ Mips_SHLL_PH = 1478,
+ Mips_SHLL_QB = 1479,
+ Mips_SHLL_S_PH = 1480,
+ Mips_SHLL_S_W = 1481,
+ Mips_SHRAV_PH = 1482,
+ Mips_SHRAV_QB = 1483,
+ Mips_SHRAV_R_PH = 1484,
+ Mips_SHRAV_R_QB = 1485,
+ Mips_SHRAV_R_W = 1486,
+ Mips_SHRA_PH = 1487,
+ Mips_SHRA_QB = 1488,
+ Mips_SHRA_R_PH = 1489,
+ Mips_SHRA_R_QB = 1490,
+ Mips_SHRA_R_W = 1491,
+ Mips_SHRLV_PH = 1492,
+ Mips_SHRLV_QB = 1493,
+ Mips_SHRL_PH = 1494,
+ Mips_SHRL_QB = 1495,
+ Mips_SH_MM = 1496,
+ Mips_SLDI_B = 1497,
+ Mips_SLDI_D = 1498,
+ Mips_SLDI_H = 1499,
+ Mips_SLDI_W = 1500,
+ Mips_SLD_B = 1501,
+ Mips_SLD_D = 1502,
+ Mips_SLD_H = 1503,
+ Mips_SLD_W = 1504,
+ Mips_SLL = 1505,
+ Mips_SLL16_MM = 1506,
+ Mips_SLL64_32 = 1507,
+ Mips_SLL64_64 = 1508,
+ Mips_SLLI_B = 1509,
+ Mips_SLLI_D = 1510,
+ Mips_SLLI_H = 1511,
+ Mips_SLLI_W = 1512,
+ Mips_SLLV = 1513,
+ Mips_SLLV_MM = 1514,
+ Mips_SLL_B = 1515,
+ Mips_SLL_D = 1516,
+ Mips_SLL_H = 1517,
+ Mips_SLL_MM = 1518,
+ Mips_SLL_W = 1519,
+ Mips_SLT = 1520,
+ Mips_SLT64 = 1521,
+ Mips_SLT_MM = 1522,
+ Mips_SLTi = 1523,
+ Mips_SLTi64 = 1524,
+ Mips_SLTi_MM = 1525,
+ Mips_SLTiu = 1526,
+ Mips_SLTiu64 = 1527,
+ Mips_SLTiu_MM = 1528,
+ Mips_SLTu = 1529,
+ Mips_SLTu64 = 1530,
+ Mips_SLTu_MM = 1531,
+ Mips_SNE = 1532,
+ Mips_SNEi = 1533,
+ Mips_SNZ_B_PSEUDO = 1534,
+ Mips_SNZ_D_PSEUDO = 1535,
+ Mips_SNZ_H_PSEUDO = 1536,
+ Mips_SNZ_V_PSEUDO = 1537,
+ Mips_SNZ_W_PSEUDO = 1538,
+ Mips_SPLATI_B = 1539,
+ Mips_SPLATI_D = 1540,
+ Mips_SPLATI_H = 1541,
+ Mips_SPLATI_W = 1542,
+ Mips_SPLAT_B = 1543,
+ Mips_SPLAT_D = 1544,
+ Mips_SPLAT_H = 1545,
+ Mips_SPLAT_W = 1546,
+ Mips_SRA = 1547,
+ Mips_SRAI_B = 1548,
+ Mips_SRAI_D = 1549,
+ Mips_SRAI_H = 1550,
+ Mips_SRAI_W = 1551,
+ Mips_SRARI_B = 1552,
+ Mips_SRARI_D = 1553,
+ Mips_SRARI_H = 1554,
+ Mips_SRARI_W = 1555,
+ Mips_SRAR_B = 1556,
+ Mips_SRAR_D = 1557,
+ Mips_SRAR_H = 1558,
+ Mips_SRAR_W = 1559,
+ Mips_SRAV = 1560,
+ Mips_SRAV_MM = 1561,
+ Mips_SRA_B = 1562,
+ Mips_SRA_D = 1563,
+ Mips_SRA_H = 1564,
+ Mips_SRA_MM = 1565,
+ Mips_SRA_W = 1566,
+ Mips_SRL = 1567,
+ Mips_SRL16_MM = 1568,
+ Mips_SRLI_B = 1569,
+ Mips_SRLI_D = 1570,
+ Mips_SRLI_H = 1571,
+ Mips_SRLI_W = 1572,
+ Mips_SRLRI_B = 1573,
+ Mips_SRLRI_D = 1574,
+ Mips_SRLRI_H = 1575,
+ Mips_SRLRI_W = 1576,
+ Mips_SRLR_B = 1577,
+ Mips_SRLR_D = 1578,
+ Mips_SRLR_H = 1579,
+ Mips_SRLR_W = 1580,
+ Mips_SRLV = 1581,
+ Mips_SRLV_MM = 1582,
+ Mips_SRL_B = 1583,
+ Mips_SRL_D = 1584,
+ Mips_SRL_H = 1585,
+ Mips_SRL_MM = 1586,
+ Mips_SRL_W = 1587,
+ Mips_SSNOP = 1588,
+ Mips_SSNOP_MM = 1589,
+ Mips_STORE_ACC128 = 1590,
+ Mips_STORE_ACC64 = 1591,
+ Mips_STORE_ACC64DSP = 1592,
+ Mips_STORE_CCOND_DSP = 1593,
+ Mips_ST_B = 1594,
+ Mips_ST_D = 1595,
+ Mips_ST_H = 1596,
+ Mips_ST_W = 1597,
+ Mips_SUB = 1598,
+ Mips_SUBQH_PH = 1599,
+ Mips_SUBQH_R_PH = 1600,
+ Mips_SUBQH_R_W = 1601,
+ Mips_SUBQH_W = 1602,
+ Mips_SUBQ_PH = 1603,
+ Mips_SUBQ_S_PH = 1604,
+ Mips_SUBQ_S_W = 1605,
+ Mips_SUBSUS_U_B = 1606,
+ Mips_SUBSUS_U_D = 1607,
+ Mips_SUBSUS_U_H = 1608,
+ Mips_SUBSUS_U_W = 1609,
+ Mips_SUBSUU_S_B = 1610,
+ Mips_SUBSUU_S_D = 1611,
+ Mips_SUBSUU_S_H = 1612,
+ Mips_SUBSUU_S_W = 1613,
+ Mips_SUBS_S_B = 1614,
+ Mips_SUBS_S_D = 1615,
+ Mips_SUBS_S_H = 1616,
+ Mips_SUBS_S_W = 1617,
+ Mips_SUBS_U_B = 1618,
+ Mips_SUBS_U_D = 1619,
+ Mips_SUBS_U_H = 1620,
+ Mips_SUBS_U_W = 1621,
+ Mips_SUBU16_MM = 1622,
+ Mips_SUBUH_QB = 1623,
+ Mips_SUBUH_R_QB = 1624,
+ Mips_SUBU_PH = 1625,
+ Mips_SUBU_QB = 1626,
+ Mips_SUBU_S_PH = 1627,
+ Mips_SUBU_S_QB = 1628,
+ Mips_SUBVI_B = 1629,
+ Mips_SUBVI_D = 1630,
+ Mips_SUBVI_H = 1631,
+ Mips_SUBVI_W = 1632,
+ Mips_SUBV_B = 1633,
+ Mips_SUBV_D = 1634,
+ Mips_SUBV_H = 1635,
+ Mips_SUBV_W = 1636,
+ Mips_SUB_MM = 1637,
+ Mips_SUBu = 1638,
+ Mips_SUBu_MM = 1639,
+ Mips_SUXC1 = 1640,
+ Mips_SUXC164 = 1641,
+ Mips_SUXC1_MM = 1642,
+ Mips_SW = 1643,
+ Mips_SW16_MM = 1644,
+ Mips_SW64 = 1645,
+ Mips_SWC1 = 1646,
+ Mips_SWC1_MM = 1647,
+ Mips_SWC2 = 1648,
+ Mips_SWC2_R6 = 1649,
+ Mips_SWC3 = 1650,
+ Mips_SWL = 1651,
+ Mips_SWL64 = 1652,
+ Mips_SWL_MM = 1653,
+ Mips_SWM16_MM = 1654,
+ Mips_SWM32_MM = 1655,
+ Mips_SWM_MM = 1656,
+ Mips_SWP_MM = 1657,
+ Mips_SWR = 1658,
+ Mips_SWR64 = 1659,
+ Mips_SWR_MM = 1660,
+ Mips_SWSP_MM = 1661,
+ Mips_SWXC1 = 1662,
+ Mips_SWXC1_MM = 1663,
+ Mips_SW_MM = 1664,
+ Mips_SYNC = 1665,
+ Mips_SYNCI = 1666,
+ Mips_SYNC_MM = 1667,
+ Mips_SYSCALL = 1668,
+ Mips_SYSCALL_MM = 1669,
+ Mips_SZ_B_PSEUDO = 1670,
+ Mips_SZ_D_PSEUDO = 1671,
+ Mips_SZ_H_PSEUDO = 1672,
+ Mips_SZ_V_PSEUDO = 1673,
+ Mips_SZ_W_PSEUDO = 1674,
+ Mips_Save16 = 1675,
+ Mips_SaveX16 = 1676,
+ Mips_SbRxRyOffMemX16 = 1677,
+ Mips_SebRx16 = 1678,
+ Mips_SehRx16 = 1679,
+ Mips_SelBeqZ = 1680,
+ Mips_SelBneZ = 1681,
+ Mips_SelTBteqZCmp = 1682,
+ Mips_SelTBteqZCmpi = 1683,
+ Mips_SelTBteqZSlt = 1684,
+ Mips_SelTBteqZSlti = 1685,
+ Mips_SelTBteqZSltiu = 1686,
+ Mips_SelTBteqZSltu = 1687,
+ Mips_SelTBtneZCmp = 1688,
+ Mips_SelTBtneZCmpi = 1689,
+ Mips_SelTBtneZSlt = 1690,
+ Mips_SelTBtneZSlti = 1691,
+ Mips_SelTBtneZSltiu = 1692,
+ Mips_SelTBtneZSltu = 1693,
+ Mips_ShRxRyOffMemX16 = 1694,
+ Mips_SllX16 = 1695,
+ Mips_SllvRxRy16 = 1696,
+ Mips_SltCCRxRy16 = 1697,
+ Mips_SltRxRy16 = 1698,
+ Mips_SltiCCRxImmX16 = 1699,
+ Mips_SltiRxImm16 = 1700,
+ Mips_SltiRxImmX16 = 1701,
+ Mips_SltiuCCRxImmX16 = 1702,
+ Mips_SltiuRxImm16 = 1703,
+ Mips_SltiuRxImmX16 = 1704,
+ Mips_SltuCCRxRy16 = 1705,
+ Mips_SltuRxRy16 = 1706,
+ Mips_SltuRxRyRz16 = 1707,
+ Mips_SraX16 = 1708,
+ Mips_SravRxRy16 = 1709,
+ Mips_SrlX16 = 1710,
+ Mips_SrlvRxRy16 = 1711,
+ Mips_SubuRxRyRz16 = 1712,
+ Mips_SwRxRyOffMemX16 = 1713,
+ Mips_SwRxSpImmX16 = 1714,
+ Mips_TAILCALL = 1715,
+ Mips_TAILCALL64_R = 1716,
+ Mips_TAILCALL_R = 1717,
+ Mips_TEQ = 1718,
+ Mips_TEQI = 1719,
+ Mips_TEQI_MM = 1720,
+ Mips_TEQ_MM = 1721,
+ Mips_TGE = 1722,
+ Mips_TGEI = 1723,
+ Mips_TGEIU = 1724,
+ Mips_TGEIU_MM = 1725,
+ Mips_TGEI_MM = 1726,
+ Mips_TGEU = 1727,
+ Mips_TGEU_MM = 1728,
+ Mips_TGE_MM = 1729,
+ Mips_TLBP = 1730,
+ Mips_TLBP_MM = 1731,
+ Mips_TLBR = 1732,
+ Mips_TLBR_MM = 1733,
+ Mips_TLBWI = 1734,
+ Mips_TLBWI_MM = 1735,
+ Mips_TLBWR = 1736,
+ Mips_TLBWR_MM = 1737,
+ Mips_TLT = 1738,
+ Mips_TLTI = 1739,
+ Mips_TLTIU_MM = 1740,
+ Mips_TLTI_MM = 1741,
+ Mips_TLTU = 1742,
+ Mips_TLTU_MM = 1743,
+ Mips_TLT_MM = 1744,
+ Mips_TNE = 1745,
+ Mips_TNEI = 1746,
+ Mips_TNEI_MM = 1747,
+ Mips_TNE_MM = 1748,
+ Mips_TRAP = 1749,
+ Mips_TRUNC_L_D64 = 1750,
+ Mips_TRUNC_L_S = 1751,
+ Mips_TRUNC_W_D32 = 1752,
+ Mips_TRUNC_W_D64 = 1753,
+ Mips_TRUNC_W_MM = 1754,
+ Mips_TRUNC_W_S = 1755,
+ Mips_TRUNC_W_S_MM = 1756,
+ Mips_TTLTIU = 1757,
+ Mips_UDIV = 1758,
+ Mips_UDIV_MM = 1759,
+ Mips_V3MULU = 1760,
+ Mips_VMM0 = 1761,
+ Mips_VMULU = 1762,
+ Mips_VSHF_B = 1763,
+ Mips_VSHF_D = 1764,
+ Mips_VSHF_H = 1765,
+ Mips_VSHF_W = 1766,
+ Mips_WAIT = 1767,
+ Mips_WAIT_MM = 1768,
+ Mips_WRDSP = 1769,
+ Mips_WSBH = 1770,
+ Mips_WSBH_MM = 1771,
+ Mips_XOR = 1772,
+ Mips_XOR16_MM = 1773,
+ Mips_XOR64 = 1774,
+ Mips_XORI_B = 1775,
+ Mips_XOR_MM = 1776,
+ Mips_XOR_V = 1777,
+ Mips_XOR_V_D_PSEUDO = 1778,
+ Mips_XOR_V_H_PSEUDO = 1779,
+ Mips_XOR_V_W_PSEUDO = 1780,
+ Mips_XORi = 1781,
+ Mips_XORi64 = 1782,
+ Mips_XORi_MM = 1783,
+ Mips_XorRxRxRy16 = 1784,
+ Mips_INSTRUCTION_LIST_END = 1785
+};
+
+#endif // GET_INSTRINFO_ENUM
diff --git a/capstone/arch/Mips/MipsGenRegisterInfo.inc b/capstone/arch/Mips/MipsGenRegisterInfo.inc
new file mode 100644
index 000000000..4501a407f
--- /dev/null
+++ b/capstone/arch/Mips/MipsGenRegisterInfo.inc
@@ -0,0 +1,1679 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|*Target Register Enum Values *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+
+
+#ifdef GET_REGINFO_ENUM
+#undef GET_REGINFO_ENUM
+
+enum {
+ Mips_NoRegister,
+ Mips_AT = 1,
+ Mips_DSPCCond = 2,
+ Mips_DSPCarry = 3,
+ Mips_DSPEFI = 4,
+ Mips_DSPOutFlag = 5,
+ Mips_DSPPos = 6,
+ Mips_DSPSCount = 7,
+ Mips_FP = 8,
+ Mips_GP = 9,
+ Mips_MSAAccess = 10,
+ Mips_MSACSR = 11,
+ Mips_MSAIR = 12,
+ Mips_MSAMap = 13,
+ Mips_MSAModify = 14,
+ Mips_MSARequest = 15,
+ Mips_MSASave = 16,
+ Mips_MSAUnmap = 17,
+ Mips_PC = 18,
+ Mips_RA = 19,
+ Mips_SP = 20,
+ Mips_ZERO = 21,
+ Mips_A0 = 22,
+ Mips_A1 = 23,
+ Mips_A2 = 24,
+ Mips_A3 = 25,
+ Mips_AC0 = 26,
+ Mips_AC1 = 27,
+ Mips_AC2 = 28,
+ Mips_AC3 = 29,
+ Mips_AT_64 = 30,
+ Mips_CC0 = 31,
+ Mips_CC1 = 32,
+ Mips_CC2 = 33,
+ Mips_CC3 = 34,
+ Mips_CC4 = 35,
+ Mips_CC5 = 36,
+ Mips_CC6 = 37,
+ Mips_CC7 = 38,
+ Mips_COP20 = 39,
+ Mips_COP21 = 40,
+ Mips_COP22 = 41,
+ Mips_COP23 = 42,
+ Mips_COP24 = 43,
+ Mips_COP25 = 44,
+ Mips_COP26 = 45,
+ Mips_COP27 = 46,
+ Mips_COP28 = 47,
+ Mips_COP29 = 48,
+ Mips_COP30 = 49,
+ Mips_COP31 = 50,
+ Mips_COP32 = 51,
+ Mips_COP33 = 52,
+ Mips_COP34 = 53,
+ Mips_COP35 = 54,
+ Mips_COP36 = 55,
+ Mips_COP37 = 56,
+ Mips_COP38 = 57,
+ Mips_COP39 = 58,
+ Mips_COP210 = 59,
+ Mips_COP211 = 60,
+ Mips_COP212 = 61,
+ Mips_COP213 = 62,
+ Mips_COP214 = 63,
+ Mips_COP215 = 64,
+ Mips_COP216 = 65,
+ Mips_COP217 = 66,
+ Mips_COP218 = 67,
+ Mips_COP219 = 68,
+ Mips_COP220 = 69,
+ Mips_COP221 = 70,
+ Mips_COP222 = 71,
+ Mips_COP223 = 72,
+ Mips_COP224 = 73,
+ Mips_COP225 = 74,
+ Mips_COP226 = 75,
+ Mips_COP227 = 76,
+ Mips_COP228 = 77,
+ Mips_COP229 = 78,
+ Mips_COP230 = 79,
+ Mips_COP231 = 80,
+ Mips_COP310 = 81,
+ Mips_COP311 = 82,
+ Mips_COP312 = 83,
+ Mips_COP313 = 84,
+ Mips_COP314 = 85,
+ Mips_COP315 = 86,
+ Mips_COP316 = 87,
+ Mips_COP317 = 88,
+ Mips_COP318 = 89,
+ Mips_COP319 = 90,
+ Mips_COP320 = 91,
+ Mips_COP321 = 92,
+ Mips_COP322 = 93,
+ Mips_COP323 = 94,
+ Mips_COP324 = 95,
+ Mips_COP325 = 96,
+ Mips_COP326 = 97,
+ Mips_COP327 = 98,
+ Mips_COP328 = 99,
+ Mips_COP329 = 100,
+ Mips_COP330 = 101,
+ Mips_COP331 = 102,
+ Mips_D0 = 103,
+ Mips_D1 = 104,
+ Mips_D2 = 105,
+ Mips_D3 = 106,
+ Mips_D4 = 107,
+ Mips_D5 = 108,
+ Mips_D6 = 109,
+ Mips_D7 = 110,
+ Mips_D8 = 111,
+ Mips_D9 = 112,
+ Mips_D10 = 113,
+ Mips_D11 = 114,
+ Mips_D12 = 115,
+ Mips_D13 = 116,
+ Mips_D14 = 117,
+ Mips_D15 = 118,
+ Mips_DSPOutFlag20 = 119,
+ Mips_DSPOutFlag21 = 120,
+ Mips_DSPOutFlag22 = 121,
+ Mips_DSPOutFlag23 = 122,
+ Mips_F0 = 123,
+ Mips_F1 = 124,
+ Mips_F2 = 125,
+ Mips_F3 = 126,
+ Mips_F4 = 127,
+ Mips_F5 = 128,
+ Mips_F6 = 129,
+ Mips_F7 = 130,
+ Mips_F8 = 131,
+ Mips_F9 = 132,
+ Mips_F10 = 133,
+ Mips_F11 = 134,
+ Mips_F12 = 135,
+ Mips_F13 = 136,
+ Mips_F14 = 137,
+ Mips_F15 = 138,
+ Mips_F16 = 139,
+ Mips_F17 = 140,
+ Mips_F18 = 141,
+ Mips_F19 = 142,
+ Mips_F20 = 143,
+ Mips_F21 = 144,
+ Mips_F22 = 145,
+ Mips_F23 = 146,
+ Mips_F24 = 147,
+ Mips_F25 = 148,
+ Mips_F26 = 149,
+ Mips_F27 = 150,
+ Mips_F28 = 151,
+ Mips_F29 = 152,
+ Mips_F30 = 153,
+ Mips_F31 = 154,
+ Mips_FCC0 = 155,
+ Mips_FCC1 = 156,
+ Mips_FCC2 = 157,
+ Mips_FCC3 = 158,
+ Mips_FCC4 = 159,
+ Mips_FCC5 = 160,
+ Mips_FCC6 = 161,
+ Mips_FCC7 = 162,
+ Mips_FCR0 = 163,
+ Mips_FCR1 = 164,
+ Mips_FCR2 = 165,
+ Mips_FCR3 = 166,
+ Mips_FCR4 = 167,
+ Mips_FCR5 = 168,
+ Mips_FCR6 = 169,
+ Mips_FCR7 = 170,
+ Mips_FCR8 = 171,
+ Mips_FCR9 = 172,
+ Mips_FCR10 = 173,
+ Mips_FCR11 = 174,
+ Mips_FCR12 = 175,
+ Mips_FCR13 = 176,
+ Mips_FCR14 = 177,
+ Mips_FCR15 = 178,
+ Mips_FCR16 = 179,
+ Mips_FCR17 = 180,
+ Mips_FCR18 = 181,
+ Mips_FCR19 = 182,
+ Mips_FCR20 = 183,
+ Mips_FCR21 = 184,
+ Mips_FCR22 = 185,
+ Mips_FCR23 = 186,
+ Mips_FCR24 = 187,
+ Mips_FCR25 = 188,
+ Mips_FCR26 = 189,
+ Mips_FCR27 = 190,
+ Mips_FCR28 = 191,
+ Mips_FCR29 = 192,
+ Mips_FCR30 = 193,
+ Mips_FCR31 = 194,
+ Mips_FP_64 = 195,
+ Mips_F_HI0 = 196,
+ Mips_F_HI1 = 197,
+ Mips_F_HI2 = 198,
+ Mips_F_HI3 = 199,
+ Mips_F_HI4 = 200,
+ Mips_F_HI5 = 201,
+ Mips_F_HI6 = 202,
+ Mips_F_HI7 = 203,
+ Mips_F_HI8 = 204,
+ Mips_F_HI9 = 205,
+ Mips_F_HI10 = 206,
+ Mips_F_HI11 = 207,
+ Mips_F_HI12 = 208,
+ Mips_F_HI13 = 209,
+ Mips_F_HI14 = 210,
+ Mips_F_HI15 = 211,
+ Mips_F_HI16 = 212,
+ Mips_F_HI17 = 213,
+ Mips_F_HI18 = 214,
+ Mips_F_HI19 = 215,
+ Mips_F_HI20 = 216,
+ Mips_F_HI21 = 217,
+ Mips_F_HI22 = 218,
+ Mips_F_HI23 = 219,
+ Mips_F_HI24 = 220,
+ Mips_F_HI25 = 221,
+ Mips_F_HI26 = 222,
+ Mips_F_HI27 = 223,
+ Mips_F_HI28 = 224,
+ Mips_F_HI29 = 225,
+ Mips_F_HI30 = 226,
+ Mips_F_HI31 = 227,
+ Mips_GP_64 = 228,
+ Mips_HI0 = 229,
+ Mips_HI1 = 230,
+ Mips_HI2 = 231,
+ Mips_HI3 = 232,
+ Mips_HWR0 = 233,
+ Mips_HWR1 = 234,
+ Mips_HWR2 = 235,
+ Mips_HWR3 = 236,
+ Mips_HWR4 = 237,
+ Mips_HWR5 = 238,
+ Mips_HWR6 = 239,
+ Mips_HWR7 = 240,
+ Mips_HWR8 = 241,
+ Mips_HWR9 = 242,
+ Mips_HWR10 = 243,
+ Mips_HWR11 = 244,
+ Mips_HWR12 = 245,
+ Mips_HWR13 = 246,
+ Mips_HWR14 = 247,
+ Mips_HWR15 = 248,
+ Mips_HWR16 = 249,
+ Mips_HWR17 = 250,
+ Mips_HWR18 = 251,
+ Mips_HWR19 = 252,
+ Mips_HWR20 = 253,
+ Mips_HWR21 = 254,
+ Mips_HWR22 = 255,
+ Mips_HWR23 = 256,
+ Mips_HWR24 = 257,
+ Mips_HWR25 = 258,
+ Mips_HWR26 = 259,
+ Mips_HWR27 = 260,
+ Mips_HWR28 = 261,
+ Mips_HWR29 = 262,
+ Mips_HWR30 = 263,
+ Mips_HWR31 = 264,
+ Mips_K0 = 265,
+ Mips_K1 = 266,
+ Mips_LO0 = 267,
+ Mips_LO1 = 268,
+ Mips_LO2 = 269,
+ Mips_LO3 = 270,
+ Mips_MPL0 = 271,
+ Mips_MPL1 = 272,
+ Mips_MPL2 = 273,
+ Mips_P0 = 274,
+ Mips_P1 = 275,
+ Mips_P2 = 276,
+ Mips_RA_64 = 277,
+ Mips_S0 = 278,
+ Mips_S1 = 279,
+ Mips_S2 = 280,
+ Mips_S3 = 281,
+ Mips_S4 = 282,
+ Mips_S5 = 283,
+ Mips_S6 = 284,
+ Mips_S7 = 285,
+ Mips_SP_64 = 286,
+ Mips_T0 = 287,
+ Mips_T1 = 288,
+ Mips_T2 = 289,
+ Mips_T3 = 290,
+ Mips_T4 = 291,
+ Mips_T5 = 292,
+ Mips_T6 = 293,
+ Mips_T7 = 294,
+ Mips_T8 = 295,
+ Mips_T9 = 296,
+ Mips_V0 = 297,
+ Mips_V1 = 298,
+ Mips_W0 = 299,
+ Mips_W1 = 300,
+ Mips_W2 = 301,
+ Mips_W3 = 302,
+ Mips_W4 = 303,
+ Mips_W5 = 304,
+ Mips_W6 = 305,
+ Mips_W7 = 306,
+ Mips_W8 = 307,
+ Mips_W9 = 308,
+ Mips_W10 = 309,
+ Mips_W11 = 310,
+ Mips_W12 = 311,
+ Mips_W13 = 312,
+ Mips_W14 = 313,
+ Mips_W15 = 314,
+ Mips_W16 = 315,
+ Mips_W17 = 316,
+ Mips_W18 = 317,
+ Mips_W19 = 318,
+ Mips_W20 = 319,
+ Mips_W21 = 320,
+ Mips_W22 = 321,
+ Mips_W23 = 322,
+ Mips_W24 = 323,
+ Mips_W25 = 324,
+ Mips_W26 = 325,
+ Mips_W27 = 326,
+ Mips_W28 = 327,
+ Mips_W29 = 328,
+ Mips_W30 = 329,
+ Mips_W31 = 330,
+ Mips_ZERO_64 = 331,
+ Mips_A0_64 = 332,
+ Mips_A1_64 = 333,
+ Mips_A2_64 = 334,
+ Mips_A3_64 = 335,
+ Mips_AC0_64 = 336,
+ Mips_D0_64 = 337,
+ Mips_D1_64 = 338,
+ Mips_D2_64 = 339,
+ Mips_D3_64 = 340,
+ Mips_D4_64 = 341,
+ Mips_D5_64 = 342,
+ Mips_D6_64 = 343,
+ Mips_D7_64 = 344,
+ Mips_D8_64 = 345,
+ Mips_D9_64 = 346,
+ Mips_D10_64 = 347,
+ Mips_D11_64 = 348,
+ Mips_D12_64 = 349,
+ Mips_D13_64 = 350,
+ Mips_D14_64 = 351,
+ Mips_D15_64 = 352,
+ Mips_D16_64 = 353,
+ Mips_D17_64 = 354,
+ Mips_D18_64 = 355,
+ Mips_D19_64 = 356,
+ Mips_D20_64 = 357,
+ Mips_D21_64 = 358,
+ Mips_D22_64 = 359,
+ Mips_D23_64 = 360,
+ Mips_D24_64 = 361,
+ Mips_D25_64 = 362,
+ Mips_D26_64 = 363,
+ Mips_D27_64 = 364,
+ Mips_D28_64 = 365,
+ Mips_D29_64 = 366,
+ Mips_D30_64 = 367,
+ Mips_D31_64 = 368,
+ Mips_DSPOutFlag16_19 = 369,
+ Mips_HI0_64 = 370,
+ Mips_K0_64 = 371,
+ Mips_K1_64 = 372,
+ Mips_LO0_64 = 373,
+ Mips_S0_64 = 374,
+ Mips_S1_64 = 375,
+ Mips_S2_64 = 376,
+ Mips_S3_64 = 377,
+ Mips_S4_64 = 378,
+ Mips_S5_64 = 379,
+ Mips_S6_64 = 380,
+ Mips_S7_64 = 381,
+ Mips_T0_64 = 382,
+ Mips_T1_64 = 383,
+ Mips_T2_64 = 384,
+ Mips_T3_64 = 385,
+ Mips_T4_64 = 386,
+ Mips_T5_64 = 387,
+ Mips_T6_64 = 388,
+ Mips_T7_64 = 389,
+ Mips_T8_64 = 390,
+ Mips_T9_64 = 391,
+ Mips_V0_64 = 392,
+ Mips_V1_64 = 393,
+ Mips_NUM_TARGET_REGS // 394
+};
+
+// Register classes
+enum {
+ Mips_OddSPRegClassID = 0,
+ Mips_CCRRegClassID = 1,
+ Mips_COP2RegClassID = 2,
+ Mips_COP3RegClassID = 3,
+ Mips_DSPRRegClassID = 4,
+ Mips_FGR32RegClassID = 5,
+ Mips_FGRCCRegClassID = 6,
+ Mips_FGRH32RegClassID = 7,
+ Mips_GPR32RegClassID = 8,
+ Mips_HWRegsRegClassID = 9,
+ Mips_OddSP_with_sub_hiRegClassID = 10,
+ Mips_FGR32_and_OddSPRegClassID = 11,
+ Mips_FGRH32_and_OddSPRegClassID = 12,
+ Mips_OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID = 13,
+ Mips_CPU16RegsPlusSPRegClassID = 14,
+ Mips_CCRegClassID = 15,
+ Mips_CPU16RegsRegClassID = 16,
+ Mips_FCCRegClassID = 17,
+ Mips_GPRMM16RegClassID = 18,
+ Mips_GPRMM16MovePRegClassID = 19,
+ Mips_GPRMM16ZeroRegClassID = 20,
+ Mips_MSACtrlRegClassID = 21,
+ Mips_OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID = 22,
+ Mips_CPU16Regs_and_GPRMM16ZeroRegClassID = 23,
+ Mips_CPU16Regs_and_GPRMM16MovePRegClassID = 24,
+ Mips_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 25,
+ Mips_HI32DSPRegClassID = 26,
+ Mips_LO32DSPRegClassID = 27,
+ Mips_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 28,
+ Mips_CPURARegRegClassID = 29,
+ Mips_CPUSPRegRegClassID = 30,
+ Mips_DSPCCRegClassID = 31,
+ Mips_HI32RegClassID = 32,
+ Mips_LO32RegClassID = 33,
+ Mips_FGR64RegClassID = 34,
+ Mips_GPR64RegClassID = 35,
+ Mips_AFGR64RegClassID = 36,
+ Mips_FGR64_and_OddSPRegClassID = 37,
+ Mips_GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 38,
+ Mips_AFGR64_and_OddSPRegClassID = 39,
+ Mips_GPR64_with_sub_32_in_CPU16RegsRegClassID = 40,
+ Mips_GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 41,
+ Mips_GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 42,
+ Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 43,
+ Mips_ACC64DSPRegClassID = 44,
+ Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 45,
+ Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 46,
+ Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 47,
+ Mips_OCTEON_MPLRegClassID = 48,
+ Mips_OCTEON_PRegClassID = 49,
+ Mips_ACC64RegClassID = 50,
+ Mips_GPR64_with_sub_32_in_CPURARegRegClassID = 51,
+ Mips_GPR64_with_sub_32_in_CPUSPRegRegClassID = 52,
+ Mips_HI64RegClassID = 53,
+ Mips_LO64RegClassID = 54,
+ Mips_MSA128BRegClassID = 55,
+ Mips_MSA128DRegClassID = 56,
+ Mips_MSA128HRegClassID = 57,
+ Mips_MSA128WRegClassID = 58,
+ Mips_MSA128B_with_sub_64_in_OddSPRegClassID = 59,
+ Mips_MSA128WEvensRegClassID = 60,
+ Mips_ACC128RegClassID = 61,
+};
+
+#endif // GET_REGINFO_ENUM
+
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|*MC Register Information *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+
+
+#ifdef GET_REGINFO_MC_DESC
+#undef GET_REGINFO_MC_DESC
+
+static const MCPhysReg MipsRegDiffLists[] = {
+ /* 0 */ 0, 0,
+ /* 2 */ 4, 1, 1, 1, 1, 0,
+ /* 8 */ 364, 65286, 1, 1, 1, 0,
+ /* 14 */ 20, 1, 0,
+ /* 17 */ 21, 1, 0,
+ /* 20 */ 22, 1, 0,
+ /* 23 */ 23, 1, 0,
+ /* 26 */ 24, 1, 0,
+ /* 29 */ 25, 1, 0,
+ /* 32 */ 26, 1, 0,
+ /* 35 */ 27, 1, 0,
+ /* 38 */ 28, 1, 0,
+ /* 41 */ 29, 1, 0,
+ /* 44 */ 30, 1, 0,
+ /* 47 */ 31, 1, 0,
+ /* 50 */ 32, 1, 0,
+ /* 53 */ 33, 1, 0,
+ /* 56 */ 34, 1, 0,
+ /* 59 */ 35, 1, 0,
+ /* 62 */ 65439, 1, 0,
+ /* 65 */ 65513, 1, 0,
+ /* 68 */ 3, 0,
+ /* 70 */ 4, 0,
+ /* 72 */ 6, 0,
+ /* 74 */ 11, 0,
+ /* 76 */ 12, 0,
+ /* 78 */ 22, 0,
+ /* 80 */ 23, 0,
+ /* 82 */ 29, 0,
+ /* 84 */ 30, 0,
+ /* 86 */ 65308, 72, 0,
+ /* 89 */ 65346, 72, 0,
+ /* 92 */ 38, 65322, 73, 0,
+ /* 96 */ 95, 0,
+ /* 98 */ 96, 0,
+ /* 100 */ 106, 0,
+ /* 102 */ 187, 0,
+ /* 104 */ 219, 0,
+ /* 106 */ 258, 0,
+ /* 108 */ 266, 0,
+ /* 110 */ 310, 0,
+ /* 112 */ 65031, 0,
+ /* 114 */ 65108, 0,
+ /* 116 */ 65172, 0,
+ /* 118 */ 65226, 0,
+ /* 120 */ 65229, 0,
+ /* 122 */ 65270, 0,
+ /* 124 */ 65278, 0,
+ /* 126 */ 65295, 0,
+ /* 128 */ 65317, 0,
+ /* 130 */ 37, 65430, 103, 65395, 65333, 0,
+ /* 136 */ 65349, 0,
+ /* 138 */ 65395, 0,
+ /* 140 */ 65410, 0,
+ /* 142 */ 65415, 0,
+ /* 144 */ 65419, 0,
+ /* 146 */ 65420, 0,
+ /* 148 */ 65421, 0,
+ /* 150 */ 65422, 0,
+ /* 152 */ 65430, 0,
+ /* 154 */ 65440, 0,
+ /* 156 */ 65441, 0,
+ /* 158 */ 141, 65498, 0,
+ /* 161 */ 65516, 234, 65498, 0,
+ /* 165 */ 65515, 235, 65498, 0,
+ /* 169 */ 65514, 236, 65498, 0,
+ /* 173 */ 65513, 237, 65498, 0,
+ /* 177 */ 65512, 238, 65498, 0,
+ /* 181 */ 65511, 239, 65498, 0,
+ /* 185 */ 65510, 240, 65498, 0,
+ /* 189 */ 65509, 241, 65498, 0,
+ /* 193 */ 65508, 242, 65498, 0,
+ /* 197 */ 65507, 243, 65498, 0,
+ /* 201 */ 65506, 244, 65498, 0,
+ /* 205 */ 65505, 245, 65498, 0,
+ /* 209 */ 65504, 246, 65498, 0,
+ /* 213 */ 65503, 247, 65498, 0,
+ /* 217 */ 65502, 248, 65498, 0,
+ /* 221 */ 65501, 249, 65498, 0,
+ /* 225 */ 65500, 250, 65498, 0,
+ /* 229 */ 65295, 347, 65499, 0,
+ /* 233 */ 65333, 344, 65502, 0,
+ /* 237 */ 65507, 0,
+ /* 239 */ 65510, 0,
+ /* 241 */ 65511, 0,
+ /* 243 */ 65512, 0,
+ /* 245 */ 65516, 0,
+ /* 247 */ 65521, 0,
+ /* 249 */ 65522, 0,
+ /* 251 */ 65535, 0,
+};
+
+static const uint16_t MipsSubRegIdxLists[] = {
+ /* 0 */ 1, 0,
+ /* 2 */ 3, 4, 5, 6, 7, 0,
+ /* 8 */ 2, 9, 8, 0,
+ /* 12 */ 9, 1, 8, 10, 11, 0,
+};
+
+static const MCRegisterDesc MipsRegDesc[] = { // Descriptors
+ { 6, 0, 0, 0, 0, 0 },
+ { 2007, 1, 82, 1, 4017, 0 },
+ { 2010, 1, 1, 1, 4017, 0 },
+ { 2102, 1, 1, 1, 4017, 0 },
+ { 1973, 1, 1, 1, 4017, 0 },
+ { 2027, 8, 1, 2, 32, 4 },
+ { 2054, 1, 1, 1, 1089, 0 },
+ { 2071, 1, 1, 1, 1089, 0 },
+ { 1985, 1, 102, 1, 1089, 0 },
+ { 1988, 1, 104, 1, 1089, 0 },
+ { 2061, 1, 1, 1, 1089, 0 },
+ { 2000, 1, 1, 1, 1089, 0 },
+ { 1994, 1, 1, 1, 1089, 0 },
+ { 2038, 1, 1, 1, 1089, 0 },
+ { 2092, 1, 1, 1, 1089, 0 },
+ { 2081, 1, 1, 1, 1089, 0 },
+ { 2019, 1, 1, 1, 1089, 0 },
+ { 2045, 1, 1, 1, 1089, 0 },
+ { 1970, 1, 1, 1, 1089, 0 },
+ { 1967, 1, 106, 1, 1089, 0 },
+ { 1991, 1, 108, 1, 1089, 0 },
+ { 1980, 1, 110, 1, 1089, 0 },
+ { 152, 1, 110, 1, 1089, 0 },
+ { 365, 1, 110, 1, 1089, 0 },
+ { 537, 1, 110, 1, 1089, 0 },
+ { 703, 1, 110, 1, 1089, 0 },
+ { 155, 190, 110, 9, 1042, 10 },
+ { 368, 190, 1, 9, 1042, 10 },
+ { 540, 190, 1, 9, 1042, 10 },
+ { 706, 190, 1, 9, 1042, 10 },
+ { 1271, 237, 1, 0, 0, 2 },
+ { 160, 1, 1, 1, 1153, 0 },
+ { 373, 1, 1, 1, 1153, 0 },
+ { 545, 1, 1, 1, 1153, 0 },
+ { 711, 1, 1, 1, 1153, 0 },
+ { 1278, 1, 1, 1, 1153, 0 },
+ { 1412, 1, 1, 1, 1153, 0 },
+ { 1542, 1, 1, 1, 1153, 0 },
+ { 1672, 1, 1, 1, 1153, 0 },
+ { 70, 1, 1, 1, 1153, 0 },
+ { 283, 1, 1, 1, 1153, 0 },
+ { 496, 1, 1, 1, 1153, 0 },
+ { 662, 1, 1, 1, 1153, 0 },
+ { 820, 1, 1, 1, 1153, 0 },
+ { 1383, 1, 1, 1, 1153, 0 },
+ { 1513, 1, 1, 1, 1153, 0 },
+ { 1643, 1, 1, 1, 1153, 0 },
+ { 1773, 1, 1, 1, 1153, 0 },
+ { 1911, 1, 1, 1, 1153, 0 },
+ { 130, 1, 1, 1, 1153, 0 },
+ { 343, 1, 1, 1, 1153, 0 },
+ { 531, 1, 1, 1, 1153, 0 },
+ { 697, 1, 1, 1, 1153, 0 },
+ { 842, 1, 1, 1, 1153, 0 },
+ { 1405, 1, 1, 1, 1153, 0 },
+ { 1535, 1, 1, 1, 1153, 0 },
+ { 1665, 1, 1, 1, 1153, 0 },
+ { 1795, 1, 1, 1, 1153, 0 },
+ { 1933, 1, 1, 1, 1153, 0 },
+ { 0, 1, 1, 1, 1153, 0 },
+ { 213, 1, 1, 1, 1153, 0 },
+ { 426, 1, 1, 1, 1153, 0 },
+ { 592, 1, 1, 1, 1153, 0 },
+ { 750, 1, 1, 1, 1153, 0 },
+ { 1313, 1, 1, 1, 1153, 0 },
+ { 1447, 1, 1, 1, 1153, 0 },
+ { 1577, 1, 1, 1, 1153, 0 },
+ { 1707, 1, 1, 1, 1153, 0 },
+ { 1829, 1, 1, 1, 1153, 0 },
+ { 45, 1, 1, 1, 1153, 0 },
+ { 258, 1, 1, 1, 1153, 0 },
+ { 471, 1, 1, 1, 1153, 0 },
+ { 637, 1, 1, 1, 1153, 0 },
+ { 795, 1, 1, 1, 1153, 0 },
+ { 1358, 1, 1, 1, 1153, 0 },
+ { 1488, 1, 1, 1, 1153, 0 },
+ { 1618, 1, 1, 1, 1153, 0 },
+ { 1748, 1, 1, 1, 1153, 0 },
+ { 1886, 1, 1, 1, 1153, 0 },
+ { 105, 1, 1, 1, 1153, 0 },
+ { 318, 1, 1, 1, 1153, 0 },
+ { 7, 1, 1, 1, 1153, 0 },
+ { 220, 1, 1, 1, 1153, 0 },
+ { 433, 1, 1, 1, 1153, 0 },
+ { 599, 1, 1, 1, 1153, 0 },
+ { 757, 1, 1, 1, 1153, 0 },
+ { 1320, 1, 1, 1, 1153, 0 },
+ { 1454, 1, 1, 1, 1153, 0 },
+ { 1584, 1, 1, 1, 1153, 0 },
+ { 1714, 1, 1, 1, 1153, 0 },
+ { 1836, 1, 1, 1, 1153, 0 },
+ { 52, 1, 1, 1, 1153, 0 },
+ { 265, 1, 1, 1, 1153, 0 },
+ { 478, 1, 1, 1, 1153, 0 },
+ { 644, 1, 1, 1, 1153, 0 },
+ { 802, 1, 1, 1, 1153, 0 },
+ { 1365, 1, 1, 1, 1153, 0 },
+ { 1495, 1, 1, 1, 1153, 0 },
+ { 1625, 1, 1, 1, 1153, 0 },
+ { 1755, 1, 1, 1, 1153, 0 },
+ { 1893, 1, 1, 1, 1153, 0 },
+ { 112, 1, 1, 1, 1153, 0 },
+ { 325, 1, 1, 1, 1153, 0 },
+ { 164, 14, 1, 9, 994, 10 },
+ { 377, 17, 1, 9, 994, 10 },
+ { 549, 20, 1, 9, 994, 10 },
+ { 715, 23, 1, 9, 994, 10 },
+ { 1282, 26, 1, 9, 994, 10 },
+ { 1416, 29, 1, 9, 994, 10 },
+ { 1546, 32, 1, 9, 994, 10 },
+ { 1676, 35, 1, 9, 994, 10 },
+ { 1801, 38, 1, 9, 994, 10 },
+ { 1939, 41, 1, 9, 994, 10 },
+ { 14, 44, 1, 9, 994, 10 },
+ { 227, 47, 1, 9, 994, 10 },
+ { 440, 50, 1, 9, 994, 10 },
+ { 606, 53, 1, 9, 994, 10 },
+ { 764, 56, 1, 9, 994, 10 },
+ { 1327, 59, 1, 9, 994, 10 },
+ { 92, 1, 150, 1, 2401, 0 },
+ { 305, 1, 148, 1, 2401, 0 },
+ { 518, 1, 146, 1, 2401, 0 },
+ { 684, 1, 144, 1, 2401, 0 },
+ { 167, 1, 161, 1, 3985, 0 },
+ { 380, 1, 165, 1, 3985, 0 },
+ { 552, 1, 165, 1, 3985, 0 },
+ { 718, 1, 169, 1, 3985, 0 },
+ { 1285, 1, 169, 1, 3985, 0 },
+ { 1419, 1, 173, 1, 3985, 0 },
+ { 1549, 1, 173, 1, 3985, 0 },
+ { 1679, 1, 177, 1, 3985, 0 },
+ { 1804, 1, 177, 1, 3985, 0 },
+ { 1942, 1, 181, 1, 3985, 0 },
+ { 18, 1, 181, 1, 3985, 0 },
+ { 231, 1, 185, 1, 3985, 0 },
+ { 444, 1, 185, 1, 3985, 0 },
+ { 610, 1, 189, 1, 3985, 0 },
+ { 768, 1, 189, 1, 3985, 0 },
+ { 1331, 1, 193, 1, 3985, 0 },
+ { 1461, 1, 193, 1, 3985, 0 },
+ { 1591, 1, 197, 1, 3985, 0 },
+ { 1721, 1, 197, 1, 3985, 0 },
+ { 1843, 1, 201, 1, 3985, 0 },
+ { 59, 1, 201, 1, 3985, 0 },
+ { 272, 1, 205, 1, 3985, 0 },
+ { 485, 1, 205, 1, 3985, 0 },
+ { 651, 1, 209, 1, 3985, 0 },
+ { 809, 1, 209, 1, 3985, 0 },
+ { 1372, 1, 213, 1, 3985, 0 },
+ { 1502, 1, 213, 1, 3985, 0 },
+ { 1632, 1, 217, 1, 3985, 0 },
+ { 1762, 1, 217, 1, 3985, 0 },
+ { 1900, 1, 221, 1, 3985, 0 },
+ { 119, 1, 221, 1, 3985, 0 },
+ { 332, 1, 225, 1, 3985, 0 },
+ { 159, 1, 1, 1, 3985, 0 },
+ { 372, 1, 1, 1, 3985, 0 },
+ { 544, 1, 1, 1, 3985, 0 },
+ { 710, 1, 1, 1, 3985, 0 },
+ { 1277, 1, 1, 1, 3985, 0 },
+ { 1411, 1, 1, 1, 3985, 0 },
+ { 1541, 1, 1, 1, 3985, 0 },
+ { 1671, 1, 1, 1, 3985, 0 },
+ { 191, 1, 1, 1, 3985, 0 },
+ { 404, 1, 1, 1, 3985, 0 },
+ { 573, 1, 1, 1, 3985, 0 },
+ { 731, 1, 1, 1, 3985, 0 },
+ { 1294, 1, 1, 1, 3985, 0 },
+ { 1428, 1, 1, 1, 3985, 0 },
+ { 1558, 1, 1, 1, 3985, 0 },
+ { 1688, 1, 1, 1, 3985, 0 },
+ { 1813, 1, 1, 1, 3985, 0 },
+ { 1951, 1, 1, 1, 3985, 0 },
+ { 29, 1, 1, 1, 3985, 0 },
+ { 242, 1, 1, 1, 3985, 0 },
+ { 455, 1, 1, 1, 3985, 0 },
+ { 621, 1, 1, 1, 3985, 0 },
+ { 779, 1, 1, 1, 3985, 0 },
+ { 1342, 1, 1, 1, 3985, 0 },
+ { 1472, 1, 1, 1, 3985, 0 },
+ { 1602, 1, 1, 1, 3985, 0 },
+ { 1732, 1, 1, 1, 3985, 0 },
+ { 1854, 1, 1, 1, 3985, 0 },
+ { 76, 1, 1, 1, 3985, 0 },
+ { 289, 1, 1, 1, 3985, 0 },
+ { 502, 1, 1, 1, 3985, 0 },
+ { 668, 1, 1, 1, 3985, 0 },
+ { 826, 1, 1, 1, 3985, 0 },
+ { 1389, 1, 1, 1, 3985, 0 },
+ { 1519, 1, 1, 1, 3985, 0 },
+ { 1649, 1, 1, 1, 3985, 0 },
+ { 1779, 1, 1, 1, 3985, 0 },
+ { 1917, 1, 1, 1, 3985, 0 },
+ { 136, 1, 1, 1, 3985, 0 },
+ { 349, 1, 1, 1, 3985, 0 },
+ { 1253, 136, 1, 0, 1184, 2 },
+ { 170, 1, 158, 1, 3953, 0 },
+ { 383, 1, 158, 1, 3953, 0 },
+ { 555, 1, 158, 1, 3953, 0 },
+ { 721, 1, 158, 1, 3953, 0 },
+ { 1288, 1, 158, 1, 3953, 0 },
+ { 1422, 1, 158, 1, 3953, 0 },
+ { 1552, 1, 158, 1, 3953, 0 },
+ { 1682, 1, 158, 1, 3953, 0 },
+ { 1807, 1, 158, 1, 3953, 0 },
+ { 1945, 1, 158, 1, 3953, 0 },
+ { 22, 1, 158, 1, 3953, 0 },
+ { 235, 1, 158, 1, 3953, 0 },
+ { 448, 1, 158, 1, 3953, 0 },
+ { 614, 1, 158, 1, 3953, 0 },
+ { 772, 1, 158, 1, 3953, 0 },
+ { 1335, 1, 158, 1, 3953, 0 },
+ { 1465, 1, 158, 1, 3953, 0 },
+ { 1595, 1, 158, 1, 3953, 0 },
+ { 1725, 1, 158, 1, 3953, 0 },
+ { 1847, 1, 158, 1, 3953, 0 },
+ { 63, 1, 158, 1, 3953, 0 },
+ { 276, 1, 158, 1, 3953, 0 },
+ { 489, 1, 158, 1, 3953, 0 },
+ { 655, 1, 158, 1, 3953, 0 },
+ { 813, 1, 158, 1, 3953, 0 },
+ { 1376, 1, 158, 1, 3953, 0 },
+ { 1506, 1, 158, 1, 3953, 0 },
+ { 1636, 1, 158, 1, 3953, 0 },
+ { 1766, 1, 158, 1, 3953, 0 },
+ { 1904, 1, 158, 1, 3953, 0 },
+ { 123, 1, 158, 1, 3953, 0 },
+ { 336, 1, 158, 1, 3953, 0 },
+ { 1259, 128, 1, 0, 1216, 2 },
+ { 172, 1, 233, 1, 1826, 0 },
+ { 385, 1, 134, 1, 1826, 0 },
+ { 557, 1, 134, 1, 1826, 0 },
+ { 723, 1, 134, 1, 1826, 0 },
+ { 196, 1, 1, 1, 3921, 0 },
+ { 409, 1, 1, 1, 3921, 0 },
+ { 578, 1, 1, 1, 3921, 0 },
+ { 736, 1, 1, 1, 3921, 0 },
+ { 1299, 1, 1, 1, 3921, 0 },
+ { 1433, 1, 1, 1, 3921, 0 },
+ { 1563, 1, 1, 1, 3921, 0 },
+ { 1693, 1, 1, 1, 3921, 0 },
+ { 1818, 1, 1, 1, 3921, 0 },
+ { 1956, 1, 1, 1, 3921, 0 },
+ { 35, 1, 1, 1, 3921, 0 },
+ { 248, 1, 1, 1, 3921, 0 },
+ { 461, 1, 1, 1, 3921, 0 },
+ { 627, 1, 1, 1, 3921, 0 },
+ { 785, 1, 1, 1, 3921, 0 },
+ { 1348, 1, 1, 1, 3921, 0 },
+ { 1478, 1, 1, 1, 3921, 0 },
+ { 1608, 1, 1, 1, 3921, 0 },
+ { 1738, 1, 1, 1, 3921, 0 },
+ { 1860, 1, 1, 1, 3921, 0 },
+ { 82, 1, 1, 1, 3921, 0 },
+ { 295, 1, 1, 1, 3921, 0 },
+ { 508, 1, 1, 1, 3921, 0 },
+ { 674, 1, 1, 1, 3921, 0 },
+ { 832, 1, 1, 1, 3921, 0 },
+ { 1395, 1, 1, 1, 3921, 0 },
+ { 1525, 1, 1, 1, 3921, 0 },
+ { 1655, 1, 1, 1, 3921, 0 },
+ { 1785, 1, 1, 1, 3921, 0 },
+ { 1923, 1, 1, 1, 3921, 0 },
+ { 142, 1, 1, 1, 3921, 0 },
+ { 355, 1, 1, 1, 3921, 0 },
+ { 176, 1, 100, 1, 3921, 0 },
+ { 389, 1, 100, 1, 3921, 0 },
+ { 184, 1, 229, 1, 1794, 0 },
+ { 397, 1, 126, 1, 1794, 0 },
+ { 566, 1, 126, 1, 1794, 0 },
+ { 727, 1, 126, 1, 1794, 0 },
+ { 179, 1, 1, 1, 3889, 0 },
+ { 392, 1, 1, 1, 3889, 0 },
+ { 561, 1, 1, 1, 3889, 0 },
+ { 188, 1, 1, 1, 3889, 0 },
+ { 401, 1, 1, 1, 3889, 0 },
+ { 570, 1, 1, 1, 3889, 0 },
+ { 1239, 124, 1, 0, 1248, 2 },
+ { 201, 1, 98, 1, 3857, 0 },
+ { 414, 1, 98, 1, 3857, 0 },
+ { 583, 1, 98, 1, 3857, 0 },
+ { 741, 1, 98, 1, 3857, 0 },
+ { 1304, 1, 98, 1, 3857, 0 },
+ { 1438, 1, 98, 1, 3857, 0 },
+ { 1568, 1, 98, 1, 3857, 0 },
+ { 1698, 1, 98, 1, 3857, 0 },
+ { 1265, 122, 1, 0, 1280, 2 },
+ { 204, 1, 96, 1, 3825, 0 },
+ { 417, 1, 96, 1, 3825, 0 },
+ { 586, 1, 96, 1, 3825, 0 },
+ { 744, 1, 96, 1, 3825, 0 },
+ { 1307, 1, 96, 1, 3825, 0 },
+ { 1441, 1, 96, 1, 3825, 0 },
+ { 1571, 1, 96, 1, 3825, 0 },
+ { 1701, 1, 96, 1, 3825, 0 },
+ { 1823, 1, 96, 1, 3825, 0 },
+ { 1961, 1, 96, 1, 3825, 0 },
+ { 207, 1, 96, 1, 3825, 0 },
+ { 420, 1, 96, 1, 3825, 0 },
+ { 210, 92, 1, 8, 1425, 10 },
+ { 423, 92, 1, 8, 1425, 10 },
+ { 589, 92, 1, 8, 1425, 10 },
+ { 747, 92, 1, 8, 1425, 10 },
+ { 1310, 92, 1, 8, 1425, 10 },
+ { 1444, 92, 1, 8, 1425, 10 },
+ { 1574, 92, 1, 8, 1425, 10 },
+ { 1704, 92, 1, 8, 1425, 10 },
+ { 1826, 92, 1, 8, 1425, 10 },
+ { 1964, 92, 1, 8, 1425, 10 },
+ { 41, 92, 1, 8, 1425, 10 },
+ { 254, 92, 1, 8, 1425, 10 },
+ { 467, 92, 1, 8, 1425, 10 },
+ { 633, 92, 1, 8, 1425, 10 },
+ { 791, 92, 1, 8, 1425, 10 },
+ { 1354, 92, 1, 8, 1425, 10 },
+ { 1484, 92, 1, 8, 1425, 10 },
+ { 1614, 92, 1, 8, 1425, 10 },
+ { 1744, 92, 1, 8, 1425, 10 },
+ { 1866, 92, 1, 8, 1425, 10 },
+ { 88, 92, 1, 8, 1425, 10 },
+ { 301, 92, 1, 8, 1425, 10 },
+ { 514, 92, 1, 8, 1425, 10 },
+ { 680, 92, 1, 8, 1425, 10 },
+ { 838, 92, 1, 8, 1425, 10 },
+ { 1401, 92, 1, 8, 1425, 10 },
+ { 1531, 92, 1, 8, 1425, 10 },
+ { 1661, 92, 1, 8, 1425, 10 },
+ { 1791, 92, 1, 8, 1425, 10 },
+ { 1929, 92, 1, 8, 1425, 10 },
+ { 148, 92, 1, 8, 1425, 10 },
+ { 361, 92, 1, 8, 1425, 10 },
+ { 1245, 118, 1, 0, 1921, 2 },
+ { 869, 118, 1, 0, 1921, 2 },
+ { 947, 118, 1, 0, 1921, 2 },
+ { 997, 118, 1, 0, 1921, 2 },
+ { 1035, 118, 1, 0, 1921, 2 },
+ { 875, 130, 1, 12, 656, 10 },
+ { 882, 93, 159, 9, 1377, 10 },
+ { 953, 93, 159, 9, 1377, 10 },
+ { 1003, 93, 159, 9, 1377, 10 },
+ { 1041, 93, 159, 9, 1377, 10 },
+ { 1073, 93, 159, 9, 1377, 10 },
+ { 1105, 93, 159, 9, 1377, 10 },
+ { 1137, 93, 159, 9, 1377, 10 },
+ { 1169, 93, 159, 9, 1377, 10 },
+ { 1201, 93, 159, 9, 1377, 10 },
+ { 1227, 93, 159, 9, 1377, 10 },
+ { 848, 93, 159, 9, 1377, 10 },
+ { 926, 93, 159, 9, 1377, 10 },
+ { 983, 93, 159, 9, 1377, 10 },
+ { 1021, 93, 159, 9, 1377, 10 },
+ { 1059, 93, 159, 9, 1377, 10 },
+ { 1091, 93, 159, 9, 1377, 10 },
+ { 1123, 93, 159, 9, 1377, 10 },
+ { 1155, 93, 159, 9, 1377, 10 },
+ { 1187, 93, 159, 9, 1377, 10 },
+ { 1213, 93, 159, 9, 1377, 10 },
+ { 855, 93, 159, 9, 1377, 10 },
+ { 933, 93, 159, 9, 1377, 10 },
+ { 990, 93, 159, 9, 1377, 10 },
+ { 1028, 93, 159, 9, 1377, 10 },
+ { 1066, 93, 159, 9, 1377, 10 },
+ { 1098, 93, 159, 9, 1377, 10 },
+ { 1130, 93, 159, 9, 1377, 10 },
+ { 1162, 93, 159, 9, 1377, 10 },
+ { 1194, 93, 159, 9, 1377, 10 },
+ { 1220, 93, 159, 9, 1377, 10 },
+ { 862, 93, 159, 9, 1377, 10 },
+ { 940, 93, 159, 9, 1377, 10 },
+ { 1870, 1, 116, 1, 1120, 0 },
+ { 888, 138, 235, 0, 1344, 2 },
+ { 895, 152, 1, 0, 2241, 2 },
+ { 959, 152, 1, 0, 2241, 2 },
+ { 901, 152, 231, 0, 1312, 2 },
+ { 908, 154, 1, 0, 2273, 2 },
+ { 965, 154, 1, 0, 2273, 2 },
+ { 1009, 154, 1, 0, 2273, 2 },
+ { 1047, 154, 1, 0, 2273, 2 },
+ { 1079, 154, 1, 0, 2273, 2 },
+ { 1111, 154, 1, 0, 2273, 2 },
+ { 1143, 154, 1, 0, 2273, 2 },
+ { 1175, 154, 1, 0, 2273, 2 },
+ { 914, 156, 1, 0, 2273, 2 },
+ { 971, 156, 1, 0, 2273, 2 },
+ { 1015, 156, 1, 0, 2273, 2 },
+ { 1053, 156, 1, 0, 2273, 2 },
+ { 1085, 156, 1, 0, 2273, 2 },
+ { 1117, 156, 1, 0, 2273, 2 },
+ { 1149, 156, 1, 0, 2273, 2 },
+ { 1181, 156, 1, 0, 2273, 2 },
+ { 1207, 156, 1, 0, 2273, 2 },
+ { 1233, 156, 1, 0, 2273, 2 },
+ { 920, 156, 1, 0, 2273, 2 },
+ { 977, 156, 1, 0, 2273, 2 },
+};
+
+ // OddSP Register Class...
+ static const MCPhysReg OddSP[] = {
+ Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31, Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31, Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64,
+ };
+
+ // OddSP Bit set.
+ static const uint8_t OddSPBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x50, 0x55, 0x55, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
+ };
+
+ // CCR Register Class...
+ static const MCPhysReg CCR[] = {
+ Mips_FCR0, Mips_FCR1, Mips_FCR2, Mips_FCR3, Mips_FCR4, Mips_FCR5, Mips_FCR6, Mips_FCR7, Mips_FCR8, Mips_FCR9, Mips_FCR10, Mips_FCR11, Mips_FCR12, Mips_FCR13, Mips_FCR14, Mips_FCR15, Mips_FCR16, Mips_FCR17, Mips_FCR18, Mips_FCR19, Mips_FCR20, Mips_FCR21, Mips_FCR22, Mips_FCR23, Mips_FCR24, Mips_FCR25, Mips_FCR26, Mips_FCR27, Mips_FCR28, Mips_FCR29, Mips_FCR30, Mips_FCR31,
+ };
+
+ // CCR Bit set.
+ static const uint8_t CCRBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
+ };
+
+ // COP2 Register Class...
+ static const MCPhysReg COP2[] = {
+ Mips_COP20, Mips_COP21, Mips_COP22, Mips_COP23, Mips_COP24, Mips_COP25, Mips_COP26, Mips_COP27, Mips_COP28, Mips_COP29, Mips_COP210, Mips_COP211, Mips_COP212, Mips_COP213, Mips_COP214, Mips_COP215, Mips_COP216, Mips_COP217, Mips_COP218, Mips_COP219, Mips_COP220, Mips_COP221, Mips_COP222, Mips_COP223, Mips_COP224, Mips_COP225, Mips_COP226, Mips_COP227, Mips_COP228, Mips_COP229, Mips_COP230, Mips_COP231,
+ };
+
+ // COP2 Bit set.
+ static const uint8_t COP2Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0xf8, 0xff, 0xff, 0x01,
+ };
+
+ // COP3 Register Class...
+ static const MCPhysReg COP3[] = {
+ Mips_COP30, Mips_COP31, Mips_COP32, Mips_COP33, Mips_COP34, Mips_COP35, Mips_COP36, Mips_COP37, Mips_COP38, Mips_COP39, Mips_COP310, Mips_COP311, Mips_COP312, Mips_COP313, Mips_COP314, Mips_COP315, Mips_COP316, Mips_COP317, Mips_COP318, Mips_COP319, Mips_COP320, Mips_COP321, Mips_COP322, Mips_COP323, Mips_COP324, Mips_COP325, Mips_COP326, Mips_COP327, Mips_COP328, Mips_COP329, Mips_COP330, Mips_COP331,
+ };
+
+ // COP3 Bit set.
+ static const uint8_t COP3Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0xfe, 0xff, 0x7f,
+ };
+
+ // DSPR Register Class...
+ static const MCPhysReg DSPR[] = {
+ Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA,
+ };
+
+ // DSPR Bit set.
+ static const uint8_t DSPRBits[] = {
+ 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07,
+ };
+
+ // FGR32 Register Class...
+ static const MCPhysReg FGR32[] = {
+ Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31,
+ };
+
+ // FGR32 Bit set.
+ static const uint8_t FGR32Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
+ };
+
+ // FGRCC Register Class...
+ static const MCPhysReg FGRCC[] = {
+ Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31,
+ };
+
+ // FGRCC Bit set.
+ static const uint8_t FGRCCBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
+ };
+
+ // FGRH32 Register Class...
+ static const MCPhysReg FGRH32[] = {
+ Mips_F_HI0, Mips_F_HI1, Mips_F_HI2, Mips_F_HI3, Mips_F_HI4, Mips_F_HI5, Mips_F_HI6, Mips_F_HI7, Mips_F_HI8, Mips_F_HI9, Mips_F_HI10, Mips_F_HI11, Mips_F_HI12, Mips_F_HI13, Mips_F_HI14, Mips_F_HI15, Mips_F_HI16, Mips_F_HI17, Mips_F_HI18, Mips_F_HI19, Mips_F_HI20, Mips_F_HI21, Mips_F_HI22, Mips_F_HI23, Mips_F_HI24, Mips_F_HI25, Mips_F_HI26, Mips_F_HI27, Mips_F_HI28, Mips_F_HI29, Mips_F_HI30, Mips_F_HI31,
+ };
+
+ // FGRH32 Bit set.
+ static const uint8_t FGRH32Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
+ };
+
+ // GPR32 Register Class...
+ static const MCPhysReg GPR32[] = {
+ Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA,
+ };
+
+ // GPR32 Bit set.
+ static const uint8_t GPR32Bits[] = {
+ 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07,
+ };
+
+ // HWRegs Register Class...
+ static const MCPhysReg HWRegs[] = {
+ Mips_HWR0, Mips_HWR1, Mips_HWR2, Mips_HWR3, Mips_HWR4, Mips_HWR5, Mips_HWR6, Mips_HWR7, Mips_HWR8, Mips_HWR9, Mips_HWR10, Mips_HWR11, Mips_HWR12, Mips_HWR13, Mips_HWR14, Mips_HWR15, Mips_HWR16, Mips_HWR17, Mips_HWR18, Mips_HWR19, Mips_HWR20, Mips_HWR21, Mips_HWR22, Mips_HWR23, Mips_HWR24, Mips_HWR25, Mips_HWR26, Mips_HWR27, Mips_HWR28, Mips_HWR29, Mips_HWR30, Mips_HWR31,
+ };
+
+ // HWRegs Bit set.
+ static const uint8_t HWRegsBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
+ };
+
+ // OddSP_with_sub_hi Register Class...
+ static const MCPhysReg OddSP_with_sub_hi[] = {
+ Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64,
+ };
+
+ // OddSP_with_sub_hi Bit set.
+ static const uint8_t OddSP_with_sub_hiBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
+ };
+
+ // FGR32_and_OddSP Register Class...
+ static const MCPhysReg FGR32_and_OddSP[] = {
+ Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31,
+ };
+
+ // FGR32_and_OddSP Bit set.
+ static const uint8_t FGR32_and_OddSPBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05,
+ };
+
+ // FGRH32_and_OddSP Register Class...
+ static const MCPhysReg FGRH32_and_OddSP[] = {
+ Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31,
+ };
+
+ // FGRH32_and_OddSP Bit set.
+ static const uint8_t FGRH32_and_OddSPBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a,
+ };
+
+ // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Register Class...
+ static const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGRH32[] = {
+ Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64,
+ };
+
+ // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Bit set.
+ static const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
+ };
+
+ // CPU16RegsPlusSP Register Class...
+ static const MCPhysReg CPU16RegsPlusSP[] = {
+ Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, Mips_SP,
+ };
+
+ // CPU16RegsPlusSP Bit set.
+ static const uint8_t CPU16RegsPlusSPBits[] = {
+ 0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
+ };
+
+ // CC Register Class...
+ static const MCPhysReg CC[] = {
+ Mips_CC0, Mips_CC1, Mips_CC2, Mips_CC3, Mips_CC4, Mips_CC5, Mips_CC6, Mips_CC7,
+ };
+
+ // CC Bit set.
+ static const uint8_t CCBits[] = {
+ 0x00, 0x00, 0x00, 0x80, 0x7f,
+ };
+
+ // CPU16Regs Register Class...
+ static const MCPhysReg CPU16Regs[] = {
+ Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1,
+ };
+
+ // CPU16Regs Bit set.
+ static const uint8_t CPU16RegsBits[] = {
+ 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
+ };
+
+ // FCC Register Class...
+ static const MCPhysReg FCC[] = {
+ Mips_FCC0, Mips_FCC1, Mips_FCC2, Mips_FCC3, Mips_FCC4, Mips_FCC5, Mips_FCC6, Mips_FCC7,
+ };
+
+ // FCC Bit set.
+ static const uint8_t FCCBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
+ };
+
+ // GPRMM16 Register Class...
+ static const MCPhysReg GPRMM16[] = {
+ Mips_S0, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3,
+ };
+
+ // GPRMM16 Bit set.
+ static const uint8_t GPRMM16Bits[] = {
+ 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
+ };
+
+ // GPRMM16MoveP Register Class...
+ static const MCPhysReg GPRMM16MoveP[] = {
+ Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_S0, Mips_S2, Mips_S3, Mips_S4,
+ };
+
+ // GPRMM16MoveP Bit set.
+ static const uint8_t GPRMM16MovePBits[] = {
+ 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,
+ };
+
+ // GPRMM16Zero Register Class...
+ static const MCPhysReg GPRMM16Zero[] = {
+ Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3,
+ };
+
+ // GPRMM16Zero Bit set.
+ static const uint8_t GPRMM16ZeroBits[] = {
+ 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
+ };
+
+ // MSACtrl Register Class...
+ static const MCPhysReg MSACtrl[] = {
+ Mips_MSAIR, Mips_MSACSR, Mips_MSAAccess, Mips_MSASave, Mips_MSAModify, Mips_MSARequest, Mips_MSAMap, Mips_MSAUnmap,
+ };
+
+ // MSACtrl Bit set.
+ static const uint8_t MSACtrlBits[] = {
+ 0x00, 0xfc, 0x03,
+ };
+
+ // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Register Class...
+ static const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGR32[] = {
+ Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15,
+ };
+
+ // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Bit set.
+ static const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
+ };
+
+ // CPU16Regs_and_GPRMM16Zero Register Class...
+ static const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = {
+ Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3,
+ };
+
+ // CPU16Regs_and_GPRMM16Zero Bit set.
+ static const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = {
+ 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
+ };
+
+ // CPU16Regs_and_GPRMM16MoveP Register Class...
+ static const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = {
+ Mips_S1, Mips_V0, Mips_V1, Mips_S0,
+ };
+
+ // CPU16Regs_and_GPRMM16MoveP Bit set.
+ static const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
+ };
+
+ // GPRMM16MoveP_and_GPRMM16Zero Register Class...
+ static const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = {
+ Mips_ZERO, Mips_S1, Mips_V0, Mips_V1,
+ };
+
+ // GPRMM16MoveP_and_GPRMM16Zero Bit set.
+ static const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
+ 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
+ };
+
+ // HI32DSP Register Class...
+ static const MCPhysReg HI32DSP[] = {
+ Mips_HI0, Mips_HI1, Mips_HI2, Mips_HI3,
+ };
+
+ // HI32DSP Bit set.
+ static const uint8_t HI32DSPBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
+ };
+
+ // LO32DSP Register Class...
+ static const MCPhysReg LO32DSP[] = {
+ Mips_LO0, Mips_LO1, Mips_LO2, Mips_LO3,
+ };
+
+ // LO32DSP Bit set.
+ static const uint8_t LO32DSPBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
+ };
+
+ // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
+ static const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
+ Mips_S1, Mips_V0, Mips_V1,
+ };
+
+ // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
+ static const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
+ };
+
+ // CPURAReg Register Class...
+ static const MCPhysReg CPURAReg[] = {
+ Mips_RA,
+ };
+
+ // CPURAReg Bit set.
+ static const uint8_t CPURARegBits[] = {
+ 0x00, 0x00, 0x08,
+ };
+
+ // CPUSPReg Register Class...
+ static const MCPhysReg CPUSPReg[] = {
+ Mips_SP,
+ };
+
+ // CPUSPReg Bit set.
+ static const uint8_t CPUSPRegBits[] = {
+ 0x00, 0x00, 0x10,
+ };
+
+ // DSPCC Register Class...
+ static const MCPhysReg DSPCC[] = {
+ Mips_DSPCCond,
+ };
+
+ // DSPCC Bit set.
+ static const uint8_t DSPCCBits[] = {
+ 0x04,
+ };
+
+ // HI32 Register Class...
+ static const MCPhysReg HI32[] = {
+ Mips_HI0,
+ };
+
+ // HI32 Bit set.
+ static const uint8_t HI32Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
+ };
+
+ // LO32 Register Class...
+ static const MCPhysReg LO32[] = {
+ Mips_LO0,
+ };
+
+ // LO32 Bit set.
+ static const uint8_t LO32Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+ };
+
+ // FGR64 Register Class...
+ static const MCPhysReg FGR64[] = {
+ Mips_D0_64, Mips_D1_64, Mips_D2_64, Mips_D3_64, Mips_D4_64, Mips_D5_64, Mips_D6_64, Mips_D7_64, Mips_D8_64, Mips_D9_64, Mips_D10_64, Mips_D11_64, Mips_D12_64, Mips_D13_64, Mips_D14_64, Mips_D15_64, Mips_D16_64, Mips_D17_64, Mips_D18_64, Mips_D19_64, Mips_D20_64, Mips_D21_64, Mips_D22_64, Mips_D23_64, Mips_D24_64, Mips_D25_64, Mips_D26_64, Mips_D27_64, Mips_D28_64, Mips_D29_64, Mips_D30_64, Mips_D31_64,
+ };
+
+ // FGR64 Bit set.
+ static const uint8_t FGR64Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
+ };
+
+ // GPR64 Register Class...
+ static const MCPhysReg GPR64[] = {
+ Mips_ZERO_64, Mips_AT_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_T0_64, Mips_T1_64, Mips_T2_64, Mips_T3_64, Mips_T4_64, Mips_T5_64, Mips_T6_64, Mips_T7_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, Mips_S5_64, Mips_S6_64, Mips_S7_64, Mips_T8_64, Mips_T9_64, Mips_K0_64, Mips_K1_64, Mips_GP_64, Mips_SP_64, Mips_FP_64, Mips_RA_64,
+ };
+
+ // GPR64 Bit set.
+ static const uint8_t GPR64Bits[] = {
+ 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,
+ };
+
+ // AFGR64 Register Class...
+ static const MCPhysReg AFGR64[] = {
+ Mips_D0, Mips_D1, Mips_D2, Mips_D3, Mips_D4, Mips_D5, Mips_D6, Mips_D7, Mips_D8, Mips_D9, Mips_D10, Mips_D11, Mips_D12, Mips_D13, Mips_D14, Mips_D15,
+ };
+
+ // AFGR64 Bit set.
+ static const uint8_t AFGR64Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
+ };
+
+ // FGR64_and_OddSP Register Class...
+ static const MCPhysReg FGR64_and_OddSP[] = {
+ Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64,
+ };
+
+ // FGR64_and_OddSP Bit set.
+ static const uint8_t FGR64_and_OddSPBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
+ };
+
+ // GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class...
+ static const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = {
+ Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, Mips_SP_64,
+ };
+
+ // GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set.
+ static const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
+ };
+
+ // AFGR64_and_OddSP Register Class...
+ static const MCPhysReg AFGR64_and_OddSP[] = {
+ Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15,
+ };
+
+ // AFGR64_and_OddSP Bit set.
+ static const uint8_t AFGR64_and_OddSPBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
+ };
+
+ // GPR64_with_sub_32_in_CPU16Regs Register Class...
+ static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = {
+ Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64,
+ };
+
+ // GPR64_with_sub_32_in_CPU16Regs Bit set.
+ static const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
+ };
+
+ // GPR64_with_sub_32_in_GPRMM16MoveP Register Class...
+ static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = {
+ Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64,
+ };
+
+ // GPR64_with_sub_32_in_GPRMM16MoveP Bit set.
+ static const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,
+ };
+
+ // GPR64_with_sub_32_in_GPRMM16Zero Register Class...
+ static const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = {
+ Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64,
+ };
+
+ // GPR64_with_sub_32_in_GPRMM16Zero Bit set.
+ static const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
+ };
+
+ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class...
+ static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = {
+ Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64,
+ };
+
+ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set.
+ static const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
+ };
+
+ // ACC64DSP Register Class...
+ static const MCPhysReg ACC64DSP[] = {
+ Mips_AC0, Mips_AC1, Mips_AC2, Mips_AC3,
+ };
+
+ // ACC64DSP Bit set.
+ static const uint8_t ACC64DSPBits[] = {
+ 0x00, 0x00, 0x00, 0x3c,
+ };
+
+ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class...
+ static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = {
+ Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64,
+ };
+
+ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set.
+ static const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
+ };
+
+ // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class...
+ static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = {
+ Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S1_64,
+ };
+
+ // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set.
+ static const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
+ };
+
+ // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
+ static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
+ Mips_V0_64, Mips_V1_64, Mips_S1_64,
+ };
+
+ // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
+ static const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
+ };
+
+ // OCTEON_MPL Register Class...
+ static const MCPhysReg OCTEON_MPL[] = {
+ Mips_MPL0, Mips_MPL1, Mips_MPL2,
+ };
+
+ // OCTEON_MPL Bit set.
+ static const uint8_t OCTEON_MPLBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03,
+ };
+
+ // OCTEON_P Register Class...
+ static const MCPhysReg OCTEON_P[] = {
+ Mips_P0, Mips_P1, Mips_P2,
+ };
+
+ // OCTEON_P Bit set.
+ static const uint8_t OCTEON_PBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,
+ };
+
+ // ACC64 Register Class...
+ static const MCPhysReg ACC64[] = {
+ Mips_AC0,
+ };
+
+ // ACC64 Bit set.
+ static const uint8_t ACC64Bits[] = {
+ 0x00, 0x00, 0x00, 0x04,
+ };
+
+ // GPR64_with_sub_32_in_CPURAReg Register Class...
+ static const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = {
+ Mips_RA_64,
+ };
+
+ // GPR64_with_sub_32_in_CPURAReg Bit set.
+ static const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
+ };
+
+ // GPR64_with_sub_32_in_CPUSPReg Register Class...
+ static const MCPhysReg GPR64_with_sub_32_in_CPUSPReg[] = {
+ Mips_SP_64,
+ };
+
+ // GPR64_with_sub_32_in_CPUSPReg Bit set.
+ static const uint8_t GPR64_with_sub_32_in_CPUSPRegBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
+ };
+
+ // HI64 Register Class...
+ static const MCPhysReg HI64[] = {
+ Mips_HI0_64,
+ };
+
+ // HI64 Bit set.
+ static const uint8_t HI64Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
+ };
+
+ // LO64 Register Class...
+ static const MCPhysReg LO64[] = {
+ Mips_LO0_64,
+ };
+
+ // LO64 Bit set.
+ static const uint8_t LO64Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
+ };
+
+ // MSA128B Register Class...
+ static const MCPhysReg MSA128B[] = {
+ Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31,
+ };
+
+ // MSA128B Bit set.
+ static const uint8_t MSA128BBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
+ };
+
+ // MSA128D Register Class...
+ static const MCPhysReg MSA128D[] = {
+ Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31,
+ };
+
+ // MSA128D Bit set.
+ static const uint8_t MSA128DBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
+ };
+
+ // MSA128H Register Class...
+ static const MCPhysReg MSA128H[] = {
+ Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31,
+ };
+
+ // MSA128H Bit set.
+ static const uint8_t MSA128HBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
+ };
+
+ // MSA128W Register Class...
+ static const MCPhysReg MSA128W[] = {
+ Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31,
+ };
+
+ // MSA128W Bit set.
+ static const uint8_t MSA128WBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
+ };
+
+ // MSA128B_with_sub_64_in_OddSP Register Class...
+ static const MCPhysReg MSA128B_with_sub_64_in_OddSP[] = {
+ Mips_W1, Mips_W3, Mips_W5, Mips_W7, Mips_W9, Mips_W11, Mips_W13, Mips_W15, Mips_W17, Mips_W19, Mips_W21, Mips_W23, Mips_W25, Mips_W27, Mips_W29, Mips_W31,
+ };
+
+ // MSA128B_with_sub_64_in_OddSP Bit set.
+ static const uint8_t MSA128B_with_sub_64_in_OddSPBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05,
+ };
+
+ // MSA128WEvens Register Class...
+ static const MCPhysReg MSA128WEvens[] = {
+ Mips_W0, Mips_W2, Mips_W4, Mips_W6, Mips_W8, Mips_W10, Mips_W12, Mips_W14, Mips_W16, Mips_W18, Mips_W20, Mips_W22, Mips_W24, Mips_W26, Mips_W28, Mips_W30,
+ };
+
+ // MSA128WEvens Bit set.
+ static const uint8_t MSA128WEvensBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02,
+ };
+
+ // ACC128 Register Class...
+ static const MCPhysReg ACC128[] = {
+ Mips_AC0_64,
+ };
+
+ // ACC128 Bit set.
+ static const uint8_t ACC128Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+ };
+
+static const MCRegisterClass MipsMCRegisterClasses[] = {
+ { OddSP, OddSPBits, sizeof(OddSPBits) },
+ { CCR, CCRBits, sizeof(CCRBits) },
+ { COP2, COP2Bits, sizeof(COP2Bits) },
+ { COP3, COP3Bits, sizeof(COP3Bits) },
+ { DSPR, DSPRBits, sizeof(DSPRBits) },
+ { FGR32, FGR32Bits, sizeof(FGR32Bits) },
+ { FGRCC, FGRCCBits, sizeof(FGRCCBits) },
+ { FGRH32, FGRH32Bits, sizeof(FGRH32Bits) },
+ { GPR32, GPR32Bits, sizeof(GPR32Bits) },
+ { HWRegs, HWRegsBits, sizeof(HWRegsBits) },
+ { OddSP_with_sub_hi, OddSP_with_sub_hiBits, sizeof(OddSP_with_sub_hiBits) },
+ { FGR32_and_OddSP, FGR32_and_OddSPBits, sizeof(FGR32_and_OddSPBits) },
+ { FGRH32_and_OddSP, FGRH32_and_OddSPBits, sizeof(FGRH32_and_OddSPBits) },
+ { OddSP_with_sub_hi_with_sub_hi_in_FGRH32, OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits) },
+ { CPU16RegsPlusSP, CPU16RegsPlusSPBits, sizeof(CPU16RegsPlusSPBits) },
+ { CC, CCBits, sizeof(CCBits) },
+ { CPU16Regs, CPU16RegsBits, sizeof(CPU16RegsBits) },
+ { FCC, FCCBits, sizeof(FCCBits) },
+ { GPRMM16, GPRMM16Bits, sizeof(GPRMM16Bits) },
+ { GPRMM16MoveP, GPRMM16MovePBits, sizeof(GPRMM16MovePBits) },
+ { GPRMM16Zero, GPRMM16ZeroBits, sizeof(GPRMM16ZeroBits) },
+ { MSACtrl, MSACtrlBits, sizeof(MSACtrlBits) },
+ { OddSP_with_sub_hi_with_sub_hi_in_FGR32, OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits) },
+ { CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, sizeof(CPU16Regs_and_GPRMM16ZeroBits) },
+ { CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, sizeof(CPU16Regs_and_GPRMM16MovePBits) },
+ { GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits) },
+ { HI32DSP, HI32DSPBits, sizeof(HI32DSPBits) },
+ { LO32DSP, LO32DSPBits, sizeof(LO32DSPBits) },
+ { GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits) },
+ { CPURAReg, CPURARegBits, sizeof(CPURARegBits) },
+ { CPUSPReg, CPUSPRegBits, sizeof(CPUSPRegBits) },
+ { DSPCC, DSPCCBits, sizeof(DSPCCBits) },
+ { HI32, HI32Bits, sizeof(HI32Bits) },
+ { LO32, LO32Bits, sizeof(LO32Bits) },
+ { FGR64, FGR64Bits, sizeof(FGR64Bits) },
+ { GPR64, GPR64Bits, sizeof(GPR64Bits) },
+ { AFGR64, AFGR64Bits, sizeof(AFGR64Bits) },
+ { FGR64_and_OddSP, FGR64_and_OddSPBits, sizeof(FGR64_and_OddSPBits) },
+ { GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits) },
+ { AFGR64_and_OddSP, AFGR64_and_OddSPBits, sizeof(AFGR64_and_OddSPBits) },
+ { GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, sizeof(GPR64_with_sub_32_in_CPU16RegsBits) },
+ { GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits) },
+ { GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits) },
+ { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits) },
+ { ACC64DSP, ACC64DSPBits, sizeof(ACC64DSPBits) },
+ { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits) },
+ { GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits) },
+ { GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits) },
+ { OCTEON_MPL, OCTEON_MPLBits, sizeof(OCTEON_MPLBits) },
+ { OCTEON_P, OCTEON_PBits, sizeof(OCTEON_PBits) },
+ { ACC64, ACC64Bits, sizeof(ACC64Bits) },
+ { GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, sizeof(GPR64_with_sub_32_in_CPURARegBits) },
+ { GPR64_with_sub_32_in_CPUSPReg, GPR64_with_sub_32_in_CPUSPRegBits, sizeof(GPR64_with_sub_32_in_CPUSPRegBits) },
+ { HI64, HI64Bits, sizeof(HI64Bits) },
+ { LO64, LO64Bits, sizeof(LO64Bits) },
+ { MSA128B, MSA128BBits, sizeof(MSA128BBits) },
+ { MSA128D, MSA128DBits, sizeof(MSA128DBits) },
+ { MSA128H, MSA128HBits, sizeof(MSA128HBits) },
+ { MSA128W, MSA128WBits, sizeof(MSA128WBits) },
+ { MSA128B_with_sub_64_in_OddSP, MSA128B_with_sub_64_in_OddSPBits, sizeof(MSA128B_with_sub_64_in_OddSPBits) },
+ { MSA128WEvens, MSA128WEvensBits, sizeof(MSA128WEvensBits) },
+ { ACC128, ACC128Bits, sizeof(ACC128Bits) },
+};
+
+#endif // GET_REGINFO_MC_DESC
diff --git a/capstone/arch/Mips/MipsGenSubtargetInfo.inc b/capstone/arch/Mips/MipsGenSubtargetInfo.inc
new file mode 100644
index 000000000..36e7a7f86
--- /dev/null
+++ b/capstone/arch/Mips/MipsGenSubtargetInfo.inc
@@ -0,0 +1,52 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|*Subtarget Enumeration Source Fragment *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+#define Mips_FeatureCnMips (1ULL << 0)
+#define Mips_FeatureDSP (1ULL << 1)
+#define Mips_FeatureDSPR2 (1ULL << 2)
+#define Mips_FeatureFP64Bit (1ULL << 3)
+#define Mips_FeatureFPXX (1ULL << 4)
+#define Mips_FeatureGP64Bit (1ULL << 5)
+#define Mips_FeatureMSA (1ULL << 6)
+#define Mips_FeatureMicroMips (1ULL << 7)
+#define Mips_FeatureMips1 (1ULL << 8)
+#define Mips_FeatureMips2 (1ULL << 9)
+#define Mips_FeatureMips3 (1ULL << 10)
+#define Mips_FeatureMips3_32 (1ULL << 11)
+#define Mips_FeatureMips3_32r2 (1ULL << 12)
+#define Mips_FeatureMips4 (1ULL << 13)
+#define Mips_FeatureMips4_32 (1ULL << 14)
+#define Mips_FeatureMips4_32r2 (1ULL << 15)
+#define Mips_FeatureMips5 (1ULL << 16)
+#define Mips_FeatureMips5_32r2 (1ULL << 17)
+#define Mips_FeatureMips16 (1ULL << 18)
+#define Mips_FeatureMips32 (1ULL << 19)
+#define Mips_FeatureMips32r2 (1ULL << 20)
+#define Mips_FeatureMips32r3 (1ULL << 21)
+#define Mips_FeatureMips32r5 (1ULL << 22)
+#define Mips_FeatureMips32r6 (1ULL << 23)
+#define Mips_FeatureMips64 (1ULL << 24)
+#define Mips_FeatureMips64r2 (1ULL << 25)
+#define Mips_FeatureMips64r3 (1ULL << 26)
+#define Mips_FeatureMips64r5 (1ULL << 27)
+#define Mips_FeatureMips64r6 (1ULL << 28)
+#define Mips_FeatureNaN2008 (1ULL << 29)
+#define Mips_FeatureNoABICalls (1ULL << 30)
+#define Mips_FeatureNoOddSPReg (1ULL << 31)
+#define Mips_FeatureSingleFloat (1ULL << 32)
+#define Mips_FeatureVFPU (1ULL << 33)
+
+#endif // GET_SUBTARGETINFO_ENUM
+
diff --git a/capstone/arch/Mips/MipsInstPrinter.c b/capstone/arch/Mips/MipsInstPrinter.c
new file mode 100644
index 000000000..9bbf4bc2e
--- /dev/null
+++ b/capstone/arch/Mips/MipsInstPrinter.c
@@ -0,0 +1,424 @@
+//===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an Mips MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifdef CAPSTONE_HAS_MIPS
+
+#include <capstone/platform.h>
+#include <stdlib.h>
+#include <stdio.h> // debug
+#include <string.h>
+
+#include "MipsInstPrinter.h"
+#include "../../MCInst.h"
+#include "../../utils.h"
+#include "../../SStream.h"
+#include "../../MCRegisterInfo.h"
+#include "MipsMapping.h"
+
+#include "MipsInstPrinter.h"
+
+static void printUnsignedImm(MCInst *MI, int opNum, SStream *O);
+static char *printAliasInstr(MCInst *MI, SStream *O, void *info);
+static char *printAlias(MCInst *MI, SStream *OS);
+
+// These enumeration declarations were originally in MipsInstrInfo.h but
+// had to be moved here to avoid circular dependencies between
+// LLVMMipsCodeGen and LLVMMipsAsmPrinter.
+
+// Mips Condition Codes
+typedef enum Mips_CondCode {
+ // To be used with float branch True
+ Mips_FCOND_F,
+ Mips_FCOND_UN,
+ Mips_FCOND_OEQ,
+ Mips_FCOND_UEQ,
+ Mips_FCOND_OLT,
+ Mips_FCOND_ULT,
+ Mips_FCOND_OLE,
+ Mips_FCOND_ULE,
+ Mips_FCOND_SF,
+ Mips_FCOND_NGLE,
+ Mips_FCOND_SEQ,
+ Mips_FCOND_NGL,
+ Mips_FCOND_LT,
+ Mips_FCOND_NGE,
+ Mips_FCOND_LE,
+ Mips_FCOND_NGT,
+
+ // To be used with float branch False
+ // This conditions have the same mnemonic as the
+ // above ones, but are used with a branch False;
+ Mips_FCOND_T,
+ Mips_FCOND_OR,
+ Mips_FCOND_UNE,
+ Mips_FCOND_ONE,
+ Mips_FCOND_UGE,
+ Mips_FCOND_OGE,
+ Mips_FCOND_UGT,
+ Mips_FCOND_OGT,
+ Mips_FCOND_ST,
+ Mips_FCOND_GLE,
+ Mips_FCOND_SNE,
+ Mips_FCOND_GL,
+ Mips_FCOND_NLT,
+ Mips_FCOND_GE,
+ Mips_FCOND_NLE,
+ Mips_FCOND_GT
+} Mips_CondCode;
+
+#define GET_INSTRINFO_ENUM
+#include "MipsGenInstrInfo.inc"
+
+static const char *getRegisterName(unsigned RegNo);
+static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI);
+
+static void set_mem_access(MCInst *MI, bool status)
+{
+ MI->csh->doing_mem = status;
+
+ if (MI->csh->detail != CS_OPT_ON)
+ return;
+
+ if (status) {
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_MEM;
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = MIPS_REG_INVALID;
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = 0;
+ } else {
+ // done, create the next operand slot
+ MI->flat_insn->detail->mips.op_count++;
+ }
+}
+
+static bool isReg(MCInst *MI, unsigned OpNo, unsigned R)
+{
+ return (MCOperand_isReg(MCInst_getOperand(MI, OpNo)) &&
+ MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == R);
+}
+
+static const char* MipsFCCToString(Mips_CondCode CC)
+{
+ switch (CC) {
+ default: return 0; // never reach
+ case Mips_FCOND_F:
+ case Mips_FCOND_T: return "f";
+ case Mips_FCOND_UN:
+ case Mips_FCOND_OR: return "un";
+ case Mips_FCOND_OEQ:
+ case Mips_FCOND_UNE: return "eq";
+ case Mips_FCOND_UEQ:
+ case Mips_FCOND_ONE: return "ueq";
+ case Mips_FCOND_OLT:
+ case Mips_FCOND_UGE: return "olt";
+ case Mips_FCOND_ULT:
+ case Mips_FCOND_OGE: return "ult";
+ case Mips_FCOND_OLE:
+ case Mips_FCOND_UGT: return "ole";
+ case Mips_FCOND_ULE:
+ case Mips_FCOND_OGT: return "ule";
+ case Mips_FCOND_SF:
+ case Mips_FCOND_ST: return "sf";
+ case Mips_FCOND_NGLE:
+ case Mips_FCOND_GLE: return "ngle";
+ case Mips_FCOND_SEQ:
+ case Mips_FCOND_SNE: return "seq";
+ case Mips_FCOND_NGL:
+ case Mips_FCOND_GL: return "ngl";
+ case Mips_FCOND_LT:
+ case Mips_FCOND_NLT: return "lt";
+ case Mips_FCOND_NGE:
+ case Mips_FCOND_GE: return "nge";
+ case Mips_FCOND_LE:
+ case Mips_FCOND_NLE: return "le";
+ case Mips_FCOND_NGT:
+ case Mips_FCOND_GT: return "ngt";
+ }
+}
+
+static void printRegName(SStream *OS, unsigned RegNo)
+{
+ SStream_concat(OS, "$%s", getRegisterName(RegNo));
+}
+
+void Mips_printInst(MCInst *MI, SStream *O, void *info)
+{
+ char *mnem;
+
+ switch (MCInst_getOpcode(MI)) {
+ default: break;
+ case Mips_Save16:
+ case Mips_SaveX16:
+ case Mips_Restore16:
+ case Mips_RestoreX16:
+ return;
+ }
+
+ // Try to print any aliases first.
+ mnem = printAliasInstr(MI, O, info);
+ if (!mnem) {
+ mnem = printAlias(MI, O);
+ if (!mnem) {
+ printInstruction(MI, O, NULL);
+ }
+ }
+
+ if (mnem) {
+ // fixup instruction id due to the change in alias instruction
+ MCInst_setOpcodePub(MI, Mips_map_insn(mnem));
+ cs_mem_free(mnem);
+ }
+}
+
+static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+ MCOperand *Op;
+
+ if (OpNo >= MI->size)
+ return;
+
+ Op = MCInst_getOperand(MI, OpNo);
+ if (MCOperand_isReg(Op)) {
+ unsigned int reg = MCOperand_getReg(Op);
+ printRegName(O, reg);
+ reg = Mips_map_register(reg);
+ if (MI->csh->detail) {
+ if (MI->csh->doing_mem) {
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = reg;
+ } else {
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG;
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg;
+ MI->flat_insn->detail->mips.op_count++;
+ }
+ }
+ } else if (MCOperand_isImm(Op)) {
+ int64_t imm = MCOperand_getImm(Op);
+ if (MI->csh->doing_mem) {
+ if (imm) { // only print Imm offset if it is not 0
+ printInt64(O, imm);
+ }
+ if (MI->csh->detail)
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = imm;
+ } else {
+ printInt64(O, imm);
+
+ if (MI->csh->detail) {
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm;
+ MI->flat_insn->detail->mips.op_count++;
+ }
+ }
+ }
+}
+
+static void printUnsignedImm(MCInst *MI, int opNum, SStream *O)
+{
+ MCOperand *MO = MCInst_getOperand(MI, opNum);
+ if (MCOperand_isImm(MO)) {
+ int64_t imm = MCOperand_getImm(MO);
+ printInt64(O, imm);
+
+ if (MI->csh->detail) {
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = (unsigned short int)imm;
+ MI->flat_insn->detail->mips.op_count++;
+ }
+ } else
+ printOperand(MI, opNum, O);
+}
+
+static void printUnsignedImm8(MCInst *MI, int opNum, SStream *O)
+{
+ MCOperand *MO = MCInst_getOperand(MI, opNum);
+ if (MCOperand_isImm(MO)) {
+ uint8_t imm = (uint8_t)MCOperand_getImm(MO);
+ if (imm > HEX_THRESHOLD)
+ SStream_concat(O, "0x%x", imm);
+ else
+ SStream_concat(O, "%u", imm);
+ if (MI->csh->detail) {
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm;
+ MI->flat_insn->detail->mips.op_count++;
+ }
+ } else
+ printOperand(MI, opNum, O);
+}
+
+static void printMemOperand(MCInst *MI, int opNum, SStream *O)
+{
+ // Load/Store memory operands -- imm($reg)
+ // If PIC target the target is loaded as the
+ // pattern lw $25,%call16($28)
+
+ // opNum can be invalid if instruction had reglist as operand.
+ // MemOperand is always last operand of instruction (base + offset).
+ switch (MCInst_getOpcode(MI)) {
+ default:
+ break;
+ case Mips_SWM32_MM:
+ case Mips_LWM32_MM:
+ case Mips_SWM16_MM:
+ case Mips_LWM16_MM:
+ opNum = MCInst_getNumOperands(MI) - 2;
+ break;
+ }
+
+ set_mem_access(MI, true);
+ printOperand(MI, opNum + 1, O);
+ SStream_concat0(O, "(");
+ printOperand(MI, opNum, O);
+ SStream_concat0(O, ")");
+ set_mem_access(MI, false);
+}
+
+// TODO???
+static void printMemOperandEA(MCInst *MI, int opNum, SStream *O)
+{
+ // when using stack locations for not load/store instructions
+ // print the same way as all normal 3 operand instructions.
+ printOperand(MI, opNum, O);
+ SStream_concat0(O, ", ");
+ printOperand(MI, opNum + 1, O);
+ return;
+}
+
+static void printFCCOperand(MCInst *MI, int opNum, SStream *O)
+{
+ MCOperand *MO = MCInst_getOperand(MI, opNum);
+ SStream_concat0(O, MipsFCCToString((Mips_CondCode)MCOperand_getImm(MO)));
+}
+
+static void printRegisterPair(MCInst *MI, int opNum, SStream *O)
+{
+ printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, opNum)));
+}
+
+static char *printAlias1(const char *Str, MCInst *MI, unsigned OpNo, SStream *OS)
+{
+ SStream_concat(OS, "%s\t", Str);
+ printOperand(MI, OpNo, OS);
+ return cs_strdup(Str);
+}
+
+static char *printAlias2(const char *Str, MCInst *MI,
+ unsigned OpNo0, unsigned OpNo1, SStream *OS)
+{
+ char *tmp;
+
+ tmp = printAlias1(Str, MI, OpNo0, OS);
+ SStream_concat0(OS, ", ");
+ printOperand(MI, OpNo1, OS);
+
+ return tmp;
+}
+
+#define GET_REGINFO_ENUM
+#include "MipsGenRegisterInfo.inc"
+
+static char *printAlias(MCInst *MI, SStream *OS)
+{
+ switch (MCInst_getOpcode(MI)) {
+ case Mips_BEQ:
+ case Mips_BEQ_MM:
+ // beq $zero, $zero, $L2 => b $L2
+ // beq $r0, $zero, $L2 => beqz $r0, $L2
+ if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO))
+ return printAlias1("b", MI, 2, OS);
+ if (isReg(MI, 1, Mips_ZERO))
+ return printAlias2("beqz", MI, 0, 2, OS);
+ return NULL;
+ case Mips_BEQ64:
+ // beq $r0, $zero, $L2 => beqz $r0, $L2
+ if (isReg(MI, 1, Mips_ZERO_64))
+ return printAlias2("beqz", MI, 0, 2, OS);
+ return NULL;
+ case Mips_BNE:
+ // bne $r0, $zero, $L2 => bnez $r0, $L2
+ if (isReg(MI, 1, Mips_ZERO))
+ return printAlias2("bnez", MI, 0, 2, OS);
+ return NULL;
+ case Mips_BNE64:
+ // bne $r0, $zero, $L2 => bnez $r0, $L2
+ if (isReg(MI, 1, Mips_ZERO_64))
+ return printAlias2("bnez", MI, 0, 2, OS);
+ return NULL;
+ case Mips_BGEZAL:
+ // bgezal $zero, $L1 => bal $L1
+ if (isReg(MI, 0, Mips_ZERO))
+ return printAlias1("bal", MI, 1, OS);
+ return NULL;
+ case Mips_BC1T:
+ // bc1t $fcc0, $L1 => bc1t $L1
+ if (isReg(MI, 0, Mips_FCC0))
+ return printAlias1("bc1t", MI, 1, OS);
+ return NULL;
+ case Mips_BC1F:
+ // bc1f $fcc0, $L1 => bc1f $L1
+ if (isReg(MI, 0, Mips_FCC0))
+ return printAlias1("bc1f", MI, 1, OS);
+ return NULL;
+ case Mips_JALR:
+ // jalr $ra, $r1 => jalr $r1
+ if (isReg(MI, 0, Mips_RA))
+ return printAlias1("jalr", MI, 1, OS);
+ return NULL;
+ case Mips_JALR64:
+ // jalr $ra, $r1 => jalr $r1
+ if (isReg(MI, 0, Mips_RA_64))
+ return printAlias1("jalr", MI, 1, OS);
+ return NULL;
+ case Mips_NOR:
+ case Mips_NOR_MM:
+ // nor $r0, $r1, $zero => not $r0, $r1
+ if (isReg(MI, 2, Mips_ZERO))
+ return printAlias2("not", MI, 0, 1, OS);
+ return NULL;
+ case Mips_NOR64:
+ // nor $r0, $r1, $zero => not $r0, $r1
+ if (isReg(MI, 2, Mips_ZERO_64))
+ return printAlias2("not", MI, 0, 1, OS);
+ return NULL;
+ case Mips_OR:
+ // or $r0, $r1, $zero => move $r0, $r1
+ if (isReg(MI, 2, Mips_ZERO))
+ return printAlias2("move", MI, 0, 1, OS);
+ return NULL;
+ default: return NULL;
+ }
+}
+
+static void printRegisterList(MCInst *MI, int opNum, SStream *O)
+{
+ int i, e, reg;
+
+ // - 2 because register List is always first operand of instruction and it is
+ // always followed by memory operand (base + offset).
+ for (i = opNum, e = MCInst_getNumOperands(MI) - 2; i != e; ++i) {
+ if (i != opNum)
+ SStream_concat0(O, ", ");
+ reg = MCOperand_getReg(MCInst_getOperand(MI, i));
+ printRegName(O, reg);
+ if (MI->csh->detail) {
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG;
+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg;
+ MI->flat_insn->detail->mips.op_count++;
+ }
+ }
+}
+
+#define PRINT_ALIAS_INSTR
+#include "MipsGenAsmWriter.inc"
+
+#endif
diff --git a/capstone/arch/Mips/MipsInstPrinter.h b/capstone/arch/Mips/MipsInstPrinter.h
new file mode 100644
index 000000000..659ef7790
--- /dev/null
+++ b/capstone/arch/Mips/MipsInstPrinter.h
@@ -0,0 +1,25 @@
+//=== MipsInstPrinter.h - Convert Mips MCInst to assembly syntax -*- C++ -*-==//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints a Mips MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_MIPSINSTPRINTER_H
+#define CS_MIPSINSTPRINTER_H
+
+#include "../../MCInst.h"
+#include "../../SStream.h"
+
+void Mips_printInst(MCInst *MI, SStream *O, void *info);
+
+#endif
diff --git a/capstone/arch/Mips/MipsMapping.c b/capstone/arch/Mips/MipsMapping.c
new file mode 100644
index 000000000..c8a159d80
--- /dev/null
+++ b/capstone/arch/Mips/MipsMapping.c
@@ -0,0 +1,1070 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifdef CAPSTONE_HAS_MIPS
+
+#include <stdio.h> // debug
+#include <string.h>
+
+#include "../../utils.h"
+
+#include "MipsMapping.h"
+
+#define GET_INSTRINFO_ENUM
+#include "MipsGenInstrInfo.inc"
+
+#ifndef CAPSTONE_DIET
+static const name_map reg_name_maps[] = {
+ { MIPS_REG_INVALID, NULL },
+
+ { MIPS_REG_PC, "pc"},
+
+ //{ MIPS_REG_0, "0"},
+ { MIPS_REG_0, "zero"},
+ { MIPS_REG_1, "at"},
+ //{ MIPS_REG_1, "1"},
+ { MIPS_REG_2, "v0"},
+ //{ MIPS_REG_2, "2"},
+ { MIPS_REG_3, "v1"},
+ //{ MIPS_REG_3, "3"},
+ { MIPS_REG_4, "a0"},
+ //{ MIPS_REG_4, "4"},
+ { MIPS_REG_5, "a1"},
+ //{ MIPS_REG_5, "5"},
+ { MIPS_REG_6, "a2"},
+ //{ MIPS_REG_6, "6"},
+ { MIPS_REG_7, "a3"},
+ //{ MIPS_REG_7, "7"},
+ { MIPS_REG_8, "t0"},
+ //{ MIPS_REG_8, "8"},
+ { MIPS_REG_9, "t1"},
+ //{ MIPS_REG_9, "9"},
+ { MIPS_REG_10, "t2"},
+ //{ MIPS_REG_10, "10"},
+ { MIPS_REG_11, "t3"},
+ //{ MIPS_REG_11, "11"},
+ { MIPS_REG_12, "t4"},
+ //{ MIPS_REG_12, "12"},
+ { MIPS_REG_13, "t5"},
+ //{ MIPS_REG_13, "13"},
+ { MIPS_REG_14, "t6"},
+ //{ MIPS_REG_14, "14"},
+ { MIPS_REG_15, "t7"},
+ //{ MIPS_REG_15, "15"},
+ { MIPS_REG_16, "s0"},
+ //{ MIPS_REG_16, "16"},
+ { MIPS_REG_17, "s1"},
+ //{ MIPS_REG_17, "17"},
+ { MIPS_REG_18, "s2"},
+ //{ MIPS_REG_18, "18"},
+ { MIPS_REG_19, "s3"},
+ //{ MIPS_REG_19, "19"},
+ { MIPS_REG_20, "s4"},
+ //{ MIPS_REG_20, "20"},
+ { MIPS_REG_21, "s5"},
+ //{ MIPS_REG_21, "21"},
+ { MIPS_REG_22, "s6"},
+ //{ MIPS_REG_22, "22"},
+ { MIPS_REG_23, "s7"},
+ //{ MIPS_REG_23, "23"},
+ { MIPS_REG_24, "t8"},
+ //{ MIPS_REG_24, "24"},
+ { MIPS_REG_25, "t9"},
+ //{ MIPS_REG_25, "25"},
+ { MIPS_REG_26, "k0"},
+ //{ MIPS_REG_26, "26"},
+ { MIPS_REG_27, "k1"},
+ //{ MIPS_REG_27, "27"},
+ { MIPS_REG_28, "gp"},
+ //{ MIPS_REG_28, "28"},
+ { MIPS_REG_29, "sp"},
+ //{ MIPS_REG_29, "29"},
+ { MIPS_REG_30, "fp"},
+ //{ MIPS_REG_30, "30"},
+ { MIPS_REG_31, "ra"},
+ //{ MIPS_REG_31, "31"},
+
+ { MIPS_REG_DSPCCOND, "dspccond"},
+ { MIPS_REG_DSPCARRY, "dspcarry"},
+ { MIPS_REG_DSPEFI, "dspefi"},
+ { MIPS_REG_DSPOUTFLAG, "dspoutflag"},
+ { MIPS_REG_DSPOUTFLAG16_19, "dspoutflag16_19"},
+ { MIPS_REG_DSPOUTFLAG20, "dspoutflag20"},
+ { MIPS_REG_DSPOUTFLAG21, "dspoutflag21"},
+ { MIPS_REG_DSPOUTFLAG22, "dspoutflag22"},
+ { MIPS_REG_DSPOUTFLAG23, "dspoutflag23"},
+ { MIPS_REG_DSPPOS, "dsppos"},
+ { MIPS_REG_DSPSCOUNT, "dspscount"},
+
+ { MIPS_REG_AC0, "ac0"},
+ { MIPS_REG_AC1, "ac1"},
+ { MIPS_REG_AC2, "ac2"},
+ { MIPS_REG_AC3, "ac3"},
+
+ { MIPS_REG_CC0, "cc0"},
+ { MIPS_REG_CC1, "cc1"},
+ { MIPS_REG_CC2, "cc2"},
+ { MIPS_REG_CC3, "cc3"},
+ { MIPS_REG_CC4, "cc4"},
+ { MIPS_REG_CC5, "cc5"},
+ { MIPS_REG_CC6, "cc6"},
+ { MIPS_REG_CC7, "cc7"},
+
+ { MIPS_REG_F0, "f0"},
+ { MIPS_REG_F1, "f1"},
+ { MIPS_REG_F2, "f2"},
+ { MIPS_REG_F3, "f3"},
+ { MIPS_REG_F4, "f4"},
+ { MIPS_REG_F5, "f5"},
+ { MIPS_REG_F6, "f6"},
+ { MIPS_REG_F7, "f7"},
+ { MIPS_REG_F8, "f8"},
+ { MIPS_REG_F9, "f9"},
+ { MIPS_REG_F10, "f10"},
+ { MIPS_REG_F11, "f11"},
+ { MIPS_REG_F12, "f12"},
+ { MIPS_REG_F13, "f13"},
+ { MIPS_REG_F14, "f14"},
+ { MIPS_REG_F15, "f15"},
+ { MIPS_REG_F16, "f16"},
+ { MIPS_REG_F17, "f17"},
+ { MIPS_REG_F18, "f18"},
+ { MIPS_REG_F19, "f19"},
+ { MIPS_REG_F20, "f20"},
+ { MIPS_REG_F21, "f21"},
+ { MIPS_REG_F22, "f22"},
+ { MIPS_REG_F23, "f23"},
+ { MIPS_REG_F24, "f24"},
+ { MIPS_REG_F25, "f25"},
+ { MIPS_REG_F26, "f26"},
+ { MIPS_REG_F27, "f27"},
+ { MIPS_REG_F28, "f28"},
+ { MIPS_REG_F29, "f29"},
+ { MIPS_REG_F30, "f30"},
+ { MIPS_REG_F31, "f31"},
+
+ { MIPS_REG_FCC0, "fcc0"},
+ { MIPS_REG_FCC1, "fcc1"},
+ { MIPS_REG_FCC2, "fcc2"},
+ { MIPS_REG_FCC3, "fcc3"},
+ { MIPS_REG_FCC4, "fcc4"},
+ { MIPS_REG_FCC5, "fcc5"},
+ { MIPS_REG_FCC6, "fcc6"},
+ { MIPS_REG_FCC7, "fcc7"},
+
+ { MIPS_REG_W0, "w0"},
+ { MIPS_REG_W1, "w1"},
+ { MIPS_REG_W2, "w2"},
+ { MIPS_REG_W3, "w3"},
+ { MIPS_REG_W4, "w4"},
+ { MIPS_REG_W5, "w5"},
+ { MIPS_REG_W6, "w6"},
+ { MIPS_REG_W7, "w7"},
+ { MIPS_REG_W8, "w8"},
+ { MIPS_REG_W9, "w9"},
+ { MIPS_REG_W10, "w10"},
+ { MIPS_REG_W11, "w11"},
+ { MIPS_REG_W12, "w12"},
+ { MIPS_REG_W13, "w13"},
+ { MIPS_REG_W14, "w14"},
+ { MIPS_REG_W15, "w15"},
+ { MIPS_REG_W16, "w16"},
+ { MIPS_REG_W17, "w17"},
+ { MIPS_REG_W18, "w18"},
+ { MIPS_REG_W19, "w19"},
+ { MIPS_REG_W20, "w20"},
+ { MIPS_REG_W21, "w21"},
+ { MIPS_REG_W22, "w22"},
+ { MIPS_REG_W23, "w23"},
+ { MIPS_REG_W24, "w24"},
+ { MIPS_REG_W25, "w25"},
+ { MIPS_REG_W26, "w26"},
+ { MIPS_REG_W27, "w27"},
+ { MIPS_REG_W28, "w28"},
+ { MIPS_REG_W29, "w29"},
+ { MIPS_REG_W30, "w30"},
+ { MIPS_REG_W31, "w31"},
+
+ { MIPS_REG_HI, "hi"},
+ { MIPS_REG_LO, "lo"},
+
+ { MIPS_REG_P0, "p0"},
+ { MIPS_REG_P1, "p1"},
+ { MIPS_REG_P2, "p2"},
+
+ { MIPS_REG_MPL0, "mpl0"},
+ { MIPS_REG_MPL1, "mpl1"},
+ { MIPS_REG_MPL2, "mpl2"},
+};
+#endif
+
+const char *Mips_reg_name(csh handle, unsigned int reg)
+{
+#ifndef CAPSTONE_DIET
+ if (reg >= ARR_SIZE(reg_name_maps))
+ return NULL;
+
+ return reg_name_maps[reg].name;
+#else
+ return NULL;
+#endif
+}
+
+static const insn_map insns[] = {
+ // dummy item
+ {
+ 0, 0,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { 0 }, 0, 0
+#endif
+ },
+
+#include "MipsMappingInsn.inc"
+};
+
+// given internal insn id, return public instruction info
+void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
+{
+ unsigned int i;
+
+ i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
+ if (i != 0) {
+ insn->id = insns[i].mapid;
+
+ if (h->detail) {
+#ifndef CAPSTONE_DIET
+ memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
+ insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
+
+ memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
+ insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
+
+ memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
+ insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups);
+
+ if (insns[i].branch || insns[i].indirect_branch) {
+ // this insn also belongs to JUMP group. add JUMP group
+ insn->detail->groups[insn->detail->groups_count] = MIPS_GRP_JUMP;
+ insn->detail->groups_count++;
+ }
+#endif
+ }
+ }
+}
+
+static const name_map insn_name_maps[] = {
+ { MIPS_INS_INVALID, NULL },
+
+ { MIPS_INS_ABSQ_S, "absq_s" },
+ { MIPS_INS_ADD, "add" },
+ { MIPS_INS_ADDIUPC, "addiupc" },
+ { MIPS_INS_ADDIUR1SP, "addiur1sp" },
+ { MIPS_INS_ADDIUR2, "addiur2" },
+ { MIPS_INS_ADDIUS5, "addius5" },
+ { MIPS_INS_ADDIUSP, "addiusp" },
+ { MIPS_INS_ADDQH, "addqh" },
+ { MIPS_INS_ADDQH_R, "addqh_r" },
+ { MIPS_INS_ADDQ, "addq" },
+ { MIPS_INS_ADDQ_S, "addq_s" },
+ { MIPS_INS_ADDSC, "addsc" },
+ { MIPS_INS_ADDS_A, "adds_a" },
+ { MIPS_INS_ADDS_S, "adds_s" },
+ { MIPS_INS_ADDS_U, "adds_u" },
+ { MIPS_INS_ADDU16, "addu16" },
+ { MIPS_INS_ADDUH, "adduh" },
+ { MIPS_INS_ADDUH_R, "adduh_r" },
+ { MIPS_INS_ADDU, "addu" },
+ { MIPS_INS_ADDU_S, "addu_s" },
+ { MIPS_INS_ADDVI, "addvi" },
+ { MIPS_INS_ADDV, "addv" },
+ { MIPS_INS_ADDWC, "addwc" },
+ { MIPS_INS_ADD_A, "add_a" },
+ { MIPS_INS_ADDI, "addi" },
+ { MIPS_INS_ADDIU, "addiu" },
+ { MIPS_INS_ALIGN, "align" },
+ { MIPS_INS_ALUIPC, "aluipc" },
+ { MIPS_INS_AND, "and" },
+ { MIPS_INS_AND16, "and16" },
+ { MIPS_INS_ANDI16, "andi16" },
+ { MIPS_INS_ANDI, "andi" },
+ { MIPS_INS_APPEND, "append" },
+ { MIPS_INS_ASUB_S, "asub_s" },
+ { MIPS_INS_ASUB_U, "asub_u" },
+ { MIPS_INS_AUI, "aui" },
+ { MIPS_INS_AUIPC, "auipc" },
+ { MIPS_INS_AVER_S, "aver_s" },
+ { MIPS_INS_AVER_U, "aver_u" },
+ { MIPS_INS_AVE_S, "ave_s" },
+ { MIPS_INS_AVE_U, "ave_u" },
+ { MIPS_INS_B16, "b16" },
+ { MIPS_INS_BADDU, "baddu" },
+ { MIPS_INS_BAL, "bal" },
+ { MIPS_INS_BALC, "balc" },
+ { MIPS_INS_BALIGN, "balign" },
+ { MIPS_INS_BBIT0, "bbit0" },
+ { MIPS_INS_BBIT032, "bbit032" },
+ { MIPS_INS_BBIT1, "bbit1" },
+ { MIPS_INS_BBIT132, "bbit132" },
+ { MIPS_INS_BC, "bc" },
+ { MIPS_INS_BC0F, "bc0f" },
+ { MIPS_INS_BC0FL, "bc0fl" },
+ { MIPS_INS_BC0T, "bc0t" },
+ { MIPS_INS_BC0TL, "bc0tl" },
+ { MIPS_INS_BC1EQZ, "bc1eqz" },
+ { MIPS_INS_BC1F, "bc1f" },
+ { MIPS_INS_BC1FL, "bc1fl" },
+ { MIPS_INS_BC1NEZ, "bc1nez" },
+ { MIPS_INS_BC1T, "bc1t" },
+ { MIPS_INS_BC1TL, "bc1tl" },
+ { MIPS_INS_BC2EQZ, "bc2eqz" },
+ { MIPS_INS_BC2F, "bc2f" },
+ { MIPS_INS_BC2FL, "bc2fl" },
+ { MIPS_INS_BC2NEZ, "bc2nez" },
+ { MIPS_INS_BC2T, "bc2t" },
+ { MIPS_INS_BC2TL, "bc2tl" },
+ { MIPS_INS_BC3F, "bc3f" },
+ { MIPS_INS_BC3FL, "bc3fl" },
+ { MIPS_INS_BC3T, "bc3t" },
+ { MIPS_INS_BC3TL, "bc3tl" },
+ { MIPS_INS_BCLRI, "bclri" },
+ { MIPS_INS_BCLR, "bclr" },
+ { MIPS_INS_BEQ, "beq" },
+ { MIPS_INS_BEQC, "beqc" },
+ { MIPS_INS_BEQL, "beql" },
+ { MIPS_INS_BEQZ16, "beqz16" },
+ { MIPS_INS_BEQZALC, "beqzalc" },
+ { MIPS_INS_BEQZC, "beqzc" },
+ { MIPS_INS_BGEC, "bgec" },
+ { MIPS_INS_BGEUC, "bgeuc" },
+ { MIPS_INS_BGEZ, "bgez" },
+ { MIPS_INS_BGEZAL, "bgezal" },
+ { MIPS_INS_BGEZALC, "bgezalc" },
+ { MIPS_INS_BGEZALL, "bgezall" },
+ { MIPS_INS_BGEZALS, "bgezals" },
+ { MIPS_INS_BGEZC, "bgezc" },
+ { MIPS_INS_BGEZL, "bgezl" },
+ { MIPS_INS_BGTZ, "bgtz" },
+ { MIPS_INS_BGTZALC, "bgtzalc" },
+ { MIPS_INS_BGTZC, "bgtzc" },
+ { MIPS_INS_BGTZL, "bgtzl" },
+ { MIPS_INS_BINSLI, "binsli" },
+ { MIPS_INS_BINSL, "binsl" },
+ { MIPS_INS_BINSRI, "binsri" },
+ { MIPS_INS_BINSR, "binsr" },
+ { MIPS_INS_BITREV, "bitrev" },
+ { MIPS_INS_BITSWAP, "bitswap" },
+ { MIPS_INS_BLEZ, "blez" },
+ { MIPS_INS_BLEZALC, "blezalc" },
+ { MIPS_INS_BLEZC, "blezc" },
+ { MIPS_INS_BLEZL, "blezl" },
+ { MIPS_INS_BLTC, "bltc" },
+ { MIPS_INS_BLTUC, "bltuc" },
+ { MIPS_INS_BLTZ, "bltz" },
+ { MIPS_INS_BLTZAL, "bltzal" },
+ { MIPS_INS_BLTZALC, "bltzalc" },
+ { MIPS_INS_BLTZALL, "bltzall" },
+ { MIPS_INS_BLTZALS, "bltzals" },
+ { MIPS_INS_BLTZC, "bltzc" },
+ { MIPS_INS_BLTZL, "bltzl" },
+ { MIPS_INS_BMNZI, "bmnzi" },
+ { MIPS_INS_BMNZ, "bmnz" },
+ { MIPS_INS_BMZI, "bmzi" },
+ { MIPS_INS_BMZ, "bmz" },
+ { MIPS_INS_BNE, "bne" },
+ { MIPS_INS_BNEC, "bnec" },
+ { MIPS_INS_BNEGI, "bnegi" },
+ { MIPS_INS_BNEG, "bneg" },
+ { MIPS_INS_BNEL, "bnel" },
+ { MIPS_INS_BNEZ16, "bnez16" },
+ { MIPS_INS_BNEZALC, "bnezalc" },
+ { MIPS_INS_BNEZC, "bnezc" },
+ { MIPS_INS_BNVC, "bnvc" },
+ { MIPS_INS_BNZ, "bnz" },
+ { MIPS_INS_BOVC, "bovc" },
+ { MIPS_INS_BPOSGE32, "bposge32" },
+ { MIPS_INS_BREAK, "break" },
+ { MIPS_INS_BREAK16, "break16" },
+ { MIPS_INS_BSELI, "bseli" },
+ { MIPS_INS_BSEL, "bsel" },
+ { MIPS_INS_BSETI, "bseti" },
+ { MIPS_INS_BSET, "bset" },
+ { MIPS_INS_BZ, "bz" },
+ { MIPS_INS_BEQZ, "beqz" },
+ { MIPS_INS_B, "b" },
+ { MIPS_INS_BNEZ, "bnez" },
+ { MIPS_INS_BTEQZ, "bteqz" },
+ { MIPS_INS_BTNEZ, "btnez" },
+ { MIPS_INS_CACHE, "cache" },
+ { MIPS_INS_CEIL, "ceil" },
+ { MIPS_INS_CEQI, "ceqi" },
+ { MIPS_INS_CEQ, "ceq" },
+ { MIPS_INS_CFC1, "cfc1" },
+ { MIPS_INS_CFCMSA, "cfcmsa" },
+ { MIPS_INS_CINS, "cins" },
+ { MIPS_INS_CINS32, "cins32" },
+ { MIPS_INS_CLASS, "class" },
+ { MIPS_INS_CLEI_S, "clei_s" },
+ { MIPS_INS_CLEI_U, "clei_u" },
+ { MIPS_INS_CLE_S, "cle_s" },
+ { MIPS_INS_CLE_U, "cle_u" },
+ { MIPS_INS_CLO, "clo" },
+ { MIPS_INS_CLTI_S, "clti_s" },
+ { MIPS_INS_CLTI_U, "clti_u" },
+ { MIPS_INS_CLT_S, "clt_s" },
+ { MIPS_INS_CLT_U, "clt_u" },
+ { MIPS_INS_CLZ, "clz" },
+ { MIPS_INS_CMPGDU, "cmpgdu" },
+ { MIPS_INS_CMPGU, "cmpgu" },
+ { MIPS_INS_CMPU, "cmpu" },
+ { MIPS_INS_CMP, "cmp" },
+ { MIPS_INS_COPY_S, "copy_s" },
+ { MIPS_INS_COPY_U, "copy_u" },
+ { MIPS_INS_CTC1, "ctc1" },
+ { MIPS_INS_CTCMSA, "ctcmsa" },
+ { MIPS_INS_CVT, "cvt" },
+ { MIPS_INS_C, "c" },
+ { MIPS_INS_CMPI, "cmpi" },
+ { MIPS_INS_DADD, "dadd" },
+ { MIPS_INS_DADDI, "daddi" },
+ { MIPS_INS_DADDIU, "daddiu" },
+ { MIPS_INS_DADDU, "daddu" },
+ { MIPS_INS_DAHI, "dahi" },
+ { MIPS_INS_DALIGN, "dalign" },
+ { MIPS_INS_DATI, "dati" },
+ { MIPS_INS_DAUI, "daui" },
+ { MIPS_INS_DBITSWAP, "dbitswap" },
+ { MIPS_INS_DCLO, "dclo" },
+ { MIPS_INS_DCLZ, "dclz" },
+ { MIPS_INS_DDIV, "ddiv" },
+ { MIPS_INS_DDIVU, "ddivu" },
+ { MIPS_INS_DERET, "deret" },
+ { MIPS_INS_DEXT, "dext" },
+ { MIPS_INS_DEXTM, "dextm" },
+ { MIPS_INS_DEXTU, "dextu" },
+ { MIPS_INS_DI, "di" },
+ { MIPS_INS_DINS, "dins" },
+ { MIPS_INS_DINSM, "dinsm" },
+ { MIPS_INS_DINSU, "dinsu" },
+ { MIPS_INS_DIV, "div" },
+ { MIPS_INS_DIVU, "divu" },
+ { MIPS_INS_DIV_S, "div_s" },
+ { MIPS_INS_DIV_U, "div_u" },
+ { MIPS_INS_DLSA, "dlsa" },
+ { MIPS_INS_DMFC0, "dmfc0" },
+ { MIPS_INS_DMFC1, "dmfc1" },
+ { MIPS_INS_DMFC2, "dmfc2" },
+ { MIPS_INS_DMOD, "dmod" },
+ { MIPS_INS_DMODU, "dmodu" },
+ { MIPS_INS_DMTC0, "dmtc0" },
+ { MIPS_INS_DMTC1, "dmtc1" },
+ { MIPS_INS_DMTC2, "dmtc2" },
+ { MIPS_INS_DMUH, "dmuh" },
+ { MIPS_INS_DMUHU, "dmuhu" },
+ { MIPS_INS_DMUL, "dmul" },
+ { MIPS_INS_DMULT, "dmult" },
+ { MIPS_INS_DMULTU, "dmultu" },
+ { MIPS_INS_DMULU, "dmulu" },
+ { MIPS_INS_DOTP_S, "dotp_s" },
+ { MIPS_INS_DOTP_U, "dotp_u" },
+ { MIPS_INS_DPADD_S, "dpadd_s" },
+ { MIPS_INS_DPADD_U, "dpadd_u" },
+ { MIPS_INS_DPAQX_SA, "dpaqx_sa" },
+ { MIPS_INS_DPAQX_S, "dpaqx_s" },
+ { MIPS_INS_DPAQ_SA, "dpaq_sa" },
+ { MIPS_INS_DPAQ_S, "dpaq_s" },
+ { MIPS_INS_DPAU, "dpau" },
+ { MIPS_INS_DPAX, "dpax" },
+ { MIPS_INS_DPA, "dpa" },
+ { MIPS_INS_DPOP, "dpop" },
+ { MIPS_INS_DPSQX_SA, "dpsqx_sa" },
+ { MIPS_INS_DPSQX_S, "dpsqx_s" },
+ { MIPS_INS_DPSQ_SA, "dpsq_sa" },
+ { MIPS_INS_DPSQ_S, "dpsq_s" },
+ { MIPS_INS_DPSUB_S, "dpsub_s" },
+ { MIPS_INS_DPSUB_U, "dpsub_u" },
+ { MIPS_INS_DPSU, "dpsu" },
+ { MIPS_INS_DPSX, "dpsx" },
+ { MIPS_INS_DPS, "dps" },
+ { MIPS_INS_DROTR, "drotr" },
+ { MIPS_INS_DROTR32, "drotr32" },
+ { MIPS_INS_DROTRV, "drotrv" },
+ { MIPS_INS_DSBH, "dsbh" },
+ { MIPS_INS_DSHD, "dshd" },
+ { MIPS_INS_DSLL, "dsll" },
+ { MIPS_INS_DSLL32, "dsll32" },
+ { MIPS_INS_DSLLV, "dsllv" },
+ { MIPS_INS_DSRA, "dsra" },
+ { MIPS_INS_DSRA32, "dsra32" },
+ { MIPS_INS_DSRAV, "dsrav" },
+ { MIPS_INS_DSRL, "dsrl" },
+ { MIPS_INS_DSRL32, "dsrl32" },
+ { MIPS_INS_DSRLV, "dsrlv" },
+ { MIPS_INS_DSUB, "dsub" },
+ { MIPS_INS_DSUBU, "dsubu" },
+ { MIPS_INS_EHB, "ehb" },
+ { MIPS_INS_EI, "ei" },
+ { MIPS_INS_ERET, "eret" },
+ { MIPS_INS_EXT, "ext" },
+ { MIPS_INS_EXTP, "extp" },
+ { MIPS_INS_EXTPDP, "extpdp" },
+ { MIPS_INS_EXTPDPV, "extpdpv" },
+ { MIPS_INS_EXTPV, "extpv" },
+ { MIPS_INS_EXTRV_RS, "extrv_rs" },
+ { MIPS_INS_EXTRV_R, "extrv_r" },
+ { MIPS_INS_EXTRV_S, "extrv_s" },
+ { MIPS_INS_EXTRV, "extrv" },
+ { MIPS_INS_EXTR_RS, "extr_rs" },
+ { MIPS_INS_EXTR_R, "extr_r" },
+ { MIPS_INS_EXTR_S, "extr_s" },
+ { MIPS_INS_EXTR, "extr" },
+ { MIPS_INS_EXTS, "exts" },
+ { MIPS_INS_EXTS32, "exts32" },
+ { MIPS_INS_ABS, "abs" },
+ { MIPS_INS_FADD, "fadd" },
+ { MIPS_INS_FCAF, "fcaf" },
+ { MIPS_INS_FCEQ, "fceq" },
+ { MIPS_INS_FCLASS, "fclass" },
+ { MIPS_INS_FCLE, "fcle" },
+ { MIPS_INS_FCLT, "fclt" },
+ { MIPS_INS_FCNE, "fcne" },
+ { MIPS_INS_FCOR, "fcor" },
+ { MIPS_INS_FCUEQ, "fcueq" },
+ { MIPS_INS_FCULE, "fcule" },
+ { MIPS_INS_FCULT, "fcult" },
+ { MIPS_INS_FCUNE, "fcune" },
+ { MIPS_INS_FCUN, "fcun" },
+ { MIPS_INS_FDIV, "fdiv" },
+ { MIPS_INS_FEXDO, "fexdo" },
+ { MIPS_INS_FEXP2, "fexp2" },
+ { MIPS_INS_FEXUPL, "fexupl" },
+ { MIPS_INS_FEXUPR, "fexupr" },
+ { MIPS_INS_FFINT_S, "ffint_s" },
+ { MIPS_INS_FFINT_U, "ffint_u" },
+ { MIPS_INS_FFQL, "ffql" },
+ { MIPS_INS_FFQR, "ffqr" },
+ { MIPS_INS_FILL, "fill" },
+ { MIPS_INS_FLOG2, "flog2" },
+ { MIPS_INS_FLOOR, "floor" },
+ { MIPS_INS_FMADD, "fmadd" },
+ { MIPS_INS_FMAX_A, "fmax_a" },
+ { MIPS_INS_FMAX, "fmax" },
+ { MIPS_INS_FMIN_A, "fmin_a" },
+ { MIPS_INS_FMIN, "fmin" },
+ { MIPS_INS_MOV, "mov" },
+ { MIPS_INS_FMSUB, "fmsub" },
+ { MIPS_INS_FMUL, "fmul" },
+ { MIPS_INS_MUL, "mul" },
+ { MIPS_INS_NEG, "neg" },
+ { MIPS_INS_FRCP, "frcp" },
+ { MIPS_INS_FRINT, "frint" },
+ { MIPS_INS_FRSQRT, "frsqrt" },
+ { MIPS_INS_FSAF, "fsaf" },
+ { MIPS_INS_FSEQ, "fseq" },
+ { MIPS_INS_FSLE, "fsle" },
+ { MIPS_INS_FSLT, "fslt" },
+ { MIPS_INS_FSNE, "fsne" },
+ { MIPS_INS_FSOR, "fsor" },
+ { MIPS_INS_FSQRT, "fsqrt" },
+ { MIPS_INS_SQRT, "sqrt" },
+ { MIPS_INS_FSUB, "fsub" },
+ { MIPS_INS_SUB, "sub" },
+ { MIPS_INS_FSUEQ, "fsueq" },
+ { MIPS_INS_FSULE, "fsule" },
+ { MIPS_INS_FSULT, "fsult" },
+ { MIPS_INS_FSUNE, "fsune" },
+ { MIPS_INS_FSUN, "fsun" },
+ { MIPS_INS_FTINT_S, "ftint_s" },
+ { MIPS_INS_FTINT_U, "ftint_u" },
+ { MIPS_INS_FTQ, "ftq" },
+ { MIPS_INS_FTRUNC_S, "ftrunc_s" },
+ { MIPS_INS_FTRUNC_U, "ftrunc_u" },
+ { MIPS_INS_HADD_S, "hadd_s" },
+ { MIPS_INS_HADD_U, "hadd_u" },
+ { MIPS_INS_HSUB_S, "hsub_s" },
+ { MIPS_INS_HSUB_U, "hsub_u" },
+ { MIPS_INS_ILVEV, "ilvev" },
+ { MIPS_INS_ILVL, "ilvl" },
+ { MIPS_INS_ILVOD, "ilvod" },
+ { MIPS_INS_ILVR, "ilvr" },
+ { MIPS_INS_INS, "ins" },
+ { MIPS_INS_INSERT, "insert" },
+ { MIPS_INS_INSV, "insv" },
+ { MIPS_INS_INSVE, "insve" },
+ { MIPS_INS_J, "j" },
+ { MIPS_INS_JAL, "jal" },
+ { MIPS_INS_JALR, "jalr" },
+ { MIPS_INS_JALRS16, "jalrs16" },
+ { MIPS_INS_JALRS, "jalrs" },
+ { MIPS_INS_JALS, "jals" },
+ { MIPS_INS_JALX, "jalx" },
+ { MIPS_INS_JIALC, "jialc" },
+ { MIPS_INS_JIC, "jic" },
+ { MIPS_INS_JR, "jr" },
+ { MIPS_INS_JR16, "jr16" },
+ { MIPS_INS_JRADDIUSP, "jraddiusp" },
+ { MIPS_INS_JRC, "jrc" },
+ { MIPS_INS_JALRC, "jalrc" },
+ { MIPS_INS_LB, "lb" },
+ { MIPS_INS_LBU16, "lbu16" },
+ { MIPS_INS_LBUX, "lbux" },
+ { MIPS_INS_LBU, "lbu" },
+ { MIPS_INS_LD, "ld" },
+ { MIPS_INS_LDC1, "ldc1" },
+ { MIPS_INS_LDC2, "ldc2" },
+ { MIPS_INS_LDC3, "ldc3" },
+ { MIPS_INS_LDI, "ldi" },
+ { MIPS_INS_LDL, "ldl" },
+ { MIPS_INS_LDPC, "ldpc" },
+ { MIPS_INS_LDR, "ldr" },
+ { MIPS_INS_LDXC1, "ldxc1" },
+ { MIPS_INS_LH, "lh" },
+ { MIPS_INS_LHU16, "lhu16" },
+ { MIPS_INS_LHX, "lhx" },
+ { MIPS_INS_LHU, "lhu" },
+ { MIPS_INS_LI16, "li16" },
+ { MIPS_INS_LL, "ll" },
+ { MIPS_INS_LLD, "lld" },
+ { MIPS_INS_LSA, "lsa" },
+ { MIPS_INS_LUXC1, "luxc1" },
+ { MIPS_INS_LUI, "lui" },
+ { MIPS_INS_LW, "lw" },
+ { MIPS_INS_LW16, "lw16" },
+ { MIPS_INS_LWC1, "lwc1" },
+ { MIPS_INS_LWC2, "lwc2" },
+ { MIPS_INS_LWC3, "lwc3" },
+ { MIPS_INS_LWL, "lwl" },
+ { MIPS_INS_LWM16, "lwm16" },
+ { MIPS_INS_LWM32, "lwm32" },
+ { MIPS_INS_LWPC, "lwpc" },
+ { MIPS_INS_LWP, "lwp" },
+ { MIPS_INS_LWR, "lwr" },
+ { MIPS_INS_LWUPC, "lwupc" },
+ { MIPS_INS_LWU, "lwu" },
+ { MIPS_INS_LWX, "lwx" },
+ { MIPS_INS_LWXC1, "lwxc1" },
+ { MIPS_INS_LWXS, "lwxs" },
+ { MIPS_INS_LI, "li" },
+ { MIPS_INS_MADD, "madd" },
+ { MIPS_INS_MADDF, "maddf" },
+ { MIPS_INS_MADDR_Q, "maddr_q" },
+ { MIPS_INS_MADDU, "maddu" },
+ { MIPS_INS_MADDV, "maddv" },
+ { MIPS_INS_MADD_Q, "madd_q" },
+ { MIPS_INS_MAQ_SA, "maq_sa" },
+ { MIPS_INS_MAQ_S, "maq_s" },
+ { MIPS_INS_MAXA, "maxa" },
+ { MIPS_INS_MAXI_S, "maxi_s" },
+ { MIPS_INS_MAXI_U, "maxi_u" },
+ { MIPS_INS_MAX_A, "max_a" },
+ { MIPS_INS_MAX, "max" },
+ { MIPS_INS_MAX_S, "max_s" },
+ { MIPS_INS_MAX_U, "max_u" },
+ { MIPS_INS_MFC0, "mfc0" },
+ { MIPS_INS_MFC1, "mfc1" },
+ { MIPS_INS_MFC2, "mfc2" },
+ { MIPS_INS_MFHC1, "mfhc1" },
+ { MIPS_INS_MFHI, "mfhi" },
+ { MIPS_INS_MFLO, "mflo" },
+ { MIPS_INS_MINA, "mina" },
+ { MIPS_INS_MINI_S, "mini_s" },
+ { MIPS_INS_MINI_U, "mini_u" },
+ { MIPS_INS_MIN_A, "min_a" },
+ { MIPS_INS_MIN, "min" },
+ { MIPS_INS_MIN_S, "min_s" },
+ { MIPS_INS_MIN_U, "min_u" },
+ { MIPS_INS_MOD, "mod" },
+ { MIPS_INS_MODSUB, "modsub" },
+ { MIPS_INS_MODU, "modu" },
+ { MIPS_INS_MOD_S, "mod_s" },
+ { MIPS_INS_MOD_U, "mod_u" },
+ { MIPS_INS_MOVE, "move" },
+ { MIPS_INS_MOVEP, "movep" },
+ { MIPS_INS_MOVF, "movf" },
+ { MIPS_INS_MOVN, "movn" },
+ { MIPS_INS_MOVT, "movt" },
+ { MIPS_INS_MOVZ, "movz" },
+ { MIPS_INS_MSUB, "msub" },
+ { MIPS_INS_MSUBF, "msubf" },
+ { MIPS_INS_MSUBR_Q, "msubr_q" },
+ { MIPS_INS_MSUBU, "msubu" },
+ { MIPS_INS_MSUBV, "msubv" },
+ { MIPS_INS_MSUB_Q, "msub_q" },
+ { MIPS_INS_MTC0, "mtc0" },
+ { MIPS_INS_MTC1, "mtc1" },
+ { MIPS_INS_MTC2, "mtc2" },
+ { MIPS_INS_MTHC1, "mthc1" },
+ { MIPS_INS_MTHI, "mthi" },
+ { MIPS_INS_MTHLIP, "mthlip" },
+ { MIPS_INS_MTLO, "mtlo" },
+ { MIPS_INS_MTM0, "mtm0" },
+ { MIPS_INS_MTM1, "mtm1" },
+ { MIPS_INS_MTM2, "mtm2" },
+ { MIPS_INS_MTP0, "mtp0" },
+ { MIPS_INS_MTP1, "mtp1" },
+ { MIPS_INS_MTP2, "mtp2" },
+ { MIPS_INS_MUH, "muh" },
+ { MIPS_INS_MUHU, "muhu" },
+ { MIPS_INS_MULEQ_S, "muleq_s" },
+ { MIPS_INS_MULEU_S, "muleu_s" },
+ { MIPS_INS_MULQ_RS, "mulq_rs" },
+ { MIPS_INS_MULQ_S, "mulq_s" },
+ { MIPS_INS_MULR_Q, "mulr_q" },
+ { MIPS_INS_MULSAQ_S, "mulsaq_s" },
+ { MIPS_INS_MULSA, "mulsa" },
+ { MIPS_INS_MULT, "mult" },
+ { MIPS_INS_MULTU, "multu" },
+ { MIPS_INS_MULU, "mulu" },
+ { MIPS_INS_MULV, "mulv" },
+ { MIPS_INS_MUL_Q, "mul_q" },
+ { MIPS_INS_MUL_S, "mul_s" },
+ { MIPS_INS_NLOC, "nloc" },
+ { MIPS_INS_NLZC, "nlzc" },
+ { MIPS_INS_NMADD, "nmadd" },
+ { MIPS_INS_NMSUB, "nmsub" },
+ { MIPS_INS_NOR, "nor" },
+ { MIPS_INS_NORI, "nori" },
+ { MIPS_INS_NOT16, "not16" },
+ { MIPS_INS_NOT, "not" },
+ { MIPS_INS_OR, "or" },
+ { MIPS_INS_OR16, "or16" },
+ { MIPS_INS_ORI, "ori" },
+ { MIPS_INS_PACKRL, "packrl" },
+ { MIPS_INS_PAUSE, "pause" },
+ { MIPS_INS_PCKEV, "pckev" },
+ { MIPS_INS_PCKOD, "pckod" },
+ { MIPS_INS_PCNT, "pcnt" },
+ { MIPS_INS_PICK, "pick" },
+ { MIPS_INS_POP, "pop" },
+ { MIPS_INS_PRECEQU, "precequ" },
+ { MIPS_INS_PRECEQ, "preceq" },
+ { MIPS_INS_PRECEU, "preceu" },
+ { MIPS_INS_PRECRQU_S, "precrqu_s" },
+ { MIPS_INS_PRECRQ, "precrq" },
+ { MIPS_INS_PRECRQ_RS, "precrq_rs" },
+ { MIPS_INS_PRECR, "precr" },
+ { MIPS_INS_PRECR_SRA, "precr_sra" },
+ { MIPS_INS_PRECR_SRA_R, "precr_sra_r" },
+ { MIPS_INS_PREF, "pref" },
+ { MIPS_INS_PREPEND, "prepend" },
+ { MIPS_INS_RADDU, "raddu" },
+ { MIPS_INS_RDDSP, "rddsp" },
+ { MIPS_INS_RDHWR, "rdhwr" },
+ { MIPS_INS_REPLV, "replv" },
+ { MIPS_INS_REPL, "repl" },
+ { MIPS_INS_RINT, "rint" },
+ { MIPS_INS_ROTR, "rotr" },
+ { MIPS_INS_ROTRV, "rotrv" },
+ { MIPS_INS_ROUND, "round" },
+ { MIPS_INS_SAT_S, "sat_s" },
+ { MIPS_INS_SAT_U, "sat_u" },
+ { MIPS_INS_SB, "sb" },
+ { MIPS_INS_SB16, "sb16" },
+ { MIPS_INS_SC, "sc" },
+ { MIPS_INS_SCD, "scd" },
+ { MIPS_INS_SD, "sd" },
+ { MIPS_INS_SDBBP, "sdbbp" },
+ { MIPS_INS_SDBBP16, "sdbbp16" },
+ { MIPS_INS_SDC1, "sdc1" },
+ { MIPS_INS_SDC2, "sdc2" },
+ { MIPS_INS_SDC3, "sdc3" },
+ { MIPS_INS_SDL, "sdl" },
+ { MIPS_INS_SDR, "sdr" },
+ { MIPS_INS_SDXC1, "sdxc1" },
+ { MIPS_INS_SEB, "seb" },
+ { MIPS_INS_SEH, "seh" },
+ { MIPS_INS_SELEQZ, "seleqz" },
+ { MIPS_INS_SELNEZ, "selnez" },
+ { MIPS_INS_SEL, "sel" },
+ { MIPS_INS_SEQ, "seq" },
+ { MIPS_INS_SEQI, "seqi" },
+ { MIPS_INS_SH, "sh" },
+ { MIPS_INS_SH16, "sh16" },
+ { MIPS_INS_SHF, "shf" },
+ { MIPS_INS_SHILO, "shilo" },
+ { MIPS_INS_SHILOV, "shilov" },
+ { MIPS_INS_SHLLV, "shllv" },
+ { MIPS_INS_SHLLV_S, "shllv_s" },
+ { MIPS_INS_SHLL, "shll" },
+ { MIPS_INS_SHLL_S, "shll_s" },
+ { MIPS_INS_SHRAV, "shrav" },
+ { MIPS_INS_SHRAV_R, "shrav_r" },
+ { MIPS_INS_SHRA, "shra" },
+ { MIPS_INS_SHRA_R, "shra_r" },
+ { MIPS_INS_SHRLV, "shrlv" },
+ { MIPS_INS_SHRL, "shrl" },
+ { MIPS_INS_SLDI, "sldi" },
+ { MIPS_INS_SLD, "sld" },
+ { MIPS_INS_SLL, "sll" },
+ { MIPS_INS_SLL16, "sll16" },
+ { MIPS_INS_SLLI, "slli" },
+ { MIPS_INS_SLLV, "sllv" },
+ { MIPS_INS_SLT, "slt" },
+ { MIPS_INS_SLTI, "slti" },
+ { MIPS_INS_SLTIU, "sltiu" },
+ { MIPS_INS_SLTU, "sltu" },
+ { MIPS_INS_SNE, "sne" },
+ { MIPS_INS_SNEI, "snei" },
+ { MIPS_INS_SPLATI, "splati" },
+ { MIPS_INS_SPLAT, "splat" },
+ { MIPS_INS_SRA, "sra" },
+ { MIPS_INS_SRAI, "srai" },
+ { MIPS_INS_SRARI, "srari" },
+ { MIPS_INS_SRAR, "srar" },
+ { MIPS_INS_SRAV, "srav" },
+ { MIPS_INS_SRL, "srl" },
+ { MIPS_INS_SRL16, "srl16" },
+ { MIPS_INS_SRLI, "srli" },
+ { MIPS_INS_SRLRI, "srlri" },
+ { MIPS_INS_SRLR, "srlr" },
+ { MIPS_INS_SRLV, "srlv" },
+ { MIPS_INS_SSNOP, "ssnop" },
+ { MIPS_INS_ST, "st" },
+ { MIPS_INS_SUBQH, "subqh" },
+ { MIPS_INS_SUBQH_R, "subqh_r" },
+ { MIPS_INS_SUBQ, "subq" },
+ { MIPS_INS_SUBQ_S, "subq_s" },
+ { MIPS_INS_SUBSUS_U, "subsus_u" },
+ { MIPS_INS_SUBSUU_S, "subsuu_s" },
+ { MIPS_INS_SUBS_S, "subs_s" },
+ { MIPS_INS_SUBS_U, "subs_u" },
+ { MIPS_INS_SUBU16, "subu16" },
+ { MIPS_INS_SUBUH, "subuh" },
+ { MIPS_INS_SUBUH_R, "subuh_r" },
+ { MIPS_INS_SUBU, "subu" },
+ { MIPS_INS_SUBU_S, "subu_s" },
+ { MIPS_INS_SUBVI, "subvi" },
+ { MIPS_INS_SUBV, "subv" },
+ { MIPS_INS_SUXC1, "suxc1" },
+ { MIPS_INS_SW, "sw" },
+ { MIPS_INS_SW16, "sw16" },
+ { MIPS_INS_SWC1, "swc1" },
+ { MIPS_INS_SWC2, "swc2" },
+ { MIPS_INS_SWC3, "swc3" },
+ { MIPS_INS_SWL, "swl" },
+ { MIPS_INS_SWM16, "swm16" },
+ { MIPS_INS_SWM32, "swm32" },
+ { MIPS_INS_SWP, "swp" },
+ { MIPS_INS_SWR, "swr" },
+ { MIPS_INS_SWXC1, "swxc1" },
+ { MIPS_INS_SYNC, "sync" },
+ { MIPS_INS_SYNCI, "synci" },
+ { MIPS_INS_SYSCALL, "syscall" },
+ { MIPS_INS_TEQ, "teq" },
+ { MIPS_INS_TEQI, "teqi" },
+ { MIPS_INS_TGE, "tge" },
+ { MIPS_INS_TGEI, "tgei" },
+ { MIPS_INS_TGEIU, "tgeiu" },
+ { MIPS_INS_TGEU, "tgeu" },
+ { MIPS_INS_TLBP, "tlbp" },
+ { MIPS_INS_TLBR, "tlbr" },
+ { MIPS_INS_TLBWI, "tlbwi" },
+ { MIPS_INS_TLBWR, "tlbwr" },
+ { MIPS_INS_TLT, "tlt" },
+ { MIPS_INS_TLTI, "tlti" },
+ { MIPS_INS_TLTIU, "tltiu" },
+ { MIPS_INS_TLTU, "tltu" },
+ { MIPS_INS_TNE, "tne" },
+ { MIPS_INS_TNEI, "tnei" },
+ { MIPS_INS_TRUNC, "trunc" },
+ { MIPS_INS_V3MULU, "v3mulu" },
+ { MIPS_INS_VMM0, "vmm0" },
+ { MIPS_INS_VMULU, "vmulu" },
+ { MIPS_INS_VSHF, "vshf" },
+ { MIPS_INS_WAIT, "wait" },
+ { MIPS_INS_WRDSP, "wrdsp" },
+ { MIPS_INS_WSBH, "wsbh" },
+ { MIPS_INS_XOR, "xor" },
+ { MIPS_INS_XOR16, "xor16" },
+ { MIPS_INS_XORI, "xori" },
+
+ // alias instructions
+ { MIPS_INS_NOP, "nop" },
+ { MIPS_INS_NEGU, "negu" },
+
+ { MIPS_INS_JALR_HB, "jalr.hb" },
+ { MIPS_INS_JR_HB, "jr.hb" },
+};
+
+const char *Mips_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+ if (id >= MIPS_INS_ENDING)
+ return NULL;
+
+ return insn_name_maps[id].name;
+#else
+ return NULL;
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static const name_map group_name_maps[] = {
+ // generic groups
+ { MIPS_GRP_INVALID, NULL },
+ { MIPS_GRP_JUMP, "jump" },
+ { MIPS_GRP_CALL, "call" },
+ { MIPS_GRP_RET, "ret" },
+ { MIPS_GRP_INT, "int" },
+ { MIPS_GRP_IRET, "iret" },
+ { MIPS_GRP_PRIVILEGE, "privileged" },
+ { MIPS_GRP_BRANCH_RELATIVE, "branch_relative" },
+
+ // architecture-specific groups
+ { MIPS_GRP_BITCOUNT, "bitcount" },
+ { MIPS_GRP_DSP, "dsp" },
+ { MIPS_GRP_DSPR2, "dspr2" },
+ { MIPS_GRP_FPIDX, "fpidx" },
+ { MIPS_GRP_MSA, "msa" },
+ { MIPS_GRP_MIPS32R2, "mips32r2" },
+ { MIPS_GRP_MIPS64, "mips64" },
+ { MIPS_GRP_MIPS64R2, "mips64r2" },
+ { MIPS_GRP_SEINREG, "seinreg" },
+ { MIPS_GRP_STDENC, "stdenc" },
+ { MIPS_GRP_SWAP, "swap" },
+ { MIPS_GRP_MICROMIPS, "micromips" },
+ { MIPS_GRP_MIPS16MODE, "mips16mode" },
+ { MIPS_GRP_FP64BIT, "fp64bit" },
+ { MIPS_GRP_NONANSFPMATH, "nonansfpmath" },
+ { MIPS_GRP_NOTFP64BIT, "notfp64bit" },
+ { MIPS_GRP_NOTINMICROMIPS, "notinmicromips" },
+ { MIPS_GRP_NOTNACL, "notnacl" },
+
+ { MIPS_GRP_NOTMIPS32R6, "notmips32r6" },
+ { MIPS_GRP_NOTMIPS64R6, "notmips64r6" },
+ { MIPS_GRP_CNMIPS, "cnmips" },
+
+ { MIPS_GRP_MIPS32, "mips32" },
+ { MIPS_GRP_MIPS32R6, "mips32r6" },
+ { MIPS_GRP_MIPS64R6, "mips64r6" },
+
+ { MIPS_GRP_MIPS2, "mips2" },
+ { MIPS_GRP_MIPS3, "mips3" },
+ { MIPS_GRP_MIPS3_32, "mips3_32"},
+ { MIPS_GRP_MIPS3_32R2, "mips3_32r2" },
+
+ { MIPS_GRP_MIPS4_32, "mips4_32" },
+ { MIPS_GRP_MIPS4_32R2, "mips4_32r2" },
+ { MIPS_GRP_MIPS5_32R2, "mips5_32r2" },
+
+ { MIPS_GRP_GP32BIT, "gp32bit" },
+ { MIPS_GRP_GP64BIT, "gp64bit" },
+};
+#endif
+
+const char *Mips_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+ return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
+#else
+ return NULL;
+#endif
+}
+
+// map instruction name to public instruction ID
+mips_reg Mips_map_insn(const char *name)
+{
+ // handle special alias first
+ unsigned int i;
+
+ // NOTE: skip first NULL name in insn_name_maps
+ i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name);
+
+ return (i != -1)? i : MIPS_REG_INVALID;
+}
+
+// map internal raw register to 'public' register
+mips_reg Mips_map_register(unsigned int r)
+{
+ // for some reasons different Mips modes can map different register number to
+ // the same Mips register. this function handles the issue for exposing Mips
+ // operands by mapping internal registers to 'public' register.
+ static const unsigned int map[] = { 0,
+ MIPS_REG_AT, MIPS_REG_DSPCCOND, MIPS_REG_DSPCARRY, MIPS_REG_DSPEFI, MIPS_REG_DSPOUTFLAG,
+ MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, MIPS_REG_FP, MIPS_REG_GP, MIPS_REG_2,
+ MIPS_REG_1, MIPS_REG_0, MIPS_REG_6, MIPS_REG_4, MIPS_REG_5,
+ MIPS_REG_3, MIPS_REG_7, MIPS_REG_PC, MIPS_REG_RA, MIPS_REG_SP,
+ MIPS_REG_ZERO, MIPS_REG_A0, MIPS_REG_A1, MIPS_REG_A2, MIPS_REG_A3,
+ MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3, MIPS_REG_AT,
+ MIPS_REG_CC0, MIPS_REG_CC1, MIPS_REG_CC2, MIPS_REG_CC3, MIPS_REG_CC4,
+ MIPS_REG_CC5, MIPS_REG_CC6, MIPS_REG_CC7, MIPS_REG_0, MIPS_REG_1,
+ MIPS_REG_2, MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6,
+ MIPS_REG_7, MIPS_REG_8, MIPS_REG_9, MIPS_REG_0, MIPS_REG_1,
+ MIPS_REG_2, MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6,
+ MIPS_REG_7, MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11,
+ MIPS_REG_12, MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16,
+ MIPS_REG_17, MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21,
+ MIPS_REG_22, MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26,
+ MIPS_REG_27, MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31,
+ MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, MIPS_REG_13, MIPS_REG_14,
+ MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, MIPS_REG_18, MIPS_REG_19,
+ MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, MIPS_REG_23, MIPS_REG_24,
+ MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, MIPS_REG_28, MIPS_REG_29,
+ MIPS_REG_30, MIPS_REG_31, MIPS_REG_F0, MIPS_REG_F2, MIPS_REG_F4,
+ MIPS_REG_F6, MIPS_REG_F8, MIPS_REG_F10, MIPS_REG_F12, MIPS_REG_F14,
+ MIPS_REG_F16, MIPS_REG_F18, MIPS_REG_F20, MIPS_REG_F22, MIPS_REG_F24,
+ MIPS_REG_F26, MIPS_REG_F28, MIPS_REG_F30, MIPS_REG_DSPOUTFLAG20, MIPS_REG_DSPOUTFLAG21,
+ MIPS_REG_DSPOUTFLAG22, MIPS_REG_DSPOUTFLAG23, MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2,
+ MIPS_REG_F3, MIPS_REG_F4, MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7,
+ MIPS_REG_F8, MIPS_REG_F9, MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12,
+ MIPS_REG_F13, MIPS_REG_F14, MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17,
+ MIPS_REG_F18, MIPS_REG_F19, MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22,
+ MIPS_REG_F23, MIPS_REG_F24, MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27,
+ MIPS_REG_F28, MIPS_REG_F29, MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_FCC0,
+ MIPS_REG_FCC1, MIPS_REG_FCC2, MIPS_REG_FCC3, MIPS_REG_FCC4, MIPS_REG_FCC5,
+ MIPS_REG_FCC6, MIPS_REG_FCC7, MIPS_REG_0, MIPS_REG_1, MIPS_REG_2,
+ MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7,
+ MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12,
+ MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17,
+ MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22,
+ MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27,
+ MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, MIPS_REG_FP,
+ MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3, MIPS_REG_F4,
+ MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8, MIPS_REG_F9,
+ MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13, MIPS_REG_F14,
+ MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18, MIPS_REG_F19,
+ MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23, MIPS_REG_F24,
+ MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28, MIPS_REG_F29,
+ MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_GP, MIPS_REG_AC0, MIPS_REG_AC1,
+ MIPS_REG_AC2, MIPS_REG_AC3, 0, 0, 0,
+ 0, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7,
+ MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12,
+ MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17,
+ MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22,
+ MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27,
+ MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, MIPS_REG_K0,
+ MIPS_REG_K1, MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3,
+ MIPS_REG_MPL0, MIPS_REG_MPL1, MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1,
+ MIPS_REG_P2, MIPS_REG_RA, MIPS_REG_S0, MIPS_REG_S1, MIPS_REG_S2,
+ MIPS_REG_S3, MIPS_REG_S4, MIPS_REG_S5, MIPS_REG_S6, MIPS_REG_S7,
+ MIPS_REG_SP, MIPS_REG_T0, MIPS_REG_T1, MIPS_REG_T2, MIPS_REG_T3,
+ MIPS_REG_T4, MIPS_REG_T5, MIPS_REG_T6, MIPS_REG_T7, MIPS_REG_T8,
+ MIPS_REG_T9, MIPS_REG_V0, MIPS_REG_V1, MIPS_REG_W0, MIPS_REG_W1,
+ MIPS_REG_W2, MIPS_REG_W3, MIPS_REG_W4, MIPS_REG_W5, MIPS_REG_W6,
+ MIPS_REG_W7, MIPS_REG_W8, MIPS_REG_W9, MIPS_REG_W10, MIPS_REG_W11,
+ MIPS_REG_W12, MIPS_REG_W13, MIPS_REG_W14, MIPS_REG_W15, MIPS_REG_W16,
+ MIPS_REG_W17, MIPS_REG_W18, MIPS_REG_W19, MIPS_REG_W20, MIPS_REG_W21,
+ MIPS_REG_W22, MIPS_REG_W23, MIPS_REG_W24, MIPS_REG_W25, MIPS_REG_W26,
+ MIPS_REG_W27, MIPS_REG_W28, MIPS_REG_W29, MIPS_REG_W30, MIPS_REG_W31,
+ MIPS_REG_ZERO, MIPS_REG_A0, MIPS_REG_A1, MIPS_REG_A2, MIPS_REG_A3,
+ MIPS_REG_AC0, MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3,
+ MIPS_REG_F4, MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8,
+ MIPS_REG_F9, MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13,
+ MIPS_REG_F14, MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18,
+ MIPS_REG_F19, MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23,
+ MIPS_REG_F24, MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28,
+ MIPS_REG_F29, MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_DSPOUTFLAG16_19, MIPS_REG_HI,
+ MIPS_REG_K0, MIPS_REG_K1, MIPS_REG_LO, MIPS_REG_S0, MIPS_REG_S1,
+ MIPS_REG_S2, MIPS_REG_S3, MIPS_REG_S4, MIPS_REG_S5, MIPS_REG_S6,
+ MIPS_REG_S7, MIPS_REG_T0, MIPS_REG_T1, MIPS_REG_T2, MIPS_REG_T3,
+ MIPS_REG_T4, MIPS_REG_T5, MIPS_REG_T6, MIPS_REG_T7, MIPS_REG_T8,
+ MIPS_REG_T9, MIPS_REG_V0, MIPS_REG_V1
+ };
+
+ if (r < ARR_SIZE(map))
+ return map[r];
+
+ // cannot find this register
+ return 0;
+}
+
+#endif
diff --git a/capstone/arch/Mips/MipsMapping.h b/capstone/arch/Mips/MipsMapping.h
new file mode 100644
index 000000000..42b86e6e9
--- /dev/null
+++ b/capstone/arch/Mips/MipsMapping.h
@@ -0,0 +1,25 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_MIPS_MAP_H
+#define CS_MIPS_MAP_H
+
+#include "capstone/capstone.h"
+
+// return name of regiser in friendly string
+const char *Mips_reg_name(csh handle, unsigned int reg);
+
+// given internal insn id, return public instruction info
+void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *Mips_insn_name(csh handle, unsigned int id);
+
+const char *Mips_group_name(csh handle, unsigned int id);
+
+// map instruction name to instruction ID
+mips_reg Mips_map_insn(const char *name);
+
+// map internal raw register to 'public' register
+mips_reg Mips_map_register(unsigned int r);
+
+#endif
diff --git a/capstone/arch/Mips/MipsMappingInsn.inc b/capstone/arch/Mips/MipsMappingInsn.inc
new file mode 100644
index 000000000..beb026c71
--- /dev/null
+++ b/capstone/arch/Mips/MipsMappingInsn.inc
@@ -0,0 +1,9315 @@
+// This is auto-gen data for Capstone engine (www.capstone-engine.org)
+// By Nguyen Anh Quynh <aquynh@gmail.com>
+
+{
+ Mips_ABSQ_S_PH, MIPS_INS_ABSQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ABSQ_S_QB, MIPS_INS_ABSQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ABSQ_S_W, MIPS_INS_ABSQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADD, MIPS_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDIUPC, MIPS_INS_ADDIUPC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDIUPC_MM, MIPS_INS_ADDIUPC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDIUR1SP_MM, MIPS_INS_ADDIUR1SP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDIUR2_MM, MIPS_INS_ADDIUR2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDIUS5_MM, MIPS_INS_ADDIUS5,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDIUSP_MM, MIPS_INS_ADDIUSP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDQH_PH, MIPS_INS_ADDQH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDQH_R_PH, MIPS_INS_ADDQH_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDQH_R_W, MIPS_INS_ADDQH_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDQH_W, MIPS_INS_ADDQH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDQ_PH, MIPS_INS_ADDQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDQ_S_PH, MIPS_INS_ADDQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDQ_S_W, MIPS_INS_ADDQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDSC, MIPS_INS_ADDSC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPCARRY, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDS_A_B, MIPS_INS_ADDS_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDS_A_D, MIPS_INS_ADDS_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDS_A_H, MIPS_INS_ADDS_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDS_A_W, MIPS_INS_ADDS_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDS_S_B, MIPS_INS_ADDS_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDS_S_D, MIPS_INS_ADDS_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDS_S_H, MIPS_INS_ADDS_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDS_S_W, MIPS_INS_ADDS_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDS_U_B, MIPS_INS_ADDS_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDS_U_D, MIPS_INS_ADDS_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDS_U_H, MIPS_INS_ADDS_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDS_U_W, MIPS_INS_ADDS_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDU16_MM, MIPS_INS_ADDU16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDUH_QB, MIPS_INS_ADDUH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDUH_R_QB, MIPS_INS_ADDUH_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDU_PH, MIPS_INS_ADDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDU_QB, MIPS_INS_ADDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDU_S_PH, MIPS_INS_ADDU_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDU_S_QB, MIPS_INS_ADDU_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDVI_B, MIPS_INS_ADDVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDVI_D, MIPS_INS_ADDVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDVI_H, MIPS_INS_ADDVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDVI_W, MIPS_INS_ADDVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDV_B, MIPS_INS_ADDV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDV_D, MIPS_INS_ADDV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDV_H, MIPS_INS_ADDV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDV_W, MIPS_INS_ADDV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDWC, MIPS_INS_ADDWC,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_DSPCARRY, 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADD_A_B, MIPS_INS_ADD_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADD_A_D, MIPS_INS_ADD_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADD_A_H, MIPS_INS_ADD_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADD_A_W, MIPS_INS_ADD_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADD_MM, MIPS_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDi, MIPS_INS_ADDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDi_MM, MIPS_INS_ADDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDiu, MIPS_INS_ADDIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDiu_MM, MIPS_INS_ADDIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDu, MIPS_INS_ADDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ADDu_MM, MIPS_INS_ADDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ALIGN, MIPS_INS_ALIGN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ALUIPC, MIPS_INS_ALUIPC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AND, MIPS_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AND16_MM, MIPS_INS_AND16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AND64, MIPS_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ANDI16_MM, MIPS_INS_ANDI16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ANDI_B, MIPS_INS_ANDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AND_MM, MIPS_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AND_V, MIPS_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ANDi, MIPS_INS_ANDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ANDi64, MIPS_INS_ANDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ANDi_MM, MIPS_INS_ANDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_APPEND, MIPS_INS_APPEND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ASUB_S_B, MIPS_INS_ASUB_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ASUB_S_D, MIPS_INS_ASUB_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ASUB_S_H, MIPS_INS_ASUB_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ASUB_S_W, MIPS_INS_ASUB_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ASUB_U_B, MIPS_INS_ASUB_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ASUB_U_D, MIPS_INS_ASUB_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ASUB_U_H, MIPS_INS_ASUB_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ASUB_U_W, MIPS_INS_ASUB_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AUI, MIPS_INS_AUI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AUIPC, MIPS_INS_AUIPC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AVER_S_B, MIPS_INS_AVER_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AVER_S_D, MIPS_INS_AVER_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AVER_S_H, MIPS_INS_AVER_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AVER_S_W, MIPS_INS_AVER_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AVER_U_B, MIPS_INS_AVER_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AVER_U_D, MIPS_INS_AVER_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AVER_U_H, MIPS_INS_AVER_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AVER_U_W, MIPS_INS_AVER_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AVE_S_B, MIPS_INS_AVE_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AVE_S_D, MIPS_INS_AVE_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AVE_S_H, MIPS_INS_AVE_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AVE_S_W, MIPS_INS_AVE_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AVE_U_B, MIPS_INS_AVE_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AVE_U_D, MIPS_INS_AVE_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AVE_U_H, MIPS_INS_AVE_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AVE_U_W, MIPS_INS_AVE_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AddiuRxImmX16, MIPS_INS_ADDIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AddiuRxPcImmX16, MIPS_INS_ADDIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AddiuRxRxImm16, MIPS_INS_ADDIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AddiuRxRxImmX16, MIPS_INS_ADDIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AddiuRxRyOffMemX16, MIPS_INS_ADDIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AddiuSpImm16, MIPS_INS_ADDIU,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AddiuSpImmX16, MIPS_INS_ADDIU,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AdduRxRyRz16, MIPS_INS_ADDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_AndRxRxRy16, MIPS_INS_AND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_B16_MM, MIPS_INS_B16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BADDu, MIPS_INS_BADDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BAL, MIPS_INS_BAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BALC, MIPS_INS_BALC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BALIGN, MIPS_INS_BALIGN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BBIT0, MIPS_INS_BBIT0,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BBIT032, MIPS_INS_BBIT032,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BBIT1, MIPS_INS_BBIT1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BBIT132, MIPS_INS_BBIT132,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BC, MIPS_INS_BC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BC0F, MIPS_INS_BC0F,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BC0FL, MIPS_INS_BC0FL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BC0T, MIPS_INS_BC0T,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BC0TL, MIPS_INS_BC0TL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BC1EQZ, MIPS_INS_BC1EQZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BC1F, MIPS_INS_BC1F,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BC1FL, MIPS_INS_BC1FL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BC1F_MM, MIPS_INS_BC1F,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BC1NEZ, MIPS_INS_BC1NEZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BC1T, MIPS_INS_BC1T,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BC1TL, MIPS_INS_BC1TL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BC1T_MM, MIPS_INS_BC1T,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BC2EQZ, MIPS_INS_BC2EQZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BC2F, MIPS_INS_BC2F,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BC2FL, MIPS_INS_BC2FL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BC2NEZ, MIPS_INS_BC2NEZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BC2T, MIPS_INS_BC2T,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BC2TL, MIPS_INS_BC2TL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BC3F, MIPS_INS_BC3F,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BC3FL, MIPS_INS_BC3FL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BC3T, MIPS_INS_BC3T,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BC3TL, MIPS_INS_BC3TL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BCLRI_B, MIPS_INS_BCLRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BCLRI_D, MIPS_INS_BCLRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BCLRI_H, MIPS_INS_BCLRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BCLRI_W, MIPS_INS_BCLRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BCLR_B, MIPS_INS_BCLR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BCLR_D, MIPS_INS_BCLR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BCLR_H, MIPS_INS_BCLR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BCLR_W, MIPS_INS_BCLR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BEQ, MIPS_INS_BEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BEQ64, MIPS_INS_BEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BEQC, MIPS_INS_BEQC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BEQL, MIPS_INS_BEQL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BEQZ16_MM, MIPS_INS_BEQZ16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BEQZALC, MIPS_INS_BEQZALC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BEQZC, MIPS_INS_BEQZC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BEQZC_MM, MIPS_INS_BEQZC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BEQ_MM, MIPS_INS_BEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BGEC, MIPS_INS_BGEC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BGEUC, MIPS_INS_BGEUC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BGEZ, MIPS_INS_BGEZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BGEZ64, MIPS_INS_BGEZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BGEZAL, MIPS_INS_BGEZAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BGEZALC, MIPS_INS_BGEZALC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BGEZALL, MIPS_INS_BGEZALL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BGEZALS_MM, MIPS_INS_BGEZALS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BGEZAL_MM, MIPS_INS_BGEZAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BGEZC, MIPS_INS_BGEZC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BGEZL, MIPS_INS_BGEZL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BGEZ_MM, MIPS_INS_BGEZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BGTZ, MIPS_INS_BGTZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BGTZ64, MIPS_INS_BGTZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BGTZALC, MIPS_INS_BGTZALC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BGTZC, MIPS_INS_BGTZC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BGTZL, MIPS_INS_BGTZL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BGTZ_MM, MIPS_INS_BGTZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BINSLI_B, MIPS_INS_BINSLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BINSLI_D, MIPS_INS_BINSLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BINSLI_H, MIPS_INS_BINSLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BINSLI_W, MIPS_INS_BINSLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BINSL_B, MIPS_INS_BINSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BINSL_D, MIPS_INS_BINSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BINSL_H, MIPS_INS_BINSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BINSL_W, MIPS_INS_BINSL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BINSRI_B, MIPS_INS_BINSRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BINSRI_D, MIPS_INS_BINSRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BINSRI_H, MIPS_INS_BINSRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BINSRI_W, MIPS_INS_BINSRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BINSR_B, MIPS_INS_BINSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BINSR_D, MIPS_INS_BINSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BINSR_H, MIPS_INS_BINSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BINSR_W, MIPS_INS_BINSR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BITREV, MIPS_INS_BITREV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BITSWAP, MIPS_INS_BITSWAP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BLEZ, MIPS_INS_BLEZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BLEZ64, MIPS_INS_BLEZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BLEZALC, MIPS_INS_BLEZALC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BLEZC, MIPS_INS_BLEZC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BLEZL, MIPS_INS_BLEZL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BLEZ_MM, MIPS_INS_BLEZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BLTC, MIPS_INS_BLTC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BLTUC, MIPS_INS_BLTUC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BLTZ, MIPS_INS_BLTZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BLTZ64, MIPS_INS_BLTZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BLTZAL, MIPS_INS_BLTZAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BLTZALC, MIPS_INS_BLTZALC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BLTZALL, MIPS_INS_BLTZALL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BLTZALS_MM, MIPS_INS_BLTZALS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BLTZAL_MM, MIPS_INS_BLTZAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BLTZC, MIPS_INS_BLTZC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BLTZL, MIPS_INS_BLTZL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BLTZ_MM, MIPS_INS_BLTZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BMNZI_B, MIPS_INS_BMNZI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BMNZ_V, MIPS_INS_BMNZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BMZI_B, MIPS_INS_BMZI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BMZ_V, MIPS_INS_BMZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BNE, MIPS_INS_BNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BNE64, MIPS_INS_BNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BNEC, MIPS_INS_BNEC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BNEGI_B, MIPS_INS_BNEGI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BNEGI_D, MIPS_INS_BNEGI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BNEGI_H, MIPS_INS_BNEGI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BNEGI_W, MIPS_INS_BNEGI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BNEG_B, MIPS_INS_BNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BNEG_D, MIPS_INS_BNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BNEG_H, MIPS_INS_BNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BNEG_W, MIPS_INS_BNEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BNEL, MIPS_INS_BNEL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BNEZ16_MM, MIPS_INS_BNEZ16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BNEZALC, MIPS_INS_BNEZALC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BNEZC, MIPS_INS_BNEZC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BNEZC_MM, MIPS_INS_BNEZC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BNE_MM, MIPS_INS_BNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BNVC, MIPS_INS_BNVC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BNZ_B, MIPS_INS_BNZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BNZ_D, MIPS_INS_BNZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BNZ_H, MIPS_INS_BNZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BNZ_V, MIPS_INS_BNZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BNZ_W, MIPS_INS_BNZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BOVC, MIPS_INS_BOVC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BPOSGE32, MIPS_INS_BPOSGE32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_DSP, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BREAK, MIPS_INS_BREAK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BREAK16_MM, MIPS_INS_BREAK16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BREAK_MM, MIPS_INS_BREAK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BSELI_B, MIPS_INS_BSELI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BSEL_V, MIPS_INS_BSEL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BSETI_B, MIPS_INS_BSETI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BSETI_D, MIPS_INS_BSETI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BSETI_H, MIPS_INS_BSETI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BSETI_W, MIPS_INS_BSETI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BSET_B, MIPS_INS_BSET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BSET_D, MIPS_INS_BSET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BSET_H, MIPS_INS_BSET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BSET_W, MIPS_INS_BSET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_BZ_B, MIPS_INS_BZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BZ_D, MIPS_INS_BZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BZ_H, MIPS_INS_BZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BZ_V, MIPS_INS_BZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BZ_W, MIPS_INS_BZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BeqzRxImm16, MIPS_INS_BEQZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BeqzRxImmX16, MIPS_INS_BEQZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
+#endif
+},
+{
+ Mips_Bimm16, MIPS_INS_B,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BimmX16, MIPS_INS_B,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BnezRxImm16, MIPS_INS_BNEZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BnezRxImmX16, MIPS_INS_BNEZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
+#endif
+},
+{
+ Mips_Break16, MIPS_INS_BREAK,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_Bteqz16, MIPS_INS_BTEQZ,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BteqzX16, MIPS_INS_BTEQZ,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
+#endif
+},
+{
+ Mips_Btnez16, MIPS_INS_BTNEZ,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
+#endif
+},
+{
+ Mips_BtnezX16, MIPS_INS_BTNEZ,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
+#endif
+},
+{
+ Mips_CACHE, MIPS_INS_CACHE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CACHE_MM, MIPS_INS_CACHE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CACHE_R6, MIPS_INS_CACHE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CEIL_L_D64, MIPS_INS_CEIL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CEIL_L_S, MIPS_INS_CEIL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CEIL_W_D32, MIPS_INS_CEIL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CEIL_W_D64, MIPS_INS_CEIL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CEIL_W_MM, MIPS_INS_CEIL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CEIL_W_S, MIPS_INS_CEIL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CEIL_W_S_MM, MIPS_INS_CEIL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CEQI_B, MIPS_INS_CEQI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CEQI_D, MIPS_INS_CEQI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CEQI_H, MIPS_INS_CEQI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CEQI_W, MIPS_INS_CEQI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CEQ_B, MIPS_INS_CEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CEQ_D, MIPS_INS_CEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CEQ_H, MIPS_INS_CEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CEQ_W, MIPS_INS_CEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CFC1, MIPS_INS_CFC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CFC1_MM, MIPS_INS_CFC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CFCMSA, MIPS_INS_CFCMSA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CINS, MIPS_INS_CINS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CINS32, MIPS_INS_CINS32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLASS_D, MIPS_INS_CLASS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLASS_S, MIPS_INS_CLASS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLEI_S_B, MIPS_INS_CLEI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLEI_S_D, MIPS_INS_CLEI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLEI_S_H, MIPS_INS_CLEI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLEI_S_W, MIPS_INS_CLEI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLEI_U_B, MIPS_INS_CLEI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLEI_U_D, MIPS_INS_CLEI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLEI_U_H, MIPS_INS_CLEI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLEI_U_W, MIPS_INS_CLEI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLE_S_B, MIPS_INS_CLE_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLE_S_D, MIPS_INS_CLE_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLE_S_H, MIPS_INS_CLE_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLE_S_W, MIPS_INS_CLE_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLE_U_B, MIPS_INS_CLE_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLE_U_D, MIPS_INS_CLE_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLE_U_H, MIPS_INS_CLE_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLE_U_W, MIPS_INS_CLE_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLO, MIPS_INS_CLO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLO_MM, MIPS_INS_CLO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLO_R6, MIPS_INS_CLO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLTI_S_B, MIPS_INS_CLTI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLTI_S_D, MIPS_INS_CLTI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLTI_S_H, MIPS_INS_CLTI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLTI_S_W, MIPS_INS_CLTI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLTI_U_B, MIPS_INS_CLTI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLTI_U_D, MIPS_INS_CLTI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLTI_U_H, MIPS_INS_CLTI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLTI_U_W, MIPS_INS_CLTI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLT_S_B, MIPS_INS_CLT_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLT_S_D, MIPS_INS_CLT_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLT_S_H, MIPS_INS_CLT_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLT_S_W, MIPS_INS_CLT_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLT_U_B, MIPS_INS_CLT_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLT_U_D, MIPS_INS_CLT_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLT_U_H, MIPS_INS_CLT_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLT_U_W, MIPS_INS_CLT_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLZ, MIPS_INS_CLZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLZ_MM, MIPS_INS_CLZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CLZ_R6, MIPS_INS_CLZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMPGDU_EQ_QB, MIPS_INS_CMPGDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMPGDU_LE_QB, MIPS_INS_CMPGDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMPGDU_LT_QB, MIPS_INS_CMPGDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMPGU_EQ_QB, MIPS_INS_CMPGU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMPGU_LE_QB, MIPS_INS_CMPGU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMPGU_LT_QB, MIPS_INS_CMPGU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMPU_EQ_QB, MIPS_INS_CMPU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMPU_LE_QB, MIPS_INS_CMPU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMPU_LT_QB, MIPS_INS_CMPU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_EQ_D, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_EQ_PH, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_EQ_S, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_F_D, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_F_S, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_LE_D, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_LE_PH, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_LE_S, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_LT_D, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_LT_PH, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_LT_S, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_SAF_D, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_SAF_S, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_SEQ_D, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_SEQ_S, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_SLE_D, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_SLE_S, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_SLT_D, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_SLT_S, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_SUEQ_D, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_SUEQ_S, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_SULE_D, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_SULE_S, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_SULT_D, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_SULT_S, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_SUN_D, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_SUN_S, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_UEQ_D, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_UEQ_S, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_ULE_D, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_ULE_S, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_ULT_D, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_ULT_S, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_UN_D, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CMP_UN_S, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_COPY_S_B, MIPS_INS_COPY_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_COPY_S_D, MIPS_INS_COPY_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0
+#endif
+},
+{
+ Mips_COPY_S_H, MIPS_INS_COPY_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_COPY_S_W, MIPS_INS_COPY_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_COPY_U_B, MIPS_INS_COPY_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_COPY_U_D, MIPS_INS_COPY_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0
+#endif
+},
+{
+ Mips_COPY_U_H, MIPS_INS_COPY_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_COPY_U_W, MIPS_INS_COPY_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CTC1, MIPS_INS_CTC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CTC1_MM, MIPS_INS_CTC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CTCMSA, MIPS_INS_CTCMSA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CVT_D32_S, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CVT_D32_W, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CVT_D32_W_MM, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CVT_D64_L, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CVT_D64_S, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CVT_D64_W, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CVT_D_S_MM, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CVT_L_D64, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CVT_L_D64_MM, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CVT_L_S, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CVT_L_S_MM, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CVT_S_D32, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CVT_S_D32_MM, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CVT_S_D64, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CVT_S_L, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CVT_S_W, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CVT_S_W_MM, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CVT_W_D32, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CVT_W_D64, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CVT_W_MM, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CVT_W_S, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CVT_W_S_MM, MIPS_INS_CVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_EQ_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_EQ_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_EQ_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_F_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_F_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_F_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_LE_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_LE_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_LE_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_LT_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_LT_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_LT_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_NGE_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_NGE_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_NGE_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_NGLE_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_NGLE_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_NGLE_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_NGL_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_NGL_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_NGL_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_NGT_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_NGT_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_NGT_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_OLE_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_OLE_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_OLE_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_OLT_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_OLT_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_OLT_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_SEQ_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_SEQ_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_SEQ_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_SF_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_SF_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_SF_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_UEQ_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_UEQ_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_UEQ_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_ULE_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_ULE_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_ULE_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_ULT_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_ULT_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_ULT_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_UN_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_UN_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_C_UN_S, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CmpRxRy16, MIPS_INS_CMP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CmpiRxImm16, MIPS_INS_CMPI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_CmpiRxImmX16, MIPS_INS_CMPI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DADD, MIPS_INS_DADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DADDi, MIPS_INS_DADDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DADDiu, MIPS_INS_DADDIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DADDu, MIPS_INS_DADDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DAHI, MIPS_INS_DAHI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DALIGN, MIPS_INS_DALIGN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DATI, MIPS_INS_DATI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DAUI, MIPS_INS_DAUI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DBITSWAP, MIPS_INS_DBITSWAP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DCLO, MIPS_INS_DCLO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DCLO_R6, MIPS_INS_DCLO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DCLZ, MIPS_INS_DCLZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DCLZ_R6, MIPS_INS_DCLZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DDIV, MIPS_INS_DDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DDIVU, MIPS_INS_DDIVU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DERET, MIPS_INS_DERET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DERET_MM, MIPS_INS_DERET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DEXT, MIPS_INS_DEXT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DEXTM, MIPS_INS_DEXTM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DEXTU, MIPS_INS_DEXTU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DI, MIPS_INS_DI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DINS, MIPS_INS_DINS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DINSM, MIPS_INS_DINSM,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DINSU, MIPS_INS_DINSU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DIV, MIPS_INS_DIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DIVU, MIPS_INS_DIVU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DIV_S_B, MIPS_INS_DIV_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DIV_S_D, MIPS_INS_DIV_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DIV_S_H, MIPS_INS_DIV_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DIV_S_W, MIPS_INS_DIV_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DIV_U_B, MIPS_INS_DIV_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DIV_U_D, MIPS_INS_DIV_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DIV_U_H, MIPS_INS_DIV_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DIV_U_W, MIPS_INS_DIV_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DI_MM, MIPS_INS_DI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DLSA, MIPS_INS_DLSA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DLSA_R6, MIPS_INS_DLSA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DMFC0, MIPS_INS_DMFC0,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DMFC1, MIPS_INS_DMFC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DMFC2, MIPS_INS_DMFC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DMOD, MIPS_INS_DMOD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DMODU, MIPS_INS_DMODU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DMTC0, MIPS_INS_DMTC0,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DMTC1, MIPS_INS_DMTC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DMTC2, MIPS_INS_DMTC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DMUH, MIPS_INS_DMUH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DMUHU, MIPS_INS_DMUHU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DMUL, MIPS_INS_DMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DMULT, MIPS_INS_DMULT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DMULTu, MIPS_INS_DMULTU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DMULU, MIPS_INS_DMULU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DMUL_R6, MIPS_INS_DMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DOTP_S_D, MIPS_INS_DOTP_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DOTP_S_H, MIPS_INS_DOTP_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DOTP_S_W, MIPS_INS_DOTP_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DOTP_U_D, MIPS_INS_DOTP_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DOTP_U_H, MIPS_INS_DOTP_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DOTP_U_W, MIPS_INS_DOTP_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPADD_S_D, MIPS_INS_DPADD_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPADD_S_H, MIPS_INS_DPADD_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPADD_S_W, MIPS_INS_DPADD_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPADD_U_D, MIPS_INS_DPADD_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPADD_U_H, MIPS_INS_DPADD_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPADD_U_W, MIPS_INS_DPADD_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPAQX_SA_W_PH, MIPS_INS_DPAQX_SA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPAQX_S_W_PH, MIPS_INS_DPAQX_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPAQ_SA_L_W, MIPS_INS_DPAQ_SA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPAQ_S_W_PH, MIPS_INS_DPAQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPAU_H_QBL, MIPS_INS_DPAU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPAU_H_QBR, MIPS_INS_DPAU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPAX_W_PH, MIPS_INS_DPAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPA_W_PH, MIPS_INS_DPA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPOP, MIPS_INS_DPOP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPSQX_SA_W_PH, MIPS_INS_DPSQX_SA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPSQX_S_W_PH, MIPS_INS_DPSQX_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPSQ_SA_L_W, MIPS_INS_DPSQ_SA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPSQ_S_W_PH, MIPS_INS_DPSQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPSUB_S_D, MIPS_INS_DPSUB_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPSUB_S_H, MIPS_INS_DPSUB_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPSUB_S_W, MIPS_INS_DPSUB_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPSUB_U_D, MIPS_INS_DPSUB_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPSUB_U_H, MIPS_INS_DPSUB_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPSUB_U_W, MIPS_INS_DPSUB_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPSU_H_QBL, MIPS_INS_DPSU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPSU_H_QBR, MIPS_INS_DPSU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPSX_W_PH, MIPS_INS_DPSX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DPS_W_PH, MIPS_INS_DPS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DROTR, MIPS_INS_DROTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DROTR32, MIPS_INS_DROTR32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DROTRV, MIPS_INS_DROTRV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DSBH, MIPS_INS_DSBH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DSDIV, MIPS_INS_DDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DSHD, MIPS_INS_DSHD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DSLL, MIPS_INS_DSLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DSLL32, MIPS_INS_DSLL32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DSLL64_32, MIPS_INS_DSLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DSLLV, MIPS_INS_DSLLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DSRA, MIPS_INS_DSRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DSRA32, MIPS_INS_DSRA32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DSRAV, MIPS_INS_DSRAV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DSRL, MIPS_INS_DSRL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DSRL32, MIPS_INS_DSRL32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DSRLV, MIPS_INS_DSRLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DSUB, MIPS_INS_DSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DSUBu, MIPS_INS_DSUBU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DUDIV, MIPS_INS_DDIVU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DivRxRy16, MIPS_INS_DIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_DivuRxRy16, MIPS_INS_DIVU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_EHB, MIPS_INS_EHB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_EHB_MM, MIPS_INS_EHB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_EI, MIPS_INS_EI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_EI_MM, MIPS_INS_EI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ERET, MIPS_INS_ERET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ERET_MM, MIPS_INS_ERET,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_EXT, MIPS_INS_EXT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_EXTP, MIPS_INS_EXTP,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_EXTPDP, MIPS_INS_EXTPDP,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_EXTPDPV, MIPS_INS_EXTPDPV,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_EXTPV, MIPS_INS_EXTPV,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_EXTRV_RS_W, MIPS_INS_EXTRV_RS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_EXTRV_R_W, MIPS_INS_EXTRV_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_EXTRV_S_H, MIPS_INS_EXTRV_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_EXTRV_W, MIPS_INS_EXTRV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_EXTR_RS_W, MIPS_INS_EXTR_RS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_EXTR_R_W, MIPS_INS_EXTR_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_EXTR_S_H, MIPS_INS_EXTR_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_EXTR_W, MIPS_INS_EXTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_EXTS, MIPS_INS_EXTS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_EXTS32, MIPS_INS_EXTS32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_EXT_MM, MIPS_INS_EXT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FABS_D32, MIPS_INS_ABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FABS_D64, MIPS_INS_ABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FABS_MM, MIPS_INS_ABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FABS_S, MIPS_INS_ABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FABS_S_MM, MIPS_INS_ABS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FADD_D, MIPS_INS_FADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FADD_D32, MIPS_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FADD_D64, MIPS_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FADD_MM, MIPS_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FADD_S, MIPS_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FADD_S_MM, MIPS_INS_ADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FADD_W, MIPS_INS_FADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCAF_D, MIPS_INS_FCAF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCAF_W, MIPS_INS_FCAF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCEQ_D, MIPS_INS_FCEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCEQ_W, MIPS_INS_FCEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCLASS_D, MIPS_INS_FCLASS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCLASS_W, MIPS_INS_FCLASS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCLE_D, MIPS_INS_FCLE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCLE_W, MIPS_INS_FCLE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCLT_D, MIPS_INS_FCLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCLT_W, MIPS_INS_FCLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCMP_D32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCMP_D32_MM, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCMP_D64, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCMP_S32, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCMP_S32_MM, MIPS_INS_C,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCNE_D, MIPS_INS_FCNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCNE_W, MIPS_INS_FCNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCOR_D, MIPS_INS_FCOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCOR_W, MIPS_INS_FCOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCUEQ_D, MIPS_INS_FCUEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCUEQ_W, MIPS_INS_FCUEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCULE_D, MIPS_INS_FCULE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCULE_W, MIPS_INS_FCULE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCULT_D, MIPS_INS_FCULT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCULT_W, MIPS_INS_FCULT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCUNE_D, MIPS_INS_FCUNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCUNE_W, MIPS_INS_FCUNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCUN_D, MIPS_INS_FCUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FCUN_W, MIPS_INS_FCUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FDIV_D, MIPS_INS_FDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FDIV_D32, MIPS_INS_DIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FDIV_D64, MIPS_INS_DIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FDIV_MM, MIPS_INS_DIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FDIV_S, MIPS_INS_DIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FDIV_S_MM, MIPS_INS_DIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FDIV_W, MIPS_INS_FDIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FEXDO_H, MIPS_INS_FEXDO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FEXDO_W, MIPS_INS_FEXDO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FEXP2_D, MIPS_INS_FEXP2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FEXP2_W, MIPS_INS_FEXP2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FEXUPL_D, MIPS_INS_FEXUPL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FEXUPL_W, MIPS_INS_FEXUPL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FEXUPR_D, MIPS_INS_FEXUPR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FEXUPR_W, MIPS_INS_FEXUPR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FFINT_S_D, MIPS_INS_FFINT_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FFINT_S_W, MIPS_INS_FFINT_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FFINT_U_D, MIPS_INS_FFINT_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FFINT_U_W, MIPS_INS_FFINT_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FFQL_D, MIPS_INS_FFQL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FFQL_W, MIPS_INS_FFQL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FFQR_D, MIPS_INS_FFQR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FFQR_W, MIPS_INS_FFQR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FILL_B, MIPS_INS_FILL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FILL_D, MIPS_INS_FILL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FILL_H, MIPS_INS_FILL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FILL_W, MIPS_INS_FILL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FLOG2_D, MIPS_INS_FLOG2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FLOG2_W, MIPS_INS_FLOG2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FLOOR_L_D64, MIPS_INS_FLOOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FLOOR_L_S, MIPS_INS_FLOOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FLOOR_W_D32, MIPS_INS_FLOOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FLOOR_W_D64, MIPS_INS_FLOOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FLOOR_W_MM, MIPS_INS_FLOOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FLOOR_W_S, MIPS_INS_FLOOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FLOOR_W_S_MM, MIPS_INS_FLOOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FMADD_D, MIPS_INS_FMADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FMADD_W, MIPS_INS_FMADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FMAX_A_D, MIPS_INS_FMAX_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FMAX_A_W, MIPS_INS_FMAX_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FMAX_D, MIPS_INS_FMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FMAX_W, MIPS_INS_FMAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FMIN_A_D, MIPS_INS_FMIN_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FMIN_A_W, MIPS_INS_FMIN_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FMIN_D, MIPS_INS_FMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FMIN_W, MIPS_INS_FMIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FMOV_D32, MIPS_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FMOV_D32_MM, MIPS_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FMOV_D64, MIPS_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FMOV_S, MIPS_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FMOV_S_MM, MIPS_INS_MOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FMSUB_D, MIPS_INS_FMSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FMSUB_W, MIPS_INS_FMSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FMUL_D, MIPS_INS_FMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FMUL_D32, MIPS_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FMUL_D64, MIPS_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FMUL_MM, MIPS_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FMUL_S, MIPS_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FMUL_S_MM, MIPS_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FMUL_W, MIPS_INS_FMUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FNEG_D32, MIPS_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FNEG_D64, MIPS_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FNEG_MM, MIPS_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FNEG_S, MIPS_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FNEG_S_MM, MIPS_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FRCP_D, MIPS_INS_FRCP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FRCP_W, MIPS_INS_FRCP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FRINT_D, MIPS_INS_FRINT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FRINT_W, MIPS_INS_FRINT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FRSQRT_D, MIPS_INS_FRSQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FRSQRT_W, MIPS_INS_FRSQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSAF_D, MIPS_INS_FSAF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSAF_W, MIPS_INS_FSAF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSEQ_D, MIPS_INS_FSEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSEQ_W, MIPS_INS_FSEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSLE_D, MIPS_INS_FSLE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSLE_W, MIPS_INS_FSLE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSLT_D, MIPS_INS_FSLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSLT_W, MIPS_INS_FSLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSNE_D, MIPS_INS_FSNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSNE_W, MIPS_INS_FSNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSOR_D, MIPS_INS_FSOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSOR_W, MIPS_INS_FSOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSQRT_D, MIPS_INS_FSQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSQRT_D32, MIPS_INS_SQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSQRT_D64, MIPS_INS_SQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSQRT_MM, MIPS_INS_SQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSQRT_S, MIPS_INS_SQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSQRT_S_MM, MIPS_INS_SQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSQRT_W, MIPS_INS_FSQRT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSUB_D, MIPS_INS_FSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSUB_D32, MIPS_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSUB_D64, MIPS_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSUB_MM, MIPS_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSUB_S, MIPS_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSUB_S_MM, MIPS_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSUB_W, MIPS_INS_FSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSUEQ_D, MIPS_INS_FSUEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSUEQ_W, MIPS_INS_FSUEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSULE_D, MIPS_INS_FSULE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSULE_W, MIPS_INS_FSULE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSULT_D, MIPS_INS_FSULT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSULT_W, MIPS_INS_FSULT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSUNE_D, MIPS_INS_FSUNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSUNE_W, MIPS_INS_FSUNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSUN_D, MIPS_INS_FSUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FSUN_W, MIPS_INS_FSUN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FTINT_S_D, MIPS_INS_FTINT_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FTINT_S_W, MIPS_INS_FTINT_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FTINT_U_D, MIPS_INS_FTINT_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FTINT_U_W, MIPS_INS_FTINT_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FTQ_H, MIPS_INS_FTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FTQ_W, MIPS_INS_FTQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FTRUNC_S_D, MIPS_INS_FTRUNC_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FTRUNC_S_W, MIPS_INS_FTRUNC_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FTRUNC_U_D, MIPS_INS_FTRUNC_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_FTRUNC_U_W, MIPS_INS_FTRUNC_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_HADD_S_D, MIPS_INS_HADD_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_HADD_S_H, MIPS_INS_HADD_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_HADD_S_W, MIPS_INS_HADD_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_HADD_U_D, MIPS_INS_HADD_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_HADD_U_H, MIPS_INS_HADD_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_HADD_U_W, MIPS_INS_HADD_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_HSUB_S_D, MIPS_INS_HSUB_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_HSUB_S_H, MIPS_INS_HSUB_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_HSUB_S_W, MIPS_INS_HSUB_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_HSUB_U_D, MIPS_INS_HSUB_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_HSUB_U_H, MIPS_INS_HSUB_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_HSUB_U_W, MIPS_INS_HSUB_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ILVEV_B, MIPS_INS_ILVEV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ILVEV_D, MIPS_INS_ILVEV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ILVEV_H, MIPS_INS_ILVEV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ILVEV_W, MIPS_INS_ILVEV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ILVL_B, MIPS_INS_ILVL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ILVL_D, MIPS_INS_ILVL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ILVL_H, MIPS_INS_ILVL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ILVL_W, MIPS_INS_ILVL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ILVOD_B, MIPS_INS_ILVOD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ILVOD_D, MIPS_INS_ILVOD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ILVOD_H, MIPS_INS_ILVOD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ILVOD_W, MIPS_INS_ILVOD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ILVR_B, MIPS_INS_ILVR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ILVR_D, MIPS_INS_ILVR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ILVR_H, MIPS_INS_ILVR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ILVR_W, MIPS_INS_ILVR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_INS, MIPS_INS_INS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_INSERT_B, MIPS_INS_INSERT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_INSERT_D, MIPS_INS_INSERT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0
+#endif
+},
+{
+ Mips_INSERT_H, MIPS_INS_INSERT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_INSERT_W, MIPS_INS_INSERT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_INSV, MIPS_INS_INSV,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_INSVE_B, MIPS_INS_INSVE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_INSVE_D, MIPS_INS_INSVE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_INSVE_H, MIPS_INS_INSVE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_INSVE_W, MIPS_INS_INSVE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_INS_MM, MIPS_INS_INS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_J, MIPS_INS_J,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
+#endif
+},
+{
+ Mips_JAL, MIPS_INS_JAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_JALR, MIPS_INS_JALR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0
+#endif
+},
+{
+ Mips_JALR16_MM, MIPS_INS_JALR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0
+#endif
+},
+{
+ Mips_JALR64, MIPS_INS_JALR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_CALL, 0 }, 0, 0
+#endif
+},
+{
+ Mips_JALRS16_MM, MIPS_INS_JALRS16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0
+#endif
+},
+{
+ Mips_JALRS_MM, MIPS_INS_JALRS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0
+#endif
+},
+{
+ Mips_JALR_HB, MIPS_INS_JALR_HB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_CALL, 0 }, 0, 1
+#endif
+},
+{
+ Mips_JALR_MM, MIPS_INS_JALR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0
+#endif
+},
+{
+ Mips_JALS_MM, MIPS_INS_JALS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_JALX, MIPS_INS_JALX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_JALX_MM, MIPS_INS_JALX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_JAL_MM, MIPS_INS_JAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_JIALC, MIPS_INS_JIALC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_JIC, MIPS_INS_JIC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_JR, MIPS_INS_JR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 1, 1
+#endif
+},
+{
+ Mips_JR16_MM, MIPS_INS_JR16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1
+#endif
+},
+{
+ Mips_JR64, MIPS_INS_JR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 1, 1
+#endif
+},
+{
+ Mips_JRADDIUSP, MIPS_INS_JRADDIUSP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1
+#endif
+},
+{
+ Mips_JRC16_MM, MIPS_INS_JRC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1
+#endif
+},
+{
+ Mips_JR_HB, MIPS_INS_JR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 1
+#endif
+},
+{
+ Mips_JR_HB_R6, MIPS_INS_JR_HB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 1
+#endif
+},
+{
+ Mips_JR_MM, MIPS_INS_JR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1
+#endif
+},
+{
+ Mips_J_MM, MIPS_INS_J,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_Jal16, MIPS_INS_JAL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_JrRa16, MIPS_INS_JR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1
+#endif
+},
+{
+ Mips_JrcRa16, MIPS_INS_JRC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1
+#endif
+},
+{
+ Mips_JrcRx16, MIPS_INS_JRC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1
+#endif
+},
+{
+ Mips_JumpLinkReg16, MIPS_INS_JALRC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MIPS16MODE, MIPS_GRP_CALL, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LB, MIPS_INS_LB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LB64, MIPS_INS_LB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LBU16_MM, MIPS_INS_LBU16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LBUX, MIPS_INS_LBUX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LB_MM, MIPS_INS_LB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LBu, MIPS_INS_LBU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LBu64, MIPS_INS_LBU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LBu_MM, MIPS_INS_LBU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LD, MIPS_INS_LD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LDC1, MIPS_INS_LDC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LDC164, MIPS_INS_LDC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LDC1_MM, MIPS_INS_LDC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LDC2, MIPS_INS_LDC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LDC2_R6, MIPS_INS_LDC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LDC3, MIPS_INS_LDC3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LDI_B, MIPS_INS_LDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LDI_D, MIPS_INS_LDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LDI_H, MIPS_INS_LDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LDI_W, MIPS_INS_LDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LDL, MIPS_INS_LDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LDPC, MIPS_INS_LDPC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LDR, MIPS_INS_LDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LDXC1, MIPS_INS_LDXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_NOTNACL, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LDXC164, MIPS_INS_LDXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LD_B, MIPS_INS_LD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LD_D, MIPS_INS_LD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LD_H, MIPS_INS_LD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LD_W, MIPS_INS_LD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LEA_ADDiu, MIPS_INS_ADDIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LEA_ADDiu64, MIPS_INS_DADDIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LEA_ADDiu_MM, MIPS_INS_ADDIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LH, MIPS_INS_LH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LH64, MIPS_INS_LH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LHU16_MM, MIPS_INS_LHU16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LHX, MIPS_INS_LHX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LH_MM, MIPS_INS_LH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LHu, MIPS_INS_LHU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LHu64, MIPS_INS_LHU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LHu_MM, MIPS_INS_LHU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LI16_MM, MIPS_INS_LI16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LL, MIPS_INS_LL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LLD, MIPS_INS_LLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LLD_R6, MIPS_INS_LLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LL_MM, MIPS_INS_LL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LL_R6, MIPS_INS_LL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LSA, MIPS_INS_LSA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LSA_R6, MIPS_INS_LSA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LUXC1, MIPS_INS_LUXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LUXC164, MIPS_INS_LUXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LUXC1_MM, MIPS_INS_LUXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LUi, MIPS_INS_LUI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LUi64, MIPS_INS_LUI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LUi_MM, MIPS_INS_LUI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LW, MIPS_INS_LW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LW16_MM, MIPS_INS_LW16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LW64, MIPS_INS_LW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LWC1, MIPS_INS_LWC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LWC1_MM, MIPS_INS_LWC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LWC2, MIPS_INS_LWC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LWC2_R6, MIPS_INS_LWC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LWC3, MIPS_INS_LWC3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LWGP_MM, MIPS_INS_LW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LWL, MIPS_INS_LWL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LWL64, MIPS_INS_LWL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LWL_MM, MIPS_INS_LWL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LWM16_MM, MIPS_INS_LWM16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LWM32_MM, MIPS_INS_LWM32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LWPC, MIPS_INS_LWPC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LWP_MM, MIPS_INS_LWP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LWR, MIPS_INS_LWR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LWR64, MIPS_INS_LWR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LWR_MM, MIPS_INS_LWR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LWSP_MM, MIPS_INS_LW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LWUPC, MIPS_INS_LWUPC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LWU_MM, MIPS_INS_LWU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LWX, MIPS_INS_LWX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LWXC1, MIPS_INS_LWXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LWXC1_MM, MIPS_INS_LWXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LWXS_MM, MIPS_INS_LWXS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LW_MM, MIPS_INS_LW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LWu, MIPS_INS_LWU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LbRxRyOffMemX16, MIPS_INS_LB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LbuRxRyOffMemX16, MIPS_INS_LBU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LhRxRyOffMemX16, MIPS_INS_LH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LhuRxRyOffMemX16, MIPS_INS_LHU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LiRxImm16, MIPS_INS_LI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LiRxImmX16, MIPS_INS_LI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LwRxPcTcp16, MIPS_INS_LW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LwRxPcTcpX16, MIPS_INS_LW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LwRxRyOffMemX16, MIPS_INS_LW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_LwRxSpImmX16, MIPS_INS_LW,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_SP, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MADD, MIPS_INS_MADD,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MADDF_D, MIPS_INS_MADDF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MADDF_S, MIPS_INS_MADDF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MADDR_Q_H, MIPS_INS_MADDR_Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MADDR_Q_W, MIPS_INS_MADDR_Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MADDU, MIPS_INS_MADDU,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MADDU_DSP, MIPS_INS_MADDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MADDU_MM, MIPS_INS_MADDU,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MADDV_B, MIPS_INS_MADDV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MADDV_D, MIPS_INS_MADDV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MADDV_H, MIPS_INS_MADDV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MADDV_W, MIPS_INS_MADDV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MADD_D32, MIPS_INS_MADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MADD_D32_MM, MIPS_INS_MADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MADD_D64, MIPS_INS_MADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MADD_DSP, MIPS_INS_MADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MADD_MM, MIPS_INS_MADD,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MADD_Q_H, MIPS_INS_MADD_Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MADD_Q_W, MIPS_INS_MADD_Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MADD_S, MIPS_INS_MADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MADD_S_MM, MIPS_INS_MADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAQ_SA_W_PHL, MIPS_INS_MAQ_SA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAQ_SA_W_PHR, MIPS_INS_MAQ_SA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAQ_S_W_PHL, MIPS_INS_MAQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAQ_S_W_PHR, MIPS_INS_MAQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAXA_D, MIPS_INS_MAXA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAXA_S, MIPS_INS_MAXA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAXI_S_B, MIPS_INS_MAXI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAXI_S_D, MIPS_INS_MAXI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAXI_S_H, MIPS_INS_MAXI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAXI_S_W, MIPS_INS_MAXI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAXI_U_B, MIPS_INS_MAXI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAXI_U_D, MIPS_INS_MAXI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAXI_U_H, MIPS_INS_MAXI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAXI_U_W, MIPS_INS_MAXI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAX_A_B, MIPS_INS_MAX_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAX_A_D, MIPS_INS_MAX_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAX_A_H, MIPS_INS_MAX_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAX_A_W, MIPS_INS_MAX_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAX_D, MIPS_INS_MAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAX_S, MIPS_INS_MAX,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAX_S_B, MIPS_INS_MAX_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAX_S_D, MIPS_INS_MAX_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAX_S_H, MIPS_INS_MAX_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAX_S_W, MIPS_INS_MAX_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAX_U_B, MIPS_INS_MAX_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAX_U_D, MIPS_INS_MAX_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAX_U_H, MIPS_INS_MAX_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MAX_U_W, MIPS_INS_MAX_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MFC0, MIPS_INS_MFC0,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MFC1, MIPS_INS_MFC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MFC1_MM, MIPS_INS_MFC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MFC2, MIPS_INS_MFC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MFHC1_D32, MIPS_INS_MFHC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MFHC1_D64, MIPS_INS_MFHC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MFHC1_MM, MIPS_INS_MFHC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MFHI, MIPS_INS_MFHI,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MFHI16_MM, MIPS_INS_MFHI,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MFHI64, MIPS_INS_MFHI,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MFHI_DSP, MIPS_INS_MFHI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MFHI_MM, MIPS_INS_MFHI,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MFLO, MIPS_INS_MFLO,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MFLO16_MM, MIPS_INS_MFLO,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MFLO64, MIPS_INS_MFLO,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MFLO_DSP, MIPS_INS_MFLO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MFLO_MM, MIPS_INS_MFLO,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MINA_D, MIPS_INS_MINA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MINA_S, MIPS_INS_MINA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MINI_S_B, MIPS_INS_MINI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MINI_S_D, MIPS_INS_MINI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MINI_S_H, MIPS_INS_MINI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MINI_S_W, MIPS_INS_MINI_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MINI_U_B, MIPS_INS_MINI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MINI_U_D, MIPS_INS_MINI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MINI_U_H, MIPS_INS_MINI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MINI_U_W, MIPS_INS_MINI_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MIN_A_B, MIPS_INS_MIN_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MIN_A_D, MIPS_INS_MIN_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MIN_A_H, MIPS_INS_MIN_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MIN_A_W, MIPS_INS_MIN_A,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MIN_D, MIPS_INS_MIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MIN_S, MIPS_INS_MIN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MIN_S_B, MIPS_INS_MIN_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MIN_S_D, MIPS_INS_MIN_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MIN_S_H, MIPS_INS_MIN_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MIN_S_W, MIPS_INS_MIN_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MIN_U_B, MIPS_INS_MIN_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MIN_U_D, MIPS_INS_MIN_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MIN_U_H, MIPS_INS_MIN_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MIN_U_W, MIPS_INS_MIN_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOD, MIPS_INS_MOD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MODSUB, MIPS_INS_MODSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MODU, MIPS_INS_MODU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOD_S_B, MIPS_INS_MOD_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOD_S_D, MIPS_INS_MOD_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOD_S_H, MIPS_INS_MOD_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOD_S_W, MIPS_INS_MOD_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOD_U_B, MIPS_INS_MOD_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOD_U_D, MIPS_INS_MOD_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOD_U_H, MIPS_INS_MOD_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOD_U_W, MIPS_INS_MOD_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVE16_MM, MIPS_INS_MOVE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVEP_MM, MIPS_INS_MOVEP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVE_V, MIPS_INS_MOVE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVF_D32, MIPS_INS_MOVF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVF_D32_MM, MIPS_INS_MOVF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVF_D64, MIPS_INS_MOVF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVF_I, MIPS_INS_MOVF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVF_I64, MIPS_INS_MOVF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVF_I_MM, MIPS_INS_MOVF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVF_S, MIPS_INS_MOVF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVF_S_MM, MIPS_INS_MOVF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVN_I64_D64, MIPS_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVN_I64_I, MIPS_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVN_I64_I64, MIPS_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVN_I64_S, MIPS_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVN_I_D32, MIPS_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVN_I_D32_MM, MIPS_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVN_I_D64, MIPS_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVN_I_I, MIPS_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVN_I_I64, MIPS_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVN_I_MM, MIPS_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVN_I_S, MIPS_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVN_I_S_MM, MIPS_INS_MOVN,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVT_D32, MIPS_INS_MOVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVT_D32_MM, MIPS_INS_MOVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVT_D64, MIPS_INS_MOVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVT_I, MIPS_INS_MOVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVT_I64, MIPS_INS_MOVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVT_I_MM, MIPS_INS_MOVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVT_S, MIPS_INS_MOVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVT_S_MM, MIPS_INS_MOVT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVZ_I64_D64, MIPS_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVZ_I64_I, MIPS_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVZ_I64_I64, MIPS_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVZ_I64_S, MIPS_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_MIPS64, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVZ_I_D32, MIPS_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVZ_I_D32_MM, MIPS_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVZ_I_D64, MIPS_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVZ_I_I, MIPS_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVZ_I_I64, MIPS_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVZ_I_MM, MIPS_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVZ_I_S, MIPS_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MOVZ_I_S_MM, MIPS_INS_MOVZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MSUB, MIPS_INS_MSUB,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MSUBF_D, MIPS_INS_MSUBF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MSUBF_S, MIPS_INS_MSUBF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MSUBR_Q_H, MIPS_INS_MSUBR_Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MSUBR_Q_W, MIPS_INS_MSUBR_Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MSUBU, MIPS_INS_MSUBU,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MSUBU_DSP, MIPS_INS_MSUBU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MSUBU_MM, MIPS_INS_MSUBU,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MSUBV_B, MIPS_INS_MSUBV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MSUBV_D, MIPS_INS_MSUBV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MSUBV_H, MIPS_INS_MSUBV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MSUBV_W, MIPS_INS_MSUBV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MSUB_D32, MIPS_INS_MSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MSUB_D32_MM, MIPS_INS_MSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MSUB_D64, MIPS_INS_MSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MSUB_DSP, MIPS_INS_MSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MSUB_MM, MIPS_INS_MSUB,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MSUB_Q_H, MIPS_INS_MSUB_Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MSUB_Q_W, MIPS_INS_MSUB_Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MSUB_S, MIPS_INS_MSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MSUB_S_MM, MIPS_INS_MSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MTC0, MIPS_INS_MTC0,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MTC1, MIPS_INS_MTC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MTC1_MM, MIPS_INS_MTC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MTC2, MIPS_INS_MTC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MTHC1_D32, MIPS_INS_MTHC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MTHC1_D64, MIPS_INS_MTHC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MTHC1_MM, MIPS_INS_MTHC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MTHI, MIPS_INS_MTHI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MTHI64, MIPS_INS_MTHI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MTHI_DSP, MIPS_INS_MTHI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MTHI_MM, MIPS_INS_MTHI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MTHLIP, MIPS_INS_MTHLIP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPPOS, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MTLO, MIPS_INS_MTLO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MTLO64, MIPS_INS_MTLO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MTLO_DSP, MIPS_INS_MTLO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MTLO_MM, MIPS_INS_MTLO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MTM0, MIPS_INS_MTM0,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_MPL0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MTM1, MIPS_INS_MTM1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_MPL1, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MTM2, MIPS_INS_MTM2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MTP0, MIPS_INS_MTP0,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_P0, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MTP1, MIPS_INS_MTP1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_P1, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MTP2, MIPS_INS_MTP2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MUH, MIPS_INS_MUH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MUHU, MIPS_INS_MUHU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MUL, MIPS_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MULEQ_S_W_PHL, MIPS_INS_MULEQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MULEQ_S_W_PHR, MIPS_INS_MULEQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MULEU_S_PH_QBL, MIPS_INS_MULEU_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MULEU_S_PH_QBR, MIPS_INS_MULEU_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MULQ_RS_PH, MIPS_INS_MULQ_RS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MULQ_RS_W, MIPS_INS_MULQ_RS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MULQ_S_PH, MIPS_INS_MULQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MULQ_S_W, MIPS_INS_MULQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MULR_Q_H, MIPS_INS_MULR_Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MULR_Q_W, MIPS_INS_MULR_Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MULSAQ_S_W_PH, MIPS_INS_MULSAQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MULSA_W_PH, MIPS_INS_MULSA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MULT, MIPS_INS_MULT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MULTU_DSP, MIPS_INS_MULTU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MULT_DSP, MIPS_INS_MULT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MULT_MM, MIPS_INS_MULT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MULTu, MIPS_INS_MULTU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MULTu_MM, MIPS_INS_MULTU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MULU, MIPS_INS_MULU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MULV_B, MIPS_INS_MULV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MULV_D, MIPS_INS_MULV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MULV_H, MIPS_INS_MULV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MULV_W, MIPS_INS_MULV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MUL_MM, MIPS_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MUL_PH, MIPS_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MUL_Q_H, MIPS_INS_MUL_Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MUL_Q_W, MIPS_INS_MUL_Q,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MUL_R6, MIPS_INS_MUL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MUL_S_PH, MIPS_INS_MUL_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_Mfhi16, MIPS_INS_MFHI,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_HI0, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_Mflo16, MIPS_INS_MFLO,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_LO0, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_Move32R16, MIPS_INS_MOVE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_MoveR3216, MIPS_INS_MOVE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NLOC_B, MIPS_INS_NLOC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NLOC_D, MIPS_INS_NLOC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NLOC_H, MIPS_INS_NLOC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NLOC_W, MIPS_INS_NLOC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NLZC_B, MIPS_INS_NLZC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NLZC_D, MIPS_INS_NLZC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NLZC_H, MIPS_INS_NLZC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NLZC_W, MIPS_INS_NLZC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NMADD_D32, MIPS_INS_NMADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NMADD_D32_MM, MIPS_INS_NMADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NMADD_D64, MIPS_INS_NMADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NMADD_S, MIPS_INS_NMADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NMADD_S_MM, MIPS_INS_NMADD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NMSUB_D32, MIPS_INS_NMSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NMSUB_D32_MM, MIPS_INS_NMSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NMSUB_D64, MIPS_INS_NMSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NMSUB_S, MIPS_INS_NMSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NMSUB_S_MM, MIPS_INS_NMSUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NOR, MIPS_INS_NOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NOR64, MIPS_INS_NOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NORI_B, MIPS_INS_NORI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NOR_MM, MIPS_INS_NOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NOR_V, MIPS_INS_NOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NOT16_MM, MIPS_INS_NOT16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NegRxRy16, MIPS_INS_NEG,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_NotRxRy16, MIPS_INS_NOT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_OR, MIPS_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_OR16_MM, MIPS_INS_OR16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_OR64, MIPS_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ORI_B, MIPS_INS_ORI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_OR_MM, MIPS_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_OR_V, MIPS_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ORi, MIPS_INS_ORI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ORi64, MIPS_INS_ORI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ORi_MM, MIPS_INS_ORI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_OrRxRxRy16, MIPS_INS_OR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PACKRL_PH, MIPS_INS_PACKRL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PAUSE, MIPS_INS_PAUSE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PAUSE_MM, MIPS_INS_PAUSE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PCKEV_B, MIPS_INS_PCKEV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PCKEV_D, MIPS_INS_PCKEV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PCKEV_H, MIPS_INS_PCKEV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PCKEV_W, MIPS_INS_PCKEV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PCKOD_B, MIPS_INS_PCKOD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PCKOD_D, MIPS_INS_PCKOD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PCKOD_H, MIPS_INS_PCKOD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PCKOD_W, MIPS_INS_PCKOD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PCNT_B, MIPS_INS_PCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PCNT_D, MIPS_INS_PCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PCNT_H, MIPS_INS_PCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PCNT_W, MIPS_INS_PCNT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PICK_PH, MIPS_INS_PICK,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PICK_QB, MIPS_INS_PICK,
+#ifndef CAPSTONE_DIET
+ { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_POP, MIPS_INS_POP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PRECEQU_PH_QBL, MIPS_INS_PRECEQU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PRECEQU_PH_QBLA, MIPS_INS_PRECEQU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PRECEQU_PH_QBR, MIPS_INS_PRECEQU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PRECEQU_PH_QBRA, MIPS_INS_PRECEQU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PRECEQ_W_PHL, MIPS_INS_PRECEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PRECEQ_W_PHR, MIPS_INS_PRECEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PRECEU_PH_QBL, MIPS_INS_PRECEU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PRECEU_PH_QBLA, MIPS_INS_PRECEU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PRECEU_PH_QBR, MIPS_INS_PRECEU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PRECEU_PH_QBRA, MIPS_INS_PRECEU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PRECRQU_S_QB_PH, MIPS_INS_PRECRQU_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PRECRQ_PH_W, MIPS_INS_PRECRQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PRECRQ_QB_PH, MIPS_INS_PRECRQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PRECRQ_RS_PH_W, MIPS_INS_PRECRQ_RS,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PRECR_QB_PH, MIPS_INS_PRECR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PRECR_SRA_PH_W, MIPS_INS_PRECR_SRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PRECR_SRA_R_PH_W, MIPS_INS_PRECR_SRA_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PREF, MIPS_INS_PREF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PREF_MM, MIPS_INS_PREF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PREF_R6, MIPS_INS_PREF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_PREPEND, MIPS_INS_PREPEND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_RADDU_W_QB, MIPS_INS_RADDU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_RDDSP, MIPS_INS_RDDSP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_RDHWR, MIPS_INS_RDHWR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_RDHWR64, MIPS_INS_RDHWR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_RDHWR_MM, MIPS_INS_RDHWR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_REPLV_PH, MIPS_INS_REPLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_REPLV_QB, MIPS_INS_REPLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_REPL_PH, MIPS_INS_REPL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_REPL_QB, MIPS_INS_REPL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_RINT_D, MIPS_INS_RINT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_RINT_S, MIPS_INS_RINT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ROTR, MIPS_INS_ROTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ROTRV, MIPS_INS_ROTRV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ROTRV_MM, MIPS_INS_ROTRV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ROTR_MM, MIPS_INS_ROTR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ROUND_L_D64, MIPS_INS_ROUND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ROUND_L_S, MIPS_INS_ROUND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ROUND_W_D32, MIPS_INS_ROUND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ROUND_W_D64, MIPS_INS_ROUND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ROUND_W_MM, MIPS_INS_ROUND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ROUND_W_S, MIPS_INS_ROUND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ROUND_W_S_MM, MIPS_INS_ROUND,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SAT_S_B, MIPS_INS_SAT_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SAT_S_D, MIPS_INS_SAT_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SAT_S_H, MIPS_INS_SAT_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SAT_S_W, MIPS_INS_SAT_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SAT_U_B, MIPS_INS_SAT_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SAT_U_D, MIPS_INS_SAT_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SAT_U_H, MIPS_INS_SAT_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SAT_U_W, MIPS_INS_SAT_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SB, MIPS_INS_SB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SB16_MM, MIPS_INS_SB16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SB64, MIPS_INS_SB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SB_MM, MIPS_INS_SB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SC, MIPS_INS_SC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SCD, MIPS_INS_SCD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SCD_R6, MIPS_INS_SCD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SC_MM, MIPS_INS_SC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SC_R6, MIPS_INS_SC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SD, MIPS_INS_SD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SDBBP, MIPS_INS_SDBBP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SDBBP16_MM, MIPS_INS_SDBBP16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SDBBP_MM, MIPS_INS_SDBBP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SDBBP_R6, MIPS_INS_SDBBP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SDC1, MIPS_INS_SDC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SDC164, MIPS_INS_SDC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SDC1_MM, MIPS_INS_SDC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SDC2, MIPS_INS_SDC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SDC2_R6, MIPS_INS_SDC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SDC3, MIPS_INS_SDC3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SDIV, MIPS_INS_DIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SDIV_MM, MIPS_INS_DIV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SDL, MIPS_INS_SDL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SDR, MIPS_INS_SDR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SDXC1, MIPS_INS_SDXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_NOTNACL, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SDXC164, MIPS_INS_SDXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SEB, MIPS_INS_SEB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SEB64, MIPS_INS_SEB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SEB_MM, MIPS_INS_SEB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SEH, MIPS_INS_SEH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SEH64, MIPS_INS_SEH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SEH_MM, MIPS_INS_SEH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SELEQZ, MIPS_INS_SELEQZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SELEQZ64, MIPS_INS_SELEQZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SELEQZ_D, MIPS_INS_SELEQZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SELEQZ_S, MIPS_INS_SELEQZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SELNEZ, MIPS_INS_SELNEZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SELNEZ64, MIPS_INS_SELNEZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SELNEZ_D, MIPS_INS_SELNEZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SELNEZ_S, MIPS_INS_SELNEZ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SEL_D, MIPS_INS_SEL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SEL_S, MIPS_INS_SEL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SEQ, MIPS_INS_SEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SEQi, MIPS_INS_SEQI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SH, MIPS_INS_SH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SH16_MM, MIPS_INS_SH16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SH64, MIPS_INS_SH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHF_B, MIPS_INS_SHF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHF_H, MIPS_INS_SHF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHF_W, MIPS_INS_SHF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHILO, MIPS_INS_SHILO,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHILOV, MIPS_INS_SHILOV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHLLV_PH, MIPS_INS_SHLLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHLLV_QB, MIPS_INS_SHLLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHLLV_S_PH, MIPS_INS_SHLLV_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHLLV_S_W, MIPS_INS_SHLLV_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHLL_PH, MIPS_INS_SHLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHLL_QB, MIPS_INS_SHLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHLL_S_PH, MIPS_INS_SHLL_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHLL_S_W, MIPS_INS_SHLL_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHRAV_PH, MIPS_INS_SHRAV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHRAV_QB, MIPS_INS_SHRAV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHRAV_R_PH, MIPS_INS_SHRAV_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHRAV_R_QB, MIPS_INS_SHRAV_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHRAV_R_W, MIPS_INS_SHRAV_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHRA_PH, MIPS_INS_SHRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHRA_QB, MIPS_INS_SHRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHRA_R_PH, MIPS_INS_SHRA_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHRA_R_QB, MIPS_INS_SHRA_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHRA_R_W, MIPS_INS_SHRA_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHRLV_PH, MIPS_INS_SHRLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHRLV_QB, MIPS_INS_SHRLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHRL_PH, MIPS_INS_SHRL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SHRL_QB, MIPS_INS_SHRL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SH_MM, MIPS_INS_SH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLDI_B, MIPS_INS_SLDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLDI_D, MIPS_INS_SLDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLDI_H, MIPS_INS_SLDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLDI_W, MIPS_INS_SLDI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLD_B, MIPS_INS_SLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLD_D, MIPS_INS_SLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLD_H, MIPS_INS_SLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLD_W, MIPS_INS_SLD,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLL, MIPS_INS_SLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLL16_MM, MIPS_INS_SLL16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLL64_32, MIPS_INS_SLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLL64_64, MIPS_INS_SLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLLI_B, MIPS_INS_SLLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLLI_D, MIPS_INS_SLLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLLI_H, MIPS_INS_SLLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLLI_W, MIPS_INS_SLLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLLV, MIPS_INS_SLLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLLV_MM, MIPS_INS_SLLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLL_B, MIPS_INS_SLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLL_D, MIPS_INS_SLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLL_H, MIPS_INS_SLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLL_MM, MIPS_INS_SLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLL_W, MIPS_INS_SLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLT, MIPS_INS_SLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLT64, MIPS_INS_SLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLT_MM, MIPS_INS_SLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLTi, MIPS_INS_SLTI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLTi64, MIPS_INS_SLTI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLTi_MM, MIPS_INS_SLTI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLTiu, MIPS_INS_SLTIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLTiu64, MIPS_INS_SLTIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLTiu_MM, MIPS_INS_SLTIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLTu, MIPS_INS_SLTU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLTu64, MIPS_INS_SLTU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SLTu_MM, MIPS_INS_SLTU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SNE, MIPS_INS_SNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SNEi, MIPS_INS_SNEI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SPLATI_B, MIPS_INS_SPLATI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SPLATI_D, MIPS_INS_SPLATI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SPLATI_H, MIPS_INS_SPLATI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SPLATI_W, MIPS_INS_SPLATI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SPLAT_B, MIPS_INS_SPLAT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SPLAT_D, MIPS_INS_SPLAT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SPLAT_H, MIPS_INS_SPLAT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SPLAT_W, MIPS_INS_SPLAT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRA, MIPS_INS_SRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRAI_B, MIPS_INS_SRAI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRAI_D, MIPS_INS_SRAI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRAI_H, MIPS_INS_SRAI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRAI_W, MIPS_INS_SRAI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRARI_B, MIPS_INS_SRARI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRARI_D, MIPS_INS_SRARI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRARI_H, MIPS_INS_SRARI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRARI_W, MIPS_INS_SRARI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRAR_B, MIPS_INS_SRAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRAR_D, MIPS_INS_SRAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRAR_H, MIPS_INS_SRAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRAR_W, MIPS_INS_SRAR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRAV, MIPS_INS_SRAV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRAV_MM, MIPS_INS_SRAV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRA_B, MIPS_INS_SRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRA_D, MIPS_INS_SRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRA_H, MIPS_INS_SRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRA_MM, MIPS_INS_SRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRA_W, MIPS_INS_SRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRL, MIPS_INS_SRL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRL16_MM, MIPS_INS_SRL16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRLI_B, MIPS_INS_SRLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRLI_D, MIPS_INS_SRLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRLI_H, MIPS_INS_SRLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRLI_W, MIPS_INS_SRLI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRLRI_B, MIPS_INS_SRLRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRLRI_D, MIPS_INS_SRLRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRLRI_H, MIPS_INS_SRLRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRLRI_W, MIPS_INS_SRLRI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRLR_B, MIPS_INS_SRLR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRLR_D, MIPS_INS_SRLR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRLR_H, MIPS_INS_SRLR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRLR_W, MIPS_INS_SRLR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRLV, MIPS_INS_SRLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRLV_MM, MIPS_INS_SRLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRL_B, MIPS_INS_SRL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRL_D, MIPS_INS_SRL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRL_H, MIPS_INS_SRL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRL_MM, MIPS_INS_SRL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SRL_W, MIPS_INS_SRL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SSNOP, MIPS_INS_SSNOP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SSNOP_MM, MIPS_INS_SSNOP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ST_B, MIPS_INS_ST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ST_D, MIPS_INS_ST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ST_H, MIPS_INS_ST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ST_W, MIPS_INS_ST,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUB, MIPS_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBQH_PH, MIPS_INS_SUBQH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBQH_R_PH, MIPS_INS_SUBQH_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBQH_R_W, MIPS_INS_SUBQH_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBQH_W, MIPS_INS_SUBQH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBQ_PH, MIPS_INS_SUBQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBQ_S_PH, MIPS_INS_SUBQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBQ_S_W, MIPS_INS_SUBQ_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBSUS_U_B, MIPS_INS_SUBSUS_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBSUS_U_D, MIPS_INS_SUBSUS_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBSUS_U_H, MIPS_INS_SUBSUS_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBSUS_U_W, MIPS_INS_SUBSUS_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBSUU_S_B, MIPS_INS_SUBSUU_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBSUU_S_D, MIPS_INS_SUBSUU_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBSUU_S_H, MIPS_INS_SUBSUU_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBSUU_S_W, MIPS_INS_SUBSUU_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBS_S_B, MIPS_INS_SUBS_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBS_S_D, MIPS_INS_SUBS_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBS_S_H, MIPS_INS_SUBS_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBS_S_W, MIPS_INS_SUBS_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBS_U_B, MIPS_INS_SUBS_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBS_U_D, MIPS_INS_SUBS_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBS_U_H, MIPS_INS_SUBS_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBS_U_W, MIPS_INS_SUBS_U,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBU16_MM, MIPS_INS_SUBU16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBUH_QB, MIPS_INS_SUBUH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBUH_R_QB, MIPS_INS_SUBUH_R,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBU_PH, MIPS_INS_SUBU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBU_QB, MIPS_INS_SUBU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBU_S_PH, MIPS_INS_SUBU_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBU_S_QB, MIPS_INS_SUBU_S,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBVI_B, MIPS_INS_SUBVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBVI_D, MIPS_INS_SUBVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBVI_H, MIPS_INS_SUBVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBVI_W, MIPS_INS_SUBVI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBV_B, MIPS_INS_SUBV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBV_D, MIPS_INS_SUBV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBV_H, MIPS_INS_SUBV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBV_W, MIPS_INS_SUBV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUB_MM, MIPS_INS_SUB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBu, MIPS_INS_SUBU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUBu_MM, MIPS_INS_SUBU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUXC1, MIPS_INS_SUXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUXC164, MIPS_INS_SUXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SUXC1_MM, MIPS_INS_SUXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SW, MIPS_INS_SW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SW16_MM, MIPS_INS_SW16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SW64, MIPS_INS_SW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SWC1, MIPS_INS_SWC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SWC1_MM, MIPS_INS_SWC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SWC2, MIPS_INS_SWC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SWC2_R6, MIPS_INS_SWC2,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SWC3, MIPS_INS_SWC3,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SWL, MIPS_INS_SWL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SWL64, MIPS_INS_SWL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SWL_MM, MIPS_INS_SWL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SWM16_MM, MIPS_INS_SWM16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SWM32_MM, MIPS_INS_SWM32,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SWP_MM, MIPS_INS_SWP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SWR, MIPS_INS_SWR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SWR64, MIPS_INS_SWR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SWR_MM, MIPS_INS_SWR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SWSP_MM, MIPS_INS_SW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SWXC1, MIPS_INS_SWXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SWXC1_MM, MIPS_INS_SWXC1,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SW_MM, MIPS_INS_SW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SYNC, MIPS_INS_SYNC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SYNCI, MIPS_INS_SYNCI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SYNC_MM, MIPS_INS_SYNC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SYSCALL, MIPS_INS_SYSCALL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_INT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SYSCALL_MM, MIPS_INS_SYSCALL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_INT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SbRxRyOffMemX16, MIPS_INS_SB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SebRx16, MIPS_INS_SEB,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SehRx16, MIPS_INS_SEH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_ShRxRyOffMemX16, MIPS_INS_SH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SllX16, MIPS_INS_SLL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SllvRxRy16, MIPS_INS_SLLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SltRxRy16, MIPS_INS_SLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SltiRxImm16, MIPS_INS_SLTI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SltiRxImmX16, MIPS_INS_SLTI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SltiuRxImm16, MIPS_INS_SLTIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SltiuRxImmX16, MIPS_INS_SLTIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SltuRxRy16, MIPS_INS_SLTU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SraX16, MIPS_INS_SRA,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SravRxRy16, MIPS_INS_SRAV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SrlX16, MIPS_INS_SRL,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SrlvRxRy16, MIPS_INS_SRLV,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SubuRxRyRz16, MIPS_INS_SUBU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SwRxRyOffMemX16, MIPS_INS_SW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_SwRxSpImmX16, MIPS_INS_SW,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TEQ, MIPS_INS_TEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TEQI, MIPS_INS_TEQI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TEQI_MM, MIPS_INS_TEQI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TEQ_MM, MIPS_INS_TEQ,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TGE, MIPS_INS_TGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TGEI, MIPS_INS_TGEI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TGEIU, MIPS_INS_TGEIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TGEIU_MM, MIPS_INS_TGEIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TGEI_MM, MIPS_INS_TGEI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TGEU, MIPS_INS_TGEU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TGEU_MM, MIPS_INS_TGEU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TGE_MM, MIPS_INS_TGE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TLBP, MIPS_INS_TLBP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TLBP_MM, MIPS_INS_TLBP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TLBR, MIPS_INS_TLBR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TLBR_MM, MIPS_INS_TLBR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TLBWI, MIPS_INS_TLBWI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TLBWI_MM, MIPS_INS_TLBWI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TLBWR, MIPS_INS_TLBWR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TLBWR_MM, MIPS_INS_TLBWR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TLT, MIPS_INS_TLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TLTI, MIPS_INS_TLTI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TLTIU_MM, MIPS_INS_TLTIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TLTI_MM, MIPS_INS_TLTI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TLTU, MIPS_INS_TLTU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TLTU_MM, MIPS_INS_TLTU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TLT_MM, MIPS_INS_TLT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TNE, MIPS_INS_TNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TNEI, MIPS_INS_TNEI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TNEI_MM, MIPS_INS_TNEI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TNE_MM, MIPS_INS_TNE,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TRUNC_L_D64, MIPS_INS_TRUNC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TRUNC_L_S, MIPS_INS_TRUNC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TRUNC_W_D32, MIPS_INS_TRUNC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TRUNC_W_D64, MIPS_INS_TRUNC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TRUNC_W_MM, MIPS_INS_TRUNC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TRUNC_W_S, MIPS_INS_TRUNC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TRUNC_W_S_MM, MIPS_INS_TRUNC,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_TTLTIU, MIPS_INS_TLTIU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_UDIV, MIPS_INS_DIVU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
+#endif
+},
+{
+ Mips_UDIV_MM, MIPS_INS_DIVU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_V3MULU, MIPS_INS_V3MULU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_VMM0, MIPS_INS_VMM0,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_MPL0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_VMULU, MIPS_INS_VMULU,
+#ifndef CAPSTONE_DIET
+ { 0 }, { MIPS_REG_MPL1, MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_VSHF_B, MIPS_INS_VSHF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_VSHF_D, MIPS_INS_VSHF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_VSHF_H, MIPS_INS_VSHF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_VSHF_W, MIPS_INS_VSHF,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_WAIT, MIPS_INS_WAIT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_WAIT_MM, MIPS_INS_WAIT,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_WRDSP, MIPS_INS_WRDSP,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
+#endif
+},
+{
+ Mips_WSBH, MIPS_INS_WSBH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
+#endif
+},
+{
+ Mips_WSBH_MM, MIPS_INS_WSBH,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_XOR, MIPS_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_XOR16_MM, MIPS_INS_XOR16,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_XOR64, MIPS_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_XORI_B, MIPS_INS_XORI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_XOR_MM, MIPS_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_XOR_V, MIPS_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
+#endif
+},
+{
+ Mips_XORi, MIPS_INS_XORI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_XORi64, MIPS_INS_XORI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
+#endif
+},
+{
+ Mips_XORi_MM, MIPS_INS_XORI,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
+#endif
+},
+{
+ Mips_XorRxRxRy16, MIPS_INS_XOR,
+#ifndef CAPSTONE_DIET
+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
+#endif
+},
diff --git a/capstone/arch/Mips/MipsModule.c b/capstone/arch/Mips/MipsModule.c
new file mode 100644
index 000000000..e06871d3b
--- /dev/null
+++ b/capstone/arch/Mips/MipsModule.c
@@ -0,0 +1,52 @@
+/* Capstone Disassembly Engine */
+/* By Dang Hoang Vu <danghvu@gmail.com> 2013 */
+
+#ifdef CAPSTONE_HAS_MIPS
+
+#include "../../utils.h"
+#include "../../MCRegisterInfo.h"
+#include "MipsDisassembler.h"
+#include "MipsInstPrinter.h"
+#include "MipsMapping.h"
+#include "MipsModule.h"
+
+// Returns mode value with implied bits set
+static cs_mode updated_mode(cs_mode mode)
+{
+ if (mode & CS_MODE_MIPS32R6) {
+ mode |= CS_MODE_32;
+ }
+
+ return mode;
+}
+
+cs_err Mips_global_init(cs_struct *ud)
+{
+ MCRegisterInfo *mri;
+ mri = cs_mem_malloc(sizeof(*mri));
+
+ Mips_init(mri);
+ ud->printer = Mips_printInst;
+ ud->printer_info = mri;
+ ud->getinsn_info = mri;
+ ud->reg_name = Mips_reg_name;
+ ud->insn_id = Mips_get_insn_id;
+ ud->insn_name = Mips_insn_name;
+ ud->group_name = Mips_group_name;
+
+ ud->disasm = Mips_getInstruction;
+
+ return CS_ERR_OK;
+}
+
+cs_err Mips_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+ if (type == CS_OPT_MODE) {
+ handle->mode = updated_mode(value);
+ return CS_ERR_OK;
+ }
+
+ return CS_ERR_OPTION;
+}
+
+#endif
diff --git a/capstone/arch/Mips/MipsModule.h b/capstone/arch/Mips/MipsModule.h
new file mode 100644
index 000000000..d1aa2cfff
--- /dev/null
+++ b/capstone/arch/Mips/MipsModule.h
@@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
+
+#ifndef CS_MIPS_MODULE_H
+#define CS_MIPS_MODULE_H
+
+#include "../../utils.h"
+
+cs_err Mips_global_init(cs_struct *ud);
+cs_err Mips_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif