Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

12 files changed, 5848 insertions, 0 deletions

diff --git a/capstone/arch/TMS320C64x/TMS320C64xDisassembler.c b/capstone/arch/TMS320C64x/TMS320C64xDisassembler.c
new file mode 100644
index 000000000..282918783
--- /dev/null
+++ b/capstone/arch/TMS320C64x/TMS320C64xDisassembler.c
@@ -0,0 +1,628 @@
+/* Capstone Disassembly Engine */
+/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
+
+#ifdef CAPSTONE_HAS_TMS320C64X
+
+#include <string.h>
+
+#include "../../cs_priv.h"
+#include "../../utils.h"
+
+#include "TMS320C64xDisassembler.h"
+
+#include "../../MCInst.h"
+#include "../../MCInstrDesc.h"
+#include "../../MCFixedLenDisassembler.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCDisassembler.h"
+#include "../../MathExtras.h"
+
+static uint64_t getFeatureBits(int mode);
+
+static DecodeStatus DecodeGPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeControlRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeScst5(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeScst16(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodePCRelScst7(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodePCRelScst10(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodePCRelScst12(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodePCRelScst21(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeMemOperand(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeMemOperandSc(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeMemOperand2(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeRegPair5(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeRegPair4(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeCondRegister(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeCondRegisterZero(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeSide(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeParallel(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeCrosspathX1(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeCrosspathX2(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeCrosspathX3(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+static DecodeStatus DecodeNop(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder);
+
+#include "TMS320C64xGenDisassemblerTables.inc"
+
+#define GET_REGINFO_ENUM
+#define GET_REGINFO_MC_DESC
+#include "TMS320C64xGenRegisterInfo.inc"
+
+static const unsigned GPRegsDecoderTable[] = {
+	TMS320C64x_A0,  TMS320C64x_A1,  TMS320C64x_A2,  TMS320C64x_A3,
+	TMS320C64x_A4,  TMS320C64x_A5,  TMS320C64x_A6,  TMS320C64x_A7,
+	TMS320C64x_A8,  TMS320C64x_A9,  TMS320C64x_A10, TMS320C64x_A11,
+	TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15,
+	TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19,
+	TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23,
+	TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27,
+	TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31
+};
+
+static const unsigned ControlRegsDecoderTable[] = {
+	TMS320C64x_AMR,    TMS320C64x_CSR,  TMS320C64x_ISR,   TMS320C64x_ICR,
+	TMS320C64x_IER,    TMS320C64x_ISTP, TMS320C64x_IRP,   TMS320C64x_NRP,
+	~0U,               ~0U,             TMS320C64x_TSCL,  TMS320C64x_TSCH,
+	~0U,               TMS320C64x_ILC,  TMS320C64x_RILC,  TMS320C64x_REP,
+	TMS320C64x_PCE1,   TMS320C64x_DNUM, ~0U,              ~0U,
+	~0U,               TMS320C64x_SSR,  TMS320C64x_GPLYA, TMS320C64x_GPLYB,
+	TMS320C64x_GFPGFR, TMS320C64x_DIER, TMS320C64x_TSR,   TMS320C64x_ITSR,
+	TMS320C64x_NTSR,   TMS320C64x_ECR,  ~0U,              TMS320C64x_IERR
+};
+
+static uint64_t getFeatureBits(int mode)
+{
+	// support everything
+	return (uint64_t)-1;
+}
+
+static unsigned getReg(const unsigned *RegTable, unsigned RegNo)
+{
+	if(RegNo > 31)
+		return ~0U;
+	return RegTable[RegNo];
+}
+
+static DecodeStatus DecodeGPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, void *Decoder)
+{
+	unsigned Reg;
+
+	if(RegNo > 31)
+		return MCDisassembler_Fail;
+
+	Reg = getReg(GPRegsDecoderTable, RegNo);
+	if(Reg == ~0U)
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, Reg);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeControlRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, void *Decoder)
+{
+	unsigned Reg;
+
+	if(RegNo > 31)
+		return MCDisassembler_Fail;
+
+	Reg = getReg(ControlRegsDecoderTable, RegNo);
+	if(Reg == ~0U)
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, Reg);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeScst5(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	int32_t imm;
+
+	imm = Val;
+	/* Sign extend 5 bit value */
+	if(imm & (1 << (5 - 1)))
+		imm |= ~((1 << 5) - 1);
+
+	MCOperand_CreateImm0(Inst, imm);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeScst16(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	int32_t imm;
+
+	imm = Val;
+	/* Sign extend 16 bit value */
+	if(imm & (1 << (16 - 1)))
+		imm |= ~((1 << 16) - 1);
+
+	MCOperand_CreateImm0(Inst, imm);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodePCRelScst7(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	int32_t imm;
+
+	imm = Val;
+	/* Sign extend 7 bit value */
+	if(imm & (1 << (7 - 1)))
+		imm |= ~((1 << 7) - 1);
+
+	/* Address is relative to the address of the first instruction in the fetch packet */
+	MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodePCRelScst10(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	int32_t imm;
+
+	imm = Val;
+	/* Sign extend 10 bit value */
+	if(imm & (1 << (10 - 1)))
+		imm |= ~((1 << 10) - 1);
+
+	/* Address is relative to the address of the first instruction in the fetch packet */
+	MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodePCRelScst12(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	int32_t imm;
+
+	imm = Val;
+	/* Sign extend 12 bit value */
+	if(imm & (1 << (12 - 1)))
+		imm |= ~((1 << 12) - 1);
+
+	/* Address is relative to the address of the first instruction in the fetch packet */
+	MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodePCRelScst21(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	int32_t imm;
+
+	imm = Val;
+	/* Sign extend 21 bit value */
+	if(imm & (1 << (21 - 1)))
+		imm |= ~((1 << 21) - 1);
+
+	/* Address is relative to the address of the first instruction in the fetch packet */
+	MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeMemOperand(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	return DecodeMemOperandSc(Inst, Val | (1 << 15), Address, Decoder);
+}
+
+static DecodeStatus DecodeMemOperandSc(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	uint8_t scaled, base, offset, mode, unit;
+	unsigned basereg, offsetreg;
+
+	scaled = (Val >> 15) & 1;
+	base = (Val >> 10) & 0x1f;
+	offset = (Val >> 5) & 0x1f;
+	mode = (Val >> 1) & 0xf;
+	unit = Val & 1;
+
+	if((base >= TMS320C64X_REG_A0) && (base <= TMS320C64X_REG_A31))
+		base = (base - TMS320C64X_REG_A0 + TMS320C64X_REG_B0);
+	else if((base >= TMS320C64X_REG_B0) && (base <= TMS320C64X_REG_B31))
+		base = (base - TMS320C64X_REG_B0 + TMS320C64X_REG_A0);
+	basereg = getReg(GPRegsDecoderTable, base);
+	if (basereg ==  ~0U)
+		return MCDisassembler_Fail;
+
+	switch(mode) {
+		case 0:
+		case 1:
+		case 8:
+		case 9:
+		case 10:
+		case 11:
+			MCOperand_CreateImm0(Inst, (scaled << 19) | (basereg << 12) | (offset << 5) | (mode << 1) | unit);
+			break;
+		case 4:
+		case 5:
+		case 12:
+		case 13:
+		case 14:
+		case 15:
+			if((offset >= TMS320C64X_REG_A0) && (offset <= TMS320C64X_REG_A31))
+				offset = (offset - TMS320C64X_REG_A0 + TMS320C64X_REG_B0);
+			else if((offset >= TMS320C64X_REG_B0) && (offset <= TMS320C64X_REG_B31))
+				offset = (offset - TMS320C64X_REG_B0 + TMS320C64X_REG_A0);
+			offsetreg = getReg(GPRegsDecoderTable, offset);
+			if (offsetreg ==  ~0U)
+				return MCDisassembler_Fail;
+			MCOperand_CreateImm0(Inst, (scaled << 19) | (basereg << 12) | (offsetreg << 5) | (mode << 1) | unit);
+			break;
+		default:
+			return MCDisassembler_Fail;
+	}
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeMemOperand2(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	uint16_t offset;
+	unsigned basereg;
+
+	if(Val & 1)
+		basereg = TMS320C64X_REG_B15;
+	else
+		basereg = TMS320C64X_REG_B14;
+
+	offset = (Val >> 1) & 0x7fff;
+	MCOperand_CreateImm0(Inst, (offset << 7) | basereg);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRegPair5(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, void *Decoder)
+{
+	unsigned Reg;
+
+	if(RegNo > 31)
+		return MCDisassembler_Fail;
+
+	Reg = getReg(GPRegsDecoderTable, RegNo);
+	MCOperand_CreateReg0(Inst, Reg);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRegPair4(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, void *Decoder)
+{
+	unsigned Reg;
+
+	if(RegNo > 15)
+		return MCDisassembler_Fail;
+
+	Reg = getReg(GPRegsDecoderTable, RegNo << 1);
+	MCOperand_CreateReg0(Inst, Reg);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeCondRegister(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	DecodeStatus ret = MCDisassembler_Success;
+
+	if(!Inst->flat_insn->detail)
+		return MCDisassembler_Success;
+
+	switch(Val) {
+		case 0:
+		case 7:
+			Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_INVALID;
+			break;
+		case 1:
+			Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_B0;
+			break;
+		case 2:
+			Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_B1;
+			break;
+		case 3:
+			Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_B2;
+			break;
+		case 4:
+			Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_A1;
+			break;
+		case 5:
+			Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_A2;
+			break;
+		case 6:
+			Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_A0;
+			break;
+		default:
+			Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_INVALID;
+			ret = MCDisassembler_Fail;
+			break;
+	}
+
+	return ret;
+}
+
+static DecodeStatus DecodeCondRegisterZero(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	DecodeStatus ret = MCDisassembler_Success;
+
+	if(!Inst->flat_insn->detail)
+		return MCDisassembler_Success;
+
+	switch(Val) {
+		case 0:
+			Inst->flat_insn->detail->tms320c64x.condition.zero = 0;
+			break;
+		case 1:
+			Inst->flat_insn->detail->tms320c64x.condition.zero = 1;
+			break;
+		default:
+			Inst->flat_insn->detail->tms320c64x.condition.zero = 0;
+			ret = MCDisassembler_Fail;
+			break;
+	}
+
+	return ret;
+}
+
+static DecodeStatus DecodeSide(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	DecodeStatus ret = MCDisassembler_Success;
+	MCOperand *op;
+	int i;
+
+	/* This is pretty messy, probably we should find a better way */
+	if(Val == 1) {
+		for(i = 0; i < Inst->size; i++) {
+			op = &Inst->Operands[i];
+			if(op->Kind == kRegister) {
+				if((op->RegVal >= TMS320C64X_REG_A0) && (op->RegVal <= TMS320C64X_REG_A31))
+					op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + TMS320C64X_REG_B0);
+				else if((op->RegVal >= TMS320C64X_REG_B0) && (op->RegVal <= TMS320C64X_REG_B31))
+					op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + TMS320C64X_REG_A0);
+			}
+		}
+	}
+
+	if(!Inst->flat_insn->detail)
+		return MCDisassembler_Success;
+
+	switch(Val) {
+		case 0:
+			Inst->flat_insn->detail->tms320c64x.funit.side = 1;
+			break;
+		case 1:
+			Inst->flat_insn->detail->tms320c64x.funit.side = 2;
+			break;
+		default:
+			Inst->flat_insn->detail->tms320c64x.funit.side = 0;
+			ret = MCDisassembler_Fail;
+			break;
+	}
+
+	return ret;
+}
+
+static DecodeStatus DecodeParallel(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	DecodeStatus ret = MCDisassembler_Success;
+
+	if(!Inst->flat_insn->detail)
+		return MCDisassembler_Success;
+
+	switch(Val) {
+		case 0:
+			Inst->flat_insn->detail->tms320c64x.parallel = 0;
+			break;
+		case 1:
+			Inst->flat_insn->detail->tms320c64x.parallel = 1;
+			break;
+		default:
+			Inst->flat_insn->detail->tms320c64x.parallel = -1;
+			ret = MCDisassembler_Fail;
+			break;
+	}
+
+	return ret;
+}
+
+static DecodeStatus DecodeCrosspathX1(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	DecodeStatus ret = MCDisassembler_Success;
+	MCOperand *op;
+
+	if(!Inst->flat_insn->detail)
+		return MCDisassembler_Success;
+
+	switch(Val) {
+		case 0:
+			Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0;
+			break;
+		case 1:
+			Inst->flat_insn->detail->tms320c64x.funit.crosspath = 1;
+			op = &Inst->Operands[0];
+			if(op->Kind == kRegister) {
+				if((op->RegVal >= TMS320C64X_REG_A0) && (op->RegVal <= TMS320C64X_REG_A31))
+					op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + TMS320C64X_REG_B0);
+				else if((op->RegVal >= TMS320C64X_REG_B0) && (op->RegVal <= TMS320C64X_REG_B31))
+					op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + TMS320C64X_REG_A0);
+			}
+			break;
+		default:
+			Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1;
+			ret = MCDisassembler_Fail;
+			break;
+	}
+
+	return ret;
+}
+
+static DecodeStatus DecodeCrosspathX2(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	DecodeStatus ret = MCDisassembler_Success;
+	MCOperand *op;
+
+	if(!Inst->flat_insn->detail)
+		return MCDisassembler_Success;
+
+	switch(Val) {
+		case 0:
+			Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0;
+			break;
+		case 1:
+			Inst->flat_insn->detail->tms320c64x.funit.crosspath = 1;
+			op = &Inst->Operands[1];
+			if(op->Kind == kRegister) {
+				if((op->RegVal >= TMS320C64X_REG_A0) && (op->RegVal <= TMS320C64X_REG_A31))
+					op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + TMS320C64X_REG_B0);
+				else if((op->RegVal >= TMS320C64X_REG_B0) && (op->RegVal <= TMS320C64X_REG_B31))
+					op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + TMS320C64X_REG_A0);
+			}
+			break;
+		default:
+			Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1;
+			ret = MCDisassembler_Fail;
+			break;
+	}
+
+	return ret;
+}
+
+static DecodeStatus DecodeCrosspathX3(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	DecodeStatus ret = MCDisassembler_Success;
+	MCOperand *op;
+
+	if(!Inst->flat_insn->detail)
+		return MCDisassembler_Success;
+
+	switch(Val) {
+		case 0:
+			Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0;
+			break;
+		case 1:
+			Inst->flat_insn->detail->tms320c64x.funit.crosspath = 2;
+			op = &Inst->Operands[2];
+			if(op->Kind == kRegister) {
+				if((op->RegVal >= TMS320C64X_REG_A0) && (op->RegVal <= TMS320C64X_REG_A31))
+					op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + TMS320C64X_REG_B0);
+				else if((op->RegVal >= TMS320C64X_REG_B0) && (op->RegVal <= TMS320C64X_REG_B31))
+					op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + TMS320C64X_REG_A0);
+			}
+			break;
+		default:
+			Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1;
+			ret = MCDisassembler_Fail;
+			break;
+	}
+
+	return ret;
+}
+
+
+static DecodeStatus DecodeNop(MCInst *Inst, unsigned Val,
+		uint64_t Address, void *Decoder)
+{
+	MCOperand_CreateImm0(Inst, Val + 1);
+
+	return MCDisassembler_Success;
+}
+
+#define GET_INSTRINFO_ENUM
+#include "TMS320C64xGenInstrInfo.inc"
+
+bool TMS320C64x_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+		MCInst *MI, uint16_t *size, uint64_t address, void *info)
+{
+	uint32_t insn;
+	DecodeStatus result;
+
+	if(code_len < 4) {
+		*size = 0;
+		return MCDisassembler_Fail;
+	}
+
+	if(MI->flat_insn->detail)
+		memset(MI->flat_insn->detail, 0, offsetof(cs_detail, tms320c64x)+sizeof(cs_tms320c64x));
+
+	insn = (code[3] << 0) | (code[2] << 8) | (code[1] << 16) | ((uint32_t) code[0] << 24);
+	result = decodeInstruction_4(DecoderTable32, MI, insn, address, info, 0);
+
+	if(result == MCDisassembler_Success) {
+		*size = 4;
+		return true;
+	}
+
+	MCInst_clear(MI);
+	*size = 0;
+	return false;
+}
+
+void TMS320C64x_init(MCRegisterInfo *MRI)
+{
+	MCRegisterInfo_InitMCRegisterInfo(MRI, TMS320C64xRegDesc, 90,
+			0, 0,
+			TMS320C64xMCRegisterClasses, 7,
+			0, 0,
+			TMS320C64xRegDiffLists,
+			0,
+			TMS320C64xSubRegIdxLists, 1,
+			0);
+}
+
+#endif
diff --git a/capstone/arch/TMS320C64x/TMS320C64xDisassembler.h b/capstone/arch/TMS320C64x/TMS320C64xDisassembler.h
new file mode 100644
index 000000000..d49d43b86
--- /dev/null
+++ b/capstone/arch/TMS320C64x/TMS320C64xDisassembler.h
@@ -0,0 +1,19 @@
+/* Capstone Disassembly Engine */
+/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
+
+#ifndef CS_TMS320C64XDISASSEMBLER_H
+#define CS_TMS320C64XDISASSEMBLER_H
+
+#include <stdint.h>
+
+#include "capstone/capstone.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCInst.h"
+
+void TMS320C64x_init(MCRegisterInfo *MRI);
+
+bool TMS320C64x_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+		MCInst *instr, uint16_t *size, uint64_t address, void *info);
+
+#endif
+
diff --git a/capstone/arch/TMS320C64x/TMS320C64xGenAsmWriter.inc b/capstone/arch/TMS320C64x/TMS320C64xGenAsmWriter.inc
new file mode 100644
index 000000000..a5242dae9
--- /dev/null
+++ b/capstone/arch/TMS320C64x/TMS320C64xGenAsmWriter.inc
@@ -0,0 +1,684 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*Assembly Writer Source Fragment                                             *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+#include <stdio.h>
+
+/// printInstruction - This method is automatically generated by tablegen
+/// from the instruction set description.
+static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) {
+  static const uint32_t OpInfo[] = {
+    0U,	// PHI
+    0U,	// INLINEASM
+    0U,	// CFI_INSTRUCTION
+    0U,	// EH_LABEL
+    0U,	// GC_LABEL
+    0U,	// KILL
+    0U,	// EXTRACT_SUBREG
+    0U,	// INSERT_SUBREG
+    0U,	// IMPLICIT_DEF
+    0U,	// SUBREG_TO_REG
+    0U,	// COPY_TO_REGCLASS
+    882U,	// DBG_VALUE
+    0U,	// REG_SEQUENCE
+    0U,	// COPY
+    875U,	// BUNDLE
+    904U,	// LIFETIME_START
+    862U,	// LIFETIME_END
+    0U,	// STACKMAP
+    0U,	// PATCHPOINT
+    0U,	// LOAD_STACK_GUARD
+    0U,	// STATEPOINT
+    0U,	// FRAME_ALLOC
+    1126U,	// ABS2_l2_rr
+    10847U,	// ABS_l1_pp
+    1631U,	// ABS_l1_rr
+    85006U,	// ADD2_d2_rrr
+    85006U,	// ADD2_l1_rrr_x2
+    85006U,	// ADD2_s1_rrr
+    85171U,	// ADD4_l1_rrr_x2
+    91479U,	// ADDAB_d1_rir
+    91479U,	// ADDAB_d1_rrr
+    91541U,	// ADDAD_d1_rir
+    91541U,	// ADDAD_d1_rrr
+    91577U,	// ADDAH_d1_rir
+    91577U,	// ADDAH_d1_rrr
+    91937U,	// ADDAW_d1_rir
+    91937U,	// ADDAW_d1_rrr
+    132488U,	// ADDKPC_s3_iir
+    1518U,	// ADDK_s2_ir
+    233140U,	// ADDU_l1_rpp
+    216756U,	// ADDU_l1_rrp_x2
+    91555U,	// ADD_d1_rir
+    91555U,	// ADD_d1_rrr
+    91555U,	// ADD_d2_rir
+    85411U,	// ADD_d2_rrr
+    232867U,	// ADD_l1_ipp
+    85411U,	// ADD_l1_irr
+    232867U,	// ADD_l1_rpp
+    216483U,	// ADD_l1_rrp_x2
+    85411U,	// ADD_l1_rrr_x2
+    85411U,	// ADD_s1_irr
+    85411U,	// ADD_s1_rrr
+    85542U,	// ANDN_d2_rrr
+    85542U,	// ANDN_l1_rrr_x2
+    85542U,	// ANDN_s4_rrr
+    85416U,	// AND_d2_rir
+    85416U,	// AND_d2_rrr
+    85416U,	// AND_l1_irr
+    85416U,	// AND_l1_rrr_x2
+    85416U,	// AND_s1_irr
+    85416U,	// AND_s1_rrr
+    85019U,	// AVG2_m1_rrr
+    85232U,	// AVGU4_m1_rrr
+    1410U,	// BDEC_s8_ir
+    1196U,	// BITC4_m2_rr
+    307756U,	// BNOP_s10_ri
+    307756U,	// BNOP_s9_ii
+    1654U,	// BPOS_s8_ir
+    53588U,	// B_s5_i
+    53588U,	// B_s6_r
+    892U,	// B_s7_irp
+    898U,	// B_s7_nrp
+    353870U,	// CLR_s15_riir
+    91726U,	// CLR_s1_rrr
+    85080U,	// CMPEQ2_s1_rrr
+    85207U,	// CMPEQ4_s1_rrr
+    101938U,	// CMPEQ_l1_ipr
+    85554U,	// CMPEQ_l1_irr
+    101938U,	// CMPEQ_l1_rpr
+    85554U,	// CMPEQ_l1_rrr_x2
+    85109U,	// CMPGT2_s1_rrr
+    85298U,	// CMPGTU4_s1_rrr
+    102037U,	// CMPGT_l1_ipr
+    85653U,	// CMPGT_l1_irr
+    102037U,	// CMPGT_l1_rpr
+    85653U,	// CMPGT_l1_rrr_x2
+    102150U,	// CMPLTU_l1_ipr
+    85766U,	// CMPLTU_l1_irr
+    102150U,	// CMPLTU_l1_rpr
+    85766U,	// CMPLTU_l1_rrr_x2
+    102044U,	// CMPLT_l1_ipr
+    85660U,	// CMPLT_l1_irr
+    102044U,	// CMPLT_l1_rpr
+    85660U,	// CMPLT_l1_rrr_x2
+    1529U,	// DEAL_m2_rr
+    216145U,	// DOTP2_m1_rrp
+    85073U,	// DOTP2_m1_rrr
+    85065U,	// DOTPN2_m1_rrr
+    85124U,	// DOTPNRSU2_m1_rrr
+    85135U,	// DOTPRSU2_m1_rrr
+    85281U,	// DOTPSU4_m1_rrr
+    85273U,	// DOTPU4_m1_rrr
+    354062U,	// EXTU_s15_riir
+    91918U,	// EXTU_s1_rrr
+    353955U,	// EXT_s15_riir
+    91811U,	// EXT_s1_rrr
+    102142U,	// GMPGTU_l1_ipr
+    85758U,	// GMPGTU_l1_irr
+    102142U,	// GMPGTU_l1_rpr
+    85758U,	// GMPGTU_l1_rrr_x2
+    85321U,	// GMPY4_m1_rrr
+    5800U,	// LDBU_d5_mr
+    6824U,	// LDBU_d6_mr
+    5470U,	// LDB_d5_mr
+    6494U,	// LDB_d6_mr
+    14120U,	// LDDW_d7_mp
+    5818U,	// LDHU_d5_mr
+    6842U,	// LDHU_d6_mr
+    5568U,	// LDH_d5_mr
+    6592U,	// LDH_d6_mr
+    14131U,	// LDNDW_d8_mp
+    5959U,	// LDNW_d5_mr
+    5934U,	// LDW_d5_mr
+    6958U,	// LDW_d6_mr
+    85404U,	// LMBD_l1_irr
+    85404U,	// LMBD_l1_rrr_x2
+    85145U,	// MAX2_l1_rrr_x2
+    85307U,	// MAXU4_l1_rrr_x2
+    85059U,	// MIN2_l1_rrr_x2
+    85266U,	// MINU4_l1_rrr_x2
+    216224U,	// MPY2_m1_rrp
+    85566U,	// MPYHIR_m1_rrr
+    216544U,	// MPYHI_m1_rrp
+    85720U,	// MPYHLU_m4_rrr
+    85516U,	// MPYHL_m4_rrr
+    85728U,	// MPYHSLU_m4_rrr
+    85743U,	// MPYHSU_m4_rrr
+    85613U,	// MPYHULS_m4_rrr
+    85628U,	// MPYHUS_m4_rrr
+    85713U,	// MPYHU_m4_rrr
+    85466U,	// MPYH_m4_rrr
+    85696U,	// MPYLHU_m4_rrr
+    85453U,	// MPYLH_m4_rrr
+    85574U,	// MPYLIR_m1_rrr
+    216551U,	// MPYLI_m1_rrp
+    85704U,	// MPYLSHU_m4_rrr
+    85604U,	// MPYLUHS_m4_rrr
+    216362U,	// MPYSU4_m1_rrp
+    85751U,	// MPYSU_m4_irr
+    85751U,	// MPYSU_m4_rrr
+    216386U,	// MPYU4_m1_rrp
+    85636U,	// MPYUS_m4_rrr
+    85780U,	// MPYU_m4_rrr
+    85849U,	// MPY_m4_irr
+    85849U,	// MPY_m4_rrr
+    1424U,	// MVC_s1_rr
+    1424U,	// MVC_s1_rr2
+    1453U,	// MVD_m2_rr
+    1477U,	// MVKLH_s12_ir
+    1524U,	// MVKL_s12_ir
+    1524U,	// MVK_d1_rr
+    1524U,	// MVK_l2_ir
+    53249U,	// NOP_n
+    2592U,	// NORM_l1_pr
+    1568U,	// NORM_l1_rr
+    85588U,	// OR_d2_rir
+    85588U,	// OR_d2_rrr
+    85588U,	// OR_l1_irr
+    85588U,	// OR_l1_rrr_x2
+    85588U,	// OR_s1_irr
+    85588U,	// OR_s1_rrr
+    85043U,	// PACK2_l1_rrr_x2
+    85043U,	// PACK2_s4_rrr
+    85025U,	// PACKH2_l1_rrr_x2
+    85025U,	// PACKH2_s1_rrr
+    85184U,	// PACKH4_l1_rrr_x2
+    85050U,	// PACKHL2_l1_rrr_x2
+    85050U,	// PACKHL2_s1_rrr
+    85192U,	// PACKL4_l1_rrr_x2
+    85033U,	// PACKLH2_l1_rrr_x2
+    85033U,	// PACKLH2_s1_rrr
+    91667U,	// ROTL_m1_rir
+    91667U,	// ROTL_m1_rrr
+    85005U,	// SADD2_s4_rrr
+    85224U,	// SADDU4_s4_rrr
+    85100U,	// SADDUS2_s4_rrr
+    232866U,	// SADD_l1_ipp
+    85410U,	// SADD_l1_irr
+    232866U,	// SADD_l1_rpp
+    85410U,	// SADD_l1_rrr_x2
+    85410U,	// SADD_s1_rrr
+    2699U,	// SAT_l1_pr
+    353936U,	// SET_s15_riir
+    91792U,	// SET_s1_rrr
+    1535U,	// SHFL_m2_rr
+    85347U,	// SHLMB_l1_rrr_x2
+    85347U,	// SHLMB_s4_rrr
+    223750U,	// SHL_s1_pip
+    223750U,	// SHL_s1_prp
+    222726U,	// SHL_s1_rip
+    91654U,	// SHL_s1_rir
+    222726U,	// SHL_s1_rrp
+    91654U,	// SHL_s1_rrr
+    91232U,	// SHR2_s1_rir
+    91232U,	// SHR2_s4_rrr
+    85354U,	// SHRMB_l1_rrr_x2
+    85354U,	// SHRMB_s4_rrr
+    91261U,	// SHRU2_s1_rir
+    91261U,	// SHRU2_s4_rrr
+    223977U,	// SHRU_s1_pip
+    223977U,	// SHRU_s1_prp
+    91881U,	// SHRU_s1_rir
+    91881U,	// SHRU_s1_rrr
+    223801U,	// SHR_s1_pip
+    223801U,	// SHR_s1_prp
+    91705U,	// SHR_s1_rir
+    91705U,	// SHR_s1_rrr
+    216223U,	// SMPY2_m1_rrp
+    85515U,	// SMPYHL_m4_rrr
+    85465U,	// SMPYH_m4_rrr
+    85452U,	// SMPYLH_m4_rrr
+    85848U,	// SMPY_m4_rrr
+    85042U,	// SPACK2_s4_rrr
+    85248U,	// SPACKU4_s4_rrr
+    91653U,	// SSHL_s1_rir
+    91653U,	// SSHL_s1_rrr
+    85529U,	// SSHVL_m1_rrr
+    85592U,	// SSHVR_m1_rrr
+    232822U,	// SSUB_l1_ipp
+    85366U,	// SSUB_l1_irr
+    85366U,	// SSUB_l1_rrr_x1
+    85366U,	// SSUB_l1_rrr_x2
+    438641U,	// STB_d5_rm
+    504177U,	// STB_d6_rm
+    8001U,	// STDW_d7_pm
+    438740U,	// STH_d5_rm
+    504276U,	// STH_d6_rm
+    7994U,	// STNDW_d8_pm
+    439117U,	// STNW_d5_rm
+    439123U,	// STW_d5_rm
+    504659U,	// STW_d6_rm
+    84999U,	// SUB2_d2_rrr
+    84999U,	// SUB2_l1_rrr_x2
+    84999U,	// SUB2_s1_rrr
+    85158U,	// SUB4_l1_rrr_x2
+    85215U,	// SUBABS4_l1_rrr_x2
+    91472U,	// SUBAB_d1_rir
+    91472U,	// SUBAB_d1_rrr
+    91472U,	// SUBAH_d1_rir
+    91570U,	// SUBAH_d1_rrr
+    91472U,	// SUBAW_d1_rir
+    91930U,	// SUBAW_d1_rrr
+    85372U,	// SUBC_l1_rrr_x2
+    216750U,	// SUBU_l1_rrp_x1
+    216750U,	// SUBU_l1_rrp_x2
+    91511U,	// SUB_d1_rir
+    91511U,	// SUB_d1_rrr
+    85367U,	// SUB_d2_rrr
+    232823U,	// SUB_l1_ipp
+    85367U,	// SUB_l1_irr
+    216439U,	// SUB_l1_rrp_x1
+    216439U,	// SUB_l1_rrp_x2
+    85367U,	// SUB_l1_rrr_x1
+    85367U,	// SUB_l1_rrr_x2
+    85367U,	// SUB_s1_irr
+    85367U,	// SUB_s1_rrr
+    91511U,	// SUB_s4_rrr
+    1232U,	// SWAP4_l2_rr
+    1271U,	// UNPKHU4_l2_rr
+    1271U,	// UNPKHU4_s14_rr
+    1289U,	// UNPKLU4_l2_rr
+    1289U,	// UNPKLU4_s14_rr
+    85587U,	// XOR_d2_rir
+    85587U,	// XOR_d2_rrr
+    85587U,	// XOR_l1_irr
+    85587U,	// XOR_l1_rrr_x2
+    85587U,	// XOR_s1_irr
+    85587U,	// XOR_s1_rrr
+    1044U,	// XPND2_m2_rr
+    1209U,	// XPND4_m2_rr
+    0U
+  };
+
+  static const char AsmStrs[] = {
+  /* 0 */ 'n', 'o', 'p', 9, 9, 0,
+  /* 6 */ 's', 'u', 'b', '2', 9, 0,
+  /* 12 */ 's', 'a', 'd', 'd', '2', 9, 0,
+  /* 19 */ 'x', 'p', 'n', 'd', '2', 9, 0,
+  /* 26 */ 'a', 'v', 'g', '2', 9, 0,
+  /* 32 */ 'p', 'a', 'c', 'k', 'h', '2', 9, 0,
+  /* 40 */ 'p', 'a', 'c', 'k', 'l', 'h', '2', 9, 0,
+  /* 49 */ 's', 'p', 'a', 'c', 'k', '2', 9, 0,
+  /* 57 */ 'p', 'a', 'c', 'k', 'h', 'l', '2', 9, 0,
+  /* 66 */ 'm', 'i', 'n', '2', 9, 0,
+  /* 72 */ 'd', 'o', 't', 'p', 'n', '2', 9, 0,
+  /* 80 */ 'd', 'o', 't', 'p', '2', 9, 0,
+  /* 87 */ 'c', 'm', 'p', 'e', 'q', '2', 9, 0,
+  /* 95 */ 's', 'h', 'r', '2', 9, 0,
+  /* 101 */ 'a', 'b', 's', '2', 9, 0,
+  /* 107 */ 's', 'a', 'd', 'd', 'u', 's', '2', 9, 0,
+  /* 116 */ 'c', 'm', 'p', 'g', 't', '2', 9, 0,
+  /* 124 */ 's', 'h', 'r', 'u', '2', 9, 0,
+  /* 131 */ 'd', 'o', 't', 'p', 'n', 'r', 's', 'u', '2', 9, 0,
+  /* 142 */ 'd', 'o', 't', 'p', 'r', 's', 'u', '2', 9, 0,
+  /* 152 */ 'm', 'a', 'x', '2', 9, 0,
+  /* 158 */ 's', 'm', 'p', 'y', '2', 9, 0,
+  /* 165 */ 's', 'u', 'b', '4', 9, 0,
+  /* 171 */ 'b', 'i', 't', 'c', '4', 9, 0,
+  /* 178 */ 'a', 'd', 'd', '4', 9, 0,
+  /* 184 */ 'x', 'p', 'n', 'd', '4', 9, 0,
+  /* 191 */ 'p', 'a', 'c', 'k', 'h', '4', 9, 0,
+  /* 199 */ 'p', 'a', 'c', 'k', 'l', '4', 9, 0,
+  /* 207 */ 's', 'w', 'a', 'p', '4', 9, 0,
+  /* 214 */ 'c', 'm', 'p', 'e', 'q', '4', 9, 0,
+  /* 222 */ 's', 'u', 'b', 'a', 'b', 's', '4', 9, 0,
+  /* 231 */ 's', 'a', 'd', 'd', 'u', '4', 9, 0,
+  /* 239 */ 'a', 'v', 'g', 'u', '4', 9, 0,
+  /* 246 */ 'u', 'n', 'p', 'k', 'h', 'u', '4', 9, 0,
+  /* 255 */ 's', 'p', 'a', 'c', 'k', 'u', '4', 9, 0,
+  /* 264 */ 'u', 'n', 'p', 'k', 'l', 'u', '4', 9, 0,
+  /* 273 */ 'm', 'i', 'n', 'u', '4', 9, 0,
+  /* 280 */ 'd', 'o', 't', 'p', 'u', '4', 9, 0,
+  /* 288 */ 'd', 'o', 't', 'p', 's', 'u', '4', 9, 0,
+  /* 297 */ 'm', 'p', 'y', 's', 'u', '4', 9, 0,
+  /* 305 */ 'c', 'm', 'p', 'g', 't', 'u', '4', 9, 0,
+  /* 314 */ 'm', 'a', 'x', 'u', '4', 9, 0,
+  /* 321 */ 'm', 'p', 'y', 'u', '4', 9, 0,
+  /* 328 */ 'g', 'm', 'p', 'y', '4', 9, 0,
+  /* 335 */ 's', 'u', 'b', 'a', 'b', 9, 0,
+  /* 342 */ 'a', 'd', 'd', 'a', 'b', 9, 0,
+  /* 349 */ 'l', 'd', 'b', 9, 0,
+  /* 354 */ 's', 'h', 'l', 'm', 'b', 9, 0,
+  /* 361 */ 's', 'h', 'r', 'm', 'b', 9, 0,
+  /* 368 */ 's', 't', 'b', 9, 0,
+  /* 373 */ 's', 's', 'u', 'b', 9, 0,
+  /* 379 */ 's', 'u', 'b', 'c', 9, 0,
+  /* 385 */ 'b', 'd', 'e', 'c', 9, 0,
+  /* 391 */ 'a', 'd', 'd', 'k', 'p', 'c', 9, 0,
+  /* 399 */ 'm', 'v', 'c', 9, 0,
+  /* 404 */ 'a', 'd', 'd', 'a', 'd', 9, 0,
+  /* 411 */ 'l', 'm', 'b', 'd', 9, 0,
+  /* 417 */ 's', 'a', 'd', 'd', 9, 0,
+  /* 423 */ 'a', 'n', 'd', 9, 0,
+  /* 428 */ 'm', 'v', 'd', 9, 0,
+  /* 433 */ 's', 'u', 'b', 'a', 'h', 9, 0,
+  /* 440 */ 'a', 'd', 'd', 'a', 'h', 9, 0,
+  /* 447 */ 'l', 'd', 'h', 9, 0,
+  /* 452 */ 'm', 'v', 'k', 'l', 'h', 9, 0,
+  /* 459 */ 's', 'm', 'p', 'y', 'l', 'h', 9, 0,
+  /* 467 */ 's', 't', 'h', 9, 0,
+  /* 472 */ 's', 'm', 'p', 'y', 'h', 9, 0,
+  /* 479 */ 'm', 'p', 'y', 'h', 'i', 9, 0,
+  /* 486 */ 'm', 'p', 'y', 'l', 'i', 9, 0,
+  /* 493 */ 'a', 'd', 'd', 'k', 9, 0,
+  /* 499 */ 'm', 'v', 'k', 9, 0,
+  /* 504 */ 'd', 'e', 'a', 'l', 9, 0,
+  /* 510 */ 's', 'h', 'f', 'l', 9, 0,
+  /* 516 */ 's', 's', 'h', 'l', 9, 0,
+  /* 522 */ 's', 'm', 'p', 'y', 'h', 'l', 9, 0,
+  /* 530 */ 'r', 'o', 't', 'l', 9, 0,
+  /* 536 */ 's', 's', 'h', 'v', 'l', 9, 0,
+  /* 543 */ 'n', 'o', 'r', 'm', 9, 0,
+  /* 549 */ 'a', 'n', 'd', 'n', 9, 0,
+  /* 555 */ 'b', 'n', 'o', 'p', 9, 0,
+  /* 561 */ 'c', 'm', 'p', 'e', 'q', 9, 0,
+  /* 568 */ 's', 'h', 'r', 9, 0,
+  /* 573 */ 'm', 'p', 'y', 'h', 'i', 'r', 9, 0,
+  /* 581 */ 'm', 'p', 'y', 'l', 'i', 'r', 9, 0,
+  /* 589 */ 'c', 'l', 'r', 9, 0,
+  /* 594 */ 'x', 'o', 'r', 9, 0,
+  /* 599 */ 's', 's', 'h', 'v', 'r', 9, 0,
+  /* 606 */ 'a', 'b', 's', 9, 0,
+  /* 611 */ 'm', 'p', 'y', 'l', 'u', 'h', 's', 9, 0,
+  /* 620 */ 'm', 'p', 'y', 'h', 'u', 'l', 's', 9, 0,
+  /* 629 */ 'b', 'p', 'o', 's', 9, 0,
+  /* 635 */ 'm', 'p', 'y', 'h', 'u', 's', 9, 0,
+  /* 643 */ 'm', 'p', 'y', 'u', 's', 9, 0,
+  /* 650 */ 's', 'a', 't', 9, 0,
+  /* 655 */ 's', 'e', 't', 9, 0,
+  /* 660 */ 'c', 'm', 'p', 'g', 't', 9, 0,
+  /* 667 */ 'c', 'm', 'p', 'l', 't', 9, 0,
+  /* 674 */ 'e', 'x', 't', 9, 0,
+  /* 679 */ 'l', 'd', 'b', 'u', 9, 0,
+  /* 685 */ 's', 'u', 'b', 'u', 9, 0,
+  /* 691 */ 'a', 'd', 'd', 'u', 9, 0,
+  /* 697 */ 'l', 'd', 'h', 'u', 9, 0,
+  /* 703 */ 'm', 'p', 'y', 'l', 'h', 'u', 9, 0,
+  /* 711 */ 'm', 'p', 'y', 'l', 's', 'h', 'u', 9, 0,
+  /* 720 */ 'm', 'p', 'y', 'h', 'u', 9, 0,
+  /* 727 */ 'm', 'p', 'y', 'h', 'l', 'u', 9, 0,
+  /* 735 */ 'm', 'p', 'y', 'h', 's', 'l', 'u', 9, 0,
+  /* 744 */ 's', 'h', 'r', 'u', 9, 0,
+  /* 750 */ 'm', 'p', 'y', 'h', 's', 'u', 9, 0,
+  /* 758 */ 'm', 'p', 'y', 's', 'u', 9, 0,
+  /* 765 */ 'c', 'm', 'p', 'g', 't', 'u', 9, 0,
+  /* 773 */ 'c', 'm', 'p', 'l', 't', 'u', 9, 0,
+  /* 781 */ 'e', 'x', 't', 'u', 9, 0,
+  /* 787 */ 'm', 'p', 'y', 'u', 9, 0,
+  /* 793 */ 's', 'u', 'b', 'a', 'w', 9, 0,
+  /* 800 */ 'a', 'd', 'd', 'a', 'w', 9, 0,
+  /* 807 */ 'l', 'd', 'd', 'w', 9, 0,
+  /* 813 */ 'l', 'd', 'w', 9, 0,
+  /* 818 */ 'l', 'd', 'n', 'd', 'w', 9, 0,
+  /* 825 */ 's', 't', 'n', 'd', 'w', 9, 0,
+  /* 832 */ 's', 't', 'd', 'w', 9, 0,
+  /* 838 */ 'l', 'd', 'n', 'w', 9, 0,
+  /* 844 */ 's', 't', 'n', 'w', 9, 0,
+  /* 850 */ 's', 't', 'w', 9, 0,
+  /* 855 */ 's', 'm', 'p', 'y', 9, 0,
+  /* 861 */ 'l', 'i', 'f', 'e', 't', 'i', 'm', 'e', '_', 'e', 'n', 'd', 0,
+  /* 874 */ 'b', 'u', 'n', 'd', 'l', 'e', 0,
+  /* 881 */ 'd', 'b', 'g', '_', 'v', 'a', 'l', 'u', 'e', 0,
+  /* 891 */ 'b', 9, 'i', 'r', 'p', 0,
+  /* 897 */ 'b', 9, 'n', 'r', 'p', 0,
+  /* 903 */ 'l', 'i', 'f', 'e', 't', 'i', 'm', 'e', '_', 's', 't', 'a', 'r', 't', 0,
+  };
+
+  // Emit the opcode for the instruction.
+  uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
+  // assert(Bits != 0 && "Cannot print this instruction.");
+#ifndef CAPSTONE_DIET
+  SStream_concat0(O, AsmStrs+(Bits & 1023)-1);
+#endif
+
+
+  // Fragment 0 encoded into 3 bits for 8 unique commands.
+  switch ((Bits >> 10) & 7) {
+  default:
+  case 0:
+    // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, B_s7_irp, B_s7_nrp
+    return;
+    break;
+  case 1:
+    // ABS2_l2_rr, ABS_l1_rr, ADDAB_d1_rir, ADDAB_d1_rrr, ADDAD_d1_rir, ADDAD...
+    printOperand(MI, 1, O); 
+    SStream_concat0(O, ", ");
+    break;
+  case 2:
+    // ABS_l1_pp, NORM_l1_pr, SAT_l1_pr, SHL_s1_pip, SHL_s1_prp, SHRU_s1_pip,...
+    printRegPair(MI, 1, O); 
+    SStream_concat0(O, ", ");
+    break;
+  case 3:
+    // ADD2_d2_rrr, ADD2_l1_rrr_x2, ADD2_s1_rrr, ADD4_l1_rrr_x2, ADDU_l1_rpp,...
+    printOperand(MI, 2, O); 
+    SStream_concat0(O, ", ");
+    break;
+  case 4:
+    // BNOP_s10_ri, BNOP_s9_ii, B_s5_i, B_s6_r, NOP_n, STB_d5_rm, STB_d6_rm, ...
+    printOperand(MI, 0, O); 
+    break;
+  case 5:
+    // LDBU_d5_mr, LDB_d5_mr, LDDW_d7_mp, LDHU_d5_mr, LDH_d5_mr, LDNDW_d8_mp,...
+    printMemOperand(MI, 1, O); 
+    SStream_concat0(O, ", ");
+    break;
+  case 6:
+    // LDBU_d6_mr, LDB_d6_mr, LDHU_d6_mr, LDH_d6_mr, LDW_d6_mr
+    printMemOperand2(MI, 1, O); 
+    SStream_concat0(O, ", ");
+    printOperand(MI, 0, O); 
+    return;
+    break;
+  case 7:
+    // STDW_d7_pm, STNDW_d8_pm
+    printRegPair(MI, 0, O); 
+    SStream_concat0(O, ", ");
+    printMemOperand(MI, 1, O); 
+    return;
+    break;
+  }
+
+
+  // Fragment 1 encoded into 3 bits for 7 unique commands.
+  switch ((Bits >> 13) & 7) {
+  default:
+  case 0:
+    // ABS2_l2_rr, ABS_l1_rr, ADDKPC_s3_iir, ADDK_s2_ir, BDEC_s8_ir, BITC4_m2...
+    printOperand(MI, 0, O); 
+    break;
+  case 1:
+    // ABS_l1_pp, LDDW_d7_mp, LDNDW_d8_mp
+    printRegPair(MI, 0, O); 
+    return;
+    break;
+  case 2:
+    // ADD2_d2_rrr, ADD2_l1_rrr_x2, ADD2_s1_rrr, ADD4_l1_rrr_x2, ADDU_l1_rrp_...
+    printOperand(MI, 1, O); 
+    SStream_concat0(O, ", ");
+    break;
+  case 3:
+    // ADDAB_d1_rir, ADDAB_d1_rrr, ADDAD_d1_rir, ADDAD_d1_rrr, ADDAH_d1_rir, ...
+    printOperand(MI, 2, O); 
+    SStream_concat0(O, ", ");
+    break;
+  case 4:
+    // ADDU_l1_rpp, ADD_l1_ipp, ADD_l1_rpp, CMPEQ_l1_ipr, CMPEQ_l1_rpr, CMPGT...
+    printRegPair(MI, 1, O); 
+    SStream_concat0(O, ", ");
+    break;
+  case 5:
+    // BNOP_s10_ri, BNOP_s9_ii, STB_d5_rm, STB_d6_rm, STH_d5_rm, STH_d6_rm, S...
+    SStream_concat0(O, ", ");
+    break;
+  case 6:
+    // B_s5_i, B_s6_r, NOP_n
+    return;
+    break;
+  }
+
+
+  // Fragment 2 encoded into 3 bits for 8 unique commands.
+  switch ((Bits >> 16) & 7) {
+  default:
+  case 0:
+    // ABS2_l2_rr, ABS_l1_rr, ADDK_s2_ir, BDEC_s8_ir, BITC4_m2_rr, BPOS_s8_ir...
+    return;
+    break;
+  case 1:
+    // ADD2_d2_rrr, ADD2_l1_rrr_x2, ADD2_s1_rrr, ADD4_l1_rrr_x2, ADDAB_d1_rir...
+    printOperand(MI, 0, O); 
+    return;
+    break;
+  case 2:
+    // ADDKPC_s3_iir
+    SStream_concat0(O, ", ");
+    printOperand(MI, 2, O); 
+    return;
+    break;
+  case 3:
+    // ADDU_l1_rpp, ADDU_l1_rrp_x2, ADD_l1_ipp, ADD_l1_rpp, ADD_l1_rrp_x2, DO...
+    printRegPair(MI, 0, O); 
+    return;
+    break;
+  case 4:
+    // BNOP_s10_ri, BNOP_s9_ii
+    printOperand(MI, 1, O); 
+    return;
+    break;
+  case 5:
+    // CLR_s15_riir, EXTU_s15_riir, EXT_s15_riir, SET_s15_riir
+    printOperand(MI, 3, O); 
+    SStream_concat0(O, ", ");
+    printOperand(MI, 0, O); 
+    return;
+    break;
+  case 6:
+    // STB_d5_rm, STH_d5_rm, STNW_d5_rm, STW_d5_rm
+    printMemOperand(MI, 1, O); 
+    return;
+    break;
+  case 7:
+    // STB_d6_rm, STH_d6_rm, STW_d6_rm
+    printMemOperand2(MI, 1, O); 
+    return;
+    break;
+  }
+
+}
+
+
+/// getRegisterName - This method is automatically generated by tblgen
+/// from the register set description.  This returns the assembler name
+/// for the specified register.
+static const char *getRegisterName(unsigned RegNo) {
+#ifndef CAPSTONE_DIET
+  static const char AsmStrs[] = {
+  /* 0 */ 'a', '1', '0', 0,
+  /* 4 */ 'b', '1', '0', 0,
+  /* 8 */ 'a', '2', '0', 0,
+  /* 12 */ 'b', '2', '0', 0,
+  /* 16 */ 'a', '3', '0', 0,
+  /* 20 */ 'b', '3', '0', 0,
+  /* 24 */ 'a', '0', 0,
+  /* 27 */ 'b', '0', 0,
+  /* 30 */ 'a', '1', '1', 0,
+  /* 34 */ 'b', '1', '1', 0,
+  /* 38 */ 'a', '2', '1', 0,
+  /* 42 */ 'b', '2', '1', 0,
+  /* 46 */ 'a', '3', '1', 0,
+  /* 50 */ 'b', '3', '1', 0,
+  /* 54 */ 'a', '1', 0,
+  /* 57 */ 'b', '1', 0,
+  /* 60 */ 'p', 'c', 'e', '1', 0,
+  /* 65 */ 'a', '1', '2', 0,
+  /* 69 */ 'b', '1', '2', 0,
+  /* 73 */ 'a', '2', '2', 0,
+  /* 77 */ 'b', '2', '2', 0,
+  /* 81 */ 'a', '2', 0,
+  /* 84 */ 'b', '2', 0,
+  /* 87 */ 'a', '1', '3', 0,
+  /* 91 */ 'b', '1', '3', 0,
+  /* 95 */ 'a', '2', '3', 0,
+  /* 99 */ 'b', '2', '3', 0,
+  /* 103 */ 'a', '3', 0,
+  /* 106 */ 'b', '3', 0,
+  /* 109 */ 'a', '1', '4', 0,
+  /* 113 */ 'b', '1', '4', 0,
+  /* 117 */ 'a', '2', '4', 0,
+  /* 121 */ 'b', '2', '4', 0,
+  /* 125 */ 'a', '4', 0,
+  /* 128 */ 'b', '4', 0,
+  /* 131 */ 'a', '1', '5', 0,
+  /* 135 */ 'b', '1', '5', 0,
+  /* 139 */ 'a', '2', '5', 0,
+  /* 143 */ 'b', '2', '5', 0,
+  /* 147 */ 'a', '5', 0,
+  /* 150 */ 'b', '5', 0,
+  /* 153 */ 'a', '1', '6', 0,
+  /* 157 */ 'b', '1', '6', 0,
+  /* 161 */ 'a', '2', '6', 0,
+  /* 165 */ 'b', '2', '6', 0,
+  /* 169 */ 'a', '6', 0,
+  /* 172 */ 'b', '6', 0,
+  /* 175 */ 'a', '1', '7', 0,
+  /* 179 */ 'b', '1', '7', 0,
+  /* 183 */ 'a', '2', '7', 0,
+  /* 187 */ 'b', '2', '7', 0,
+  /* 191 */ 'a', '7', 0,
+  /* 194 */ 'b', '7', 0,
+  /* 197 */ 'a', '1', '8', 0,
+  /* 201 */ 'b', '1', '8', 0,
+  /* 205 */ 'a', '2', '8', 0,
+  /* 209 */ 'b', '2', '8', 0,
+  /* 213 */ 'a', '8', 0,
+  /* 216 */ 'b', '8', 0,
+  /* 219 */ 'a', '1', '9', 0,
+  /* 223 */ 'b', '1', '9', 0,
+  /* 227 */ 'a', '2', '9', 0,
+  /* 231 */ 'b', '2', '9', 0,
+  /* 235 */ 'a', '9', 0,
+  /* 238 */ 'b', '9', 0,
+  /* 241 */ 'g', 'p', 'l', 'y', 'a', 0,
+  /* 247 */ 'g', 'p', 'l', 'y', 'b', 0,
+  /* 253 */ 'r', 'i', 'l', 'c', 0,
+  /* 258 */ 't', 's', 'c', 'h', 0,
+  /* 263 */ 't', 's', 'c', 'l', 0,
+  /* 268 */ 'd', 'n', 'u', 'm', 0,
+  /* 273 */ 'r', 'e', 'p', 0,
+  /* 277 */ 'i', 'r', 'p', 0,
+  /* 281 */ 'n', 'r', 'p', 0,
+  /* 285 */ 'i', 's', 't', 'p', 0,
+  /* 290 */ 'e', 'c', 'r', 0,
+  /* 294 */ 'i', 'c', 'r', 0,
+  /* 298 */ 'd', 'i', 'e', 'r', 0,
+  /* 303 */ 'g', 'f', 'p', 'g', 'f', 'r', 0,
+  /* 310 */ 'a', 'm', 'r', 0,
+  /* 314 */ 'i', 'e', 'r', 'r', 0,
+  /* 319 */ 'c', 's', 'r', 0,
+  /* 323 */ 'i', 's', 'r', 0,
+  /* 327 */ 's', 's', 'r', 0,
+  /* 331 */ 'i', 't', 's', 'r', 0,
+  /* 336 */ 'n', 't', 's', 'r', 0,
+  };
+
+  static const uint16_t RegAsmOffset[] = {
+    310, 319, 298, 268, 290, 303, 241, 247, 294, 299, 314, 254, 277, 323, 
+    285, 331, 281, 336, 273, 253, 327, 258, 263, 332, 24, 54, 81, 103, 
+    125, 147, 169, 191, 213, 235, 0, 30, 65, 87, 109, 131, 153, 175, 
+    197, 219, 8, 38, 73, 95, 117, 139, 161, 183, 205, 227, 16, 46, 
+    27, 57, 84, 106, 128, 150, 172, 194, 216, 238, 4, 34, 69, 91, 
+    113, 135, 157, 179, 201, 223, 12, 42, 77, 99, 121, 143, 165, 187, 
+    209, 231, 20, 50, 60, 
+  };
+
+  return AsmStrs+RegAsmOffset[RegNo-1];
+#else
+  return NULL;
+#endif
+}
diff --git a/capstone/arch/TMS320C64x/TMS320C64xGenDisassemblerTables.inc b/capstone/arch/TMS320C64x/TMS320C64xGenDisassemblerTables.inc
new file mode 100644
index 000000000..415e6b76b
--- /dev/null
+++ b/capstone/arch/TMS320C64x/TMS320C64xGenDisassemblerTables.inc
@@ -0,0 +1,1352 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|* * TMS320C64x Disassembler                                                  *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+#include "../../MCInst.h"
+#include "../../LEB128.h"
+
+// Helper function for extracting fields from encoded instructions.
+#define FieldFromInstruction(fname, InsnType) \
+static InsnType fname(InsnType insn, unsigned startBit, \
+                                     unsigned numBits) { \
+    InsnType fieldMask; \
+    if (numBits == sizeof(InsnType)*8) \
+      fieldMask = (InsnType)(-1LL); \
+    else \
+      fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
+    return (insn & fieldMask) >> startBit; \
+}
+
+static const uint8_t DecoderTable32[] = {
+/* 0 */       MCD_OPC_ExtractField, 2, 5,  // Inst{6-2} ...
+/* 3 */       MCD_OPC_FilterValue, 0, 199, 0, // Skip to: 206
+/* 7 */       MCD_OPC_ExtractField, 7, 5,  // Inst{11-7} ...
+/* 10 */      MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 30
+/* 14 */      MCD_OPC_CheckField, 17, 11, 0, 153, 8, // Skip to: 2221
+/* 20 */      MCD_OPC_CheckField, 12, 1, 0, 147, 8, // Skip to: 2221
+/* 26 */      MCD_OPC_Decode, 162, 1, 0, // Opcode: NOP_n
+/* 30 */      MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 38
+/* 34 */      MCD_OPC_Decode, 140, 1, 1, // Opcode: MPYH_m4_rrr
+/* 38 */      MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 46
+/* 42 */      MCD_OPC_Decode, 219, 1, 1, // Opcode: SMPYH_m4_rrr
+/* 46 */      MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 54
+/* 50 */      MCD_OPC_Decode, 136, 1, 1, // Opcode: MPYHSU_m4_rrr
+/* 54 */      MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 62
+/* 58 */      MCD_OPC_Decode, 138, 1, 1, // Opcode: MPYHUS_m4_rrr
+/* 62 */      MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 70
+/* 66 */      MCD_OPC_Decode, 139, 1, 1, // Opcode: MPYHU_m4_rrr
+/* 70 */      MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 78
+/* 74 */      MCD_OPC_Decode, 134, 1, 1, // Opcode: MPYHL_m4_rrr
+/* 78 */      MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 86
+/* 82 */      MCD_OPC_Decode, 218, 1, 1, // Opcode: SMPYHL_m4_rrr
+/* 86 */      MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 94
+/* 90 */      MCD_OPC_Decode, 135, 1, 1, // Opcode: MPYHSLU_m4_rrr
+/* 94 */      MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 102
+/* 98 */      MCD_OPC_Decode, 137, 1, 1, // Opcode: MPYHULS_m4_rrr
+/* 102 */     MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 110
+/* 106 */     MCD_OPC_Decode, 133, 1, 1, // Opcode: MPYHLU_m4_rrr
+/* 110 */     MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 118
+/* 114 */     MCD_OPC_Decode, 142, 1, 1, // Opcode: MPYLH_m4_rrr
+/* 118 */     MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 126
+/* 122 */     MCD_OPC_Decode, 220, 1, 1, // Opcode: SMPYLH_m4_rrr
+/* 126 */     MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 134
+/* 130 */     MCD_OPC_Decode, 145, 1, 1, // Opcode: MPYLSHU_m4_rrr
+/* 134 */     MCD_OPC_FilterValue, 21, 4, 0, // Skip to: 142
+/* 138 */     MCD_OPC_Decode, 146, 1, 1, // Opcode: MPYLUHS_m4_rrr
+/* 142 */     MCD_OPC_FilterValue, 23, 4, 0, // Skip to: 150
+/* 146 */     MCD_OPC_Decode, 141, 1, 1, // Opcode: MPYLHU_m4_rrr
+/* 150 */     MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 158
+/* 154 */     MCD_OPC_Decode, 153, 1, 2, // Opcode: MPY_m4_irr
+/* 158 */     MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 166
+/* 162 */     MCD_OPC_Decode, 154, 1, 1, // Opcode: MPY_m4_rrr
+/* 166 */     MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 174
+/* 170 */     MCD_OPC_Decode, 221, 1, 1, // Opcode: SMPY_m4_rrr
+/* 174 */     MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 182
+/* 178 */     MCD_OPC_Decode, 149, 1, 1, // Opcode: MPYSU_m4_rrr
+/* 182 */     MCD_OPC_FilterValue, 29, 4, 0, // Skip to: 190
+/* 186 */     MCD_OPC_Decode, 151, 1, 1, // Opcode: MPYUS_m4_rrr
+/* 190 */     MCD_OPC_FilterValue, 30, 4, 0, // Skip to: 198
+/* 194 */     MCD_OPC_Decode, 148, 1, 2, // Opcode: MPYSU_m4_irr
+/* 198 */     MCD_OPC_FilterValue, 31, 227, 7, // Skip to: 2221
+/* 202 */     MCD_OPC_Decode, 152, 1, 1, // Opcode: MPYU_m4_rrr
+/* 206 */     MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 219
+/* 210 */     MCD_OPC_CheckField, 8, 1, 0, 213, 7, // Skip to: 2221
+/* 216 */     MCD_OPC_Decode, 116, 3, // Opcode: LDHU_d5_mr
+/* 219 */     MCD_OPC_FilterValue, 2, 18, 0, // Skip to: 241
+/* 223 */     MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 226 */     MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 233
+/* 230 */     MCD_OPC_Decode, 102, 4, // Opcode: EXTU_s15_riir
+/* 233 */     MCD_OPC_FilterValue, 1, 192, 7, // Skip to: 2221
+/* 237 */     MCD_OPC_Decode, 192, 1, 4, // Opcode: SET_s15_riir
+/* 241 */     MCD_OPC_FilterValue, 3, 3, 0, // Skip to: 248
+/* 245 */     MCD_OPC_Decode, 117, 5, // Opcode: LDHU_d6_mr
+/* 248 */     MCD_OPC_FilterValue, 4, 3, 0, // Skip to: 255
+/* 252 */     MCD_OPC_Decode, 68, 6, // Opcode: B_s5_i
+/* 255 */     MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 268
+/* 259 */     MCD_OPC_CheckField, 8, 1, 0, 164, 7, // Skip to: 2221
+/* 265 */     MCD_OPC_Decode, 111, 3, // Opcode: LDBU_d5_mr
+/* 268 */     MCD_OPC_FilterValue, 6, 157, 0, // Skip to: 429
+/* 272 */     MCD_OPC_ExtractField, 7, 5,  // Inst{11-7} ...
+/* 275 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 283
+/* 279 */     MCD_OPC_Decode, 171, 1, 1, // Opcode: PACK2_l1_rrr_x2
+/* 283 */     MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 291
+/* 287 */     MCD_OPC_Decode, 242, 1, 1, // Opcode: SUB2_l1_rrr_x2
+/* 291 */     MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 299
+/* 295 */     MCD_OPC_Decode, 176, 1, 1, // Opcode: PACKHL2_l1_rrr_x2
+/* 299 */     MCD_OPC_FilterValue, 8, 3, 0, // Skip to: 306
+/* 303 */     MCD_OPC_Decode, 45, 7, // Opcode: ADD_l1_ipp
+/* 306 */     MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 314
+/* 310 */     MCD_OPC_Decode, 130, 2, 7, // Opcode: SUB_l1_ipp
+/* 314 */     MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 322
+/* 318 */     MCD_OPC_Decode, 228, 1, 7, // Opcode: SSUB_l1_ipp
+/* 322 */     MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 330
+/* 326 */     MCD_OPC_Decode, 186, 1, 7, // Opcode: SADD_l1_ipp
+/* 330 */     MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 343
+/* 334 */     MCD_OPC_CheckField, 13, 5, 0, 89, 7, // Skip to: 2221
+/* 340 */     MCD_OPC_Decode, 23, 8, // Opcode: ABS_l1_pp
+/* 343 */     MCD_OPC_FilterValue, 16, 10, 0, // Skip to: 357
+/* 347 */     MCD_OPC_CheckField, 13, 5, 0, 76, 7, // Skip to: 2221
+/* 353 */     MCD_OPC_Decode, 191, 1, 9, // Opcode: SAT_l1_pr
+/* 357 */     MCD_OPC_FilterValue, 17, 3, 0, // Skip to: 364
+/* 361 */     MCD_OPC_Decode, 82, 10, // Opcode: CMPGT_l1_ipr
+/* 364 */     MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 372
+/* 368 */     MCD_OPC_Decode, 129, 1, 1, // Opcode: MINU4_l1_rrr_x2
+/* 372 */     MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 379
+/* 376 */     MCD_OPC_Decode, 106, 11, // Opcode: GMPGTU_l1_ipr
+/* 379 */     MCD_OPC_FilterValue, 20, 3, 0, // Skip to: 386
+/* 383 */     MCD_OPC_Decode, 76, 10, // Opcode: CMPEQ_l1_ipr
+/* 386 */     MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 393
+/* 390 */     MCD_OPC_Decode, 90, 10, // Opcode: CMPLT_l1_ipr
+/* 393 */     MCD_OPC_FilterValue, 23, 3, 0, // Skip to: 400
+/* 397 */     MCD_OPC_Decode, 86, 11, // Opcode: CMPLTU_l1_ipr
+/* 400 */     MCD_OPC_FilterValue, 24, 10, 0, // Skip to: 414
+/* 404 */     MCD_OPC_CheckField, 13, 5, 0, 19, 7, // Skip to: 2221
+/* 410 */     MCD_OPC_Decode, 163, 1, 12, // Opcode: NORM_l1_pr
+/* 414 */     MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 422
+/* 418 */     MCD_OPC_Decode, 178, 1, 1, // Opcode: PACKL4_l1_rrr_x2
+/* 422 */     MCD_OPC_FilterValue, 31, 3, 7, // Skip to: 2221
+/* 426 */     MCD_OPC_Decode, 53, 1, // Opcode: ANDN_l1_rrr_x2
+/* 429 */     MCD_OPC_FilterValue, 7, 3, 0, // Skip to: 436
+/* 433 */     MCD_OPC_Decode, 112, 5, // Opcode: LDBU_d6_mr
+/* 436 */     MCD_OPC_FilterValue, 8, 222, 0, // Skip to: 662
+/* 440 */     MCD_OPC_ExtractField, 7, 5,  // Inst{11-7} ...
+/* 443 */     MCD_OPC_FilterValue, 0, 17, 0, // Skip to: 464
+/* 447 */     MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 450 */     MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 457
+/* 454 */     MCD_OPC_Decode, 67, 13, // Opcode: BPOS_s8_ir
+/* 457 */     MCD_OPC_FilterValue, 1, 224, 6, // Skip to: 2221
+/* 461 */     MCD_OPC_Decode, 63, 13, // Opcode: BDEC_s8_ir
+/* 464 */     MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 477
+/* 468 */     MCD_OPC_CheckField, 12, 1, 0, 211, 6, // Skip to: 2221
+/* 474 */     MCD_OPC_Decode, 66, 14, // Opcode: BNOP_s9_ii
+/* 477 */     MCD_OPC_FilterValue, 3, 3, 0, // Skip to: 484
+/* 481 */     MCD_OPC_Decode, 50, 2, // Opcode: ADD_s1_irr
+/* 484 */     MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 492
+/* 488 */     MCD_OPC_Decode, 177, 1, 1, // Opcode: PACKHL2_s1_rrr
+/* 492 */     MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 500
+/* 496 */     MCD_OPC_Decode, 148, 2, 2, // Opcode: XOR_s1_irr
+/* 500 */     MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 514
+/* 504 */     MCD_OPC_CheckField, 13, 5, 0, 175, 6, // Skip to: 2221
+/* 510 */     MCD_OPC_Decode, 156, 1, 15, // Opcode: MVC_s1_rr2
+/* 514 */     MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 522
+/* 518 */     MCD_OPC_Decode, 180, 1, 1, // Opcode: PACKLH2_s1_rrr
+/* 522 */     MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 530
+/* 526 */     MCD_OPC_Decode, 199, 1, 16, // Opcode: SHL_s1_rip
+/* 530 */     MCD_OPC_FilterValue, 10, 3, 0, // Skip to: 537
+/* 534 */     MCD_OPC_Decode, 80, 1, // Opcode: CMPGT2_s1_rrr
+/* 537 */     MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 545
+/* 541 */     MCD_OPC_Decode, 136, 2, 2, // Opcode: SUB_s1_irr
+/* 545 */     MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 553
+/* 549 */     MCD_OPC_Decode, 203, 1, 17, // Opcode: SHR2_s1_rir
+/* 553 */     MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 561
+/* 557 */     MCD_OPC_Decode, 169, 1, 2, // Opcode: OR_s1_irr
+/* 561 */     MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 568
+/* 565 */     MCD_OPC_Decode, 75, 1, // Opcode: CMPEQ4_s1_rrr
+/* 568 */     MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 575
+/* 572 */     MCD_OPC_Decode, 59, 2, // Opcode: AND_s1_irr
+/* 575 */     MCD_OPC_FilterValue, 16, 4, 0, // Skip to: 583
+/* 579 */     MCD_OPC_Decode, 190, 1, 1, // Opcode: SADD_s1_rrr
+/* 583 */     MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 591
+/* 587 */     MCD_OPC_Decode, 224, 1, 17, // Opcode: SSHL_s1_rir
+/* 591 */     MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 599
+/* 595 */     MCD_OPC_Decode, 209, 1, 18, // Opcode: SHRU_s1_pip
+/* 599 */     MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 607
+/* 603 */     MCD_OPC_Decode, 211, 1, 17, // Opcode: SHRU_s1_rir
+/* 607 */     MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 615
+/* 611 */     MCD_OPC_Decode, 197, 1, 19, // Opcode: SHL_s1_pip
+/* 615 */     MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 623
+/* 619 */     MCD_OPC_Decode, 200, 1, 20, // Opcode: SHL_s1_rir
+/* 623 */     MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 631
+/* 627 */     MCD_OPC_Decode, 213, 1, 18, // Opcode: SHR_s1_pip
+/* 631 */     MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 639
+/* 635 */     MCD_OPC_Decode, 215, 1, 17, // Opcode: SHR_s1_rir
+/* 639 */     MCD_OPC_FilterValue, 30, 42, 6, // Skip to: 2221
+/* 643 */     MCD_OPC_ExtractField, 13, 5,  // Inst{17-13} ...
+/* 646 */     MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 654
+/* 650 */     MCD_OPC_Decode, 143, 2, 21, // Opcode: UNPKLU4_s14_rr
+/* 654 */     MCD_OPC_FilterValue, 3, 27, 6, // Skip to: 2221
+/* 658 */     MCD_OPC_Decode, 141, 2, 21, // Opcode: UNPKHU4_s14_rr
+/* 662 */     MCD_OPC_FilterValue, 9, 17, 0, // Skip to: 683
+/* 666 */     MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
+/* 669 */     MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 676
+/* 673 */     MCD_OPC_Decode, 113, 3, // Opcode: LDB_d5_mr
+/* 676 */     MCD_OPC_FilterValue, 1, 5, 6, // Skip to: 2221
+/* 680 */     MCD_OPC_Decode, 120, 22, // Opcode: LDNDW_d8_mp
+/* 683 */     MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 691
+/* 687 */     MCD_OPC_Decode, 159, 1, 23, // Opcode: MVKL_s12_ir
+/* 691 */     MCD_OPC_FilterValue, 11, 3, 0, // Skip to: 698
+/* 695 */     MCD_OPC_Decode, 114, 5, // Opcode: LDB_d6_mr
+/* 698 */     MCD_OPC_FilterValue, 12, 194, 0, // Skip to: 896
+/* 702 */     MCD_OPC_ExtractField, 7, 5,  // Inst{11-7} ...
+/* 705 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 713
+/* 709 */     MCD_OPC_Decode, 130, 1, 24, // Opcode: MPY2_m1_rrp
+/* 713 */     MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 720
+/* 717 */     MCD_OPC_Decode, 100, 1, // Opcode: DOTPSU4_m1_rrr
+/* 720 */     MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 728
+/* 724 */     MCD_OPC_Decode, 150, 1, 24, // Opcode: MPYU4_m1_rrp
+/* 728 */     MCD_OPC_FilterValue, 3, 3, 0, // Skip to: 735
+/* 732 */     MCD_OPC_Decode, 101, 1, // Opcode: DOTPU4_m1_rrr
+/* 735 */     MCD_OPC_FilterValue, 6, 3, 0, // Skip to: 742
+/* 739 */     MCD_OPC_Decode, 96, 1, // Opcode: DOTP2_m1_rrr
+/* 742 */     MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 750
+/* 746 */     MCD_OPC_Decode, 143, 1, 1, // Opcode: MPYLIR_m1_rrr
+/* 750 */     MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 758
+/* 754 */     MCD_OPC_Decode, 131, 1, 1, // Opcode: MPYHIR_m1_rrr
+/* 758 */     MCD_OPC_FilterValue, 9, 3, 0, // Skip to: 765
+/* 762 */     MCD_OPC_Decode, 62, 1, // Opcode: AVGU4_m1_rrr
+/* 765 */     MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 773
+/* 769 */     MCD_OPC_Decode, 132, 1, 24, // Opcode: MPYHI_m1_rrp
+/* 773 */     MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 781
+/* 777 */     MCD_OPC_Decode, 227, 1, 1, // Opcode: SSHVR_m1_rrr
+/* 781 */     MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 789
+/* 785 */     MCD_OPC_Decode, 226, 1, 1, // Opcode: SSHVL_m1_rrr
+/* 789 */     MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 797
+/* 793 */     MCD_OPC_Decode, 181, 1, 17, // Opcode: ROTL_m1_rir
+/* 797 */     MCD_OPC_FilterValue, 16, 3, 0, // Skip to: 804
+/* 801 */     MCD_OPC_Decode, 52, 1, // Opcode: ANDN_d2_rrr
+/* 804 */     MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 812
+/* 808 */     MCD_OPC_Decode, 166, 1, 1, // Opcode: OR_d2_rrr
+/* 812 */     MCD_OPC_FilterValue, 18, 3, 0, // Skip to: 819
+/* 816 */     MCD_OPC_Decode, 25, 1, // Opcode: ADD2_d2_rrr
+/* 819 */     MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 826
+/* 823 */     MCD_OPC_Decode, 56, 1, // Opcode: AND_d2_rrr
+/* 826 */     MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 833
+/* 830 */     MCD_OPC_Decode, 44, 1, // Opcode: ADD_d2_rrr
+/* 833 */     MCD_OPC_FilterValue, 22, 4, 0, // Skip to: 841
+/* 837 */     MCD_OPC_Decode, 129, 2, 1, // Opcode: SUB_d2_rrr
+/* 841 */     MCD_OPC_FilterValue, 23, 4, 0, // Skip to: 849
+/* 845 */     MCD_OPC_Decode, 145, 2, 1, // Opcode: XOR_d2_rrr
+/* 849 */     MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 857
+/* 853 */     MCD_OPC_Decode, 183, 1, 1, // Opcode: SADD2_s4_rrr
+/* 857 */     MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 865
+/* 861 */     MCD_OPC_Decode, 222, 1, 1, // Opcode: SPACK2_s4_rrr
+/* 865 */     MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 873
+/* 869 */     MCD_OPC_Decode, 223, 1, 1, // Opcode: SPACKU4_s4_rrr
+/* 873 */     MCD_OPC_FilterValue, 27, 3, 0, // Skip to: 880
+/* 877 */     MCD_OPC_Decode, 54, 1, // Opcode: ANDN_s4_rrr
+/* 880 */     MCD_OPC_FilterValue, 28, 4, 0, // Skip to: 888
+/* 884 */     MCD_OPC_Decode, 208, 1, 1, // Opcode: SHRU2_s4_rrr
+/* 888 */     MCD_OPC_FilterValue, 29, 49, 5, // Skip to: 2221
+/* 892 */     MCD_OPC_Decode, 206, 1, 1, // Opcode: SHRMB_s4_rrr
+/* 896 */     MCD_OPC_FilterValue, 13, 18, 0, // Skip to: 918
+/* 900 */     MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
+/* 903 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 911
+/* 907 */     MCD_OPC_Decode, 232, 1, 3, // Opcode: STB_d5_rm
+/* 911 */     MCD_OPC_FilterValue, 1, 26, 5, // Skip to: 2221
+/* 915 */     MCD_OPC_Decode, 121, 3, // Opcode: LDNW_d5_mr
+/* 918 */     MCD_OPC_FilterValue, 14, 98, 0, // Skip to: 1020
+/* 922 */     MCD_OPC_ExtractField, 7, 5,  // Inst{11-7} ...
+/* 925 */     MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 932
+/* 929 */     MCD_OPC_Decode, 26, 1, // Opcode: ADD2_l1_rrr_x2
+/* 932 */     MCD_OPC_FilterValue, 8, 3, 0, // Skip to: 939
+/* 936 */     MCD_OPC_Decode, 47, 25, // Opcode: ADD_l1_rpp
+/* 939 */     MCD_OPC_FilterValue, 10, 3, 0, // Skip to: 946
+/* 943 */     MCD_OPC_Decode, 39, 25, // Opcode: ADDU_l1_rpp
+/* 946 */     MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 954
+/* 950 */     MCD_OPC_Decode, 188, 1, 25, // Opcode: SADD_l1_rpp
+/* 954 */     MCD_OPC_FilterValue, 16, 4, 0, // Skip to: 962
+/* 958 */     MCD_OPC_Decode, 128, 1, 1, // Opcode: MIN2_l1_rrr_x2
+/* 962 */     MCD_OPC_FilterValue, 17, 3, 0, // Skip to: 969
+/* 966 */     MCD_OPC_Decode, 84, 26, // Opcode: CMPGT_l1_rpr
+/* 969 */     MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 976
+/* 973 */     MCD_OPC_Decode, 108, 26, // Opcode: GMPGTU_l1_rpr
+/* 976 */     MCD_OPC_FilterValue, 20, 3, 0, // Skip to: 983
+/* 980 */     MCD_OPC_Decode, 78, 26, // Opcode: CMPEQ_l1_rpr
+/* 983 */     MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 990
+/* 987 */     MCD_OPC_Decode, 92, 26, // Opcode: CMPLT_l1_rpr
+/* 990 */     MCD_OPC_FilterValue, 23, 3, 0, // Skip to: 997
+/* 994 */     MCD_OPC_Decode, 88, 26, // Opcode: CMPLTU_l1_rpr
+/* 997 */     MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 1005
+/* 1001 */    MCD_OPC_Decode, 195, 1, 1, // Opcode: SHLMB_l1_rrr_x2
+/* 1005 */    MCD_OPC_FilterValue, 25, 3, 0, // Skip to: 1012
+/* 1009 */    MCD_OPC_Decode, 28, 1, // Opcode: ADD4_l1_rrr_x2
+/* 1012 */    MCD_OPC_FilterValue, 26, 181, 4, // Skip to: 2221
+/* 1016 */    MCD_OPC_Decode, 175, 1, 1, // Opcode: PACKH4_l1_rrr_x2
+/* 1020 */    MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 1028
+/* 1024 */    MCD_OPC_Decode, 233, 1, 5, // Opcode: STB_d6_rm
+/* 1028 */    MCD_OPC_FilterValue, 16, 151, 0, // Skip to: 1183
+/* 1032 */    MCD_OPC_ExtractField, 7, 6,  // Inst{12-7} ...
+/* 1035 */    MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1049
+/* 1039 */    MCD_OPC_CheckField, 18, 5, 0, 152, 4, // Skip to: 2221
+/* 1045 */    MCD_OPC_Decode, 160, 1, 27, // Opcode: MVK_d1_rr
+/* 1049 */    MCD_OPC_FilterValue, 16, 3, 0, // Skip to: 1056
+/* 1053 */    MCD_OPC_Decode, 42, 28, // Opcode: ADD_d1_rrr
+/* 1056 */    MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 1064
+/* 1060 */    MCD_OPC_Decode, 128, 2, 28, // Opcode: SUB_d1_rrr
+/* 1064 */    MCD_OPC_FilterValue, 18, 3, 0, // Skip to: 1071
+/* 1068 */    MCD_OPC_Decode, 41, 29, // Opcode: ADD_d1_rir
+/* 1071 */    MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 1079
+/* 1075 */    MCD_OPC_Decode, 255, 1, 29, // Opcode: SUB_d1_rir
+/* 1079 */    MCD_OPC_FilterValue, 48, 3, 0, // Skip to: 1086
+/* 1083 */    MCD_OPC_Decode, 30, 28, // Opcode: ADDAB_d1_rrr
+/* 1086 */    MCD_OPC_FilterValue, 49, 4, 0, // Skip to: 1094
+/* 1090 */    MCD_OPC_Decode, 247, 1, 28, // Opcode: SUBAB_d1_rrr
+/* 1094 */    MCD_OPC_FilterValue, 50, 3, 0, // Skip to: 1101
+/* 1098 */    MCD_OPC_Decode, 29, 29, // Opcode: ADDAB_d1_rir
+/* 1101 */    MCD_OPC_FilterValue, 51, 4, 0, // Skip to: 1109
+/* 1105 */    MCD_OPC_Decode, 246, 1, 29, // Opcode: SUBAB_d1_rir
+/* 1109 */    MCD_OPC_FilterValue, 52, 3, 0, // Skip to: 1116
+/* 1113 */    MCD_OPC_Decode, 34, 28, // Opcode: ADDAH_d1_rrr
+/* 1116 */    MCD_OPC_FilterValue, 53, 4, 0, // Skip to: 1124
+/* 1120 */    MCD_OPC_Decode, 249, 1, 28, // Opcode: SUBAH_d1_rrr
+/* 1124 */    MCD_OPC_FilterValue, 54, 3, 0, // Skip to: 1131
+/* 1128 */    MCD_OPC_Decode, 33, 29, // Opcode: ADDAH_d1_rir
+/* 1131 */    MCD_OPC_FilterValue, 55, 4, 0, // Skip to: 1139
+/* 1135 */    MCD_OPC_Decode, 248, 1, 29, // Opcode: SUBAH_d1_rir
+/* 1139 */    MCD_OPC_FilterValue, 56, 3, 0, // Skip to: 1146
+/* 1143 */    MCD_OPC_Decode, 36, 28, // Opcode: ADDAW_d1_rrr
+/* 1146 */    MCD_OPC_FilterValue, 57, 4, 0, // Skip to: 1154
+/* 1150 */    MCD_OPC_Decode, 251, 1, 28, // Opcode: SUBAW_d1_rrr
+/* 1154 */    MCD_OPC_FilterValue, 58, 3, 0, // Skip to: 1161
+/* 1158 */    MCD_OPC_Decode, 35, 29, // Opcode: ADDAW_d1_rir
+/* 1161 */    MCD_OPC_FilterValue, 59, 4, 0, // Skip to: 1169
+/* 1165 */    MCD_OPC_Decode, 250, 1, 29, // Opcode: SUBAW_d1_rir
+/* 1169 */    MCD_OPC_FilterValue, 60, 3, 0, // Skip to: 1176
+/* 1173 */    MCD_OPC_Decode, 32, 28, // Opcode: ADDAD_d1_rrr
+/* 1176 */    MCD_OPC_FilterValue, 61, 17, 4, // Skip to: 2221
+/* 1180 */    MCD_OPC_Decode, 31, 29, // Opcode: ADDAD_d1_rir
+/* 1183 */    MCD_OPC_FilterValue, 17, 18, 0, // Skip to: 1205
+/* 1187 */    MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
+/* 1190 */    MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1197
+/* 1194 */    MCD_OPC_Decode, 118, 3, // Opcode: LDH_d5_mr
+/* 1197 */    MCD_OPC_FilterValue, 1, 252, 3, // Skip to: 2221
+/* 1201 */    MCD_OPC_Decode, 234, 1, 30, // Opcode: STDW_d7_pm
+/* 1205 */    MCD_OPC_FilterValue, 18, 17, 0, // Skip to: 1226
+/* 1209 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1212 */    MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1219
+/* 1216 */    MCD_OPC_Decode, 104, 4, // Opcode: EXT_s15_riir
+/* 1219 */    MCD_OPC_FilterValue, 1, 230, 3, // Skip to: 2221
+/* 1223 */    MCD_OPC_Decode, 72, 4, // Opcode: CLR_s15_riir
+/* 1226 */    MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 1233
+/* 1230 */    MCD_OPC_Decode, 119, 5, // Opcode: LDH_d6_mr
+/* 1233 */    MCD_OPC_FilterValue, 20, 3, 0, // Skip to: 1240
+/* 1237 */    MCD_OPC_Decode, 38, 23, // Opcode: ADDK_s2_ir
+/* 1240 */    MCD_OPC_FilterValue, 21, 19, 0, // Skip to: 1263
+/* 1244 */    MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
+/* 1247 */    MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1255
+/* 1251 */    MCD_OPC_Decode, 235, 1, 3, // Opcode: STH_d5_rm
+/* 1255 */    MCD_OPC_FilterValue, 1, 194, 3, // Skip to: 2221
+/* 1259 */    MCD_OPC_Decode, 238, 1, 3, // Opcode: STNW_d5_rm
+/* 1263 */    MCD_OPC_FilterValue, 22, 191, 0, // Skip to: 1458
+/* 1267 */    MCD_OPC_ExtractField, 7, 5,  // Inst{11-7} ...
+/* 1270 */    MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1277
+/* 1274 */    MCD_OPC_Decode, 46, 2, // Opcode: ADD_l1_irr
+/* 1277 */    MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1285
+/* 1281 */    MCD_OPC_Decode, 131, 2, 2, // Opcode: SUB_l1_irr
+/* 1285 */    MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 1293
+/* 1289 */    MCD_OPC_Decode, 229, 1, 2, // Opcode: SSUB_l1_irr
+/* 1293 */    MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 1301
+/* 1297 */    MCD_OPC_Decode, 187, 1, 2, // Opcode: SADD_l1_irr
+/* 1301 */    MCD_OPC_FilterValue, 6, 49, 0, // Skip to: 1354
+/* 1305 */    MCD_OPC_ExtractField, 13, 5,  // Inst{17-13} ...
+/* 1308 */    MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1315
+/* 1312 */    MCD_OPC_Decode, 24, 21, // Opcode: ABS_l1_rr
+/* 1315 */    MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1323
+/* 1319 */    MCD_OPC_Decode, 139, 2, 21, // Opcode: SWAP4_l2_rr
+/* 1323 */    MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 1331
+/* 1327 */    MCD_OPC_Decode, 142, 2, 21, // Opcode: UNPKLU4_l2_rr
+/* 1331 */    MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 1339
+/* 1335 */    MCD_OPC_Decode, 140, 2, 21, // Opcode: UNPKHU4_l2_rr
+/* 1339 */    MCD_OPC_FilterValue, 4, 3, 0, // Skip to: 1346
+/* 1343 */    MCD_OPC_Decode, 22, 21, // Opcode: ABS2_l2_rr
+/* 1346 */    MCD_OPC_FilterValue, 5, 103, 3, // Skip to: 2221
+/* 1350 */    MCD_OPC_Decode, 161, 1, 31, // Opcode: MVK_l2_ir
+/* 1354 */    MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 1362
+/* 1358 */    MCD_OPC_Decode, 173, 1, 1, // Opcode: PACKH2_l1_rrr_x2
+/* 1362 */    MCD_OPC_FilterValue, 16, 3, 0, // Skip to: 1369
+/* 1366 */    MCD_OPC_Decode, 126, 1, // Opcode: MAX2_l1_rrr_x2
+/* 1369 */    MCD_OPC_FilterValue, 17, 3, 0, // Skip to: 1376
+/* 1373 */    MCD_OPC_Decode, 83, 2, // Opcode: CMPGT_l1_irr
+/* 1376 */    MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 1383
+/* 1380 */    MCD_OPC_Decode, 107, 17, // Opcode: GMPGTU_l1_irr
+/* 1383 */    MCD_OPC_FilterValue, 20, 3, 0, // Skip to: 1390
+/* 1387 */    MCD_OPC_Decode, 77, 2, // Opcode: CMPEQ_l1_irr
+/* 1390 */    MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 1397
+/* 1394 */    MCD_OPC_Decode, 91, 2, // Opcode: CMPLT_l1_irr
+/* 1397 */    MCD_OPC_FilterValue, 22, 4, 0, // Skip to: 1405
+/* 1401 */    MCD_OPC_Decode, 245, 1, 1, // Opcode: SUBABS4_l1_rrr_x2
+/* 1405 */    MCD_OPC_FilterValue, 23, 3, 0, // Skip to: 1412
+/* 1409 */    MCD_OPC_Decode, 87, 17, // Opcode: CMPLTU_l1_irr
+/* 1412 */    MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 1420
+/* 1416 */    MCD_OPC_Decode, 205, 1, 1, // Opcode: SHRMB_l1_rrr_x2
+/* 1420 */    MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 1428
+/* 1424 */    MCD_OPC_Decode, 244, 1, 1, // Opcode: SUB4_l1_rrr_x2
+/* 1428 */    MCD_OPC_FilterValue, 26, 3, 0, // Skip to: 1435
+/* 1432 */    MCD_OPC_Decode, 124, 2, // Opcode: LMBD_l1_irr
+/* 1435 */    MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 1443
+/* 1439 */    MCD_OPC_Decode, 146, 2, 2, // Opcode: XOR_l1_irr
+/* 1443 */    MCD_OPC_FilterValue, 30, 3, 0, // Skip to: 1450
+/* 1447 */    MCD_OPC_Decode, 57, 2, // Opcode: AND_l1_irr
+/* 1450 */    MCD_OPC_FilterValue, 31, 255, 2, // Skip to: 2221
+/* 1454 */    MCD_OPC_Decode, 167, 1, 2, // Opcode: OR_l1_irr
+/* 1458 */    MCD_OPC_FilterValue, 23, 4, 0, // Skip to: 1466
+/* 1462 */    MCD_OPC_Decode, 236, 1, 5, // Opcode: STH_d6_rm
+/* 1466 */    MCD_OPC_FilterValue, 24, 6, 1, // Skip to: 1732
+/* 1470 */    MCD_OPC_ExtractField, 7, 5,  // Inst{11-7} ...
+/* 1473 */    MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1480
+/* 1477 */    MCD_OPC_Decode, 27, 1, // Opcode: ADD2_s1_rrr
+/* 1480 */    MCD_OPC_FilterValue, 1, 19, 0, // Skip to: 1503
+/* 1484 */    MCD_OPC_ExtractField, 12, 16,  // Inst{27-12} ...
+/* 1487 */    MCD_OPC_FilterValue, 128, 3, 3, 0, // Skip to: 1495
+/* 1492 */    MCD_OPC_Decode, 70, 32, // Opcode: B_s7_irp
+/* 1495 */    MCD_OPC_FilterValue, 192, 3, 209, 2, // Skip to: 2221
+/* 1500 */    MCD_OPC_Decode, 71, 32, // Opcode: B_s7_nrp
+/* 1503 */    MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1516
+/* 1507 */    MCD_OPC_CheckField, 12, 1, 0, 196, 2, // Skip to: 2221
+/* 1513 */    MCD_OPC_Decode, 37, 33, // Opcode: ADDKPC_s3_iir
+/* 1516 */    MCD_OPC_FilterValue, 3, 3, 0, // Skip to: 1523
+/* 1520 */    MCD_OPC_Decode, 51, 1, // Opcode: ADD_s1_rrr
+/* 1523 */    MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 1531
+/* 1527 */    MCD_OPC_Decode, 174, 1, 1, // Opcode: PACKH2_s1_rrr
+/* 1531 */    MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 1539
+/* 1535 */    MCD_OPC_Decode, 149, 2, 1, // Opcode: XOR_s1_rrr
+/* 1539 */    MCD_OPC_FilterValue, 6, 29, 0, // Skip to: 1572
+/* 1543 */    MCD_OPC_ExtractField, 23, 5,  // Inst{27-23} ...
+/* 1546 */    MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1559
+/* 1550 */    MCD_OPC_CheckField, 13, 5, 0, 153, 2, // Skip to: 2221
+/* 1556 */    MCD_OPC_Decode, 69, 34, // Opcode: B_s6_r
+/* 1559 */    MCD_OPC_FilterValue, 1, 146, 2, // Skip to: 2221
+/* 1563 */    MCD_OPC_CheckField, 16, 2, 0, 140, 2, // Skip to: 2221
+/* 1569 */    MCD_OPC_Decode, 65, 35, // Opcode: BNOP_s10_ri
+/* 1572 */    MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 1586
+/* 1576 */    MCD_OPC_CheckField, 13, 5, 0, 127, 2, // Skip to: 2221
+/* 1582 */    MCD_OPC_Decode, 155, 1, 36, // Opcode: MVC_s1_rr
+/* 1586 */    MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 1594
+/* 1590 */    MCD_OPC_Decode, 243, 1, 1, // Opcode: SUB2_s1_rrr
+/* 1594 */    MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 1602
+/* 1598 */    MCD_OPC_Decode, 201, 1, 37, // Opcode: SHL_s1_rrp
+/* 1602 */    MCD_OPC_FilterValue, 10, 3, 0, // Skip to: 1609
+/* 1606 */    MCD_OPC_Decode, 81, 1, // Opcode: CMPGTU4_s1_rrr
+/* 1609 */    MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 1617
+/* 1613 */    MCD_OPC_Decode, 137, 2, 1, // Opcode: SUB_s1_rrr
+/* 1617 */    MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 1625
+/* 1621 */    MCD_OPC_Decode, 207, 1, 17, // Opcode: SHRU2_s1_rir
+/* 1625 */    MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 1633
+/* 1629 */    MCD_OPC_Decode, 170, 1, 1, // Opcode: OR_s1_rrr
+/* 1633 */    MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 1640
+/* 1637 */    MCD_OPC_Decode, 74, 1, // Opcode: CMPEQ2_s1_rrr
+/* 1640 */    MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 1647
+/* 1644 */    MCD_OPC_Decode, 60, 1, // Opcode: AND_s1_rrr
+/* 1647 */    MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 1655
+/* 1651 */    MCD_OPC_Decode, 225, 1, 1, // Opcode: SSHL_s1_rrr
+/* 1655 */    MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 1663
+/* 1659 */    MCD_OPC_Decode, 210, 1, 38, // Opcode: SHRU_s1_prp
+/* 1663 */    MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 1671
+/* 1667 */    MCD_OPC_Decode, 212, 1, 1, // Opcode: SHRU_s1_rrr
+/* 1671 */    MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 1678
+/* 1675 */    MCD_OPC_Decode, 103, 1, // Opcode: EXTU_s1_rrr
+/* 1678 */    MCD_OPC_FilterValue, 23, 3, 0, // Skip to: 1685
+/* 1682 */    MCD_OPC_Decode, 105, 1, // Opcode: EXT_s1_rrr
+/* 1685 */    MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 1693
+/* 1689 */    MCD_OPC_Decode, 198, 1, 25, // Opcode: SHL_s1_prp
+/* 1693 */    MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 1701
+/* 1697 */    MCD_OPC_Decode, 202, 1, 39, // Opcode: SHL_s1_rrr
+/* 1701 */    MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 1709
+/* 1705 */    MCD_OPC_Decode, 214, 1, 38, // Opcode: SHR_s1_prp
+/* 1709 */    MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 1717
+/* 1713 */    MCD_OPC_Decode, 216, 1, 1, // Opcode: SHR_s1_rrr
+/* 1717 */    MCD_OPC_FilterValue, 29, 4, 0, // Skip to: 1725
+/* 1721 */    MCD_OPC_Decode, 193, 1, 1, // Opcode: SET_s1_rrr
+/* 1725 */    MCD_OPC_FilterValue, 31, 236, 1, // Skip to: 2221
+/* 1729 */    MCD_OPC_Decode, 73, 1, // Opcode: CLR_s1_rrr
+/* 1732 */    MCD_OPC_FilterValue, 25, 17, 0, // Skip to: 1753
+/* 1736 */    MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
+/* 1739 */    MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1746
+/* 1743 */    MCD_OPC_Decode, 122, 3, // Opcode: LDW_d5_mr
+/* 1746 */    MCD_OPC_FilterValue, 1, 215, 1, // Skip to: 2221
+/* 1750 */    MCD_OPC_Decode, 115, 30, // Opcode: LDDW_d7_mp
+/* 1753 */    MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 1761
+/* 1757 */    MCD_OPC_Decode, 158, 1, 23, // Opcode: MVKLH_s12_ir
+/* 1761 */    MCD_OPC_FilterValue, 27, 3, 0, // Skip to: 1768
+/* 1765 */    MCD_OPC_Decode, 123, 5, // Opcode: LDW_d6_mr
+/* 1768 */    MCD_OPC_FilterValue, 28, 216, 0, // Skip to: 1988
+/* 1772 */    MCD_OPC_ExtractField, 7, 5,  // Inst{11-7} ...
+/* 1775 */    MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1783
+/* 1779 */    MCD_OPC_Decode, 217, 1, 24, // Opcode: SMPY2_m1_rrp
+/* 1783 */    MCD_OPC_FilterValue, 1, 49, 0, // Skip to: 1836
+/* 1787 */    MCD_OPC_ExtractField, 13, 5,  // Inst{17-13} ...
+/* 1790 */    MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 1798
+/* 1794 */    MCD_OPC_Decode, 151, 2, 21, // Opcode: XPND4_m2_rr
+/* 1798 */    MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 1806
+/* 1802 */    MCD_OPC_Decode, 150, 2, 21, // Opcode: XPND2_m2_rr
+/* 1806 */    MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 1814
+/* 1810 */    MCD_OPC_Decode, 157, 1, 21, // Opcode: MVD_m2_rr
+/* 1814 */    MCD_OPC_FilterValue, 28, 4, 0, // Skip to: 1822
+/* 1818 */    MCD_OPC_Decode, 194, 1, 21, // Opcode: SHFL_m2_rr
+/* 1822 */    MCD_OPC_FilterValue, 29, 3, 0, // Skip to: 1829
+/* 1826 */    MCD_OPC_Decode, 94, 21, // Opcode: DEAL_m2_rr
+/* 1829 */    MCD_OPC_FilterValue, 30, 132, 1, // Skip to: 2221
+/* 1833 */    MCD_OPC_Decode, 64, 21, // Opcode: BITC4_m2_rr
+/* 1836 */    MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 1844
+/* 1840 */    MCD_OPC_Decode, 147, 1, 24, // Opcode: MPYSU4_m1_rrp
+/* 1844 */    MCD_OPC_FilterValue, 3, 3, 0, // Skip to: 1851
+/* 1848 */    MCD_OPC_Decode, 98, 1, // Opcode: DOTPNRSU2_m1_rrr
+/* 1851 */    MCD_OPC_FilterValue, 4, 3, 0, // Skip to: 1858
+/* 1855 */    MCD_OPC_Decode, 97, 1, // Opcode: DOTPN2_m1_rrr
+/* 1858 */    MCD_OPC_FilterValue, 5, 3, 0, // Skip to: 1865
+/* 1862 */    MCD_OPC_Decode, 95, 24, // Opcode: DOTP2_m1_rrp
+/* 1865 */    MCD_OPC_FilterValue, 6, 3, 0, // Skip to: 1872
+/* 1869 */    MCD_OPC_Decode, 99, 1, // Opcode: DOTPRSU2_m1_rrr
+/* 1872 */    MCD_OPC_FilterValue, 8, 3, 0, // Skip to: 1879
+/* 1876 */    MCD_OPC_Decode, 110, 1, // Opcode: GMPY4_m1_rrr
+/* 1879 */    MCD_OPC_FilterValue, 9, 3, 0, // Skip to: 1886
+/* 1883 */    MCD_OPC_Decode, 61, 1, // Opcode: AVG2_m1_rrr
+/* 1886 */    MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 1894
+/* 1890 */    MCD_OPC_Decode, 144, 1, 24, // Opcode: MPYLI_m1_rrp
+/* 1894 */    MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 1902
+/* 1898 */    MCD_OPC_Decode, 182, 1, 1, // Opcode: ROTL_m1_rrr
+/* 1902 */    MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 1910
+/* 1906 */    MCD_OPC_Decode, 165, 1, 2, // Opcode: OR_d2_rir
+/* 1910 */    MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 1918
+/* 1914 */    MCD_OPC_Decode, 241, 1, 1, // Opcode: SUB2_d2_rrr
+/* 1918 */    MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 1925
+/* 1922 */    MCD_OPC_Decode, 55, 2, // Opcode: AND_d2_rir
+/* 1925 */    MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 1932
+/* 1929 */    MCD_OPC_Decode, 43, 2, // Opcode: ADD_d2_rir
+/* 1932 */    MCD_OPC_FilterValue, 23, 4, 0, // Skip to: 1940
+/* 1936 */    MCD_OPC_Decode, 144, 2, 2, // Opcode: XOR_d2_rir
+/* 1940 */    MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 1948
+/* 1944 */    MCD_OPC_Decode, 185, 1, 1, // Opcode: SADDUS2_s4_rrr
+/* 1948 */    MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 1956
+/* 1952 */    MCD_OPC_Decode, 184, 1, 1, // Opcode: SADDU4_s4_rrr
+/* 1956 */    MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 1964
+/* 1960 */    MCD_OPC_Decode, 138, 2, 1, // Opcode: SUB_s4_rrr
+/* 1964 */    MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 1972
+/* 1968 */    MCD_OPC_Decode, 204, 1, 1, // Opcode: SHR2_s4_rrr
+/* 1972 */    MCD_OPC_FilterValue, 28, 4, 0, // Skip to: 1980
+/* 1976 */    MCD_OPC_Decode, 196, 1, 1, // Opcode: SHLMB_s4_rrr
+/* 1980 */    MCD_OPC_FilterValue, 31, 237, 0, // Skip to: 2221
+/* 1984 */    MCD_OPC_Decode, 172, 1, 1, // Opcode: PACK2_s4_rrr
+/* 1988 */    MCD_OPC_FilterValue, 29, 19, 0, // Skip to: 2011
+/* 1992 */    MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
+/* 1995 */    MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 2003
+/* 1999 */    MCD_OPC_Decode, 239, 1, 3, // Opcode: STW_d5_rm
+/* 2003 */    MCD_OPC_FilterValue, 1, 214, 0, // Skip to: 2221
+/* 2007 */    MCD_OPC_Decode, 237, 1, 22, // Opcode: STNDW_d8_pm
+/* 2011 */    MCD_OPC_FilterValue, 30, 198, 0, // Skip to: 2213
+/* 2015 */    MCD_OPC_ExtractField, 7, 5,  // Inst{11-7} ...
+/* 2018 */    MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 2025
+/* 2022 */    MCD_OPC_Decode, 49, 1, // Opcode: ADD_l1_rrr_x2
+/* 2025 */    MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 2033
+/* 2029 */    MCD_OPC_Decode, 135, 2, 1, // Opcode: SUB_l1_rrr_x2
+/* 2033 */    MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 2041
+/* 2037 */    MCD_OPC_Decode, 231, 1, 1, // Opcode: SSUB_l1_rrr_x2
+/* 2041 */    MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 2049
+/* 2045 */    MCD_OPC_Decode, 189, 1, 1, // Opcode: SADD_l1_rrr_x2
+/* 2049 */    MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 2057
+/* 2053 */    MCD_OPC_Decode, 134, 2, 39, // Opcode: SUB_l1_rrr_x1
+/* 2057 */    MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 2065
+/* 2061 */    MCD_OPC_Decode, 179, 1, 1, // Opcode: PACKLH2_l1_rrr_x2
+/* 2065 */    MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 2073
+/* 2069 */    MCD_OPC_Decode, 230, 1, 39, // Opcode: SSUB_l1_rrr_x1
+/* 2073 */    MCD_OPC_FilterValue, 8, 3, 0, // Skip to: 2080
+/* 2077 */    MCD_OPC_Decode, 48, 24, // Opcode: ADD_l1_rrp_x2
+/* 2080 */    MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 2088
+/* 2084 */    MCD_OPC_Decode, 133, 2, 24, // Opcode: SUB_l1_rrp_x2
+/* 2088 */    MCD_OPC_FilterValue, 10, 3, 0, // Skip to: 2095
+/* 2092 */    MCD_OPC_Decode, 40, 24, // Opcode: ADDU_l1_rrp_x2
+/* 2095 */    MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 2103
+/* 2099 */    MCD_OPC_Decode, 254, 1, 24, // Opcode: SUBU_l1_rrp_x2
+/* 2103 */    MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 2111
+/* 2107 */    MCD_OPC_Decode, 132, 2, 37, // Opcode: SUB_l1_rrp_x1
+/* 2111 */    MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 2119
+/* 2115 */    MCD_OPC_Decode, 253, 1, 37, // Opcode: SUBU_l1_rrp_x1
+/* 2119 */    MCD_OPC_FilterValue, 16, 3, 0, // Skip to: 2126
+/* 2123 */    MCD_OPC_Decode, 127, 1, // Opcode: MAXU4_l1_rrr_x2
+/* 2126 */    MCD_OPC_FilterValue, 17, 3, 0, // Skip to: 2133
+/* 2130 */    MCD_OPC_Decode, 85, 1, // Opcode: CMPGT_l1_rrr_x2
+/* 2133 */    MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 2141
+/* 2137 */    MCD_OPC_Decode, 252, 1, 1, // Opcode: SUBC_l1_rrr_x2
+/* 2141 */    MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 2148
+/* 2145 */    MCD_OPC_Decode, 109, 1, // Opcode: GMPGTU_l1_rrr_x2
+/* 2148 */    MCD_OPC_FilterValue, 20, 3, 0, // Skip to: 2155
+/* 2152 */    MCD_OPC_Decode, 79, 1, // Opcode: CMPEQ_l1_rrr_x2
+/* 2155 */    MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 2162
+/* 2159 */    MCD_OPC_Decode, 93, 1, // Opcode: CMPLT_l1_rrr_x2
+/* 2162 */    MCD_OPC_FilterValue, 23, 3, 0, // Skip to: 2169
+/* 2166 */    MCD_OPC_Decode, 89, 1, // Opcode: CMPLTU_l1_rrr_x2
+/* 2169 */    MCD_OPC_FilterValue, 24, 10, 0, // Skip to: 2183
+/* 2173 */    MCD_OPC_CheckField, 13, 5, 0, 42, 0, // Skip to: 2221
+/* 2179 */    MCD_OPC_Decode, 164, 1, 21, // Opcode: NORM_l1_rr
+/* 2183 */    MCD_OPC_FilterValue, 26, 3, 0, // Skip to: 2190
+/* 2187 */    MCD_OPC_Decode, 125, 1, // Opcode: LMBD_l1_rrr_x2
+/* 2190 */    MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 2198
+/* 2194 */    MCD_OPC_Decode, 147, 2, 1, // Opcode: XOR_l1_rrr_x2
+/* 2198 */    MCD_OPC_FilterValue, 30, 3, 0, // Skip to: 2205
+/* 2202 */    MCD_OPC_Decode, 58, 1, // Opcode: AND_l1_rrr_x2
+/* 2205 */    MCD_OPC_FilterValue, 31, 12, 0, // Skip to: 2221
+/* 2209 */    MCD_OPC_Decode, 168, 1, 1, // Opcode: OR_l1_rrr_x2
+/* 2213 */    MCD_OPC_FilterValue, 31, 4, 0, // Skip to: 2221
+/* 2217 */    MCD_OPC_Decode, 240, 1, 5, // Opcode: STW_d6_rm
+/* 2221 */    MCD_OPC_Fail,
+  0
+};
+
+static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) {
+  return true;
+}
+
+#define DecodeToMCInst(fname,fieldname, InsnType) \
+static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \
+                                   uint64_t Address, void *Decoder) { \
+  InsnType tmp; \
+  switch (Idx) { \
+  default: \
+  case 0: \
+    tmp = fieldname(insn, 13, 4); \
+    if (DecodeNop(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 1: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 13, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 12, 1); \
+    if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 2: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 13, 5); \
+    if (DecodeScst5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 12, 1); \
+    if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 3: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = 0; \
+    tmp |= fieldname(insn, 7, 1) << 0; \
+    tmp |= fieldname(insn, 9, 14) << 1; \
+    if (DecodeMemOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 4: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 13, 5); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 8, 5); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 5: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 7, 16); \
+    if (DecodeMemOperand2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 6: \
+    tmp = fieldname(insn, 7, 21); \
+    if (DecodePCRelScst21(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 7: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 13, 5); \
+    if (DecodeScst5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 12, 1); \
+    if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 8: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 12, 1); \
+    if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 9: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 12, 1); \
+    if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 10: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 13, 5); \
+    if (DecodeScst5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 12, 1); \
+    if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 11: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 13, 5); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 12, 1); \
+    if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 12: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 12, 1); \
+    if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 13: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 13, 10); \
+    if (DecodePCRelScst10(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 14: \
+    tmp = fieldname(insn, 16, 12); \
+    if (DecodePCRelScst12(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 13, 3); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 15: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeControlRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 12, 1); \
+    if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 16: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 13, 5); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 12, 1); \
+    if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 17: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 13, 5); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 12, 1); \
+    if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 18: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 13, 5); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 12, 1); \
+    if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 19: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 13, 5); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 12, 1); \
+    if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 20: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 13, 5); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 12, 1); \
+    if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 21: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 12, 1); \
+    if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 22: \
+    tmp = fieldname(insn, 24, 4); \
+    if (DecodeRegPair4(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = 0; \
+    tmp |= fieldname(insn, 7, 1) << 0; \
+    tmp |= fieldname(insn, 9, 15) << 1; \
+    if (DecodeMemOperandSc(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 23: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 7, 16); \
+    if (DecodeScst16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 24: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 13, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 12, 1); \
+    if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 25: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 13, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 12, 1); \
+    if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 26: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 13, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 12, 1); \
+    if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 27: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 13, 5); \
+    if (DecodeScst5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 28: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 13, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 29: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 13, 5); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 30: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = 0; \
+    tmp |= fieldname(insn, 7, 1) << 0; \
+    tmp |= fieldname(insn, 9, 14) << 1; \
+    if (DecodeMemOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 31: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeScst5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 12, 1); \
+    if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 32: \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 33: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 16, 7); \
+    if (DecodePCRelScst7(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 13, 3); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 34: \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 12, 1); \
+    if (DecodeCrosspathX1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 35: \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 13, 3); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 12, 1); \
+    if (DecodeCrosspathX1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 36: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeControlRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 12, 1); \
+    if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 37: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 13, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 12, 1); \
+    if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 38: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 13, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 12, 1); \
+    if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 39: \
+    tmp = fieldname(insn, 23, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 18, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 13, 5); \
+    if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 12, 1); \
+    if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 29, 3); \
+    if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 28, 1); \
+    if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 1, 1); \
+    if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 1); \
+    if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  } \
+}
+
+#define DecodeInstruction(fname, fieldname, decoder, InsnType) \
+static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
+                                      InsnType insn, uint64_t Address, \
+                                      MCRegisterInfo *MRI, \
+                                      int feature) { \
+  uint64_t Bits = getFeatureBits(feature); \
+  const uint8_t *Ptr = DecodeTable; \
+  uint32_t CurFieldValue = 0, ExpectedValue; \
+  DecodeStatus S = MCDisassembler_Success; \
+  unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
+  InsnType Val, FieldValue, PositiveMask, NegativeMask; \
+  bool Pred, Fail; \
+  for (;;) { \
+    switch (*Ptr) { \
+    default: \
+      return MCDisassembler_Fail; \
+    case MCD_OPC_ExtractField: { \
+      Start = *++Ptr; \
+      Len = *++Ptr; \
+      ++Ptr; \
+      CurFieldValue = (uint32_t) fieldname(insn, Start, Len); \
+      break; \
+    } \
+    case MCD_OPC_FilterValue: { \
+      Val = (InsnType) decodeULEB128(++Ptr, &Len); \
+      Ptr += Len; \
+      NumToSkip = *Ptr++; \
+      NumToSkip |= (*Ptr++) << 8; \
+      if (Val != CurFieldValue) \
+        Ptr += NumToSkip; \
+      break; \
+    } \
+    case MCD_OPC_CheckField: { \
+      Start = *++Ptr; \
+      Len = *++Ptr; \
+      FieldValue = fieldname(insn, Start, Len); \
+      ExpectedValue = (uint32_t) decodeULEB128(++Ptr, &Len); \
+      Ptr += Len; \
+      NumToSkip = *Ptr++; \
+      NumToSkip |= (*Ptr++) << 8; \
+      if (ExpectedValue != FieldValue) \
+        Ptr += NumToSkip; \
+      break; \
+    } \
+    case MCD_OPC_CheckPredicate: { \
+      PIdx = (uint32_t) decodeULEB128(++Ptr, &Len); \
+      Ptr += Len; \
+      NumToSkip = *Ptr++; \
+      NumToSkip |= (*Ptr++) << 8; \
+      Pred = checkDecoderPredicate(PIdx, Bits); \
+      if (!Pred) \
+        Ptr += NumToSkip; \
+      (void)Pred; \
+      break; \
+    } \
+    case MCD_OPC_Decode: { \
+      Opc = (unsigned) decodeULEB128(++Ptr, &Len); \
+      Ptr += Len; \
+      DecodeIdx = (unsigned) decodeULEB128(Ptr, &Len); \
+      Ptr += Len; \
+      MCInst_setOpcode(MI, Opc); \
+      return decoder(S, DecodeIdx, insn, MI, Address, MRI); \
+    } \
+    case MCD_OPC_SoftFail: { \
+      PositiveMask = (InsnType) decodeULEB128(++Ptr, &Len); \
+      Ptr += Len; \
+      NegativeMask = (InsnType) decodeULEB128(Ptr, &Len); \
+      Ptr += Len; \
+      Fail = (insn & PositiveMask) || (~insn & NegativeMask); \
+      if (Fail) \
+        S = MCDisassembler_SoftFail; \
+      break; \
+    } \
+    case MCD_OPC_Fail: { \
+      return MCDisassembler_Fail; \
+    } \
+    } \
+  } \
+}
+
+FieldFromInstruction(fieldFromInstruction_4, uint32_t)
+DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t)
+DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t)
diff --git a/capstone/arch/TMS320C64x/TMS320C64xGenInstrInfo.inc b/capstone/arch/TMS320C64x/TMS320C64xGenInstrInfo.inc
new file mode 100644
index 000000000..6f2dad87e
--- /dev/null
+++ b/capstone/arch/TMS320C64x/TMS320C64xGenInstrInfo.inc
@@ -0,0 +1,298 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*Target Instruction Enum Values                                              *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_INSTRINFO_ENUM
+#undef GET_INSTRINFO_ENUM
+
+enum {
+  TMS320C64x_PHI	= 0,
+  TMS320C64x_INLINEASM	= 1,
+  TMS320C64x_CFI_INSTRUCTION	= 2,
+  TMS320C64x_EH_LABEL	= 3,
+  TMS320C64x_GC_LABEL	= 4,
+  TMS320C64x_KILL	= 5,
+  TMS320C64x_EXTRACT_SUBREG	= 6,
+  TMS320C64x_INSERT_SUBREG	= 7,
+  TMS320C64x_IMPLICIT_DEF	= 8,
+  TMS320C64x_SUBREG_TO_REG	= 9,
+  TMS320C64x_COPY_TO_REGCLASS	= 10,
+  TMS320C64x_DBG_VALUE	= 11,
+  TMS320C64x_REG_SEQUENCE	= 12,
+  TMS320C64x_COPY	= 13,
+  TMS320C64x_BUNDLE	= 14,
+  TMS320C64x_LIFETIME_START	= 15,
+  TMS320C64x_LIFETIME_END	= 16,
+  TMS320C64x_STACKMAP	= 17,
+  TMS320C64x_PATCHPOINT	= 18,
+  TMS320C64x_LOAD_STACK_GUARD	= 19,
+  TMS320C64x_STATEPOINT	= 20,
+  TMS320C64x_FRAME_ALLOC	= 21,
+  TMS320C64x_ABS2_l2_rr	= 22,
+  TMS320C64x_ABS_l1_pp	= 23,
+  TMS320C64x_ABS_l1_rr	= 24,
+  TMS320C64x_ADD2_d2_rrr	= 25,
+  TMS320C64x_ADD2_l1_rrr_x2	= 26,
+  TMS320C64x_ADD2_s1_rrr	= 27,
+  TMS320C64x_ADD4_l1_rrr_x2	= 28,
+  TMS320C64x_ADDAB_d1_rir	= 29,
+  TMS320C64x_ADDAB_d1_rrr	= 30,
+  TMS320C64x_ADDAD_d1_rir	= 31,
+  TMS320C64x_ADDAD_d1_rrr	= 32,
+  TMS320C64x_ADDAH_d1_rir	= 33,
+  TMS320C64x_ADDAH_d1_rrr	= 34,
+  TMS320C64x_ADDAW_d1_rir	= 35,
+  TMS320C64x_ADDAW_d1_rrr	= 36,
+  TMS320C64x_ADDKPC_s3_iir	= 37,
+  TMS320C64x_ADDK_s2_ir	= 38,
+  TMS320C64x_ADDU_l1_rpp	= 39,
+  TMS320C64x_ADDU_l1_rrp_x2	= 40,
+  TMS320C64x_ADD_d1_rir	= 41,
+  TMS320C64x_ADD_d1_rrr	= 42,
+  TMS320C64x_ADD_d2_rir	= 43,
+  TMS320C64x_ADD_d2_rrr	= 44,
+  TMS320C64x_ADD_l1_ipp	= 45,
+  TMS320C64x_ADD_l1_irr	= 46,
+  TMS320C64x_ADD_l1_rpp	= 47,
+  TMS320C64x_ADD_l1_rrp_x2	= 48,
+  TMS320C64x_ADD_l1_rrr_x2	= 49,
+  TMS320C64x_ADD_s1_irr	= 50,
+  TMS320C64x_ADD_s1_rrr	= 51,
+  TMS320C64x_ANDN_d2_rrr	= 52,
+  TMS320C64x_ANDN_l1_rrr_x2	= 53,
+  TMS320C64x_ANDN_s4_rrr	= 54,
+  TMS320C64x_AND_d2_rir	= 55,
+  TMS320C64x_AND_d2_rrr	= 56,
+  TMS320C64x_AND_l1_irr	= 57,
+  TMS320C64x_AND_l1_rrr_x2	= 58,
+  TMS320C64x_AND_s1_irr	= 59,
+  TMS320C64x_AND_s1_rrr	= 60,
+  TMS320C64x_AVG2_m1_rrr	= 61,
+  TMS320C64x_AVGU4_m1_rrr	= 62,
+  TMS320C64x_BDEC_s8_ir	= 63,
+  TMS320C64x_BITC4_m2_rr	= 64,
+  TMS320C64x_BNOP_s10_ri	= 65,
+  TMS320C64x_BNOP_s9_ii	= 66,
+  TMS320C64x_BPOS_s8_ir	= 67,
+  TMS320C64x_B_s5_i	= 68,
+  TMS320C64x_B_s6_r	= 69,
+  TMS320C64x_B_s7_irp	= 70,
+  TMS320C64x_B_s7_nrp	= 71,
+  TMS320C64x_CLR_s15_riir	= 72,
+  TMS320C64x_CLR_s1_rrr	= 73,
+  TMS320C64x_CMPEQ2_s1_rrr	= 74,
+  TMS320C64x_CMPEQ4_s1_rrr	= 75,
+  TMS320C64x_CMPEQ_l1_ipr	= 76,
+  TMS320C64x_CMPEQ_l1_irr	= 77,
+  TMS320C64x_CMPEQ_l1_rpr	= 78,
+  TMS320C64x_CMPEQ_l1_rrr_x2	= 79,
+  TMS320C64x_CMPGT2_s1_rrr	= 80,
+  TMS320C64x_CMPGTU4_s1_rrr	= 81,
+  TMS320C64x_CMPGT_l1_ipr	= 82,
+  TMS320C64x_CMPGT_l1_irr	= 83,
+  TMS320C64x_CMPGT_l1_rpr	= 84,
+  TMS320C64x_CMPGT_l1_rrr_x2	= 85,
+  TMS320C64x_CMPLTU_l1_ipr	= 86,
+  TMS320C64x_CMPLTU_l1_irr	= 87,
+  TMS320C64x_CMPLTU_l1_rpr	= 88,
+  TMS320C64x_CMPLTU_l1_rrr_x2	= 89,
+  TMS320C64x_CMPLT_l1_ipr	= 90,
+  TMS320C64x_CMPLT_l1_irr	= 91,
+  TMS320C64x_CMPLT_l1_rpr	= 92,
+  TMS320C64x_CMPLT_l1_rrr_x2	= 93,
+  TMS320C64x_DEAL_m2_rr	= 94,
+  TMS320C64x_DOTP2_m1_rrp	= 95,
+  TMS320C64x_DOTP2_m1_rrr	= 96,
+  TMS320C64x_DOTPN2_m1_rrr	= 97,
+  TMS320C64x_DOTPNRSU2_m1_rrr	= 98,
+  TMS320C64x_DOTPRSU2_m1_rrr	= 99,
+  TMS320C64x_DOTPSU4_m1_rrr	= 100,
+  TMS320C64x_DOTPU4_m1_rrr	= 101,
+  TMS320C64x_EXTU_s15_riir	= 102,
+  TMS320C64x_EXTU_s1_rrr	= 103,
+  TMS320C64x_EXT_s15_riir	= 104,
+  TMS320C64x_EXT_s1_rrr	= 105,
+  TMS320C64x_GMPGTU_l1_ipr	= 106,
+  TMS320C64x_GMPGTU_l1_irr	= 107,
+  TMS320C64x_GMPGTU_l1_rpr	= 108,
+  TMS320C64x_GMPGTU_l1_rrr_x2	= 109,
+  TMS320C64x_GMPY4_m1_rrr	= 110,
+  TMS320C64x_LDBU_d5_mr	= 111,
+  TMS320C64x_LDBU_d6_mr	= 112,
+  TMS320C64x_LDB_d5_mr	= 113,
+  TMS320C64x_LDB_d6_mr	= 114,
+  TMS320C64x_LDDW_d7_mp	= 115,
+  TMS320C64x_LDHU_d5_mr	= 116,
+  TMS320C64x_LDHU_d6_mr	= 117,
+  TMS320C64x_LDH_d5_mr	= 118,
+  TMS320C64x_LDH_d6_mr	= 119,
+  TMS320C64x_LDNDW_d8_mp	= 120,
+  TMS320C64x_LDNW_d5_mr	= 121,
+  TMS320C64x_LDW_d5_mr	= 122,
+  TMS320C64x_LDW_d6_mr	= 123,
+  TMS320C64x_LMBD_l1_irr	= 124,
+  TMS320C64x_LMBD_l1_rrr_x2	= 125,
+  TMS320C64x_MAX2_l1_rrr_x2	= 126,
+  TMS320C64x_MAXU4_l1_rrr_x2	= 127,
+  TMS320C64x_MIN2_l1_rrr_x2	= 128,
+  TMS320C64x_MINU4_l1_rrr_x2	= 129,
+  TMS320C64x_MPY2_m1_rrp	= 130,
+  TMS320C64x_MPYHIR_m1_rrr	= 131,
+  TMS320C64x_MPYHI_m1_rrp	= 132,
+  TMS320C64x_MPYHLU_m4_rrr	= 133,
+  TMS320C64x_MPYHL_m4_rrr	= 134,
+  TMS320C64x_MPYHSLU_m4_rrr	= 135,
+  TMS320C64x_MPYHSU_m4_rrr	= 136,
+  TMS320C64x_MPYHULS_m4_rrr	= 137,
+  TMS320C64x_MPYHUS_m4_rrr	= 138,
+  TMS320C64x_MPYHU_m4_rrr	= 139,
+  TMS320C64x_MPYH_m4_rrr	= 140,
+  TMS320C64x_MPYLHU_m4_rrr	= 141,
+  TMS320C64x_MPYLH_m4_rrr	= 142,
+  TMS320C64x_MPYLIR_m1_rrr	= 143,
+  TMS320C64x_MPYLI_m1_rrp	= 144,
+  TMS320C64x_MPYLSHU_m4_rrr	= 145,
+  TMS320C64x_MPYLUHS_m4_rrr	= 146,
+  TMS320C64x_MPYSU4_m1_rrp	= 147,
+  TMS320C64x_MPYSU_m4_irr	= 148,
+  TMS320C64x_MPYSU_m4_rrr	= 149,
+  TMS320C64x_MPYU4_m1_rrp	= 150,
+  TMS320C64x_MPYUS_m4_rrr	= 151,
+  TMS320C64x_MPYU_m4_rrr	= 152,
+  TMS320C64x_MPY_m4_irr	= 153,
+  TMS320C64x_MPY_m4_rrr	= 154,
+  TMS320C64x_MVC_s1_rr	= 155,
+  TMS320C64x_MVC_s1_rr2	= 156,
+  TMS320C64x_MVD_m2_rr	= 157,
+  TMS320C64x_MVKLH_s12_ir	= 158,
+  TMS320C64x_MVKL_s12_ir	= 159,
+  TMS320C64x_MVK_d1_rr	= 160,
+  TMS320C64x_MVK_l2_ir	= 161,
+  TMS320C64x_NOP_n	= 162,
+  TMS320C64x_NORM_l1_pr	= 163,
+  TMS320C64x_NORM_l1_rr	= 164,
+  TMS320C64x_OR_d2_rir	= 165,
+  TMS320C64x_OR_d2_rrr	= 166,
+  TMS320C64x_OR_l1_irr	= 167,
+  TMS320C64x_OR_l1_rrr_x2	= 168,
+  TMS320C64x_OR_s1_irr	= 169,
+  TMS320C64x_OR_s1_rrr	= 170,
+  TMS320C64x_PACK2_l1_rrr_x2	= 171,
+  TMS320C64x_PACK2_s4_rrr	= 172,
+  TMS320C64x_PACKH2_l1_rrr_x2	= 173,
+  TMS320C64x_PACKH2_s1_rrr	= 174,
+  TMS320C64x_PACKH4_l1_rrr_x2	= 175,
+  TMS320C64x_PACKHL2_l1_rrr_x2	= 176,
+  TMS320C64x_PACKHL2_s1_rrr	= 177,
+  TMS320C64x_PACKL4_l1_rrr_x2	= 178,
+  TMS320C64x_PACKLH2_l1_rrr_x2	= 179,
+  TMS320C64x_PACKLH2_s1_rrr	= 180,
+  TMS320C64x_ROTL_m1_rir	= 181,
+  TMS320C64x_ROTL_m1_rrr	= 182,
+  TMS320C64x_SADD2_s4_rrr	= 183,
+  TMS320C64x_SADDU4_s4_rrr	= 184,
+  TMS320C64x_SADDUS2_s4_rrr	= 185,
+  TMS320C64x_SADD_l1_ipp	= 186,
+  TMS320C64x_SADD_l1_irr	= 187,
+  TMS320C64x_SADD_l1_rpp	= 188,
+  TMS320C64x_SADD_l1_rrr_x2	= 189,
+  TMS320C64x_SADD_s1_rrr	= 190,
+  TMS320C64x_SAT_l1_pr	= 191,
+  TMS320C64x_SET_s15_riir	= 192,
+  TMS320C64x_SET_s1_rrr	= 193,
+  TMS320C64x_SHFL_m2_rr	= 194,
+  TMS320C64x_SHLMB_l1_rrr_x2	= 195,
+  TMS320C64x_SHLMB_s4_rrr	= 196,
+  TMS320C64x_SHL_s1_pip	= 197,
+  TMS320C64x_SHL_s1_prp	= 198,
+  TMS320C64x_SHL_s1_rip	= 199,
+  TMS320C64x_SHL_s1_rir	= 200,
+  TMS320C64x_SHL_s1_rrp	= 201,
+  TMS320C64x_SHL_s1_rrr	= 202,
+  TMS320C64x_SHR2_s1_rir	= 203,
+  TMS320C64x_SHR2_s4_rrr	= 204,
+  TMS320C64x_SHRMB_l1_rrr_x2	= 205,
+  TMS320C64x_SHRMB_s4_rrr	= 206,
+  TMS320C64x_SHRU2_s1_rir	= 207,
+  TMS320C64x_SHRU2_s4_rrr	= 208,
+  TMS320C64x_SHRU_s1_pip	= 209,
+  TMS320C64x_SHRU_s1_prp	= 210,
+  TMS320C64x_SHRU_s1_rir	= 211,
+  TMS320C64x_SHRU_s1_rrr	= 212,
+  TMS320C64x_SHR_s1_pip	= 213,
+  TMS320C64x_SHR_s1_prp	= 214,
+  TMS320C64x_SHR_s1_rir	= 215,
+  TMS320C64x_SHR_s1_rrr	= 216,
+  TMS320C64x_SMPY2_m1_rrp	= 217,
+  TMS320C64x_SMPYHL_m4_rrr	= 218,
+  TMS320C64x_SMPYH_m4_rrr	= 219,
+  TMS320C64x_SMPYLH_m4_rrr	= 220,
+  TMS320C64x_SMPY_m4_rrr	= 221,
+  TMS320C64x_SPACK2_s4_rrr	= 222,
+  TMS320C64x_SPACKU4_s4_rrr	= 223,
+  TMS320C64x_SSHL_s1_rir	= 224,
+  TMS320C64x_SSHL_s1_rrr	= 225,
+  TMS320C64x_SSHVL_m1_rrr	= 226,
+  TMS320C64x_SSHVR_m1_rrr	= 227,
+  TMS320C64x_SSUB_l1_ipp	= 228,
+  TMS320C64x_SSUB_l1_irr	= 229,
+  TMS320C64x_SSUB_l1_rrr_x1	= 230,
+  TMS320C64x_SSUB_l1_rrr_x2	= 231,
+  TMS320C64x_STB_d5_rm	= 232,
+  TMS320C64x_STB_d6_rm	= 233,
+  TMS320C64x_STDW_d7_pm	= 234,
+  TMS320C64x_STH_d5_rm	= 235,
+  TMS320C64x_STH_d6_rm	= 236,
+  TMS320C64x_STNDW_d8_pm	= 237,
+  TMS320C64x_STNW_d5_rm	= 238,
+  TMS320C64x_STW_d5_rm	= 239,
+  TMS320C64x_STW_d6_rm	= 240,
+  TMS320C64x_SUB2_d2_rrr	= 241,
+  TMS320C64x_SUB2_l1_rrr_x2	= 242,
+  TMS320C64x_SUB2_s1_rrr	= 243,
+  TMS320C64x_SUB4_l1_rrr_x2	= 244,
+  TMS320C64x_SUBABS4_l1_rrr_x2	= 245,
+  TMS320C64x_SUBAB_d1_rir	= 246,
+  TMS320C64x_SUBAB_d1_rrr	= 247,
+  TMS320C64x_SUBAH_d1_rir	= 248,
+  TMS320C64x_SUBAH_d1_rrr	= 249,
+  TMS320C64x_SUBAW_d1_rir	= 250,
+  TMS320C64x_SUBAW_d1_rrr	= 251,
+  TMS320C64x_SUBC_l1_rrr_x2	= 252,
+  TMS320C64x_SUBU_l1_rrp_x1	= 253,
+  TMS320C64x_SUBU_l1_rrp_x2	= 254,
+  TMS320C64x_SUB_d1_rir	= 255,
+  TMS320C64x_SUB_d1_rrr	= 256,
+  TMS320C64x_SUB_d2_rrr	= 257,
+  TMS320C64x_SUB_l1_ipp	= 258,
+  TMS320C64x_SUB_l1_irr	= 259,
+  TMS320C64x_SUB_l1_rrp_x1	= 260,
+  TMS320C64x_SUB_l1_rrp_x2	= 261,
+  TMS320C64x_SUB_l1_rrr_x1	= 262,
+  TMS320C64x_SUB_l1_rrr_x2	= 263,
+  TMS320C64x_SUB_s1_irr	= 264,
+  TMS320C64x_SUB_s1_rrr	= 265,
+  TMS320C64x_SUB_s4_rrr	= 266,
+  TMS320C64x_SWAP4_l2_rr	= 267,
+  TMS320C64x_UNPKHU4_l2_rr	= 268,
+  TMS320C64x_UNPKHU4_s14_rr	= 269,
+  TMS320C64x_UNPKLU4_l2_rr	= 270,
+  TMS320C64x_UNPKLU4_s14_rr	= 271,
+  TMS320C64x_XOR_d2_rir	= 272,
+  TMS320C64x_XOR_d2_rrr	= 273,
+  TMS320C64x_XOR_l1_irr	= 274,
+  TMS320C64x_XOR_l1_rrr_x2	= 275,
+  TMS320C64x_XOR_s1_irr	= 276,
+  TMS320C64x_XOR_s1_rrr	= 277,
+  TMS320C64x_XPND2_m2_rr	= 278,
+  TMS320C64x_XPND4_m2_rr	= 279,
+  TMS320C64x_INSTRUCTION_LIST_END = 280
+};
+
+#endif // GET_INSTRINFO_ENUM
+
diff --git a/capstone/arch/TMS320C64x/TMS320C64xGenRegisterInfo.inc b/capstone/arch/TMS320C64x/TMS320C64xGenRegisterInfo.inc
new file mode 100644
index 000000000..c095762f3
--- /dev/null
+++ b/capstone/arch/TMS320C64x/TMS320C64xGenRegisterInfo.inc
@@ -0,0 +1,277 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*Target Register Enum Values                                                 *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_REGINFO_ENUM
+#undef GET_REGINFO_ENUM
+
+enum {
+  TMS320C64x_NoRegister,
+  TMS320C64x_AMR = 1,
+  TMS320C64x_CSR = 2,
+  TMS320C64x_DIER = 3,
+  TMS320C64x_DNUM = 4,
+  TMS320C64x_ECR = 5,
+  TMS320C64x_GFPGFR = 6,
+  TMS320C64x_GPLYA = 7,
+  TMS320C64x_GPLYB = 8,
+  TMS320C64x_ICR = 9,
+  TMS320C64x_IER = 10,
+  TMS320C64x_IERR = 11,
+  TMS320C64x_ILC = 12,
+  TMS320C64x_IRP = 13,
+  TMS320C64x_ISR = 14,
+  TMS320C64x_ISTP = 15,
+  TMS320C64x_ITSR = 16,
+  TMS320C64x_NRP = 17,
+  TMS320C64x_NTSR = 18,
+  TMS320C64x_REP = 19,
+  TMS320C64x_RILC = 20,
+  TMS320C64x_SSR = 21,
+  TMS320C64x_TSCH = 22,
+  TMS320C64x_TSCL = 23,
+  TMS320C64x_TSR = 24,
+  TMS320C64x_A0 = 25,
+  TMS320C64x_A1 = 26,
+  TMS320C64x_A2 = 27,
+  TMS320C64x_A3 = 28,
+  TMS320C64x_A4 = 29,
+  TMS320C64x_A5 = 30,
+  TMS320C64x_A6 = 31,
+  TMS320C64x_A7 = 32,
+  TMS320C64x_A8 = 33,
+  TMS320C64x_A9 = 34,
+  TMS320C64x_A10 = 35,
+  TMS320C64x_A11 = 36,
+  TMS320C64x_A12 = 37,
+  TMS320C64x_A13 = 38,
+  TMS320C64x_A14 = 39,
+  TMS320C64x_A15 = 40,
+  TMS320C64x_A16 = 41,
+  TMS320C64x_A17 = 42,
+  TMS320C64x_A18 = 43,
+  TMS320C64x_A19 = 44,
+  TMS320C64x_A20 = 45,
+  TMS320C64x_A21 = 46,
+  TMS320C64x_A22 = 47,
+  TMS320C64x_A23 = 48,
+  TMS320C64x_A24 = 49,
+  TMS320C64x_A25 = 50,
+  TMS320C64x_A26 = 51,
+  TMS320C64x_A27 = 52,
+  TMS320C64x_A28 = 53,
+  TMS320C64x_A29 = 54,
+  TMS320C64x_A30 = 55,
+  TMS320C64x_A31 = 56,
+  TMS320C64x_B0 = 57,
+  TMS320C64x_B1 = 58,
+  TMS320C64x_B2 = 59,
+  TMS320C64x_B3 = 60,
+  TMS320C64x_B4 = 61,
+  TMS320C64x_B5 = 62,
+  TMS320C64x_B6 = 63,
+  TMS320C64x_B7 = 64,
+  TMS320C64x_B8 = 65,
+  TMS320C64x_B9 = 66,
+  TMS320C64x_B10 = 67,
+  TMS320C64x_B11 = 68,
+  TMS320C64x_B12 = 69,
+  TMS320C64x_B13 = 70,
+  TMS320C64x_B14 = 71,
+  TMS320C64x_B15 = 72,
+  TMS320C64x_B16 = 73,
+  TMS320C64x_B17 = 74,
+  TMS320C64x_B18 = 75,
+  TMS320C64x_B19 = 76,
+  TMS320C64x_B20 = 77,
+  TMS320C64x_B21 = 78,
+  TMS320C64x_B22 = 79,
+  TMS320C64x_B23 = 80,
+  TMS320C64x_B24 = 81,
+  TMS320C64x_B25 = 82,
+  TMS320C64x_B26 = 83,
+  TMS320C64x_B27 = 84,
+  TMS320C64x_B28 = 85,
+  TMS320C64x_B29 = 86,
+  TMS320C64x_B30 = 87,
+  TMS320C64x_B31 = 88,
+  TMS320C64x_PCE1 = 89,
+  TMS320C64x_NUM_TARGET_REGS 	// 90
+};
+
+// Register classes
+enum {
+  TMS320C64x_GPRegsRegClassID = 0,
+  TMS320C64x_AFRegsRegClassID = 1,
+  TMS320C64x_BFRegsRegClassID = 2,
+  TMS320C64x_ControlRegsRegClassID = 3,
+
+  };
+#endif // GET_REGINFO_ENUM
+
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*MC Register Information                                                     *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_REGINFO_MC_DESC
+#undef GET_REGINFO_MC_DESC
+
+static const MCPhysReg TMS320C64xRegDiffLists[] = {
+  /* 0 */ 65535, 0,
+};
+
+static const uint16_t TMS320C64xSubRegIdxLists[] = {
+  /* 0 */ 0,
+};
+
+static const MCRegisterDesc TMS320C64xRegDesc[] = { // Descriptors
+  { 3, 0, 0, 0, 0 },
+  { 310, 1, 1, 0, 1 },
+  { 319, 1, 1, 0, 1 },
+  { 298, 1, 1, 0, 1 },
+  { 268, 1, 1, 0, 1 },
+  { 290, 1, 1, 0, 1 },
+  { 303, 1, 1, 0, 1 },
+  { 241, 1, 1, 0, 1 },
+  { 247, 1, 1, 0, 1 },
+  { 294, 1, 1, 0, 1 },
+  { 299, 1, 1, 0, 1 },
+  { 314, 1, 1, 0, 1 },
+  { 254, 1, 1, 0, 1 },
+  { 277, 1, 1, 0, 1 },
+  { 323, 1, 1, 0, 1 },
+  { 285, 1, 1, 0, 1 },
+  { 331, 1, 1, 0, 1 },
+  { 281, 1, 1, 0, 1 },
+  { 336, 1, 1, 0, 1 },
+  { 273, 1, 1, 0, 1 },
+  { 253, 1, 1, 0, 1 },
+  { 327, 1, 1, 0, 1 },
+  { 258, 1, 1, 0, 1 },
+  { 263, 1, 1, 0, 1 },
+  { 332, 1, 1, 0, 1 },
+  { 24, 1, 1, 0, 1 },
+  { 54, 1, 1, 0, 1 },
+  { 81, 1, 1, 0, 1 },
+  { 103, 1, 1, 0, 1 },
+  { 125, 1, 1, 0, 1 },
+  { 147, 1, 1, 0, 1 },
+  { 169, 1, 1, 0, 1 },
+  { 191, 1, 1, 0, 1 },
+  { 213, 1, 1, 0, 1 },
+  { 235, 1, 1, 0, 1 },
+  { 0, 1, 1, 0, 1 },
+  { 30, 1, 1, 0, 1 },
+  { 65, 1, 1, 0, 1 },
+  { 87, 1, 1, 0, 1 },
+  { 109, 1, 1, 0, 1 },
+  { 131, 1, 1, 0, 1 },
+  { 153, 1, 1, 0, 1 },
+  { 175, 1, 1, 0, 1 },
+  { 197, 1, 1, 0, 1 },
+  { 219, 1, 1, 0, 1 },
+  { 8, 1, 1, 0, 1 },
+  { 38, 1, 1, 0, 1 },
+  { 73, 1, 1, 0, 1 },
+  { 95, 1, 1, 0, 1 },
+  { 117, 1, 1, 0, 1 },
+  { 139, 1, 1, 0, 1 },
+  { 161, 1, 1, 0, 1 },
+  { 183, 1, 1, 0, 1 },
+  { 205, 1, 1, 0, 1 },
+  { 227, 1, 1, 0, 1 },
+  { 16, 1, 1, 0, 1 },
+  { 46, 1, 1, 0, 1 },
+  { 27, 1, 1, 0, 1 },
+  { 57, 1, 1, 0, 1 },
+  { 84, 1, 1, 0, 1 },
+  { 106, 1, 1, 0, 1 },
+  { 128, 1, 1, 0, 1 },
+  { 150, 1, 1, 0, 1 },
+  { 172, 1, 1, 0, 1 },
+  { 194, 1, 1, 0, 1 },
+  { 216, 1, 1, 0, 1 },
+  { 238, 1, 1, 0, 1 },
+  { 4, 1, 1, 0, 1 },
+  { 34, 1, 1, 0, 1 },
+  { 69, 1, 1, 0, 1 },
+  { 91, 1, 1, 0, 1 },
+  { 113, 1, 1, 0, 1 },
+  { 135, 1, 1, 0, 1 },
+  { 157, 1, 1, 0, 1 },
+  { 179, 1, 1, 0, 1 },
+  { 201, 1, 1, 0, 1 },
+  { 223, 1, 1, 0, 1 },
+  { 12, 1, 1, 0, 1 },
+  { 42, 1, 1, 0, 1 },
+  { 77, 1, 1, 0, 1 },
+  { 99, 1, 1, 0, 1 },
+  { 121, 1, 1, 0, 1 },
+  { 143, 1, 1, 0, 1 },
+  { 165, 1, 1, 0, 1 },
+  { 187, 1, 1, 0, 1 },
+  { 209, 1, 1, 0, 1 },
+  { 231, 1, 1, 0, 1 },
+  { 20, 1, 1, 0, 1 },
+  { 50, 1, 1, 0, 1 },
+  { 60, 1, 1, 0, 1 },
+};
+
+// GPRegs Register Class...
+static const MCPhysReg GPRegs[] = {
+  TMS320C64x_A0, TMS320C64x_A1, TMS320C64x_A2, TMS320C64x_A3, TMS320C64x_A4, TMS320C64x_A5, TMS320C64x_A6, TMS320C64x_A7, TMS320C64x_A8, TMS320C64x_A9, TMS320C64x_A10, TMS320C64x_A11, TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15, TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19, TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23, TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27, TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31, TMS320C64x_B0, TMS320C64x_B1, TMS320C64x_B2, TMS320C64x_B3, TMS320C64x_B4, TMS320C64x_B5, TMS320C64x_B6, TMS320C64x_B7, TMS320C64x_B8, TMS320C64x_B9, TMS320C64x_B10, TMS320C64x_B11, TMS320C64x_B12, TMS320C64x_B13, TMS320C64x_B14, TMS320C64x_B15, TMS320C64x_B16, TMS320C64x_B17, TMS320C64x_B18, TMS320C64x_B19, TMS320C64x_B20, TMS320C64x_B21, TMS320C64x_B22, TMS320C64x_B23, TMS320C64x_B24, TMS320C64x_B25, TMS320C64x_B26, TMS320C64x_B27, TMS320C64x_B28, TMS320C64x_B29, TMS320C64x_B30, TMS320C64x_B31,
+};
+
+// GPRegs Bit set.
+static const uint8_t GPRegsBits[] = {
+  0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01,
+};
+
+// AFRegs Register Class...
+static const MCPhysReg AFRegs[] = {
+  TMS320C64x_A0, TMS320C64x_A1, TMS320C64x_A2, TMS320C64x_A3, TMS320C64x_A4, TMS320C64x_A5, TMS320C64x_A6, TMS320C64x_A7, TMS320C64x_A8, TMS320C64x_A9, TMS320C64x_A10, TMS320C64x_A11, TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15, TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19, TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23, TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27, TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31,
+};
+
+// AFRegs Bit set.
+static const uint8_t AFRegsBits[] = {
+  0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
+};
+
+// BFRegs Register Class...
+static const MCPhysReg BFRegs[] = {
+  TMS320C64x_B0, TMS320C64x_B1, TMS320C64x_B2, TMS320C64x_B3, TMS320C64x_B4, TMS320C64x_B5, TMS320C64x_B6, TMS320C64x_B7, TMS320C64x_B8, TMS320C64x_B9, TMS320C64x_B10, TMS320C64x_B11, TMS320C64x_B12, TMS320C64x_B13, TMS320C64x_B14, TMS320C64x_B15, TMS320C64x_B16, TMS320C64x_B17, TMS320C64x_B18, TMS320C64x_B19, TMS320C64x_B20, TMS320C64x_B21, TMS320C64x_B22, TMS320C64x_B23, TMS320C64x_B24, TMS320C64x_B25, TMS320C64x_B26, TMS320C64x_B27, TMS320C64x_B28, TMS320C64x_B29, TMS320C64x_B30, TMS320C64x_B31,
+};
+
+// BFRegs Bit set.
+static const uint8_t BFRegsBits[] = {
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
+};
+
+// ControlRegs Register Class...
+static const MCPhysReg ControlRegs[] = {
+  TMS320C64x_AMR, TMS320C64x_CSR, TMS320C64x_DIER, TMS320C64x_DNUM, TMS320C64x_ECR, TMS320C64x_GFPGFR, TMS320C64x_GPLYA, TMS320C64x_GPLYB, TMS320C64x_ICR, TMS320C64x_IER, TMS320C64x_IERR, TMS320C64x_ILC, TMS320C64x_IRP, TMS320C64x_ISR, TMS320C64x_ISTP, TMS320C64x_ITSR, TMS320C64x_NRP, TMS320C64x_NTSR, TMS320C64x_PCE1, TMS320C64x_REP, TMS320C64x_RILC, TMS320C64x_SSR, TMS320C64x_TSCH, TMS320C64x_TSCL, TMS320C64x_TSR,
+};
+
+// ControlRegs Bit set.
+static const uint8_t ControlRegsBits[] = {
+  0xfe, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+};
+
+static const MCRegisterClass TMS320C64xMCRegisterClasses[] = {
+  { GPRegs, GPRegsBits, TMS320C64x_GPRegsRegClassID },
+  { AFRegs, AFRegsBits, TMS320C64x_AFRegsRegClassID },
+  { BFRegs, BFRegsBits, TMS320C64x_BFRegsRegClassID },
+  { ControlRegs, ControlRegsBits, TMS320C64x_ControlRegsRegClassID },
+};
+
+#endif // GET_REGINFO_MC_DESC
diff --git a/capstone/arch/TMS320C64x/TMS320C64xInstPrinter.c b/capstone/arch/TMS320C64x/TMS320C64xInstPrinter.c
new file mode 100644
index 000000000..46bdbe7c4
--- /dev/null
+++ b/capstone/arch/TMS320C64x/TMS320C64xInstPrinter.c
@@ -0,0 +1,572 @@
+/* Capstone Disassembly Engine */
+/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
+
+#ifdef CAPSTONE_HAS_TMS320C64X
+
+#ifdef _MSC_VER
+// Disable security warnings for strcpy
+#ifndef _CRT_SECURE_NO_WARNINGS
+#define _CRT_SECURE_NO_WARNINGS
+#endif
+
+// Banned API Usage : strcpy is a Banned API as listed in dontuse.h for
+// security purposes.
+#pragma warning(disable:28719)
+#endif
+
+#include <ctype.h>
+#include <string.h>
+
+#include "TMS320C64xInstPrinter.h"
+#include "../../MCInst.h"
+#include "../../utils.h"
+#include "../../SStream.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MathExtras.h"
+#include "TMS320C64xMapping.h"
+
+#include "capstone/tms320c64x.h"
+
+static const char *getRegisterName(unsigned RegNo);
+static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
+static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O);
+static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O);
+static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O);
+
+void TMS320C64x_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
+{
+	SStream ss;
+	char *p, *p2, tmp[8];
+	unsigned int unit = 0;
+	int i;
+	cs_tms320c64x *tms320c64x;
+
+	if (mci->csh->detail) {
+		tms320c64x = &mci->flat_insn->detail->tms320c64x;
+
+		for (i = 0; i < insn->detail->groups_count; i++) {
+			switch(insn->detail->groups[i]) {
+				case TMS320C64X_GRP_FUNIT_D:
+					unit = TMS320C64X_FUNIT_D;
+					break;
+				case TMS320C64X_GRP_FUNIT_L:
+					unit = TMS320C64X_FUNIT_L;
+					break;
+				case TMS320C64X_GRP_FUNIT_M:
+					unit = TMS320C64X_FUNIT_M;
+					break;
+				case TMS320C64X_GRP_FUNIT_S:
+					unit = TMS320C64X_FUNIT_S;
+					break;
+				case TMS320C64X_GRP_FUNIT_NO:
+					unit = TMS320C64X_FUNIT_NO;
+					break;
+			}
+			if (unit != 0)
+				break;
+		}
+		tms320c64x->funit.unit = unit;
+
+		SStream_Init(&ss);
+		if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID)
+			SStream_concat(&ss, "[%c%s]|", (tms320c64x->condition.zero == 1) ? '!' : '|', cs_reg_name(ud, tms320c64x->condition.reg));
+
+		p = strchr(insn_asm, '\t');
+		if (p != NULL)
+			*p++ = '\0';
+
+		SStream_concat0(&ss, insn_asm);
+		if ((p != NULL) && (((p2 = strchr(p, '[')) != NULL) || ((p2 = strchr(p, '(')) != NULL))) {
+			while ((p2 > p) && ((*p2 != 'a') && (*p2 != 'b')))
+				p2--;
+			if (p2 == p) {
+				strcpy(insn_asm, "Invalid!");
+				return;
+			}
+			if (*p2 == 'a')
+				strcpy(tmp, "1T");
+			else
+				strcpy(tmp, "2T");
+		} else {
+			tmp[0] = '\0';
+		}
+		switch(tms320c64x->funit.unit) {
+			case TMS320C64X_FUNIT_D:
+				SStream_concat(&ss, ".D%s%u", tmp, tms320c64x->funit.side);
+				break;
+			case TMS320C64X_FUNIT_L:
+				SStream_concat(&ss, ".L%s%u", tmp, tms320c64x->funit.side);
+				break;
+			case TMS320C64X_FUNIT_M:
+				SStream_concat(&ss, ".M%s%u", tmp, tms320c64x->funit.side);
+				break;
+			case TMS320C64X_FUNIT_S:
+				SStream_concat(&ss, ".S%s%u", tmp, tms320c64x->funit.side);
+				break;
+		}
+		if (tms320c64x->funit.crosspath > 0)
+			SStream_concat0(&ss, "X");
+
+		if (p != NULL)
+			SStream_concat(&ss, "\t%s", p);
+
+		if (tms320c64x->parallel != 0)
+			SStream_concat(&ss, "\t||");
+
+		/* insn_asm is a buffer from an SStream, so there should be enough space */
+		strcpy(insn_asm, ss.buffer);
+	}
+}
+
+#define PRINT_ALIAS_INSTR
+#include "TMS320C64xGenAsmWriter.inc"
+
+#define GET_INSTRINFO_ENUM
+#include "TMS320C64xGenInstrInfo.inc"
+
+static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	MCOperand *Op = MCInst_getOperand(MI, OpNo);
+	unsigned reg;
+
+	if (MCOperand_isReg(Op)) {
+		reg = MCOperand_getReg(Op);
+		if ((MCInst_getOpcode(MI) == TMS320C64x_MVC_s1_rr) && (OpNo == 1)) {
+			switch(reg) {
+				case TMS320C64X_REG_EFR:
+					SStream_concat0(O, "EFR");
+					break;
+				case TMS320C64X_REG_IFR:
+					SStream_concat0(O, "IFR");
+					break;
+				default:
+					SStream_concat0(O, getRegisterName(reg));
+					break;
+			}
+		} else {
+			SStream_concat0(O, getRegisterName(reg));
+		}
+
+		if (MI->csh->detail) {
+			MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].type = TMS320C64X_OP_REG;
+			MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].reg = reg;
+			MI->flat_insn->detail->tms320c64x.op_count++;
+		}
+	} else if (MCOperand_isImm(Op)) {
+		int64_t Imm = MCOperand_getImm(Op);
+
+		if (Imm >= 0) {
+			if (Imm > HEX_THRESHOLD)
+				SStream_concat(O, "0x%"PRIx64, Imm);
+			else
+				SStream_concat(O, "%"PRIu64, Imm);
+		} else {
+			if (Imm < -HEX_THRESHOLD)
+				SStream_concat(O, "-0x%"PRIx64, -Imm);
+			else
+				SStream_concat(O, "-%"PRIu64, -Imm);
+		}
+
+		if (MI->csh->detail) {
+			MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].type = TMS320C64X_OP_IMM;
+			MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].imm = Imm;
+			MI->flat_insn->detail->tms320c64x.op_count++;
+		}
+	}
+}
+
+static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	MCOperand *Op = MCInst_getOperand(MI, OpNo);
+	int64_t Val = MCOperand_getImm(Op);
+	unsigned scaled, base, offset, mode, unit;
+	cs_tms320c64x *tms320c64x;
+	char st, nd;
+
+	scaled = (Val >> 19) & 1;
+	base = (Val >> 12) & 0x7f;
+	offset = (Val >> 5) & 0x7f;
+	mode = (Val >> 1) & 0xf;
+	unit = Val & 1;
+
+	if (scaled) {
+		st = '[';
+		nd = ']';
+	} else {
+		st = '(';
+		nd = ')';
+	}
+
+	switch(mode) {
+		case 0:
+			SStream_concat(O, "*-%s%c%u%c", getRegisterName(base), st, offset, nd);
+			break;
+		case 1:
+			SStream_concat(O, "*+%s%c%u%c", getRegisterName(base), st, offset, nd);
+			break;
+		case 4:
+			SStream_concat(O, "*-%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
+			break;
+		case 5:
+			SStream_concat(O, "*+%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
+			break;
+		case 8:
+			SStream_concat(O, "*--%s%c%u%c", getRegisterName(base), st, offset, nd);
+			break;
+		case 9:
+			SStream_concat(O, "*++%s%c%u%c", getRegisterName(base), st, offset, nd);
+			break;
+		case 10:
+			SStream_concat(O, "*%s--%c%u%c", getRegisterName(base), st, offset, nd);
+			break;
+		case 11:
+			SStream_concat(O, "*%s++%c%u%c", getRegisterName(base), st, offset, nd);
+			break;
+		case 12:
+			SStream_concat(O, "*--%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
+			break;
+		case 13:
+			SStream_concat(O, "*++%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
+			break;
+		case 14:
+			SStream_concat(O, "*%s--%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
+			break;
+		case 15:
+			SStream_concat(O, "*%s++%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
+			break;
+	}
+
+	if (MI->csh->detail) {
+		tms320c64x = &MI->flat_insn->detail->tms320c64x;
+
+		tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_MEM;
+		tms320c64x->operands[tms320c64x->op_count].mem.base = base;
+		tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
+		tms320c64x->operands[tms320c64x->op_count].mem.unit = unit + 1;
+		tms320c64x->operands[tms320c64x->op_count].mem.scaled = scaled;
+		switch(mode) {
+			case 0:
+				tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
+				tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
+				tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
+				break;
+			case 1:
+				tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
+				tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
+				tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
+				break;
+			case 4:
+				tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
+				tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
+				tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
+				break;
+			case 5:
+				tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
+				tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
+				tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
+				break;
+			case 8:
+				tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
+				tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
+				tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
+				break;
+			case 9:
+				tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
+				tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
+				tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
+				break;
+			case 10:
+				tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
+				tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
+				tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
+				break;
+			case 11:
+				tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
+				tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
+				tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
+				break;
+			case 12:
+				tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
+				tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
+				tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
+				break;
+			case 13:
+				tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
+				tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
+				tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
+				break;
+			case 14:
+				tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
+				tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
+				tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
+				break;
+			case 15:
+				tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
+				tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
+				tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
+				break;
+		}
+		tms320c64x->op_count++;
+	}
+}
+
+static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	MCOperand *Op = MCInst_getOperand(MI, OpNo);
+	int64_t Val = MCOperand_getImm(Op);
+	uint16_t offset;
+	unsigned basereg;
+	cs_tms320c64x *tms320c64x;
+
+	basereg = Val & 0x7f;
+	offset = (Val >> 7) & 0x7fff;
+	SStream_concat(O, "*+%s[0x%x]", getRegisterName(basereg), offset);
+
+	if (MI->csh->detail) {
+		tms320c64x = &MI->flat_insn->detail->tms320c64x;
+
+		tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_MEM;
+		tms320c64x->operands[tms320c64x->op_count].mem.base = basereg;
+		tms320c64x->operands[tms320c64x->op_count].mem.unit = 2;
+		tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
+		tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
+		tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
+		tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
+		tms320c64x->op_count++;
+	}
+}
+
+static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O)
+{
+	MCOperand *Op = MCInst_getOperand(MI, OpNo);
+	unsigned reg = MCOperand_getReg(Op);
+	cs_tms320c64x *tms320c64x;
+
+	SStream_concat(O, "%s:%s", getRegisterName(reg + 1), getRegisterName(reg));
+
+	if (MI->csh->detail) {
+		tms320c64x = &MI->flat_insn->detail->tms320c64x;
+
+		tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_REGPAIR;
+		tms320c64x->operands[tms320c64x->op_count].reg = reg;
+		tms320c64x->op_count++;
+	}
+}
+
+static bool printAliasInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
+{
+	unsigned opcode = MCInst_getOpcode(MI);
+	MCOperand *op;
+
+	switch(opcode) {
+		/* ADD.Dx -i, x, y -> SUB.Dx x, i, y */
+		case TMS320C64x_ADD_d2_rir:
+		/* ADD.L -i, x, y -> SUB.L x, i, y */
+		case TMS320C64x_ADD_l1_irr:
+		case TMS320C64x_ADD_l1_ipp:
+		/* ADD.S -i, x, y -> SUB.S x, i, y */
+		case TMS320C64x_ADD_s1_irr:
+			if ((MCInst_getNumOperands(MI) == 3) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+				MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+				(MCOperand_getImm(MCInst_getOperand(MI, 2)) < 0)) {
+
+				MCInst_setOpcodePub(MI, TMS320C64X_INS_SUB);
+				op = MCInst_getOperand(MI, 2);
+				MCOperand_setImm(op, -MCOperand_getImm(op));
+
+				SStream_concat0(O, "SUB\t");
+				printOperand(MI, 1, O);
+				SStream_concat0(O, ", ");
+				printOperand(MI, 2, O);
+				SStream_concat0(O, ", ");
+				printOperand(MI, 0, O);
+
+				return true;
+			}
+			break;
+	}
+	switch(opcode) {
+		/* ADD.D 0, x, y -> MV.D x, y */
+		case TMS320C64x_ADD_d1_rir:
+		/* OR.D x, 0, y -> MV.D x, y */
+		case TMS320C64x_OR_d2_rir:
+		/* ADD.L 0, x, y -> MV.L x, y */
+		case TMS320C64x_ADD_l1_irr:
+		case TMS320C64x_ADD_l1_ipp:
+		/* OR.L 0, x, y -> MV.L x, y */
+		case TMS320C64x_OR_l1_irr:
+		/* ADD.S 0, x, y -> MV.S x, y */
+		case TMS320C64x_ADD_s1_irr:
+		/* OR.S 0, x, y -> MV.S x, y */
+		case TMS320C64x_OR_s1_irr:
+			if ((MCInst_getNumOperands(MI) == 3) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+				MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+				(MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
+
+				MCInst_setOpcodePub(MI, TMS320C64X_INS_MV);
+				MI->size--;
+
+				SStream_concat0(O, "MV\t");
+				printOperand(MI, 1, O);
+				SStream_concat0(O, ", ");
+				printOperand(MI, 0, O);
+
+				return true;
+			}
+			break;
+	}
+	switch(opcode) {
+		/* XOR.D -1, x, y -> NOT.D x, y */
+		case TMS320C64x_XOR_d2_rir:
+		/* XOR.L -1, x, y -> NOT.L x, y */
+		case TMS320C64x_XOR_l1_irr:
+		/* XOR.S -1, x, y -> NOT.S x, y */
+		case TMS320C64x_XOR_s1_irr:
+			if ((MCInst_getNumOperands(MI) == 3) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+				MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+				(MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1)) {
+
+				MCInst_setOpcodePub(MI, TMS320C64X_INS_NOT);
+				MI->size--;
+
+				SStream_concat0(O, "NOT\t");
+				printOperand(MI, 1, O);
+				SStream_concat0(O, ", ");
+				printOperand(MI, 0, O);
+
+				return true;
+			}
+			break;
+	}
+	switch(opcode) {
+		/* MVK.D 0, x -> ZERO.D x */
+		case TMS320C64x_MVK_d1_rr:
+		/* MVK.L 0, x -> ZERO.L x */
+		case TMS320C64x_MVK_l2_ir:
+			if ((MCInst_getNumOperands(MI) == 2) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+				MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
+				(MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0)) {
+
+				MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
+				MI->size--;
+
+				SStream_concat0(O, "ZERO\t");
+				printOperand(MI, 0, O);
+
+				return true;
+			}
+			break;
+	}
+	switch(opcode) {
+		/* SUB.L x, x, y -> ZERO.L y */
+		case TMS320C64x_SUB_l1_rrp_x1:
+		/* SUB.S x, x, y -> ZERO.S y */
+		case TMS320C64x_SUB_s1_rrr:
+			if ((MCInst_getNumOperands(MI) == 3) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+				(MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
+
+				MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
+				MI->size -= 2;
+
+				SStream_concat0(O, "ZERO\t");
+				printOperand(MI, 0, O);
+
+				return true;
+			}
+			break;
+	}
+	switch(opcode) {
+		/* SUB.L 0, x, y -> NEG.L x, y */
+		case TMS320C64x_SUB_l1_irr:
+		case TMS320C64x_SUB_l1_ipp:
+		/* SUB.S 0, x, y -> NEG.S x, y */
+		case TMS320C64x_SUB_s1_irr:
+			if ((MCInst_getNumOperands(MI) == 3) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+				MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
+				(MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
+
+				MCInst_setOpcodePub(MI, TMS320C64X_INS_NEG);
+				MI->size--;
+
+				SStream_concat0(O, "NEG\t");
+				printOperand(MI, 1, O);
+				SStream_concat0(O, ", ");
+				printOperand(MI, 0, O);
+
+				return true;
+			}
+			break;
+	}
+	switch(opcode) {
+		/* PACKLH2.L x, x, y -> SWAP2.L x, y */
+		case TMS320C64x_PACKLH2_l1_rrr_x2:
+		/* PACKLH2.S x, x, y -> SWAP2.S x, y */
+		case TMS320C64x_PACKLH2_s1_rrr:
+			if ((MCInst_getNumOperands(MI) == 3) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
+				MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
+				(MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
+
+				MCInst_setOpcodePub(MI, TMS320C64X_INS_SWAP2);
+				MI->size--;
+
+				SStream_concat0(O, "SWAP2\t");
+				printOperand(MI, 1, O);
+				SStream_concat0(O, ", ");
+				printOperand(MI, 0, O);
+
+				return true;
+			}
+			break;
+	}
+	switch(opcode) {
+		/* NOP 16 -> IDLE */
+		/* NOP 1 -> NOP */
+		case TMS320C64x_NOP_n:
+			if ((MCInst_getNumOperands(MI) == 1) &&
+				MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
+				(MCOperand_getReg(MCInst_getOperand(MI, 0)) == 16)) {
+
+				MCInst_setOpcodePub(MI, TMS320C64X_INS_IDLE);
+				MI->size--;
+
+				SStream_concat0(O, "IDLE");
+
+				return true;
+			}
+			if ((MCInst_getNumOperands(MI) == 1) &&
+				MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
+				(MCOperand_getReg(MCInst_getOperand(MI, 0)) == 1)) {
+
+				MI->size--;
+
+				SStream_concat0(O, "NOP");
+
+				return true;
+			}
+			break;
+	}
+
+	return false;
+}
+
+void TMS320C64x_printInst(MCInst *MI, SStream *O, void *Info)
+{
+	if (!printAliasInstruction(MI, O, Info))
+		printInstruction(MI, O, Info);
+}
+
+#endif
diff --git a/capstone/arch/TMS320C64x/TMS320C64xInstPrinter.h b/capstone/arch/TMS320C64x/TMS320C64xInstPrinter.h
new file mode 100644
index 000000000..3a79139e8
--- /dev/null
+++ b/capstone/arch/TMS320C64x/TMS320C64xInstPrinter.h
@@ -0,0 +1,15 @@
+/* Capstone Disassembly Engine */
+/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
+
+#ifndef CS_TMS320C64XINSTPRINTER_H
+#define CS_TMS320C64XINSTPRINTER_H
+
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+
+void TMS320C64x_printInst(MCInst *MI, SStream *O, void *Info);
+
+void TMS320C64x_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci);
+
+#endif
diff --git a/capstone/arch/TMS320C64x/TMS320C64xMapping.c b/capstone/arch/TMS320C64x/TMS320C64xMapping.c
new file mode 100644
index 000000000..feb3aeab8
--- /dev/null
+++ b/capstone/arch/TMS320C64x/TMS320C64xMapping.c
@@ -0,0 +1,1926 @@
+/* Capstone Disassembly Engine */
+/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
+
+#ifdef CAPSTONE_HAS_TMS320C64X
+
+#include <stdio.h>	// debug
+#include <string.h>
+
+#include "../../utils.h"
+
+#include "TMS320C64xMapping.h"
+
+#define GET_INSTRINFO_ENUM
+#include "TMS320C64xGenInstrInfo.inc"
+
+static const name_map reg_name_maps[] = {
+	{ TMS320C64X_REG_INVALID, NULL },
+
+	{ TMS320C64X_REG_AMR, "amr" },
+	{ TMS320C64X_REG_CSR, "csr" },
+	{ TMS320C64X_REG_DIER, "dier" },
+	{ TMS320C64X_REG_DNUM, "dnum" },
+	{ TMS320C64X_REG_ECR, "ecr" },
+	{ TMS320C64X_REG_GFPGFR, "gfpgfr" },
+	{ TMS320C64X_REG_GPLYA, "gplya" },
+	{ TMS320C64X_REG_GPLYB, "gplyb" },
+	{ TMS320C64X_REG_ICR, "icr" },
+	{ TMS320C64X_REG_IER, "ier" },
+	{ TMS320C64X_REG_IERR, "ierr" },
+	{ TMS320C64X_REG_ILC, "ilc" },
+	{ TMS320C64X_REG_IRP, "irp" },
+	{ TMS320C64X_REG_ISR, "isr" },
+	{ TMS320C64X_REG_ISTP, "istp" },
+	{ TMS320C64X_REG_ITSR, "itsr" },
+	{ TMS320C64X_REG_NRP, "nrp" },
+	{ TMS320C64X_REG_NTSR, "ntsr" },
+	{ TMS320C64X_REG_REP, "rep" },
+	{ TMS320C64X_REG_RILC, "rilc" },
+	{ TMS320C64X_REG_SSR, "ssr" },
+	{ TMS320C64X_REG_TSCH, "tsch" },
+	{ TMS320C64X_REG_TSCL, "tscl" },
+	{ TMS320C64X_REG_TSR, "tsr" },
+	{ TMS320C64X_REG_A0, "a0" },
+	{ TMS320C64X_REG_A1, "a1" },
+	{ TMS320C64X_REG_A2, "a2" },
+	{ TMS320C64X_REG_A3, "a3" },
+	{ TMS320C64X_REG_A4, "a4" },
+	{ TMS320C64X_REG_A5, "a5" },
+	{ TMS320C64X_REG_A6, "a6" },
+	{ TMS320C64X_REG_A7, "a7" },
+	{ TMS320C64X_REG_A8, "a8" },
+	{ TMS320C64X_REG_A9, "a9" },
+	{ TMS320C64X_REG_A10, "a10" },
+	{ TMS320C64X_REG_A11, "a11" },
+	{ TMS320C64X_REG_A12, "a12" },
+	{ TMS320C64X_REG_A13, "a13" },
+	{ TMS320C64X_REG_A14, "a14" },
+	{ TMS320C64X_REG_A15, "a15" },
+	{ TMS320C64X_REG_A16, "a16" },
+	{ TMS320C64X_REG_A17, "a17" },
+	{ TMS320C64X_REG_A18, "a18" },
+	{ TMS320C64X_REG_A19, "a19" },
+	{ TMS320C64X_REG_A20, "a20" },
+	{ TMS320C64X_REG_A21, "a21" },
+	{ TMS320C64X_REG_A22, "a22" },
+	{ TMS320C64X_REG_A23, "a23" },
+	{ TMS320C64X_REG_A24, "a24" },
+	{ TMS320C64X_REG_A25, "a25" },
+	{ TMS320C64X_REG_A26, "a26" },
+	{ TMS320C64X_REG_A27, "a27" },
+	{ TMS320C64X_REG_A28, "a28" },
+	{ TMS320C64X_REG_A29, "a29" },
+	{ TMS320C64X_REG_A30, "a30" },
+	{ TMS320C64X_REG_A31, "a31" },
+	{ TMS320C64X_REG_B0, "b0" },
+	{ TMS320C64X_REG_B1, "b1" },
+	{ TMS320C64X_REG_B2, "b2" },
+	{ TMS320C64X_REG_B3, "b3" },
+	{ TMS320C64X_REG_B4, "b4" },
+	{ TMS320C64X_REG_B5, "b5" },
+	{ TMS320C64X_REG_B6, "b6" },
+	{ TMS320C64X_REG_B7, "b7" },
+	{ TMS320C64X_REG_B8, "b8" },
+	{ TMS320C64X_REG_B9, "b9" },
+	{ TMS320C64X_REG_B10, "b10" },
+	{ TMS320C64X_REG_B11, "b11" },
+	{ TMS320C64X_REG_B12, "b12" },
+	{ TMS320C64X_REG_B13, "b13" },
+	{ TMS320C64X_REG_B14, "b14" },
+	{ TMS320C64X_REG_B15, "b15" },
+	{ TMS320C64X_REG_B16, "b16" },
+	{ TMS320C64X_REG_B17, "b17" },
+	{ TMS320C64X_REG_B18, "b18" },
+	{ TMS320C64X_REG_B19, "b19" },
+	{ TMS320C64X_REG_B20, "b20" },
+	{ TMS320C64X_REG_B21, "b21" },
+	{ TMS320C64X_REG_B22, "b22" },
+	{ TMS320C64X_REG_B23, "b23" },
+	{ TMS320C64X_REG_B24, "b24" },
+	{ TMS320C64X_REG_B25, "b25" },
+	{ TMS320C64X_REG_B26, "b26" },
+	{ TMS320C64X_REG_B27, "b27" },
+	{ TMS320C64X_REG_B28, "b28" },
+	{ TMS320C64X_REG_B29, "b29" },
+	{ TMS320C64X_REG_B30, "b30" },
+	{ TMS320C64X_REG_B31, "b31" },
+	{ TMS320C64X_REG_PCE1, "pce1" },
+};
+
+const char *TMS320C64x_reg_name(csh handle, unsigned int reg)
+{
+#ifndef CAPSTONE_DIET
+	if (reg >= ARR_SIZE(reg_name_maps))
+		return NULL;
+
+	return reg_name_maps[reg].name;
+#else
+	return NULL;
+#endif
+}
+
+tms320c64x_reg TMS320C64x_reg_id(char *name)
+{
+	int i;
+
+	for(i = 1; i < ARR_SIZE(reg_name_maps); i++) {
+		if (!strcmp(name, reg_name_maps[i].name))
+			return reg_name_maps[i].id;
+	}
+
+	return 0;
+}
+
+static const insn_map insns[] = {
+	{
+		0, 0,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+	},
+
+	{
+		TMS320C64x_ABS2_l2_rr, TMS320C64X_INS_ABS2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ABS_l1_pp, TMS320C64X_INS_ABS,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ABS_l1_rr, TMS320C64X_INS_ABS,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADD2_d2_rrr, TMS320C64X_INS_ADD2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADD2_l1_rrr_x2, TMS320C64X_INS_ADD2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADD2_s1_rrr, TMS320C64X_INS_ADD2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADD4_l1_rrr_x2, TMS320C64X_INS_ADD4,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADDAB_d1_rir, TMS320C64X_INS_ADDAB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADDAB_d1_rrr, TMS320C64X_INS_ADDAB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADDAD_d1_rir, TMS320C64X_INS_ADDAD,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADDAD_d1_rrr, TMS320C64X_INS_ADDAD,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADDAH_d1_rir, TMS320C64X_INS_ADDAH,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADDAH_d1_rrr, TMS320C64X_INS_ADDAH,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADDAW_d1_rir, TMS320C64X_INS_ADDAW,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADDAW_d1_rrr, TMS320C64X_INS_ADDAW,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADDKPC_s3_iir, TMS320C64X_INS_ADDKPC,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADDK_s2_ir, TMS320C64X_INS_ADDK,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADDU_l1_rpp, TMS320C64X_INS_ADDU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADDU_l1_rrp_x2, TMS320C64X_INS_ADDU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADD_d1_rir, TMS320C64X_INS_ADD,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADD_d1_rrr, TMS320C64X_INS_ADD,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADD_d2_rir, TMS320C64X_INS_ADD,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADD_d2_rrr, TMS320C64X_INS_ADD,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADD_l1_ipp, TMS320C64X_INS_ADD,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADD_l1_irr, TMS320C64X_INS_ADD,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADD_l1_rpp, TMS320C64X_INS_ADD,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADD_l1_rrp_x2, TMS320C64X_INS_ADD,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADD_l1_rrr_x2, TMS320C64X_INS_ADD,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADD_s1_irr, TMS320C64X_INS_ADD,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ADD_s1_rrr, TMS320C64X_INS_ADD,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ANDN_d2_rrr, TMS320C64X_INS_ANDN,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ANDN_l1_rrr_x2, TMS320C64X_INS_ANDN,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ANDN_s4_rrr, TMS320C64X_INS_ANDN,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_AND_d2_rir, TMS320C64X_INS_AND,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_AND_d2_rrr, TMS320C64X_INS_AND,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_AND_l1_irr, TMS320C64X_INS_AND,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_AND_l1_rrr_x2, TMS320C64X_INS_AND,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_AND_s1_irr, TMS320C64X_INS_AND,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_AND_s1_rrr, TMS320C64X_INS_AND,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_AVG2_m1_rrr, TMS320C64X_INS_AVG2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_AVGU4_m1_rrr, TMS320C64X_INS_AVGU4,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_BDEC_s8_ir, TMS320C64X_INS_BDEC,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0
+#endif
+	},
+	{
+		TMS320C64x_BITC4_m2_rr, TMS320C64X_INS_BITC4,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_BNOP_s10_ri, TMS320C64X_INS_BNOP,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0
+#endif
+	},
+	{
+		TMS320C64x_BNOP_s9_ii, TMS320C64X_INS_BNOP,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0
+#endif
+	},
+	{
+		TMS320C64x_BPOS_s8_ir, TMS320C64X_INS_BPOS,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0
+#endif
+	},
+	{
+		TMS320C64x_B_s5_i, TMS320C64X_INS_B,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0
+#endif
+	},
+	{
+		TMS320C64x_B_s6_r, TMS320C64X_INS_B,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0
+#endif
+	},
+	{
+		TMS320C64x_B_s7_irp, TMS320C64X_INS_B,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0
+#endif
+	},
+	{
+		TMS320C64x_B_s7_nrp, TMS320C64X_INS_B,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0
+#endif
+	},
+	{
+		TMS320C64x_CLR_s15_riir, TMS320C64X_INS_CLR,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_CLR_s1_rrr, TMS320C64X_INS_CLR,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_CMPEQ2_s1_rrr, TMS320C64X_INS_CMPEQ2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_CMPEQ4_s1_rrr, TMS320C64X_INS_CMPEQ4,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_CMPEQ_l1_ipr, TMS320C64X_INS_CMPEQ,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_CMPEQ_l1_irr, TMS320C64X_INS_CMPEQ,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_CMPEQ_l1_rpr, TMS320C64X_INS_CMPEQ,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_CMPEQ_l1_rrr_x2, TMS320C64X_INS_CMPEQ,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_CMPGT2_s1_rrr, TMS320C64X_INS_CMPGT2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_CMPGTU4_s1_rrr, TMS320C64X_INS_CMPGTU4,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_CMPGT_l1_ipr, TMS320C64X_INS_CMPGT,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_CMPGT_l1_irr, TMS320C64X_INS_CMPGT,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_CMPGT_l1_rpr, TMS320C64X_INS_CMPGT,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_CMPGT_l1_rrr_x2, TMS320C64X_INS_CMPGT,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_CMPLTU_l1_ipr, TMS320C64X_INS_CMPLTU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_CMPLTU_l1_irr, TMS320C64X_INS_CMPLTU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_CMPLTU_l1_rpr, TMS320C64X_INS_CMPLTU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_CMPLTU_l1_rrr_x2, TMS320C64X_INS_CMPLTU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_CMPLT_l1_ipr, TMS320C64X_INS_CMPLT,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_CMPLT_l1_irr, TMS320C64X_INS_CMPLT,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_CMPLT_l1_rpr, TMS320C64X_INS_CMPLT,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_CMPLT_l1_rrr_x2, TMS320C64X_INS_CMPLT,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_DEAL_m2_rr, TMS320C64X_INS_DEAL,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_DOTP2_m1_rrp, TMS320C64X_INS_DOTP2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_DOTP2_m1_rrr, TMS320C64X_INS_DOTP2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_DOTPN2_m1_rrr, TMS320C64X_INS_DOTPN2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_DOTPNRSU2_m1_rrr, TMS320C64X_INS_DOTPNRSU2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_DOTPRSU2_m1_rrr, TMS320C64X_INS_DOTPRSU2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_DOTPSU4_m1_rrr, TMS320C64X_INS_DOTPSU4,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_DOTPU4_m1_rrr, TMS320C64X_INS_DOTPU4,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_EXTU_s15_riir, TMS320C64X_INS_EXTU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_EXTU_s1_rrr, TMS320C64X_INS_EXTU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_EXT_s15_riir, TMS320C64X_INS_EXT,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_EXT_s1_rrr, TMS320C64X_INS_EXT,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_GMPGTU_l1_ipr, TMS320C64X_INS_GMPGTU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_GMPGTU_l1_irr, TMS320C64X_INS_GMPGTU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_GMPGTU_l1_rpr, TMS320C64X_INS_GMPGTU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_GMPGTU_l1_rrr_x2, TMS320C64X_INS_GMPGTU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_GMPY4_m1_rrr, TMS320C64X_INS_GMPY4,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_LDBU_d5_mr, TMS320C64X_INS_LDBU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_LDBU_d6_mr, TMS320C64X_INS_LDBU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_LDB_d5_mr, TMS320C64X_INS_LDB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_LDB_d6_mr, TMS320C64X_INS_LDB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_LDDW_d7_mp, TMS320C64X_INS_LDDW,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_LDHU_d5_mr, TMS320C64X_INS_LDHU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_LDHU_d6_mr, TMS320C64X_INS_LDHU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_LDH_d5_mr, TMS320C64X_INS_LDH,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_LDH_d6_mr, TMS320C64X_INS_LDH,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_LDNDW_d8_mp, TMS320C64X_INS_LDNDW,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_LDNW_d5_mr, TMS320C64X_INS_LDNW,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_LDW_d5_mr, TMS320C64X_INS_LDW,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_LDW_d6_mr, TMS320C64X_INS_LDW,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_LMBD_l1_irr, TMS320C64X_INS_LMBD,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_LMBD_l1_rrr_x2, TMS320C64X_INS_LMBD,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MAX2_l1_rrr_x2, TMS320C64X_INS_MAX2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MAXU4_l1_rrr_x2, TMS320C64X_INS_MAXU4,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MIN2_l1_rrr_x2, TMS320C64X_INS_MIN2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MINU4_l1_rrr_x2, TMS320C64X_INS_MINU4,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MPY2_m1_rrp, TMS320C64X_INS_MPY2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MPYHIR_m1_rrr, TMS320C64X_INS_MPYHIR,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MPYHI_m1_rrp, TMS320C64X_INS_MPYHI,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MPYHLU_m4_rrr, TMS320C64X_INS_MPYHLU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MPYHL_m4_rrr, TMS320C64X_INS_MPYHL,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MPYHSLU_m4_rrr, TMS320C64X_INS_MPYHSLU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MPYHSU_m4_rrr, TMS320C64X_INS_MPYHSU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MPYHULS_m4_rrr, TMS320C64X_INS_MPYHULS,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MPYHUS_m4_rrr, TMS320C64X_INS_MPYHUS,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MPYHU_m4_rrr, TMS320C64X_INS_MPYHU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MPYH_m4_rrr, TMS320C64X_INS_MPYH,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MPYLHU_m4_rrr, TMS320C64X_INS_MPYLHU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MPYLH_m4_rrr, TMS320C64X_INS_MPYLH,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MPYLIR_m1_rrr, TMS320C64X_INS_MPYLIR,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MPYLI_m1_rrp, TMS320C64X_INS_MPYLI,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MPYLSHU_m4_rrr, TMS320C64X_INS_MPYLSHU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MPYLUHS_m4_rrr, TMS320C64X_INS_MPYLUHS,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MPYSU4_m1_rrp, TMS320C64X_INS_MPYSU4,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MPYSU_m4_irr, TMS320C64X_INS_MPYSU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MPYSU_m4_rrr, TMS320C64X_INS_MPYSU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MPYU4_m1_rrp, TMS320C64X_INS_MPYU4,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MPYUS_m4_rrr, TMS320C64X_INS_MPYUS,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MPYU_m4_rrr, TMS320C64X_INS_MPYU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MPY_m4_irr, TMS320C64X_INS_MPY,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MPY_m4_rrr, TMS320C64X_INS_MPY,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MVC_s1_rr, TMS320C64X_INS_MVC,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MVC_s1_rr2, TMS320C64X_INS_MVC,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MVD_m2_rr, TMS320C64X_INS_MVD,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MVKLH_s12_ir, TMS320C64X_INS_MVKLH,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MVKL_s12_ir, TMS320C64X_INS_MVKL,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MVK_d1_rr, TMS320C64X_INS_MVK,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_MVK_l2_ir, TMS320C64X_INS_MVK,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_NOP_n, TMS320C64X_INS_NOP,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_NO, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_NORM_l1_pr, TMS320C64X_INS_NORM,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_NORM_l1_rr, TMS320C64X_INS_NORM,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_OR_d2_rir, TMS320C64X_INS_OR,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_OR_d2_rrr, TMS320C64X_INS_OR,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_OR_l1_irr, TMS320C64X_INS_OR,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_OR_l1_rrr_x2, TMS320C64X_INS_OR,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_OR_s1_irr, TMS320C64X_INS_OR,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_OR_s1_rrr, TMS320C64X_INS_OR,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_PACK2_l1_rrr_x2, TMS320C64X_INS_PACK2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_PACK2_s4_rrr, TMS320C64X_INS_PACK2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_PACKH2_l1_rrr_x2, TMS320C64X_INS_PACKH2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_PACKH2_s1_rrr, TMS320C64X_INS_PACKH2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_PACKH4_l1_rrr_x2, TMS320C64X_INS_PACKH4,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_PACKHL2_l1_rrr_x2, TMS320C64X_INS_PACKHL2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_PACKHL2_s1_rrr, TMS320C64X_INS_PACKHL2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_PACKL4_l1_rrr_x2, TMS320C64X_INS_PACKL4,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_PACKLH2_l1_rrr_x2, TMS320C64X_INS_PACKLH2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_PACKLH2_s1_rrr, TMS320C64X_INS_PACKLH2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ROTL_m1_rir, TMS320C64X_INS_ROTL,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_ROTL_m1_rrr, TMS320C64X_INS_ROTL,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SADD2_s4_rrr, TMS320C64X_INS_SADD2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SADDU4_s4_rrr, TMS320C64X_INS_SADDU4,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SADDUS2_s4_rrr, TMS320C64X_INS_SADDUS2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SADD_l1_ipp, TMS320C64X_INS_SADD,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SADD_l1_irr, TMS320C64X_INS_SADD,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SADD_l1_rpp, TMS320C64X_INS_SADD,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SADD_l1_rrr_x2, TMS320C64X_INS_SADD,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SADD_s1_rrr, TMS320C64X_INS_SADD,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SAT_l1_pr, TMS320C64X_INS_SAT,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SET_s15_riir, TMS320C64X_INS_SET,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SET_s1_rrr, TMS320C64X_INS_SET,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SHFL_m2_rr, TMS320C64X_INS_SHFL,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SHLMB_l1_rrr_x2, TMS320C64X_INS_SHLMB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SHLMB_s4_rrr, TMS320C64X_INS_SHLMB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SHL_s1_pip, TMS320C64X_INS_SHL,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SHL_s1_prp, TMS320C64X_INS_SHL,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SHL_s1_rip, TMS320C64X_INS_SHL,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SHL_s1_rir, TMS320C64X_INS_SHL,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SHL_s1_rrp, TMS320C64X_INS_SHL,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SHL_s1_rrr, TMS320C64X_INS_SHL,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SHR2_s1_rir, TMS320C64X_INS_SHR2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SHR2_s4_rrr, TMS320C64X_INS_SHR2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SHRMB_l1_rrr_x2, TMS320C64X_INS_SHRMB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SHRMB_s4_rrr, TMS320C64X_INS_SHRMB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SHRU2_s1_rir, TMS320C64X_INS_SHRU2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SHRU2_s4_rrr, TMS320C64X_INS_SHRU2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SHRU_s1_pip, TMS320C64X_INS_SHRU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SHRU_s1_prp, TMS320C64X_INS_SHRU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SHRU_s1_rir, TMS320C64X_INS_SHRU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SHRU_s1_rrr, TMS320C64X_INS_SHRU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SHR_s1_pip, TMS320C64X_INS_SHR,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SHR_s1_prp, TMS320C64X_INS_SHR,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SHR_s1_rir, TMS320C64X_INS_SHR,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SHR_s1_rrr, TMS320C64X_INS_SHR,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SMPY2_m1_rrp, TMS320C64X_INS_SMPY2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SMPYHL_m4_rrr, TMS320C64X_INS_SMPYHL,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SMPYH_m4_rrr, TMS320C64X_INS_SMPYH,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SMPYLH_m4_rrr, TMS320C64X_INS_SMPYLH,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SMPY_m4_rrr, TMS320C64X_INS_SMPY,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SPACK2_s4_rrr, TMS320C64X_INS_SPACK2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SPACKU4_s4_rrr, TMS320C64X_INS_SPACKU4,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SSHL_s1_rir, TMS320C64X_INS_SSHL,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SSHL_s1_rrr, TMS320C64X_INS_SSHL,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SSHVL_m1_rrr, TMS320C64X_INS_SSHVL,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SSHVR_m1_rrr, TMS320C64X_INS_SSHVR,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SSUB_l1_ipp, TMS320C64X_INS_SSUB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SSUB_l1_irr, TMS320C64X_INS_SSUB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SSUB_l1_rrr_x1, TMS320C64X_INS_SSUB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SSUB_l1_rrr_x2, TMS320C64X_INS_SSUB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_STB_d5_rm, TMS320C64X_INS_STB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_STB_d6_rm, TMS320C64X_INS_STB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_STDW_d7_pm, TMS320C64X_INS_STDW,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_STH_d5_rm, TMS320C64X_INS_STH,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_STH_d6_rm, TMS320C64X_INS_STH,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_STNDW_d8_pm, TMS320C64X_INS_STNDW,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_STNW_d5_rm, TMS320C64X_INS_STNW,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_STW_d5_rm, TMS320C64X_INS_STW,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_STW_d6_rm, TMS320C64X_INS_STW,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUB2_d2_rrr, TMS320C64X_INS_SUB2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUB2_l1_rrr_x2, TMS320C64X_INS_SUB2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUB2_s1_rrr, TMS320C64X_INS_SUB2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUB4_l1_rrr_x2, TMS320C64X_INS_SUB4,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUBABS4_l1_rrr_x2, TMS320C64X_INS_SUBABS4,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUBAB_d1_rir, TMS320C64X_INS_SUBAB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUBAB_d1_rrr, TMS320C64X_INS_SUBAB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUBAH_d1_rir, TMS320C64X_INS_SUBAH,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUBAH_d1_rrr, TMS320C64X_INS_SUBAH,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUBAW_d1_rir, TMS320C64X_INS_SUBAW,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUBAW_d1_rrr, TMS320C64X_INS_SUBAW,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUBC_l1_rrr_x2, TMS320C64X_INS_SUBC,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUBU_l1_rrp_x1, TMS320C64X_INS_SUBU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUBU_l1_rrp_x2, TMS320C64X_INS_SUBU,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUB_d1_rir, TMS320C64X_INS_SUB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUB_d1_rrr, TMS320C64X_INS_SUB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUB_d2_rrr, TMS320C64X_INS_SUB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUB_l1_ipp, TMS320C64X_INS_SUB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUB_l1_irr, TMS320C64X_INS_SUB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUB_l1_rrp_x1, TMS320C64X_INS_SUB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUB_l1_rrp_x2, TMS320C64X_INS_SUB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUB_l1_rrr_x1, TMS320C64X_INS_SUB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUB_l1_rrr_x2, TMS320C64X_INS_SUB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUB_s1_irr, TMS320C64X_INS_SUB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUB_s1_rrr, TMS320C64X_INS_SUB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SUB_s4_rrr, TMS320C64X_INS_SUB,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_SWAP4_l2_rr, TMS320C64X_INS_SWAP4,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_UNPKHU4_l2_rr, TMS320C64X_INS_UNPKHU4,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_UNPKHU4_s14_rr, TMS320C64X_INS_UNPKHU4,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_UNPKLU4_l2_rr, TMS320C64X_INS_UNPKLU4,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_UNPKLU4_s14_rr, TMS320C64X_INS_UNPKLU4,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_XOR_d2_rir, TMS320C64X_INS_XOR,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_XOR_d2_rrr, TMS320C64X_INS_XOR,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_XOR_l1_irr, TMS320C64X_INS_XOR,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_XOR_l1_rrr_x2, TMS320C64X_INS_XOR,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_XOR_s1_irr, TMS320C64X_INS_XOR,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_XOR_s1_rrr, TMS320C64X_INS_XOR,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_XPND2_m2_rr, TMS320C64X_INS_XPND2,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+	{
+		TMS320C64x_XPND4_m2_rr, TMS320C64X_INS_XPND4,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
+#endif
+	},
+};
+
+void TMS320C64x_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
+{
+	unsigned short i;
+
+	i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
+	if (i != 0) {
+		insn->id = insns[i].mapid;
+
+		if (h->detail) {
+#ifndef CAPSTONE_DIET
+			memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
+			insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
+
+			memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
+			insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
+
+			memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
+			insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups);
+
+			if (insns[i].branch || insns[i].indirect_branch) {
+				insn->detail->groups[insn->detail->groups_count] = TMS320C64X_GRP_JUMP;
+				insn->detail->groups_count++;
+			}
+#endif
+		}
+	}
+}
+
+#ifndef CAPSTONE_DIET
+//grep TMS320C64X_INS include/capstone/tms320c64x.h | awk '{print "{"$1 "\""tolower(substr($1, 16, length($1)-16))"\"""},"}'
+static const name_map insn_name_maps[] = {
+	{TMS320C64X_INS_INVALID, NULL},
+	{TMS320C64X_INS_ABS, "abs"},
+	{TMS320C64X_INS_ABS2, "abs2"},
+	{TMS320C64X_INS_ADD, "add"},
+	{TMS320C64X_INS_ADD2, "add2"},
+	{TMS320C64X_INS_ADD4, "add4"},
+	{TMS320C64X_INS_ADDAB, "addab"},
+	{TMS320C64X_INS_ADDAD, "addad"},
+	{TMS320C64X_INS_ADDAH, "addah"},
+	{TMS320C64X_INS_ADDAW, "addaw"},
+	{TMS320C64X_INS_ADDK, "addk"},
+	{TMS320C64X_INS_ADDKPC, "addkpc"},
+	{TMS320C64X_INS_ADDU, "addu"},
+	{TMS320C64X_INS_AND, "and"},
+	{TMS320C64X_INS_ANDN, "andn"},
+	{TMS320C64X_INS_AVG2, "avg2"},
+	{TMS320C64X_INS_AVGU4, "avgu4"},
+	{TMS320C64X_INS_B, "b"},
+	{TMS320C64X_INS_BDEC, "bdec"},
+	{TMS320C64X_INS_BITC4, "bitc4"},
+	{TMS320C64X_INS_BNOP, "bnop"},
+	{TMS320C64X_INS_BPOS, "bpos"},
+	{TMS320C64X_INS_CLR, "clr"},
+	{TMS320C64X_INS_CMPEQ, "cmpeq"},
+	{TMS320C64X_INS_CMPEQ2, "cmpeq2"},
+	{TMS320C64X_INS_CMPEQ4, "cmpeq4"},
+	{TMS320C64X_INS_CMPGT, "cmpgt"},
+	{TMS320C64X_INS_CMPGT2, "cmpgt2"},
+	{TMS320C64X_INS_CMPGTU4, "cmpgtu4"},
+	{TMS320C64X_INS_CMPLT, "cmplt"},
+	{TMS320C64X_INS_CMPLTU, "cmpltu"},
+	{TMS320C64X_INS_DEAL, "deal"},
+	{TMS320C64X_INS_DOTP2, "dotp2"},
+	{TMS320C64X_INS_DOTPN2, "dotpn2"},
+	{TMS320C64X_INS_DOTPNRSU2, "dotpnrsu2"},
+	{TMS320C64X_INS_DOTPRSU2, "dotprsu2"},
+	{TMS320C64X_INS_DOTPSU4, "dotpsu4"},
+	{TMS320C64X_INS_DOTPU4, "dotpu4"},
+	{TMS320C64X_INS_EXT, "ext"},
+	{TMS320C64X_INS_EXTU, "extu"},
+	{TMS320C64X_INS_GMPGTU, "gmpgtu"},
+	{TMS320C64X_INS_GMPY4, "gmpy4"},
+	{TMS320C64X_INS_LDB, "ldb"},
+	{TMS320C64X_INS_LDBU, "ldbu"},
+	{TMS320C64X_INS_LDDW, "lddw"},
+	{TMS320C64X_INS_LDH, "ldh"},
+	{TMS320C64X_INS_LDHU, "ldhu"},
+	{TMS320C64X_INS_LDNDW, "ldndw"},
+	{TMS320C64X_INS_LDNW, "ldnw"},
+	{TMS320C64X_INS_LDW, "ldw"},
+	{TMS320C64X_INS_LMBD, "lmbd"},
+	{TMS320C64X_INS_MAX2, "max2"},
+	{TMS320C64X_INS_MAXU4, "maxu4"},
+	{TMS320C64X_INS_MIN2, "min2"},
+	{TMS320C64X_INS_MINU4, "minu4"},
+	{TMS320C64X_INS_MPY, "mpy"},
+	{TMS320C64X_INS_MPY2, "mpy2"},
+	{TMS320C64X_INS_MPYH, "mpyh"},
+	{TMS320C64X_INS_MPYHI, "mpyhi"},
+	{TMS320C64X_INS_MPYHIR, "mpyhir"},
+	{TMS320C64X_INS_MPYHL, "mpyhl"},
+	{TMS320C64X_INS_MPYHLU, "mpyhlu"},
+	{TMS320C64X_INS_MPYHSLU, "mpyhslu"},
+	{TMS320C64X_INS_MPYHSU, "mpyhsu"},
+	{TMS320C64X_INS_MPYHU, "mpyhu"},
+	{TMS320C64X_INS_MPYHULS, "mpyhuls"},
+	{TMS320C64X_INS_MPYHUS, "mpyhus"},
+	{TMS320C64X_INS_MPYLH, "mpylh"},
+	{TMS320C64X_INS_MPYLHU, "mpylhu"},
+	{TMS320C64X_INS_MPYLI, "mpyli"},
+	{TMS320C64X_INS_MPYLIR, "mpylir"},
+	{TMS320C64X_INS_MPYLSHU, "mpylshu"},
+	{TMS320C64X_INS_MPYLUHS, "mpyluhs"},
+	{TMS320C64X_INS_MPYSU, "mpysu"},
+	{TMS320C64X_INS_MPYSU4, "mpysu4"},
+	{TMS320C64X_INS_MPYU, "mpyu"},
+	{TMS320C64X_INS_MPYU4, "mpyu4"},
+	{TMS320C64X_INS_MPYUS, "mpyus"},
+	{TMS320C64X_INS_MVC, "mvc"},
+	{TMS320C64X_INS_MVD, "mvd"},
+	{TMS320C64X_INS_MVK, "mvk"},
+	{TMS320C64X_INS_MVKL, "mvkl"},
+	{TMS320C64X_INS_MVKLH, "mvklh"},
+	{TMS320C64X_INS_NOP, "nop"},
+	{TMS320C64X_INS_NORM, "norm"},
+	{TMS320C64X_INS_OR, "or"},
+	{TMS320C64X_INS_PACK2, "pack2"},
+	{TMS320C64X_INS_PACKH2, "packh2"},
+	{TMS320C64X_INS_PACKH4, "packh4"},
+	{TMS320C64X_INS_PACKHL2, "packhl2"},
+	{TMS320C64X_INS_PACKL4, "packl4"},
+	{TMS320C64X_INS_PACKLH2, "packlh2"},
+	{TMS320C64X_INS_ROTL, "rotl"},
+	{TMS320C64X_INS_SADD, "sadd"},
+	{TMS320C64X_INS_SADD2, "sadd2"},
+	{TMS320C64X_INS_SADDU4, "saddu4"},
+	{TMS320C64X_INS_SADDUS2, "saddus2"},
+	{TMS320C64X_INS_SAT, "sat"},
+	{TMS320C64X_INS_SET, "set"},
+	{TMS320C64X_INS_SHFL, "shfl"},
+	{TMS320C64X_INS_SHL, "shl"},
+	{TMS320C64X_INS_SHLMB, "shlmb"},
+	{TMS320C64X_INS_SHR, "shr"},
+	{TMS320C64X_INS_SHR2, "shr2"},
+	{TMS320C64X_INS_SHRMB, "shrmb"},
+	{TMS320C64X_INS_SHRU, "shru"},
+	{TMS320C64X_INS_SHRU2, "shru2"},
+	{TMS320C64X_INS_SMPY, "smpy"},
+	{TMS320C64X_INS_SMPY2, "smpy2"},
+	{TMS320C64X_INS_SMPYH, "smpyh"},
+	{TMS320C64X_INS_SMPYHL, "smpyhl"},
+	{TMS320C64X_INS_SMPYLH, "smpylh"},
+	{TMS320C64X_INS_SPACK2, "spack2"},
+	{TMS320C64X_INS_SPACKU4, "spacku4"},
+	{TMS320C64X_INS_SSHL, "sshl"},
+	{TMS320C64X_INS_SSHVL, "sshvl"},
+	{TMS320C64X_INS_SSHVR, "sshvr"},
+	{TMS320C64X_INS_SSUB, "ssub"},
+	{TMS320C64X_INS_STB, "stb"},
+	{TMS320C64X_INS_STDW, "stdw"},
+	{TMS320C64X_INS_STH, "sth"},
+	{TMS320C64X_INS_STNDW, "stndw"},
+	{TMS320C64X_INS_STNW, "stnw"},
+	{TMS320C64X_INS_STW, "stw"},
+	{TMS320C64X_INS_SUB, "sub"},
+	{TMS320C64X_INS_SUB2, "sub2"},
+	{TMS320C64X_INS_SUB4, "sub4"},
+	{TMS320C64X_INS_SUBAB, "subab"},
+	{TMS320C64X_INS_SUBABS4, "subabs4"},
+	{TMS320C64X_INS_SUBAH, "subah"},
+	{TMS320C64X_INS_SUBAW, "subaw"},
+	{TMS320C64X_INS_SUBC, "subc"},
+	{TMS320C64X_INS_SUBU, "subu"},
+	{TMS320C64X_INS_SWAP4, "swap4"},
+	{TMS320C64X_INS_UNPKHU4, "unpkhu4"},
+	{TMS320C64X_INS_UNPKLU4, "unpklu4"},
+	{TMS320C64X_INS_XOR, "xor"},
+	{TMS320C64X_INS_XPND2, "xpnd2"},
+	{TMS320C64X_INS_XPND4, "xpnd4"},
+	{TMS320C64X_INS_IDLE, "idle"},
+	{TMS320C64X_INS_MV, "mv"},
+	{TMS320C64X_INS_NEG, "neg"},
+	{TMS320C64X_INS_NOT, "not"},
+	{TMS320C64X_INS_SWAP2, "swap2"},
+	{TMS320C64X_INS_ZERO, "zero"},
+};
+
+#endif
+
+const char *TMS320C64x_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	if (id >= TMS320C64X_INS_ENDING)
+		return NULL;
+
+	return insn_name_maps[id].name;
+#else
+	return NULL;
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static const name_map group_name_maps[] = {
+	{ TMS320C64X_GRP_INVALID, NULL },
+	{ TMS320C64X_GRP_FUNIT_D, "funit_d" },
+	{ TMS320C64X_GRP_FUNIT_L, "funit_l" },
+	{ TMS320C64X_GRP_FUNIT_M, "funit_m" },
+	{ TMS320C64X_GRP_FUNIT_S, "funit_s" },
+	{ TMS320C64X_GRP_FUNIT_NO, "funit_no" },
+	{ TMS320C64X_GRP_JUMP, "jump" },
+};
+#endif
+
+const char *TMS320C64x_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	unsigned int i;
+
+	if (id >= TMS320C64X_GRP_ENDING)
+		return NULL;
+
+	for (i = 0; i < ARR_SIZE(group_name_maps); i++) {
+		if (group_name_maps[i].id == id)
+			return group_name_maps[i].name;
+	}
+
+	return group_name_maps[id].name;
+#else
+	return NULL;
+#endif
+}
+
+tms320c64x_reg TMS320C64x_map_register(unsigned int r)
+{
+	static unsigned int map[] = { 0,
+	};
+
+	if (r < ARR_SIZE(map))
+		return map[r];
+
+	return 0;
+}
+
+#endif
diff --git a/capstone/arch/TMS320C64x/TMS320C64xMapping.h b/capstone/arch/TMS320C64x/TMS320C64xMapping.h
new file mode 100644
index 000000000..ce26d3e89
--- /dev/null
+++ b/capstone/arch/TMS320C64x/TMS320C64xMapping.h
@@ -0,0 +1,26 @@
+/* Capstone Disassembly Engine */
+/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
+
+#ifndef CS_TMS320C64X_MAP_H
+#define CS_TMS320C64X_MAP_H
+
+#include "capstone/capstone.h"
+
+// return name of regiser in friendly string
+const char *TMS320C64x_reg_name(csh handle, unsigned int reg);
+
+// given internal insn id, return public instruction info
+void TMS320C64x_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *TMS320C64x_insn_name(csh handle, unsigned int id);
+
+const char *TMS320C64x_group_name(csh handle, unsigned int id);
+
+// map internal raw register to 'public' register
+tms320c64x_reg TMS320C64x_map_register(unsigned int r);
+
+// map register name to register ID
+tms320c64x_reg TMS320C64x_reg_id(char *name);
+
+#endif
+
diff --git a/capstone/arch/TMS320C64x/TMS320C64xModule.c b/capstone/arch/TMS320C64x/TMS320C64xModule.c
new file mode 100644
index 000000000..ff678c7cd
--- /dev/null
+++ b/capstone/arch/TMS320C64x/TMS320C64xModule.c
@@ -0,0 +1,39 @@
+/* Capstone Disassembly Engine */
+/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
+
+#ifdef CAPSTONE_HAS_TMS320C64X
+
+#include "../../utils.h"
+#include "../../MCRegisterInfo.h"
+#include "TMS320C64xDisassembler.h"
+#include "TMS320C64xInstPrinter.h"
+#include "TMS320C64xMapping.h"
+#include "TMS320C64xModule.h"
+
+cs_err TMS320C64x_global_init(cs_struct *ud)
+{
+	MCRegisterInfo *mri;
+
+	mri = cs_mem_malloc(sizeof(*mri));
+
+	TMS320C64x_init(mri);
+	ud->printer = TMS320C64x_printInst;
+	ud->printer_info = mri;
+	ud->getinsn_info = mri;
+	ud->disasm = TMS320C64x_getInstruction;
+	ud->post_printer = TMS320C64x_post_printer;
+
+	ud->reg_name = TMS320C64x_reg_name;
+	ud->insn_id = TMS320C64x_get_insn_id;
+	ud->insn_name = TMS320C64x_insn_name;
+	ud->group_name = TMS320C64x_group_name;
+
+	return CS_ERR_OK;
+}
+
+cs_err TMS320C64x_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	return CS_ERR_OK;
+}
+
+#endif
diff --git a/capstone/arch/TMS320C64x/TMS320C64xModule.h b/capstone/arch/TMS320C64x/TMS320C64xModule.h
new file mode 100644
index 000000000..f1c531208
--- /dev/null
+++ b/capstone/arch/TMS320C64x/TMS320C64xModule.h
@@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
+
+#ifndef CS_TMS320C64X_MODULE_H
+#define CS_TMS320C64X_MODULE_H
+
+#include "../../utils.h"
+
+cs_err TMS320C64x_global_init(cs_struct *ud);
+cs_err TMS320C64x_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif