Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

13 files changed, 4744 insertions, 0 deletions

diff --git a/capstone/arch/XCore/XCoreDisassembler.c b/capstone/arch/XCore/XCoreDisassembler.c
new file mode 100644
index 000000000..c095240a5
--- /dev/null
+++ b/capstone/arch/XCore/XCoreDisassembler.c
@@ -0,0 +1,794 @@
+//===------ XCoreDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifdef CAPSTONE_HAS_XCORE
+
+#include <stdio.h>	// DEBUG
+#include <stdlib.h>
+#include <string.h>
+
+#include "../../cs_priv.h"
+#include "../../utils.h"
+
+#include "XCoreDisassembler.h"
+
+#include "../../MCInst.h"
+#include "../../MCInstrDesc.h"
+#include "../../MCFixedLenDisassembler.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCDisassembler.h"
+#include "../../MathExtras.h"
+
+static uint64_t getFeatureBits(int mode)
+{
+	// support everything
+	return (uint64_t)-1;
+}
+
+static bool readInstruction16(const uint8_t *code, size_t code_len, uint16_t *insn)
+{
+	if (code_len < 2)
+		// insufficient data
+		return false;
+
+	// Encoded as a little-endian 16-bit word in the stream.
+	*insn = (code[0] <<  0) | (code[1] <<  8);
+	return true;
+}
+
+static bool readInstruction32(const uint8_t *code, size_t code_len, uint32_t *insn)
+{
+	if (code_len < 4)
+		// insufficient data
+		return false;
+
+	// Encoded as a little-endian 32-bit word in the stream.
+	*insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | ((uint32_t) code[3] << 24);
+
+	return true;
+}
+
+static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
+{
+	const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
+	return rc->RegsBegin[RegNo];
+}
+
+static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, const void *Decoder);
+
+static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, const void *Decoder);
+
+static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val,
+		uint64_t Address, const void *Decoder);
+
+static DecodeStatus DecodeNegImmOperand(MCInst *Inst, unsigned Val,
+		uint64_t Address, const void *Decoder);
+
+static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn,
+		uint64_t Address, const void *Decoder);
+
+static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn,
+		uint64_t Address, const void *Decoder);
+
+static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn,
+		uint64_t Address, const void *Decoder);
+
+static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn,
+		uint64_t Address, const void *Decoder);
+
+static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn,
+		uint64_t Address, const void *Decoder);
+
+static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn,
+		uint64_t Address, const void *Decoder);
+
+static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn,
+		uint64_t Address, const void *Decoder);
+
+static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn,
+		uint64_t Address, const void *Decoder);
+
+static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn,
+		uint64_t Address, const void *Decoder);
+
+static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn,
+		uint64_t Address, const void *Decoder);
+
+static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn,
+		uint64_t Address, const void *Decoder);
+
+static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn,
+		uint64_t Address, const void *Decoder);
+
+static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn,
+		uint64_t Address, const void *Decoder);
+
+static DecodeStatus DecodeL3RInstruction(MCInst *Inst, unsigned Insn,
+		uint64_t Address, const void *Decoder);
+
+static DecodeStatus DecodeL3RSrcDstInstruction(MCInst *Inst, unsigned Insn,
+		uint64_t Address, const void *Decoder);
+
+static DecodeStatus DecodeL2RUSInstruction(MCInst *Inst, unsigned Insn,
+		uint64_t Address, const void *Decoder);
+
+static DecodeStatus DecodeL2RUSBitpInstruction(MCInst *Inst, unsigned Insn,
+		uint64_t Address, const void *Decoder);
+
+static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn,
+		uint64_t Address, const void *Decoder);
+
+static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn,
+		uint64_t Address, const void *Decoder);
+
+static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn,
+		uint64_t Address, const void *Decoder);
+
+static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst *Inst, unsigned Insn,
+		uint64_t Address, const void *Decoder);
+
+#include "XCoreGenDisassemblerTables.inc"
+
+#define GET_REGINFO_ENUM
+#define GET_REGINFO_MC_DESC
+#include "XCoreGenRegisterInfo.inc"
+
+static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	unsigned Reg;
+
+	if (RegNo > 11)
+		return MCDisassembler_Fail;
+
+	Reg = getReg(Decoder, XCore_GRRegsRegClassID, RegNo);
+	MCOperand_CreateReg0(Inst, Reg);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
+		uint64_t Address, const void *Decoder)
+{
+	unsigned Reg;
+	if (RegNo > 15)
+		return MCDisassembler_Fail;
+
+	Reg = getReg(Decoder, XCore_RRegsRegClassID, RegNo);
+	MCOperand_CreateReg0(Inst, Reg);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val,
+		uint64_t Address, const void *Decoder)
+{
+	static const unsigned Values[] = {
+		32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
+	};
+
+	if (Val > 11)
+		return MCDisassembler_Fail;
+
+	MCOperand_CreateImm0(Inst, Values[Val]);
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeNegImmOperand(MCInst *Inst, unsigned Val,
+		uint64_t Address, const void *Decoder)
+{
+	MCOperand_CreateImm0(Inst, -(int64_t)Val);
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus Decode2OpInstruction(unsigned Insn, unsigned *Op1, unsigned *Op2)
+{
+	unsigned Op1High, Op2High;
+	unsigned Combined = fieldFromInstruction_4(Insn, 6, 5);
+
+	if (Combined < 27)
+		return MCDisassembler_Fail;
+
+	if (fieldFromInstruction_4(Insn, 5, 1)) {
+		if (Combined == 31)
+			return MCDisassembler_Fail;
+		Combined += 5;
+	}
+
+	Combined -= 27;
+	Op1High = Combined % 3;
+	Op2High = Combined / 3;
+	*Op1 = (Op1High << 2) | fieldFromInstruction_4(Insn, 2, 2);
+	*Op2 = (Op2High << 2) | fieldFromInstruction_4(Insn, 0, 2);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus Decode3OpInstruction(unsigned Insn,
+		unsigned *Op1, unsigned *Op2, unsigned *Op3)
+{
+	unsigned Op1High, Op2High, Op3High;
+	unsigned Combined = fieldFromInstruction_4(Insn, 6, 5);
+	if (Combined >= 27)
+		return MCDisassembler_Fail;
+
+	Op1High = Combined % 3;
+	Op2High = (Combined / 3) % 3;
+	Op3High = Combined / 9;
+	*Op1 = (Op1High << 2) | fieldFromInstruction_4(Insn, 4, 2);
+	*Op2 = (Op2High << 2) | fieldFromInstruction_4(Insn, 2, 2);
+	*Op3 = (Op3High << 2) | fieldFromInstruction_4(Insn, 0, 2);
+
+	return MCDisassembler_Success;
+}
+
+#define GET_INSTRINFO_ENUM
+#include "XCoreGenInstrInfo.inc"
+static DecodeStatus Decode2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address,
+		const void *Decoder)
+{
+	// Try and decode as a 3R instruction.
+	unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5);
+	switch (Opcode) {
+		case 0x0:
+			MCInst_setOpcode(Inst, XCore_STW_2rus);
+			return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
+		case 0x1:
+			MCInst_setOpcode(Inst, XCore_LDW_2rus);
+			return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
+		case 0x2:
+			MCInst_setOpcode(Inst, XCore_ADD_3r);
+			return Decode3RInstruction(Inst, Insn, Address, Decoder);
+		case 0x3:
+			MCInst_setOpcode(Inst, XCore_SUB_3r);
+			return Decode3RInstruction(Inst, Insn, Address, Decoder);
+		case 0x4:
+			MCInst_setOpcode(Inst, XCore_SHL_3r);
+			return Decode3RInstruction(Inst, Insn, Address, Decoder);
+		case 0x5:
+			MCInst_setOpcode(Inst, XCore_SHR_3r);
+			return Decode3RInstruction(Inst, Insn, Address, Decoder);
+		case 0x6:
+			MCInst_setOpcode(Inst, XCore_EQ_3r);
+			return Decode3RInstruction(Inst, Insn, Address, Decoder);
+		case 0x7:
+			MCInst_setOpcode(Inst, XCore_AND_3r);
+			return Decode3RInstruction(Inst, Insn, Address, Decoder);
+		case 0x8:
+			MCInst_setOpcode(Inst, XCore_OR_3r);
+			return Decode3RInstruction(Inst, Insn, Address, Decoder);
+		case 0x9:
+			MCInst_setOpcode(Inst, XCore_LDW_3r);
+			return Decode3RInstruction(Inst, Insn, Address, Decoder);
+		case 0x10:
+			MCInst_setOpcode(Inst, XCore_LD16S_3r);
+			return Decode3RInstruction(Inst, Insn, Address, Decoder);
+		case 0x11:
+			MCInst_setOpcode(Inst, XCore_LD8U_3r);
+			return Decode3RInstruction(Inst, Insn, Address, Decoder);
+		case 0x12:
+			MCInst_setOpcode(Inst, XCore_ADD_2rus);
+			return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
+		case 0x13:
+			MCInst_setOpcode(Inst, XCore_SUB_2rus);
+			return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
+		case 0x14:
+			MCInst_setOpcode(Inst, XCore_SHL_2rus);
+			return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
+		case 0x15:
+			MCInst_setOpcode(Inst, XCore_SHR_2rus);
+			return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
+		case 0x16:
+			MCInst_setOpcode(Inst, XCore_EQ_2rus);
+			return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
+		case 0x17:
+			MCInst_setOpcode(Inst, XCore_TSETR_3r);
+			return Decode3RImmInstruction(Inst, Insn, Address, Decoder);
+		case 0x18:
+			MCInst_setOpcode(Inst, XCore_LSS_3r);
+			return Decode3RInstruction(Inst, Insn, Address, Decoder);
+		case 0x19:
+			MCInst_setOpcode(Inst, XCore_LSU_3r);
+			return Decode3RInstruction(Inst, Insn, Address, Decoder);
+	}
+
+	return MCDisassembler_Fail;
+}
+
+static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+		const void *Decoder)
+{
+	unsigned Op1, Op2;
+	DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
+	if (S != MCDisassembler_Success)
+		return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+	DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+	DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+
+	return S;
+}
+
+static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+		const void *Decoder)
+{
+	unsigned Op1, Op2;
+	DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
+	if (S != MCDisassembler_Success)
+		return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+	MCOperand_CreateImm0(Inst, Op1);
+	DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+
+	return S;
+}
+
+static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+		const void *Decoder)
+{
+	unsigned Op1, Op2;
+	DecodeStatus S = Decode2OpInstruction(Insn, &Op2, &Op1);
+	if (S != MCDisassembler_Success)
+		return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+	DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+	DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+
+	return S;
+}
+
+static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+		const void *Decoder)
+{
+	unsigned Op1, Op2;
+	DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
+	if (S != MCDisassembler_Success)
+		return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+	DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+	DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+	DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+
+	return S;
+}
+
+static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+		const void *Decoder)
+{
+	unsigned Op1, Op2;
+	DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
+	if (S != MCDisassembler_Success)
+		return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+	DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+	MCOperand_CreateImm0(Inst, Op2);
+
+	return S;
+}
+
+static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+		const void *Decoder)
+{
+	unsigned Op1, Op2;
+	DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
+	if (S != MCDisassembler_Success)
+		return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+	DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+	DecodeBitpOperand(Inst, Op2, Address, Decoder);
+
+	return S;
+}
+
+static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+		const void *Decoder)
+{
+	unsigned Op1, Op2;
+	DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
+	if (S != MCDisassembler_Success)
+		return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+	DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+	DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+	DecodeBitpOperand(Inst, Op2, Address, Decoder);
+
+	return S;
+}
+
+static DecodeStatus DecodeL2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address,
+		const void *Decoder)
+{
+	// Try and decode as a L3R / L2RUS instruction.
+	unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) |
+		fieldFromInstruction_4(Insn, 27, 5) << 4;
+	switch (Opcode) {
+		case 0x0c:
+			MCInst_setOpcode(Inst, XCore_STW_l3r);
+			return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+		case 0x1c:
+			MCInst_setOpcode(Inst, XCore_XOR_l3r);
+			return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+		case 0x2c:
+			MCInst_setOpcode(Inst, XCore_ASHR_l3r);
+			return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+		case 0x3c:
+			MCInst_setOpcode(Inst, XCore_LDAWF_l3r);
+			return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+		case 0x4c:
+			MCInst_setOpcode(Inst, XCore_LDAWB_l3r);
+			return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+		case 0x5c:
+			MCInst_setOpcode(Inst, XCore_LDA16F_l3r);
+			return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+		case 0x6c:
+			MCInst_setOpcode(Inst, XCore_LDA16B_l3r);
+			return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+		case 0x7c:
+			MCInst_setOpcode(Inst, XCore_MUL_l3r);
+			return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+		case 0x8c:
+			MCInst_setOpcode(Inst, XCore_DIVS_l3r);
+			return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+		case 0x9c:
+			MCInst_setOpcode(Inst, XCore_DIVU_l3r);
+			return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+		case 0x10c:
+			MCInst_setOpcode(Inst, XCore_ST16_l3r);
+			return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+		case 0x11c:
+			MCInst_setOpcode(Inst, XCore_ST8_l3r);
+			return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+		case 0x12c:
+			MCInst_setOpcode(Inst, XCore_ASHR_l2rus);
+			return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
+		case 0x12d:
+			MCInst_setOpcode(Inst, XCore_OUTPW_l2rus);
+			return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
+		case 0x12e:
+			MCInst_setOpcode(Inst, XCore_INPW_l2rus);
+			return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
+		case 0x13c:
+			MCInst_setOpcode(Inst, XCore_LDAWF_l2rus);
+			return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
+		case 0x14c:
+			MCInst_setOpcode(Inst, XCore_LDAWB_l2rus);
+			return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
+		case 0x15c:
+			MCInst_setOpcode(Inst, XCore_CRC_l3r);
+			return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
+		case 0x18c:
+			MCInst_setOpcode(Inst, XCore_REMS_l3r);
+			return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+		case 0x19c:
+			MCInst_setOpcode(Inst, XCore_REMU_l3r);
+			return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
+	}
+
+	return MCDisassembler_Fail;
+}
+
+static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+		const void *Decoder)
+{
+	unsigned Op1, Op2;
+	DecodeStatus S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2);
+	if (S != MCDisassembler_Success)
+		return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+	DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+	DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+
+	return S;
+}
+
+static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+		const void *Decoder)
+{
+	unsigned Op1, Op2;
+	DecodeStatus S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2);
+	if (S != MCDisassembler_Success)
+		return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+	DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+	DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+
+	return S;
+}
+
+static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+		const void *Decoder)
+{
+	unsigned Op1, Op2, Op3;
+	DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
+	if (S == MCDisassembler_Success) {
+		DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+		DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+		DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
+	}
+
+	return S;
+}
+
+static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+		const void *Decoder)
+{
+	unsigned Op1, Op2, Op3;
+	DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
+	if (S == MCDisassembler_Success) {
+		MCOperand_CreateImm0(Inst, Op1);
+		DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+		DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
+	}
+
+	return S;
+}
+
+static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+		const void *Decoder)
+{
+	unsigned Op1, Op2, Op3;
+	DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
+	if (S == MCDisassembler_Success) {
+		DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+		DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+		MCOperand_CreateImm0(Inst, Op3);
+	}
+
+	return S;
+}
+
+static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+		const void *Decoder)
+{
+	unsigned Op1, Op2, Op3;
+	DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
+	if (S == MCDisassembler_Success) {
+		DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+		DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+		DecodeBitpOperand(Inst, Op3, Address, Decoder);
+	}
+
+	return S;
+}
+
+static DecodeStatus DecodeL3RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+		const void *Decoder)
+{
+	unsigned Op1, Op2, Op3;
+	DecodeStatus S =
+		Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
+	if (S == MCDisassembler_Success) {
+		DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+		DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+		DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
+	}
+
+	return S;
+}
+
+static DecodeStatus DecodeL3RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+		const void *Decoder)
+{
+	unsigned Op1, Op2, Op3;
+	DecodeStatus S =
+		Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
+	if (S == MCDisassembler_Success) {
+		DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+		DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+		DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+		DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
+	}
+
+	return S;
+}
+
+static DecodeStatus DecodeL2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+		const void *Decoder)
+{
+	unsigned Op1, Op2, Op3;
+	DecodeStatus S =
+		Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
+	if (S == MCDisassembler_Success) {
+		DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+		DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+		MCOperand_CreateImm0(Inst, Op3);
+	}
+
+	return S;
+}
+
+static DecodeStatus DecodeL2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+		const void *Decoder)
+{
+	unsigned Op1, Op2, Op3;
+	DecodeStatus S =
+		Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
+	if (S == MCDisassembler_Success) {
+		DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+		DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+		DecodeBitpOperand(Inst, Op3, Address, Decoder);
+	}
+
+	return S;
+}
+
+static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+		const void *Decoder)
+{
+	unsigned Op1, Op2, Op3, Op4, Op5, Op6;
+	DecodeStatus S =
+		Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
+	if (S != MCDisassembler_Success)
+		return S;
+
+	S = Decode3OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5, &Op6);
+	if (S != MCDisassembler_Success)
+		return S;
+
+	DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+	DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
+	DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+	DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
+	DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
+	DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
+	return S;
+}
+
+static DecodeStatus DecodeL5RInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address,
+		const void *Decoder)
+{
+	unsigned Opcode;
+
+	// Try and decode as a L6R instruction.
+	MCInst_clear(Inst);
+	Opcode = fieldFromInstruction_4(Insn, 27, 5);
+	switch (Opcode) {
+		default:
+			break;
+		case 0x00:
+			MCInst_setOpcode(Inst, XCore_LMUL_l6r);
+			return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
+	}
+
+	return MCDisassembler_Fail;
+}
+
+static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+		const void *Decoder)
+{
+	unsigned Op1, Op2, Op3, Op4, Op5;
+	DecodeStatus S =
+		Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
+	if (S != MCDisassembler_Success)
+		return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
+
+	S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5);
+	if (S != MCDisassembler_Success)
+		return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
+
+	DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+	DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
+	DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+	DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
+	DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
+	return S;
+}
+
+static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+		const void *Decoder)
+{
+	unsigned Op1, Op2, Op3;
+	unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4);
+	DecodeStatus S =
+		Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
+	if (S == MCDisassembler_Success) {
+		DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+		S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
+	}
+
+	if (S == MCDisassembler_Success) {
+		DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
+		DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+		DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
+	}
+	return S;
+}
+
+static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
+		const void *Decoder)
+{
+	unsigned Op1, Op2, Op3;
+	unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4);
+	DecodeStatus S =
+		Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
+	if (S == MCDisassembler_Success) {
+		DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+		S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
+	}
+
+	if (S == MCDisassembler_Success) {
+		DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+		DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
+		DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+		DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
+	}
+
+	return S;
+}
+
+#define GET_SUBTARGETINFO_ENUM
+#include "XCoreGenInstrInfo.inc"
+bool XCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI,
+		uint16_t *size, uint64_t address, void *info)
+{
+	uint16_t insn16;
+	uint32_t insn32;
+	DecodeStatus Result;
+
+	if (!readInstruction16(code, code_len, &insn16)) {
+		return false;
+	}
+
+	if (MI->flat_insn->detail) {
+		memset(MI->flat_insn->detail, 0, offsetof(cs_detail, xcore)+sizeof(cs_xcore));
+	}
+
+	// Calling the auto-generated decoder function.
+	Result = decodeInstruction_2(DecoderTable16, MI, insn16, address, info, 0);
+	if (Result != MCDisassembler_Fail) {
+		*size = 2;
+		return true;
+	}
+
+	if (!readInstruction32(code, code_len, &insn32)) {
+		return false;
+	}
+
+	// Calling the auto-generated decoder function.
+	Result = decodeInstruction_4(DecoderTable32, MI, insn32, address, info, 0);
+	if (Result != MCDisassembler_Fail) {
+		*size = 4;
+		return true;
+	}
+
+	return false;
+}
+
+void XCore_init(MCRegisterInfo *MRI)
+{
+	/*
+	InitMCRegisterInfo(XCoreRegDesc, 17, RA, PC,
+			XCoreMCRegisterClasses, 2,
+			XCoreRegUnitRoots,
+			16,
+			XCoreRegDiffLists,
+			XCoreRegStrings,
+			XCoreSubRegIdxLists,
+			1,
+			XCoreSubRegIdxRanges,
+			XCoreRegEncodingTable);
+	*/
+
+
+	MCRegisterInfo_InitMCRegisterInfo(MRI, XCoreRegDesc, 17,
+			0, 0,
+			XCoreMCRegisterClasses, 2,
+			0, 0,
+			XCoreRegDiffLists,
+			0,
+			XCoreSubRegIdxLists, 1,
+			0);
+}
+
+#endif
diff --git a/capstone/arch/XCore/XCoreDisassembler.h b/capstone/arch/XCore/XCoreDisassembler.h
new file mode 100644
index 000000000..a7478001d
--- /dev/null
+++ b/capstone/arch/XCore/XCoreDisassembler.h
@@ -0,0 +1,17 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_XCOREDISASSEMBLER_H
+#define CS_XCOREDISASSEMBLER_H
+
+#include "capstone/capstone.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCInst.h"
+
+void XCore_init(MCRegisterInfo *MRI);
+
+bool XCore_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+		MCInst *instr, uint16_t *size, uint64_t address, void *info);
+
+#endif
+
diff --git a/capstone/arch/XCore/XCoreGenAsmWriter.inc b/capstone/arch/XCore/XCoreGenAsmWriter.inc
new file mode 100644
index 000000000..adddeffd3
--- /dev/null
+++ b/capstone/arch/XCore/XCoreGenAsmWriter.inc
@@ -0,0 +1,772 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*Assembly Writer Source Fragment                                             *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#include <stdio.h>	// debug
+#include <capstone/platform.h>
+
+
+/// printInstruction - This method is automatically generated by tablegen
+/// from the instruction set description.
+static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
+{
+  static const uint32_t OpInfo[] = {
+    0U,	// PHI
+    0U,	// INLINEASM
+    0U,	// CFI_INSTRUCTION
+    0U,	// EH_LABEL
+    0U,	// GC_LABEL
+    0U,	// KILL
+    0U,	// EXTRACT_SUBREG
+    0U,	// INSERT_SUBREG
+    0U,	// IMPLICIT_DEF
+    0U,	// SUBREG_TO_REG
+    0U,	// COPY_TO_REGCLASS
+    665U,	// DBG_VALUE
+    0U,	// REG_SEQUENCE
+    0U,	// COPY
+    658U,	// BUNDLE
+    687U,	// LIFETIME_START
+    645U,	// LIFETIME_END
+    0U,	// STACKMAP
+    0U,	// PATCHPOINT
+    0U,	// LOAD_STACK_GUARD
+    0U,	// STATEPOINT
+    0U,	// FRAME_ALLOC
+    2250U,	// ADD_2rus
+    2250U,	// ADD_3r
+    10363U,	// ADJCALLSTACKDOWN
+    10383U,	// ADJCALLSTACKUP
+    2361840U,	// ANDNOT_2r
+    2255U,	// AND_3r
+    2404U,	// ASHR_l2rus
+    2404U,	// ASHR_l3r
+    10769U,	// BAU_1r
+    2099777U,	// BITREV_l2r
+    19161U,	// BLACP_lu10
+    19161U,	// BLACP_u10
+    10672U,	// BLAT_lu6
+    10672U,	// BLAT_u6
+    10425U,	// BLA_1r
+    10510U,	// BLRB_lu10
+    10510U,	// BLRB_u10
+    10510U,	// BLRF_lu10
+    10510U,	// BLRF_u10
+    2099418U,	// BRBF_lru6
+    2099418U,	// BRBF_ru6
+    2099638U,	// BRBT_lru6
+    2099638U,	// BRBT_ru6
+    10774U,	// BRBU_lu6
+    10774U,	// BRBU_u6
+    2099418U,	// BRFF_lru6
+    2099418U,	// BRFF_ru6
+    2099638U,	// BRFT_lru6
+    2099638U,	// BRFT_ru6
+    10774U,	// BRFU_lu6
+    10774U,	// BRFU_u6
+    10791U,	// BRU_1r
+    553511U,	// BR_JT
+    815655U,	// BR_JT32
+    2099768U,	// BYTEREV_l2r
+    2132815U,	// CHKCT_2r
+    2132815U,	// CHKCT_rus
+    1163U,	// CLRE_0R
+    19301U,	// CLRPT_1R
+    10614U,	// CLRSR_branch_lu6
+    10614U,	// CLRSR_branch_u6
+    10614U,	// CLRSR_lu6
+    10614U,	// CLRSR_u6
+    2099807U,	// CLZ_l2r
+    5247047U,	// CRC8_l4r
+    17041459U,	// CRC_l3r
+    1168U,	// DCALL_0R
+    1200U,	// DENTSP_0R
+    10488U,	// DGETREG_1r
+    2474U,	// DIVS_l3r
+    2610U,	// DIVU_l3r
+    1207U,	// DRESTSP_0R
+    1242U,	// DRET_0R
+    10475U,	// ECALLF_1r
+    10723U,	// ECALLT_1r
+    19342U,	// EDU_1r
+    6334686U,	// EEF_2r
+    6334929U,	// EET_2r
+    19351U,	// EEU_1r
+    2099310U,	// EH_RETURN
+    6334765U,	// ENDIN_2r
+    10569U,	// ENTSP_lu6
+    10569U,	// ENTSP_u6
+    2400U,	// EQ_2rus
+    2400U,	// EQ_3r
+    10554U,	// EXTDP_lu6
+    10554U,	// EXTDP_u6
+    10585U,	// EXTSP_lu6
+    10585U,	// EXTSP_u6
+    10401U,	// FRAME_TO_ARGS_OFFSET
+    19256U,	// FREER_1r
+    1236U,	// FREET_0R
+    6334676U,	// GETD_l2r
+    1139U,	// GETED_0R
+    1224U,	// GETET_0R
+    1151U,	// GETID_0R
+    1174U,	// GETKEP_0R
+    1187U,	// GETKSP_0R
+    6334772U,	// GETN_l2r
+    51670U,	// GETPS_l2r
+    2099588U,	// GETR_rus
+    10252U,	// GETSR_lu6
+    10252U,	// GETSR_u6
+    6334968U,	// GETST_2r
+    6334883U,	// GETTS_2r
+    6334906U,	// INCT_2r
+    62438U,	// INITCP_2r
+    70630U,	// INITDP_2r
+    78822U,	// INITLR_l2r
+    87014U,	// INITPC_2r
+    95206U,	// INITSP_2r
+    8432212U,	// INPW_l2rus
+    6596970U,	// INSHR_2r
+    6334955U,	// INT_2r
+    6334768U,	// IN_2r
+    675U,	// Int_MemBarrier
+    10528U,	// KCALL_1r
+    10528U,	// KCALL_lu6
+    10528U,	// KCALL_u6
+    10568U,	// KENTSP_lu6
+    10568U,	// KENTSP_u6
+    10576U,	// KRESTSP_lu6
+    10576U,	// KRESTSP_u6
+    1247U,	// KRET_0R
+    45093065U,	// LADD_l5r
+    12585354U,	// LD16S_3r
+    12585483U,	// LD8U_3r
+    14682170U,	// LDA16B_l3r
+    12585018U,	// LDA16F_l3r
+    10241U,	// LDAPB_lu10
+    10241U,	// LDAPB_u10
+    10241U,	// LDAPF_lu10
+    10241U,	// LDAPF_lu10_ba
+    10241U,	// LDAPF_u10
+    14682697U,	// LDAWB_l2rus
+    14682697U,	// LDAWB_l3r
+    19134U,	// LDAWCP_lu6
+    19134U,	// LDAWCP_u6
+    100937U,	// LDAWDP_lru6
+    100937U,	// LDAWDP_ru6
+    2099282U,	// LDAWFI
+    12585545U,	// LDAWF_l2rus
+    12585545U,	// LDAWF_l3r
+    109129U,	// LDAWSP_lru6
+    109129U,	// LDAWSP_ru6
+    2099396U,	// LDC_lru6
+    2099396U,	// LDC_ru6
+    1105U,	// LDET_0R
+    184551985U,	// LDIVU_l5r
+    1075U,	// LDSED_0R
+    1015U,	// LDSPC_0R
+    1045U,	// LDSSR_0R
+    117327U,	// LDWCP_lru6
+    19148U,	// LDWCP_lu10
+    117327U,	// LDWCP_ru6
+    19148U,	// LDWCP_u10
+    100943U,	// LDWDP_lru6
+    100943U,	// LDWDP_ru6
+    2099292U,	// LDWFI
+    109135U,	// LDWSP_lru6
+    109135U,	// LDWSP_ru6
+    12585551U,	// LDW_2rus
+    12585551U,	// LDW_3r
+    268437799U,	// LMUL_l6r
+    2462U,	// LSS_3r
+    45093054U,	// LSUB_l5r
+    2604U,	// LSU_3r
+    452987281U,	// MACCS_l4r
+    452987418U,	// MACCU_l4r
+    19224U,	// MJOIN_1r
+    2099463U,	// MKMSK_2r
+    2099463U,	// MKMSK_rus
+    19169U,	// MSYNC_1r
+    2344U,	// MUL_l3r
+    2099443U,	// NEG
+    2099699U,	// NOT
+    2418U,	// OR_3r
+    2132826U,	// OUTCT_2r
+    2132826U,	// OUTCT_rus
+    78681013U,	// OUTPW_l2rus
+    2136899U,	// OUTSHR_2r
+    2132859U,	// OUTT_2r
+    2132869U,	// OUT_2r
+    6334721U,	// PEEK_2r
+    2456U,	// REMS_l3r
+    2593U,	// REMU_l3r
+    10561U,	// RETSP_lu6
+    10561U,	// RETSP_u6
+    612U,	// SELECT_CC
+    2132748U,	// SETCLK_l2r
+    10264U,	// SETCP_1r
+    2132728U,	// SETC_l2r
+    2132728U,	// SETC_lru6
+    2132728U,	// SETC_ru6
+    10273U,	// SETDP_1r
+    2132738U,	// SETD_2r
+    125856U,	// SETEV_1r
+    632U,	// SETKEP_0R
+    2132771U,	// SETN_l2r
+    2132716U,	// SETPSC_2r
+    2132951U,	// SETPS_l2r
+    2132848U,	// SETPT_2r
+    2132939U,	// SETRDY_l2r
+    10282U,	// SETSP_1r
+    10621U,	// SETSR_branch_lu6
+    10621U,	// SETSR_branch_u6
+    10621U,	// SETSR_lu6
+    10621U,	// SETSR_u6
+    2132928U,	// SETTW_l2r
+    125867U,	// SETV_1r
+    2361855U,	// SEXT_2r
+    2361855U,	// SEXT_rus
+    2331U,	// SHL_2rus
+    2331U,	// SHL_3r
+    2405U,	// SHR_2rus
+    2405U,	// SHR_3r
+    1133U,	// SSYNC_0r
+    12585025U,	// ST16_l3r
+    12585037U,	// ST8_l3r
+    1119U,	// STET_0R
+    1090U,	// STSED_0R
+    1030U,	// STSPC_0R
+    1060U,	// STSSR_0R
+    100954U,	// STWDP_lru6
+    100954U,	// STWDP_ru6
+    2099301U,	// STWFI
+    109146U,	// STWSP_lru6
+    109146U,	// STWSP_ru6
+    12585562U,	// STW_2rus
+    12585562U,	// STW_l3r
+    2239U,	// SUB_2rus
+    2239U,	// SUB_3r
+    19245U,	// SYNCR_1r
+    6334912U,	// TESTCT_2r
+    6334738U,	// TESTLCL_l2r
+    6334920U,	// TESTWCT_2r
+    2100415U,	// TSETMR_2r
+    138207U,	// TSETR_3r
+    19438U,	// TSTART_1R
+    10467U,	// WAITEF_1R
+    10715U,	// WAITET_1R
+    1252U,	// WAITEU_0R
+    2417U,	// XOR_l3r
+    2361861U,	// ZEXT_2r
+    2361861U,	// ZEXT_rus
+    0U
+  };
+
+  static const char AsmStrs[] = {
+  /* 0 */ 'l', 'd', 'a', 'p', 32, 'r', '1', '1', ',', 32, 0,
+  /* 11 */ 'g', 'e', 't', 's', 'r', 32, 'r', '1', '1', ',', 32, 0,
+  /* 23 */ 's', 'e', 't', 32, 'c', 'p', ',', 32, 0,
+  /* 32 */ 's', 'e', 't', 32, 'd', 'p', ',', 32, 0,
+  /* 41 */ 's', 'e', 't', 32, 's', 'p', ',', 32, 0,
+  /* 50 */ 'c', 'r', 'c', '3', '2', 32, 0,
+  /* 57 */ 'l', 'd', 'a', '1', '6', 32, 0,
+  /* 64 */ 's', 't', '1', '6', 32, 0,
+  /* 70 */ 'c', 'r', 'c', '8', 32, 0,
+  /* 76 */ 's', 't', '8', 32, 0,
+  /* 81 */ '#', 32, 'L', 'D', 'A', 'W', 'F', 'I', 32, 0,
+  /* 91 */ '#', 32, 'L', 'D', 'W', 'F', 'I', 32, 0,
+  /* 100 */ '#', 32, 'S', 'T', 'W', 'F', 'I', 32, 0,
+  /* 109 */ '#', 32, 'E', 'H', '_', 'R', 'E', 'T', 'U', 'R', 'N', 32, 0,
+  /* 122 */ '#', 32, 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0,
+  /* 142 */ '#', 32, 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0,
+  /* 160 */ '#', 32, 'F', 'R', 'A', 'M', 'E', '_', 'T', 'O', '_', 'A', 'R', 'G', 'S', '_', 'O', 'F', 'F', 'S', 'E', 'T', 32, 0,
+  /* 184 */ 'b', 'l', 'a', 32, 0,
+  /* 189 */ 'l', 's', 'u', 'b', 32, 0,
+  /* 195 */ 'l', 'd', 'c', 32, 0,
+  /* 200 */ 'l', 'a', 'd', 'd', 32, 0,
+  /* 206 */ 'a', 'n', 'd', 32, 0,
+  /* 211 */ 'g', 'e', 't', 'd', 32, 0,
+  /* 217 */ 'b', 'f', 32, 0,
+  /* 221 */ 'e', 'e', 'f', 32, 0,
+  /* 226 */ 'w', 'a', 'i', 't', 'e', 'f', 32, 0,
+  /* 234 */ 'e', 'c', 'a', 'l', 'l', 'f', 32, 0,
+  /* 242 */ 'n', 'e', 'g', 32, 0,
+  /* 247 */ 'd', 'g', 'e', 't', 'r', 'e', 'g', 32, 0,
+  /* 256 */ 'p', 'e', 'e', 'k', 32, 0,
+  /* 262 */ 'm', 'k', 'm', 's', 'k', 32, 0,
+  /* 269 */ 'b', 'l', 32, 0,
+  /* 273 */ 't', 'e', 's', 't', 'l', 'c', 'l', 32, 0,
+  /* 282 */ 's', 'h', 'l', 32, 0,
+  /* 287 */ 'k', 'c', 'a', 'l', 'l', 32, 0,
+  /* 294 */ 'l', 'm', 'u', 'l', 32, 0,
+  /* 300 */ 'e', 'n', 'd', 'i', 'n', 32, 0,
+  /* 307 */ 'g', 'e', 't', 'n', 32, 0,
+  /* 313 */ 'e', 'x', 't', 'd', 'p', 32, 0,
+  /* 320 */ 'r', 'e', 't', 's', 'p', 32, 0,
+  /* 327 */ 'k', 'e', 'n', 't', 's', 'p', 32, 0,
+  /* 335 */ 'k', 'r', 'e', 's', 't', 's', 'p', 32, 0,
+  /* 344 */ 'e', 'x', 't', 's', 'p', 32, 0,
+  /* 351 */ 'e', 'q', 32, 0,
+  /* 355 */ 'a', 's', 'h', 'r', 32, 0,
+  /* 361 */ 'i', 'n', 's', 'h', 'r', 32, 0,
+  /* 368 */ 'x', 'o', 'r', 32, 0,
+  /* 373 */ 'c', 'l', 'r', 's', 'r', 32, 0,
+  /* 380 */ 's', 'e', 't', 's', 'r', 32, 0,
+  /* 387 */ 'g', 'e', 't', 'r', 32, 0,
+  /* 393 */ 'l', 'd', '1', '6', 's', 32, 0,
+  /* 400 */ 'm', 'a', 'c', 'c', 's', 32, 0,
+  /* 407 */ 'r', 'e', 'm', 's', 32, 0,
+  /* 413 */ 'l', 's', 's', 32, 0,
+  /* 418 */ 'g', 'e', 't', 't', 's', 32, 0,
+  /* 425 */ 'd', 'i', 'v', 's', 32, 0,
+  /* 431 */ 'b', 'l', 'a', 't', 32, 0,
+  /* 437 */ 'b', 't', 32, 0,
+  /* 441 */ 'i', 'n', 'c', 't', 32, 0,
+  /* 447 */ 't', 'e', 's', 't', 'c', 't', 32, 0,
+  /* 455 */ 't', 'e', 's', 't', 'w', 'c', 't', 32, 0,
+  /* 464 */ 'e', 'e', 't', 32, 0,
+  /* 469 */ 'g', 'e', 't', 32, 0,
+  /* 474 */ 'w', 'a', 'i', 't', 'e', 't', 32, 0,
+  /* 482 */ 'e', 'c', 'a', 'l', 'l', 't', 32, 0,
+  /* 490 */ 'i', 'n', 't', 32, 0,
+  /* 495 */ 'a', 'n', 'd', 'n', 'o', 't', 32, 0,
+  /* 503 */ 'g', 'e', 't', 's', 't', 32, 0,
+  /* 510 */ 's', 'e', 'x', 't', 32, 0,
+  /* 516 */ 'z', 'e', 'x', 't', 32, 0,
+  /* 522 */ 'l', 'd', '8', 'u', 32, 0,
+  /* 528 */ 'b', 'a', 'u', 32, 0,
+  /* 533 */ 'b', 'u', 32, 0,
+  /* 537 */ 'm', 'a', 'c', 'c', 'u', 32, 0,
+  /* 544 */ 'r', 'e', 'm', 'u', 32, 0,
+  /* 550 */ 'b', 'r', 'u', 32, 0,
+  /* 555 */ 'l', 's', 'u', 32, 0,
+  /* 560 */ 'l', 'd', 'i', 'v', 'u', 32, 0,
+  /* 567 */ 'b', 'y', 't', 'e', 'r', 'e', 'v', 32, 0,
+  /* 576 */ 'b', 'i', 't', 'r', 'e', 'v', 32, 0,
+  /* 584 */ 'l', 'd', 'a', 'w', 32, 0,
+  /* 590 */ 'l', 'd', 'w', 32, 0,
+  /* 595 */ 'i', 'n', 'p', 'w', 32, 0,
+  /* 601 */ 's', 't', 'w', 32, 0,
+  /* 606 */ 'c', 'l', 'z', 32, 0,
+  /* 611 */ '#', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
+  /* 631 */ 's', 'e', 't', 32, 'k', 'e', 'p', ',', 32, 'r', '1', '1', 0,
+  /* 644 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
+  /* 657 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
+  /* 664 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
+  /* 674 */ '#', 'M', 'E', 'M', 'B', 'A', 'R', 'R', 'I', 'E', 'R', 0,
+  /* 686 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
+  /* 701 */ 'l', 'd', 'a', 'w', 32, 'r', '1', '1', ',', 32, 'c', 'p', '[', 0,
+  /* 715 */ 'l', 'd', 'w', 32, 'r', '1', '1', ',', 32, 'c', 'p', '[', 0,
+  /* 728 */ 'b', 'l', 'a', 32, 'c', 'p', '[', 0,
+  /* 736 */ 'm', 's', 'y', 'n', 'c', 32, 'r', 'e', 's', '[', 0,
+  /* 747 */ 's', 'e', 't', 'p', 's', 'c', 32, 'r', 'e', 's', '[', 0,
+  /* 759 */ 's', 'e', 't', 'c', 32, 'r', 'e', 's', '[', 0,
+  /* 769 */ 's', 'e', 't', 'd', 32, 'r', 'e', 's', '[', 0,
+  /* 779 */ 's', 'e', 't', 'c', 'l', 'k', 32, 'r', 'e', 's', '[', 0,
+  /* 791 */ 'm', 'j', 'o', 'i', 'n', 32, 'r', 'e', 's', '[', 0,
+  /* 802 */ 's', 'e', 't', 'n', 32, 'r', 'e', 's', '[', 0,
+  /* 812 */ 's', 'y', 'n', 'c', 'r', 32, 'r', 'e', 's', '[', 0,
+  /* 823 */ 'f', 'r', 'e', 'e', 'r', 32, 'r', 'e', 's', '[', 0,
+  /* 834 */ 'o', 'u', 't', 's', 'h', 'r', 32, 'r', 'e', 's', '[', 0,
+  /* 846 */ 'c', 'h', 'k', 'c', 't', 32, 'r', 'e', 's', '[', 0,
+  /* 857 */ 'o', 'u', 't', 'c', 't', 32, 'r', 'e', 's', '[', 0,
+  /* 868 */ 'c', 'l', 'r', 'p', 't', 32, 'r', 'e', 's', '[', 0,
+  /* 879 */ 's', 'e', 't', 'p', 't', 32, 'r', 'e', 's', '[', 0,
+  /* 890 */ 'o', 'u', 't', 't', 32, 'r', 'e', 's', '[', 0,
+  /* 900 */ 'o', 'u', 't', 32, 'r', 'e', 's', '[', 0,
+  /* 909 */ 'e', 'd', 'u', 32, 'r', 'e', 's', '[', 0,
+  /* 918 */ 'e', 'e', 'u', 32, 'r', 'e', 's', '[', 0,
+  /* 927 */ 's', 'e', 't', 'e', 'v', 32, 'r', 'e', 's', '[', 0,
+  /* 938 */ 's', 'e', 't', 'v', 32, 'r', 'e', 's', '[', 0,
+  /* 948 */ 'o', 'u', 't', 'p', 'w', 32, 'r', 'e', 's', '[', 0,
+  /* 959 */ 's', 'e', 't', 't', 'w', 32, 'r', 'e', 's', '[', 0,
+  /* 970 */ 's', 'e', 't', 'r', 'd', 'y', 32, 'r', 'e', 's', '[', 0,
+  /* 982 */ 's', 'e', 't', 32, 'p', 's', '[', 0,
+  /* 990 */ 's', 'e', 't', 32, 't', '[', 0,
+  /* 997 */ 'i', 'n', 'i', 't', 32, 't', '[', 0,
+  /* 1005 */ 's', 't', 'a', 'r', 't', 32, 't', '[', 0,
+  /* 1014 */ 'l', 'd', 'w', 32, 's', 'p', 'c', ',', 32, 's', 'p', '[', '1', ']', 0,
+  /* 1029 */ 's', 't', 'w', 32, 's', 'p', 'c', ',', 32, 's', 'p', '[', '1', ']', 0,
+  /* 1044 */ 'l', 'd', 'w', 32, 's', 's', 'r', ',', 32, 's', 'p', '[', '2', ']', 0,
+  /* 1059 */ 's', 't', 'w', 32, 's', 's', 'r', ',', 32, 's', 'p', '[', '2', ']', 0,
+  /* 1074 */ 'l', 'd', 'w', 32, 's', 'e', 'd', ',', 32, 's', 'p', '[', '3', ']', 0,
+  /* 1089 */ 's', 't', 'w', 32, 's', 'e', 'd', ',', 32, 's', 'p', '[', '3', ']', 0,
+  /* 1104 */ 'l', 'd', 'w', 32, 'e', 't', ',', 32, 's', 'p', '[', '4', ']', 0,
+  /* 1118 */ 's', 't', 'w', 32, 'e', 't', ',', 32, 's', 'p', '[', '4', ']', 0,
+  /* 1132 */ 's', 's', 'y', 'n', 'c', 0,
+  /* 1138 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'e', 'd', 0,
+  /* 1150 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'i', 'd', 0,
+  /* 1162 */ 'c', 'l', 'r', 'e', 0,
+  /* 1167 */ 'd', 'c', 'a', 'l', 'l', 0,
+  /* 1173 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'k', 'e', 'p', 0,
+  /* 1186 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'k', 's', 'p', 0,
+  /* 1199 */ 'd', 'e', 'n', 't', 's', 'p', 0,
+  /* 1206 */ 'd', 'r', 'e', 's', 't', 's', 'p', 0,
+  /* 1214 */ 't', 's', 'e', 't', 'm', 'r', 32, 'r', 0,
+  /* 1223 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'e', 't', 0,
+  /* 1235 */ 'f', 'r', 'e', 'e', 't', 0,
+  /* 1241 */ 'd', 'r', 'e', 't', 0,
+  /* 1246 */ 'k', 'r', 'e', 't', 0,
+  /* 1251 */ 'w', 'a', 'i', 't', 'e', 'u', 0,
+  };
+
+  // Emit the opcode for the instruction.
+  uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
+  // assert(Bits != 0 && "Cannot print this instruction.");
+#ifndef CAPSTONE_DIET
+  SStream_concat0(O, AsmStrs+(Bits & 2047)-1);
+#endif
+
+
+  if (strchr((const char *)AsmStrs+(Bits & 2047)-1, '[')) {
+    set_mem_access(MI, true, 0);
+  }
+
+  // Fragment 0 encoded into 2 bits for 4 unique commands.
+  //printf(">>%s\n", AsmStrs+(Bits & 2047)-1);
+  //printf("Frag-0: %u\n", (Bits >> 11) & 3);
+  switch ((Bits >> 11) & 3) {
+  default:   // unreachable.
+  case 0:
+    // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, CLRE_0R, DCALL_0R, DE...
+    // already done. this means we have to extract details out ourself.
+    XCore_insn_extract(MI, (const char *)AsmStrs+(Bits & 2047)-1);
+    return;
+    break;
+  case 1:
+    // ADD_2rus, ADD_3r, ADJCALLSTACKDOWN, ADJCALLSTACKUP, ANDNOT_2r, AND_3r,...
+    printOperand(MI, 0, O); 
+    break;
+  case 2:
+    // BR_JT, BR_JT32, CRC8_l4r, INITCP_2r, INITDP_2r, INITLR_l2r, INITPC_2r,...
+    printOperand(MI, 1, O); 
+    break;
+  case 3:
+    // OUTSHR_2r, TSETR_3r
+    printOperand(MI, 2, O); 
+    break;
+  }
+
+
+  // Fragment 1 encoded into 5 bits for 17 unique commands.
+  //printf("Frag-1: %u\n", (Bits >> 13) & 31);
+  switch ((Bits >> 13) & 31) {
+  default:   // unreachable.
+  case 0:
+    // ADD_2rus, ADD_3r, ANDNOT_2r, AND_3r, ASHR_l2rus, ASHR_l3r, BITREV_l2r,...
+    SStream_concat0(O, ", "); 
+    break;
+  case 1:
+    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BAU_1r, BLAT_lu6, BLAT_u6, BLA_1r, B...
+    return;
+    break;
+  case 2:
+    // BLACP_lu10, BLACP_u10, CLRPT_1R, EDU_1r, EEU_1r, FREER_1r, LDAWCP_lu6,...
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false, 0);
+    return;
+    break;
+  case 3:
+    // BR_JT, BR_JT32
+    SStream_concat0(O, "\n"); 
+    break;
+  case 4:
+    // CHKCT_2r, CHKCT_rus, OUTCT_2r, OUTCT_rus, OUTPW_l2rus, OUTSHR_2r, OUTT...
+    SStream_concat0(O, "], "); 
+    set_mem_access(MI, false, 0);
+    break;
+  case 5:
+    // EEF_2r, EET_2r, ENDIN_2r, GETD_l2r, GETN_l2r, GETST_2r, GETTS_2r, INCT...
+    SStream_concat0(O, ", res["); 
+    set_mem_access(MI, true, 0);
+    break;
+  case 6:
+    // GETPS_l2r
+    SStream_concat0(O, ", ps["); 
+    set_mem_access(MI, true, 0);
+    printOperand(MI, 1, O); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false, 0);
+    return;
+    break;
+  case 7:
+    // INITCP_2r
+    SStream_concat0(O, "]:cp, "); 
+    set_mem_access(MI, false, XCORE_REG_CP);
+    printOperand(MI, 0, O); 
+    return;
+    break;
+  case 8:
+    // INITDP_2r
+    SStream_concat0(O, "]:dp, "); 
+    set_mem_access(MI, false, XCORE_REG_DP);
+    printOperand(MI, 0, O); 
+    return;
+    break;
+  case 9:
+    // INITLR_l2r
+    SStream_concat0(O, "]:lr, "); 
+    set_mem_access(MI, false, XCORE_REG_LR);
+    printOperand(MI, 0, O); 
+    return;
+    break;
+  case 10:
+    // INITPC_2r
+    SStream_concat0(O, "]:pc, "); 
+    set_mem_access(MI, false, XCORE_REG_PC);
+    printOperand(MI, 0, O); 
+    return;
+    break;
+  case 11:
+    // INITSP_2r
+    SStream_concat0(O, "]:sp, "); 
+    set_mem_access(MI, false, XCORE_REG_SP);
+    printOperand(MI, 0, O); 
+    return;
+    break;
+  case 12:
+    // LDAWDP_lru6, LDAWDP_ru6, LDWDP_lru6, LDWDP_ru6, STWDP_lru6, STWDP_ru6
+    SStream_concat0(O, ", dp["); 
+    set_mem_access(MI, true, XCORE_REG_DP);
+    printOperand(MI, 1, O); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false, 0);
+    return;
+    break;
+  case 13:
+    // LDAWSP_lru6, LDAWSP_ru6, LDWSP_lru6, LDWSP_ru6, STWSP_lru6, STWSP_ru6
+    SStream_concat0(O, ", sp["); 
+    set_mem_access(MI, true, XCORE_REG_SP);
+    printOperand(MI, 1, O); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false, 0);
+    return;
+    break;
+  case 14:
+    // LDWCP_lru6, LDWCP_ru6
+    SStream_concat0(O, ", cp["); 
+    set_mem_access(MI, true, XCORE_REG_CP);
+    printOperand(MI, 1, O); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false, 0);
+    return;
+    break;
+  case 15:
+    // SETEV_1r, SETV_1r
+    SStream_concat0(O, "], r11"); 
+    set_mem_access(MI, false, 0);
+    return;
+    break;
+  case 16:
+    // TSETR_3r
+    SStream_concat0(O, "]:r"); 
+    set_mem_access(MI, false, 0);
+    printOperand(MI, 0, O); 
+    SStream_concat0(O, ", "); 
+    printOperand(MI, 1, O); 
+    return;
+    break;
+  }
+
+
+  // Fragment 2 encoded into 3 bits for 5 unique commands.
+  //printf("Frag-2: %u\n", (Bits >> 18) & 7);
+  switch ((Bits >> 18) & 7) {
+  default:   // unreachable.
+  case 0:
+    // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, BITREV_l2r, BRBF_lru6,...
+    printOperand(MI, 1, O); 
+    break;
+  case 1:
+    // ANDNOT_2r, CRC_l3r, INSHR_2r, SEXT_2r, SEXT_rus, ZEXT_2r, ZEXT_rus
+    printOperand(MI, 2, O); 
+    break;
+  case 2:
+    // BR_JT
+    printInlineJT(MI, 0, O); 
+    return;
+    break;
+  case 3:
+    // BR_JT32
+    printInlineJT32(MI, 0, O); 
+    return;
+    break;
+  case 4:
+    // CRC8_l4r, LADD_l5r, LSUB_l5r, OUTPW_l2rus
+    printOperand(MI, 0, O); 
+    SStream_concat0(O, ", "); 
+    break;
+  }
+
+
+  // Fragment 3 encoded into 3 bits for 8 unique commands.
+  //printf("Frag-3: %u\n", (Bits >> 21) & 7);
+  switch ((Bits >> 21) & 7) {
+  default:   // unreachable.
+  case 0:
+    // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, CRC_l3r, DIVS_l3r, DIV...
+    SStream_concat0(O, ", "); 
+    break;
+  case 1:
+    // ANDNOT_2r, BITREV_l2r, BRBF_lru6, BRBF_ru6, BRBT_lru6, BRBT_ru6, BRFF_...
+    return;
+    break;
+  case 2:
+    // CRC8_l4r
+    printOperand(MI, 3, O); 
+    SStream_concat0(O, ", "); 
+    printOperand(MI, 4, O); 
+    return;
+    break;
+  case 3:
+    // EEF_2r, EET_2r, ENDIN_2r, GETD_l2r, GETN_l2r, GETST_2r, GETTS_2r, INCT...
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false, 0);
+    return;
+    break;
+  case 4:
+    // INPW_l2rus
+    SStream_concat0(O, "], "); 
+    set_mem_access(MI, false, 0);
+    printOperand(MI, 2, O); 
+    return;
+    break;
+  case 5:
+    // LADD_l5r, LSUB_l5r, OUTPW_l2rus
+    printOperand(MI, 2, O); 
+    break;
+  case 6:
+    // LD16S_3r, LD8U_3r, LDA16F_l3r, LDAWF_l2rus, LDAWF_l3r, LDW_2rus, LDW_3...
+    SStream_concat0(O, "["); 
+    set_mem_access(MI, true, 0xffff);
+    printOperand(MI, 2, O); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false, 0);
+    return;
+    break;
+  case 7:
+    // LDA16B_l3r, LDAWB_l2rus, LDAWB_l3r
+    SStream_concat0(O, "[-"); 
+    set_mem_access(MI, true, -0xffff);
+    printOperand(MI, 2, O); 
+    SStream_concat0(O, "]"); 
+    set_mem_access(MI, false, 0);
+    return;
+    break;
+  }
+
+
+  // Fragment 4 encoded into 3 bits for 5 unique commands.
+  //printf("Frag-4: %u\n", (Bits >> 24) & 7);
+  switch ((Bits >> 24) & 7) {
+  default:   // unreachable.
+  case 0:
+    // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, DIVS_l3r, DIVU_l3r, EQ...
+    printOperand(MI, 2, O); 
+    break;
+  case 1:
+    // CRC_l3r
+    printOperand(MI, 3, O); 
+    return;
+    break;
+  case 2:
+    // LADD_l5r, LSUB_l5r
+    SStream_concat0(O, ", "); 
+    printOperand(MI, 3, O); 
+    SStream_concat0(O, ", "); 
+    printOperand(MI, 4, O); 
+    return;
+    break;
+  case 3:
+    // LDIVU_l5r, MACCS_l4r, MACCU_l4r
+    printOperand(MI, 4, O); 
+    SStream_concat0(O, ", "); 
+    break;
+  case 4:
+    // OUTPW_l2rus
+    return;
+    break;
+  }
+
+
+  // Fragment 5 encoded into 2 bits for 4 unique commands.
+  //printf("Frag-5: %u\n", (Bits >> 27) & 3);
+  switch ((Bits >> 27) & 3) {
+  default:   // unreachable.
+  case 0:
+    // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, DIVS_l3r, DIVU_l3r, EQ...
+    return;
+    break;
+  case 1:
+    // LDIVU_l5r
+    printOperand(MI, 2, O); 
+    SStream_concat0(O, ", "); 
+    printOperand(MI, 3, O); 
+    return;
+    break;
+  case 2:
+    // LMUL_l6r
+    SStream_concat0(O, ", "); 
+    printOperand(MI, 3, O); 
+    SStream_concat0(O, ", "); 
+    printOperand(MI, 4, O); 
+    SStream_concat0(O, ", "); 
+    printOperand(MI, 5, O); 
+    return;
+    break;
+  case 3:
+    // MACCS_l4r, MACCU_l4r
+    printOperand(MI, 5, O); 
+    return;
+    break;
+  }
+}
+
+
+/// getRegisterName - This method is automatically generated by tblgen
+/// from the register set description.  This returns the assembler name
+/// for the specified register.
+static const char *getRegisterName(unsigned RegNo)
+{
+  // assert(RegNo && RegNo < 17 && "Invalid register number!");
+
+#ifndef CAPSTONE_DIET
+  static const char AsmStrs[] = {
+  /* 0 */ 'r', '1', '0', 0,
+  /* 4 */ 'r', '0', 0,
+  /* 7 */ 'r', '1', '1', 0,
+  /* 11 */ 'r', '1', 0,
+  /* 14 */ 'r', '2', 0,
+  /* 17 */ 'r', '3', 0,
+  /* 20 */ 'r', '4', 0,
+  /* 23 */ 'r', '5', 0,
+  /* 26 */ 'r', '6', 0,
+  /* 29 */ 'r', '7', 0,
+  /* 32 */ 'r', '8', 0,
+  /* 35 */ 'r', '9', 0,
+  /* 38 */ 'c', 'p', 0,
+  /* 41 */ 'd', 'p', 0,
+  /* 44 */ 's', 'p', 0,
+  /* 47 */ 'l', 'r', 0,
+  };
+
+  static const uint8_t RegAsmOffset[] = {
+    38, 41, 47, 44, 4, 11, 14, 17, 20, 23, 26, 29, 32, 35, 
+    0, 7, 
+  };
+
+  //int i;
+  //for (i = 0; i < sizeof(RegAsmOffset); i++)
+  //     printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
+  //printf("*************************\n");
+  return AsmStrs+RegAsmOffset[RegNo-1];
+#else
+  return NULL;
+#endif
+}
diff --git a/capstone/arch/XCore/XCoreGenDisassemblerTables.inc b/capstone/arch/XCore/XCoreGenDisassemblerTables.inc
new file mode 100644
index 000000000..fe4e67080
--- /dev/null
+++ b/capstone/arch/XCore/XCoreGenDisassemblerTables.inc
@@ -0,0 +1,853 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|* * XCore Disassembler                                                         *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#include "../../MCInst.h"
+#include "../../LEB128.h"
+
+// Helper function for extracting fields from encoded instructions.
+#define FieldFromInstruction(fname, InsnType) \
+static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
+{ \
+  InsnType fieldMask; \
+  if (numBits == sizeof(InsnType)*8) \
+    fieldMask = (InsnType)(-1LL); \
+  else \
+    fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
+  return (insn & fieldMask) >> startBit; \
+}
+
+static const uint8_t DecoderTable16[] = {
+/* 0 */       MCD_OPC_ExtractField, 11, 5,  // Inst{15-11} ...
+/* 3 */       MCD_OPC_FilterValue, 0, 108, 0, // Skip to: 115
+/* 7 */       MCD_OPC_ExtractField, 0, 11,  // Inst{10-0} ...
+/* 10 */      MCD_OPC_FilterValue, 236, 15, 4, 0, // Skip to: 19
+/* 15 */      MCD_OPC_Decode, 243, 1, 0, // Opcode: WAITEU_0R
+/* 19 */      MCD_OPC_FilterValue, 237, 15, 3, 0, // Skip to: 27
+/* 24 */      MCD_OPC_Decode, 59, 0, // Opcode: CLRE_0R
+/* 27 */      MCD_OPC_FilterValue, 238, 15, 4, 0, // Skip to: 36
+/* 32 */      MCD_OPC_Decode, 218, 1, 0, // Opcode: SSYNC_0r
+/* 36 */      MCD_OPC_FilterValue, 239, 15, 3, 0, // Skip to: 44
+/* 41 */      MCD_OPC_Decode, 93, 0, // Opcode: FREET_0R
+/* 44 */      MCD_OPC_FilterValue, 252, 15, 3, 0, // Skip to: 52
+/* 49 */      MCD_OPC_Decode, 68, 0, // Opcode: DCALL_0R
+/* 52 */      MCD_OPC_FilterValue, 253, 15, 3, 0, // Skip to: 60
+/* 57 */      MCD_OPC_Decode, 125, 0, // Opcode: KRET_0R
+/* 60 */      MCD_OPC_FilterValue, 254, 15, 3, 0, // Skip to: 68
+/* 65 */      MCD_OPC_Decode, 74, 0, // Opcode: DRET_0R
+/* 68 */      MCD_OPC_FilterValue, 255, 15, 4, 0, // Skip to: 77
+/* 73 */      MCD_OPC_Decode, 199, 1, 0, // Opcode: SETKEP_0R
+/* 77 */      MCD_OPC_ExtractField, 4, 7,  // Inst{10-4} ...
+/* 80 */      MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 87
+/* 84 */      MCD_OPC_Decode, 77, 1, // Opcode: EDU_1r
+/* 87 */      MCD_OPC_FilterValue, 127, 3, 0, // Skip to: 94
+/* 91 */      MCD_OPC_Decode, 80, 1, // Opcode: EEU_1r
+/* 94 */      MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 97 */      MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 104
+/* 101 */     MCD_OPC_Decode, 111, 2, // Opcode: INITPC_2r
+/* 104 */     MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 111
+/* 108 */     MCD_OPC_Decode, 105, 2, // Opcode: GETST_2r
+/* 111 */     MCD_OPC_Decode, 230, 1, 3, // Opcode: STW_2rus
+/* 115 */     MCD_OPC_FilterValue, 1, 114, 0, // Skip to: 233
+/* 119 */     MCD_OPC_ExtractField, 0, 11,  // Inst{10-0} ...
+/* 122 */     MCD_OPC_FilterValue, 236, 15, 4, 0, // Skip to: 131
+/* 127 */     MCD_OPC_Decode, 152, 1, 0, // Opcode: LDSPC_0R
+/* 131 */     MCD_OPC_FilterValue, 237, 15, 4, 0, // Skip to: 140
+/* 136 */     MCD_OPC_Decode, 223, 1, 0, // Opcode: STSPC_0R
+/* 140 */     MCD_OPC_FilterValue, 238, 15, 4, 0, // Skip to: 149
+/* 145 */     MCD_OPC_Decode, 153, 1, 0, // Opcode: LDSSR_0R
+/* 149 */     MCD_OPC_FilterValue, 239, 15, 4, 0, // Skip to: 158
+/* 154 */     MCD_OPC_Decode, 224, 1, 0, // Opcode: STSSR_0R
+/* 158 */     MCD_OPC_FilterValue, 252, 15, 4, 0, // Skip to: 167
+/* 163 */     MCD_OPC_Decode, 222, 1, 0, // Opcode: STSED_0R
+/* 167 */     MCD_OPC_FilterValue, 253, 15, 4, 0, // Skip to: 176
+/* 172 */     MCD_OPC_Decode, 221, 1, 0, // Opcode: STET_0R
+/* 176 */     MCD_OPC_FilterValue, 254, 15, 3, 0, // Skip to: 184
+/* 181 */     MCD_OPC_Decode, 95, 0, // Opcode: GETED_0R
+/* 184 */     MCD_OPC_FilterValue, 255, 15, 3, 0, // Skip to: 192
+/* 189 */     MCD_OPC_Decode, 96, 0, // Opcode: GETET_0R
+/* 192 */     MCD_OPC_ExtractField, 4, 7,  // Inst{10-4} ...
+/* 195 */     MCD_OPC_FilterValue, 126, 4, 0, // Skip to: 203
+/* 199 */     MCD_OPC_Decode, 242, 1, 1, // Opcode: WAITET_1R
+/* 203 */     MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 211
+/* 207 */     MCD_OPC_Decode, 241, 1, 1, // Opcode: WAITEF_1R
+/* 211 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 214 */     MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 221
+/* 218 */     MCD_OPC_Decode, 109, 2, // Opcode: INITDP_2r
+/* 221 */     MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 229
+/* 225 */     MCD_OPC_Decode, 183, 1, 4, // Opcode: OUTT_2r
+/* 229 */     MCD_OPC_Decode, 163, 1, 3, // Opcode: LDW_2rus
+/* 233 */     MCD_OPC_FilterValue, 2, 100, 0, // Skip to: 337
+/* 237 */     MCD_OPC_ExtractField, 0, 11,  // Inst{10-0} ...
+/* 240 */     MCD_OPC_FilterValue, 236, 15, 3, 0, // Skip to: 248
+/* 245 */     MCD_OPC_Decode, 69, 0, // Opcode: DENTSP_0R
+/* 248 */     MCD_OPC_FilterValue, 237, 15, 3, 0, // Skip to: 256
+/* 253 */     MCD_OPC_Decode, 73, 0, // Opcode: DRESTSP_0R
+/* 256 */     MCD_OPC_FilterValue, 238, 15, 3, 0, // Skip to: 264
+/* 261 */     MCD_OPC_Decode, 97, 0, // Opcode: GETID_0R
+/* 264 */     MCD_OPC_FilterValue, 239, 15, 3, 0, // Skip to: 272
+/* 269 */     MCD_OPC_Decode, 98, 0, // Opcode: GETKEP_0R
+/* 272 */     MCD_OPC_FilterValue, 252, 15, 3, 0, // Skip to: 280
+/* 277 */     MCD_OPC_Decode, 99, 0, // Opcode: GETKSP_0R
+/* 280 */     MCD_OPC_FilterValue, 253, 15, 4, 0, // Skip to: 289
+/* 285 */     MCD_OPC_Decode, 151, 1, 0, // Opcode: LDSED_0R
+/* 289 */     MCD_OPC_FilterValue, 254, 15, 4, 0, // Skip to: 298
+/* 294 */     MCD_OPC_Decode, 149, 1, 0, // Opcode: LDET_0R
+/* 298 */     MCD_OPC_ExtractField, 4, 7,  // Inst{10-4} ...
+/* 301 */     MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 308
+/* 305 */     MCD_OPC_Decode, 92, 1, // Opcode: FREER_1r
+/* 308 */     MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 316
+/* 312 */     MCD_OPC_Decode, 171, 1, 1, // Opcode: MJOIN_1r
+/* 316 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 319 */     MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 326
+/* 323 */     MCD_OPC_Decode, 112, 2, // Opcode: INITSP_2r
+/* 326 */     MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 334
+/* 330 */     MCD_OPC_Decode, 197, 1, 4, // Opcode: SETD_2r
+/* 334 */     MCD_OPC_Decode, 23, 5, // Opcode: ADD_3r
+/* 337 */     MCD_OPC_FilterValue, 3, 41, 0, // Skip to: 382
+/* 341 */     MCD_OPC_ExtractField, 4, 7,  // Inst{10-4} ...
+/* 344 */     MCD_OPC_FilterValue, 126, 4, 0, // Skip to: 352
+/* 348 */     MCD_OPC_Decode, 240, 1, 1, // Opcode: TSTART_1R
+/* 352 */     MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 360
+/* 356 */     MCD_OPC_Decode, 174, 1, 1, // Opcode: MSYNC_1r
+/* 360 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 363 */     MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 370
+/* 367 */     MCD_OPC_Decode, 108, 2, // Opcode: INITCP_2r
+/* 370 */     MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 378
+/* 374 */     MCD_OPC_Decode, 238, 1, 6, // Opcode: TSETMR_2r
+/* 378 */     MCD_OPC_Decode, 233, 1, 5, // Opcode: SUB_3r
+/* 382 */     MCD_OPC_FilterValue, 4, 30, 0, // Skip to: 416
+/* 386 */     MCD_OPC_ExtractField, 4, 7,  // Inst{10-4} ...
+/* 389 */     MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 396
+/* 393 */     MCD_OPC_Decode, 36, 1, // Opcode: BLA_1r
+/* 396 */     MCD_OPC_FilterValue, 127, 3, 0, // Skip to: 403
+/* 400 */     MCD_OPC_Decode, 30, 1, // Opcode: BAU_1r
+/* 403 */     MCD_OPC_CheckField, 4, 1, 1, 3, 0, // Skip to: 412
+/* 409 */     MCD_OPC_Decode, 79, 2, // Opcode: EET_2r
+/* 412 */     MCD_OPC_Decode, 215, 1, 5, // Opcode: SHL_3r
+/* 416 */     MCD_OPC_FilterValue, 5, 39, 0, // Skip to: 459
+/* 420 */     MCD_OPC_ExtractField, 4, 7,  // Inst{10-4} ...
+/* 423 */     MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 430
+/* 427 */     MCD_OPC_Decode, 53, 1, // Opcode: BRU_1r
+/* 430 */     MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 438
+/* 434 */     MCD_OPC_Decode, 205, 1, 1, // Opcode: SETSP_1r
+/* 438 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 441 */     MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 448
+/* 445 */     MCD_OPC_Decode, 26, 7, // Opcode: ANDNOT_2r
+/* 448 */     MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 455
+/* 452 */     MCD_OPC_Decode, 78, 2, // Opcode: EEF_2r
+/* 455 */     MCD_OPC_Decode, 217, 1, 5, // Opcode: SHR_3r
+/* 459 */     MCD_OPC_FilterValue, 6, 41, 0, // Skip to: 504
+/* 463 */     MCD_OPC_ExtractField, 4, 7,  // Inst{10-4} ...
+/* 466 */     MCD_OPC_FilterValue, 126, 4, 0, // Skip to: 474
+/* 470 */     MCD_OPC_Decode, 196, 1, 1, // Opcode: SETDP_1r
+/* 474 */     MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 482
+/* 478 */     MCD_OPC_Decode, 192, 1, 1, // Opcode: SETCP_1r
+/* 482 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 485 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 493
+/* 489 */     MCD_OPC_Decode, 212, 1, 7, // Opcode: SEXT_2r
+/* 493 */     MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 501
+/* 497 */     MCD_OPC_Decode, 213, 1, 8, // Opcode: SEXT_rus
+/* 501 */     MCD_OPC_Decode, 86, 5, // Opcode: EQ_3r
+/* 504 */     MCD_OPC_FilterValue, 7, 39, 0, // Skip to: 547
+/* 508 */     MCD_OPC_ExtractField, 4, 7,  // Inst{10-4} ...
+/* 511 */     MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 518
+/* 515 */     MCD_OPC_Decode, 70, 1, // Opcode: DGETREG_1r
+/* 518 */     MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 526
+/* 522 */     MCD_OPC_Decode, 198, 1, 1, // Opcode: SETEV_1r
+/* 526 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 529 */     MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 536
+/* 533 */     MCD_OPC_Decode, 106, 2, // Opcode: GETTS_2r
+/* 536 */     MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 544
+/* 540 */     MCD_OPC_Decode, 203, 1, 4, // Opcode: SETPT_2r
+/* 544 */     MCD_OPC_Decode, 27, 5, // Opcode: AND_3r
+/* 547 */     MCD_OPC_FilterValue, 8, 41, 0, // Skip to: 592
+/* 551 */     MCD_OPC_ExtractField, 4, 7,  // Inst{10-4} ...
+/* 554 */     MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 561
+/* 558 */     MCD_OPC_Decode, 118, 1, // Opcode: KCALL_1r
+/* 561 */     MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 569
+/* 565 */     MCD_OPC_Decode, 211, 1, 1, // Opcode: SETV_1r
+/* 569 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 572 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 580
+/* 576 */     MCD_OPC_Decode, 245, 1, 7, // Opcode: ZEXT_2r
+/* 580 */     MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 588
+/* 584 */     MCD_OPC_Decode, 246, 1, 8, // Opcode: ZEXT_rus
+/* 588 */     MCD_OPC_Decode, 178, 1, 5, // Opcode: OR_3r
+/* 592 */     MCD_OPC_FilterValue, 9, 40, 0, // Skip to: 636
+/* 596 */     MCD_OPC_ExtractField, 4, 7,  // Inst{10-4} ...
+/* 599 */     MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 606
+/* 603 */     MCD_OPC_Decode, 75, 1, // Opcode: ECALLF_1r
+/* 606 */     MCD_OPC_FilterValue, 127, 3, 0, // Skip to: 613
+/* 610 */     MCD_OPC_Decode, 76, 1, // Opcode: ECALLT_1r
+/* 613 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 616 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 624
+/* 620 */     MCD_OPC_Decode, 179, 1, 2, // Opcode: OUTCT_2r
+/* 624 */     MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 632
+/* 628 */     MCD_OPC_Decode, 180, 1, 9, // Opcode: OUTCT_rus
+/* 632 */     MCD_OPC_Decode, 164, 1, 5, // Opcode: LDW_3r
+/* 636 */     MCD_OPC_FilterValue, 10, 19, 0, // Skip to: 659
+/* 640 */     MCD_OPC_ExtractField, 10, 1,  // Inst{10} ...
+/* 643 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 651
+/* 647 */     MCD_OPC_Decode, 226, 1, 10, // Opcode: STWDP_ru6
+/* 651 */     MCD_OPC_FilterValue, 1, 54, 2, // Skip to: 1221
+/* 655 */     MCD_OPC_Decode, 229, 1, 10, // Opcode: STWSP_ru6
+/* 659 */     MCD_OPC_FilterValue, 11, 19, 0, // Skip to: 682
+/* 663 */     MCD_OPC_ExtractField, 10, 1,  // Inst{10} ...
+/* 666 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 674
+/* 670 */     MCD_OPC_Decode, 159, 1, 10, // Opcode: LDWDP_ru6
+/* 674 */     MCD_OPC_FilterValue, 1, 31, 2, // Skip to: 1221
+/* 678 */     MCD_OPC_Decode, 162, 1, 10, // Opcode: LDWSP_ru6
+/* 682 */     MCD_OPC_FilterValue, 12, 19, 0, // Skip to: 705
+/* 686 */     MCD_OPC_ExtractField, 10, 1,  // Inst{10} ...
+/* 689 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 697
+/* 693 */     MCD_OPC_Decode, 141, 1, 10, // Opcode: LDAWDP_ru6
+/* 697 */     MCD_OPC_FilterValue, 1, 8, 2, // Skip to: 1221
+/* 701 */     MCD_OPC_Decode, 146, 1, 10, // Opcode: LDAWSP_ru6
+/* 705 */     MCD_OPC_FilterValue, 13, 19, 0, // Skip to: 728
+/* 709 */     MCD_OPC_ExtractField, 10, 1,  // Inst{10} ...
+/* 712 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 720
+/* 716 */     MCD_OPC_Decode, 148, 1, 10, // Opcode: LDC_ru6
+/* 720 */     MCD_OPC_FilterValue, 1, 241, 1, // Skip to: 1221
+/* 724 */     MCD_OPC_Decode, 156, 1, 10, // Opcode: LDWCP_ru6
+/* 728 */     MCD_OPC_FilterValue, 14, 80, 0, // Skip to: 812
+/* 732 */     MCD_OPC_ExtractField, 10, 1,  // Inst{10} ...
+/* 735 */     MCD_OPC_FilterValue, 0, 34, 0, // Skip to: 773
+/* 739 */     MCD_OPC_ExtractField, 6, 4,  // Inst{9-6} ...
+/* 742 */     MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 749
+/* 746 */     MCD_OPC_Decode, 52, 11, // Opcode: BRFU_u6
+/* 749 */     MCD_OPC_FilterValue, 13, 3, 0, // Skip to: 756
+/* 753 */     MCD_OPC_Decode, 35, 11, // Opcode: BLAT_u6
+/* 756 */     MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 763
+/* 760 */     MCD_OPC_Decode, 88, 11, // Opcode: EXTDP_u6
+/* 763 */     MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 770
+/* 767 */     MCD_OPC_Decode, 120, 11, // Opcode: KCALL_u6
+/* 770 */     MCD_OPC_Decode, 50, 12, // Opcode: BRFT_ru6
+/* 773 */     MCD_OPC_FilterValue, 1, 188, 1, // Skip to: 1221
+/* 777 */     MCD_OPC_ExtractField, 6, 4,  // Inst{9-6} ...
+/* 780 */     MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 787
+/* 784 */     MCD_OPC_Decode, 46, 13, // Opcode: BRBU_u6
+/* 787 */     MCD_OPC_FilterValue, 13, 3, 0, // Skip to: 794
+/* 791 */     MCD_OPC_Decode, 84, 11, // Opcode: ENTSP_u6
+/* 794 */     MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 801
+/* 798 */     MCD_OPC_Decode, 90, 11, // Opcode: EXTSP_u6
+/* 801 */     MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 809
+/* 805 */     MCD_OPC_Decode, 189, 1, 11, // Opcode: RETSP_u6
+/* 809 */     MCD_OPC_Decode, 44, 14, // Opcode: BRBT_ru6
+/* 812 */     MCD_OPC_FilterValue, 15, 67, 0, // Skip to: 883
+/* 816 */     MCD_OPC_ExtractField, 10, 1,  // Inst{10} ...
+/* 819 */     MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 858
+/* 823 */     MCD_OPC_ExtractField, 6, 4,  // Inst{9-6} ...
+/* 826 */     MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 833
+/* 830 */     MCD_OPC_Decode, 64, 11, // Opcode: CLRSR_u6
+/* 833 */     MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 841
+/* 837 */     MCD_OPC_Decode, 209, 1, 11, // Opcode: SETSR_u6
+/* 841 */     MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 848
+/* 845 */     MCD_OPC_Decode, 122, 11, // Opcode: KENTSP_u6
+/* 848 */     MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 855
+/* 852 */     MCD_OPC_Decode, 124, 11, // Opcode: KRESTSP_u6
+/* 855 */     MCD_OPC_Decode, 48, 12, // Opcode: BRFF_ru6
+/* 858 */     MCD_OPC_FilterValue, 1, 103, 1, // Skip to: 1221
+/* 862 */     MCD_OPC_ExtractField, 6, 4,  // Inst{9-6} ...
+/* 865 */     MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 872
+/* 869 */     MCD_OPC_Decode, 104, 11, // Opcode: GETSR_u6
+/* 872 */     MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 880
+/* 876 */     MCD_OPC_Decode, 139, 1, 11, // Opcode: LDAWCP_u6
+/* 880 */     MCD_OPC_Decode, 42, 14, // Opcode: BRBF_ru6
+/* 883 */     MCD_OPC_FilterValue, 16, 38, 0, // Skip to: 925
+/* 887 */     MCD_OPC_ExtractField, 4, 7,  // Inst{10-4} ...
+/* 890 */     MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 897
+/* 894 */     MCD_OPC_Decode, 60, 1, // Opcode: CLRPT_1R
+/* 897 */     MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 905
+/* 901 */     MCD_OPC_Decode, 234, 1, 1, // Opcode: SYNCR_1r
+/* 905 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 908 */     MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 915
+/* 912 */     MCD_OPC_Decode, 102, 9, // Opcode: GETR_rus
+/* 915 */     MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 922
+/* 919 */     MCD_OPC_Decode, 107, 2, // Opcode: INCT_2r
+/* 922 */     MCD_OPC_Decode, 127, 5, // Opcode: LD16S_3r
+/* 925 */     MCD_OPC_FilterValue, 17, 22, 0, // Skip to: 951
+/* 929 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 932 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 940
+/* 936 */     MCD_OPC_Decode, 177, 1, 2, // Opcode: NOT
+/* 940 */     MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 947
+/* 944 */     MCD_OPC_Decode, 115, 2, // Opcode: INT_2r
+/* 947 */     MCD_OPC_Decode, 128, 1, 5, // Opcode: LD8U_3r
+/* 951 */     MCD_OPC_FilterValue, 18, 21, 0, // Skip to: 976
+/* 955 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 958 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 966
+/* 962 */     MCD_OPC_Decode, 176, 1, 2, // Opcode: NEG
+/* 966 */     MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 973
+/* 970 */     MCD_OPC_Decode, 82, 2, // Opcode: ENDIN_2r
+/* 973 */     MCD_OPC_Decode, 22, 3, // Opcode: ADD_2rus
+/* 976 */     MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 984
+/* 980 */     MCD_OPC_Decode, 232, 1, 3, // Opcode: SUB_2rus
+/* 984 */     MCD_OPC_FilterValue, 20, 23, 0, // Skip to: 1011
+/* 988 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 991 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 999
+/* 995 */     MCD_OPC_Decode, 172, 1, 2, // Opcode: MKMSK_2r
+/* 999 */     MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1007
+/* 1003 */    MCD_OPC_Decode, 173, 1, 15, // Opcode: MKMSK_rus
+/* 1007 */    MCD_OPC_Decode, 214, 1, 16, // Opcode: SHL_2rus
+/* 1011 */    MCD_OPC_FilterValue, 21, 23, 0, // Skip to: 1038
+/* 1015 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 1018 */    MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1026
+/* 1022 */    MCD_OPC_Decode, 184, 1, 4, // Opcode: OUT_2r
+/* 1026 */    MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1034
+/* 1030 */    MCD_OPC_Decode, 182, 1, 7, // Opcode: OUTSHR_2r
+/* 1034 */    MCD_OPC_Decode, 216, 1, 16, // Opcode: SHR_2rus
+/* 1038 */    MCD_OPC_FilterValue, 22, 20, 0, // Skip to: 1062
+/* 1042 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 1045 */    MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1052
+/* 1049 */    MCD_OPC_Decode, 116, 2, // Opcode: IN_2r
+/* 1052 */    MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 1059
+/* 1056 */    MCD_OPC_Decode, 114, 7, // Opcode: INSHR_2r
+/* 1059 */    MCD_OPC_Decode, 85, 3, // Opcode: EQ_2rus
+/* 1062 */    MCD_OPC_FilterValue, 23, 23, 0, // Skip to: 1089
+/* 1066 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 1069 */    MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1077
+/* 1073 */    MCD_OPC_Decode, 185, 1, 2, // Opcode: PEEK_2r
+/* 1077 */    MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1085
+/* 1081 */    MCD_OPC_Decode, 235, 1, 2, // Opcode: TESTCT_2r
+/* 1085 */    MCD_OPC_Decode, 239, 1, 17, // Opcode: TSETR_3r
+/* 1089 */    MCD_OPC_FilterValue, 24, 23, 0, // Skip to: 1116
+/* 1093 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 1096 */    MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1104
+/* 1100 */    MCD_OPC_Decode, 201, 1, 4, // Opcode: SETPSC_2r
+/* 1104 */    MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1112
+/* 1108 */    MCD_OPC_Decode, 237, 1, 2, // Opcode: TESTWCT_2r
+/* 1112 */    MCD_OPC_Decode, 166, 1, 5, // Opcode: LSS_3r
+/* 1116 */    MCD_OPC_FilterValue, 25, 21, 0, // Skip to: 1141
+/* 1120 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 1123 */    MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1130
+/* 1127 */    MCD_OPC_Decode, 57, 2, // Opcode: CHKCT_2r
+/* 1130 */    MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 1137
+/* 1134 */    MCD_OPC_Decode, 58, 15, // Opcode: CHKCT_rus
+/* 1137 */    MCD_OPC_Decode, 168, 1, 5, // Opcode: LSU_3r
+/* 1141 */    MCD_OPC_FilterValue, 26, 17, 0, // Skip to: 1162
+/* 1145 */    MCD_OPC_ExtractField, 10, 1,  // Inst{10} ...
+/* 1148 */    MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1155
+/* 1152 */    MCD_OPC_Decode, 40, 18, // Opcode: BLRF_u10
+/* 1155 */    MCD_OPC_FilterValue, 1, 62, 0, // Skip to: 1221
+/* 1159 */    MCD_OPC_Decode, 38, 19, // Opcode: BLRB_u10
+/* 1162 */    MCD_OPC_FilterValue, 27, 19, 0, // Skip to: 1185
+/* 1166 */    MCD_OPC_ExtractField, 10, 1,  // Inst{10} ...
+/* 1169 */    MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1177
+/* 1173 */    MCD_OPC_Decode, 135, 1, 18, // Opcode: LDAPF_u10
+/* 1177 */    MCD_OPC_FilterValue, 1, 40, 0, // Skip to: 1221
+/* 1181 */    MCD_OPC_Decode, 132, 1, 19, // Opcode: LDAPB_u10
+/* 1185 */    MCD_OPC_FilterValue, 28, 18, 0, // Skip to: 1207
+/* 1189 */    MCD_OPC_ExtractField, 10, 1,  // Inst{10} ...
+/* 1192 */    MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1199
+/* 1196 */    MCD_OPC_Decode, 33, 18, // Opcode: BLACP_u10
+/* 1199 */    MCD_OPC_FilterValue, 1, 18, 0, // Skip to: 1221
+/* 1203 */    MCD_OPC_Decode, 157, 1, 18, // Opcode: LDWCP_u10
+/* 1207 */    MCD_OPC_FilterValue, 29, 10, 0, // Skip to: 1221
+/* 1211 */    MCD_OPC_CheckField, 10, 1, 0, 4, 0, // Skip to: 1221
+/* 1217 */    MCD_OPC_Decode, 195, 1, 12, // Opcode: SETC_ru6
+/* 1221 */    MCD_OPC_Fail,
+  0
+};
+
+static const uint8_t DecoderTable32[] = {
+/* 0 */       MCD_OPC_ExtractField, 27, 5,  // Inst{31-27} ...
+/* 3 */       MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 96
+/* 7 */       MCD_OPC_ExtractField, 11, 5,  // Inst{15-11} ...
+/* 10 */      MCD_OPC_FilterValue, 31, 216, 3, // Skip to: 998
+/* 14 */      MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 17 */      MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 31
+/* 21 */      MCD_OPC_CheckField, 16, 11, 236, 15, 17, 0, // Skip to: 45
+/* 28 */      MCD_OPC_Decode, 31, 20, // Opcode: BITREV_l2r
+/* 31 */      MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 45
+/* 35 */      MCD_OPC_CheckField, 16, 11, 236, 15, 3, 0, // Skip to: 45
+/* 42 */      MCD_OPC_Decode, 56, 20, // Opcode: BYTEREV_l2r
+/* 45 */      MCD_OPC_CheckField, 16, 11, 236, 15, 4, 0, // Skip to: 56
+/* 52 */      MCD_OPC_Decode, 231, 1, 21, // Opcode: STW_l3r
+/* 56 */      MCD_OPC_ExtractField, 20, 7,  // Inst{26-20} ...
+/* 59 */      MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 66
+/* 63 */      MCD_OPC_Decode, 66, 22, // Opcode: CRC8_l4r
+/* 66 */      MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 74
+/* 70 */      MCD_OPC_Decode, 170, 1, 23, // Opcode: MACCU_l4r
+/* 74 */      MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 77 */      MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 85
+/* 81 */      MCD_OPC_Decode, 150, 1, 24, // Opcode: LDIVU_l5r
+/* 85 */      MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 92
+/* 89 */      MCD_OPC_Decode, 126, 24, // Opcode: LADD_l5r
+/* 92 */      MCD_OPC_Decode, 165, 1, 25, // Opcode: LMUL_l6r
+/* 96 */      MCD_OPC_FilterValue, 1, 86, 0, // Skip to: 186
+/* 100 */     MCD_OPC_ExtractField, 11, 5,  // Inst{15-11} ...
+/* 103 */     MCD_OPC_FilterValue, 31, 123, 3, // Skip to: 998
+/* 107 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 110 */     MCD_OPC_FilterValue, 0, 116, 3, // Skip to: 998
+/* 114 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 117 */     MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 136
+/* 121 */     MCD_OPC_CheckField, 21, 6, 63, 29, 0, // Skip to: 156
+/* 127 */     MCD_OPC_CheckField, 16, 4, 12, 23, 0, // Skip to: 156
+/* 133 */     MCD_OPC_Decode, 65, 20, // Opcode: CLZ_l2r
+/* 136 */     MCD_OPC_FilterValue, 1, 16, 0, // Skip to: 156
+/* 140 */     MCD_OPC_CheckField, 21, 6, 63, 10, 0, // Skip to: 156
+/* 146 */     MCD_OPC_CheckField, 16, 4, 12, 4, 0, // Skip to: 156
+/* 152 */     MCD_OPC_Decode, 191, 1, 26, // Opcode: SETCLK_l2r
+/* 156 */     MCD_OPC_CheckField, 21, 6, 63, 10, 0, // Skip to: 172
+/* 162 */     MCD_OPC_CheckField, 16, 4, 12, 4, 0, // Skip to: 172
+/* 168 */     MCD_OPC_Decode, 244, 1, 21, // Opcode: XOR_l3r
+/* 172 */     MCD_OPC_CheckField, 21, 6, 63, 4, 0, // Skip to: 182
+/* 178 */     MCD_OPC_Decode, 169, 1, 23, // Opcode: MACCS_l4r
+/* 182 */     MCD_OPC_Decode, 167, 1, 24, // Opcode: LSUB_l5r
+/* 186 */     MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 219
+/* 190 */     MCD_OPC_ExtractField, 11, 16,  // Inst{26-11} ...
+/* 193 */     MCD_OPC_FilterValue, 159, 251, 3, 31, 3, // Skip to: 998
+/* 199 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 202 */     MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 209
+/* 206 */     MCD_OPC_Decode, 110, 20, // Opcode: INITLR_l2r
+/* 209 */     MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 216
+/* 213 */     MCD_OPC_Decode, 101, 20, // Opcode: GETPS_l2r
+/* 216 */     MCD_OPC_Decode, 29, 21, // Opcode: ASHR_l3r
+/* 219 */     MCD_OPC_FilterValue, 3, 31, 0, // Skip to: 254
+/* 223 */     MCD_OPC_ExtractField, 11, 16,  // Inst{26-11} ...
+/* 226 */     MCD_OPC_FilterValue, 159, 251, 3, 254, 2, // Skip to: 998
+/* 232 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 235 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 243
+/* 239 */     MCD_OPC_Decode, 202, 1, 26, // Opcode: SETPS_l2r
+/* 243 */     MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 250
+/* 247 */     MCD_OPC_Decode, 94, 20, // Opcode: GETD_l2r
+/* 250 */     MCD_OPC_Decode, 144, 1, 21, // Opcode: LDAWF_l3r
+/* 254 */     MCD_OPC_FilterValue, 4, 32, 0, // Skip to: 290
+/* 258 */     MCD_OPC_ExtractField, 11, 16,  // Inst{26-11} ...
+/* 261 */     MCD_OPC_FilterValue, 159, 251, 3, 219, 2, // Skip to: 998
+/* 267 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 270 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 278
+/* 274 */     MCD_OPC_Decode, 236, 1, 20, // Opcode: TESTLCL_l2r
+/* 278 */     MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 286
+/* 282 */     MCD_OPC_Decode, 210, 1, 26, // Opcode: SETTW_l2r
+/* 286 */     MCD_OPC_Decode, 137, 1, 21, // Opcode: LDAWB_l3r
+/* 290 */     MCD_OPC_FilterValue, 5, 32, 0, // Skip to: 326
+/* 294 */     MCD_OPC_ExtractField, 11, 16,  // Inst{26-11} ...
+/* 297 */     MCD_OPC_FilterValue, 159, 251, 3, 183, 2, // Skip to: 998
+/* 303 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 306 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 314
+/* 310 */     MCD_OPC_Decode, 204, 1, 26, // Opcode: SETRDY_l2r
+/* 314 */     MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 322
+/* 318 */     MCD_OPC_Decode, 193, 1, 20, // Opcode: SETC_l2r
+/* 322 */     MCD_OPC_Decode, 130, 1, 21, // Opcode: LDA16F_l3r
+/* 326 */     MCD_OPC_FilterValue, 6, 31, 0, // Skip to: 361
+/* 330 */     MCD_OPC_ExtractField, 11, 16,  // Inst{26-11} ...
+/* 333 */     MCD_OPC_FilterValue, 159, 251, 3, 147, 2, // Skip to: 998
+/* 339 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 342 */     MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 350
+/* 346 */     MCD_OPC_Decode, 200, 1, 26, // Opcode: SETN_l2r
+/* 350 */     MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 357
+/* 354 */     MCD_OPC_Decode, 100, 20, // Opcode: GETN_l2r
+/* 357 */     MCD_OPC_Decode, 129, 1, 21, // Opcode: LDA16B_l3r
+/* 361 */     MCD_OPC_FilterValue, 7, 12, 0, // Skip to: 377
+/* 365 */     MCD_OPC_CheckField, 11, 16, 159, 251, 3, 113, 2, // Skip to: 998
+/* 373 */     MCD_OPC_Decode, 175, 1, 21, // Opcode: MUL_l3r
+/* 377 */     MCD_OPC_FilterValue, 8, 11, 0, // Skip to: 392
+/* 381 */     MCD_OPC_CheckField, 11, 16, 159, 251, 3, 97, 2, // Skip to: 998
+/* 389 */     MCD_OPC_Decode, 71, 21, // Opcode: DIVS_l3r
+/* 392 */     MCD_OPC_FilterValue, 9, 11, 0, // Skip to: 407
+/* 396 */     MCD_OPC_CheckField, 11, 16, 159, 251, 3, 82, 2, // Skip to: 998
+/* 404 */     MCD_OPC_Decode, 72, 21, // Opcode: DIVU_l3r
+/* 407 */     MCD_OPC_FilterValue, 10, 31, 0, // Skip to: 442
+/* 411 */     MCD_OPC_ExtractField, 26, 1,  // Inst{26} ...
+/* 414 */     MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 428
+/* 418 */     MCD_OPC_CheckField, 10, 6, 60, 62, 2, // Skip to: 998
+/* 424 */     MCD_OPC_Decode, 225, 1, 27, // Opcode: STWDP_lru6
+/* 428 */     MCD_OPC_FilterValue, 1, 54, 2, // Skip to: 998
+/* 432 */     MCD_OPC_CheckField, 10, 6, 60, 48, 2, // Skip to: 998
+/* 438 */     MCD_OPC_Decode, 228, 1, 27, // Opcode: STWSP_lru6
+/* 442 */     MCD_OPC_FilterValue, 11, 31, 0, // Skip to: 477
+/* 446 */     MCD_OPC_ExtractField, 26, 1,  // Inst{26} ...
+/* 449 */     MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 463
+/* 453 */     MCD_OPC_CheckField, 10, 6, 60, 27, 2, // Skip to: 998
+/* 459 */     MCD_OPC_Decode, 158, 1, 27, // Opcode: LDWDP_lru6
+/* 463 */     MCD_OPC_FilterValue, 1, 19, 2, // Skip to: 998
+/* 467 */     MCD_OPC_CheckField, 10, 6, 60, 13, 2, // Skip to: 998
+/* 473 */     MCD_OPC_Decode, 161, 1, 27, // Opcode: LDWSP_lru6
+/* 477 */     MCD_OPC_FilterValue, 12, 31, 0, // Skip to: 512
+/* 481 */     MCD_OPC_ExtractField, 26, 1,  // Inst{26} ...
+/* 484 */     MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 498
+/* 488 */     MCD_OPC_CheckField, 10, 6, 60, 248, 1, // Skip to: 998
+/* 494 */     MCD_OPC_Decode, 140, 1, 27, // Opcode: LDAWDP_lru6
+/* 498 */     MCD_OPC_FilterValue, 1, 240, 1, // Skip to: 998
+/* 502 */     MCD_OPC_CheckField, 10, 6, 60, 234, 1, // Skip to: 998
+/* 508 */     MCD_OPC_Decode, 145, 1, 27, // Opcode: LDAWSP_lru6
+/* 512 */     MCD_OPC_FilterValue, 13, 31, 0, // Skip to: 547
+/* 516 */     MCD_OPC_ExtractField, 26, 1,  // Inst{26} ...
+/* 519 */     MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 533
+/* 523 */     MCD_OPC_CheckField, 10, 6, 60, 213, 1, // Skip to: 998
+/* 529 */     MCD_OPC_Decode, 147, 1, 27, // Opcode: LDC_lru6
+/* 533 */     MCD_OPC_FilterValue, 1, 205, 1, // Skip to: 998
+/* 537 */     MCD_OPC_CheckField, 10, 6, 60, 199, 1, // Skip to: 998
+/* 543 */     MCD_OPC_Decode, 154, 1, 27, // Opcode: LDWCP_lru6
+/* 547 */     MCD_OPC_FilterValue, 14, 94, 0, // Skip to: 645
+/* 551 */     MCD_OPC_ExtractField, 26, 1,  // Inst{26} ...
+/* 554 */     MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 599
+/* 558 */     MCD_OPC_ExtractField, 10, 6,  // Inst{15-10} ...
+/* 561 */     MCD_OPC_FilterValue, 60, 177, 1, // Skip to: 998
+/* 565 */     MCD_OPC_ExtractField, 22, 4,  // Inst{25-22} ...
+/* 568 */     MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 575
+/* 572 */     MCD_OPC_Decode, 51, 28, // Opcode: BRFU_lu6
+/* 575 */     MCD_OPC_FilterValue, 13, 3, 0, // Skip to: 582
+/* 579 */     MCD_OPC_Decode, 34, 28, // Opcode: BLAT_lu6
+/* 582 */     MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 589
+/* 586 */     MCD_OPC_Decode, 87, 28, // Opcode: EXTDP_lu6
+/* 589 */     MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 596
+/* 593 */     MCD_OPC_Decode, 119, 28, // Opcode: KCALL_lu6
+/* 596 */     MCD_OPC_Decode, 49, 29, // Opcode: BRFT_lru6
+/* 599 */     MCD_OPC_FilterValue, 1, 139, 1, // Skip to: 998
+/* 603 */     MCD_OPC_ExtractField, 10, 6,  // Inst{15-10} ...
+/* 606 */     MCD_OPC_FilterValue, 60, 132, 1, // Skip to: 998
+/* 610 */     MCD_OPC_ExtractField, 22, 4,  // Inst{25-22} ...
+/* 613 */     MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 620
+/* 617 */     MCD_OPC_Decode, 45, 30, // Opcode: BRBU_lu6
+/* 620 */     MCD_OPC_FilterValue, 13, 3, 0, // Skip to: 627
+/* 624 */     MCD_OPC_Decode, 83, 28, // Opcode: ENTSP_lu6
+/* 627 */     MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 634
+/* 631 */     MCD_OPC_Decode, 89, 28, // Opcode: EXTSP_lu6
+/* 634 */     MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 642
+/* 638 */     MCD_OPC_Decode, 188, 1, 28, // Opcode: RETSP_lu6
+/* 642 */     MCD_OPC_Decode, 43, 31, // Opcode: BRBT_lru6
+/* 645 */     MCD_OPC_FilterValue, 15, 81, 0, // Skip to: 730
+/* 649 */     MCD_OPC_ExtractField, 26, 1,  // Inst{26} ...
+/* 652 */     MCD_OPC_FilterValue, 0, 42, 0, // Skip to: 698
+/* 656 */     MCD_OPC_ExtractField, 10, 6,  // Inst{15-10} ...
+/* 659 */     MCD_OPC_FilterValue, 60, 79, 1, // Skip to: 998
+/* 663 */     MCD_OPC_ExtractField, 22, 4,  // Inst{25-22} ...
+/* 666 */     MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 673
+/* 670 */     MCD_OPC_Decode, 63, 28, // Opcode: CLRSR_lu6
+/* 673 */     MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 681
+/* 677 */     MCD_OPC_Decode, 208, 1, 28, // Opcode: SETSR_lu6
+/* 681 */     MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 688
+/* 685 */     MCD_OPC_Decode, 121, 28, // Opcode: KENTSP_lu6
+/* 688 */     MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 695
+/* 692 */     MCD_OPC_Decode, 123, 28, // Opcode: KRESTSP_lu6
+/* 695 */     MCD_OPC_Decode, 47, 29, // Opcode: BRFF_lru6
+/* 698 */     MCD_OPC_FilterValue, 1, 40, 1, // Skip to: 998
+/* 702 */     MCD_OPC_ExtractField, 10, 6,  // Inst{15-10} ...
+/* 705 */     MCD_OPC_FilterValue, 60, 33, 1, // Skip to: 998
+/* 709 */     MCD_OPC_ExtractField, 22, 4,  // Inst{25-22} ...
+/* 712 */     MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 719
+/* 716 */     MCD_OPC_Decode, 103, 28, // Opcode: GETSR_lu6
+/* 719 */     MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 727
+/* 723 */     MCD_OPC_Decode, 138, 1, 28, // Opcode: LDAWCP_lu6
+/* 727 */     MCD_OPC_Decode, 41, 31, // Opcode: BRBF_lru6
+/* 730 */     MCD_OPC_FilterValue, 16, 12, 0, // Skip to: 746
+/* 734 */     MCD_OPC_CheckField, 11, 16, 159, 251, 3, 0, 1, // Skip to: 998
+/* 742 */     MCD_OPC_Decode, 219, 1, 21, // Opcode: ST16_l3r
+/* 746 */     MCD_OPC_FilterValue, 17, 12, 0, // Skip to: 762
+/* 750 */     MCD_OPC_CheckField, 11, 16, 159, 251, 3, 240, 0, // Skip to: 998
+/* 758 */     MCD_OPC_Decode, 220, 1, 21, // Opcode: ST8_l3r
+/* 762 */     MCD_OPC_FilterValue, 18, 31, 0, // Skip to: 797
+/* 766 */     MCD_OPC_ExtractField, 11, 16,  // Inst{26-11} ...
+/* 769 */     MCD_OPC_FilterValue, 159, 251, 3, 3, 0, // Skip to: 778
+/* 775 */     MCD_OPC_Decode, 28, 32, // Opcode: ASHR_l2rus
+/* 778 */     MCD_OPC_FilterValue, 191, 251, 3, 4, 0, // Skip to: 788
+/* 784 */     MCD_OPC_Decode, 181, 1, 32, // Opcode: OUTPW_l2rus
+/* 788 */     MCD_OPC_FilterValue, 223, 251, 3, 204, 0, // Skip to: 998
+/* 794 */     MCD_OPC_Decode, 113, 32, // Opcode: INPW_l2rus
+/* 797 */     MCD_OPC_FilterValue, 19, 12, 0, // Skip to: 813
+/* 801 */     MCD_OPC_CheckField, 11, 16, 159, 251, 3, 189, 0, // Skip to: 998
+/* 809 */     MCD_OPC_Decode, 143, 1, 33, // Opcode: LDAWF_l2rus
+/* 813 */     MCD_OPC_FilterValue, 20, 12, 0, // Skip to: 829
+/* 817 */     MCD_OPC_CheckField, 11, 16, 159, 251, 3, 173, 0, // Skip to: 998
+/* 825 */     MCD_OPC_Decode, 136, 1, 33, // Opcode: LDAWB_l2rus
+/* 829 */     MCD_OPC_FilterValue, 21, 11, 0, // Skip to: 844
+/* 833 */     MCD_OPC_CheckField, 11, 16, 159, 251, 3, 157, 0, // Skip to: 998
+/* 841 */     MCD_OPC_Decode, 67, 34, // Opcode: CRC_l3r
+/* 844 */     MCD_OPC_FilterValue, 24, 12, 0, // Skip to: 860
+/* 848 */     MCD_OPC_CheckField, 11, 16, 159, 251, 3, 142, 0, // Skip to: 998
+/* 856 */     MCD_OPC_Decode, 186, 1, 21, // Opcode: REMS_l3r
+/* 860 */     MCD_OPC_FilterValue, 25, 12, 0, // Skip to: 876
+/* 864 */     MCD_OPC_CheckField, 11, 16, 159, 251, 3, 126, 0, // Skip to: 998
+/* 872 */     MCD_OPC_Decode, 187, 1, 21, // Opcode: REMU_l3r
+/* 876 */     MCD_OPC_FilterValue, 26, 29, 0, // Skip to: 909
+/* 880 */     MCD_OPC_ExtractField, 26, 1,  // Inst{26} ...
+/* 883 */     MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 896
+/* 887 */     MCD_OPC_CheckField, 10, 6, 60, 105, 0, // Skip to: 998
+/* 893 */     MCD_OPC_Decode, 39, 35, // Opcode: BLRF_lu10
+/* 896 */     MCD_OPC_FilterValue, 1, 98, 0, // Skip to: 998
+/* 900 */     MCD_OPC_CheckField, 10, 6, 60, 92, 0, // Skip to: 998
+/* 906 */     MCD_OPC_Decode, 37, 36, // Opcode: BLRB_lu10
+/* 909 */     MCD_OPC_FilterValue, 27, 31, 0, // Skip to: 944
+/* 913 */     MCD_OPC_ExtractField, 26, 1,  // Inst{26} ...
+/* 916 */     MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 930
+/* 920 */     MCD_OPC_CheckField, 10, 6, 60, 72, 0, // Skip to: 998
+/* 926 */     MCD_OPC_Decode, 133, 1, 35, // Opcode: LDAPF_lu10
+/* 930 */     MCD_OPC_FilterValue, 1, 64, 0, // Skip to: 998
+/* 934 */     MCD_OPC_CheckField, 10, 6, 60, 58, 0, // Skip to: 998
+/* 940 */     MCD_OPC_Decode, 131, 1, 36, // Opcode: LDAPB_lu10
+/* 944 */     MCD_OPC_FilterValue, 28, 30, 0, // Skip to: 978
+/* 948 */     MCD_OPC_ExtractField, 26, 1,  // Inst{26} ...
+/* 951 */     MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 964
+/* 955 */     MCD_OPC_CheckField, 10, 6, 60, 37, 0, // Skip to: 998
+/* 961 */     MCD_OPC_Decode, 32, 35, // Opcode: BLACP_lu10
+/* 964 */     MCD_OPC_FilterValue, 1, 30, 0, // Skip to: 998
+/* 968 */     MCD_OPC_CheckField, 10, 6, 60, 24, 0, // Skip to: 998
+/* 974 */     MCD_OPC_Decode, 155, 1, 35, // Opcode: LDWCP_lu10
+/* 978 */     MCD_OPC_FilterValue, 29, 16, 0, // Skip to: 998
+/* 982 */     MCD_OPC_CheckField, 26, 1, 0, 10, 0, // Skip to: 998
+/* 988 */     MCD_OPC_CheckField, 10, 6, 60, 4, 0, // Skip to: 998
+/* 994 */     MCD_OPC_Decode, 194, 1, 29, // Opcode: SETC_lru6
+/* 998 */     MCD_OPC_Fail,
+  0
+};
+
+static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits)
+{
+  return true;  //llvm_unreachable("Invalid index!");
+}
+
+#define DecodeToMCInst(fname,fieldname, InsnType) \
+static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \
+                uint64_t Address, const void *Decoder) \
+{ \
+  InsnType tmp; \
+  switch (Idx) { \
+  default: \
+  case 0: \
+    return S; \
+  case 1: \
+    tmp = fieldname(insn, 0, 4); \
+    if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 2: \
+    if (Decode2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 3: \
+    if (Decode2RUSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 4: \
+    if (DecodeR2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 5: \
+    if (Decode3RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 6: \
+    if (Decode2RImmInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 7: \
+    if (Decode2RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 8: \
+    if (DecodeRUSSrcDstBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 9: \
+    if (DecodeRUSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 10: \
+    tmp = fieldname(insn, 6, 4); \
+    if (DecodeRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 6); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 11: \
+    tmp = fieldname(insn, 0, 6); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 12: \
+    tmp = fieldname(insn, 6, 4); \
+    if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 6); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 13: \
+    tmp = fieldname(insn, 0, 6); \
+    if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 14: \
+    tmp = fieldname(insn, 6, 4); \
+    if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = fieldname(insn, 0, 6); \
+    if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 15: \
+    if (DecodeRUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 16: \
+    if (Decode2RUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 17: \
+    if (Decode3RImmInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 18: \
+    tmp = fieldname(insn, 0, 10); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 19: \
+    tmp = fieldname(insn, 0, 10); \
+    if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 20: \
+    if (DecodeL2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 21: \
+    if (DecodeL3RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 22: \
+    if (DecodeL4RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 23: \
+    if (DecodeL4RSrcDstSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 24: \
+    if (DecodeL5RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 25: \
+    if (DecodeL6RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 26: \
+    if (DecodeLR2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 27: \
+    tmp = fieldname(insn, 22, 4); \
+    if (DecodeRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = 0; \
+    tmp |= (fieldname(insn, 0, 10) << 6); \
+    tmp |= (fieldname(insn, 16, 6) << 0); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 28: \
+    tmp = 0; \
+    tmp |= (fieldname(insn, 0, 10) << 6); \
+    tmp |= (fieldname(insn, 16, 6) << 0); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 29: \
+    tmp = fieldname(insn, 22, 4); \
+    if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = 0; \
+    tmp |= (fieldname(insn, 0, 10) << 6); \
+    tmp |= (fieldname(insn, 16, 6) << 0); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 30: \
+    tmp = 0; \
+    tmp |= (fieldname(insn, 0, 10) << 6); \
+    tmp |= (fieldname(insn, 16, 6) << 0); \
+    if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 31: \
+    tmp = fieldname(insn, 22, 4); \
+    if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    tmp = 0; \
+    tmp |= (fieldname(insn, 0, 10) << 6); \
+    tmp |= (fieldname(insn, 16, 6) << 0); \
+    if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 32: \
+    if (DecodeL2RUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 33: \
+    if (DecodeL2RUSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 34: \
+    if (DecodeL3RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  case 35: \
+    tmp = 0; \
+    tmp |= (fieldname(insn, 0, 10) << 10); \
+    tmp |= (fieldname(insn, 16, 10) << 0); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 36: \
+    tmp = 0; \
+    tmp |= (fieldname(insn, 0, 10) << 10); \
+    tmp |= (fieldname(insn, 16, 10) << 0); \
+    if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
+    return S; \
+  } \
+} 
+
+#define DecodeInstruction(fname, fieldname, decoder, InsnType) \
+static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
+           InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \
+{ \
+  uint64_t Bits = getFeatureBits(feature); \
+  const uint8_t *Ptr = DecodeTable; \
+  uint32_t CurFieldValue = 0, ExpectedValue; \
+  DecodeStatus S = MCDisassembler_Success; \
+  unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
+  InsnType Val, FieldValue, PositiveMask, NegativeMask; \
+  bool Pred, Fail; \
+  for (;;) { \
+    switch (*Ptr) { \
+    default: \
+      return MCDisassembler_Fail; \
+    case MCD_OPC_ExtractField: { \
+      Start = *++Ptr; \
+      Len = *++Ptr; \
+      ++Ptr; \
+      CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \
+      break; \
+    } \
+    case MCD_OPC_FilterValue: { \
+      Val = (InsnType)decodeULEB128(++Ptr, &Len); \
+      Ptr += Len; \
+      NumToSkip = *Ptr++; \
+      NumToSkip |= (*Ptr++) << 8; \
+      if (Val != CurFieldValue) \
+        Ptr += NumToSkip; \
+      break; \
+    } \
+    case MCD_OPC_CheckField: { \
+      Start = *++Ptr; \
+      Len = *++Ptr; \
+      FieldValue = fieldname(insn, Start, Len); \
+      ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \
+      Ptr += Len; \
+      NumToSkip = *Ptr++; \
+      NumToSkip |= (*Ptr++) << 8; \
+      if (ExpectedValue != FieldValue) \
+        Ptr += NumToSkip; \
+      break; \
+    } \
+    case MCD_OPC_CheckPredicate: { \
+      PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \
+      Ptr += Len; \
+      NumToSkip = *Ptr++; \
+      NumToSkip |= (*Ptr++) << 8; \
+      Pred = checkDecoderPredicate(PIdx, Bits); \
+      if (!Pred) \
+        Ptr += NumToSkip; \
+      (void)Pred; \
+      break; \
+    } \
+    case MCD_OPC_Decode: { \
+      Opc = (unsigned)decodeULEB128(++Ptr, &Len); \
+      Ptr += Len; \
+      DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \
+      Ptr += Len; \
+      MCInst_setOpcode(MI, Opc); \
+      return decoder(S, DecodeIdx, insn, MI, Address, MRI); \
+    } \
+    case MCD_OPC_SoftFail: { \
+      PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \
+      Ptr += Len; \
+      NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \
+      Ptr += Len; \
+      Fail = (insn & PositiveMask) || (~insn & NegativeMask); \
+      if (Fail) \
+        S = MCDisassembler_SoftFail; \
+      break; \
+    } \
+    case MCD_OPC_Fail: { \
+      return MCDisassembler_Fail; \
+    } \
+    } \
+  } \
+}
+
+
+FieldFromInstruction(fieldFromInstruction_2, uint16_t)
+DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, uint16_t)
+DecodeInstruction(decodeInstruction_2, fieldFromInstruction_2, decodeToMCInst_2, uint16_t)
+FieldFromInstruction(fieldFromInstruction_4, uint32_t)
+DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t)
+DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t)
diff --git a/capstone/arch/XCore/XCoreGenInstrInfo.inc b/capstone/arch/XCore/XCoreGenInstrInfo.inc
new file mode 100644
index 000000000..7f579f111
--- /dev/null
+++ b/capstone/arch/XCore/XCoreGenInstrInfo.inc
@@ -0,0 +1,267 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*Target Instruction Enum Values                                              *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+
+#ifdef GET_INSTRINFO_ENUM
+#undef GET_INSTRINFO_ENUM
+
+enum {
+    XCore_PHI	= 0,
+    XCore_INLINEASM	= 1,
+    XCore_CFI_INSTRUCTION	= 2,
+    XCore_EH_LABEL	= 3,
+    XCore_GC_LABEL	= 4,
+    XCore_KILL	= 5,
+    XCore_EXTRACT_SUBREG	= 6,
+    XCore_INSERT_SUBREG	= 7,
+    XCore_IMPLICIT_DEF	= 8,
+    XCore_SUBREG_TO_REG	= 9,
+    XCore_COPY_TO_REGCLASS	= 10,
+    XCore_DBG_VALUE	= 11,
+    XCore_REG_SEQUENCE	= 12,
+    XCore_COPY	= 13,
+    XCore_BUNDLE	= 14,
+    XCore_LIFETIME_START	= 15,
+    XCore_LIFETIME_END	= 16,
+    XCore_STACKMAP	= 17,
+    XCore_PATCHPOINT	= 18,
+    XCore_LOAD_STACK_GUARD	= 19,
+    XCore_STATEPOINT	= 20,
+    XCore_FRAME_ALLOC	= 21,
+    XCore_ADD_2rus	= 22,
+    XCore_ADD_3r	= 23,
+    XCore_ADJCALLSTACKDOWN	= 24,
+    XCore_ADJCALLSTACKUP	= 25,
+    XCore_ANDNOT_2r	= 26,
+    XCore_AND_3r	= 27,
+    XCore_ASHR_l2rus	= 28,
+    XCore_ASHR_l3r	= 29,
+    XCore_BAU_1r	= 30,
+    XCore_BITREV_l2r	= 31,
+    XCore_BLACP_lu10	= 32,
+    XCore_BLACP_u10	= 33,
+    XCore_BLAT_lu6	= 34,
+    XCore_BLAT_u6	= 35,
+    XCore_BLA_1r	= 36,
+    XCore_BLRB_lu10	= 37,
+    XCore_BLRB_u10	= 38,
+    XCore_BLRF_lu10	= 39,
+    XCore_BLRF_u10	= 40,
+    XCore_BRBF_lru6	= 41,
+    XCore_BRBF_ru6	= 42,
+    XCore_BRBT_lru6	= 43,
+    XCore_BRBT_ru6	= 44,
+    XCore_BRBU_lu6	= 45,
+    XCore_BRBU_u6	= 46,
+    XCore_BRFF_lru6	= 47,
+    XCore_BRFF_ru6	= 48,
+    XCore_BRFT_lru6	= 49,
+    XCore_BRFT_ru6	= 50,
+    XCore_BRFU_lu6	= 51,
+    XCore_BRFU_u6	= 52,
+    XCore_BRU_1r	= 53,
+    XCore_BR_JT	= 54,
+    XCore_BR_JT32	= 55,
+    XCore_BYTEREV_l2r	= 56,
+    XCore_CHKCT_2r	= 57,
+    XCore_CHKCT_rus	= 58,
+    XCore_CLRE_0R	= 59,
+    XCore_CLRPT_1R	= 60,
+    XCore_CLRSR_branch_lu6	= 61,
+    XCore_CLRSR_branch_u6	= 62,
+    XCore_CLRSR_lu6	= 63,
+    XCore_CLRSR_u6	= 64,
+    XCore_CLZ_l2r	= 65,
+    XCore_CRC8_l4r	= 66,
+    XCore_CRC_l3r	= 67,
+    XCore_DCALL_0R	= 68,
+    XCore_DENTSP_0R	= 69,
+    XCore_DGETREG_1r	= 70,
+    XCore_DIVS_l3r	= 71,
+    XCore_DIVU_l3r	= 72,
+    XCore_DRESTSP_0R	= 73,
+    XCore_DRET_0R	= 74,
+    XCore_ECALLF_1r	= 75,
+    XCore_ECALLT_1r	= 76,
+    XCore_EDU_1r	= 77,
+    XCore_EEF_2r	= 78,
+    XCore_EET_2r	= 79,
+    XCore_EEU_1r	= 80,
+    XCore_EH_RETURN	= 81,
+    XCore_ENDIN_2r	= 82,
+    XCore_ENTSP_lu6	= 83,
+    XCore_ENTSP_u6	= 84,
+    XCore_EQ_2rus	= 85,
+    XCore_EQ_3r	= 86,
+    XCore_EXTDP_lu6	= 87,
+    XCore_EXTDP_u6	= 88,
+    XCore_EXTSP_lu6	= 89,
+    XCore_EXTSP_u6	= 90,
+    XCore_FRAME_TO_ARGS_OFFSET	= 91,
+    XCore_FREER_1r	= 92,
+    XCore_FREET_0R	= 93,
+    XCore_GETD_l2r	= 94,
+    XCore_GETED_0R	= 95,
+    XCore_GETET_0R	= 96,
+    XCore_GETID_0R	= 97,
+    XCore_GETKEP_0R	= 98,
+    XCore_GETKSP_0R	= 99,
+    XCore_GETN_l2r	= 100,
+    XCore_GETPS_l2r	= 101,
+    XCore_GETR_rus	= 102,
+    XCore_GETSR_lu6	= 103,
+    XCore_GETSR_u6	= 104,
+    XCore_GETST_2r	= 105,
+    XCore_GETTS_2r	= 106,
+    XCore_INCT_2r	= 107,
+    XCore_INITCP_2r	= 108,
+    XCore_INITDP_2r	= 109,
+    XCore_INITLR_l2r	= 110,
+    XCore_INITPC_2r	= 111,
+    XCore_INITSP_2r	= 112,
+    XCore_INPW_l2rus	= 113,
+    XCore_INSHR_2r	= 114,
+    XCore_INT_2r	= 115,
+    XCore_IN_2r	= 116,
+    XCore_Int_MemBarrier	= 117,
+    XCore_KCALL_1r	= 118,
+    XCore_KCALL_lu6	= 119,
+    XCore_KCALL_u6	= 120,
+    XCore_KENTSP_lu6	= 121,
+    XCore_KENTSP_u6	= 122,
+    XCore_KRESTSP_lu6	= 123,
+    XCore_KRESTSP_u6	= 124,
+    XCore_KRET_0R	= 125,
+    XCore_LADD_l5r	= 126,
+    XCore_LD16S_3r	= 127,
+    XCore_LD8U_3r	= 128,
+    XCore_LDA16B_l3r	= 129,
+    XCore_LDA16F_l3r	= 130,
+    XCore_LDAPB_lu10	= 131,
+    XCore_LDAPB_u10	= 132,
+    XCore_LDAPF_lu10	= 133,
+    XCore_LDAPF_lu10_ba	= 134,
+    XCore_LDAPF_u10	= 135,
+    XCore_LDAWB_l2rus	= 136,
+    XCore_LDAWB_l3r	= 137,
+    XCore_LDAWCP_lu6	= 138,
+    XCore_LDAWCP_u6	= 139,
+    XCore_LDAWDP_lru6	= 140,
+    XCore_LDAWDP_ru6	= 141,
+    XCore_LDAWFI	= 142,
+    XCore_LDAWF_l2rus	= 143,
+    XCore_LDAWF_l3r	= 144,
+    XCore_LDAWSP_lru6	= 145,
+    XCore_LDAWSP_ru6	= 146,
+    XCore_LDC_lru6	= 147,
+    XCore_LDC_ru6	= 148,
+    XCore_LDET_0R	= 149,
+    XCore_LDIVU_l5r	= 150,
+    XCore_LDSED_0R	= 151,
+    XCore_LDSPC_0R	= 152,
+    XCore_LDSSR_0R	= 153,
+    XCore_LDWCP_lru6	= 154,
+    XCore_LDWCP_lu10	= 155,
+    XCore_LDWCP_ru6	= 156,
+    XCore_LDWCP_u10	= 157,
+    XCore_LDWDP_lru6	= 158,
+    XCore_LDWDP_ru6	= 159,
+    XCore_LDWFI	= 160,
+    XCore_LDWSP_lru6	= 161,
+    XCore_LDWSP_ru6	= 162,
+    XCore_LDW_2rus	= 163,
+    XCore_LDW_3r	= 164,
+    XCore_LMUL_l6r	= 165,
+    XCore_LSS_3r	= 166,
+    XCore_LSUB_l5r	= 167,
+    XCore_LSU_3r	= 168,
+    XCore_MACCS_l4r	= 169,
+    XCore_MACCU_l4r	= 170,
+    XCore_MJOIN_1r	= 171,
+    XCore_MKMSK_2r	= 172,
+    XCore_MKMSK_rus	= 173,
+    XCore_MSYNC_1r	= 174,
+    XCore_MUL_l3r	= 175,
+    XCore_NEG	= 176,
+    XCore_NOT	= 177,
+    XCore_OR_3r	= 178,
+    XCore_OUTCT_2r	= 179,
+    XCore_OUTCT_rus	= 180,
+    XCore_OUTPW_l2rus	= 181,
+    XCore_OUTSHR_2r	= 182,
+    XCore_OUTT_2r	= 183,
+    XCore_OUT_2r	= 184,
+    XCore_PEEK_2r	= 185,
+    XCore_REMS_l3r	= 186,
+    XCore_REMU_l3r	= 187,
+    XCore_RETSP_lu6	= 188,
+    XCore_RETSP_u6	= 189,
+    XCore_SELECT_CC	= 190,
+    XCore_SETCLK_l2r	= 191,
+    XCore_SETCP_1r	= 192,
+    XCore_SETC_l2r	= 193,
+    XCore_SETC_lru6	= 194,
+    XCore_SETC_ru6	= 195,
+    XCore_SETDP_1r	= 196,
+    XCore_SETD_2r	= 197,
+    XCore_SETEV_1r	= 198,
+    XCore_SETKEP_0R	= 199,
+    XCore_SETN_l2r	= 200,
+    XCore_SETPSC_2r	= 201,
+    XCore_SETPS_l2r	= 202,
+    XCore_SETPT_2r	= 203,
+    XCore_SETRDY_l2r	= 204,
+    XCore_SETSP_1r	= 205,
+    XCore_SETSR_branch_lu6	= 206,
+    XCore_SETSR_branch_u6	= 207,
+    XCore_SETSR_lu6	= 208,
+    XCore_SETSR_u6	= 209,
+    XCore_SETTW_l2r	= 210,
+    XCore_SETV_1r	= 211,
+    XCore_SEXT_2r	= 212,
+    XCore_SEXT_rus	= 213,
+    XCore_SHL_2rus	= 214,
+    XCore_SHL_3r	= 215,
+    XCore_SHR_2rus	= 216,
+    XCore_SHR_3r	= 217,
+    XCore_SSYNC_0r	= 218,
+    XCore_ST16_l3r	= 219,
+    XCore_ST8_l3r	= 220,
+    XCore_STET_0R	= 221,
+    XCore_STSED_0R	= 222,
+    XCore_STSPC_0R	= 223,
+    XCore_STSSR_0R	= 224,
+    XCore_STWDP_lru6	= 225,
+    XCore_STWDP_ru6	= 226,
+    XCore_STWFI	= 227,
+    XCore_STWSP_lru6	= 228,
+    XCore_STWSP_ru6	= 229,
+    XCore_STW_2rus	= 230,
+    XCore_STW_l3r	= 231,
+    XCore_SUB_2rus	= 232,
+    XCore_SUB_3r	= 233,
+    XCore_SYNCR_1r	= 234,
+    XCore_TESTCT_2r	= 235,
+    XCore_TESTLCL_l2r	= 236,
+    XCore_TESTWCT_2r	= 237,
+    XCore_TSETMR_2r	= 238,
+    XCore_TSETR_3r	= 239,
+    XCore_TSTART_1R	= 240,
+    XCore_WAITEF_1R	= 241,
+    XCore_WAITET_1R	= 242,
+    XCore_WAITEU_0R	= 243,
+    XCore_XOR_l3r	= 244,
+    XCore_ZEXT_2r	= 245,
+    XCore_ZEXT_rus	= 246,
+    XCore_INSTRUCTION_LIST_END = 247
+};
+
+#endif // GET_INSTRINFO_ENUM
diff --git a/capstone/arch/XCore/XCoreGenRegisterInfo.inc b/capstone/arch/XCore/XCoreGenRegisterInfo.inc
new file mode 100644
index 000000000..0349badb5
--- /dev/null
+++ b/capstone/arch/XCore/XCoreGenRegisterInfo.inc
@@ -0,0 +1,110 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*Target Register Enum Values                                                 *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+
+
+#ifdef GET_REGINFO_ENUM
+#undef GET_REGINFO_ENUM
+
+enum {
+  XCore_NoRegister,
+  XCore_CP = 1,
+  XCore_DP = 2,
+  XCore_LR = 3,
+  XCore_SP = 4,
+  XCore_R0 = 5,
+  XCore_R1 = 6,
+  XCore_R2 = 7,
+  XCore_R3 = 8,
+  XCore_R4 = 9,
+  XCore_R5 = 10,
+  XCore_R6 = 11,
+  XCore_R7 = 12,
+  XCore_R8 = 13,
+  XCore_R9 = 14,
+  XCore_R10 = 15,
+  XCore_R11 = 16,
+  XCore_NUM_TARGET_REGS 	// 17
+};
+
+// Register classes
+enum {
+  XCore_RRegsRegClassID = 0,
+  XCore_GRRegsRegClassID = 1
+};
+
+#endif // GET_REGINFO_ENUM
+
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*MC Register Information                                                     *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_REGINFO_MC_DESC
+#undef GET_REGINFO_MC_DESC
+
+static const MCPhysReg XCoreRegDiffLists[] = {
+  /* 0 */ 65535, 0,
+};
+
+static const uint16_t XCoreSubRegIdxLists[] = {
+  /* 0 */ 0,
+};
+
+static const MCRegisterDesc XCoreRegDesc[] = { // Descriptors
+  { 3, 0, 0, 0, 0, 0 },
+  { 38, 1, 1, 0, 1, 0 },
+  { 41, 1, 1, 0, 1, 0 },
+  { 47, 1, 1, 0, 1, 0 },
+  { 44, 1, 1, 0, 1, 0 },
+  { 4, 1, 1, 0, 1, 0 },
+  { 11, 1, 1, 0, 1, 0 },
+  { 14, 1, 1, 0, 1, 0 },
+  { 17, 1, 1, 0, 1, 0 },
+  { 20, 1, 1, 0, 1, 0 },
+  { 23, 1, 1, 0, 1, 0 },
+  { 26, 1, 1, 0, 1, 0 },
+  { 29, 1, 1, 0, 1, 0 },
+  { 32, 1, 1, 0, 1, 0 },
+  { 35, 1, 1, 0, 1, 0 },
+  { 0, 1, 1, 0, 1, 0 },
+  { 7, 1, 1, 0, 1, 0 },
+};
+
+  // RRegs Register Class...
+  static const MCPhysReg RRegs[] = {
+    XCore_R0, XCore_R1, XCore_R2, XCore_R3, XCore_R4, XCore_R5, XCore_R6, XCore_R7, XCore_R8, XCore_R9, XCore_R10, XCore_R11, XCore_CP, XCore_DP, XCore_SP, XCore_LR,
+  };
+
+  // RRegs Bit set.
+  static const uint8_t RRegsBits[] = {
+    0xfe, 0xff, 0x01,
+  };
+
+  // GRRegs Register Class...
+  static const MCPhysReg GRRegs[] = {
+    XCore_R0, XCore_R1, XCore_R2, XCore_R3, XCore_R4, XCore_R5, XCore_R6, XCore_R7, XCore_R8, XCore_R9, XCore_R10, XCore_R11,
+  };
+
+  // GRRegs Bit set.
+  static const uint8_t GRRegsBits[] = {
+    0xe0, 0xff, 0x01,
+  };
+
+static const MCRegisterClass XCoreMCRegisterClasses[] = {
+  { RRegs, RRegsBits, sizeof(RRegsBits) },
+  { GRRegs, GRRegsBits, sizeof(GRRegsBits) },
+};
+
+#endif // GET_REGINFO_MC_DESC
diff --git a/capstone/arch/XCore/XCoreInstPrinter.c b/capstone/arch/XCore/XCoreInstPrinter.c
new file mode 100644
index 000000000..fcd020596
--- /dev/null
+++ b/capstone/arch/XCore/XCoreInstPrinter.c
@@ -0,0 +1,250 @@
+//===-- XCoreInstPrinter.cpp - Convert XCore MCInst to assembly syntax --------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an XCore MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifdef CAPSTONE_HAS_XCORE
+
+#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)
+#pragma warning(disable : 4996)			// disable MSVC's warning on strcpy()
+#pragma warning(disable : 28719)		// disable MSVC's warning on strcpy()
+#endif
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <capstone/platform.h>
+
+#include "XCoreInstPrinter.h"
+#include "../../MCInst.h"
+#include "../../utils.h"
+#include "../../SStream.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MathExtras.h"
+#include "XCoreMapping.h"
+
+static const char *getRegisterName(unsigned RegNo);
+
+void XCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
+{
+	/*
+	   if (((cs_struct *)ud)->detail != CS_OPT_ON)
+	   return;
+	 */
+}
+
+// stw sed, sp[3]
+void XCore_insn_extract(MCInst *MI, const char *code)
+{
+	int id;
+	char *p, *p2;
+	char tmp[128];
+
+	strcpy(tmp, code); // safe because code is way shorter than 128 bytes
+
+	// find the first space
+	p = strchr(tmp, ' ');
+	if (p) {
+		p++;
+		// find the next ','
+		p2 = strchr(p, ',');
+		if (p2) {
+			*p2 = '\0';
+			id = XCore_reg_id(p);
+			if (id) {
+				// register
+				if (MI->csh->detail) {
+					MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG;
+					MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id;
+					MI->flat_insn->detail->xcore.op_count++;
+				}
+			}
+			// next should be register, or memory?
+			// skip space
+			p2++;
+			while(*p2 && *p2 == ' ')
+				p2++;
+			if (*p2) {
+				// find '['
+				p = p2;
+				while(*p && *p != '[')
+					p++;
+				if (*p) {
+					// this is '['
+					*p = '\0';
+					id = XCore_reg_id(p2);
+					if (id) {
+						// base register
+						if (MI->csh->detail) {
+							MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM;
+							MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)id;
+							MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID;
+							MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0;
+							MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = 1;
+						}
+
+						p++;
+						p2 = p;
+						// until ']'
+						while(*p && *p != ']')
+							p++;
+						if (*p) {
+							*p = '\0';
+							// p2 is either index, or disp
+							id = XCore_reg_id(p2);
+							if (id) {
+								// index register
+								if (MI->csh->detail) {
+									MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = (uint8_t)id;
+								}
+							} else {
+								// a number means disp
+								if (MI->csh->detail) {
+									MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = atoi(p2);
+								}
+							}
+						}
+
+						if (MI->csh->detail) {
+							MI->flat_insn->detail->xcore.op_count++;
+						}
+					}
+				} else {
+					// a register?
+					id = XCore_reg_id(p2);
+					if (id) {
+						// register
+						if (MI->csh->detail) {
+							MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG;
+							MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id;
+							MI->flat_insn->detail->xcore.op_count++;
+						}
+					}
+				}
+			}
+		} else {
+			id = XCore_reg_id(p);
+			if (id) {
+				// register
+				if (MI->csh->detail) {
+					MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG;
+					MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id;
+					MI->flat_insn->detail->xcore.op_count++;
+				}
+			}
+		}
+	}
+}
+
+static void set_mem_access(MCInst *MI, bool status, int reg)
+{
+	if (MI->csh->detail != CS_OPT_ON)
+		return;
+
+	MI->csh->doing_mem = status;
+	if (status) {
+		if (reg != 0xffff && reg != -0xffff) {
+			MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM;
+			if (reg) {
+				MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)reg;
+			} else {
+				MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = XCORE_REG_INVALID;
+			}
+			MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID;
+			MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0;
+			MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = 1;
+		} else {
+			// the last op should be the memory base
+			MI->flat_insn->detail->xcore.op_count--;
+			MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM;
+			MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg;
+			MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID;
+			MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0;
+			if (reg > 0)
+				MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = 1;
+			else
+				MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = -1;
+		}
+	} else {
+		if (reg) {
+			MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = (uint8_t)reg;
+			// done, create the next operand slot
+			MI->flat_insn->detail->xcore.op_count++;
+		}
+	}
+}
+
+static void _printOperand(MCInst *MI, MCOperand *MO, SStream *O)
+{
+	if (MCOperand_isReg(MO)) {
+		unsigned reg;
+
+		reg = MCOperand_getReg(MO);
+		SStream_concat0(O, getRegisterName(reg));
+
+		if (MI->csh->detail) {
+			if (MI->csh->doing_mem) {
+				if (MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base == ARM_REG_INVALID)
+					MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)reg;
+				else
+					MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = (uint8_t)reg;
+			} else {
+				MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG;
+				MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = reg;
+				MI->flat_insn->detail->xcore.op_count++;
+			}
+		}
+	} else if (MCOperand_isImm(MO)) {
+		int32_t Imm = (int32_t)MCOperand_getImm(MO);
+
+		printInt32(O, Imm);
+
+		if (MI->csh->detail) {
+			if (MI->csh->doing_mem) {
+				MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = Imm;
+			} else {
+				MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_IMM;
+				MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].imm = Imm;
+				MI->flat_insn->detail->xcore.op_count++;
+			}
+		}
+	}
+}
+
+static void printOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	if (OpNum >= MI->size)
+		return;
+
+	_printOperand(MI, MCInst_getOperand(MI, OpNum), O);
+}
+
+static void printInlineJT(MCInst *MI, int OpNum, SStream *O)
+{
+}
+
+static void printInlineJT32(MCInst *MI, int OpNum, SStream *O)
+{
+}
+
+#define PRINT_ALIAS_INSTR
+#include "XCoreGenAsmWriter.inc"
+
+void XCore_printInst(MCInst *MI, SStream *O, void *Info)
+{
+	printInstruction(MI, O, Info);
+	set_mem_access(MI, false, 0);
+}
+
+#endif
diff --git a/capstone/arch/XCore/XCoreInstPrinter.h b/capstone/arch/XCore/XCoreInstPrinter.h
new file mode 100644
index 000000000..f9d000131
--- /dev/null
+++ b/capstone/arch/XCore/XCoreInstPrinter.h
@@ -0,0 +1,18 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_XCOREINSTPRINTER_H
+#define CS_XCOREINSTPRINTER_H
+
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+
+void XCore_printInst(MCInst *MI, SStream *O, void *Info);
+
+void XCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci);
+
+// extract details from assembly code @code
+void XCore_insn_extract(MCInst *MI, const char *code);
+
+#endif
diff --git a/capstone/arch/XCore/XCoreMapping.c b/capstone/arch/XCore/XCoreMapping.c
new file mode 100644
index 000000000..2a07e1224
--- /dev/null
+++ b/capstone/arch/XCore/XCoreMapping.c
@@ -0,0 +1,297 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifdef CAPSTONE_HAS_XCORE
+
+#include <stdio.h>	// debug
+#include <string.h>
+
+#include "../../utils.h"
+
+#include "XCoreMapping.h"
+
+#define GET_INSTRINFO_ENUM
+#include "XCoreGenInstrInfo.inc"
+
+static const name_map reg_name_maps[] = {
+	{ XCORE_REG_INVALID, NULL },
+
+	{ XCORE_REG_CP, "cp" },
+	{ XCORE_REG_DP, "dp" },
+	{ XCORE_REG_LR, "lr" },
+	{ XCORE_REG_SP, "sp" },
+	{ XCORE_REG_R0, "r0" },
+	{ XCORE_REG_R1, "r1" },
+	{ XCORE_REG_R2, "r2" },
+	{ XCORE_REG_R3, "r3" },
+	{ XCORE_REG_R4, "r4" },
+	{ XCORE_REG_R5, "r5" },
+	{ XCORE_REG_R6, "r6" },
+	{ XCORE_REG_R7, "r7" },
+	{ XCORE_REG_R8, "r8" },
+	{ XCORE_REG_R9, "r9" },
+	{ XCORE_REG_R10, "r10" },
+	{ XCORE_REG_R11, "r11" },
+
+	// pseudo registers
+	{ XCORE_REG_PC, "pc" },
+
+	{ XCORE_REG_SCP, "scp" },
+	{ XCORE_REG_SSR, "ssr" },
+	{ XCORE_REG_ET, "et" },
+	{ XCORE_REG_ED, "ed" },
+	{ XCORE_REG_SED, "sed" },
+	{ XCORE_REG_KEP, "kep" },
+	{ XCORE_REG_KSP, "ksp" },
+	{ XCORE_REG_ID, "id" },
+};
+
+const char *XCore_reg_name(csh handle, unsigned int reg)
+{
+#ifndef CAPSTONE_DIET
+	if (reg >= ARR_SIZE(reg_name_maps))
+		return NULL;
+
+	return reg_name_maps[reg].name;
+#else
+	return NULL;
+#endif
+}
+
+xcore_reg XCore_reg_id(char *name)
+{
+	int i;
+
+	for(i = 1; i < ARR_SIZE(reg_name_maps); i++) {
+		if (!strcmp(name, reg_name_maps[i].name))
+			return reg_name_maps[i].id;
+	}
+
+	// not found
+	return 0;
+}
+
+static const insn_map insns[] = {
+	// dummy item
+	{
+		0, 0,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+	},
+
+#include "XCoreMappingInsn.inc"
+};
+
+// given internal insn id, return public instruction info
+void XCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
+{
+	unsigned short i;
+
+	i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
+	if (i != 0) {
+		insn->id = insns[i].mapid;
+
+		if (h->detail) {
+#ifndef CAPSTONE_DIET
+			memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
+			insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
+
+			memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
+			insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
+
+			memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
+			insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups);
+
+			if (insns[i].branch || insns[i].indirect_branch) {
+				// this insn also belongs to JUMP group. add JUMP group
+				insn->detail->groups[insn->detail->groups_count] = XCORE_GRP_JUMP;
+				insn->detail->groups_count++;
+			}
+#endif
+		}
+	}
+}
+
+#ifndef CAPSTONE_DIET
+static const name_map insn_name_maps[] = {
+	{ XCORE_INS_INVALID, NULL },
+
+	{ XCORE_INS_ADD, "add" },
+	{ XCORE_INS_ANDNOT, "andnot" },
+	{ XCORE_INS_AND, "and" },
+	{ XCORE_INS_ASHR, "ashr" },
+	{ XCORE_INS_BAU, "bau" },
+	{ XCORE_INS_BITREV, "bitrev" },
+	{ XCORE_INS_BLA, "bla" },
+	{ XCORE_INS_BLAT, "blat" },
+	{ XCORE_INS_BL, "bl" },
+	{ XCORE_INS_BF, "bf" },
+	{ XCORE_INS_BT, "bt" },
+	{ XCORE_INS_BU, "bu" },
+	{ XCORE_INS_BRU, "bru" },
+	{ XCORE_INS_BYTEREV, "byterev" },
+	{ XCORE_INS_CHKCT, "chkct" },
+	{ XCORE_INS_CLRE, "clre" },
+	{ XCORE_INS_CLRPT, "clrpt" },
+	{ XCORE_INS_CLRSR, "clrsr" },
+	{ XCORE_INS_CLZ, "clz" },
+	{ XCORE_INS_CRC8, "crc8" },
+	{ XCORE_INS_CRC32, "crc32" },
+	{ XCORE_INS_DCALL, "dcall" },
+	{ XCORE_INS_DENTSP, "dentsp" },
+	{ XCORE_INS_DGETREG, "dgetreg" },
+	{ XCORE_INS_DIVS, "divs" },
+	{ XCORE_INS_DIVU, "divu" },
+	{ XCORE_INS_DRESTSP, "drestsp" },
+	{ XCORE_INS_DRET, "dret" },
+	{ XCORE_INS_ECALLF, "ecallf" },
+	{ XCORE_INS_ECALLT, "ecallt" },
+	{ XCORE_INS_EDU, "edu" },
+	{ XCORE_INS_EEF, "eef" },
+	{ XCORE_INS_EET, "eet" },
+	{ XCORE_INS_EEU, "eeu" },
+	{ XCORE_INS_ENDIN, "endin" },
+	{ XCORE_INS_ENTSP, "entsp" },
+	{ XCORE_INS_EQ, "eq" },
+	{ XCORE_INS_EXTDP, "extdp" },
+	{ XCORE_INS_EXTSP, "extsp" },
+	{ XCORE_INS_FREER, "freer" },
+	{ XCORE_INS_FREET, "freet" },
+	{ XCORE_INS_GETD, "getd" },
+	{ XCORE_INS_GET, "get" },
+	{ XCORE_INS_GETN, "getn" },
+	{ XCORE_INS_GETR, "getr" },
+	{ XCORE_INS_GETSR, "getsr" },
+	{ XCORE_INS_GETST, "getst" },
+	{ XCORE_INS_GETTS, "getts" },
+	{ XCORE_INS_INCT, "inct" },
+	{ XCORE_INS_INIT, "init" },
+	{ XCORE_INS_INPW, "inpw" },
+	{ XCORE_INS_INSHR, "inshr" },
+	{ XCORE_INS_INT, "int" },
+	{ XCORE_INS_IN, "in" },
+	{ XCORE_INS_KCALL, "kcall" },
+	{ XCORE_INS_KENTSP, "kentsp" },
+	{ XCORE_INS_KRESTSP, "krestsp" },
+	{ XCORE_INS_KRET, "kret" },
+	{ XCORE_INS_LADD, "ladd" },
+	{ XCORE_INS_LD16S, "ld16s" },
+	{ XCORE_INS_LD8U, "ld8u" },
+	{ XCORE_INS_LDA16, "lda16" },
+	{ XCORE_INS_LDAP, "ldap" },
+	{ XCORE_INS_LDAW, "ldaw" },
+	{ XCORE_INS_LDC, "ldc" },
+	{ XCORE_INS_LDW, "ldw" },
+	{ XCORE_INS_LDIVU, "ldivu" },
+	{ XCORE_INS_LMUL, "lmul" },
+	{ XCORE_INS_LSS, "lss" },
+	{ XCORE_INS_LSUB, "lsub" },
+	{ XCORE_INS_LSU, "lsu" },
+	{ XCORE_INS_MACCS, "maccs" },
+	{ XCORE_INS_MACCU, "maccu" },
+	{ XCORE_INS_MJOIN, "mjoin" },
+	{ XCORE_INS_MKMSK, "mkmsk" },
+	{ XCORE_INS_MSYNC, "msync" },
+	{ XCORE_INS_MUL, "mul" },
+	{ XCORE_INS_NEG, "neg" },
+	{ XCORE_INS_NOT, "not" },
+	{ XCORE_INS_OR, "or" },
+	{ XCORE_INS_OUTCT, "outct" },
+	{ XCORE_INS_OUTPW, "outpw" },
+	{ XCORE_INS_OUTSHR, "outshr" },
+	{ XCORE_INS_OUTT, "outt" },
+	{ XCORE_INS_OUT, "out" },
+	{ XCORE_INS_PEEK, "peek" },
+	{ XCORE_INS_REMS, "rems" },
+	{ XCORE_INS_REMU, "remu" },
+	{ XCORE_INS_RETSP, "retsp" },
+	{ XCORE_INS_SETCLK, "setclk" },
+	{ XCORE_INS_SET, "set" },
+	{ XCORE_INS_SETC, "setc" },
+	{ XCORE_INS_SETD, "setd" },
+	{ XCORE_INS_SETEV, "setev" },
+	{ XCORE_INS_SETN, "setn" },
+	{ XCORE_INS_SETPSC, "setpsc" },
+	{ XCORE_INS_SETPT, "setpt" },
+	{ XCORE_INS_SETRDY, "setrdy" },
+	{ XCORE_INS_SETSR, "setsr" },
+	{ XCORE_INS_SETTW, "settw" },
+	{ XCORE_INS_SETV, "setv" },
+	{ XCORE_INS_SEXT, "sext" },
+	{ XCORE_INS_SHL, "shl" },
+	{ XCORE_INS_SHR, "shr" },
+	{ XCORE_INS_SSYNC, "ssync" },
+	{ XCORE_INS_ST16, "st16" },
+	{ XCORE_INS_ST8, "st8" },
+	{ XCORE_INS_STW, "stw" },
+	{ XCORE_INS_SUB, "sub" },
+	{ XCORE_INS_SYNCR, "syncr" },
+	{ XCORE_INS_TESTCT, "testct" },
+	{ XCORE_INS_TESTLCL, "testlcl" },
+	{ XCORE_INS_TESTWCT, "testwct" },
+	{ XCORE_INS_TSETMR, "tsetmr" },
+	{ XCORE_INS_START, "start" },
+	{ XCORE_INS_WAITEF, "waitef" },
+	{ XCORE_INS_WAITET, "waitet" },
+	{ XCORE_INS_WAITEU, "waiteu" },
+	{ XCORE_INS_XOR, "xor" },
+	{ XCORE_INS_ZEXT, "zext" },
+};
+
+// special alias insn
+static const name_map alias_insn_names[] = {
+	{ 0, NULL }
+};
+#endif
+
+const char *XCore_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	unsigned int i;
+
+	if (id >= XCORE_INS_ENDING)
+		return NULL;
+
+	// handle special alias first
+	for (i = 0; i < ARR_SIZE(alias_insn_names); i++) {
+		if (alias_insn_names[i].id == id)
+			return alias_insn_names[i].name;
+	}
+
+	return insn_name_maps[id].name;
+#else
+	return NULL;
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static const name_map group_name_maps[] = {
+	{ XCORE_GRP_INVALID, NULL },
+	{ XCORE_GRP_JUMP, "jump" },
+};
+#endif
+
+const char *XCore_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
+#else
+	return NULL;
+#endif
+}
+
+// map internal raw register to 'public' register
+xcore_reg XCore_map_register(unsigned int r)
+{
+	static const unsigned int map[] = { 0,
+	};
+
+	if (r < ARR_SIZE(map))
+		return map[r];
+
+	// cannot find this register
+	return 0;
+}
+
+#endif
diff --git a/capstone/arch/XCore/XCoreMapping.h b/capstone/arch/XCore/XCoreMapping.h
new file mode 100644
index 000000000..f9b506a25
--- /dev/null
+++ b/capstone/arch/XCore/XCoreMapping.h
@@ -0,0 +1,26 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_XCORE_MAP_H
+#define CS_XCORE_MAP_H
+
+#include "capstone/capstone.h"
+
+// return name of regiser in friendly string
+const char *XCore_reg_name(csh handle, unsigned int reg);
+
+// given internal insn id, return public instruction info
+void XCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *XCore_insn_name(csh handle, unsigned int id);
+
+const char *XCore_group_name(csh handle, unsigned int id);
+
+// map internal raw register to 'public' register
+xcore_reg XCore_map_register(unsigned int r);
+
+// map register name to register ID
+xcore_reg XCore_reg_id(char *name);
+
+#endif
+
diff --git a/capstone/arch/XCore/XCoreMappingInsn.inc b/capstone/arch/XCore/XCoreMappingInsn.inc
new file mode 100644
index 000000000..7d115724b
--- /dev/null
+++ b/capstone/arch/XCore/XCoreMappingInsn.inc
@@ -0,0 +1,1287 @@
+// This is auto-gen data for Capstone engine (www.capstone-engine.org)
+// By Nguyen Anh Quynh <aquynh@gmail.com>
+
+{
+	XCore_ADD_2rus, XCORE_INS_ADD,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_ADD_3r, XCORE_INS_ADD,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_ANDNOT_2r, XCORE_INS_ANDNOT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_AND_3r, XCORE_INS_AND,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_ASHR_l2rus, XCORE_INS_ASHR,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_ASHR_l3r, XCORE_INS_ASHR,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_BAU_1r, XCORE_INS_BAU,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 1, 1
+#endif
+},
+{
+	XCore_BITREV_l2r, XCORE_INS_BITREV,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_BLACP_lu10, XCORE_INS_BLA,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_BLACP_u10, XCORE_INS_BLA,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_BLAT_lu6, XCORE_INS_BLAT,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_R11, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_BLAT_u6, XCORE_INS_BLAT,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_R11, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_BLA_1r, XCORE_INS_BLA,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_BLRB_lu10, XCORE_INS_BL,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_BLRB_u10, XCORE_INS_BL,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_BLRF_lu10, XCORE_INS_BL,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_BLRF_u10, XCORE_INS_BL,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_BRBF_lru6, XCORE_INS_BF,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 1, 0
+#endif
+},
+{
+	XCore_BRBF_ru6, XCORE_INS_BF,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 1, 0
+#endif
+},
+{
+	XCore_BRBT_lru6, XCORE_INS_BT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 1, 0
+#endif
+},
+{
+	XCore_BRBT_ru6, XCORE_INS_BT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 1, 0
+#endif
+},
+{
+	XCore_BRBU_lu6, XCORE_INS_BU,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 1, 0
+#endif
+},
+{
+	XCore_BRBU_u6, XCORE_INS_BU,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 1, 0
+#endif
+},
+{
+	XCore_BRFF_lru6, XCORE_INS_BF,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 1, 0
+#endif
+},
+{
+	XCore_BRFF_ru6, XCORE_INS_BF,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 1, 0
+#endif
+},
+{
+	XCore_BRFT_lru6, XCORE_INS_BT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 1, 0
+#endif
+},
+{
+	XCore_BRFT_ru6, XCORE_INS_BT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 1, 0
+#endif
+},
+{
+	XCore_BRFU_lu6, XCORE_INS_BU,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 1, 0
+#endif
+},
+{
+	XCore_BRFU_u6, XCORE_INS_BU,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 1, 0
+#endif
+},
+{
+	XCore_BRU_1r, XCORE_INS_BRU,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 1, 1
+#endif
+},
+{
+	XCore_BYTEREV_l2r, XCORE_INS_BYTEREV,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_CHKCT_2r, XCORE_INS_CHKCT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_CHKCT_rus, XCORE_INS_CHKCT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_CLRE_0R, XCORE_INS_CLRE,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_CLRPT_1R, XCORE_INS_CLRPT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_CLRSR_branch_lu6, XCORE_INS_CLRSR,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 1, 1
+#endif
+},
+{
+	XCore_CLRSR_branch_u6, XCORE_INS_CLRSR,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 1, 1
+#endif
+},
+{
+	XCore_CLRSR_lu6, XCORE_INS_CLRSR,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_CLRSR_u6, XCORE_INS_CLRSR,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_CLZ_l2r, XCORE_INS_CLZ,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_CRC8_l4r, XCORE_INS_CRC8,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_CRC_l3r, XCORE_INS_CRC32,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_DCALL_0R, XCORE_INS_DCALL,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_DENTSP_0R, XCORE_INS_DENTSP,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_DGETREG_1r, XCORE_INS_DGETREG,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_DIVS_l3r, XCORE_INS_DIVS,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_DIVU_l3r, XCORE_INS_DIVU,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_DRESTSP_0R, XCORE_INS_DRESTSP,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_DRET_0R, XCORE_INS_DRET,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_ECALLF_1r, XCORE_INS_ECALLF,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_ECALLT_1r, XCORE_INS_ECALLT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_EDU_1r, XCORE_INS_EDU,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_EEF_2r, XCORE_INS_EEF,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_EET_2r, XCORE_INS_EET,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_EEU_1r, XCORE_INS_EEU,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_ENDIN_2r, XCORE_INS_ENDIN,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_ENTSP_lu6, XCORE_INS_ENTSP,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_ENTSP_u6, XCORE_INS_ENTSP,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_EQ_2rus, XCORE_INS_EQ,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_EQ_3r, XCORE_INS_EQ,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_EXTDP_lu6, XCORE_INS_EXTDP,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_EXTDP_u6, XCORE_INS_EXTDP,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_EXTSP_lu6, XCORE_INS_EXTSP,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_EXTSP_u6, XCORE_INS_EXTSP,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_FREER_1r, XCORE_INS_FREER,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_FREET_0R, XCORE_INS_FREET,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_GETD_l2r, XCORE_INS_GETD,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_GETED_0R, XCORE_INS_GET,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_GETET_0R, XCORE_INS_GET,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_GETID_0R, XCORE_INS_GET,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_GETKEP_0R, XCORE_INS_GET,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_GETKSP_0R, XCORE_INS_GET,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_GETN_l2r, XCORE_INS_GETN,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_GETPS_l2r, XCORE_INS_GET,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_GETR_rus, XCORE_INS_GETR,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_GETSR_lu6, XCORE_INS_GETSR,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_GETSR_u6, XCORE_INS_GETSR,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_GETST_2r, XCORE_INS_GETST,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_GETTS_2r, XCORE_INS_GETTS,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_INCT_2r, XCORE_INS_INCT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_INITCP_2r, XCORE_INS_INIT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_INITDP_2r, XCORE_INS_INIT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_INITLR_l2r, XCORE_INS_INIT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_INITPC_2r, XCORE_INS_INIT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_INITSP_2r, XCORE_INS_INIT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_INPW_l2rus, XCORE_INS_INPW,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_INSHR_2r, XCORE_INS_INSHR,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_INT_2r, XCORE_INS_INT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_IN_2r, XCORE_INS_IN,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_KCALL_1r, XCORE_INS_KCALL,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_KCALL_lu6, XCORE_INS_KCALL,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_KCALL_u6, XCORE_INS_KCALL,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_KENTSP_lu6, XCORE_INS_KENTSP,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_KENTSP_u6, XCORE_INS_KENTSP,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_KRESTSP_lu6, XCORE_INS_KRESTSP,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_KRESTSP_u6, XCORE_INS_KRESTSP,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_KRET_0R, XCORE_INS_KRET,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LADD_l5r, XCORE_INS_LADD,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LD16S_3r, XCORE_INS_LD16S,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LD8U_3r, XCORE_INS_LD8U,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDA16B_l3r, XCORE_INS_LDA16,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDA16F_l3r, XCORE_INS_LDA16,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDAPB_lu10, XCORE_INS_LDAP,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDAPB_u10, XCORE_INS_LDAP,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDAPF_lu10, XCORE_INS_LDAP,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDAPF_lu10_ba, XCORE_INS_LDAP,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDAPF_u10, XCORE_INS_LDAP,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDAWB_l2rus, XCORE_INS_LDAW,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDAWB_l3r, XCORE_INS_LDAW,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDAWCP_lu6, XCORE_INS_LDAW,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDAWCP_u6, XCORE_INS_LDAW,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDAWDP_lru6, XCORE_INS_LDAW,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDAWDP_ru6, XCORE_INS_LDAW,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDAWF_l2rus, XCORE_INS_LDAW,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDAWF_l3r, XCORE_INS_LDAW,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDAWSP_lru6, XCORE_INS_LDAW,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDAWSP_ru6, XCORE_INS_LDAW,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDC_lru6, XCORE_INS_LDC,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDC_ru6, XCORE_INS_LDC,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDET_0R, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDIVU_l5r, XCORE_INS_LDIVU,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDSED_0R, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDSPC_0R, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDSSR_0R, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDWCP_lru6, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDWCP_lu10, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDWCP_ru6, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDWCP_u10, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDWDP_lru6, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDWDP_ru6, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDWSP_lru6, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDWSP_ru6, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDW_2rus, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LDW_3r, XCORE_INS_LDW,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LMUL_l6r, XCORE_INS_LMUL,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LSS_3r, XCORE_INS_LSS,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LSUB_l5r, XCORE_INS_LSUB,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_LSU_3r, XCORE_INS_LSU,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_MACCS_l4r, XCORE_INS_MACCS,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_MACCU_l4r, XCORE_INS_MACCU,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_MJOIN_1r, XCORE_INS_MJOIN,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_MKMSK_2r, XCORE_INS_MKMSK,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_MKMSK_rus, XCORE_INS_MKMSK,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_MSYNC_1r, XCORE_INS_MSYNC,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_MUL_l3r, XCORE_INS_MUL,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_NEG, XCORE_INS_NEG,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_NOT, XCORE_INS_NOT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_OR_3r, XCORE_INS_OR,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_OUTCT_2r, XCORE_INS_OUTCT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_OUTCT_rus, XCORE_INS_OUTCT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_OUTPW_l2rus, XCORE_INS_OUTPW,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_OUTSHR_2r, XCORE_INS_OUTSHR,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_OUTT_2r, XCORE_INS_OUTT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_OUT_2r, XCORE_INS_OUT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_PEEK_2r, XCORE_INS_PEEK,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_REMS_l3r, XCORE_INS_REMS,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_REMU_l3r, XCORE_INS_REMU,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_RETSP_lu6, XCORE_INS_RETSP,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_RETSP_u6, XCORE_INS_RETSP,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SETCLK_l2r, XCORE_INS_SETCLK,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SETCP_1r, XCORE_INS_SET,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SETC_l2r, XCORE_INS_SETC,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SETC_lru6, XCORE_INS_SETC,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SETC_ru6, XCORE_INS_SETC,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SETDP_1r, XCORE_INS_SET,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SETD_2r, XCORE_INS_SETD,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SETEV_1r, XCORE_INS_SETEV,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_R11, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SETKEP_0R, XCORE_INS_SET,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_R11, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SETN_l2r, XCORE_INS_SETN,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SETPSC_2r, XCORE_INS_SETPSC,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SETPS_l2r, XCORE_INS_SET,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SETPT_2r, XCORE_INS_SETPT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SETRDY_l2r, XCORE_INS_SETRDY,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SETSP_1r, XCORE_INS_SET,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SETSR_branch_lu6, XCORE_INS_SETSR,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 1, 1
+#endif
+},
+{
+	XCore_SETSR_branch_u6, XCORE_INS_SETSR,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 1, 1
+#endif
+},
+{
+	XCore_SETSR_lu6, XCORE_INS_SETSR,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SETSR_u6, XCORE_INS_SETSR,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SETTW_l2r, XCORE_INS_SETTW,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SETV_1r, XCORE_INS_SETV,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_R11, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SEXT_2r, XCORE_INS_SEXT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SEXT_rus, XCORE_INS_SEXT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SHL_2rus, XCORE_INS_SHL,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SHL_3r, XCORE_INS_SHL,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SHR_2rus, XCORE_INS_SHR,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SHR_3r, XCORE_INS_SHR,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SSYNC_0r, XCORE_INS_SSYNC,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_ST16_l3r, XCORE_INS_ST16,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_ST8_l3r, XCORE_INS_ST8,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_STET_0R, XCORE_INS_STW,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_STSED_0R, XCORE_INS_STW,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_STSPC_0R, XCORE_INS_STW,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_STSSR_0R, XCORE_INS_STW,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_STWDP_lru6, XCORE_INS_STW,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_STWDP_ru6, XCORE_INS_STW,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_STWSP_lru6, XCORE_INS_STW,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_STWSP_ru6, XCORE_INS_STW,
+#ifndef CAPSTONE_DIET
+	{ XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_STW_2rus, XCORE_INS_STW,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_STW_l3r, XCORE_INS_STW,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SUB_2rus, XCORE_INS_SUB,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SUB_3r, XCORE_INS_SUB,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_SYNCR_1r, XCORE_INS_SYNCR,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_TESTCT_2r, XCORE_INS_TESTCT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_TESTLCL_l2r, XCORE_INS_TESTLCL,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_TESTWCT_2r, XCORE_INS_TESTWCT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_TSETMR_2r, XCORE_INS_TSETMR,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_TSETR_3r, XCORE_INS_SET,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_TSTART_1R, XCORE_INS_START,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_WAITEF_1R, XCORE_INS_WAITEF,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_WAITET_1R, XCORE_INS_WAITET,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_WAITEU_0R, XCORE_INS_WAITEU,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 1, 1
+#endif
+},
+{
+	XCore_XOR_l3r, XCORE_INS_XOR,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_ZEXT_2r, XCORE_INS_ZEXT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
+{
+	XCore_ZEXT_rus, XCORE_INS_ZEXT,
+#ifndef CAPSTONE_DIET
+	{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+},
diff --git a/capstone/arch/XCore/XCoreModule.c b/capstone/arch/XCore/XCoreModule.c
new file mode 100644
index 000000000..90940d48b
--- /dev/null
+++ b/capstone/arch/XCore/XCoreModule.c
@@ -0,0 +1,41 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifdef CAPSTONE_HAS_XCORE
+
+#include "../../utils.h"
+#include "../../MCRegisterInfo.h"
+#include "XCoreDisassembler.h"
+#include "XCoreInstPrinter.h"
+#include "XCoreMapping.h"
+#include "XCoreModule.h"
+
+cs_err XCore_global_init(cs_struct *ud)
+{
+	MCRegisterInfo *mri;
+	mri = cs_mem_malloc(sizeof(*mri));
+
+	XCore_init(mri);
+	ud->printer = XCore_printInst;
+	ud->printer_info = mri;
+	ud->getinsn_info = mri;
+	ud->disasm = XCore_getInstruction;
+	ud->post_printer = XCore_post_printer;
+
+	ud->reg_name = XCore_reg_name;
+	ud->insn_id = XCore_get_insn_id;
+	ud->insn_name = XCore_insn_name;
+	ud->group_name = XCore_group_name;
+
+	return CS_ERR_OK;
+}
+
+cs_err XCore_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	// Do not set mode because only CS_MODE_BIG_ENDIAN is valid; we cannot
+	// test for CS_MODE_LITTLE_ENDIAN because it is 0
+
+	return CS_ERR_OK;
+}
+
+#endif
diff --git a/capstone/arch/XCore/XCoreModule.h b/capstone/arch/XCore/XCoreModule.h
new file mode 100644
index 000000000..c4a7d2b26
--- /dev/null
+++ b/capstone/arch/XCore/XCoreModule.h
@@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
+
+#ifndef CS_XCORE_MODULE_H
+#define CS_XCORE_MODULE_H
+
+#include "../../utils.h"
+
+cs_err XCore_global_init(cs_struct *ud);
+cs_err XCore_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif