+#ifndef CAPSTONE_ARM_H

+#define CAPSTONE_ARM_H

+

+/* Capstone Disassembly Engine */

+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+#include "platform.h"

+

+#ifdef _MSC_VER

+#pragma warning(disable:4201)

+#endif

+

+/// ARM shift type

+typedef enum arm_shifter {

+ ARM_SFT_INVALID = 0,

+ ARM_SFT_ASR, ///< shift with immediate const

+ ARM_SFT_LSL, ///< shift with immediate const

+ ARM_SFT_LSR, ///< shift with immediate const

+ ARM_SFT_ROR, ///< shift with immediate const

+ ARM_SFT_RRX, ///< shift with immediate const

+ ARM_SFT_ASR_REG, ///< shift with register

+ ARM_SFT_LSL_REG, ///< shift with register

+ ARM_SFT_LSR_REG, ///< shift with register

+ ARM_SFT_ROR_REG, ///< shift with register

+ ARM_SFT_RRX_REG, ///< shift with register

+} arm_shifter;

+

+/// ARM condition code

+typedef enum arm_cc {

+ ARM_CC_INVALID = 0,

+ ARM_CC_EQ, ///< Equal Equal

+ ARM_CC_NE, ///< Not equal Not equal, or unordered

+ ARM_CC_HS, ///< Carry set >, ==, or unordered

+ ARM_CC_LO, ///< Carry clear Less than

+ ARM_CC_MI, ///< Minus, negative Less than

+ ARM_CC_PL, ///< Plus, positive or zero >, ==, or unordered

+ ARM_CC_VS, ///< Overflow Unordered

+ ARM_CC_VC, ///< No overflow Not unordered

+ ARM_CC_HI, ///< Unsigned higher Greater than, or unordered

+ ARM_CC_LS, ///< Unsigned lower or same Less than or equal

+ ARM_CC_GE, ///< Greater than or equal Greater than or equal

+ ARM_CC_LT, ///< Less than Less than, or unordered

+ ARM_CC_GT, ///< Greater than Greater than

+ ARM_CC_LE, ///< Less than or equal <, ==, or unordered

+ ARM_CC_AL ///< Always (unconditional) Always (unconditional)

+} arm_cc;

+

+typedef enum arm_sysreg {

+ /// Special registers for MSR

+ ARM_SYSREG_INVALID = 0,

+

+ // SPSR* registers can be OR combined

+ ARM_SYSREG_SPSR_C = 1,

+ ARM_SYSREG_SPSR_X = 2,

+ ARM_SYSREG_SPSR_S = 4,

+ ARM_SYSREG_SPSR_F = 8,

+

+ // CPSR* registers can be OR combined

+ ARM_SYSREG_CPSR_C = 16,

+ ARM_SYSREG_CPSR_X = 32,

+ ARM_SYSREG_CPSR_S = 64,

+ ARM_SYSREG_CPSR_F = 128,

+

+ // independent registers

+ ARM_SYSREG_APSR = 256,

+ ARM_SYSREG_APSR_G,

+ ARM_SYSREG_APSR_NZCVQ,

+ ARM_SYSREG_APSR_NZCVQG,

+

+ ARM_SYSREG_IAPSR,

+ ARM_SYSREG_IAPSR_G,

+ ARM_SYSREG_IAPSR_NZCVQG,

+ ARM_SYSREG_IAPSR_NZCVQ,

+

+ ARM_SYSREG_EAPSR,

+ ARM_SYSREG_EAPSR_G,

+ ARM_SYSREG_EAPSR_NZCVQG,

+ ARM_SYSREG_EAPSR_NZCVQ,

+

+ ARM_SYSREG_XPSR,

+ ARM_SYSREG_XPSR_G,

+ ARM_SYSREG_XPSR_NZCVQG,

+ ARM_SYSREG_XPSR_NZCVQ,

+

+ ARM_SYSREG_IPSR,

+ ARM_SYSREG_EPSR,

+ ARM_SYSREG_IEPSR,

+

+ ARM_SYSREG_MSP,

+ ARM_SYSREG_PSP,

+ ARM_SYSREG_PRIMASK,

+ ARM_SYSREG_BASEPRI,

+ ARM_SYSREG_BASEPRI_MAX,

+ ARM_SYSREG_FAULTMASK,

+ ARM_SYSREG_CONTROL,

+ ARM_SYSREG_MSPLIM,

+ ARM_SYSREG_PSPLIM,

+ ARM_SYSREG_MSP_NS,

+ ARM_SYSREG_PSP_NS,

+ ARM_SYSREG_MSPLIM_NS,

+ ARM_SYSREG_PSPLIM_NS,

+ ARM_SYSREG_PRIMASK_NS,

+ ARM_SYSREG_BASEPRI_NS,

+ ARM_SYSREG_FAULTMASK_NS,

+ ARM_SYSREG_CONTROL_NS,

+ ARM_SYSREG_SP_NS,

+

+ // Banked Registers

+ ARM_SYSREG_R8_USR,

+ ARM_SYSREG_R9_USR,

+ ARM_SYSREG_R10_USR,

+ ARM_SYSREG_R11_USR,

+ ARM_SYSREG_R12_USR,

+ ARM_SYSREG_SP_USR,

+ ARM_SYSREG_LR_USR,

+ ARM_SYSREG_R8_FIQ,

+ ARM_SYSREG_R9_FIQ,

+ ARM_SYSREG_R10_FIQ,

+ ARM_SYSREG_R11_FIQ,

+ ARM_SYSREG_R12_FIQ,

+ ARM_SYSREG_SP_FIQ,

+ ARM_SYSREG_LR_FIQ,

+ ARM_SYSREG_LR_IRQ,

+ ARM_SYSREG_SP_IRQ,

+ ARM_SYSREG_LR_SVC,

+ ARM_SYSREG_SP_SVC,

+ ARM_SYSREG_LR_ABT,

+ ARM_SYSREG_SP_ABT,

+ ARM_SYSREG_LR_UND,

+ ARM_SYSREG_SP_UND,

+ ARM_SYSREG_LR_MON,

+ ARM_SYSREG_SP_MON,

+ ARM_SYSREG_ELR_HYP,

+ ARM_SYSREG_SP_HYP,

+

+ ARM_SYSREG_SPSR_FIQ,

+ ARM_SYSREG_SPSR_IRQ,

+ ARM_SYSREG_SPSR_SVC,

+ ARM_SYSREG_SPSR_ABT,

+ ARM_SYSREG_SPSR_UND,

+ ARM_SYSREG_SPSR_MON,

+ ARM_SYSREG_SPSR_HYP,

+} arm_sysreg;

+

+/// The memory barrier constants map directly to the 4-bit encoding of

+/// the option field for Memory Barrier operations.

+typedef enum arm_mem_barrier {

+ ARM_MB_INVALID = 0,

+ ARM_MB_RESERVED_0,

+ ARM_MB_OSHLD,

+ ARM_MB_OSHST,

+ ARM_MB_OSH,

+ ARM_MB_RESERVED_4,

+ ARM_MB_NSHLD,

+ ARM_MB_NSHST,

+ ARM_MB_NSH,

+ ARM_MB_RESERVED_8,

+ ARM_MB_ISHLD,

+ ARM_MB_ISHST,

+ ARM_MB_ISH,

+ ARM_MB_RESERVED_12,

+ ARM_MB_LD,

+ ARM_MB_ST,

+ ARM_MB_SY,

+} arm_mem_barrier;

+

+/// Operand type for instruction's operands

+typedef enum arm_op_type {

+ ARM_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).

+ ARM_OP_REG, ///< = CS_OP_REG (Register operand).

+ ARM_OP_IMM, ///< = CS_OP_IMM (Immediate operand).

+ ARM_OP_MEM, ///< = CS_OP_MEM (Memory operand).

+ ARM_OP_FP, ///< = CS_OP_FP (Floating-Point operand).

+ ARM_OP_CIMM = 64, ///< C-Immediate (coprocessor registers)

+ ARM_OP_PIMM, ///< P-Immediate (coprocessor registers)

+ ARM_OP_SETEND, ///< operand for SETEND instruction

+ ARM_OP_SYSREG, ///< MSR/MRS special register operand

+} arm_op_type;

+

+/// Operand type for SETEND instruction

+typedef enum arm_setend_type {

+ ARM_SETEND_INVALID = 0, ///< Uninitialized.

+ ARM_SETEND_BE, ///< BE operand.

+ ARM_SETEND_LE, ///< LE operand

+} arm_setend_type;

+

+typedef enum arm_cpsmode_type {

+ ARM_CPSMODE_INVALID = 0,

+ ARM_CPSMODE_IE = 2,

+ ARM_CPSMODE_ID = 3

+} arm_cpsmode_type;

+

+/// Operand type for SETEND instruction

+typedef enum arm_cpsflag_type {

+ ARM_CPSFLAG_INVALID = 0,

+ ARM_CPSFLAG_F = 1,

+ ARM_CPSFLAG_I = 2,

+ ARM_CPSFLAG_A = 4,

+ ARM_CPSFLAG_NONE = 16, ///< no flag

+} arm_cpsflag_type;

+

+/// Data type for elements of vector instructions.

+typedef enum arm_vectordata_type {

+ ARM_VECTORDATA_INVALID = 0,

+

+ // Integer type

+ ARM_VECTORDATA_I8,

+ ARM_VECTORDATA_I16,

+ ARM_VECTORDATA_I32,

+ ARM_VECTORDATA_I64,

+

+ // Signed integer type

+ ARM_VECTORDATA_S8,

+ ARM_VECTORDATA_S16,

+ ARM_VECTORDATA_S32,

+ ARM_VECTORDATA_S64,

+

+ // Unsigned integer type

+ ARM_VECTORDATA_U8,

+ ARM_VECTORDATA_U16,

+ ARM_VECTORDATA_U32,

+ ARM_VECTORDATA_U64,

+

+ // Data type for VMUL/VMULL

+ ARM_VECTORDATA_P8,

+

+ // Floating type

+ ARM_VECTORDATA_F16,

+ ARM_VECTORDATA_F32,

+ ARM_VECTORDATA_F64,

+

+ // Convert float <-> float

+ ARM_VECTORDATA_F16F64, // f16.f64

+ ARM_VECTORDATA_F64F16, // f64.f16

+ ARM_VECTORDATA_F32F16, // f32.f16

+ ARM_VECTORDATA_F16F32, // f32.f16

+ ARM_VECTORDATA_F64F32, // f64.f32

+ ARM_VECTORDATA_F32F64, // f32.f64

+

+ // Convert integer <-> float

+ ARM_VECTORDATA_S32F32, // s32.f32

+ ARM_VECTORDATA_U32F32, // u32.f32

+ ARM_VECTORDATA_F32S32, // f32.s32

+ ARM_VECTORDATA_F32U32, // f32.u32

+ ARM_VECTORDATA_F64S16, // f64.s16

+ ARM_VECTORDATA_F32S16, // f32.s16

+ ARM_VECTORDATA_F64S32, // f64.s32

+ ARM_VECTORDATA_S16F64, // s16.f64

+ ARM_VECTORDATA_S16F32, // s16.f64

+ ARM_VECTORDATA_S32F64, // s32.f64

+ ARM_VECTORDATA_U16F64, // u16.f64

+ ARM_VECTORDATA_U16F32, // u16.f32

+ ARM_VECTORDATA_U32F64, // u32.f64

+ ARM_VECTORDATA_F64U16, // f64.u16

+ ARM_VECTORDATA_F32U16, // f32.u16

+ ARM_VECTORDATA_F64U32, // f64.u32

+ ARM_VECTORDATA_F16U16, // f16.u16

+ ARM_VECTORDATA_U16F16, // u16.f16

+ ARM_VECTORDATA_F16U32, // f16.u32

+ ARM_VECTORDATA_U32F16, // u32.f16

+} arm_vectordata_type;

+

+/// ARM registers

+typedef enum arm_reg {

+ ARM_REG_INVALID = 0,

+ ARM_REG_APSR,

+ ARM_REG_APSR_NZCV,

+ ARM_REG_CPSR,

+ ARM_REG_FPEXC,

+ ARM_REG_FPINST,

+ ARM_REG_FPSCR,

+ ARM_REG_FPSCR_NZCV,

+ ARM_REG_FPSID,

+ ARM_REG_ITSTATE,

+ ARM_REG_LR,

+ ARM_REG_PC,

+ ARM_REG_SP,

+ ARM_REG_SPSR,

+ ARM_REG_D0,

+ ARM_REG_D1,

+ ARM_REG_D2,

+ ARM_REG_D3,

+ ARM_REG_D4,

+ ARM_REG_D5,

+ ARM_REG_D6,

+ ARM_REG_D7,

+ ARM_REG_D8,

+ ARM_REG_D9,

+ ARM_REG_D10,

+ ARM_REG_D11,

+ ARM_REG_D12,

+ ARM_REG_D13,

+ ARM_REG_D14,

+ ARM_REG_D15,

+ ARM_REG_D16,

+ ARM_REG_D17,

+ ARM_REG_D18,

+ ARM_REG_D19,

+ ARM_REG_D20,

+ ARM_REG_D21,

+ ARM_REG_D22,

+ ARM_REG_D23,

+ ARM_REG_D24,

+ ARM_REG_D25,

+ ARM_REG_D26,

+ ARM_REG_D27,

+ ARM_REG_D28,

+ ARM_REG_D29,

+ ARM_REG_D30,

+ ARM_REG_D31,

+ ARM_REG_FPINST2,

+ ARM_REG_MVFR0,

+ ARM_REG_MVFR1,

+ ARM_REG_MVFR2,

+ ARM_REG_Q0,

+ ARM_REG_Q1,

+ ARM_REG_Q2,

+ ARM_REG_Q3,

+ ARM_REG_Q4,

+ ARM_REG_Q5,

+ ARM_REG_Q6,

+ ARM_REG_Q7,

+ ARM_REG_Q8,

+ ARM_REG_Q9,

+ ARM_REG_Q10,

+ ARM_REG_Q11,

+ ARM_REG_Q12,

+ ARM_REG_Q13,

+ ARM_REG_Q14,

+ ARM_REG_Q15,

+ ARM_REG_R0,

+ ARM_REG_R1,

+ ARM_REG_R2,

+ ARM_REG_R3,

+ ARM_REG_R4,

+ ARM_REG_R5,

+ ARM_REG_R6,

+ ARM_REG_R7,

+ ARM_REG_R8,

+ ARM_REG_R9,

+ ARM_REG_R10,

+ ARM_REG_R11,

+ ARM_REG_R12,

+ ARM_REG_S0,

+ ARM_REG_S1,

+ ARM_REG_S2,

+ ARM_REG_S3,

+ ARM_REG_S4,

+ ARM_REG_S5,

+ ARM_REG_S6,

+ ARM_REG_S7,

+ ARM_REG_S8,

+ ARM_REG_S9,

+ ARM_REG_S10,

+ ARM_REG_S11,

+ ARM_REG_S12,

+ ARM_REG_S13,

+ ARM_REG_S14,

+ ARM_REG_S15,

+ ARM_REG_S16,

+ ARM_REG_S17,

+ ARM_REG_S18,

+ ARM_REG_S19,

+ ARM_REG_S20,

+ ARM_REG_S21,

+ ARM_REG_S22,

+ ARM_REG_S23,

+ ARM_REG_S24,

+ ARM_REG_S25,

+ ARM_REG_S26,

+ ARM_REG_S27,

+ ARM_REG_S28,

+ ARM_REG_S29,

+ ARM_REG_S30,

+ ARM_REG_S31,

+

+ ARM_REG_ENDING, // <-- mark the end of the list or registers

+

+ // alias registers

+ ARM_REG_R13 = ARM_REG_SP,

+ ARM_REG_R14 = ARM_REG_LR,

+ ARM_REG_R15 = ARM_REG_PC,

+

+ ARM_REG_SB = ARM_REG_R9,

+ ARM_REG_SL = ARM_REG_R10,

+ ARM_REG_FP = ARM_REG_R11,

+ ARM_REG_IP = ARM_REG_R12,

+} arm_reg;

+

+/// Instruction's operand referring to memory

+/// This is associated with ARM_OP_MEM operand type above

+typedef struct arm_op_mem {

+ arm_reg base; ///< base register

+ arm_reg index; ///< index register

+ int scale; ///< scale for index register (can be 1, or -1)

+ int disp; ///< displacement/offset value

+ /// left-shift on index register, or 0 if irrelevant

+ /// NOTE: this value can also be fetched via operand.shift.value

+ int lshift;

+} arm_op_mem;

+

+/// Instruction operand

+typedef struct cs_arm_op {

+ int vector_index; ///< Vector Index for some vector operands (or -1 if irrelevant)

+

+ struct {

+ arm_shifter type;

+ unsigned int value;

+ } shift;

+

+ arm_op_type type; ///< operand type

+

+ union {

+ int reg; ///< register value for REG/SYSREG operand

+ int32_t imm; ///< immediate value for C-IMM, P-IMM or IMM operand

+ double fp; ///< floating point value for FP operand

+ arm_op_mem mem; ///< base/index/scale/disp value for MEM operand

+ arm_setend_type setend; ///< SETEND instruction's operand type

+ };

+

+ /// in some instructions, an operand can be subtracted or added to

+ /// the base register,

+ /// if TRUE, this operand is subtracted. otherwise, it is added.

+ bool subtracted;

+

+ /// How is this operand accessed? (READ, WRITE or READ|WRITE)

+ /// This field is combined of cs_ac_type.

+ /// NOTE: this field is irrelevant if engine is compiled in DIET mode.

+ uint8_t access;

+

+ /// Neon lane index for NEON instructions (or -1 if irrelevant)

+ int8_t neon_lane;

+} cs_arm_op;

+

+/// Instruction structure

+typedef struct cs_arm {

+ bool usermode; ///< User-mode registers to be loaded (for LDM/STM instructions)

+ int vector_size; ///< Scalar size for vector instructions

+ arm_vectordata_type vector_data; ///< Data type for elements of vector instructions

+ arm_cpsmode_type cps_mode; ///< CPS mode for CPS instruction

+ arm_cpsflag_type cps_flag; ///< CPS mode for CPS instruction

+ arm_cc cc; ///< conditional code for this insn

+ bool update_flags; ///< does this insn update flags?

+ bool writeback; ///< does this insn write-back?

+ arm_mem_barrier mem_barrier; ///< Option for some memory barrier instructions

+

+ /// Number of operands of this instruction,

+ /// or 0 when instruction has no operand.

+ uint8_t op_count;

+

+ cs_arm_op operands[36]; ///< operands for this instruction.

+} cs_arm;

+

+/// ARM instruction

+typedef enum arm_insn {

+ ARM_INS_INVALID = 0,

+

+ ARM_INS_ADC,

+ ARM_INS_ADD,

+ ARM_INS_ADDW,

+ ARM_INS_ADR,

+ ARM_INS_AESD,

+ ARM_INS_AESE,

+ ARM_INS_AESIMC,

+ ARM_INS_AESMC,

+ ARM_INS_AND,

+ ARM_INS_ASR,

+ ARM_INS_B,

+ ARM_INS_BFC,

+ ARM_INS_BFI,

+ ARM_INS_BIC,

+ ARM_INS_BKPT,

+ ARM_INS_BL,

+ ARM_INS_BLX,

+ ARM_INS_BLXNS,

+ ARM_INS_BX,

+ ARM_INS_BXJ,

+ ARM_INS_BXNS,

+ ARM_INS_CBNZ,

+ ARM_INS_CBZ,

+ ARM_INS_CDP,

+ ARM_INS_CDP2,

+ ARM_INS_CLREX,

+ ARM_INS_CLZ,

+ ARM_INS_CMN,

+ ARM_INS_CMP,

+ ARM_INS_CPS,

+ ARM_INS_CRC32B,

+ ARM_INS_CRC32CB,

+ ARM_INS_CRC32CH,

+ ARM_INS_CRC32CW,

+ ARM_INS_CRC32H,

+ ARM_INS_CRC32W,

+ ARM_INS_CSDB,

+ ARM_INS_DBG,

+ ARM_INS_DCPS1,

+ ARM_INS_DCPS2,

+ ARM_INS_DCPS3,

+ ARM_INS_DFB,

+ ARM_INS_DMB,

+ ARM_INS_DSB,

+ ARM_INS_EOR,

+ ARM_INS_ERET,

+ ARM_INS_ESB,

+ ARM_INS_FADDD,

+ ARM_INS_FADDS,

+ ARM_INS_FCMPZD,

+ ARM_INS_FCMPZS,

+ ARM_INS_FCONSTD,

+ ARM_INS_FCONSTS,

+ ARM_INS_FLDMDBX,

+ ARM_INS_FLDMIAX,

+ ARM_INS_FMDHR,

+ ARM_INS_FMDLR,

+ ARM_INS_FMSTAT,

+ ARM_INS_FSTMDBX,

+ ARM_INS_FSTMIAX,

+ ARM_INS_FSUBD,

+ ARM_INS_FSUBS,

+ ARM_INS_HINT,

+ ARM_INS_HLT,

+ ARM_INS_HVC,

+ ARM_INS_ISB,

+ ARM_INS_IT,

+ ARM_INS_LDA,

+ ARM_INS_LDAB,

+ ARM_INS_LDAEX,

+ ARM_INS_LDAEXB,

+ ARM_INS_LDAEXD,

+ ARM_INS_LDAEXH,

+ ARM_INS_LDAH,

+ ARM_INS_LDC,

+ ARM_INS_LDC2,

+ ARM_INS_LDC2L,

+ ARM_INS_LDCL,

+ ARM_INS_LDM,

+ ARM_INS_LDMDA,

+ ARM_INS_LDMDB,

+ ARM_INS_LDMIB,

+ ARM_INS_LDR,

+ ARM_INS_LDRB,

+ ARM_INS_LDRBT,

+ ARM_INS_LDRD,

+ ARM_INS_LDREX,

+ ARM_INS_LDREXB,

+ ARM_INS_LDREXD,

+ ARM_INS_LDREXH,

+ ARM_INS_LDRH,

+ ARM_INS_LDRHT,

+ ARM_INS_LDRSB,

+ ARM_INS_LDRSBT,

+ ARM_INS_LDRSH,

+ ARM_INS_LDRSHT,

+ ARM_INS_LDRT,

+ ARM_INS_LSL,

+ ARM_INS_LSR,

+ ARM_INS_MCR,

+ ARM_INS_MCR2,

+ ARM_INS_MCRR,

+ ARM_INS_MCRR2,

+ ARM_INS_MLA,

+ ARM_INS_MLS,

+ ARM_INS_MOV,

+ ARM_INS_MOVS,

+ ARM_INS_MOVT,

+ ARM_INS_MOVW,

+ ARM_INS_MRC,

+ ARM_INS_MRC2,

+ ARM_INS_MRRC,

+ ARM_INS_MRRC2,

+ ARM_INS_MRS,

+ ARM_INS_MSR,

+ ARM_INS_MUL,

+ ARM_INS_MVN,

+ ARM_INS_NEG,

+ ARM_INS_NOP,

+ ARM_INS_ORN,

+ ARM_INS_ORR,

+ ARM_INS_PKHBT,

+ ARM_INS_PKHTB,

+ ARM_INS_PLD,

+ ARM_INS_PLDW,

+ ARM_INS_PLI,

+ ARM_INS_POP,

+ ARM_INS_PUSH,

+ ARM_INS_QADD,

+ ARM_INS_QADD16,

+ ARM_INS_QADD8,

+ ARM_INS_QASX,

+ ARM_INS_QDADD,

+ ARM_INS_QDSUB,

+ ARM_INS_QSAX,

+ ARM_INS_QSUB,

+ ARM_INS_QSUB16,

+ ARM_INS_QSUB8,

+ ARM_INS_RBIT,

+ ARM_INS_REV,

+ ARM_INS_REV16,

+ ARM_INS_REVSH,

+ ARM_INS_RFEDA,

+ ARM_INS_RFEDB,

+ ARM_INS_RFEIA,

+ ARM_INS_RFEIB,

+ ARM_INS_ROR,

+ ARM_INS_RRX,

+ ARM_INS_RSB,

+ ARM_INS_RSC,

+ ARM_INS_SADD16,

+ ARM_INS_SADD8,

+ ARM_INS_SASX,

+ ARM_INS_SBC,

+ ARM_INS_SBFX,

+ ARM_INS_SDIV,

+ ARM_INS_SEL,

+ ARM_INS_SETEND,

+ ARM_INS_SETPAN,

+ ARM_INS_SEV,

+ ARM_INS_SEVL,

+ ARM_INS_SG,

+ ARM_INS_SHA1C,

+ ARM_INS_SHA1H,

+ ARM_INS_SHA1M,

+ ARM_INS_SHA1P,

+ ARM_INS_SHA1SU0,

+ ARM_INS_SHA1SU1,

+ ARM_INS_SHA256H,

+ ARM_INS_SHA256H2,

+ ARM_INS_SHA256SU0,

+ ARM_INS_SHA256SU1,

+ ARM_INS_SHADD16,

+ ARM_INS_SHADD8,

+ ARM_INS_SHASX,

+ ARM_INS_SHSAX,

+ ARM_INS_SHSUB16,

+ ARM_INS_SHSUB8,

+ ARM_INS_SMC,

+ ARM_INS_SMLABB,

+ ARM_INS_SMLABT,

+ ARM_INS_SMLAD,

+ ARM_INS_SMLADX,

+ ARM_INS_SMLAL,

+ ARM_INS_SMLALBB,

+ ARM_INS_SMLALBT,

+ ARM_INS_SMLALD,

+ ARM_INS_SMLALDX,

+ ARM_INS_SMLALTB,

+ ARM_INS_SMLALTT,

+ ARM_INS_SMLATB,

+ ARM_INS_SMLATT,

+ ARM_INS_SMLAWB,

+ ARM_INS_SMLAWT,

+ ARM_INS_SMLSD,

+ ARM_INS_SMLSDX,

+ ARM_INS_SMLSLD,

+ ARM_INS_SMLSLDX,

+ ARM_INS_SMMLA,

+ ARM_INS_SMMLAR,

+ ARM_INS_SMMLS,

+ ARM_INS_SMMLSR,

+ ARM_INS_SMMUL,

+ ARM_INS_SMMULR,

+ ARM_INS_SMUAD,

+ ARM_INS_SMUADX,

+ ARM_INS_SMULBB,

+ ARM_INS_SMULBT,

+ ARM_INS_SMULL,

+ ARM_INS_SMULTB,

+ ARM_INS_SMULTT,

+ ARM_INS_SMULWB,

+ ARM_INS_SMULWT,

+ ARM_INS_SMUSD,

+ ARM_INS_SMUSDX,

+ ARM_INS_SRSDA,

+ ARM_INS_SRSDB,

+ ARM_INS_SRSIA,

+ ARM_INS_SRSIB,

+ ARM_INS_SSAT,

+ ARM_INS_SSAT16,

+ ARM_INS_SSAX,

+ ARM_INS_SSUB16,

+ ARM_INS_SSUB8,

+ ARM_INS_STC,

+ ARM_INS_STC2,

+ ARM_INS_STC2L,

+ ARM_INS_STCL,

+ ARM_INS_STL,

+ ARM_INS_STLB,

+ ARM_INS_STLEX,

+ ARM_INS_STLEXB,

+ ARM_INS_STLEXD,

+ ARM_INS_STLEXH,

+ ARM_INS_STLH,

+ ARM_INS_STM,

+ ARM_INS_STMDA,

+ ARM_INS_STMDB,

+ ARM_INS_STMIB,

+ ARM_INS_STR,

+ ARM_INS_STRB,

+ ARM_INS_STRBT,

+ ARM_INS_STRD,

+ ARM_INS_STREX,

+ ARM_INS_STREXB,

+ ARM_INS_STREXD,

+ ARM_INS_STREXH,

+ ARM_INS_STRH,

+ ARM_INS_STRHT,

+ ARM_INS_STRT,

+ ARM_INS_SUB,

+ ARM_INS_SUBS,

+ ARM_INS_SUBW,

+ ARM_INS_SVC,

+ ARM_INS_SWP,

+ ARM_INS_SWPB,

+ ARM_INS_SXTAB,

+ ARM_INS_SXTAB16,

+ ARM_INS_SXTAH,

+ ARM_INS_SXTB,

+ ARM_INS_SXTB16,

+ ARM_INS_SXTH,

+ ARM_INS_TBB,

+ ARM_INS_TBH,

+ ARM_INS_TEQ,

+ ARM_INS_TRAP,

+ ARM_INS_TSB,

+ ARM_INS_TST,

+ ARM_INS_TT,

+ ARM_INS_TTA,

+ ARM_INS_TTAT,

+ ARM_INS_TTT,

+ ARM_INS_UADD16,

+ ARM_INS_UADD8,

+ ARM_INS_UASX,

+ ARM_INS_UBFX,

+ ARM_INS_UDF,

+ ARM_INS_UDIV,

+ ARM_INS_UHADD16,

+ ARM_INS_UHADD8,

+ ARM_INS_UHASX,

+ ARM_INS_UHSAX,

+ ARM_INS_UHSUB16,

+ ARM_INS_UHSUB8,

+ ARM_INS_UMAAL,

+ ARM_INS_UMLAL,

+ ARM_INS_UMULL,

+ ARM_INS_UQADD16,

+ ARM_INS_UQADD8,

+ ARM_INS_UQASX,

+ ARM_INS_UQSAX,

+ ARM_INS_UQSUB16,

+ ARM_INS_UQSUB8,

+ ARM_INS_USAD8,

+ ARM_INS_USADA8,

+ ARM_INS_USAT,

+ ARM_INS_USAT16,

+ ARM_INS_USAX,

+ ARM_INS_USUB16,

+ ARM_INS_USUB8,

+ ARM_INS_UXTAB,

+ ARM_INS_UXTAB16,

+ ARM_INS_UXTAH,

+ ARM_INS_UXTB,

+ ARM_INS_UXTB16,

+ ARM_INS_UXTH,

+ ARM_INS_VABA,

+ ARM_INS_VABAL,

+ ARM_INS_VABD,

+ ARM_INS_VABDL,

+ ARM_INS_VABS,

+ ARM_INS_VACGE,

+ ARM_INS_VACGT,

+ ARM_INS_VACLE,

+ ARM_INS_VACLT,

+ ARM_INS_VADD,

+ ARM_INS_VADDHN,

+ ARM_INS_VADDL,

+ ARM_INS_VADDW,

+ ARM_INS_VAND,

+ ARM_INS_VBIC,

+ ARM_INS_VBIF,

+ ARM_INS_VBIT,

+ ARM_INS_VBSL,

+ ARM_INS_VCADD,

+ ARM_INS_VCEQ,

+ ARM_INS_VCGE,

+ ARM_INS_VCGT,

+ ARM_INS_VCLE,

+ ARM_INS_VCLS,

+ ARM_INS_VCLT,

+ ARM_INS_VCLZ,

+ ARM_INS_VCMLA,

+ ARM_INS_VCMP,

+ ARM_INS_VCMPE,

+ ARM_INS_VCNT,

+ ARM_INS_VCVT,

+ ARM_INS_VCVTA,

+ ARM_INS_VCVTB,

+ ARM_INS_VCVTM,

+ ARM_INS_VCVTN,

+ ARM_INS_VCVTP,

+ ARM_INS_VCVTR,

+ ARM_INS_VCVTT,

+ ARM_INS_VDIV,

+ ARM_INS_VDUP,

+ ARM_INS_VEOR,

+ ARM_INS_VEXT,

+ ARM_INS_VFMA,

+ ARM_INS_VFMS,

+ ARM_INS_VFNMA,

+ ARM_INS_VFNMS,

+ ARM_INS_VHADD,

+ ARM_INS_VHSUB,

+ ARM_INS_VINS,

+ ARM_INS_VJCVT,

+ ARM_INS_VLD1,

+ ARM_INS_VLD2,

+ ARM_INS_VLD3,

+ ARM_INS_VLD4,

+ ARM_INS_VLDMDB,

+ ARM_INS_VLDMIA,

+ ARM_INS_VLDR,

+ ARM_INS_VLLDM,

+ ARM_INS_VLSTM,

+ ARM_INS_VMAX,

+ ARM_INS_VMAXNM,

+ ARM_INS_VMIN,

+ ARM_INS_VMINNM,

+ ARM_INS_VMLA,

+ ARM_INS_VMLAL,

+ ARM_INS_VMLS,

+ ARM_INS_VMLSL,

+ ARM_INS_VMOV,

+ ARM_INS_VMOVL,

+ ARM_INS_VMOVN,

+ ARM_INS_VMOVX,

+ ARM_INS_VMRS,

+ ARM_INS_VMSR,

+ ARM_INS_VMUL,

+ ARM_INS_VMULL,

+ ARM_INS_VMVN,

+ ARM_INS_VNEG,

+ ARM_INS_VNMLA,

+ ARM_INS_VNMLS,

+ ARM_INS_VNMUL,

+ ARM_INS_VORN,

+ ARM_INS_VORR,

+ ARM_INS_VPADAL,

+ ARM_INS_VPADD,

+ ARM_INS_VPADDL,

+ ARM_INS_VPMAX,

+ ARM_INS_VPMIN,

+ ARM_INS_VPOP,

+ ARM_INS_VPUSH,

+ ARM_INS_VQABS,

+ ARM_INS_VQADD,

+ ARM_INS_VQDMLAL,

+ ARM_INS_VQDMLSL,

+ ARM_INS_VQDMULH,

+ ARM_INS_VQDMULL,

+ ARM_INS_VQMOVN,

+ ARM_INS_VQMOVUN,

+ ARM_INS_VQNEG,

+ ARM_INS_VQRDMLAH,

+ ARM_INS_VQRDMLSH,

+ ARM_INS_VQRDMULH,

+ ARM_INS_VQRSHL,

+ ARM_INS_VQRSHRN,

+ ARM_INS_VQRSHRUN,

+ ARM_INS_VQSHL,

+ ARM_INS_VQSHLU,

+ ARM_INS_VQSHRN,

+ ARM_INS_VQSHRUN,

+ ARM_INS_VQSUB,

+ ARM_INS_VRADDHN,

+ ARM_INS_VRECPE,

+ ARM_INS_VRECPS,

+ ARM_INS_VREV16,

+ ARM_INS_VREV32,

+ ARM_INS_VREV64,

+ ARM_INS_VRHADD,

+ ARM_INS_VRINTA,

+ ARM_INS_VRINTM,

+ ARM_INS_VRINTN,

+ ARM_INS_VRINTP,

+ ARM_INS_VRINTR,

+ ARM_INS_VRINTX,

+ ARM_INS_VRINTZ,

+ ARM_INS_VRSHL,

+ ARM_INS_VRSHR,

+ ARM_INS_VRSHRN,

+ ARM_INS_VRSQRTE,

+ ARM_INS_VRSQRTS,

+ ARM_INS_VRSRA,

+ ARM_INS_VRSUBHN,

+ ARM_INS_VSDOT,

+ ARM_INS_VSELEQ,

+ ARM_INS_VSELGE,

+ ARM_INS_VSELGT,

+ ARM_INS_VSELVS,

+ ARM_INS_VSHL,

+ ARM_INS_VSHLL,

+ ARM_INS_VSHR,

+ ARM_INS_VSHRN,

+ ARM_INS_VSLI,

+ ARM_INS_VSQRT,

+ ARM_INS_VSRA,

+ ARM_INS_VSRI,

+ ARM_INS_VST1,

+ ARM_INS_VST2,

+ ARM_INS_VST3,

+ ARM_INS_VST4,

+ ARM_INS_VSTMDB,

+ ARM_INS_VSTMIA,

+ ARM_INS_VSTR,

+ ARM_INS_VSUB,

+ ARM_INS_VSUBHN,

+ ARM_INS_VSUBL,

+ ARM_INS_VSUBW,

+ ARM_INS_VSWP,

+ ARM_INS_VTBL,

+ ARM_INS_VTBX,

+ ARM_INS_VTRN,

+ ARM_INS_VTST,

+ ARM_INS_VUDOT,

+ ARM_INS_VUZP,

+ ARM_INS_VZIP,

+ ARM_INS_WFE,

+ ARM_INS_WFI,

+ ARM_INS_YIELD,

+

+ ARM_INS_ENDING, // <-- mark the end of the list of instructions

+} arm_insn;

+

+/// Group of ARM instructions

+typedef enum arm_insn_group {

+ ARM_GRP_INVALID = 0, ///< = CS_GRP_INVALID

+

+ // Generic groups

+ // all jump instructions (conditional+direct+indirect jumps)

+ ARM_GRP_JUMP, ///< = CS_GRP_JUMP

+ ARM_GRP_CALL, ///< = CS_GRP_CALL

+ ARM_GRP_INT = 4, ///< = CS_GRP_INT

+ ARM_GRP_PRIVILEGE = 6, ///< = CS_GRP_PRIVILEGE

+ ARM_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE

+

+ // Architecture-specific groups

+ ARM_GRP_CRYPTO = 128,

+ ARM_GRP_DATABARRIER,

+ ARM_GRP_DIVIDE,

+ ARM_GRP_FPARMV8,

+ ARM_GRP_MULTPRO,

+ ARM_GRP_NEON,

+ ARM_GRP_T2EXTRACTPACK,

+ ARM_GRP_THUMB2DSP,

+ ARM_GRP_TRUSTZONE,

+ ARM_GRP_V4T,

+ ARM_GRP_V5T,

+ ARM_GRP_V5TE,

+ ARM_GRP_V6,

+ ARM_GRP_V6T2,

+ ARM_GRP_V7,

+ ARM_GRP_V8,

+ ARM_GRP_VFP2,

+ ARM_GRP_VFP3,

+ ARM_GRP_VFP4,

+ ARM_GRP_ARM,

+ ARM_GRP_MCLASS,

+ ARM_GRP_NOTMCLASS,

+ ARM_GRP_THUMB,

+ ARM_GRP_THUMB1ONLY,

+ ARM_GRP_THUMB2,

+ ARM_GRP_PREV8,

+ ARM_GRP_FPVMLX,

+ ARM_GRP_MULOPS,

+ ARM_GRP_CRC,

+ ARM_GRP_DPVFP,

+ ARM_GRP_V6M,

+ ARM_GRP_VIRTUALIZATION,

+

+ ARM_GRP_ENDING,

+} arm_insn_group;

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

+#ifndef CAPSTONE_ARM64_H

+#define CAPSTONE_ARM64_H

+

+/* Capstone Disassembly Engine */

+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+#include "platform.h"

+

+#ifdef _MSC_VER

+#pragma warning(disable:4201)

+#endif

+

+/// ARM64 shift type

+typedef enum arm64_shifter {

+ ARM64_SFT_INVALID = 0,

+ ARM64_SFT_LSL = 1,

+ ARM64_SFT_MSL = 2,

+ ARM64_SFT_LSR = 3,

+ ARM64_SFT_ASR = 4,

+ ARM64_SFT_ROR = 5,

+} arm64_shifter;

+

+/// ARM64 extender type

+typedef enum arm64_extender {

+ ARM64_EXT_INVALID = 0,

+ ARM64_EXT_UXTB = 1,

+ ARM64_EXT_UXTH = 2,

+ ARM64_EXT_UXTW = 3,

+ ARM64_EXT_UXTX = 4,

+ ARM64_EXT_SXTB = 5,

+ ARM64_EXT_SXTH = 6,

+ ARM64_EXT_SXTW = 7,

+ ARM64_EXT_SXTX = 8,

+} arm64_extender;

+

+/// ARM64 condition code

+typedef enum arm64_cc {

+ ARM64_CC_INVALID = 0,

+ ARM64_CC_EQ = 1, ///< Equal

+ ARM64_CC_NE = 2, ///< Not equal: Not equal, or unordered

+ ARM64_CC_HS = 3, ///< Unsigned higher or same: >, ==, or unordered

+ ARM64_CC_LO = 4, ///< Unsigned lower or same: Less than

+ ARM64_CC_MI = 5, ///< Minus, negative: Less than

+ ARM64_CC_PL = 6, ///< Plus, positive or zero: >, ==, or unordered

+ ARM64_CC_VS = 7, ///< Overflow: Unordered

+ ARM64_CC_VC = 8, ///< No overflow: Ordered

+ ARM64_CC_HI = 9, ///< Unsigned higher: Greater than, or unordered

+ ARM64_CC_LS = 10, ///< Unsigned lower or same: Less than or equal

+ ARM64_CC_GE = 11, ///< Greater than or equal: Greater than or equal

+ ARM64_CC_LT = 12, ///< Less than: Less than, or unordered

+ ARM64_CC_GT = 13, ///< Signed greater than: Greater than

+ ARM64_CC_LE = 14, ///< Signed less than or equal: <, ==, or unordered

+ ARM64_CC_AL = 15, ///< Always (unconditional): Always (unconditional)

+ ARM64_CC_NV = 16, ///< Always (unconditional): Always (unconditional)

+ //< Note the NV exists purely to disassemble 0b1111. Execution is "always".

+} arm64_cc;

+

+/// System registers

+typedef enum arm64_sysreg {

+ // System registers for MRS

+ ARM64_SYSREG_INVALID = 0,

+

+ ARM64_SYSREG_MDCCSR_EL0 = 0x9808,

+ ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828,

+ ARM64_SYSREG_MDRAR_EL1 = 0x8080,

+ ARM64_SYSREG_OSLSR_EL1 = 0x808C,

+ ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83F6,

+ ARM64_SYSREG_PMCEID0_EL0 = 0xDCE6,

+ ARM64_SYSREG_PMCEID1_EL0 = 0xDCE7,

+ ARM64_SYSREG_MIDR_EL1 = 0xC000,

+ ARM64_SYSREG_CCSIDR_EL1 = 0xC800,

+ ARM64_SYSREG_CCSIDR2_EL1 = 0xC802,

+ ARM64_SYSREG_CLIDR_EL1 = 0xC801,

+ ARM64_SYSREG_CTR_EL0 = 0xD801,

+ ARM64_SYSREG_MPIDR_EL1 = 0xC005,

+ ARM64_SYSREG_REVIDR_EL1 = 0xC006,

+ ARM64_SYSREG_AIDR_EL1 = 0xC807,

+ ARM64_SYSREG_DCZID_EL0 = 0xD807,

+ ARM64_SYSREG_ID_PFR0_EL1 = 0xC008,

+ ARM64_SYSREG_ID_PFR1_EL1 = 0xC009,

+ ARM64_SYSREG_ID_DFR0_EL1 = 0xC00A,

+ ARM64_SYSREG_ID_AFR0_EL1 = 0xC00B,

+ ARM64_SYSREG_ID_MMFR0_EL1 = 0xC00C,

+ ARM64_SYSREG_ID_MMFR1_EL1 = 0xC00D,

+ ARM64_SYSREG_ID_MMFR2_EL1 = 0xC00E,

+ ARM64_SYSREG_ID_MMFR3_EL1 = 0xC00F,

+ ARM64_SYSREG_ID_ISAR0_EL1 = 0xC010,

+ ARM64_SYSREG_ID_ISAR1_EL1 = 0xC011,

+ ARM64_SYSREG_ID_ISAR2_EL1 = 0xC012,

+ ARM64_SYSREG_ID_ISAR3_EL1 = 0xC013,

+ ARM64_SYSREG_ID_ISAR4_EL1 = 0xC014,

+ ARM64_SYSREG_ID_ISAR5_EL1 = 0xC015,

+ ARM64_SYSREG_ID_ISAR6_EL1 = 0xC017,

+ ARM64_SYSREG_ID_AA64PFR0_EL1 = 0xC020,

+ ARM64_SYSREG_ID_AA64PFR1_EL1 = 0xC021,

+ ARM64_SYSREG_ID_AA64DFR0_EL1 = 0xC028,

+ ARM64_SYSREG_ID_AA64DFR1_EL1 = 0xC029,

+ ARM64_SYSREG_ID_AA64AFR0_EL1 = 0xC02C,

+ ARM64_SYSREG_ID_AA64AFR1_EL1 = 0xC02D,

+ ARM64_SYSREG_ID_AA64ISAR0_EL1 = 0xC030,

+ ARM64_SYSREG_ID_AA64ISAR1_EL1 = 0xC031,

+ ARM64_SYSREG_ID_AA64MMFR0_EL1 = 0xC038,

+ ARM64_SYSREG_ID_AA64MMFR1_EL1 = 0xC039,

+ ARM64_SYSREG_ID_AA64MMFR2_EL1 = 0xC03A,

+ ARM64_SYSREG_MVFR0_EL1 = 0xC018,

+ ARM64_SYSREG_MVFR1_EL1 = 0xC019,

+ ARM64_SYSREG_MVFR2_EL1 = 0xC01A,

+ ARM64_SYSREG_RVBAR_EL1 = 0xC601,

+ ARM64_SYSREG_RVBAR_EL2 = 0xE601,

+ ARM64_SYSREG_RVBAR_EL3 = 0xF601,

+ ARM64_SYSREG_ISR_EL1 = 0xC608,

+ ARM64_SYSREG_CNTPCT_EL0 = 0xDF01,

+ ARM64_SYSREG_CNTVCT_EL0 = 0xDF02,

+ ARM64_SYSREG_ID_MMFR4_EL1 = 0xC016,

+ ARM64_SYSREG_TRCSTATR = 0x8818,

+ ARM64_SYSREG_TRCIDR8 = 0x8806,

+ ARM64_SYSREG_TRCIDR9 = 0x880E,

+ ARM64_SYSREG_TRCIDR10 = 0x8816,

+ ARM64_SYSREG_TRCIDR11 = 0x881E,

+ ARM64_SYSREG_TRCIDR12 = 0x8826,

+ ARM64_SYSREG_TRCIDR13 = 0x882E,

+ ARM64_SYSREG_TRCIDR0 = 0x8847,

+ ARM64_SYSREG_TRCIDR1 = 0x884F,

+ ARM64_SYSREG_TRCIDR2 = 0x8857,

+ ARM64_SYSREG_TRCIDR3 = 0x885F,

+ ARM64_SYSREG_TRCIDR4 = 0x8867,

+ ARM64_SYSREG_TRCIDR5 = 0x886F,

+ ARM64_SYSREG_TRCIDR6 = 0x8877,

+ ARM64_SYSREG_TRCIDR7 = 0x887F,

+ ARM64_SYSREG_TRCOSLSR = 0x888C,

+ ARM64_SYSREG_TRCPDSR = 0x88AC,

+ ARM64_SYSREG_TRCDEVAFF0 = 0x8BD6,

+ ARM64_SYSREG_TRCDEVAFF1 = 0x8BDE,

+ ARM64_SYSREG_TRCLSR = 0x8BEE,

+ ARM64_SYSREG_TRCAUTHSTATUS = 0x8BF6,

+ ARM64_SYSREG_TRCDEVARCH = 0x8BFE,

+ ARM64_SYSREG_TRCDEVID = 0x8B97,

+ ARM64_SYSREG_TRCDEVTYPE = 0x8B9F,

+ ARM64_SYSREG_TRCPIDR4 = 0x8BA7,

+ ARM64_SYSREG_TRCPIDR5 = 0x8BAF,

+ ARM64_SYSREG_TRCPIDR6 = 0x8BB7,

+ ARM64_SYSREG_TRCPIDR7 = 0x8BBF,

+ ARM64_SYSREG_TRCPIDR0 = 0x8BC7,

+ ARM64_SYSREG_TRCPIDR1 = 0x8BCF,

+ ARM64_SYSREG_TRCPIDR2 = 0x8BD7,

+ ARM64_SYSREG_TRCPIDR3 = 0x8BDF,

+ ARM64_SYSREG_TRCCIDR0 = 0x8BE7,

+ ARM64_SYSREG_TRCCIDR1 = 0x8BEF,

+ ARM64_SYSREG_TRCCIDR2 = 0x8BF7,

+ ARM64_SYSREG_TRCCIDR3 = 0x8BFF,

+ ARM64_SYSREG_ICC_IAR1_EL1 = 0xC660,

+ ARM64_SYSREG_ICC_IAR0_EL1 = 0xC640,

+ ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xC662,

+ ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xC642,

+ ARM64_SYSREG_ICC_RPR_EL1 = 0xC65B,

+ ARM64_SYSREG_ICH_VTR_EL2 = 0xE659,

+ ARM64_SYSREG_ICH_EISR_EL2 = 0xE65B,

+ ARM64_SYSREG_ICH_ELRSR_EL2 = 0xE65D,

+ ARM64_SYSREG_ID_AA64ZFR0_EL1 = 0xC024,

+ ARM64_SYSREG_LORID_EL1 = 0xC527,

+ ARM64_SYSREG_ERRIDR_EL1 = 0xC298,

+ ARM64_SYSREG_ERXFR_EL1 = 0xC2A0,

+ ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828,

+ ARM64_SYSREG_OSLAR_EL1 = 0x8084,

+ ARM64_SYSREG_PMSWINC_EL0 = 0xDCE4,

+ ARM64_SYSREG_TRCOSLAR = 0x8884,

+ ARM64_SYSREG_TRCLAR = 0x8BE6,

+ ARM64_SYSREG_ICC_EOIR1_EL1 = 0xC661,

+ ARM64_SYSREG_ICC_EOIR0_EL1 = 0xC641,

+ ARM64_SYSREG_ICC_DIR_EL1 = 0xC659,

+ ARM64_SYSREG_ICC_SGI1R_EL1 = 0xC65D,

+ ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xC65E,

+ ARM64_SYSREG_ICC_SGI0R_EL1 = 0xC65F,

+ ARM64_SYSREG_OSDTRRX_EL1 = 0x8002,

+ ARM64_SYSREG_OSDTRTX_EL1 = 0x801A,

+ ARM64_SYSREG_TEECR32_EL1 = 0x9000,

+ ARM64_SYSREG_MDCCINT_EL1 = 0x8010,

+ ARM64_SYSREG_MDSCR_EL1 = 0x8012,

+ ARM64_SYSREG_DBGDTR_EL0 = 0x9820,

+ ARM64_SYSREG_OSECCR_EL1 = 0x8032,

+ ARM64_SYSREG_DBGVCR32_EL2 = 0xA038,

+ ARM64_SYSREG_DBGBVR0_EL1 = 0x8004,

+ ARM64_SYSREG_DBGBVR1_EL1 = 0x800C,

+ ARM64_SYSREG_DBGBVR2_EL1 = 0x8014,

+ ARM64_SYSREG_DBGBVR3_EL1 = 0x801C,

+ ARM64_SYSREG_DBGBVR4_EL1 = 0x8024,

+ ARM64_SYSREG_DBGBVR5_EL1 = 0x802C,

+ ARM64_SYSREG_DBGBVR6_EL1 = 0x8034,

+ ARM64_SYSREG_DBGBVR7_EL1 = 0x803C,

+ ARM64_SYSREG_DBGBVR8_EL1 = 0x8044,

+ ARM64_SYSREG_DBGBVR9_EL1 = 0x804C,

+ ARM64_SYSREG_DBGBVR10_EL1 = 0x8054,

+ ARM64_SYSREG_DBGBVR11_EL1 = 0x805C,

+ ARM64_SYSREG_DBGBVR12_EL1 = 0x8064,

+ ARM64_SYSREG_DBGBVR13_EL1 = 0x806C,

+ ARM64_SYSREG_DBGBVR14_EL1 = 0x8074,

+ ARM64_SYSREG_DBGBVR15_EL1 = 0x807C,

+ ARM64_SYSREG_DBGBCR0_EL1 = 0x8005,

+ ARM64_SYSREG_DBGBCR1_EL1 = 0x800D,

+ ARM64_SYSREG_DBGBCR2_EL1 = 0x8015,

+ ARM64_SYSREG_DBGBCR3_EL1 = 0x801D,

+ ARM64_SYSREG_DBGBCR4_EL1 = 0x8025,

+ ARM64_SYSREG_DBGBCR5_EL1 = 0x802D,

+ ARM64_SYSREG_DBGBCR6_EL1 = 0x8035,

+ ARM64_SYSREG_DBGBCR7_EL1 = 0x803D,

+ ARM64_SYSREG_DBGBCR8_EL1 = 0x8045,

+ ARM64_SYSREG_DBGBCR9_EL1 = 0x804D,

+ ARM64_SYSREG_DBGBCR10_EL1 = 0x8055,

+ ARM64_SYSREG_DBGBCR11_EL1 = 0x805D,

+ ARM64_SYSREG_DBGBCR12_EL1 = 0x8065,

+ ARM64_SYSREG_DBGBCR13_EL1 = 0x806D,

+ ARM64_SYSREG_DBGBCR14_EL1 = 0x8075,

+ ARM64_SYSREG_DBGBCR15_EL1 = 0x807D,

+ ARM64_SYSREG_DBGWVR0_EL1 = 0x8006,

+ ARM64_SYSREG_DBGWVR1_EL1 = 0x800E,

+ ARM64_SYSREG_DBGWVR2_EL1 = 0x8016,

+ ARM64_SYSREG_DBGWVR3_EL1 = 0x801E,

+ ARM64_SYSREG_DBGWVR4_EL1 = 0x8026,

+ ARM64_SYSREG_DBGWVR5_EL1 = 0x802E,

+ ARM64_SYSREG_DBGWVR6_EL1 = 0x8036,

+ ARM64_SYSREG_DBGWVR7_EL1 = 0x803E,

+ ARM64_SYSREG_DBGWVR8_EL1 = 0x8046,

+ ARM64_SYSREG_DBGWVR9_EL1 = 0x804E,

+ ARM64_SYSREG_DBGWVR10_EL1 = 0x8056,

+ ARM64_SYSREG_DBGWVR11_EL1 = 0x805E,

+ ARM64_SYSREG_DBGWVR12_EL1 = 0x8066,

+ ARM64_SYSREG_DBGWVR13_EL1 = 0x806E,

+ ARM64_SYSREG_DBGWVR14_EL1 = 0x8076,

+ ARM64_SYSREG_DBGWVR15_EL1 = 0x807E,

+ ARM64_SYSREG_DBGWCR0_EL1 = 0x8007,

+ ARM64_SYSREG_DBGWCR1_EL1 = 0x800F,

+ ARM64_SYSREG_DBGWCR2_EL1 = 0x8017,

+ ARM64_SYSREG_DBGWCR3_EL1 = 0x801F,

+ ARM64_SYSREG_DBGWCR4_EL1 = 0x8027,

+ ARM64_SYSREG_DBGWCR5_EL1 = 0x802F,

+ ARM64_SYSREG_DBGWCR6_EL1 = 0x8037,

+ ARM64_SYSREG_DBGWCR7_EL1 = 0x803F,

+ ARM64_SYSREG_DBGWCR8_EL1 = 0x8047,

+ ARM64_SYSREG_DBGWCR9_EL1 = 0x804F,

+ ARM64_SYSREG_DBGWCR10_EL1 = 0x8057,

+ ARM64_SYSREG_DBGWCR11_EL1 = 0x805F,

+ ARM64_SYSREG_DBGWCR12_EL1 = 0x8067,

+ ARM64_SYSREG_DBGWCR13_EL1 = 0x806F,

+ ARM64_SYSREG_DBGWCR14_EL1 = 0x8077,

+ ARM64_SYSREG_DBGWCR15_EL1 = 0x807F,

+ ARM64_SYSREG_TEEHBR32_EL1 = 0x9080,

+ ARM64_SYSREG_OSDLR_EL1 = 0x809C,

+ ARM64_SYSREG_DBGPRCR_EL1 = 0x80A4,

+ ARM64_SYSREG_DBGCLAIMSET_EL1 = 0x83C6,

+ ARM64_SYSREG_DBGCLAIMCLR_EL1 = 0x83CE,

+ ARM64_SYSREG_CSSELR_EL1 = 0xD000,

+ ARM64_SYSREG_VPIDR_EL2 = 0xE000,

+ ARM64_SYSREG_VMPIDR_EL2 = 0xE005,

+ ARM64_SYSREG_CPACR_EL1 = 0xC082,

+ ARM64_SYSREG_SCTLR_EL1 = 0xC080,

+ ARM64_SYSREG_SCTLR_EL2 = 0xE080,

+ ARM64_SYSREG_SCTLR_EL3 = 0xF080,

+ ARM64_SYSREG_ACTLR_EL1 = 0xC081,

+ ARM64_SYSREG_ACTLR_EL2 = 0xE081,

+ ARM64_SYSREG_ACTLR_EL3 = 0xF081,

+ ARM64_SYSREG_HCR_EL2 = 0xE088,

+ ARM64_SYSREG_SCR_EL3 = 0xF088,

+ ARM64_SYSREG_MDCR_EL2 = 0xE089,

+ ARM64_SYSREG_SDER32_EL3 = 0xF089,

+ ARM64_SYSREG_CPTR_EL2 = 0xE08A,

+ ARM64_SYSREG_CPTR_EL3 = 0xF08A,

+ ARM64_SYSREG_HSTR_EL2 = 0xE08B,

+ ARM64_SYSREG_HACR_EL2 = 0xE08F,

+ ARM64_SYSREG_MDCR_EL3 = 0xF099,

+ ARM64_SYSREG_TTBR0_EL1 = 0xC100,

+ ARM64_SYSREG_TTBR0_EL2 = 0xE100,

+ ARM64_SYSREG_TTBR0_EL3 = 0xF100,

+ ARM64_SYSREG_TTBR1_EL1 = 0xC101,

+ ARM64_SYSREG_TCR_EL1 = 0xC102,

+ ARM64_SYSREG_TCR_EL2 = 0xE102,

+ ARM64_SYSREG_TCR_EL3 = 0xF102,

+ ARM64_SYSREG_VTTBR_EL2 = 0xE108,

+ ARM64_SYSREG_VTCR_EL2 = 0xE10A,

+ ARM64_SYSREG_DACR32_EL2 = 0xE180,

+ ARM64_SYSREG_SPSR_EL1 = 0xC200,

+ ARM64_SYSREG_SPSR_EL2 = 0xE200,

+ ARM64_SYSREG_SPSR_EL3 = 0xF200,

+ ARM64_SYSREG_ELR_EL1 = 0xC201,

+ ARM64_SYSREG_ELR_EL2 = 0xE201,

+ ARM64_SYSREG_ELR_EL3 = 0xF201,

+ ARM64_SYSREG_SP_EL0 = 0xC208,

+ ARM64_SYSREG_SP_EL1 = 0xE208,

+ ARM64_SYSREG_SP_EL2 = 0xF208,

+ ARM64_SYSREG_SPSEL = 0xC210,

+ ARM64_SYSREG_NZCV = 0xDA10,

+ ARM64_SYSREG_DAIF = 0xDA11,

+ ARM64_SYSREG_CURRENTEL = 0xC212,

+ ARM64_SYSREG_SPSR_IRQ = 0xE218,

+ ARM64_SYSREG_SPSR_ABT = 0xE219,

+ ARM64_SYSREG_SPSR_UND = 0xE21A,

+ ARM64_SYSREG_SPSR_FIQ = 0xE21B,

+ ARM64_SYSREG_FPCR = 0xDA20,

+ ARM64_SYSREG_FPSR = 0xDA21,

+ ARM64_SYSREG_DSPSR_EL0 = 0xDA28,

+ ARM64_SYSREG_DLR_EL0 = 0xDA29,

+ ARM64_SYSREG_IFSR32_EL2 = 0xE281,

+ ARM64_SYSREG_AFSR0_EL1 = 0xC288,

+ ARM64_SYSREG_AFSR0_EL2 = 0xE288,

+ ARM64_SYSREG_AFSR0_EL3 = 0xF288,

+ ARM64_SYSREG_AFSR1_EL1 = 0xC289,

+ ARM64_SYSREG_AFSR1_EL2 = 0xE289,

+ ARM64_SYSREG_AFSR1_EL3 = 0xF289,

+ ARM64_SYSREG_ESR_EL1 = 0xC290,

+ ARM64_SYSREG_ESR_EL2 = 0xE290,

+ ARM64_SYSREG_ESR_EL3 = 0xF290,

+ ARM64_SYSREG_FPEXC32_EL2 = 0xE298,

+ ARM64_SYSREG_FAR_EL1 = 0xC300,

+ ARM64_SYSREG_FAR_EL2 = 0xE300,

+ ARM64_SYSREG_FAR_EL3 = 0xF300,

+ ARM64_SYSREG_HPFAR_EL2 = 0xE304,

+ ARM64_SYSREG_PAR_EL1 = 0xC3A0,

+ ARM64_SYSREG_PMCR_EL0 = 0xDCE0,

+ ARM64_SYSREG_PMCNTENSET_EL0 = 0xDCE1,

+ ARM64_SYSREG_PMCNTENCLR_EL0 = 0xDCE2,

+ ARM64_SYSREG_PMOVSCLR_EL0 = 0xDCE3,

+ ARM64_SYSREG_PMSELR_EL0 = 0xDCE5,

+ ARM64_SYSREG_PMCCNTR_EL0 = 0xDCE8,

+ ARM64_SYSREG_PMXEVTYPER_EL0 = 0xDCE9,

+ ARM64_SYSREG_PMXEVCNTR_EL0 = 0xDCEA,

+ ARM64_SYSREG_PMUSERENR_EL0 = 0xDCF0,

+ ARM64_SYSREG_PMINTENSET_EL1 = 0xC4F1,

+ ARM64_SYSREG_PMINTENCLR_EL1 = 0xC4F2,

+ ARM64_SYSREG_PMOVSSET_EL0 = 0xDCF3,

+ ARM64_SYSREG_MAIR_EL1 = 0xC510,

+ ARM64_SYSREG_MAIR_EL2 = 0xE510,

+ ARM64_SYSREG_MAIR_EL3 = 0xF510,

+ ARM64_SYSREG_AMAIR_EL1 = 0xC518,

+ ARM64_SYSREG_AMAIR_EL2 = 0xE518,

+ ARM64_SYSREG_AMAIR_EL3 = 0xF518,

+ ARM64_SYSREG_VBAR_EL1 = 0xC600,

+ ARM64_SYSREG_VBAR_EL2 = 0xE600,

+ ARM64_SYSREG_VBAR_EL3 = 0xF600,

+ ARM64_SYSREG_RMR_EL1 = 0xC602,

+ ARM64_SYSREG_RMR_EL2 = 0xE602,

+ ARM64_SYSREG_RMR_EL3 = 0xF602,

+ ARM64_SYSREG_CONTEXTIDR_EL1 = 0xC681,

+ ARM64_SYSREG_TPIDR_EL0 = 0xDE82,

+ ARM64_SYSREG_TPIDR_EL2 = 0xE682,

+ ARM64_SYSREG_TPIDR_EL3 = 0xF682,

+ ARM64_SYSREG_TPIDRRO_EL0 = 0xDE83,

+ ARM64_SYSREG_TPIDR_EL1 = 0xC684,

+ ARM64_SYSREG_CNTFRQ_EL0 = 0xDF00,

+ ARM64_SYSREG_CNTVOFF_EL2 = 0xE703,

+ ARM64_SYSREG_CNTKCTL_EL1 = 0xC708,

+ ARM64_SYSREG_CNTHCTL_EL2 = 0xE708,

+ ARM64_SYSREG_CNTP_TVAL_EL0 = 0xDF10,

+ ARM64_SYSREG_CNTHP_TVAL_EL2 = 0xE710,

+ ARM64_SYSREG_CNTPS_TVAL_EL1 = 0xFF10,

+ ARM64_SYSREG_CNTP_CTL_EL0 = 0xDF11,

+ ARM64_SYSREG_CNTHP_CTL_EL2 = 0xE711,

+ ARM64_SYSREG_CNTPS_CTL_EL1 = 0xFF11,

+ ARM64_SYSREG_CNTP_CVAL_EL0 = 0xDF12,

+ ARM64_SYSREG_CNTHP_CVAL_EL2 = 0xE712,

+ ARM64_SYSREG_CNTPS_CVAL_EL1 = 0xFF12,

+ ARM64_SYSREG_CNTV_TVAL_EL0 = 0xDF18,

+ ARM64_SYSREG_CNTV_CTL_EL0 = 0xDF19,

+ ARM64_SYSREG_CNTV_CVAL_EL0 = 0xDF1A,

+ ARM64_SYSREG_PMEVCNTR0_EL0 = 0xDF40,

+ ARM64_SYSREG_PMEVCNTR1_EL0 = 0xDF41,

+ ARM64_SYSREG_PMEVCNTR2_EL0 = 0xDF42,

+ ARM64_SYSREG_PMEVCNTR3_EL0 = 0xDF43,

+ ARM64_SYSREG_PMEVCNTR4_EL0 = 0xDF44,

+ ARM64_SYSREG_PMEVCNTR5_EL0 = 0xDF45,

+ ARM64_SYSREG_PMEVCNTR6_EL0 = 0xDF46,

+ ARM64_SYSREG_PMEVCNTR7_EL0 = 0xDF47,

+ ARM64_SYSREG_PMEVCNTR8_EL0 = 0xDF48,

+ ARM64_SYSREG_PMEVCNTR9_EL0 = 0xDF49,

+ ARM64_SYSREG_PMEVCNTR10_EL0 = 0xDF4A,

+ ARM64_SYSREG_PMEVCNTR11_EL0 = 0xDF4B,

+ ARM64_SYSREG_PMEVCNTR12_EL0 = 0xDF4C,

+ ARM64_SYSREG_PMEVCNTR13_EL0 = 0xDF4D,

+ ARM64_SYSREG_PMEVCNTR14_EL0 = 0xDF4E,

+ ARM64_SYSREG_PMEVCNTR15_EL0 = 0xDF4F,

+ ARM64_SYSREG_PMEVCNTR16_EL0 = 0xDF50,

+ ARM64_SYSREG_PMEVCNTR17_EL0 = 0xDF51,

+ ARM64_SYSREG_PMEVCNTR18_EL0 = 0xDF52,

+ ARM64_SYSREG_PMEVCNTR19_EL0 = 0xDF53,

+ ARM64_SYSREG_PMEVCNTR20_EL0 = 0xDF54,

+ ARM64_SYSREG_PMEVCNTR21_EL0 = 0xDF55,

+ ARM64_SYSREG_PMEVCNTR22_EL0 = 0xDF56,

+ ARM64_SYSREG_PMEVCNTR23_EL0 = 0xDF57,

+ ARM64_SYSREG_PMEVCNTR24_EL0 = 0xDF58,

+ ARM64_SYSREG_PMEVCNTR25_EL0 = 0xDF59,

+ ARM64_SYSREG_PMEVCNTR26_EL0 = 0xDF5A,

+ ARM64_SYSREG_PMEVCNTR27_EL0 = 0xDF5B,

+ ARM64_SYSREG_PMEVCNTR28_EL0 = 0xDF5C,

+ ARM64_SYSREG_PMEVCNTR29_EL0 = 0xDF5D,

+ ARM64_SYSREG_PMEVCNTR30_EL0 = 0xDF5E,

+ ARM64_SYSREG_PMCCFILTR_EL0 = 0xDF7F,

+ ARM64_SYSREG_PMEVTYPER0_EL0 = 0xDF60,

+ ARM64_SYSREG_PMEVTYPER1_EL0 = 0xDF61,

+ ARM64_SYSREG_PMEVTYPER2_EL0 = 0xDF62,

+ ARM64_SYSREG_PMEVTYPER3_EL0 = 0xDF63,

+ ARM64_SYSREG_PMEVTYPER4_EL0 = 0xDF64,

+ ARM64_SYSREG_PMEVTYPER5_EL0 = 0xDF65,

+ ARM64_SYSREG_PMEVTYPER6_EL0 = 0xDF66,

+ ARM64_SYSREG_PMEVTYPER7_EL0 = 0xDF67,

+ ARM64_SYSREG_PMEVTYPER8_EL0 = 0xDF68,

+ ARM64_SYSREG_PMEVTYPER9_EL0 = 0xDF69,

+ ARM64_SYSREG_PMEVTYPER10_EL0 = 0xDF6A,

+ ARM64_SYSREG_PMEVTYPER11_EL0 = 0xDF6B,

+ ARM64_SYSREG_PMEVTYPER12_EL0 = 0xDF6C,

+ ARM64_SYSREG_PMEVTYPER13_EL0 = 0xDF6D,

+ ARM64_SYSREG_PMEVTYPER14_EL0 = 0xDF6E,

+ ARM64_SYSREG_PMEVTYPER15_EL0 = 0xDF6F,

+ ARM64_SYSREG_PMEVTYPER16_EL0 = 0xDF70,

+ ARM64_SYSREG_PMEVTYPER17_EL0 = 0xDF71,

+ ARM64_SYSREG_PMEVTYPER18_EL0 = 0xDF72,

+ ARM64_SYSREG_PMEVTYPER19_EL0 = 0xDF73,

+ ARM64_SYSREG_PMEVTYPER20_EL0 = 0xDF74,

+ ARM64_SYSREG_PMEVTYPER21_EL0 = 0xDF75,

+ ARM64_SYSREG_PMEVTYPER22_EL0 = 0xDF76,

+ ARM64_SYSREG_PMEVTYPER23_EL0 = 0xDF77,

+ ARM64_SYSREG_PMEVTYPER24_EL0 = 0xDF78,

+ ARM64_SYSREG_PMEVTYPER25_EL0 = 0xDF79,

+ ARM64_SYSREG_PMEVTYPER26_EL0 = 0xDF7A,

+ ARM64_SYSREG_PMEVTYPER27_EL0 = 0xDF7B,

+ ARM64_SYSREG_PMEVTYPER28_EL0 = 0xDF7C,

+ ARM64_SYSREG_PMEVTYPER29_EL0 = 0xDF7D,

+ ARM64_SYSREG_PMEVTYPER30_EL0 = 0xDF7E,

+ ARM64_SYSREG_TRCPRGCTLR = 0x8808,

+ ARM64_SYSREG_TRCPROCSELR = 0x8810,

+ ARM64_SYSREG_TRCCONFIGR = 0x8820,

+ ARM64_SYSREG_TRCAUXCTLR = 0x8830,

+ ARM64_SYSREG_TRCEVENTCTL0R = 0x8840,

+ ARM64_SYSREG_TRCEVENTCTL1R = 0x8848,

+ ARM64_SYSREG_TRCSTALLCTLR = 0x8858,

+ ARM64_SYSREG_TRCTSCTLR = 0x8860,

+ ARM64_SYSREG_TRCSYNCPR = 0x8868,

+ ARM64_SYSREG_TRCCCCTLR = 0x8870,

+ ARM64_SYSREG_TRCBBCTLR = 0x8878,

+ ARM64_SYSREG_TRCTRACEIDR = 0x8801,

+ ARM64_SYSREG_TRCQCTLR = 0x8809,

+ ARM64_SYSREG_TRCVICTLR = 0x8802,

+ ARM64_SYSREG_TRCVIIECTLR = 0x880A,

+ ARM64_SYSREG_TRCVISSCTLR = 0x8812,

+ ARM64_SYSREG_TRCVIPCSSCTLR = 0x881A,

+ ARM64_SYSREG_TRCVDCTLR = 0x8842,

+ ARM64_SYSREG_TRCVDSACCTLR = 0x884A,

+ ARM64_SYSREG_TRCVDARCCTLR = 0x8852,

+ ARM64_SYSREG_TRCSEQEVR0 = 0x8804,

+ ARM64_SYSREG_TRCSEQEVR1 = 0x880C,

+ ARM64_SYSREG_TRCSEQEVR2 = 0x8814,

+ ARM64_SYSREG_TRCSEQRSTEVR = 0x8834,

+ ARM64_SYSREG_TRCSEQSTR = 0x883C,

+ ARM64_SYSREG_TRCEXTINSELR = 0x8844,

+ ARM64_SYSREG_TRCCNTRLDVR0 = 0x8805,

+ ARM64_SYSREG_TRCCNTRLDVR1 = 0x880D,

+ ARM64_SYSREG_TRCCNTRLDVR2 = 0x8815,

+ ARM64_SYSREG_TRCCNTRLDVR3 = 0x881D,

+ ARM64_SYSREG_TRCCNTCTLR0 = 0x8825,

+ ARM64_SYSREG_TRCCNTCTLR1 = 0x882D,

+ ARM64_SYSREG_TRCCNTCTLR2 = 0x8835,

+ ARM64_SYSREG_TRCCNTCTLR3 = 0x883D,

+ ARM64_SYSREG_TRCCNTVR0 = 0x8845,

+ ARM64_SYSREG_TRCCNTVR1 = 0x884D,

+ ARM64_SYSREG_TRCCNTVR2 = 0x8855,

+ ARM64_SYSREG_TRCCNTVR3 = 0x885D,

+ ARM64_SYSREG_TRCIMSPEC0 = 0x8807,

+ ARM64_SYSREG_TRCIMSPEC1 = 0x880F,

+ ARM64_SYSREG_TRCIMSPEC2 = 0x8817,

+ ARM64_SYSREG_TRCIMSPEC3 = 0x881F,

+ ARM64_SYSREG_TRCIMSPEC4 = 0x8827,

+ ARM64_SYSREG_TRCIMSPEC5 = 0x882F,

+ ARM64_SYSREG_TRCIMSPEC6 = 0x8837,

+ ARM64_SYSREG_TRCIMSPEC7 = 0x883F,

+ ARM64_SYSREG_TRCRSCTLR2 = 0x8890,

+ ARM64_SYSREG_TRCRSCTLR3 = 0x8898,

+ ARM64_SYSREG_TRCRSCTLR4 = 0x88A0,

+ ARM64_SYSREG_TRCRSCTLR5 = 0x88A8,

+ ARM64_SYSREG_TRCRSCTLR6 = 0x88B0,

+ ARM64_SYSREG_TRCRSCTLR7 = 0x88B8,

+ ARM64_SYSREG_TRCRSCTLR8 = 0x88C0,

+ ARM64_SYSREG_TRCRSCTLR9 = 0x88C8,

+ ARM64_SYSREG_TRCRSCTLR10 = 0x88D0,

+ ARM64_SYSREG_TRCRSCTLR11 = 0x88D8,

+ ARM64_SYSREG_TRCRSCTLR12 = 0x88E0,

+ ARM64_SYSREG_TRCRSCTLR13 = 0x88E8,

+ ARM64_SYSREG_TRCRSCTLR14 = 0x88F0,

+ ARM64_SYSREG_TRCRSCTLR15 = 0x88F8,

+ ARM64_SYSREG_TRCRSCTLR16 = 0x8881,

+ ARM64_SYSREG_TRCRSCTLR17 = 0x8889,

+ ARM64_SYSREG_TRCRSCTLR18 = 0x8891,

+ ARM64_SYSREG_TRCRSCTLR19 = 0x8899,

+ ARM64_SYSREG_TRCRSCTLR20 = 0x88A1,

+ ARM64_SYSREG_TRCRSCTLR21 = 0x88A9,

+ ARM64_SYSREG_TRCRSCTLR22 = 0x88B1,

+ ARM64_SYSREG_TRCRSCTLR23 = 0x88B9,

+ ARM64_SYSREG_TRCRSCTLR24 = 0x88C1,

+ ARM64_SYSREG_TRCRSCTLR25 = 0x88C9,

+ ARM64_SYSREG_TRCRSCTLR26 = 0x88D1,

+ ARM64_SYSREG_TRCRSCTLR27 = 0x88D9,

+ ARM64_SYSREG_TRCRSCTLR28 = 0x88E1,

+ ARM64_SYSREG_TRCRSCTLR29 = 0x88E9,

+ ARM64_SYSREG_TRCRSCTLR30 = 0x88F1,

+ ARM64_SYSREG_TRCRSCTLR31 = 0x88F9,

+ ARM64_SYSREG_TRCSSCCR0 = 0x8882,

+ ARM64_SYSREG_TRCSSCCR1 = 0x888A,

+ ARM64_SYSREG_TRCSSCCR2 = 0x8892,

+ ARM64_SYSREG_TRCSSCCR3 = 0x889A,

+ ARM64_SYSREG_TRCSSCCR4 = 0x88A2,

+ ARM64_SYSREG_TRCSSCCR5 = 0x88AA,

+ ARM64_SYSREG_TRCSSCCR6 = 0x88B2,

+ ARM64_SYSREG_TRCSSCCR7 = 0x88BA,

+ ARM64_SYSREG_TRCSSCSR0 = 0x88C2,

+ ARM64_SYSREG_TRCSSCSR1 = 0x88CA,

+ ARM64_SYSREG_TRCSSCSR2 = 0x88D2,

+ ARM64_SYSREG_TRCSSCSR3 = 0x88DA,

+ ARM64_SYSREG_TRCSSCSR4 = 0x88E2,

+ ARM64_SYSREG_TRCSSCSR5 = 0x88EA,

+ ARM64_SYSREG_TRCSSCSR6 = 0x88F2,

+ ARM64_SYSREG_TRCSSCSR7 = 0x88FA,

+ ARM64_SYSREG_TRCSSPCICR0 = 0x8883,

+ ARM64_SYSREG_TRCSSPCICR1 = 0x888B,

+ ARM64_SYSREG_TRCSSPCICR2 = 0x8893,

+ ARM64_SYSREG_TRCSSPCICR3 = 0x889B,

+ ARM64_SYSREG_TRCSSPCICR4 = 0x88A3,

+ ARM64_SYSREG_TRCSSPCICR5 = 0x88AB,

+ ARM64_SYSREG_TRCSSPCICR6 = 0x88B3,

+ ARM64_SYSREG_TRCSSPCICR7 = 0x88BB,

+ ARM64_SYSREG_TRCPDCR = 0x88A4,

+ ARM64_SYSREG_TRCACVR0 = 0x8900,

+ ARM64_SYSREG_TRCACVR1 = 0x8910,

+ ARM64_SYSREG_TRCACVR2 = 0x8920,

+ ARM64_SYSREG_TRCACVR3 = 0x8930,

+ ARM64_SYSREG_TRCACVR4 = 0x8940,

+ ARM64_SYSREG_TRCACVR5 = 0x8950,

+ ARM64_SYSREG_TRCACVR6 = 0x8960,

+ ARM64_SYSREG_TRCACVR7 = 0x8970,

+ ARM64_SYSREG_TRCACVR8 = 0x8901,

+ ARM64_SYSREG_TRCACVR9 = 0x8911,

+ ARM64_SYSREG_TRCACVR10 = 0x8921,

+ ARM64_SYSREG_TRCACVR11 = 0x8931,

+ ARM64_SYSREG_TRCACVR12 = 0x8941,

+ ARM64_SYSREG_TRCACVR13 = 0x8951,

+ ARM64_SYSREG_TRCACVR14 = 0x8961,

+ ARM64_SYSREG_TRCACVR15 = 0x8971,

+ ARM64_SYSREG_TRCACATR0 = 0x8902,

+ ARM64_SYSREG_TRCACATR1 = 0x8912,

+ ARM64_SYSREG_TRCACATR2 = 0x8922,

+ ARM64_SYSREG_TRCACATR3 = 0x8932,

+ ARM64_SYSREG_TRCACATR4 = 0x8942,

+ ARM64_SYSREG_TRCACATR5 = 0x8952,

+ ARM64_SYSREG_TRCACATR6 = 0x8962,

+ ARM64_SYSREG_TRCACATR7 = 0x8972,

+ ARM64_SYSREG_TRCACATR8 = 0x8903,

+ ARM64_SYSREG_TRCACATR9 = 0x8913,

+ ARM64_SYSREG_TRCACATR10 = 0x8923,

+ ARM64_SYSREG_TRCACATR11 = 0x8933,

+ ARM64_SYSREG_TRCACATR12 = 0x8943,

+ ARM64_SYSREG_TRCACATR13 = 0x8953,

+ ARM64_SYSREG_TRCACATR14 = 0x8963,

+ ARM64_SYSREG_TRCACATR15 = 0x8973,

+ ARM64_SYSREG_TRCDVCVR0 = 0x8904,

+ ARM64_SYSREG_TRCDVCVR1 = 0x8924,

+ ARM64_SYSREG_TRCDVCVR2 = 0x8944,

+ ARM64_SYSREG_TRCDVCVR3 = 0x8964,

+ ARM64_SYSREG_TRCDVCVR4 = 0x8905,

+ ARM64_SYSREG_TRCDVCVR5 = 0x8925,

+ ARM64_SYSREG_TRCDVCVR6 = 0x8945,

+ ARM64_SYSREG_TRCDVCVR7 = 0x8965,

+ ARM64_SYSREG_TRCDVCMR0 = 0x8906,

+ ARM64_SYSREG_TRCDVCMR1 = 0x8926,

+ ARM64_SYSREG_TRCDVCMR2 = 0x8946,

+ ARM64_SYSREG_TRCDVCMR3 = 0x8966,

+ ARM64_SYSREG_TRCDVCMR4 = 0x8907,

+ ARM64_SYSREG_TRCDVCMR5 = 0x8927,

+ ARM64_SYSREG_TRCDVCMR6 = 0x8947,

+ ARM64_SYSREG_TRCDVCMR7 = 0x8967,

+ ARM64_SYSREG_TRCCIDCVR0 = 0x8980,

+ ARM64_SYSREG_TRCCIDCVR1 = 0x8990,

+ ARM64_SYSREG_TRCCIDCVR2 = 0x89A0,

+ ARM64_SYSREG_TRCCIDCVR3 = 0x89B0,

+ ARM64_SYSREG_TRCCIDCVR4 = 0x89C0,

+ ARM64_SYSREG_TRCCIDCVR5 = 0x89D0,

+ ARM64_SYSREG_TRCCIDCVR6 = 0x89E0,

+ ARM64_SYSREG_TRCCIDCVR7 = 0x89F0,

+ ARM64_SYSREG_TRCVMIDCVR0 = 0x8981,

+ ARM64_SYSREG_TRCVMIDCVR1 = 0x8991,

+ ARM64_SYSREG_TRCVMIDCVR2 = 0x89A1,

+ ARM64_SYSREG_TRCVMIDCVR3 = 0x89B1,

+ ARM64_SYSREG_TRCVMIDCVR4 = 0x89C1,

+ ARM64_SYSREG_TRCVMIDCVR5 = 0x89D1,

+ ARM64_SYSREG_TRCVMIDCVR6 = 0x89E1,

+ ARM64_SYSREG_TRCVMIDCVR7 = 0x89F1,

+ ARM64_SYSREG_TRCCIDCCTLR0 = 0x8982,

+ ARM64_SYSREG_TRCCIDCCTLR1 = 0x898A,

+ ARM64_SYSREG_TRCVMIDCCTLR0 = 0x8992,

+ ARM64_SYSREG_TRCVMIDCCTLR1 = 0x899A,

+ ARM64_SYSREG_TRCITCTRL = 0x8B84,

+ ARM64_SYSREG_TRCCLAIMSET = 0x8BC6,

+ ARM64_SYSREG_TRCCLAIMCLR = 0x8BCE,

+ ARM64_SYSREG_ICC_BPR1_EL1 = 0xC663,

+ ARM64_SYSREG_ICC_BPR0_EL1 = 0xC643,

+ ARM64_SYSREG_ICC_PMR_EL1 = 0xC230,

+ ARM64_SYSREG_ICC_CTLR_EL1 = 0xC664,

+ ARM64_SYSREG_ICC_CTLR_EL3 = 0xF664,

+ ARM64_SYSREG_ICC_SRE_EL1 = 0xC665,

+ ARM64_SYSREG_ICC_SRE_EL2 = 0xE64D,

+ ARM64_SYSREG_ICC_SRE_EL3 = 0xF665,

+ ARM64_SYSREG_ICC_IGRPEN0_EL1 = 0xC666,

+ ARM64_SYSREG_ICC_IGRPEN1_EL1 = 0xC667,

+ ARM64_SYSREG_ICC_IGRPEN1_EL3 = 0xF667,

+ ARM64_SYSREG_ICC_SEIEN_EL1 = 0xC668,

+ ARM64_SYSREG_ICC_AP0R0_EL1 = 0xC644,

+ ARM64_SYSREG_ICC_AP0R1_EL1 = 0xC645,

+ ARM64_SYSREG_ICC_AP0R2_EL1 = 0xC646,

+ ARM64_SYSREG_ICC_AP0R3_EL1 = 0xC647,

+ ARM64_SYSREG_ICC_AP1R0_EL1 = 0xC648,

+ ARM64_SYSREG_ICC_AP1R1_EL1 = 0xC649,

+ ARM64_SYSREG_ICC_AP1R2_EL1 = 0xC64A,

+ ARM64_SYSREG_ICC_AP1R3_EL1 = 0xC64B,

+ ARM64_SYSREG_ICH_AP0R0_EL2 = 0xE640,

+ ARM64_SYSREG_ICH_AP0R1_EL2 = 0xE641,

+ ARM64_SYSREG_ICH_AP0R2_EL2 = 0xE642,

+ ARM64_SYSREG_ICH_AP0R3_EL2 = 0xE643,

+ ARM64_SYSREG_ICH_AP1R0_EL2 = 0xE648,

+ ARM64_SYSREG_ICH_AP1R1_EL2 = 0xE649,

+ ARM64_SYSREG_ICH_AP1R2_EL2 = 0xE64A,

+ ARM64_SYSREG_ICH_AP1R3_EL2 = 0xE64B,

+ ARM64_SYSREG_ICH_HCR_EL2 = 0xE658,

+ ARM64_SYSREG_ICH_MISR_EL2 = 0xE65A,

+ ARM64_SYSREG_ICH_VMCR_EL2 = 0xE65F,

+ ARM64_SYSREG_ICH_VSEIR_EL2 = 0xE64C,

+ ARM64_SYSREG_ICH_LR0_EL2 = 0xE660,

+ ARM64_SYSREG_ICH_LR1_EL2 = 0xE661,

+ ARM64_SYSREG_ICH_LR2_EL2 = 0xE662,

+ ARM64_SYSREG_ICH_LR3_EL2 = 0xE663,

+ ARM64_SYSREG_ICH_LR4_EL2 = 0xE664,

+ ARM64_SYSREG_ICH_LR5_EL2 = 0xE665,

+ ARM64_SYSREG_ICH_LR6_EL2 = 0xE666,

+ ARM64_SYSREG_ICH_LR7_EL2 = 0xE667,

+ ARM64_SYSREG_ICH_LR8_EL2 = 0xE668,

+ ARM64_SYSREG_ICH_LR9_EL2 = 0xE669,

+ ARM64_SYSREG_ICH_LR10_EL2 = 0xE66A,

+ ARM64_SYSREG_ICH_LR11_EL2 = 0xE66B,

+ ARM64_SYSREG_ICH_LR12_EL2 = 0xE66C,

+ ARM64_SYSREG_ICH_LR13_EL2 = 0xE66D,

+ ARM64_SYSREG_ICH_LR14_EL2 = 0xE66E,

+ ARM64_SYSREG_ICH_LR15_EL2 = 0xE66F,

+ ARM64_SYSREG_PAN = 0xC213,

+ ARM64_SYSREG_LORSA_EL1 = 0xC520,

+ ARM64_SYSREG_LOREA_EL1 = 0xC521,

+ ARM64_SYSREG_LORN_EL1 = 0xC522,

+ ARM64_SYSREG_LORC_EL1 = 0xC523,

+ ARM64_SYSREG_TTBR1_EL2 = 0xE101,

+ ARM64_SYSREG_CONTEXTIDR_EL2 = 0xE681,

+ ARM64_SYSREG_CNTHV_TVAL_EL2 = 0xE718,

+ ARM64_SYSREG_CNTHV_CVAL_EL2 = 0xE71A,

+ ARM64_SYSREG_CNTHV_CTL_EL2 = 0xE719,

+ ARM64_SYSREG_SCTLR_EL12 = 0xE880,

+ ARM64_SYSREG_CPACR_EL12 = 0xE882,

+ ARM64_SYSREG_TTBR0_EL12 = 0xE900,

+ ARM64_SYSREG_TTBR1_EL12 = 0xE901,

+ ARM64_SYSREG_TCR_EL12 = 0xE902,

+ ARM64_SYSREG_AFSR0_EL12 = 0xEA88,

+ ARM64_SYSREG_AFSR1_EL12 = 0xEA89,

+ ARM64_SYSREG_ESR_EL12 = 0xEA90,

+ ARM64_SYSREG_FAR_EL12 = 0xEB00,

+ ARM64_SYSREG_MAIR_EL12 = 0xED10,

+ ARM64_SYSREG_AMAIR_EL12 = 0xED18,

+ ARM64_SYSREG_VBAR_EL12 = 0xEE00,

+ ARM64_SYSREG_CONTEXTIDR_EL12 = 0xEE81,

+ ARM64_SYSREG_CNTKCTL_EL12 = 0xEF08,

+ ARM64_SYSREG_CNTP_TVAL_EL02 = 0xEF10,

+ ARM64_SYSREG_CNTP_CTL_EL02 = 0xEF11,

+ ARM64_SYSREG_CNTP_CVAL_EL02 = 0xEF12,

+ ARM64_SYSREG_CNTV_TVAL_EL02 = 0xEF18,

+ ARM64_SYSREG_CNTV_CTL_EL02 = 0xEF19,

+ ARM64_SYSREG_CNTV_CVAL_EL02 = 0xEF1A,

+ ARM64_SYSREG_SPSR_EL12 = 0xEA00,

+ ARM64_SYSREG_ELR_EL12 = 0xEA01,

+ ARM64_SYSREG_UAO = 0xC214,

+ ARM64_SYSREG_PMBLIMITR_EL1 = 0xC4D0,

+ ARM64_SYSREG_PMBPTR_EL1 = 0xC4D1,

+ ARM64_SYSREG_PMBSR_EL1 = 0xC4D3,

+ ARM64_SYSREG_PMBIDR_EL1 = 0xC4D7,

+ ARM64_SYSREG_PMSCR_EL2 = 0xE4C8,

+ ARM64_SYSREG_PMSCR_EL12 = 0xECC8,

+ ARM64_SYSREG_PMSCR_EL1 = 0xC4C8,

+ ARM64_SYSREG_PMSICR_EL1 = 0xC4CA,

+ ARM64_SYSREG_PMSIRR_EL1 = 0xC4CB,

+ ARM64_SYSREG_PMSFCR_EL1 = 0xC4CC,

+ ARM64_SYSREG_PMSEVFR_EL1 = 0xC4CD,

+ ARM64_SYSREG_PMSLATFR_EL1 = 0xC4CE,

+ ARM64_SYSREG_PMSIDR_EL1 = 0xC4CF,

+ ARM64_SYSREG_ERRSELR_EL1 = 0xC299,

+ ARM64_SYSREG_ERXCTLR_EL1 = 0xC2A1,

+ ARM64_SYSREG_ERXSTATUS_EL1 = 0xC2A2,

+ ARM64_SYSREG_ERXADDR_EL1 = 0xC2A3,

+ ARM64_SYSREG_ERXMISC0_EL1 = 0xC2A8,

+ ARM64_SYSREG_ERXMISC1_EL1 = 0xC2A9,

+ ARM64_SYSREG_DISR_EL1 = 0xC609,

+ ARM64_SYSREG_VDISR_EL2 = 0xE609,

+ ARM64_SYSREG_VSESR_EL2 = 0xE293,

+ ARM64_SYSREG_APIAKEYLO_EL1 = 0xC108,

+ ARM64_SYSREG_APIAKEYHI_EL1 = 0xC109,

+ ARM64_SYSREG_APIBKEYLO_EL1 = 0xC10A,

+ ARM64_SYSREG_APIBKEYHI_EL1 = 0xC10B,

+ ARM64_SYSREG_APDAKEYLO_EL1 = 0xC110,

+ ARM64_SYSREG_APDAKEYHI_EL1 = 0xC111,

+ ARM64_SYSREG_APDBKEYLO_EL1 = 0xC112,

+ ARM64_SYSREG_APDBKEYHI_EL1 = 0xC113,

+ ARM64_SYSREG_APGAKEYLO_EL1 = 0xC118,

+ ARM64_SYSREG_APGAKEYHI_EL1 = 0xC119,

+ ARM64_SYSREG_VSTCR_EL2 = 0xE132,

+ ARM64_SYSREG_VSTTBR_EL2 = 0xE130,

+ ARM64_SYSREG_CNTHVS_TVAL_EL2 = 0xE720,

+ ARM64_SYSREG_CNTHVS_CVAL_EL2 = 0xE722,

+ ARM64_SYSREG_CNTHVS_CTL_EL2 = 0xE721,

+ ARM64_SYSREG_CNTHPS_TVAL_EL2 = 0xE728,

+ ARM64_SYSREG_CNTHPS_CVAL_EL2 = 0xE72A,

+ ARM64_SYSREG_CNTHPS_CTL_EL2 = 0xE729,

+ ARM64_SYSREG_SDER32_EL2 = 0xE099,

+ ARM64_SYSREG_ERXPFGCTL_EL1 = 0xC2A5,

+ ARM64_SYSREG_ERXPFGCDN_EL1 = 0xC2A6,

+ ARM64_SYSREG_ERXTS_EL1 = 0xC2AF,

+ ARM64_SYSREG_ERXMISC2_EL1 = 0xC2AA,

+ ARM64_SYSREG_ERXMISC3_EL1 = 0xC2AB,

+ ARM64_SYSREG_ERXPFGF_EL1 = 0xC2A4,

+ ARM64_SYSREG_MPAM0_EL1 = 0xC529,

+ ARM64_SYSREG_MPAM1_EL1 = 0xC528,

+ ARM64_SYSREG_MPAM2_EL2 = 0xE528,

+ ARM64_SYSREG_MPAM3_EL3 = 0xF528,

+ ARM64_SYSREG_MPAM1_EL12 = 0xED28,

+ ARM64_SYSREG_MPAMHCR_EL2 = 0xE520,

+ ARM64_SYSREG_MPAMVPMV_EL2 = 0xE521,

+ ARM64_SYSREG_MPAMVPM0_EL2 = 0xE530,

+ ARM64_SYSREG_MPAMVPM1_EL2 = 0xE531,

+ ARM64_SYSREG_MPAMVPM2_EL2 = 0xE532,

+ ARM64_SYSREG_MPAMVPM3_EL2 = 0xE533,

+ ARM64_SYSREG_MPAMVPM4_EL2 = 0xE534,

+ ARM64_SYSREG_MPAMVPM5_EL2 = 0xE535,

+ ARM64_SYSREG_MPAMVPM6_EL2 = 0xE536,

+ ARM64_SYSREG_MPAMVPM7_EL2 = 0xE537,

+ ARM64_SYSREG_MPAMIDR_EL1 = 0xC524,

+ ARM64_SYSREG_AMCR_EL0 = 0xDE90,

+ ARM64_SYSREG_AMCFGR_EL0 = 0xDE91,

+ ARM64_SYSREG_AMCGCR_EL0 = 0xDE92,

+ ARM64_SYSREG_AMUSERENR_EL0 = 0xDE93,

+ ARM64_SYSREG_AMCNTENCLR0_EL0 = 0xDE94,

+ ARM64_SYSREG_AMCNTENSET0_EL0 = 0xDE95,

+ ARM64_SYSREG_AMEVCNTR00_EL0 = 0xDEA0,

+ ARM64_SYSREG_AMEVCNTR01_EL0 = 0xDEA1,

+ ARM64_SYSREG_AMEVCNTR02_EL0 = 0xDEA2,

+ ARM64_SYSREG_AMEVCNTR03_EL0 = 0xDEA3,

+ ARM64_SYSREG_AMEVTYPER00_EL0 = 0xDEB0,

+ ARM64_SYSREG_AMEVTYPER01_EL0 = 0xDEB1,

+ ARM64_SYSREG_AMEVTYPER02_EL0 = 0xDEB2,

+ ARM64_SYSREG_AMEVTYPER03_EL0 = 0xDEB3,

+ ARM64_SYSREG_AMCNTENCLR1_EL0 = 0xDE98,

+ ARM64_SYSREG_AMCNTENSET1_EL0 = 0xDE99,

+ ARM64_SYSREG_AMEVCNTR10_EL0 = 0xDEE0,

+ ARM64_SYSREG_AMEVCNTR11_EL0 = 0xDEE1,

+ ARM64_SYSREG_AMEVCNTR12_EL0 = 0xDEE2,

+ ARM64_SYSREG_AMEVCNTR13_EL0 = 0xDEE3,

+ ARM64_SYSREG_AMEVCNTR14_EL0 = 0xDEE4,

+ ARM64_SYSREG_AMEVCNTR15_EL0 = 0xDEE5,

+ ARM64_SYSREG_AMEVCNTR16_EL0 = 0xDEE6,

+ ARM64_SYSREG_AMEVCNTR17_EL0 = 0xDEE7,

+ ARM64_SYSREG_AMEVCNTR18_EL0 = 0xDEE8,

+ ARM64_SYSREG_AMEVCNTR19_EL0 = 0xDEE9,

+ ARM64_SYSREG_AMEVCNTR110_EL0 = 0xDEEA,

+ ARM64_SYSREG_AMEVCNTR111_EL0 = 0xDEEB,

+ ARM64_SYSREG_AMEVCNTR112_EL0 = 0xDEEC,

+ ARM64_SYSREG_AMEVCNTR113_EL0 = 0xDEED,

+ ARM64_SYSREG_AMEVCNTR114_EL0 = 0xDEEE,

+ ARM64_SYSREG_AMEVCNTR115_EL0 = 0xDEEF,

+ ARM64_SYSREG_AMEVTYPER10_EL0 = 0xDEF0,

+ ARM64_SYSREG_AMEVTYPER11_EL0 = 0xDEF1,

+ ARM64_SYSREG_AMEVTYPER12_EL0 = 0xDEF2,

+ ARM64_SYSREG_AMEVTYPER13_EL0 = 0xDEF3,

+ ARM64_SYSREG_AMEVTYPER14_EL0 = 0xDEF4,

+ ARM64_SYSREG_AMEVTYPER15_EL0 = 0xDEF5,

+ ARM64_SYSREG_AMEVTYPER16_EL0 = 0xDEF6,

+ ARM64_SYSREG_AMEVTYPER17_EL0 = 0xDEF7,

+ ARM64_SYSREG_AMEVTYPER18_EL0 = 0xDEF8,

+ ARM64_SYSREG_AMEVTYPER19_EL0 = 0xDEF9,

+ ARM64_SYSREG_AMEVTYPER110_EL0 = 0xDEFA,

+ ARM64_SYSREG_AMEVTYPER111_EL0 = 0xDEFB,

+ ARM64_SYSREG_AMEVTYPER112_EL0 = 0xDEFC,

+ ARM64_SYSREG_AMEVTYPER113_EL0 = 0xDEFD,

+ ARM64_SYSREG_AMEVTYPER114_EL0 = 0xDEFE,

+ ARM64_SYSREG_AMEVTYPER115_EL0 = 0xDEFF,

+ ARM64_SYSREG_TRFCR_EL1 = 0xC091,

+ ARM64_SYSREG_TRFCR_EL2 = 0xE091,

+ ARM64_SYSREG_TRFCR_EL12 = 0xE891,

+ ARM64_SYSREG_DIT = 0xDA15,

+ ARM64_SYSREG_VNCR_EL2 = 0xE110,

+ ARM64_SYSREG_ZCR_EL1 = 0xC090,

+ ARM64_SYSREG_ZCR_EL2 = 0xE090,

+ ARM64_SYSREG_ZCR_EL3 = 0xF090,

+ ARM64_SYSREG_ZCR_EL12 = 0xE890,

+ ARM64_SYSREG_CPM_IOACC_CTL_EL3 = 0xFF90,

+} arm64_sysreg;

+

+/// System PState Field (MSR instruction)

+typedef enum arm64_pstate {

+ ARM64_PSTATE_INVALID = 0,

+ ARM64_PSTATE_SPSEL = 0x05,

+ ARM64_PSTATE_DAIFSET = 0x1e,

+ ARM64_PSTATE_DAIFCLR = 0x1f,

+ ARM64_PSTATE_PAN = 0x4,

+ ARM64_PSTATE_UAO = 0x3,

+ ARM64_PSTATE_DIT = 0x1a,

+} arm64_pstate;

+

+/// Vector arrangement specifier (for FloatingPoint/Advanced SIMD insn)

+typedef enum arm64_vas {

+ ARM64_VAS_INVALID = 0,

+ ARM64_VAS_16B,

+ ARM64_VAS_8B,

+ ARM64_VAS_4B,

+ ARM64_VAS_1B,

+ ARM64_VAS_8H,

+ ARM64_VAS_4H,

+ ARM64_VAS_2H,

+ ARM64_VAS_1H,

+ ARM64_VAS_4S,

+ ARM64_VAS_2S,

+ ARM64_VAS_1S,

+ ARM64_VAS_2D,

+ ARM64_VAS_1D,

+ ARM64_VAS_1Q,

+} arm64_vas;

+

+/// Memory barrier operands

+typedef enum arm64_barrier_op {

+ ARM64_BARRIER_INVALID = 0,

+ ARM64_BARRIER_OSHLD = 0x1,

+ ARM64_BARRIER_OSHST = 0x2,

+ ARM64_BARRIER_OSH = 0x3,

+ ARM64_BARRIER_NSHLD = 0x5,

+ ARM64_BARRIER_NSHST = 0x6,

+ ARM64_BARRIER_NSH = 0x7,

+ ARM64_BARRIER_ISHLD = 0x9,

+ ARM64_BARRIER_ISHST = 0xa,

+ ARM64_BARRIER_ISH = 0xb,

+ ARM64_BARRIER_LD = 0xd,

+ ARM64_BARRIER_ST = 0xe,

+ ARM64_BARRIER_SY = 0xf

+} arm64_barrier_op;

+

+/// Operand type for instruction's operands

+typedef enum arm64_op_type {

+ ARM64_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).

+ ARM64_OP_REG, ///< = CS_OP_REG (Register operand).

+ ARM64_OP_IMM, ///< = CS_OP_IMM (Immediate operand).

+ ARM64_OP_MEM, ///< = CS_OP_MEM (Memory operand).

+ ARM64_OP_FP, ///< = CS_OP_FP (Floating-Point operand).

+ ARM64_OP_CIMM = 64, ///< C-Immediate

+ ARM64_OP_REG_MRS, ///< MRS register operand.

+ ARM64_OP_REG_MSR, ///< MSR register operand.

+ ARM64_OP_PSTATE, ///< PState operand.

+ ARM64_OP_SYS, ///< SYS operand for IC/DC/AT/TLBI instructions.

+ ARM64_OP_PREFETCH, ///< Prefetch operand (PRFM).

+ ARM64_OP_BARRIER, ///< Memory barrier operand (ISB/DMB/DSB instructions).

+} arm64_op_type;

+

+/// TLBI operations

+typedef enum arm64_tlbi_op {

+ ARM64_TLBI_INVALID = 0,

+

+ ARM64_TLBI_IPAS2E1IS,

+ ARM64_TLBI_IPAS2LE1IS,

+ ARM64_TLBI_VMALLE1IS,

+ ARM64_TLBI_ALLE2IS,

+ ARM64_TLBI_ALLE3IS,

+ ARM64_TLBI_VAE1IS,

+ ARM64_TLBI_VAE2IS,

+ ARM64_TLBI_VAE3IS,

+ ARM64_TLBI_ASIDE1IS,

+ ARM64_TLBI_VAAE1IS,

+ ARM64_TLBI_ALLE1IS,

+ ARM64_TLBI_VALE1IS,

+ ARM64_TLBI_VALE2IS,

+ ARM64_TLBI_VALE3IS,

+ ARM64_TLBI_VMALLS12E1IS,

+ ARM64_TLBI_VAALE1IS,

+ ARM64_TLBI_IPAS2E1,

+ ARM64_TLBI_IPAS2LE1,

+ ARM64_TLBI_VMALLE1,

+ ARM64_TLBI_ALLE2,

+ ARM64_TLBI_ALLE3,

+ ARM64_TLBI_VAE1,

+ ARM64_TLBI_VAE2,

+ ARM64_TLBI_VAE3,

+ ARM64_TLBI_ASIDE1,

+ ARM64_TLBI_VAAE1,

+ ARM64_TLBI_ALLE1,

+ ARM64_TLBI_VALE1,

+ ARM64_TLBI_VALE2,

+ ARM64_TLBI_VALE3,

+ ARM64_TLBI_VMALLS12E1,

+ ARM64_TLBI_VAALE1,

+ ARM64_TLBI_VMALLE1OS,

+ ARM64_TLBI_VAE1OS,

+ ARM64_TLBI_ASIDE1OS,

+ ARM64_TLBI_VAAE1OS,

+ ARM64_TLBI_VALE1OS,

+ ARM64_TLBI_VAALE1OS,

+ ARM64_TLBI_IPAS2E1OS,

+ ARM64_TLBI_IPAS2LE1OS,

+ ARM64_TLBI_VAE2OS,

+ ARM64_TLBI_VALE2OS,

+ ARM64_TLBI_VMALLS12E1OS,

+ ARM64_TLBI_VAE3OS,

+ ARM64_TLBI_VALE3OS,

+ ARM64_TLBI_ALLE2OS,

+ ARM64_TLBI_ALLE1OS,

+ ARM64_TLBI_ALLE3OS,

+ ARM64_TLBI_RVAE1,

+ ARM64_TLBI_RVAAE1,

+ ARM64_TLBI_RVALE1,

+ ARM64_TLBI_RVAALE1,

+ ARM64_TLBI_RVAE1IS,

+ ARM64_TLBI_RVAAE1IS,

+ ARM64_TLBI_RVALE1IS,

+ ARM64_TLBI_RVAALE1IS,

+ ARM64_TLBI_RVAE1OS,

+ ARM64_TLBI_RVAAE1OS,

+ ARM64_TLBI_RVALE1OS,

+ ARM64_TLBI_RVAALE1OS,

+ ARM64_TLBI_RIPAS2E1IS,

+ ARM64_TLBI_RIPAS2LE1IS,

+ ARM64_TLBI_RIPAS2E1,

+ ARM64_TLBI_RIPAS2LE1,

+ ARM64_TLBI_RIPAS2E1OS,

+ ARM64_TLBI_RIPAS2LE1OS,

+ ARM64_TLBI_RVAE2,

+ ARM64_TLBI_RVALE2,

+ ARM64_TLBI_RVAE2IS,

+ ARM64_TLBI_RVALE2IS,

+ ARM64_TLBI_RVAE2OS,

+ ARM64_TLBI_RVALE2OS,

+ ARM64_TLBI_RVAE3,

+ ARM64_TLBI_RVALE3,

+ ARM64_TLBI_RVAE3IS,

+ ARM64_TLBI_RVALE3IS,

+ ARM64_TLBI_RVAE3OS,

+ ARM64_TLBI_RVALE3OS,

+} arm64_tlbi_op;

+

+/// AT operations

+typedef enum arm64_at_op {

+ ARM64_AT_S1E1R,

+ ARM64_AT_S1E2R,

+ ARM64_AT_S1E3R,

+ ARM64_AT_S1E1W,

+ ARM64_AT_S1E2W,

+ ARM64_AT_S1E3W,

+ ARM64_AT_S1E0R,

+ ARM64_AT_S1E0W,

+ ARM64_AT_S12E1R,

+ ARM64_AT_S12E1W,

+ ARM64_AT_S12E0R,

+ ARM64_AT_S12E0W,

+ ARM64_AT_S1E1RP,

+ ARM64_AT_S1E1WP,

+} arm64_at_op;

+

+/// DC operations

+typedef enum arm64_dc_op {

+ ARM64_DC_INVALID = 0,

+ ARM64_DC_ZVA,

+ ARM64_DC_IVAC,

+ ARM64_DC_ISW,

+ ARM64_DC_CVAC,

+ ARM64_DC_CSW,

+ ARM64_DC_CVAU,

+ ARM64_DC_CIVAC,

+ ARM64_DC_CISW,

+ ARM64_DC_CVAP,

+} arm64_dc_op;

+

+/// IC operations

+typedef enum arm64_ic_op {

+ ARM64_IC_INVALID = 0,

+ ARM64_IC_IALLUIS,

+ ARM64_IC_IALLU,

+ ARM64_IC_IVAU,

+} arm64_ic_op;

+

+/// Prefetch operations (PRFM)

+typedef enum arm64_prefetch_op {

+ ARM64_PRFM_INVALID = 0,

+ ARM64_PRFM_PLDL1KEEP = 0x00 + 1,

+ ARM64_PRFM_PLDL1STRM = 0x01 + 1,

+ ARM64_PRFM_PLDL2KEEP = 0x02 + 1,

+ ARM64_PRFM_PLDL2STRM = 0x03 + 1,

+ ARM64_PRFM_PLDL3KEEP = 0x04 + 1,

+ ARM64_PRFM_PLDL3STRM = 0x05 + 1,

+ ARM64_PRFM_PLIL1KEEP = 0x08 + 1,

+ ARM64_PRFM_PLIL1STRM = 0x09 + 1,

+ ARM64_PRFM_PLIL2KEEP = 0x0a + 1,

+ ARM64_PRFM_PLIL2STRM = 0x0b + 1,

+ ARM64_PRFM_PLIL3KEEP = 0x0c + 1,

+ ARM64_PRFM_PLIL3STRM = 0x0d + 1,

+ ARM64_PRFM_PSTL1KEEP = 0x10 + 1,

+ ARM64_PRFM_PSTL1STRM = 0x11 + 1,

+ ARM64_PRFM_PSTL2KEEP = 0x12 + 1,

+ ARM64_PRFM_PSTL2STRM = 0x13 + 1,

+ ARM64_PRFM_PSTL3KEEP = 0x14 + 1,

+ ARM64_PRFM_PSTL3STRM = 0x15 + 1,

+} arm64_prefetch_op;

+

+/// ARM64 registers

+typedef enum arm64_reg {

+ ARM64_REG_INVALID = 0,

+

+ ARM64_REG_FFR = 1,

+ ARM64_REG_FP = 2,

+ ARM64_REG_LR = 3,

+ ARM64_REG_NZCV = 4,

+ ARM64_REG_SP = 5,

+ ARM64_REG_WSP = 6,

+ ARM64_REG_WZR = 7,

+ ARM64_REG_XZR = 8,

+ ARM64_REG_B0 = 9,

+ ARM64_REG_B1 = 10,

+ ARM64_REG_B2 = 11,

+ ARM64_REG_B3 = 12,

+ ARM64_REG_B4 = 13,

+ ARM64_REG_B5 = 14,

+ ARM64_REG_B6 = 15,

+ ARM64_REG_B7 = 16,

+ ARM64_REG_B8 = 17,

+ ARM64_REG_B9 = 18,

+ ARM64_REG_B10 = 19,

+ ARM64_REG_B11 = 20,

+ ARM64_REG_B12 = 21,

+ ARM64_REG_B13 = 22,

+ ARM64_REG_B14 = 23,

+ ARM64_REG_B15 = 24,

+ ARM64_REG_B16 = 25,

+ ARM64_REG_B17 = 26,

+ ARM64_REG_B18 = 27,

+ ARM64_REG_B19 = 28,

+ ARM64_REG_B20 = 29,

+ ARM64_REG_B21 = 30,

+ ARM64_REG_B22 = 31,

+ ARM64_REG_B23 = 32,

+ ARM64_REG_B24 = 33,

+ ARM64_REG_B25 = 34,

+ ARM64_REG_B26 = 35,

+ ARM64_REG_B27 = 36,

+ ARM64_REG_B28 = 37,

+ ARM64_REG_B29 = 38,

+ ARM64_REG_B30 = 39,

+ ARM64_REG_B31 = 40,

+ ARM64_REG_D0 = 41,

+ ARM64_REG_D1 = 42,

+ ARM64_REG_D2 = 43,

+ ARM64_REG_D3 = 44,

+ ARM64_REG_D4 = 45,

+ ARM64_REG_D5 = 46,

+ ARM64_REG_D6 = 47,

+ ARM64_REG_D7 = 48,

+ ARM64_REG_D8 = 49,

+ ARM64_REG_D9 = 50,

+ ARM64_REG_D10 = 51,

+ ARM64_REG_D11 = 52,

+ ARM64_REG_D12 = 53,

+ ARM64_REG_D13 = 54,

+ ARM64_REG_D14 = 55,

+ ARM64_REG_D15 = 56,

+ ARM64_REG_D16 = 57,

+ ARM64_REG_D17 = 58,

+ ARM64_REG_D18 = 59,

+ ARM64_REG_D19 = 60,

+ ARM64_REG_D20 = 61,

+ ARM64_REG_D21 = 62,

+ ARM64_REG_D22 = 63,

+ ARM64_REG_D23 = 64,

+ ARM64_REG_D24 = 65,

+ ARM64_REG_D25 = 66,

+ ARM64_REG_D26 = 67,

+ ARM64_REG_D27 = 68,

+ ARM64_REG_D28 = 69,

+ ARM64_REG_D29 = 70,

+ ARM64_REG_D30 = 71,

+ ARM64_REG_D31 = 72,

+ ARM64_REG_H0 = 73,

+ ARM64_REG_H1 = 74,

+ ARM64_REG_H2 = 75,

+ ARM64_REG_H3 = 76,

+ ARM64_REG_H4 = 77,

+ ARM64_REG_H5 = 78,

+ ARM64_REG_H6 = 79,

+ ARM64_REG_H7 = 80,

+ ARM64_REG_H8 = 81,

+ ARM64_REG_H9 = 82,

+ ARM64_REG_H10 = 83,

+ ARM64_REG_H11 = 84,

+ ARM64_REG_H12 = 85,

+ ARM64_REG_H13 = 86,

+ ARM64_REG_H14 = 87,

+ ARM64_REG_H15 = 88,

+ ARM64_REG_H16 = 89,

+ ARM64_REG_H17 = 90,

+ ARM64_REG_H18 = 91,

+ ARM64_REG_H19 = 92,

+ ARM64_REG_H20 = 93,

+ ARM64_REG_H21 = 94,

+ ARM64_REG_H22 = 95,

+ ARM64_REG_H23 = 96,

+ ARM64_REG_H24 = 97,

+ ARM64_REG_H25 = 98,

+ ARM64_REG_H26 = 99,

+ ARM64_REG_H27 = 100,

+ ARM64_REG_H28 = 101,

+ ARM64_REG_H29 = 102,

+ ARM64_REG_H30 = 103,

+ ARM64_REG_H31 = 104,

+ ARM64_REG_P0 = 105,

+ ARM64_REG_P1 = 106,

+ ARM64_REG_P2 = 107,

+ ARM64_REG_P3 = 108,

+ ARM64_REG_P4 = 109,

+ ARM64_REG_P5 = 110,

+ ARM64_REG_P6 = 111,

+ ARM64_REG_P7 = 112,

+ ARM64_REG_P8 = 113,

+ ARM64_REG_P9 = 114,

+ ARM64_REG_P10 = 115,

+ ARM64_REG_P11 = 116,

+ ARM64_REG_P12 = 117,

+ ARM64_REG_P13 = 118,

+ ARM64_REG_P14 = 119,

+ ARM64_REG_P15 = 120,

+ ARM64_REG_Q0 = 121,

+ ARM64_REG_Q1 = 122,

+ ARM64_REG_Q2 = 123,

+ ARM64_REG_Q3 = 124,

+ ARM64_REG_Q4 = 125,

+ ARM64_REG_Q5 = 126,

+ ARM64_REG_Q6 = 127,

+ ARM64_REG_Q7 = 128,

+ ARM64_REG_Q8 = 129,

+ ARM64_REG_Q9 = 130,

+ ARM64_REG_Q10 = 131,

+ ARM64_REG_Q11 = 132,

+ ARM64_REG_Q12 = 133,

+ ARM64_REG_Q13 = 134,

+ ARM64_REG_Q14 = 135,

+ ARM64_REG_Q15 = 136,

+ ARM64_REG_Q16 = 137,

+ ARM64_REG_Q17 = 138,

+ ARM64_REG_Q18 = 139,

+ ARM64_REG_Q19 = 140,

+ ARM64_REG_Q20 = 141,

+ ARM64_REG_Q21 = 142,

+ ARM64_REG_Q22 = 143,

+ ARM64_REG_Q23 = 144,

+ ARM64_REG_Q24 = 145,

+ ARM64_REG_Q25 = 146,

+ ARM64_REG_Q26 = 147,

+ ARM64_REG_Q27 = 148,

+ ARM64_REG_Q28 = 149,

+ ARM64_REG_Q29 = 150,

+ ARM64_REG_Q30 = 151,

+ ARM64_REG_Q31 = 152,

+ ARM64_REG_S0 = 153,

+ ARM64_REG_S1 = 154,

+ ARM64_REG_S2 = 155,

+ ARM64_REG_S3 = 156,

+ ARM64_REG_S4 = 157,

+ ARM64_REG_S5 = 158,

+ ARM64_REG_S6 = 159,

+ ARM64_REG_S7 = 160,

+ ARM64_REG_S8 = 161,

+ ARM64_REG_S9 = 162,

+ ARM64_REG_S10 = 163,

+ ARM64_REG_S11 = 164,

+ ARM64_REG_S12 = 165,

+ ARM64_REG_S13 = 166,

+ ARM64_REG_S14 = 167,

+ ARM64_REG_S15 = 168,

+ ARM64_REG_S16 = 169,

+ ARM64_REG_S17 = 170,

+ ARM64_REG_S18 = 171,

+ ARM64_REG_S19 = 172,

+ ARM64_REG_S20 = 173,

+ ARM64_REG_S21 = 174,

+ ARM64_REG_S22 = 175,

+ ARM64_REG_S23 = 176,

+ ARM64_REG_S24 = 177,

+ ARM64_REG_S25 = 178,

+ ARM64_REG_S26 = 179,

+ ARM64_REG_S27 = 180,

+ ARM64_REG_S28 = 181,

+ ARM64_REG_S29 = 182,

+ ARM64_REG_S30 = 183,

+ ARM64_REG_S31 = 184,

+ ARM64_REG_W0 = 185,

+ ARM64_REG_W1 = 186,

+ ARM64_REG_W2 = 187,

+ ARM64_REG_W3 = 188,

+ ARM64_REG_W4 = 189,

+ ARM64_REG_W5 = 190,

+ ARM64_REG_W6 = 191,

+ ARM64_REG_W7 = 192,

+ ARM64_REG_W8 = 193,

+ ARM64_REG_W9 = 194,

+ ARM64_REG_W10 = 195,

+ ARM64_REG_W11 = 196,

+ ARM64_REG_W12 = 197,

+ ARM64_REG_W13 = 198,

+ ARM64_REG_W14 = 199,

+ ARM64_REG_W15 = 200,

+ ARM64_REG_W16 = 201,

+ ARM64_REG_W17 = 202,

+ ARM64_REG_W18 = 203,

+ ARM64_REG_W19 = 204,

+ ARM64_REG_W20 = 205,

+ ARM64_REG_W21 = 206,

+ ARM64_REG_W22 = 207,

+ ARM64_REG_W23 = 208,

+ ARM64_REG_W24 = 209,

+ ARM64_REG_W25 = 210,

+ ARM64_REG_W26 = 211,

+ ARM64_REG_W27 = 212,

+ ARM64_REG_W28 = 213,

+ ARM64_REG_W29 = 214,

+ ARM64_REG_W30 = 215,

+ ARM64_REG_X0 = 216,

+ ARM64_REG_X1 = 217,

+ ARM64_REG_X2 = 218,

+ ARM64_REG_X3 = 219,

+ ARM64_REG_X4 = 220,

+ ARM64_REG_X5 = 221,

+ ARM64_REG_X6 = 222,

+ ARM64_REG_X7 = 223,

+ ARM64_REG_X8 = 224,

+ ARM64_REG_X9 = 225,

+ ARM64_REG_X10 = 226,

+ ARM64_REG_X11 = 227,

+ ARM64_REG_X12 = 228,

+ ARM64_REG_X13 = 229,

+ ARM64_REG_X14 = 230,

+ ARM64_REG_X15 = 231,

+ ARM64_REG_X16 = 232,

+ ARM64_REG_X17 = 233,

+ ARM64_REG_X18 = 234,

+ ARM64_REG_X19 = 235,

+ ARM64_REG_X20 = 236,

+ ARM64_REG_X21 = 237,

+ ARM64_REG_X22 = 238,

+ ARM64_REG_X23 = 239,

+ ARM64_REG_X24 = 240,

+ ARM64_REG_X25 = 241,

+ ARM64_REG_X26 = 242,

+ ARM64_REG_X27 = 243,

+ ARM64_REG_X28 = 244,

+ ARM64_REG_Z0 = 245,

+ ARM64_REG_Z1 = 246,

+ ARM64_REG_Z2 = 247,

+ ARM64_REG_Z3 = 248,

+ ARM64_REG_Z4 = 249,

+ ARM64_REG_Z5 = 250,

+ ARM64_REG_Z6 = 251,

+ ARM64_REG_Z7 = 252,

+ ARM64_REG_Z8 = 253,

+ ARM64_REG_Z9 = 254,

+ ARM64_REG_Z10 = 255,

+ ARM64_REG_Z11 = 256,

+ ARM64_REG_Z12 = 257,

+ ARM64_REG_Z13 = 258,

+ ARM64_REG_Z14 = 259,

+ ARM64_REG_Z15 = 260,

+ ARM64_REG_Z16 = 261,

+ ARM64_REG_Z17 = 262,

+ ARM64_REG_Z18 = 263,

+ ARM64_REG_Z19 = 264,

+ ARM64_REG_Z20 = 265,

+ ARM64_REG_Z21 = 266,

+ ARM64_REG_Z22 = 267,

+ ARM64_REG_Z23 = 268,

+ ARM64_REG_Z24 = 269,

+ ARM64_REG_Z25 = 270,

+ ARM64_REG_Z26 = 271,

+ ARM64_REG_Z27 = 272,

+ ARM64_REG_Z28 = 273,

+ ARM64_REG_Z29 = 274,

+ ARM64_REG_Z30 = 275,

+ ARM64_REG_Z31 = 276,

+

+ ARM64_REG_V0,

+ ARM64_REG_V1,

+ ARM64_REG_V2,

+ ARM64_REG_V3,

+ ARM64_REG_V4,

+ ARM64_REG_V5,

+ ARM64_REG_V6,

+ ARM64_REG_V7,

+ ARM64_REG_V8,

+ ARM64_REG_V9,

+ ARM64_REG_V10,

+ ARM64_REG_V11,

+ ARM64_REG_V12,

+ ARM64_REG_V13,

+ ARM64_REG_V14,

+ ARM64_REG_V15,

+ ARM64_REG_V16,

+ ARM64_REG_V17,

+ ARM64_REG_V18,

+ ARM64_REG_V19,

+ ARM64_REG_V20,

+ ARM64_REG_V21,

+ ARM64_REG_V22,

+ ARM64_REG_V23,

+ ARM64_REG_V24,

+ ARM64_REG_V25,

+ ARM64_REG_V26,

+ ARM64_REG_V27,

+ ARM64_REG_V28,

+ ARM64_REG_V29,

+ ARM64_REG_V30,

+ ARM64_REG_V31,

+

+ ARM64_REG_ENDING, // <-- mark the end of the list of registers

+

+ // alias registers

+ ARM64_REG_IP0 = ARM64_REG_X16,

+ ARM64_REG_IP1 = ARM64_REG_X17,

+ ARM64_REG_X29 = ARM64_REG_FP,

+ ARM64_REG_X30 = ARM64_REG_LR,

+} arm64_reg;

+

+/// Instruction's operand referring to memory

+/// This is associated with ARM64_OP_MEM operand type above

+typedef struct arm64_op_mem {

+ arm64_reg base; ///< base register

+ arm64_reg index; ///< index register

+ int32_t disp; ///< displacement/offset value

+} arm64_op_mem;

+

+/// Instruction operand

+typedef struct cs_arm64_op {

+ int vector_index; ///< Vector Index for some vector operands (or -1 if irrelevant)

+ arm64_vas vas; ///< Vector Arrangement Specifier

+ struct {

+ arm64_shifter type; ///< shifter type of this operand

+ unsigned int value; ///< shifter value of this operand

+ } shift;

+ arm64_extender ext; ///< extender type of this operand

+ arm64_op_type type; ///< operand type

+ union {

+ arm64_reg reg; ///< register value for REG operand

+ int64_t imm; ///< immediate value, or index for C-IMM or IMM operand

+ double fp; ///< floating point value for FP operand

+ arm64_op_mem mem; ///< base/index/scale/disp value for MEM operand

+ arm64_pstate pstate; ///< PState field of MSR instruction.

+ unsigned int sys; ///< IC/DC/AT/TLBI operation (see arm64_ic_op, arm64_dc_op, arm64_at_op, arm64_tlbi_op)

+ arm64_prefetch_op prefetch; ///< PRFM operation.

+ arm64_barrier_op barrier; ///< Memory barrier operation (ISB/DMB/DSB instructions).

+ };

+

+ /// How is this operand accessed? (READ, WRITE or READ|WRITE)

+ /// This field is combined of cs_ac_type.

+ /// NOTE: this field is irrelevant if engine is compiled in DIET mode.

+ uint8_t access;

+} cs_arm64_op;

+

+/// Instruction structure

+typedef struct cs_arm64 {

+ arm64_cc cc; ///< conditional code for this insn

+ bool update_flags; ///< does this insn update flags?

+ bool writeback; ///< does this insn request writeback? 'True' means 'yes'

+

+ /// Number of operands of this instruction,

+ /// or 0 when instruction has no operand.

+ uint8_t op_count;

+

+ cs_arm64_op operands[8]; ///< operands for this instruction.

+} cs_arm64;

+

+/// ARM64 instruction

+typedef enum arm64_insn {

+ ARM64_INS_INVALID = 0,

+

+ ARM64_INS_ABS,

+ ARM64_INS_ADC,

+ ARM64_INS_ADCS,

+ ARM64_INS_ADD,

+ ARM64_INS_ADDHN,

+ ARM64_INS_ADDHN2,

+ ARM64_INS_ADDP,

+ ARM64_INS_ADDPL,

+ ARM64_INS_ADDS,

+ ARM64_INS_ADDV,

+ ARM64_INS_ADDVL,

+ ARM64_INS_ADR,

+ ARM64_INS_ADRP,

+ ARM64_INS_AESD,

+ ARM64_INS_AESE,

+ ARM64_INS_AESIMC,

+ ARM64_INS_AESMC,

+ ARM64_INS_AND,

+ ARM64_INS_ANDS,

+ ARM64_INS_ANDV,

+ ARM64_INS_ASR,

+ ARM64_INS_ASRD,

+ ARM64_INS_ASRR,

+ ARM64_INS_ASRV,

+ ARM64_INS_AUTDA,

+ ARM64_INS_AUTDB,

+ ARM64_INS_AUTDZA,

+ ARM64_INS_AUTDZB,

+ ARM64_INS_AUTIA,

+ ARM64_INS_AUTIA1716,

+ ARM64_INS_AUTIASP,

+ ARM64_INS_AUTIAZ,

+ ARM64_INS_AUTIB,

+ ARM64_INS_AUTIB1716,

+ ARM64_INS_AUTIBSP,

+ ARM64_INS_AUTIBZ,

+ ARM64_INS_AUTIZA,

+ ARM64_INS_AUTIZB,

+ ARM64_INS_B,

+ ARM64_INS_BCAX,

+ ARM64_INS_BFM,

+ ARM64_INS_BIC,

+ ARM64_INS_BICS,

+ ARM64_INS_BIF,

+ ARM64_INS_BIT,

+ ARM64_INS_BL,

+ ARM64_INS_BLR,

+ ARM64_INS_BLRAA,

+ ARM64_INS_BLRAAZ,

+ ARM64_INS_BLRAB,

+ ARM64_INS_BLRABZ,

+ ARM64_INS_BR,

+ ARM64_INS_BRAA,

+ ARM64_INS_BRAAZ,

+ ARM64_INS_BRAB,

+ ARM64_INS_BRABZ,

+ ARM64_INS_BRK,

+ ARM64_INS_BRKA,

+ ARM64_INS_BRKAS,

+ ARM64_INS_BRKB,

+ ARM64_INS_BRKBS,

+ ARM64_INS_BRKN,

+ ARM64_INS_BRKNS,

+ ARM64_INS_BRKPA,

+ ARM64_INS_BRKPAS,

+ ARM64_INS_BRKPB,

+ ARM64_INS_BRKPBS,

+ ARM64_INS_BSL,

+ ARM64_INS_CAS,

+ ARM64_INS_CASA,

+ ARM64_INS_CASAB,

+ ARM64_INS_CASAH,

+ ARM64_INS_CASAL,

+ ARM64_INS_CASALB,

+ ARM64_INS_CASALH,

+ ARM64_INS_CASB,

+ ARM64_INS_CASH,

+ ARM64_INS_CASL,

+ ARM64_INS_CASLB,

+ ARM64_INS_CASLH,

+ ARM64_INS_CASP,

+ ARM64_INS_CASPA,

+ ARM64_INS_CASPAL,

+ ARM64_INS_CASPL,

+ ARM64_INS_CBNZ,

+ ARM64_INS_CBZ,

+ ARM64_INS_CCMN,

+ ARM64_INS_CCMP,

+ ARM64_INS_CFINV,

+ ARM64_INS_CINC,

+ ARM64_INS_CINV,

+ ARM64_INS_CLASTA,

+ ARM64_INS_CLASTB,

+ ARM64_INS_CLREX,

+ ARM64_INS_CLS,

+ ARM64_INS_CLZ,

+ ARM64_INS_CMEQ,

+ ARM64_INS_CMGE,

+ ARM64_INS_CMGT,

+ ARM64_INS_CMHI,

+ ARM64_INS_CMHS,

+ ARM64_INS_CMLE,

+ ARM64_INS_CMLO,

+ ARM64_INS_CMLS,

+ ARM64_INS_CMLT,

+ ARM64_INS_CMN,

+ ARM64_INS_CMP,

+ ARM64_INS_CMPEQ,

+ ARM64_INS_CMPGE,

+ ARM64_INS_CMPGT,

+ ARM64_INS_CMPHI,

+ ARM64_INS_CMPHS,

+ ARM64_INS_CMPLE,

+ ARM64_INS_CMPLO,

+ ARM64_INS_CMPLS,

+ ARM64_INS_CMPLT,

+ ARM64_INS_CMPNE,

+ ARM64_INS_CMTST,

+ ARM64_INS_CNEG,

+ ARM64_INS_CNOT,

+ ARM64_INS_CNT,

+ ARM64_INS_CNTB,

+ ARM64_INS_CNTD,

+ ARM64_INS_CNTH,

+ ARM64_INS_CNTP,

+ ARM64_INS_CNTW,

+ ARM64_INS_COMPACT,

+ ARM64_INS_CPY,

+ ARM64_INS_CRC32B,

+ ARM64_INS_CRC32CB,

+ ARM64_INS_CRC32CH,

+ ARM64_INS_CRC32CW,

+ ARM64_INS_CRC32CX,

+ ARM64_INS_CRC32H,

+ ARM64_INS_CRC32W,

+ ARM64_INS_CRC32X,

+ ARM64_INS_CSDB,

+ ARM64_INS_CSEL,

+ ARM64_INS_CSET,

+ ARM64_INS_CSETM,

+ ARM64_INS_CSINC,

+ ARM64_INS_CSINV,

+ ARM64_INS_CSNEG,

+ ARM64_INS_CTERMEQ,

+ ARM64_INS_CTERMNE,

+ ARM64_INS_DCPS1,

+ ARM64_INS_DCPS2,

+ ARM64_INS_DCPS3,

+ ARM64_INS_DECB,

+ ARM64_INS_DECD,

+ ARM64_INS_DECH,

+ ARM64_INS_DECP,

+ ARM64_INS_DECW,

+ ARM64_INS_DMB,

+ ARM64_INS_DRPS,

+ ARM64_INS_DSB,

+ ARM64_INS_DUP,

+ ARM64_INS_DUPM,

+ ARM64_INS_EON,

+ ARM64_INS_EOR,

+ ARM64_INS_EOR3,

+ ARM64_INS_EORS,

+ ARM64_INS_EORV,

+ ARM64_INS_ERET,

+ ARM64_INS_ERETAA,

+ ARM64_INS_ERETAB,

+ ARM64_INS_ESB,

+ ARM64_INS_EXT,

+ ARM64_INS_EXTR,

+ ARM64_INS_FABD,

+ ARM64_INS_FABS,

+ ARM64_INS_FACGE,

+ ARM64_INS_FACGT,

+ ARM64_INS_FACLE,

+ ARM64_INS_FACLT,

+ ARM64_INS_FADD,

+ ARM64_INS_FADDA,

+ ARM64_INS_FADDP,

+ ARM64_INS_FADDV,

+ ARM64_INS_FCADD,

+ ARM64_INS_FCCMP,

+ ARM64_INS_FCCMPE,

+ ARM64_INS_FCMEQ,

+ ARM64_INS_FCMGE,

+ ARM64_INS_FCMGT,

+ ARM64_INS_FCMLA,

+ ARM64_INS_FCMLE,

+ ARM64_INS_FCMLT,

+ ARM64_INS_FCMNE,

+ ARM64_INS_FCMP,

+ ARM64_INS_FCMPE,

+ ARM64_INS_FCMUO,

+ ARM64_INS_FCPY,

+ ARM64_INS_FCSEL,

+ ARM64_INS_FCVT,

+ ARM64_INS_FCVTAS,

+ ARM64_INS_FCVTAU,

+ ARM64_INS_FCVTL,

+ ARM64_INS_FCVTL2,

+ ARM64_INS_FCVTMS,

+ ARM64_INS_FCVTMU,

+ ARM64_INS_FCVTN,

+ ARM64_INS_FCVTN2,

+ ARM64_INS_FCVTNS,

+ ARM64_INS_FCVTNU,

+ ARM64_INS_FCVTPS,

+ ARM64_INS_FCVTPU,

+ ARM64_INS_FCVTXN,

+ ARM64_INS_FCVTXN2,

+ ARM64_INS_FCVTZS,

+ ARM64_INS_FCVTZU,

+ ARM64_INS_FDIV,

+ ARM64_INS_FDIVR,

+ ARM64_INS_FDUP,

+ ARM64_INS_FEXPA,

+ ARM64_INS_FJCVTZS,

+ ARM64_INS_FMAD,

+ ARM64_INS_FMADD,

+ ARM64_INS_FMAX,

+ ARM64_INS_FMAXNM,

+ ARM64_INS_FMAXNMP,

+ ARM64_INS_FMAXNMV,

+ ARM64_INS_FMAXP,

+ ARM64_INS_FMAXV,

+ ARM64_INS_FMIN,

+ ARM64_INS_FMINNM,

+ ARM64_INS_FMINNMP,

+ ARM64_INS_FMINNMV,

+ ARM64_INS_FMINP,

+ ARM64_INS_FMINV,

+ ARM64_INS_FMLA,

+ ARM64_INS_FMLS,

+ ARM64_INS_FMOV,

+ ARM64_INS_FMSB,

+ ARM64_INS_FMSUB,

+ ARM64_INS_FMUL,

+ ARM64_INS_FMULX,

+ ARM64_INS_FNEG,

+ ARM64_INS_FNMAD,

+ ARM64_INS_FNMADD,

+ ARM64_INS_FNMLA,

+ ARM64_INS_FNMLS,

+ ARM64_INS_FNMSB,

+ ARM64_INS_FNMSUB,

+ ARM64_INS_FNMUL,

+ ARM64_INS_FRECPE,

+ ARM64_INS_FRECPS,

+ ARM64_INS_FRECPX,

+ ARM64_INS_FRINTA,

+ ARM64_INS_FRINTI,

+ ARM64_INS_FRINTM,

+ ARM64_INS_FRINTN,

+ ARM64_INS_FRINTP,

+ ARM64_INS_FRINTX,

+ ARM64_INS_FRINTZ,

+ ARM64_INS_FRSQRTE,

+ ARM64_INS_FRSQRTS,

+ ARM64_INS_FSCALE,

+ ARM64_INS_FSQRT,

+ ARM64_INS_FSUB,

+ ARM64_INS_FSUBR,

+ ARM64_INS_FTMAD,

+ ARM64_INS_FTSMUL,

+ ARM64_INS_FTSSEL,

+ ARM64_INS_HINT,

+ ARM64_INS_HLT,

+ ARM64_INS_HVC,

+ ARM64_INS_INCB,

+ ARM64_INS_INCD,

+ ARM64_INS_INCH,

+ ARM64_INS_INCP,

+ ARM64_INS_INCW,

+ ARM64_INS_INDEX,

+ ARM64_INS_INS,

+ ARM64_INS_INSR,

+ ARM64_INS_ISB,

+ ARM64_INS_LASTA,

+ ARM64_INS_LASTB,

+ ARM64_INS_LD1,

+ ARM64_INS_LD1B,

+ ARM64_INS_LD1D,

+ ARM64_INS_LD1H,

+ ARM64_INS_LD1R,

+ ARM64_INS_LD1RB,

+ ARM64_INS_LD1RD,

+ ARM64_INS_LD1RH,

+ ARM64_INS_LD1RQB,

+ ARM64_INS_LD1RQD,

+ ARM64_INS_LD1RQH,

+ ARM64_INS_LD1RQW,

+ ARM64_INS_LD1RSB,

+ ARM64_INS_LD1RSH,

+ ARM64_INS_LD1RSW,

+ ARM64_INS_LD1RW,

+ ARM64_INS_LD1SB,

+ ARM64_INS_LD1SH,

+ ARM64_INS_LD1SW,

+ ARM64_INS_LD1W,

+ ARM64_INS_LD2,

+ ARM64_INS_LD2B,

+ ARM64_INS_LD2D,

+ ARM64_INS_LD2H,

+ ARM64_INS_LD2R,

+ ARM64_INS_LD2W,

+ ARM64_INS_LD3,

+ ARM64_INS_LD3B,

+ ARM64_INS_LD3D,

+ ARM64_INS_LD3H,

+ ARM64_INS_LD3R,

+ ARM64_INS_LD3W,

+ ARM64_INS_LD4,

+ ARM64_INS_LD4B,

+ ARM64_INS_LD4D,

+ ARM64_INS_LD4H,

+ ARM64_INS_LD4R,

+ ARM64_INS_LD4W,

+ ARM64_INS_LDADD,

+ ARM64_INS_LDADDA,

+ ARM64_INS_LDADDAB,

+ ARM64_INS_LDADDAH,

+ ARM64_INS_LDADDAL,

+ ARM64_INS_LDADDALB,

+ ARM64_INS_LDADDALH,

+ ARM64_INS_LDADDB,

+ ARM64_INS_LDADDH,

+ ARM64_INS_LDADDL,

+ ARM64_INS_LDADDLB,

+ ARM64_INS_LDADDLH,

+ ARM64_INS_LDAPR,

+ ARM64_INS_LDAPRB,

+ ARM64_INS_LDAPRH,

+ ARM64_INS_LDAPUR,

+ ARM64_INS_LDAPURB,

+ ARM64_INS_LDAPURH,

+ ARM64_INS_LDAPURSB,

+ ARM64_INS_LDAPURSH,

+ ARM64_INS_LDAPURSW,

+ ARM64_INS_LDAR,

+ ARM64_INS_LDARB,

+ ARM64_INS_LDARH,

+ ARM64_INS_LDAXP,

+ ARM64_INS_LDAXR,

+ ARM64_INS_LDAXRB,

+ ARM64_INS_LDAXRH,

+ ARM64_INS_LDCLR,

+ ARM64_INS_LDCLRA,

+ ARM64_INS_LDCLRAB,

+ ARM64_INS_LDCLRAH,

+ ARM64_INS_LDCLRAL,

+ ARM64_INS_LDCLRALB,

+ ARM64_INS_LDCLRALH,

+ ARM64_INS_LDCLRB,

+ ARM64_INS_LDCLRH,

+ ARM64_INS_LDCLRL,

+ ARM64_INS_LDCLRLB,

+ ARM64_INS_LDCLRLH,

+ ARM64_INS_LDEOR,

+ ARM64_INS_LDEORA,

+ ARM64_INS_LDEORAB,

+ ARM64_INS_LDEORAH,

+ ARM64_INS_LDEORAL,

+ ARM64_INS_LDEORALB,

+ ARM64_INS_LDEORALH,

+ ARM64_INS_LDEORB,

+ ARM64_INS_LDEORH,

+ ARM64_INS_LDEORL,

+ ARM64_INS_LDEORLB,

+ ARM64_INS_LDEORLH,

+ ARM64_INS_LDFF1B,

+ ARM64_INS_LDFF1D,

+ ARM64_INS_LDFF1H,

+ ARM64_INS_LDFF1SB,

+ ARM64_INS_LDFF1SH,

+ ARM64_INS_LDFF1SW,

+ ARM64_INS_LDFF1W,

+ ARM64_INS_LDLAR,

+ ARM64_INS_LDLARB,

+ ARM64_INS_LDLARH,

+ ARM64_INS_LDNF1B,

+ ARM64_INS_LDNF1D,

+ ARM64_INS_LDNF1H,

+ ARM64_INS_LDNF1SB,

+ ARM64_INS_LDNF1SH,

+ ARM64_INS_LDNF1SW,

+ ARM64_INS_LDNF1W,

+ ARM64_INS_LDNP,

+ ARM64_INS_LDNT1B,

+ ARM64_INS_LDNT1D,

+ ARM64_INS_LDNT1H,

+ ARM64_INS_LDNT1W,

+ ARM64_INS_LDP,

+ ARM64_INS_LDPSW,

+ ARM64_INS_LDR,

+ ARM64_INS_LDRAA,

+ ARM64_INS_LDRAB,

+ ARM64_INS_LDRB,

+ ARM64_INS_LDRH,

+ ARM64_INS_LDRSB,

+ ARM64_INS_LDRSH,

+ ARM64_INS_LDRSW,

+ ARM64_INS_LDSET,

+ ARM64_INS_LDSETA,

+ ARM64_INS_LDSETAB,

+ ARM64_INS_LDSETAH,

+ ARM64_INS_LDSETAL,

+ ARM64_INS_LDSETALB,

+ ARM64_INS_LDSETALH,

+ ARM64_INS_LDSETB,

+ ARM64_INS_LDSETH,

+ ARM64_INS_LDSETL,

+ ARM64_INS_LDSETLB,

+ ARM64_INS_LDSETLH,

+ ARM64_INS_LDSMAX,

+ ARM64_INS_LDSMAXA,

+ ARM64_INS_LDSMAXAB,

+ ARM64_INS_LDSMAXAH,

+ ARM64_INS_LDSMAXAL,

+ ARM64_INS_LDSMAXALB,

+ ARM64_INS_LDSMAXALH,

+ ARM64_INS_LDSMAXB,

+ ARM64_INS_LDSMAXH,

+ ARM64_INS_LDSMAXL,

+ ARM64_INS_LDSMAXLB,

+ ARM64_INS_LDSMAXLH,

+ ARM64_INS_LDSMIN,

+ ARM64_INS_LDSMINA,

+ ARM64_INS_LDSMINAB,

+ ARM64_INS_LDSMINAH,

+ ARM64_INS_LDSMINAL,

+ ARM64_INS_LDSMINALB,

+ ARM64_INS_LDSMINALH,

+ ARM64_INS_LDSMINB,

+ ARM64_INS_LDSMINH,

+ ARM64_INS_LDSMINL,

+ ARM64_INS_LDSMINLB,

+ ARM64_INS_LDSMINLH,

+ ARM64_INS_LDTR,

+ ARM64_INS_LDTRB,

+ ARM64_INS_LDTRH,

+ ARM64_INS_LDTRSB,

+ ARM64_INS_LDTRSH,

+ ARM64_INS_LDTRSW,

+ ARM64_INS_LDUMAX,

+ ARM64_INS_LDUMAXA,

+ ARM64_INS_LDUMAXAB,

+ ARM64_INS_LDUMAXAH,

+ ARM64_INS_LDUMAXAL,

+ ARM64_INS_LDUMAXALB,

+ ARM64_INS_LDUMAXALH,

+ ARM64_INS_LDUMAXB,

+ ARM64_INS_LDUMAXH,

+ ARM64_INS_LDUMAXL,

+ ARM64_INS_LDUMAXLB,

+ ARM64_INS_LDUMAXLH,

+ ARM64_INS_LDUMIN,

+ ARM64_INS_LDUMINA,

+ ARM64_INS_LDUMINAB,

+ ARM64_INS_LDUMINAH,

+ ARM64_INS_LDUMINAL,

+ ARM64_INS_LDUMINALB,

+ ARM64_INS_LDUMINALH,

+ ARM64_INS_LDUMINB,

+ ARM64_INS_LDUMINH,

+ ARM64_INS_LDUMINL,

+ ARM64_INS_LDUMINLB,

+ ARM64_INS_LDUMINLH,

+ ARM64_INS_LDUR,

+ ARM64_INS_LDURB,

+ ARM64_INS_LDURH,

+ ARM64_INS_LDURSB,

+ ARM64_INS_LDURSH,

+ ARM64_INS_LDURSW,

+ ARM64_INS_LDXP,

+ ARM64_INS_LDXR,

+ ARM64_INS_LDXRB,

+ ARM64_INS_LDXRH,

+ ARM64_INS_LSL,

+ ARM64_INS_LSLR,

+ ARM64_INS_LSLV,

+ ARM64_INS_LSR,

+ ARM64_INS_LSRR,

+ ARM64_INS_LSRV,

+ ARM64_INS_MAD,

+ ARM64_INS_MADD,

+ ARM64_INS_MLA,

+ ARM64_INS_MLS,

+ ARM64_INS_MNEG,

+ ARM64_INS_MOV,

+ ARM64_INS_MOVI,

+ ARM64_INS_MOVK,

+ ARM64_INS_MOVN,

+ ARM64_INS_MOVPRFX,

+ ARM64_INS_MOVS,

+ ARM64_INS_MOVZ,

+ ARM64_INS_MRS,

+ ARM64_INS_MSB,

+ ARM64_INS_MSR,

+ ARM64_INS_MSUB,

+ ARM64_INS_MUL,

+ ARM64_INS_MVN,

+ ARM64_INS_MVNI,

+ ARM64_INS_NAND,

+ ARM64_INS_NANDS,

+ ARM64_INS_NEG,

+ ARM64_INS_NEGS,

+ ARM64_INS_NGC,

+ ARM64_INS_NGCS,

+ ARM64_INS_NOP,

+ ARM64_INS_NOR,

+ ARM64_INS_NORS,

+ ARM64_INS_NOT,

+ ARM64_INS_NOTS,

+ ARM64_INS_ORN,

+ ARM64_INS_ORNS,

+ ARM64_INS_ORR,

+ ARM64_INS_ORRS,

+ ARM64_INS_ORV,

+ ARM64_INS_PACDA,

+ ARM64_INS_PACDB,

+ ARM64_INS_PACDZA,

+ ARM64_INS_PACDZB,

+ ARM64_INS_PACGA,

+ ARM64_INS_PACIA,

+ ARM64_INS_PACIA1716,

+ ARM64_INS_PACIASP,

+ ARM64_INS_PACIAZ,

+ ARM64_INS_PACIB,

+ ARM64_INS_PACIB1716,

+ ARM64_INS_PACIBSP,

+ ARM64_INS_PACIBZ,

+ ARM64_INS_PACIZA,

+ ARM64_INS_PACIZB,

+ ARM64_INS_PFALSE,

+ ARM64_INS_PFIRST,

+ ARM64_INS_PMUL,

+ ARM64_INS_PMULL,

+ ARM64_INS_PMULL2,

+ ARM64_INS_PNEXT,

+ ARM64_INS_PRFB,

+ ARM64_INS_PRFD,

+ ARM64_INS_PRFH,

+ ARM64_INS_PRFM,

+ ARM64_INS_PRFUM,

+ ARM64_INS_PRFW,

+ ARM64_INS_PSB,

+ ARM64_INS_PTEST,

+ ARM64_INS_PTRUE,

+ ARM64_INS_PTRUES,

+ ARM64_INS_PUNPKHI,

+ ARM64_INS_PUNPKLO,

+ ARM64_INS_RADDHN,

+ ARM64_INS_RADDHN2,

+ ARM64_INS_RAX1,

+ ARM64_INS_RBIT,

+ ARM64_INS_RDFFR,

+ ARM64_INS_RDFFRS,

+ ARM64_INS_RDVL,

+ ARM64_INS_RET,

+ ARM64_INS_RETAA,

+ ARM64_INS_RETAB,

+ ARM64_INS_REV,

+ ARM64_INS_REV16,

+ ARM64_INS_REV32,

+ ARM64_INS_REV64,

+ ARM64_INS_REVB,

+ ARM64_INS_REVH,

+ ARM64_INS_REVW,

+ ARM64_INS_RMIF,

+ ARM64_INS_ROR,

+ ARM64_INS_RORV,

+ ARM64_INS_RSHRN,

+ ARM64_INS_RSHRN2,

+ ARM64_INS_RSUBHN,

+ ARM64_INS_RSUBHN2,

+ ARM64_INS_SABA,

+ ARM64_INS_SABAL,

+ ARM64_INS_SABAL2,

+ ARM64_INS_SABD,

+ ARM64_INS_SABDL,

+ ARM64_INS_SABDL2,

+ ARM64_INS_SADALP,

+ ARM64_INS_SADDL,

+ ARM64_INS_SADDL2,

+ ARM64_INS_SADDLP,

+ ARM64_INS_SADDLV,

+ ARM64_INS_SADDV,

+ ARM64_INS_SADDW,

+ ARM64_INS_SADDW2,

+ ARM64_INS_SBC,

+ ARM64_INS_SBCS,

+ ARM64_INS_SBFM,

+ ARM64_INS_SCVTF,

+ ARM64_INS_SDIV,

+ ARM64_INS_SDIVR,

+ ARM64_INS_SDOT,

+ ARM64_INS_SEL,

+ ARM64_INS_SETF16,

+ ARM64_INS_SETF8,

+ ARM64_INS_SETFFR,

+ ARM64_INS_SEV,

+ ARM64_INS_SEVL,

+ ARM64_INS_SHA1C,

+ ARM64_INS_SHA1H,

+ ARM64_INS_SHA1M,

+ ARM64_INS_SHA1P,

+ ARM64_INS_SHA1SU0,

+ ARM64_INS_SHA1SU1,

+ ARM64_INS_SHA256H,

+ ARM64_INS_SHA256H2,

+ ARM64_INS_SHA256SU0,

+ ARM64_INS_SHA256SU1,

+ ARM64_INS_SHA512H,

+ ARM64_INS_SHA512H2,

+ ARM64_INS_SHA512SU0,

+ ARM64_INS_SHA512SU1,

+ ARM64_INS_SHADD,

+ ARM64_INS_SHL,

+ ARM64_INS_SHLL,

+ ARM64_INS_SHLL2,

+ ARM64_INS_SHRN,

+ ARM64_INS_SHRN2,

+ ARM64_INS_SHSUB,

+ ARM64_INS_SLI,

+ ARM64_INS_SM3PARTW1,

+ ARM64_INS_SM3PARTW2,

+ ARM64_INS_SM3SS1,

+ ARM64_INS_SM3TT1A,

+ ARM64_INS_SM3TT1B,

+ ARM64_INS_SM3TT2A,

+ ARM64_INS_SM3TT2B,

+ ARM64_INS_SM4E,

+ ARM64_INS_SM4EKEY,

+ ARM64_INS_SMADDL,

+ ARM64_INS_SMAX,

+ ARM64_INS_SMAXP,

+ ARM64_INS_SMAXV,

+ ARM64_INS_SMC,

+ ARM64_INS_SMIN,

+ ARM64_INS_SMINP,

+ ARM64_INS_SMINV,

+ ARM64_INS_SMLAL,

+ ARM64_INS_SMLAL2,

+ ARM64_INS_SMLSL,

+ ARM64_INS_SMLSL2,

+ ARM64_INS_SMNEGL,

+ ARM64_INS_SMOV,

+ ARM64_INS_SMSUBL,

+ ARM64_INS_SMULH,

+ ARM64_INS_SMULL,

+ ARM64_INS_SMULL2,

+ ARM64_INS_SPLICE,

+ ARM64_INS_SQABS,

+ ARM64_INS_SQADD,

+ ARM64_INS_SQDECB,

+ ARM64_INS_SQDECD,

+ ARM64_INS_SQDECH,

+ ARM64_INS_SQDECP,

+ ARM64_INS_SQDECW,

+ ARM64_INS_SQDMLAL,

+ ARM64_INS_SQDMLAL2,

+ ARM64_INS_SQDMLSL,

+ ARM64_INS_SQDMLSL2,

+ ARM64_INS_SQDMULH,

+ ARM64_INS_SQDMULL,

+ ARM64_INS_SQDMULL2,

+ ARM64_INS_SQINCB,

+ ARM64_INS_SQINCD,

+ ARM64_INS_SQINCH,

+ ARM64_INS_SQINCP,

+ ARM64_INS_SQINCW,

+ ARM64_INS_SQNEG,

+ ARM64_INS_SQRDMLAH,

+ ARM64_INS_SQRDMLSH,

+ ARM64_INS_SQRDMULH,

+ ARM64_INS_SQRSHL,

+ ARM64_INS_SQRSHRN,

+ ARM64_INS_SQRSHRN2,

+ ARM64_INS_SQRSHRUN,

+ ARM64_INS_SQRSHRUN2,

+ ARM64_INS_SQSHL,

+ ARM64_INS_SQSHLU,

+ ARM64_INS_SQSHRN,

+ ARM64_INS_SQSHRN2,

+ ARM64_INS_SQSHRUN,

+ ARM64_INS_SQSHRUN2,

+ ARM64_INS_SQSUB,

+ ARM64_INS_SQXTN,

+ ARM64_INS_SQXTN2,

+ ARM64_INS_SQXTUN,

+ ARM64_INS_SQXTUN2,

+ ARM64_INS_SRHADD,

+ ARM64_INS_SRI,

+ ARM64_INS_SRSHL,

+ ARM64_INS_SRSHR,

+ ARM64_INS_SRSRA,

+ ARM64_INS_SSHL,

+ ARM64_INS_SSHLL,

+ ARM64_INS_SSHLL2,

+ ARM64_INS_SSHR,

+ ARM64_INS_SSRA,

+ ARM64_INS_SSUBL,

+ ARM64_INS_SSUBL2,

+ ARM64_INS_SSUBW,

+ ARM64_INS_SSUBW2,

+ ARM64_INS_ST1,

+ ARM64_INS_ST1B,

+ ARM64_INS_ST1D,

+ ARM64_INS_ST1H,

+ ARM64_INS_ST1W,

+ ARM64_INS_ST2,

+ ARM64_INS_ST2B,

+ ARM64_INS_ST2D,

+ ARM64_INS_ST2H,

+ ARM64_INS_ST2W,

+ ARM64_INS_ST3,

+ ARM64_INS_ST3B,

+ ARM64_INS_ST3D,

+ ARM64_INS_ST3H,

+ ARM64_INS_ST3W,

+ ARM64_INS_ST4,

+ ARM64_INS_ST4B,

+ ARM64_INS_ST4D,

+ ARM64_INS_ST4H,

+ ARM64_INS_ST4W,

+ ARM64_INS_STADD,

+ ARM64_INS_STADDB,

+ ARM64_INS_STADDH,

+ ARM64_INS_STADDL,

+ ARM64_INS_STADDLB,

+ ARM64_INS_STADDLH,

+ ARM64_INS_STCLR,

+ ARM64_INS_STCLRB,

+ ARM64_INS_STCLRH,

+ ARM64_INS_STCLRL,

+ ARM64_INS_STCLRLB,

+ ARM64_INS_STCLRLH,

+ ARM64_INS_STEOR,

+ ARM64_INS_STEORB,

+ ARM64_INS_STEORH,

+ ARM64_INS_STEORL,

+ ARM64_INS_STEORLB,

+ ARM64_INS_STEORLH,

+ ARM64_INS_STLLR,

+ ARM64_INS_STLLRB,

+ ARM64_INS_STLLRH,

+ ARM64_INS_STLR,

+ ARM64_INS_STLRB,

+ ARM64_INS_STLRH,

+ ARM64_INS_STLUR,

+ ARM64_INS_STLURB,

+ ARM64_INS_STLURH,

+ ARM64_INS_STLXP,

+ ARM64_INS_STLXR,

+ ARM64_INS_STLXRB,

+ ARM64_INS_STLXRH,

+ ARM64_INS_STNP,

+ ARM64_INS_STNT1B,

+ ARM64_INS_STNT1D,

+ ARM64_INS_STNT1H,

+ ARM64_INS_STNT1W,

+ ARM64_INS_STP,

+ ARM64_INS_STR,

+ ARM64_INS_STRB,

+ ARM64_INS_STRH,

+ ARM64_INS_STSET,

+ ARM64_INS_STSETB,

+ ARM64_INS_STSETH,

+ ARM64_INS_STSETL,

+ ARM64_INS_STSETLB,

+ ARM64_INS_STSETLH,

+ ARM64_INS_STSMAX,

+ ARM64_INS_STSMAXB,

+ ARM64_INS_STSMAXH,

+ ARM64_INS_STSMAXL,

+ ARM64_INS_STSMAXLB,

+ ARM64_INS_STSMAXLH,

+ ARM64_INS_STSMIN,

+ ARM64_INS_STSMINB,

+ ARM64_INS_STSMINH,

+ ARM64_INS_STSMINL,

+ ARM64_INS_STSMINLB,

+ ARM64_INS_STSMINLH,

+ ARM64_INS_STTR,

+ ARM64_INS_STTRB,

+ ARM64_INS_STTRH,

+ ARM64_INS_STUMAX,

+ ARM64_INS_STUMAXB,

+ ARM64_INS_STUMAXH,

+ ARM64_INS_STUMAXL,

+ ARM64_INS_STUMAXLB,

+ ARM64_INS_STUMAXLH,

+ ARM64_INS_STUMIN,

+ ARM64_INS_STUMINB,

+ ARM64_INS_STUMINH,

+ ARM64_INS_STUMINL,

+ ARM64_INS_STUMINLB,

+ ARM64_INS_STUMINLH,

+ ARM64_INS_STUR,

+ ARM64_INS_STURB,

+ ARM64_INS_STURH,

+ ARM64_INS_STXP,

+ ARM64_INS_STXR,

+ ARM64_INS_STXRB,

+ ARM64_INS_STXRH,

+ ARM64_INS_SUB,

+ ARM64_INS_SUBHN,

+ ARM64_INS_SUBHN2,

+ ARM64_INS_SUBR,

+ ARM64_INS_SUBS,

+ ARM64_INS_SUNPKHI,

+ ARM64_INS_SUNPKLO,

+ ARM64_INS_SUQADD,

+ ARM64_INS_SVC,

+ ARM64_INS_SWP,

+ ARM64_INS_SWPA,

+ ARM64_INS_SWPAB,

+ ARM64_INS_SWPAH,

+ ARM64_INS_SWPAL,

+ ARM64_INS_SWPALB,

+ ARM64_INS_SWPALH,

+ ARM64_INS_SWPB,

+ ARM64_INS_SWPH,

+ ARM64_INS_SWPL,

+ ARM64_INS_SWPLB,

+ ARM64_INS_SWPLH,

+ ARM64_INS_SXTB,

+ ARM64_INS_SXTH,

+ ARM64_INS_SXTL,

+ ARM64_INS_SXTL2,

+ ARM64_INS_SXTW,

+ ARM64_INS_SYS,

+ ARM64_INS_SYSL,

+ ARM64_INS_TBL,

+ ARM64_INS_TBNZ,

+ ARM64_INS_TBX,

+ ARM64_INS_TBZ,

+ ARM64_INS_TRN1,

+ ARM64_INS_TRN2,

+ ARM64_INS_TSB,

+ ARM64_INS_TST,

+ ARM64_INS_UABA,

+ ARM64_INS_UABAL,

+ ARM64_INS_UABAL2,

+ ARM64_INS_UABD,

+ ARM64_INS_UABDL,

+ ARM64_INS_UABDL2,

+ ARM64_INS_UADALP,

+ ARM64_INS_UADDL,

+ ARM64_INS_UADDL2,

+ ARM64_INS_UADDLP,

+ ARM64_INS_UADDLV,

+ ARM64_INS_UADDV,

+ ARM64_INS_UADDW,

+ ARM64_INS_UADDW2,

+ ARM64_INS_UBFM,

+ ARM64_INS_UCVTF,

+ ARM64_INS_UDIV,

+ ARM64_INS_UDIVR,

+ ARM64_INS_UDOT,

+ ARM64_INS_UHADD,

+ ARM64_INS_UHSUB,

+ ARM64_INS_UMADDL,

+ ARM64_INS_UMAX,

+ ARM64_INS_UMAXP,

+ ARM64_INS_UMAXV,

+ ARM64_INS_UMIN,

+ ARM64_INS_UMINP,

+ ARM64_INS_UMINV,

+ ARM64_INS_UMLAL,

+ ARM64_INS_UMLAL2,

+ ARM64_INS_UMLSL,

+ ARM64_INS_UMLSL2,

+ ARM64_INS_UMNEGL,

+ ARM64_INS_UMOV,

+ ARM64_INS_UMSUBL,

+ ARM64_INS_UMULH,

+ ARM64_INS_UMULL,

+ ARM64_INS_UMULL2,

+ ARM64_INS_UQADD,

+ ARM64_INS_UQDECB,

+ ARM64_INS_UQDECD,

+ ARM64_INS_UQDECH,

+ ARM64_INS_UQDECP,

+ ARM64_INS_UQDECW,

+ ARM64_INS_UQINCB,

+ ARM64_INS_UQINCD,

+ ARM64_INS_UQINCH,

+ ARM64_INS_UQINCP,

+ ARM64_INS_UQINCW,

+ ARM64_INS_UQRSHL,

+ ARM64_INS_UQRSHRN,

+ ARM64_INS_UQRSHRN2,

+ ARM64_INS_UQSHL,

+ ARM64_INS_UQSHRN,

+ ARM64_INS_UQSHRN2,

+ ARM64_INS_UQSUB,

+ ARM64_INS_UQXTN,

+ ARM64_INS_UQXTN2,

+ ARM64_INS_URECPE,

+ ARM64_INS_URHADD,

+ ARM64_INS_URSHL,

+ ARM64_INS_URSHR,

+ ARM64_INS_URSQRTE,

+ ARM64_INS_URSRA,

+ ARM64_INS_USHL,

+ ARM64_INS_USHLL,

+ ARM64_INS_USHLL2,

+ ARM64_INS_USHR,

+ ARM64_INS_USQADD,

+ ARM64_INS_USRA,

+ ARM64_INS_USUBL,

+ ARM64_INS_USUBL2,

+ ARM64_INS_USUBW,

+ ARM64_INS_USUBW2,

+ ARM64_INS_UUNPKHI,

+ ARM64_INS_UUNPKLO,

+ ARM64_INS_UXTB,

+ ARM64_INS_UXTH,

+ ARM64_INS_UXTL,

+ ARM64_INS_UXTL2,

+ ARM64_INS_UXTW,

+ ARM64_INS_UZP1,

+ ARM64_INS_UZP2,

+ ARM64_INS_WFE,

+ ARM64_INS_WFI,

+ ARM64_INS_WHILELE,

+ ARM64_INS_WHILELO,

+ ARM64_INS_WHILELS,

+ ARM64_INS_WHILELT,

+ ARM64_INS_WRFFR,

+ ARM64_INS_XAR,

+ ARM64_INS_XPACD,

+ ARM64_INS_XPACI,

+ ARM64_INS_XPACLRI,

+ ARM64_INS_XTN,

+ ARM64_INS_XTN2,

+ ARM64_INS_YIELD,

+ ARM64_INS_ZIP1,

+ ARM64_INS_ZIP2,

+

+ // alias insn

+ ARM64_INS_SBFIZ,

+ ARM64_INS_UBFIZ,

+ ARM64_INS_SBFX,

+ ARM64_INS_UBFX,

+ ARM64_INS_BFI,

+ ARM64_INS_BFXIL,

+ ARM64_INS_IC,

+ ARM64_INS_DC,

+ ARM64_INS_AT,

+ ARM64_INS_TLBI,

+

+ ARM64_INS_ENDING, // <-- mark the end of the list of insn

+} arm64_insn;

+

+/// Group of ARM64 instructions

+typedef enum arm64_insn_group {

+ ARM64_GRP_INVALID = 0, ///< = CS_GRP_INVALID

+

+ // Generic groups

+ // all jump instructions (conditional+direct+indirect jumps)

+ ARM64_GRP_JUMP, ///< = CS_GRP_JUMP

+ ARM64_GRP_CALL,

+ ARM64_GRP_RET,

+ ARM64_GRP_INT,

+ ARM64_GRP_PRIVILEGE = 6, ///< = CS_GRP_PRIVILEGE

+ ARM64_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE

+ ARM64_GRP_PAC,

+

+ // Architecture-specific groups

+ ARM64_GRP_CRYPTO = 128,

+ ARM64_GRP_FPARMV8,

+ ARM64_GRP_NEON,

+ ARM64_GRP_CRC,

+ ARM64_GRP_AES,

+ ARM64_GRP_DOTPROD,

+ ARM64_GRP_FULLFP16,

+ ARM64_GRP_LSE,

+ ARM64_GRP_RCPC,

+ ARM64_GRP_RDM,

+ ARM64_GRP_SHA2,

+ ARM64_GRP_SHA3,

+ ARM64_GRP_SM4,

+ ARM64_GRP_SVE,

+ ARM64_GRP_V8_1A,

+ ARM64_GRP_V8_3A,

+ ARM64_GRP_V8_4A,

+

+ ARM64_GRP_ENDING, // <-- mark the end of the list of groups

+} arm64_insn_group;

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

+/* Capstone Disassembly Engine */

+/* BPF Backend by david942j <david942j@gmail.com>, 2019 */

+

+#ifndef CAPSTONE_BPF_H

+#define CAPSTONE_BPF_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+#include "platform.h"

+

+#ifdef _MSC_VER

+#pragma warning(disable:4201)

+#endif

+

+/// Operand type for instruction's operands

+typedef enum bpf_op_type {

+ BPF_OP_INVALID = 0,

+

+ BPF_OP_REG,

+ BPF_OP_IMM,

+ BPF_OP_OFF,

+ BPF_OP_MEM,

+ BPF_OP_MMEM, ///< M[k] in cBPF

+ BPF_OP_MSH, ///< corresponds to cBPF's BPF_MSH mode

+ BPF_OP_EXT, ///< cBPF's extension (not eBPF)

+} bpf_op_type;

+

+/// BPF registers

+typedef enum bpf_reg {

+ BPF_REG_INVALID = 0,

+

+ ///< cBPF

+ BPF_REG_A,

+ BPF_REG_X,

+

+ ///< eBPF

+ BPF_REG_R0,

+ BPF_REG_R1,

+ BPF_REG_R2,

+ BPF_REG_R3,

+ BPF_REG_R4,

+ BPF_REG_R5,

+ BPF_REG_R6,

+ BPF_REG_R7,

+ BPF_REG_R8,

+ BPF_REG_R9,

+ BPF_REG_R10,

+

+ BPF_REG_ENDING,

+} bpf_reg;

+

+/// Instruction's operand referring to memory

+/// This is associated with BPF_OP_MEM operand type above

+typedef struct bpf_op_mem {

+ bpf_reg base; ///< base register

+ uint32_t disp; ///< offset value

+} bpf_op_mem;

+

+typedef enum bpf_ext_type {

+ BPF_EXT_INVALID = 0,

+

+ BPF_EXT_LEN,

+} bpf_ext_type;

+

+/// Instruction operand

+typedef struct cs_bpf_op {

+ bpf_op_type type;

+ union {

+ uint8_t reg; ///< register value for REG operand

+ uint64_t imm; ///< immediate value IMM operand

+ uint32_t off; ///< offset value, used in jump & call

+ bpf_op_mem mem; ///< base/disp value for MEM operand

+ /* cBPF only */

+ uint32_t mmem; ///< M[k] in cBPF

+ uint32_t msh; ///< corresponds to cBPF's BPF_MSH mode

+ uint32_t ext; ///< cBPF's extension (not eBPF)

+ };

+

+ /// How is this operand accessed? (READ, WRITE or READ|WRITE)

+ /// This field is combined of cs_ac_type.

+ /// NOTE: this field is irrelevant if engine is compiled in DIET mode.

+ uint8_t access;

+} cs_bpf_op;

+

+/// Instruction structure

+typedef struct cs_bpf {

+ uint8_t op_count;

+ cs_bpf_op operands[4];

+} cs_bpf;

+

+/// BPF instruction

+typedef enum bpf_insn {

+ BPF_INS_INVALID = 0,

+

+ ///< ALU

+ BPF_INS_ADD,

+ BPF_INS_SUB,

+ BPF_INS_MUL,

+ BPF_INS_DIV,

+ BPF_INS_OR,

+ BPF_INS_AND,

+ BPF_INS_LSH,

+ BPF_INS_RSH,

+ BPF_INS_NEG,

+ BPF_INS_MOD,

+ BPF_INS_XOR,

+ BPF_INS_MOV, ///< eBPF only

+ BPF_INS_ARSH, ///< eBPF only

+

+ ///< ALU64, eBPF only

+ BPF_INS_ADD64,

+ BPF_INS_SUB64,

+ BPF_INS_MUL64,

+ BPF_INS_DIV64,

+ BPF_INS_OR64,

+ BPF_INS_AND64,

+ BPF_INS_LSH64,

+ BPF_INS_RSH64,

+ BPF_INS_NEG64,

+ BPF_INS_MOD64,

+ BPF_INS_XOR64,

+ BPF_INS_MOV64,

+ BPF_INS_ARSH64,

+

+ ///< Byteswap, eBPF only

+ BPF_INS_LE16,

+ BPF_INS_LE32,

+ BPF_INS_LE64,

+ BPF_INS_BE16,

+ BPF_INS_BE32,

+ BPF_INS_BE64,

+

+ ///< Load

+ BPF_INS_LDW, ///< eBPF only

+ BPF_INS_LDH,

+ BPF_INS_LDB,

+ BPF_INS_LDDW, ///< eBPF only: load 64-bit imm

+ BPF_INS_LDXW, ///< eBPF only

+ BPF_INS_LDXH, ///< eBPF only

+ BPF_INS_LDXB, ///< eBPF only

+ BPF_INS_LDXDW, ///< eBPF only

+

+ ///< Store

+ BPF_INS_STW, ///< eBPF only

+ BPF_INS_STH, ///< eBPF only

+ BPF_INS_STB, ///< eBPF only

+ BPF_INS_STDW, ///< eBPF only

+ BPF_INS_STXW, ///< eBPF only

+ BPF_INS_STXH, ///< eBPF only

+ BPF_INS_STXB, ///< eBPF only

+ BPF_INS_STXDW, ///< eBPF only

+ BPF_INS_XADDW, ///< eBPF only

+ BPF_INS_XADDDW, ///< eBPF only

+

+ ///< Jump

+ BPF_INS_JMP,

+ BPF_INS_JEQ,

+ BPF_INS_JGT,

+ BPF_INS_JGE,

+ BPF_INS_JSET,

+ BPF_INS_JNE, ///< eBPF only

+ BPF_INS_JSGT, ///< eBPF only

+ BPF_INS_JSGE, ///< eBPF only

+ BPF_INS_CALL, ///< eBPF only

+ BPF_INS_EXIT, ///< eBPF only

+ BPF_INS_JLT, ///< eBPF only

+ BPF_INS_JLE, ///< eBPF only

+ BPF_INS_JSLT, ///< eBPF only

+ BPF_INS_JSLE, ///< eBPF only

+

+ ///< Return, cBPF only

+ BPF_INS_RET,

+

+ ///< Misc, cBPF only

+ BPF_INS_TAX,

+ BPF_INS_TXA,

+

+ BPF_INS_ENDING,

+

+ // alias instructions

+ BPF_INS_LD = BPF_INS_LDW, ///< cBPF only

+ BPF_INS_LDX = BPF_INS_LDXW, ///< cBPF only

+ BPF_INS_ST = BPF_INS_STW, ///< cBPF only

+ BPF_INS_STX = BPF_INS_STXW, ///< cBPF only

+} bpf_insn;

+

+/// Group of BPF instructions

+typedef enum bpf_insn_group {

+ BPF_GRP_INVALID = 0, ///< = CS_GRP_INVALID

+

+ BPF_GRP_LOAD,

+ BPF_GRP_STORE,

+ BPF_GRP_ALU,

+ BPF_GRP_JUMP,

+ BPF_GRP_CALL, ///< eBPF only

+ BPF_GRP_RETURN,

+ BPF_GRP_MISC, ///< cBPF only

+

+ BPF_GRP_ENDING,

+} bpf_insn_group;

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

+#ifndef CAPSTONE_ENGINE_H

+#define CAPSTONE_ENGINE_H

+

+/* Capstone Disassembly Engine */

+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2016 */

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+#include <stdarg.h>

+

+#if defined(CAPSTONE_HAS_OSXKERNEL)

+#include <libkern/libkern.h>

+#else

+#include <stdlib.h>

+#include <stdio.h>

+#endif

+

+#include "platform.h"

+

+#ifdef _MSC_VER

+#pragma warning(disable:4201)

+#pragma warning(disable:4100)

+#define CAPSTONE_API __cdecl

+#ifdef CAPSTONE_SHARED

+#define CAPSTONE_EXPORT __declspec(dllexport)

+#else // defined(CAPSTONE_STATIC)

+#define CAPSTONE_EXPORT

+#endif

+#else

+#define CAPSTONE_API

+#if (defined(__GNUC__) || defined(__IBMC__)) && !defined(CAPSTONE_STATIC)

+#define CAPSTONE_EXPORT __attribute__((visibility("default")))

+#else // defined(CAPSTONE_STATIC)

+#define CAPSTONE_EXPORT

+#endif

+#endif

+

+#if (defined(__GNUC__) || defined(__IBMC__))

+#define CAPSTONE_DEPRECATED __attribute__((deprecated))

+#elif defined(_MSC_VER)

+#define CAPSTONE_DEPRECATED __declspec(deprecated)

+#else

+#pragma message("WARNING: You need to implement CAPSTONE_DEPRECATED for this compiler")

+#define CAPSTONE_DEPRECATED

+#endif

+

+// Capstone API version

+#define CS_API_MAJOR 5

+#define CS_API_MINOR 0

+

+// Version for bleeding edge code of the Github's "next" branch.

+// Use this if you want the absolutely latest development code.

+// This version number will be bumped up whenever we have a new major change.

+#define CS_NEXT_VERSION 5

+

+// Capstone package version

+#define CS_VERSION_MAJOR CS_API_MAJOR

+#define CS_VERSION_MINOR CS_API_MINOR

+#define CS_VERSION_EXTRA 0

+

+/// Macro to create combined version which can be compared to

+/// result of cs_version() API.

+#define CS_MAKE_VERSION(major, minor) ((major << 8) + minor)

+

+/// Maximum size of an instruction mnemonic string.

+#define CS_MNEMONIC_SIZE 32

+

+// Handle using with all API

+typedef size_t csh;

+

+/// Architecture type

+typedef enum cs_arch {

+ CS_ARCH_ARM = 0, ///< ARM architecture (including Thumb, Thumb-2)

+ CS_ARCH_ARM64, ///< ARM-64, also called AArch64

+ CS_ARCH_MIPS, ///< Mips architecture

+ CS_ARCH_X86, ///< X86 architecture (including x86 & x86-64)

+ CS_ARCH_PPC, ///< PowerPC architecture

+ CS_ARCH_SPARC, ///< Sparc architecture

+ CS_ARCH_SYSZ, ///< SystemZ architecture

+ CS_ARCH_XCORE, ///< XCore architecture

+ CS_ARCH_M68K, ///< 68K architecture

+ CS_ARCH_TMS320C64X, ///< TMS320C64x architecture

+ CS_ARCH_M680X, ///< 680X architecture

+ CS_ARCH_EVM, ///< Ethereum architecture

+ CS_ARCH_MOS65XX, ///< MOS65XX architecture (including MOS6502)

+ CS_ARCH_WASM, ///< WebAssembly architecture

+ CS_ARCH_BPF, ///< Berkeley Packet Filter architecture (including eBPF)

+ CS_ARCH_RISCV, ///< RISCV architecture

+ CS_ARCH_MAX,

+ CS_ARCH_ALL = 0xFFFF, // All architectures - for cs_support()

+} cs_arch;

+

+// Support value to verify diet mode of the engine.

+// If cs_support(CS_SUPPORT_DIET) return True, the engine was compiled

+// in diet mode.

+#define CS_SUPPORT_DIET (CS_ARCH_ALL + 1)

+

+// Support value to verify X86 reduce mode of the engine.

+// If cs_support(CS_SUPPORT_X86_REDUCE) return True, the engine was compiled

+// in X86 reduce mode.

+#define CS_SUPPORT_X86_REDUCE (CS_ARCH_ALL + 2)

+

+/// Mode type

+typedef enum cs_mode {

+ CS_MODE_LITTLE_ENDIAN = 0, ///< little-endian mode (default mode)

+ CS_MODE_ARM = 0, ///< 32-bit ARM

+ CS_MODE_16 = 1 << 1, ///< 16-bit mode (X86)

+ CS_MODE_32 = 1 << 2, ///< 32-bit mode (X86)

+ CS_MODE_64 = 1 << 3, ///< 64-bit mode (X86, PPC)

+ CS_MODE_THUMB = 1 << 4, ///< ARM's Thumb mode, including Thumb-2

+ CS_MODE_MCLASS = 1 << 5, ///< ARM's Cortex-M series

+ CS_MODE_V8 = 1 << 6, ///< ARMv8 A32 encodings for ARM

+ CS_MODE_MICRO = 1 << 4, ///< MicroMips mode (MIPS)

+ CS_MODE_MIPS3 = 1 << 5, ///< Mips III ISA

+ CS_MODE_MIPS32R6 = 1 << 6, ///< Mips32r6 ISA

+ CS_MODE_MIPS2 = 1 << 7, ///< Mips II ISA

+ CS_MODE_V9 = 1 << 4, ///< SparcV9 mode (Sparc)

+ CS_MODE_QPX = 1 << 4, ///< Quad Processing eXtensions mode (PPC)

+ CS_MODE_SPE = 1 << 5, ///< Signal Processing Engine mode (PPC)

+ CS_MODE_BOOKE = 1 << 6, ///< Book-E mode (PPC)

+ CS_MODE_M68K_000 = 1 << 1, ///< M68K 68000 mode

+ CS_MODE_M68K_010 = 1 << 2, ///< M68K 68010 mode

+ CS_MODE_M68K_020 = 1 << 3, ///< M68K 68020 mode

+ CS_MODE_M68K_030 = 1 << 4, ///< M68K 68030 mode

+ CS_MODE_M68K_040 = 1 << 5, ///< M68K 68040 mode

+ CS_MODE_M68K_060 = 1 << 6, ///< M68K 68060 mode

+ CS_MODE_BIG_ENDIAN = 1 << 31, ///< big-endian mode

+ CS_MODE_MIPS32 = CS_MODE_32, ///< Mips32 ISA (Mips)

+ CS_MODE_MIPS64 = CS_MODE_64, ///< Mips64 ISA (Mips)

+ CS_MODE_M680X_6301 = 1 << 1, ///< M680X Hitachi 6301,6303 mode

+ CS_MODE_M680X_6309 = 1 << 2, ///< M680X Hitachi 6309 mode

+ CS_MODE_M680X_6800 = 1 << 3, ///< M680X Motorola 6800,6802 mode

+ CS_MODE_M680X_6801 = 1 << 4, ///< M680X Motorola 6801,6803 mode

+ CS_MODE_M680X_6805 = 1 << 5, ///< M680X Motorola/Freescale 6805 mode

+ CS_MODE_M680X_6808 = 1 << 6, ///< M680X Motorola/Freescale/NXP 68HC08 mode

+ CS_MODE_M680X_6809 = 1 << 7, ///< M680X Motorola 6809 mode

+ CS_MODE_M680X_6811 = 1 << 8, ///< M680X Motorola/Freescale/NXP 68HC11 mode

+ CS_MODE_M680X_CPU12 = 1 << 9, ///< M680X Motorola/Freescale/NXP CPU12

+ ///< used on M68HC12/HCS12

+ CS_MODE_M680X_HCS08 = 1 << 10, ///< M680X Freescale/NXP HCS08 mode

+ CS_MODE_BPF_CLASSIC = 0, ///< Classic BPF mode (default)

+ CS_MODE_BPF_EXTENDED = 1 << 0, ///< Extended BPF mode

+ CS_MODE_RISCV32 = 1 << 0, ///< RISCV RV32G

+ CS_MODE_RISCV64 = 1 << 1, ///< RISCV RV64G

+ CS_MODE_RISCVC = 1 << 2, ///< RISCV compressed instructure mode

+ CS_MODE_MOS65XX_6502 = 1 << 1, ///< MOS65XXX MOS 6502

+ CS_MODE_MOS65XX_65C02 = 1 << 2, ///< MOS65XXX WDC 65c02

+ CS_MODE_MOS65XX_W65C02 = 1 << 3, ///< MOS65XXX WDC W65c02

+ CS_MODE_MOS65XX_65816 = 1 << 4, ///< MOS65XXX WDC 65816, 8-bit m/x

+ CS_MODE_MOS65XX_65816_LONG_M = (1 << 5), ///< MOS65XXX WDC 65816, 16-bit m, 8-bit x

+ CS_MODE_MOS65XX_65816_LONG_X = (1 << 6), ///< MOS65XXX WDC 65816, 8-bit m, 16-bit x

+ CS_MODE_MOS65XX_65816_LONG_MX = CS_MODE_MOS65XX_65816_LONG_M | CS_MODE_MOS65XX_65816_LONG_X,

+} cs_mode;

+

+typedef void* (CAPSTONE_API *cs_malloc_t)(size_t size);

+typedef void* (CAPSTONE_API *cs_calloc_t)(size_t nmemb, size_t size);

+typedef void* (CAPSTONE_API *cs_realloc_t)(void *ptr, size_t size);

+typedef void (CAPSTONE_API *cs_free_t)(void *ptr);

+typedef int (CAPSTONE_API *cs_vsnprintf_t)(char *str, size_t size, const char *format, va_list ap);

+

+

+/// User-defined dynamic memory related functions: malloc/calloc/realloc/free/vsnprintf()

+/// By default, Capstone uses system's malloc(), calloc(), realloc(), free() & vsnprintf().

+typedef struct cs_opt_mem {

+ cs_malloc_t malloc;

+ cs_calloc_t calloc;

+ cs_realloc_t realloc;

+ cs_free_t free;

+ cs_vsnprintf_t vsnprintf;

+} cs_opt_mem;

+

+/// Customize mnemonic for instructions with alternative name.

+/// To reset existing customized instruction to its default mnemonic,

+/// call cs_option(CS_OPT_MNEMONIC) again with the same @id and NULL value

+/// for @mnemonic.

+typedef struct cs_opt_mnem {

+ /// ID of instruction to be customized.

+ unsigned int id;

+ /// Customized instruction mnemonic.

+ const char *mnemonic;

+} cs_opt_mnem;

+

+/// Runtime option for the disassembled engine

+typedef enum cs_opt_type {

+ CS_OPT_INVALID = 0, ///< No option specified

+ CS_OPT_SYNTAX, ///< Assembly output syntax

+ CS_OPT_DETAIL, ///< Break down instruction structure into details

+ CS_OPT_MODE, ///< Change engine's mode at run-time

+ CS_OPT_MEM, ///< User-defined dynamic memory related functions

+ CS_OPT_SKIPDATA, ///< Skip data when disassembling. Then engine is in SKIPDATA mode.

+ CS_OPT_SKIPDATA_SETUP, ///< Setup user-defined function for SKIPDATA option

+ CS_OPT_MNEMONIC, ///< Customize instruction mnemonic

+ CS_OPT_UNSIGNED, ///< print immediate operands in unsigned form

+} cs_opt_type;

+

+/// Runtime option value (associated with option type above)

+typedef enum cs_opt_value {

+ CS_OPT_OFF = 0, ///< Turn OFF an option - default for CS_OPT_DETAIL, CS_OPT_SKIPDATA, CS_OPT_UNSIGNED.

+ CS_OPT_ON = 3, ///< Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA).

+ CS_OPT_SYNTAX_DEFAULT = 0, ///< Default asm syntax (CS_OPT_SYNTAX).

+ CS_OPT_SYNTAX_INTEL, ///< X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX).

+ CS_OPT_SYNTAX_ATT, ///< X86 ATT asm syntax (CS_OPT_SYNTAX).

+ CS_OPT_SYNTAX_NOREGNAME, ///< Prints register name with only number (CS_OPT_SYNTAX)

+ CS_OPT_SYNTAX_MASM, ///< X86 Intel Masm syntax (CS_OPT_SYNTAX).

+ CS_OPT_SYNTAX_MOTOROLA, ///< MOS65XX use $ as hex prefix

+} cs_opt_value;

+

+/// Common instruction operand types - to be consistent across all architectures.

+typedef enum cs_op_type {

+ CS_OP_INVALID = 0, ///< uninitialized/invalid operand.

+ CS_OP_REG, ///< Register operand.

+ CS_OP_IMM, ///< Immediate operand.

+ CS_OP_MEM, ///< Memory operand.

+ CS_OP_FP, ///< Floating-Point operand.

+} cs_op_type;

+

+/// Common instruction operand access types - to be consistent across all architectures.

+/// It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE

+typedef enum cs_ac_type {

+ CS_AC_INVALID = 0, ///< Uninitialized/invalid access type.

+ CS_AC_READ = 1 << 0, ///< Operand read from memory or register.

+ CS_AC_WRITE = 1 << 1, ///< Operand write to memory or register.

+} cs_ac_type;

+

+/// Common instruction groups - to be consistent across all architectures.

+typedef enum cs_group_type {

+ CS_GRP_INVALID = 0, ///< uninitialized/invalid group.

+ CS_GRP_JUMP, ///< all jump instructions (conditional+direct+indirect jumps)

+ CS_GRP_CALL, ///< all call instructions

+ CS_GRP_RET, ///< all return instructions

+ CS_GRP_INT, ///< all interrupt instructions (int+syscall)

+ CS_GRP_IRET, ///< all interrupt return instructions

+ CS_GRP_PRIVILEGE, ///< all privileged instructions

+ CS_GRP_BRANCH_RELATIVE, ///< all relative branching instructions

+} cs_group_type;

+

+/**

+ User-defined callback function for SKIPDATA option.

+ See tests/test_skipdata.c for sample code demonstrating this API.

+

+ @code: the input buffer containing code to be disassembled.

+ This is the same buffer passed to cs_disasm().

+ @code_size: size (in bytes) of the above @code buffer.

+ @offset: the position of the currently-examining byte in the input

+ buffer @code mentioned above.

+ @user_data: user-data passed to cs_option() via @user_data field in

+ cs_opt_skipdata struct below.

+

+ @return: return number of bytes to skip, or 0 to immediately stop disassembling.

+*/

+typedef size_t (CAPSTONE_API *cs_skipdata_cb_t)(const uint8_t *code, size_t code_size, size_t offset, void *user_data);

+

+/// User-customized setup for SKIPDATA option

+typedef struct cs_opt_skipdata {

+ /// Capstone considers data to skip as special "instructions".

+ /// User can specify the string for this instruction's "mnemonic" here.

+ /// By default (if @mnemonic is NULL), Capstone use ".byte".

+ const char *mnemonic;

+

+ /// User-defined callback function to be called when Capstone hits data.

+ /// If the returned value from this callback is positive (>0), Capstone

+ /// will skip exactly that number of bytes & continue. Otherwise, if

+ /// the callback returns 0, Capstone stops disassembling and returns

+ /// immediately from cs_disasm()

+ /// NOTE: if this callback pointer is NULL, Capstone would skip a number

+ /// of bytes depending on architectures, as following:

+ /// Arm: 2 bytes (Thumb mode) or 4 bytes.

+ /// Arm64: 4 bytes.

+ /// Mips: 4 bytes.

+ /// M680x: 1 byte.

+ /// PowerPC: 4 bytes.

+ /// Sparc: 4 bytes.

+ /// SystemZ: 2 bytes.

+ /// X86: 1 bytes.

+ /// XCore: 2 bytes.

+ /// EVM: 1 bytes.

+ /// RISCV: 4 bytes.

+ /// WASM: 1 bytes.

+ /// MOS65XX: 1 bytes.

+ /// BPF: 8 bytes.

+ cs_skipdata_cb_t callback; // default value is NULL

+

+ /// User-defined data to be passed to @callback function pointer.

+ void *user_data;

+} cs_opt_skipdata;

+

+

+#include "arm.h"

+#include "arm64.h"

+#include "m68k.h"

+#include "mips.h"

+#include "ppc.h"

+#include "sparc.h"

+#include "systemz.h"

+#include "x86.h"

+#include "xcore.h"

+#include "tms320c64x.h"

+#include "m680x.h"

+#include "evm.h"

+#include "riscv.h"

+#include "wasm.h"

+#include "mos65xx.h"

+#include "bpf.h"

+

+/// NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON

+/// Initialized as memset(., 0, offsetof(cs_detail, ARCH)+sizeof(cs_ARCH))

+/// by ARCH_getInstruction in arch/ARCH/ARCHDisassembler.c

+/// if cs_detail changes, in particular if a field is added after the union,

+/// then update arch/ARCH/ARCHDisassembler.c accordingly

+typedef struct cs_detail {

+ uint16_t regs_read[16]; ///< list of implicit registers read by this insn

+ uint8_t regs_read_count; ///< number of implicit registers read by this insn

+

+ uint16_t regs_write[20]; ///< list of implicit registers modified by this insn

+ uint8_t regs_write_count; ///< number of implicit registers modified by this insn

+

+ uint8_t groups[8]; ///< list of group this instruction belong to

+ uint8_t groups_count; ///< number of groups this insn belongs to

+

+ /// Architecture-specific instruction info

+ union {

+ cs_x86 x86; ///< X86 architecture, including 16-bit, 32-bit & 64-bit mode

+ cs_arm64 arm64; ///< ARM64 architecture (aka AArch64)

+ cs_arm arm; ///< ARM architecture (including Thumb/Thumb2)

+ cs_m68k m68k; ///< M68K architecture

+ cs_mips mips; ///< MIPS architecture

+ cs_ppc ppc; ///< PowerPC architecture

+ cs_sparc sparc; ///< Sparc architecture

+ cs_sysz sysz; ///< SystemZ architecture

+ cs_xcore xcore; ///< XCore architecture

+ cs_tms320c64x tms320c64x; ///< TMS320C64x architecture

+ cs_m680x m680x; ///< M680X architecture

+ cs_evm evm; ///< Ethereum architecture

+ cs_mos65xx mos65xx; ///< MOS65XX architecture (including MOS6502)

+ cs_wasm wasm; ///< Web Assembly architecture

+ cs_bpf bpf; ///< Berkeley Packet Filter architecture (including eBPF)

+ cs_riscv riscv; ///< RISCV architecture

+ };

+} cs_detail;

+

+/// Detail information of disassembled instruction

+typedef struct cs_insn {

+ /// Instruction ID (basically a numeric ID for the instruction mnemonic)

+ /// Find the instruction id in the '[ARCH]_insn' enum in the header file

+ /// of corresponding architecture, such as 'arm_insn' in arm.h for ARM,

+ /// 'x86_insn' in x86.h for X86, etc...

+ /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF

+ /// NOTE: in Skipdata mode, "data" instruction has 0 for this id field.

+ unsigned int id;

+

+ /// Address (EIP) of this instruction

+ /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF

+ uint64_t address;

+

+ /// Size of this instruction

+ /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF

+ uint16_t size;

+

+ /// Machine bytes of this instruction, with number of bytes indicated by @size above

+ /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF

+ uint8_t bytes[24];

+

+ /// Ascii text of instruction mnemonic

+ /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF

+ char mnemonic[CS_MNEMONIC_SIZE];

+

+ /// Ascii text of instruction operands

+ /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF

+ char op_str[160];

+

+ /// Pointer to cs_detail.

+ /// NOTE: detail pointer is only valid when both requirements below are met:

+ /// (1) CS_OP_DETAIL = CS_OPT_ON

+ /// (2) Engine is not in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON)

+ ///

+ /// NOTE 2: when in Skipdata mode, or when detail mode is OFF, even if this pointer

+ /// is not NULL, its content is still irrelevant.

+ cs_detail *detail;

+} cs_insn;

+

+

+/// Calculate the offset of a disassembled instruction in its buffer, given its position

+/// in its array of disassembled insn

+/// NOTE: this macro works with position (>=1), not index

+#define CS_INSN_OFFSET(insns, post) (insns[post - 1].address - insns[0].address)

+

+

+/// All type of errors encountered by Capstone API.

+/// These are values returned by cs_errno()

+typedef enum cs_err {

+ CS_ERR_OK = 0, ///< No error: everything was fine

+ CS_ERR_MEM, ///< Out-Of-Memory error: cs_open(), cs_disasm(), cs_disasm_iter()

+ CS_ERR_ARCH, ///< Unsupported architecture: cs_open()

+ CS_ERR_HANDLE, ///< Invalid handle: cs_op_count(), cs_op_index()

+ CS_ERR_CSH, ///< Invalid csh argument: cs_close(), cs_errno(), cs_option()

+ CS_ERR_MODE, ///< Invalid/unsupported mode: cs_open()

+ CS_ERR_OPTION, ///< Invalid/unsupported option: cs_option()

+ CS_ERR_DETAIL, ///< Information is unavailable because detail option is OFF

+ CS_ERR_MEMSETUP, ///< Dynamic memory management uninitialized (see CS_OPT_MEM)

+ CS_ERR_VERSION, ///< Unsupported version (bindings)

+ CS_ERR_DIET, ///< Access irrelevant data in "diet" engine

+ CS_ERR_SKIPDATA, ///< Access irrelevant data for "data" instruction in SKIPDATA mode

+ CS_ERR_X86_ATT, ///< X86 AT&T syntax is unsupported (opt-out at compile time)

+ CS_ERR_X86_INTEL, ///< X86 Intel syntax is unsupported (opt-out at compile time)

+ CS_ERR_X86_MASM, ///< X86 Masm syntax is unsupported (opt-out at compile time)

+} cs_err;

+

+/**

+ Return combined API version & major and minor version numbers.

+

+ @major: major number of API version

+ @minor: minor number of API version

+

+ @return hexical number as (major << 8 | minor), which encodes both

+ major & minor versions.

+ NOTE: This returned value can be compared with version number made

+ with macro CS_MAKE_VERSION

+

+ For example, second API version would return 1 in @major, and 1 in @minor

+ The return value would be 0x0101

+

+ NOTE: if you only care about returned value, but not major and minor values,

+ set both @major & @minor arguments to NULL.

+*/

+CAPSTONE_EXPORT

+unsigned int CAPSTONE_API cs_version(int *major, int *minor);

+

+

+/**

+ This API can be used to either ask for archs supported by this library,

+ or check to see if the library was compile with 'diet' option (or called

+ in 'diet' mode).

+

+ To check if a particular arch is supported by this library, set @query to

+ arch mode (CS_ARCH_* value).

+ To verify if this library supports all the archs, use CS_ARCH_ALL.

+

+ To check if this library is in 'diet' mode, set @query to CS_SUPPORT_DIET.

+

+ @return True if this library supports the given arch, or in 'diet' mode.

+*/

+CAPSTONE_EXPORT

+bool CAPSTONE_API cs_support(int query);

+

+/**

+ Initialize CS handle: this must be done before any usage of CS.

+

+ @arch: architecture type (CS_ARCH_*)

+ @mode: hardware mode. This is combined of CS_MODE_*

+ @handle: pointer to handle, which will be updated at return time

+

+ @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum

+ for detailed error).

+*/

+CAPSTONE_EXPORT

+cs_err CAPSTONE_API cs_open(cs_arch arch, cs_mode mode, csh *handle);

+

+/**

+ Close CS handle: MUST do to release the handle when it is not used anymore.

+ NOTE: this must be only called when there is no longer usage of Capstone,

+ not even access to cs_insn array. The reason is the this API releases some

+ cached memory, thus access to any Capstone API after cs_close() might crash

+ your application.

+

+ In fact,this API invalidate @handle by ZERO out its value (i.e *handle = 0).

+

+ @handle: pointer to a handle returned by cs_open()

+

+ @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum

+ for detailed error).

+*/

+CAPSTONE_EXPORT

+cs_err CAPSTONE_API cs_close(csh *handle);

+

+/**

+ Set option for disassembling engine at runtime

+

+ @handle: handle returned by cs_open()

+ @type: type of option to be set

+ @value: option value corresponding with @type

+

+ @return: CS_ERR_OK on success, or other value on failure.

+ Refer to cs_err enum for detailed error.

+

+ NOTE: in the case of CS_OPT_MEM, handle's value can be anything,

+ so that cs_option(handle, CS_OPT_MEM, value) can (i.e must) be called

+ even before cs_open()

+*/

+CAPSTONE_EXPORT

+cs_err CAPSTONE_API cs_option(csh handle, cs_opt_type type, size_t value);

+

+/**

+ Report the last error number when some API function fail.

+ Like glibc's errno, cs_errno might not retain its old value once accessed.

+

+ @handle: handle returned by cs_open()

+

+ @return: error code of cs_err enum type (CS_ERR_*, see above)

+*/

+CAPSTONE_EXPORT

+cs_err CAPSTONE_API cs_errno(csh handle);

+

+

+/**

+ Return a string describing given error code.

+

+ @code: error code (see CS_ERR_* above)

+

+ @return: returns a pointer to a string that describes the error code

+ passed in the argument @code

+*/

+CAPSTONE_EXPORT

+const char * CAPSTONE_API cs_strerror(cs_err code);

+

+/**

+ Disassemble binary code, given the code buffer, size, address and number

+ of instructions to be decoded.

+ This API dynamically allocate memory to contain disassembled instruction.

+ Resulting instructions will be put into @*insn

+

+ NOTE 1: this API will automatically determine memory needed to contain

+ output disassembled instructions in @insn.

+

+ NOTE 2: caller must free the allocated memory itself to avoid memory leaking.

+

+ NOTE 3: for system with scarce memory to be dynamically allocated such as

+ OS kernel or firmware, the API cs_disasm_iter() might be a better choice than

+ cs_disasm(). The reason is that with cs_disasm(), based on limited available

+ memory, we have to calculate in advance how many instructions to be disassembled,

+ which complicates things. This is especially troublesome for the case @count=0,

+ when cs_disasm() runs uncontrollably (until either end of input buffer, or

+ when it encounters an invalid instruction).

+

+ @handle: handle returned by cs_open()

+ @code: buffer containing raw binary code to be disassembled.

+ @code_size: size of the above code buffer.

+ @address: address of the first instruction in given raw code buffer.

+ @insn: array of instructions filled in by this API.

+ NOTE: @insn will be allocated by this function, and should be freed

+ with cs_free() API.

+ @count: number of instructions to be disassembled, or 0 to get all of them

+

+ @return: the number of successfully disassembled instructions,

+ or 0 if this function failed to disassemble the given code

+

+ On failure, call cs_errno() for error code.

+*/

+CAPSTONE_EXPORT

+size_t CAPSTONE_API cs_disasm(csh handle,

+ const uint8_t *code, size_t code_size,

+ uint64_t address,

+ size_t count,

+ cs_insn **insn);

+

+/**

+ Free memory allocated by cs_malloc() or cs_disasm() (argument @insn)

+

+ @insn: pointer returned by @insn argument in cs_disasm() or cs_malloc()

+ @count: number of cs_insn structures returned by cs_disasm(), or 1

+ to free memory allocated by cs_malloc().

+*/

+CAPSTONE_EXPORT

+void CAPSTONE_API cs_free(cs_insn *insn, size_t count);

+

+

+/**

+ Allocate memory for 1 instruction to be used by cs_disasm_iter().

+

+ @handle: handle returned by cs_open()

+

+ NOTE: when no longer in use, you can reclaim the memory allocated for

+ this instruction with cs_free(insn, 1)

+*/

+CAPSTONE_EXPORT

+cs_insn * CAPSTONE_API cs_malloc(csh handle);

+

+/**

+ Fast API to disassemble binary code, given the code buffer, size, address

+ and number of instructions to be decoded.

+ This API puts the resulting instruction into a given cache in @insn.

+ See tests/test_iter.c for sample code demonstrating this API.

+

+ NOTE 1: this API will update @code, @size & @address to point to the next

+ instruction in the input buffer. Therefore, it is convenient to use

+ cs_disasm_iter() inside a loop to quickly iterate all the instructions.

+ While decoding one instruction at a time can also be achieved with

+ cs_disasm(count=1), some benchmarks shown that cs_disasm_iter() can be 30%

+ faster on random input.

+

+ NOTE 2: the cache in @insn can be created with cs_malloc() API.

+

+ NOTE 3: for system with scarce memory to be dynamically allocated such as

+ OS kernel or firmware, this API is recommended over cs_disasm(), which

+ allocates memory based on the number of instructions to be disassembled.

+ The reason is that with cs_disasm(), based on limited available memory,

+ we have to calculate in advance how many instructions to be disassembled,

+ which complicates things. This is especially troublesome for the case

+ @count=0, when cs_disasm() runs uncontrollably (until either end of input

+ buffer, or when it encounters an invalid instruction).

+

+ @handle: handle returned by cs_open()

+ @code: buffer containing raw binary code to be disassembled

+ @size: size of above code

+ @address: address of the first insn in given raw code buffer

+ @insn: pointer to instruction to be filled in by this API.

+

+ @return: true if this API successfully decode 1 instruction,

+ or false otherwise.

+

+ On failure, call cs_errno() for error code.

+*/

+CAPSTONE_EXPORT

+bool CAPSTONE_API cs_disasm_iter(csh handle,

+ const uint8_t **code, size_t *size,

+ uint64_t *address, cs_insn *insn);

+

+/**

+ Return friendly name of register in a string.

+ Find the instruction id from header file of corresponding architecture (arm.h for ARM,

+ x86.h for X86, ...)

+

+ WARN: when in 'diet' mode, this API is irrelevant because engine does not

+ store register name.

+

+ @handle: handle returned by cs_open()

+ @reg_id: register id

+

+ @return: string name of the register, or NULL if @reg_id is invalid.

+*/

+CAPSTONE_EXPORT

+const char * CAPSTONE_API cs_reg_name(csh handle, unsigned int reg_id);

+

+/**

+ Return friendly name of an instruction in a string.

+ Find the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)

+

+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not

+ store instruction name.

+

+ @handle: handle returned by cs_open()

+ @insn_id: instruction id

+

+ @return: string name of the instruction, or NULL if @insn_id is invalid.

+*/

+CAPSTONE_EXPORT

+const char * CAPSTONE_API cs_insn_name(csh handle, unsigned int insn_id);

+

+/**

+ Return friendly name of a group id (that an instruction can belong to)

+ Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)

+

+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not

+ store group name.

+

+ @handle: handle returned by cs_open()

+ @group_id: group id

+

+ @return: string name of the group, or NULL if @group_id is invalid.

+*/

+CAPSTONE_EXPORT

+const char * CAPSTONE_API cs_group_name(csh handle, unsigned int group_id);

+

+/**

+ Check if a disassembled instruction belong to a particular group.

+ Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)

+ Internally, this simply verifies if @group_id matches any member of insn->groups array.

+

+ NOTE: this API is only valid when detail option is ON (which is OFF by default).

+

+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not

+ update @groups array.

+

+ @handle: handle returned by cs_open()

+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()

+ @group_id: group that you want to check if this instruction belong to.

+

+ @return: true if this instruction indeed belongs to the given group, or false otherwise.

+*/

+CAPSTONE_EXPORT

+bool CAPSTONE_API cs_insn_group(csh handle, const cs_insn *insn, unsigned int group_id);

+

+/**

+ Check if a disassembled instruction IMPLICITLY used a particular register.

+ Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)

+ Internally, this simply verifies if @reg_id matches any member of insn->regs_read array.

+

+ NOTE: this API is only valid when detail option is ON (which is OFF by default)

+

+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not

+ update @regs_read array.

+

+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()

+ @reg_id: register that you want to check if this instruction used it.

+

+ @return: true if this instruction indeed implicitly used the given register, or false otherwise.

+*/

+CAPSTONE_EXPORT

+bool CAPSTONE_API cs_reg_read(csh handle, const cs_insn *insn, unsigned int reg_id);

+

+/**

+ Check if a disassembled instruction IMPLICITLY modified a particular register.

+ Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)

+ Internally, this simply verifies if @reg_id matches any member of insn->regs_write array.

+

+ NOTE: this API is only valid when detail option is ON (which is OFF by default)

+

+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not

+ update @regs_write array.

+

+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()

+ @reg_id: register that you want to check if this instruction modified it.

+

+ @return: true if this instruction indeed implicitly modified the given register, or false otherwise.

+*/

+CAPSTONE_EXPORT

+bool CAPSTONE_API cs_reg_write(csh handle, const cs_insn *insn, unsigned int reg_id);

+

+/**

+ Count the number of operands of a given type.

+ Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)

+

+ NOTE: this API is only valid when detail option is ON (which is OFF by default)

+

+ @handle: handle returned by cs_open()

+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()

+ @op_type: Operand type to be found.

+

+ @return: number of operands of given type @op_type in instruction @insn,

+ or -1 on failure.

+*/

+CAPSTONE_EXPORT

+int CAPSTONE_API cs_op_count(csh handle, const cs_insn *insn, unsigned int op_type);

+

+/**

+ Retrieve the position of operand of given type in <arch>.operands[] array.

+ Later, the operand can be accessed using the returned position.

+ Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)

+

+ NOTE: this API is only valid when detail option is ON (which is OFF by default)

+

+ @handle: handle returned by cs_open()

+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()

+ @op_type: Operand type to be found.

+ @position: position of the operand to be found. This must be in the range

+ [1, cs_op_count(handle, insn, op_type)]

+

+ @return: index of operand of given type @op_type in <arch>.operands[] array

+ in instruction @insn, or -1 on failure.

+*/

+CAPSTONE_EXPORT

+int CAPSTONE_API cs_op_index(csh handle, const cs_insn *insn, unsigned int op_type,

+ unsigned int position);

+

+/// Type of array to keep the list of registers

+typedef uint16_t cs_regs[64];

+

+/**

+ Retrieve all the registers accessed by an instruction, either explicitly or

+ implicitly.

+

+ WARN: when in 'diet' mode, this API is irrelevant because engine does not

+ store registers.

+

+ @handle: handle returned by cs_open()

+ @insn: disassembled instruction structure returned from cs_disasm() or cs_disasm_iter()

+ @regs_read: on return, this array contains all registers read by instruction.

+ @regs_read_count: number of registers kept inside @regs_read array.

+ @regs_write: on return, this array contains all registers written by instruction.

+ @regs_write_count: number of registers kept inside @regs_write array.

+

+ @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum

+ for detailed error).

+*/

+CAPSTONE_EXPORT

+cs_err CAPSTONE_API cs_regs_access(csh handle, const cs_insn *insn,

+ cs_regs regs_read, uint8_t *regs_read_count,

+ cs_regs regs_write, uint8_t *regs_write_count);

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

+#ifndef CAPSTONE_EVM_H

+#define CAPSTONE_EVM_H

+

+/* Capstone Disassembly Engine */

+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2018 */

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+#include "platform.h"

+

+#ifdef _MSC_VER

+#pragma warning(disable:4201)

+#endif

+

+/// Instruction structure

+typedef struct cs_evm {

+ unsigned char pop; ///< number of items popped from the stack

+ unsigned char push; ///< number of items pushed into the stack

+ unsigned int fee; ///< gas fee for the instruction

+} cs_evm;

+

+/// EVM instruction

+typedef enum evm_insn {

+ EVM_INS_STOP = 0,

+ EVM_INS_ADD = 1,

+ EVM_INS_MUL = 2,

+ EVM_INS_SUB = 3,

+ EVM_INS_DIV = 4,

+ EVM_INS_SDIV = 5,

+ EVM_INS_MOD = 6,

+ EVM_INS_SMOD = 7,

+ EVM_INS_ADDMOD = 8,

+ EVM_INS_MULMOD = 9,

+ EVM_INS_EXP = 10,

+ EVM_INS_SIGNEXTEND = 11,

+ EVM_INS_LT = 16,

+ EVM_INS_GT = 17,

+ EVM_INS_SLT = 18,

+ EVM_INS_SGT = 19,

+ EVM_INS_EQ = 20,

+ EVM_INS_ISZERO = 21,

+ EVM_INS_AND = 22,

+ EVM_INS_OR = 23,

+ EVM_INS_XOR = 24,

+ EVM_INS_NOT = 25,

+ EVM_INS_BYTE = 26,

+ EVM_INS_SHA3 = 32,

+ EVM_INS_ADDRESS = 48,

+ EVM_INS_BALANCE = 49,

+ EVM_INS_ORIGIN = 50,

+ EVM_INS_CALLER = 51,

+ EVM_INS_CALLVALUE = 52,

+ EVM_INS_CALLDATALOAD = 53,

+ EVM_INS_CALLDATASIZE = 54,

+ EVM_INS_CALLDATACOPY = 55,

+ EVM_INS_CODESIZE = 56,

+ EVM_INS_CODECOPY = 57,

+ EVM_INS_GASPRICE = 58,

+ EVM_INS_EXTCODESIZE = 59,

+ EVM_INS_EXTCODECOPY = 60,

+ EVM_INS_RETURNDATASIZE = 61,

+ EVM_INS_RETURNDATACOPY = 62,

+ EVM_INS_BLOCKHASH = 64,

+ EVM_INS_COINBASE = 65,

+ EVM_INS_TIMESTAMP = 66,

+ EVM_INS_NUMBER = 67,

+ EVM_INS_DIFFICULTY = 68,

+ EVM_INS_GASLIMIT = 69,

+ EVM_INS_POP = 80,

+ EVM_INS_MLOAD = 81,

+ EVM_INS_MSTORE = 82,

+ EVM_INS_MSTORE8 = 83,

+ EVM_INS_SLOAD = 84,

+ EVM_INS_SSTORE = 85,

+ EVM_INS_JUMP = 86,

+ EVM_INS_JUMPI = 87,

+ EVM_INS_PC = 88,

+ EVM_INS_MSIZE = 89,

+ EVM_INS_GAS = 90,

+ EVM_INS_JUMPDEST = 91,

+ EVM_INS_PUSH1 = 96,

+ EVM_INS_PUSH2 = 97,

+ EVM_INS_PUSH3 = 98,

+ EVM_INS_PUSH4 = 99,

+ EVM_INS_PUSH5 = 100,

+ EVM_INS_PUSH6 = 101,

+ EVM_INS_PUSH7 = 102,

+ EVM_INS_PUSH8 = 103,

+ EVM_INS_PUSH9 = 104,

+ EVM_INS_PUSH10 = 105,

+ EVM_INS_PUSH11 = 106,

+ EVM_INS_PUSH12 = 107,

+ EVM_INS_PUSH13 = 108,

+ EVM_INS_PUSH14 = 109,

+ EVM_INS_PUSH15 = 110,

+ EVM_INS_PUSH16 = 111,

+ EVM_INS_PUSH17 = 112,

+ EVM_INS_PUSH18 = 113,

+ EVM_INS_PUSH19 = 114,

+ EVM_INS_PUSH20 = 115,

+ EVM_INS_PUSH21 = 116,

+ EVM_INS_PUSH22 = 117,

+ EVM_INS_PUSH23 = 118,

+ EVM_INS_PUSH24 = 119,

+ EVM_INS_PUSH25 = 120,

+ EVM_INS_PUSH26 = 121,

+ EVM_INS_PUSH27 = 122,

+ EVM_INS_PUSH28 = 123,

+ EVM_INS_PUSH29 = 124,

+ EVM_INS_PUSH30 = 125,

+ EVM_INS_PUSH31 = 126,

+ EVM_INS_PUSH32 = 127,

+ EVM_INS_DUP1 = 128,

+ EVM_INS_DUP2 = 129,

+ EVM_INS_DUP3 = 130,

+ EVM_INS_DUP4 = 131,

+ EVM_INS_DUP5 = 132,

+ EVM_INS_DUP6 = 133,

+ EVM_INS_DUP7 = 134,

+ EVM_INS_DUP8 = 135,

+ EVM_INS_DUP9 = 136,

+ EVM_INS_DUP10 = 137,

+ EVM_INS_DUP11 = 138,

+ EVM_INS_DUP12 = 139,

+ EVM_INS_DUP13 = 140,

+ EVM_INS_DUP14 = 141,

+ EVM_INS_DUP15 = 142,

+ EVM_INS_DUP16 = 143,

+ EVM_INS_SWAP1 = 144,

+ EVM_INS_SWAP2 = 145,

+ EVM_INS_SWAP3 = 146,

+ EVM_INS_SWAP4 = 147,

+ EVM_INS_SWAP5 = 148,

+ EVM_INS_SWAP6 = 149,

+ EVM_INS_SWAP7 = 150,

+ EVM_INS_SWAP8 = 151,

+ EVM_INS_SWAP9 = 152,

+ EVM_INS_SWAP10 = 153,

+ EVM_INS_SWAP11 = 154,

+ EVM_INS_SWAP12 = 155,

+ EVM_INS_SWAP13 = 156,

+ EVM_INS_SWAP14 = 157,

+ EVM_INS_SWAP15 = 158,

+ EVM_INS_SWAP16 = 159,

+ EVM_INS_LOG0 = 160,

+ EVM_INS_LOG1 = 161,

+ EVM_INS_LOG2 = 162,

+ EVM_INS_LOG3 = 163,

+ EVM_INS_LOG4 = 164,

+ EVM_INS_CREATE = 240,

+ EVM_INS_CALL = 241,

+ EVM_INS_CALLCODE = 242,

+ EVM_INS_RETURN = 243,

+ EVM_INS_DELEGATECALL = 244,

+ EVM_INS_CALLBLACKBOX = 245,

+ EVM_INS_STATICCALL = 250,

+ EVM_INS_REVERT = 253,

+ EVM_INS_SUICIDE = 255,

+

+ EVM_INS_INVALID = 512,

+ EVM_INS_ENDING, // <-- mark the end of the list of instructions

+} evm_insn;

+

+/// Group of EVM instructions

+typedef enum evm_insn_group {

+ EVM_GRP_INVALID = 0, ///< = CS_GRP_INVALID

+

+ EVM_GRP_JUMP, ///< all jump instructions

+

+ EVM_GRP_MATH = 8, ///< math instructions

+ EVM_GRP_STACK_WRITE, ///< instructions write to stack

+ EVM_GRP_STACK_READ, ///< instructions read from stack

+ EVM_GRP_MEM_WRITE, ///< instructions write to memory

+ EVM_GRP_MEM_READ, ///< instructions read from memory

+ EVM_GRP_STORE_WRITE, ///< instructions write to storage

+ EVM_GRP_STORE_READ, ///< instructions read from storage

+ EVM_GRP_HALT, ///< instructions halt execution

+

+ EVM_GRP_ENDING, ///< <-- mark the end of the list of groups

+} evm_insn_group;

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

+#ifndef CAPSTONE_M680X_H

+#define CAPSTONE_M680X_H

+

+/* Capstone Disassembly Engine */

+/* M680X Backend by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net> 2017 */

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+#include "platform.h"

+

+#ifdef _MSC_VER

+#pragma warning(disable:4201)

+#endif

+

+#define M680X_OPERAND_COUNT 9

+

+/// M680X registers and special registers

+typedef enum m680x_reg {

+ M680X_REG_INVALID = 0,

+

+ M680X_REG_A, ///< M6800/1/2/3/9, HD6301/9

+ M680X_REG_B, ///< M6800/1/2/3/9, HD6301/9

+ M680X_REG_E, ///< HD6309

+ M680X_REG_F, ///< HD6309

+ M680X_REG_0, ///< HD6309

+

+ M680X_REG_D, ///< M6801/3/9, HD6301/9

+ M680X_REG_W, ///< HD6309

+

+ M680X_REG_CC, ///< M6800/1/2/3/9, M6301/9

+ M680X_REG_DP, ///< M6809/M6309

+ M680X_REG_MD, ///< M6309

+

+ M680X_REG_HX, ///< M6808

+ M680X_REG_H, ///< M6808

+ M680X_REG_X, ///< M6800/1/2/3/9, M6301/9

+ M680X_REG_Y, ///< M6809/M6309

+ M680X_REG_S, ///< M6809/M6309

+ M680X_REG_U, ///< M6809/M6309

+ M680X_REG_V, ///< M6309

+

+ M680X_REG_Q, ///< M6309

+

+ M680X_REG_PC, ///< M6800/1/2/3/9, M6301/9

+

+ M680X_REG_TMP2, ///< CPU12

+ M680X_REG_TMP3, ///< CPU12

+

+ M680X_REG_ENDING, ///< <-- mark the end of the list of registers

+} m680x_reg;

+

+/// Operand type for instruction's operands

+typedef enum m680x_op_type {

+ M680X_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).

+ M680X_OP_REGISTER, ///< = Register operand.

+ M680X_OP_IMMEDIATE, ///< = Immediate operand.

+ M680X_OP_INDEXED, ///< = Indexed addressing operand.

+ M680X_OP_EXTENDED, ///< = Extended addressing operand.

+ M680X_OP_DIRECT, ///< = Direct addressing operand.

+ M680X_OP_RELATIVE, ///< = Relative addressing operand.

+ M680X_OP_CONSTANT, ///< = constant operand (Displayed as number only).

+ ///< Used e.g. for a bit index or page number.

+} m680x_op_type;

+

+// Supported bit values for mem.idx.offset_bits

+#define M680X_OFFSET_NONE 0

+#define M680X_OFFSET_BITS_5 5

+#define M680X_OFFSET_BITS_8 8

+#define M680X_OFFSET_BITS_9 9

+#define M680X_OFFSET_BITS_16 16

+

+// Supported bit flags for mem.idx.flags

+// These flags can be combined

+#define M680X_IDX_INDIRECT 1

+#define M680X_IDX_NO_COMMA 2

+#define M680X_IDX_POST_INC_DEC 4

+

+/// Instruction's operand referring to indexed addressing

+typedef struct m680x_op_idx {

+ m680x_reg base_reg; ///< base register (or M680X_REG_INVALID if

+ ///< irrelevant)

+ m680x_reg offset_reg; ///< offset register (or M680X_REG_INVALID if

+ ///< irrelevant)

+ int16_t offset; ///< 5-,8- or 16-bit offset. See also offset_bits.

+ uint16_t offset_addr; ///< = offset addr. if base_reg == M680X_REG_PC.

+ ///< calculated as offset + PC

+ uint8_t offset_bits; ///< offset width in bits for indexed addressing

+ int8_t inc_dec; ///< inc. or dec. value:

+ ///< 0: no inc-/decrement

+ ///< 1 .. 8: increment by 1 .. 8

+ ///< -1 .. -8: decrement by 1 .. 8

+ ///< if flag M680X_IDX_POST_INC_DEC set it is post

+ ///< inc-/decrement otherwise pre inc-/decrement

+ uint8_t flags; ///< 8-bit flags (see above)

+} m680x_op_idx;

+

+/// Instruction's memory operand referring to relative addressing (Bcc/LBcc)

+typedef struct m680x_op_rel {

+ uint16_t address; ///< The absolute address.

+ ///< calculated as PC + offset. PC is the first

+ ///< address after the instruction.

+ int16_t offset; ///< the offset/displacement value

+} m680x_op_rel;

+

+/// Instruction's operand referring to extended addressing

+typedef struct m680x_op_ext {

+ uint16_t address; ///< The absolute address

+ bool indirect; ///< true if extended indirect addressing

+} m680x_op_ext;

+

+/// Instruction operand

+typedef struct cs_m680x_op {

+ m680x_op_type type;

+ union {

+ int32_t imm; ///< immediate value for IMM operand

+ m680x_reg reg; ///< register value for REG operand

+ m680x_op_idx idx; ///< Indexed addressing operand

+ m680x_op_rel rel; ///< Relative address. operand (Bcc/LBcc)

+ m680x_op_ext ext; ///< Extended address

+ uint8_t direct_addr; ///<</ Direct address (lower 8-bit)

+ uint8_t const_val; ///< constant value (bit index, page nr.)

+ };

+ uint8_t size; ///< size of this operand (in bytes)

+ /// How is this operand accessed? (READ, WRITE or READ|WRITE)

+ /// This field is combined of cs_ac_type.

+ /// NOTE: this field is irrelevant if engine is compiled in DIET

+ uint8_t access;

+} cs_m680x_op;

+

+/// Group of M680X instructions

+typedef enum m680x_group_type {

+ M680X_GRP_INVALID = 0, /// = CS_GRP_INVALID

+ // Generic groups

+ // all jump instructions (conditional+direct+indirect jumps)

+ M680X_GRP_JUMP, ///< = CS_GRP_JUMP

+ // all call instructions

+ M680X_GRP_CALL, ///< = CS_GRP_CALL

+ // all return instructions

+ M680X_GRP_RET, ///< = CS_GRP_RET

+ // all interrupt instructions (int+syscall)

+ M680X_GRP_INT, ///< = CS_GRP_INT

+ // all interrupt return instructions

+ M680X_GRP_IRET, ///< = CS_GRP_IRET

+ // all privileged instructions

+ M680X_GRP_PRIV, ///< = CS_GRP_PRIVILEDGE; not used

+ // all relative branching instructions

+ M680X_GRP_BRAREL, ///< = CS_GRP_BRANCH_RELATIVE

+

+ // Architecture-specific groups

+ M680X_GRP_ENDING, // <-- mark the end of the list of groups

+} m680x_group_type;

+

+// M680X instruction flags:

+

+/// The first (register) operand is part of the

+/// instruction mnemonic

+#define M680X_FIRST_OP_IN_MNEM 1

+/// The second (register) operand is part of the

+/// instruction mnemonic

+#define M680X_SECOND_OP_IN_MNEM 2

+

+/// The M680X instruction and it's operands

+typedef struct cs_m680x {

+ uint8_t flags; ///< See: M680X instruction flags

+ uint8_t op_count; ///< number of operands for the instruction or 0

+ cs_m680x_op operands[M680X_OPERAND_COUNT]; ///< operands for this insn.

+} cs_m680x;

+

+/// M680X instruction IDs

+typedef enum m680x_insn {

+ M680X_INS_INVLD = 0,

+ M680X_INS_ABA, ///< M6800/1/2/3

+ M680X_INS_ABX,

+ M680X_INS_ABY,

+ M680X_INS_ADC,

+ M680X_INS_ADCA,

+ M680X_INS_ADCB,

+ M680X_INS_ADCD,

+ M680X_INS_ADCR,

+ M680X_INS_ADD,

+ M680X_INS_ADDA,

+ M680X_INS_ADDB,

+ M680X_INS_ADDD,

+ M680X_INS_ADDE,

+ M680X_INS_ADDF,

+ M680X_INS_ADDR,

+ M680X_INS_ADDW,

+ M680X_INS_AIM,

+ M680X_INS_AIS,

+ M680X_INS_AIX,

+ M680X_INS_AND,

+ M680X_INS_ANDA,

+ M680X_INS_ANDB,

+ M680X_INS_ANDCC,

+ M680X_INS_ANDD,

+ M680X_INS_ANDR,

+ M680X_INS_ASL,

+ M680X_INS_ASLA,

+ M680X_INS_ASLB,

+ M680X_INS_ASLD, ///< or LSLD

+ M680X_INS_ASR,

+ M680X_INS_ASRA,

+ M680X_INS_ASRB,

+ M680X_INS_ASRD,

+ M680X_INS_ASRX,

+ M680X_INS_BAND,

+ M680X_INS_BCC, ///< or BHS

+ M680X_INS_BCLR,

+ M680X_INS_BCS, ///< or BLO

+ M680X_INS_BEOR,

+ M680X_INS_BEQ,

+ M680X_INS_BGE,

+ M680X_INS_BGND,

+ M680X_INS_BGT,

+ M680X_INS_BHCC,

+ M680X_INS_BHCS,

+ M680X_INS_BHI,

+ M680X_INS_BIAND,

+ M680X_INS_BIEOR,

+ M680X_INS_BIH,

+ M680X_INS_BIL,

+ M680X_INS_BIOR,

+ M680X_INS_BIT,

+ M680X_INS_BITA,

+ M680X_INS_BITB,

+ M680X_INS_BITD,

+ M680X_INS_BITMD,

+ M680X_INS_BLE,

+ M680X_INS_BLS,

+ M680X_INS_BLT,

+ M680X_INS_BMC,

+ M680X_INS_BMI,

+ M680X_INS_BMS,

+ M680X_INS_BNE,

+ M680X_INS_BOR,

+ M680X_INS_BPL,

+ M680X_INS_BRCLR,

+ M680X_INS_BRSET,

+ M680X_INS_BRA,

+ M680X_INS_BRN,

+ M680X_INS_BSET,

+ M680X_INS_BSR,

+ M680X_INS_BVC,

+ M680X_INS_BVS,

+ M680X_INS_CALL,

+ M680X_INS_CBA, ///< M6800/1/2/3

+ M680X_INS_CBEQ,

+ M680X_INS_CBEQA,

+ M680X_INS_CBEQX,

+ M680X_INS_CLC, ///< M6800/1/2/3

+ M680X_INS_CLI, ///< M6800/1/2/3

+ M680X_INS_CLR,

+ M680X_INS_CLRA,

+ M680X_INS_CLRB,

+ M680X_INS_CLRD,

+ M680X_INS_CLRE,

+ M680X_INS_CLRF,

+ M680X_INS_CLRH,

+ M680X_INS_CLRW,

+ M680X_INS_CLRX,

+ M680X_INS_CLV, ///< M6800/1/2/3

+ M680X_INS_CMP,

+ M680X_INS_CMPA,

+ M680X_INS_CMPB,

+ M680X_INS_CMPD,

+ M680X_INS_CMPE,

+ M680X_INS_CMPF,

+ M680X_INS_CMPR,

+ M680X_INS_CMPS,

+ M680X_INS_CMPU,

+ M680X_INS_CMPW,

+ M680X_INS_CMPX,

+ M680X_INS_CMPY,

+ M680X_INS_COM,

+ M680X_INS_COMA,

+ M680X_INS_COMB,

+ M680X_INS_COMD,

+ M680X_INS_COME,

+ M680X_INS_COMF,

+ M680X_INS_COMW,

+ M680X_INS_COMX,

+ M680X_INS_CPD,

+ M680X_INS_CPHX,

+ M680X_INS_CPS,

+ M680X_INS_CPX, ///< M6800/1/2/3

+ M680X_INS_CPY,

+ M680X_INS_CWAI,

+ M680X_INS_DAA,

+ M680X_INS_DBEQ,

+ M680X_INS_DBNE,

+ M680X_INS_DBNZ,

+ M680X_INS_DBNZA,

+ M680X_INS_DBNZX,

+ M680X_INS_DEC,

+ M680X_INS_DECA,

+ M680X_INS_DECB,

+ M680X_INS_DECD,

+ M680X_INS_DECE,

+ M680X_INS_DECF,

+ M680X_INS_DECW,

+ M680X_INS_DECX,

+ M680X_INS_DES, ///< M6800/1/2/3

+ M680X_INS_DEX, ///< M6800/1/2/3

+ M680X_INS_DEY,

+ M680X_INS_DIV,

+ M680X_INS_DIVD,

+ M680X_INS_DIVQ,

+ M680X_INS_EDIV,

+ M680X_INS_EDIVS,

+ M680X_INS_EIM,

+ M680X_INS_EMACS,

+ M680X_INS_EMAXD,

+ M680X_INS_EMAXM,

+ M680X_INS_EMIND,

+ M680X_INS_EMINM,

+ M680X_INS_EMUL,

+ M680X_INS_EMULS,

+ M680X_INS_EOR,

+ M680X_INS_EORA,

+ M680X_INS_EORB,

+ M680X_INS_EORD,

+ M680X_INS_EORR,

+ M680X_INS_ETBL,

+ M680X_INS_EXG,

+ M680X_INS_FDIV,

+ M680X_INS_IBEQ,

+ M680X_INS_IBNE,

+ M680X_INS_IDIV,

+ M680X_INS_IDIVS,

+ M680X_INS_ILLGL,

+ M680X_INS_INC,

+ M680X_INS_INCA,

+ M680X_INS_INCB,

+ M680X_INS_INCD,

+ M680X_INS_INCE,

+ M680X_INS_INCF,

+ M680X_INS_INCW,

+ M680X_INS_INCX,

+ M680X_INS_INS, ///< M6800/1/2/3

+ M680X_INS_INX, ///< M6800/1/2/3

+ M680X_INS_INY,

+ M680X_INS_JMP,

+ M680X_INS_JSR,

+ M680X_INS_LBCC, ///< or LBHS

+ M680X_INS_LBCS, ///< or LBLO

+ M680X_INS_LBEQ,

+ M680X_INS_LBGE,

+ M680X_INS_LBGT,

+ M680X_INS_LBHI,

+ M680X_INS_LBLE,

+ M680X_INS_LBLS,

+ M680X_INS_LBLT,

+ M680X_INS_LBMI,

+ M680X_INS_LBNE,

+ M680X_INS_LBPL,

+ M680X_INS_LBRA,

+ M680X_INS_LBRN,

+ M680X_INS_LBSR,

+ M680X_INS_LBVC,

+ M680X_INS_LBVS,

+ M680X_INS_LDA,

+ M680X_INS_LDAA, ///< M6800/1/2/3

+ M680X_INS_LDAB, ///< M6800/1/2/3

+ M680X_INS_LDB,

+ M680X_INS_LDBT,

+ M680X_INS_LDD,

+ M680X_INS_LDE,

+ M680X_INS_LDF,

+ M680X_INS_LDHX,

+ M680X_INS_LDMD,

+ M680X_INS_LDQ,

+ M680X_INS_LDS,

+ M680X_INS_LDU,

+ M680X_INS_LDW,

+ M680X_INS_LDX,

+ M680X_INS_LDY,

+ M680X_INS_LEAS,

+ M680X_INS_LEAU,

+ M680X_INS_LEAX,

+ M680X_INS_LEAY,

+ M680X_INS_LSL,

+ M680X_INS_LSLA,

+ M680X_INS_LSLB,

+ M680X_INS_LSLD,

+ M680X_INS_LSLX,

+ M680X_INS_LSR,

+ M680X_INS_LSRA,

+ M680X_INS_LSRB,

+ M680X_INS_LSRD, ///< or ASRD

+ M680X_INS_LSRW,

+ M680X_INS_LSRX,

+ M680X_INS_MAXA,

+ M680X_INS_MAXM,

+ M680X_INS_MEM,

+ M680X_INS_MINA,

+ M680X_INS_MINM,

+ M680X_INS_MOV,

+ M680X_INS_MOVB,

+ M680X_INS_MOVW,

+ M680X_INS_MUL,

+ M680X_INS_MULD,

+ M680X_INS_NEG,

+ M680X_INS_NEGA,

+ M680X_INS_NEGB,

+ M680X_INS_NEGD,

+ M680X_INS_NEGX,

+ M680X_INS_NOP,

+ M680X_INS_NSA,

+ M680X_INS_OIM,

+ M680X_INS_ORA,

+ M680X_INS_ORAA, ///< M6800/1/2/3

+ M680X_INS_ORAB, ///< M6800/1/2/3

+ M680X_INS_ORB,

+ M680X_INS_ORCC,

+ M680X_INS_ORD,

+ M680X_INS_ORR,

+ M680X_INS_PSHA, ///< M6800/1/2/3

+ M680X_INS_PSHB, ///< M6800/1/2/3

+ M680X_INS_PSHC,

+ M680X_INS_PSHD,

+ M680X_INS_PSHH,

+ M680X_INS_PSHS,

+ M680X_INS_PSHSW,

+ M680X_INS_PSHU,

+ M680X_INS_PSHUW,

+ M680X_INS_PSHX, ///< M6800/1/2/3

+ M680X_INS_PSHY,

+ M680X_INS_PULA, ///< M6800/1/2/3

+ M680X_INS_PULB, ///< M6800/1/2/3

+ M680X_INS_PULC,

+ M680X_INS_PULD,

+ M680X_INS_PULH,

+ M680X_INS_PULS,

+ M680X_INS_PULSW,

+ M680X_INS_PULU,

+ M680X_INS_PULUW,

+ M680X_INS_PULX, ///< M6800/1/2/3

+ M680X_INS_PULY,

+ M680X_INS_REV,

+ M680X_INS_REVW,

+ M680X_INS_ROL,

+ M680X_INS_ROLA,

+ M680X_INS_ROLB,

+ M680X_INS_ROLD,

+ M680X_INS_ROLW,

+ M680X_INS_ROLX,

+ M680X_INS_ROR,

+ M680X_INS_RORA,

+ M680X_INS_RORB,

+ M680X_INS_RORD,

+ M680X_INS_RORW,

+ M680X_INS_RORX,

+ M680X_INS_RSP,

+ M680X_INS_RTC,

+ M680X_INS_RTI,

+ M680X_INS_RTS,

+ M680X_INS_SBA, ///< M6800/1/2/3

+ M680X_INS_SBC,

+ M680X_INS_SBCA,

+ M680X_INS_SBCB,

+ M680X_INS_SBCD,

+ M680X_INS_SBCR,

+ M680X_INS_SEC,

+ M680X_INS_SEI,

+ M680X_INS_SEV,

+ M680X_INS_SEX,

+ M680X_INS_SEXW,

+ M680X_INS_SLP,

+ M680X_INS_STA,

+ M680X_INS_STAA, ///< M6800/1/2/3

+ M680X_INS_STAB, ///< M6800/1/2/3

+ M680X_INS_STB,

+ M680X_INS_STBT,

+ M680X_INS_STD,

+ M680X_INS_STE,

+ M680X_INS_STF,

+ M680X_INS_STOP,

+ M680X_INS_STHX,

+ M680X_INS_STQ,

+ M680X_INS_STS,

+ M680X_INS_STU,

+ M680X_INS_STW,

+ M680X_INS_STX,

+ M680X_INS_STY,

+ M680X_INS_SUB,

+ M680X_INS_SUBA,

+ M680X_INS_SUBB,

+ M680X_INS_SUBD,

+ M680X_INS_SUBE,

+ M680X_INS_SUBF,

+ M680X_INS_SUBR,

+ M680X_INS_SUBW,

+ M680X_INS_SWI,

+ M680X_INS_SWI2,

+ M680X_INS_SWI3,

+ M680X_INS_SYNC,

+ M680X_INS_TAB, ///< M6800/1/2/3

+ M680X_INS_TAP, ///< M6800/1/2/3

+ M680X_INS_TAX,

+ M680X_INS_TBA, ///< M6800/1/2/3

+ M680X_INS_TBEQ,

+ M680X_INS_TBL,

+ M680X_INS_TBNE,

+ M680X_INS_TEST,

+ M680X_INS_TFM,

+ M680X_INS_TFR,

+ M680X_INS_TIM,

+ M680X_INS_TPA, ///< M6800/1/2/3

+ M680X_INS_TST,

+ M680X_INS_TSTA,

+ M680X_INS_TSTB,

+ M680X_INS_TSTD,

+ M680X_INS_TSTE,

+ M680X_INS_TSTF,

+ M680X_INS_TSTW,

+ M680X_INS_TSTX,

+ M680X_INS_TSX, ///< M6800/1/2/3

+ M680X_INS_TSY,

+ M680X_INS_TXA,

+ M680X_INS_TXS, ///< M6800/1/2/3

+ M680X_INS_TYS,

+ M680X_INS_WAI, ///< M6800/1/2/3

+ M680X_INS_WAIT,

+ M680X_INS_WAV,

+ M680X_INS_WAVR,

+ M680X_INS_XGDX, ///< HD6301

+ M680X_INS_XGDY,

+ M680X_INS_ENDING, // <-- mark the end of the list of instructions

+} m680x_insn;

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

+#ifndef CAPSTONE_M68K_H

+#define CAPSTONE_M68K_H

+

+/* Capstone Disassembly Engine */

+/* By Daniel Collin <daniel@collin.com>, 2015-2016 */

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+#include "platform.h"

+

+#ifdef _MSC_VER

+#pragma warning(disable:4201)

+#endif

+

+#define M68K_OPERAND_COUNT 4

+

+/// M68K registers and special registers

+typedef enum m68k_reg {

+ M68K_REG_INVALID = 0,

+

+ M68K_REG_D0,

+ M68K_REG_D1,

+ M68K_REG_D2,

+ M68K_REG_D3,

+ M68K_REG_D4,

+ M68K_REG_D5,

+ M68K_REG_D6,

+ M68K_REG_D7,

+

+ M68K_REG_A0,

+ M68K_REG_A1,

+ M68K_REG_A2,

+ M68K_REG_A3,

+ M68K_REG_A4,

+ M68K_REG_A5,

+ M68K_REG_A6,

+ M68K_REG_A7,

+

+ M68K_REG_FP0,

+ M68K_REG_FP1,

+ M68K_REG_FP2,

+ M68K_REG_FP3,

+ M68K_REG_FP4,

+ M68K_REG_FP5,

+ M68K_REG_FP6,

+ M68K_REG_FP7,

+

+ M68K_REG_PC,

+

+ M68K_REG_SR,

+ M68K_REG_CCR,

+ M68K_REG_SFC,

+ M68K_REG_DFC,

+ M68K_REG_USP,

+ M68K_REG_VBR,

+ M68K_REG_CACR,

+ M68K_REG_CAAR,

+ M68K_REG_MSP,

+ M68K_REG_ISP,

+ M68K_REG_TC,

+ M68K_REG_ITT0,

+ M68K_REG_ITT1,

+ M68K_REG_DTT0,

+ M68K_REG_DTT1,

+ M68K_REG_MMUSR,

+ M68K_REG_URP,

+ M68K_REG_SRP,

+

+ M68K_REG_FPCR,

+ M68K_REG_FPSR,

+ M68K_REG_FPIAR,

+

+ M68K_REG_ENDING, // <-- mark the end of the list of registers

+} m68k_reg;

+

+/// M68K Addressing Modes

+typedef enum m68k_address_mode {

+ M68K_AM_NONE = 0, ///< No address mode.

+

+ M68K_AM_REG_DIRECT_DATA, ///< Register Direct - Data

+ M68K_AM_REG_DIRECT_ADDR, ///< Register Direct - Address

+

+ M68K_AM_REGI_ADDR, ///< Register Indirect - Address

+ M68K_AM_REGI_ADDR_POST_INC, ///< Register Indirect - Address with Postincrement

+ M68K_AM_REGI_ADDR_PRE_DEC, ///< Register Indirect - Address with Predecrement

+ M68K_AM_REGI_ADDR_DISP, ///< Register Indirect - Address with Displacement

+

+ M68K_AM_AREGI_INDEX_8_BIT_DISP, ///< Address Register Indirect With Index- 8-bit displacement

+ M68K_AM_AREGI_INDEX_BASE_DISP, ///< Address Register Indirect With Index- Base displacement

+

+ M68K_AM_MEMI_POST_INDEX, ///< Memory indirect - Postindex

+ M68K_AM_MEMI_PRE_INDEX, ///< Memory indirect - Preindex

+

+ M68K_AM_PCI_DISP, ///< Program Counter Indirect - with Displacement

+

+ M68K_AM_PCI_INDEX_8_BIT_DISP, ///< Program Counter Indirect with Index - with 8-Bit Displacement

+ M68K_AM_PCI_INDEX_BASE_DISP, ///< Program Counter Indirect with Index - with Base Displacement

+

+ M68K_AM_PC_MEMI_POST_INDEX, ///< Program Counter Memory Indirect - Postindexed

+ M68K_AM_PC_MEMI_PRE_INDEX, ///< Program Counter Memory Indirect - Preindexed

+

+ M68K_AM_ABSOLUTE_DATA_SHORT, ///< Absolute Data Addressing - Short

+ M68K_AM_ABSOLUTE_DATA_LONG, ///< Absolute Data Addressing - Long

+ M68K_AM_IMMEDIATE, ///< Immediate value

+

+ M68K_AM_BRANCH_DISPLACEMENT, ///< Address as displacement from (PC+2) used by branches

+} m68k_address_mode;

+

+/// Operand type for instruction's operands

+typedef enum m68k_op_type {

+ M68K_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).

+ M68K_OP_REG, ///< = CS_OP_REG (Register operand).

+ M68K_OP_IMM, ///< = CS_OP_IMM (Immediate operand).

+ M68K_OP_MEM, ///< = CS_OP_MEM (Memory operand).

+ M68K_OP_FP_SINGLE, ///< single precision Floating-Point operand

+ M68K_OP_FP_DOUBLE, ///< double precision Floating-Point operand

+ M68K_OP_REG_BITS, ///< Register bits move

+ M68K_OP_REG_PAIR, ///< Register pair in the same op (upper 4 bits for first reg, lower for second)

+ M68K_OP_BR_DISP, ///< Branch displacement

+} m68k_op_type;

+

+/// Instruction's operand referring to memory

+/// This is associated with M68K_OP_MEM operand type above

+typedef struct m68k_op_mem {

+ m68k_reg base_reg; ///< base register (or M68K_REG_INVALID if irrelevant)

+ m68k_reg index_reg; ///< index register (or M68K_REG_INVALID if irrelevant)

+ m68k_reg in_base_reg; ///< indirect base register (or M68K_REG_INVALID if irrelevant)

+ uint32_t in_disp; ///< indirect displacement

+ uint32_t out_disp; ///< other displacement

+ int16_t disp; ///< displacement value

+ uint8_t scale; ///< scale for index register

+ uint8_t bitfield; ///< set to true if the two values below should be used

+ uint8_t width; ///< used for bf* instructions

+ uint8_t offset; ///< used for bf* instructions

+ uint8_t index_size; ///< 0 = w, 1 = l

+} m68k_op_mem;

+

+/// Operand type for instruction's operands

+typedef enum m68k_op_br_disp_size {

+ M68K_OP_BR_DISP_SIZE_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).

+ M68K_OP_BR_DISP_SIZE_BYTE = 1, ///< signed 8-bit displacement

+ M68K_OP_BR_DISP_SIZE_WORD = 2, ///< signed 16-bit displacement

+ M68K_OP_BR_DISP_SIZE_LONG = 4, ///< signed 32-bit displacement

+} m68k_op_br_disp_size;

+

+typedef struct m68k_op_br_disp {

+ int32_t disp; ///< displacement value

+ uint8_t disp_size; ///< Size from m68k_op_br_disp_size type above

+} m68k_op_br_disp;

+

+/// Register pair in one operand.

+typedef struct cs_m68k_op_reg_pair {

+ m68k_reg reg_0;

+ m68k_reg reg_1;

+} cs_m68k_op_reg_pair;

+

+/// Instruction operand

+typedef struct cs_m68k_op {

+ union {

+ uint64_t imm; ///< immediate value for IMM operand

+ double dimm; ///< double imm

+ float simm; ///< float imm

+ m68k_reg reg; ///< register value for REG operand

+ cs_m68k_op_reg_pair reg_pair; ///< register pair in one operand

+ };

+

+ m68k_op_mem mem; ///< data when operand is targeting memory

+ m68k_op_br_disp br_disp; ///< data when operand is a branch displacement

+ uint32_t register_bits; ///< register bits for movem etc. (always in d0-d7, a0-a7, fp0 - fp7 order)

+ m68k_op_type type;

+ m68k_address_mode address_mode; ///< M68K addressing mode for this op

+} cs_m68k_op;

+

+/// Operation size of the CPU instructions

+typedef enum m68k_cpu_size {

+ M68K_CPU_SIZE_NONE = 0, ///< unsized or unspecified

+ M68K_CPU_SIZE_BYTE = 1, ///< 1 byte in size

+ M68K_CPU_SIZE_WORD = 2, ///< 2 bytes in size

+ M68K_CPU_SIZE_LONG = 4, ///< 4 bytes in size

+} m68k_cpu_size;

+

+/// Operation size of the FPU instructions (Notice that FPU instruction can also use CPU sizes if needed)

+typedef enum m68k_fpu_size {

+ M68K_FPU_SIZE_NONE = 0, ///< unsized like fsave/frestore

+ M68K_FPU_SIZE_SINGLE = 4, ///< 4 byte in size (single float)

+ M68K_FPU_SIZE_DOUBLE = 8, ///< 8 byte in size (double)

+ M68K_FPU_SIZE_EXTENDED = 12, ///< 12 byte in size (extended real format)

+} m68k_fpu_size;

+

+/// Type of size that is being used for the current instruction

+typedef enum m68k_size_type {

+ M68K_SIZE_TYPE_INVALID = 0,

+

+ M68K_SIZE_TYPE_CPU,

+ M68K_SIZE_TYPE_FPU,

+} m68k_size_type;

+

+/// Operation size of the current instruction (NOT the actually size of instruction)

+typedef struct m68k_op_size {

+ m68k_size_type type;

+ union {

+ m68k_cpu_size cpu_size;

+ m68k_fpu_size fpu_size;

+ };

+} m68k_op_size;

+

+/// The M68K instruction and it's operands

+typedef struct cs_m68k {

+ // Number of operands of this instruction or 0 when instruction has no operand.

+ cs_m68k_op operands[M68K_OPERAND_COUNT]; ///< operands for this instruction.

+ m68k_op_size op_size; ///< size of data operand works on in bytes (.b, .w, .l, etc)

+ uint8_t op_count; ///< number of operands for the instruction

+} cs_m68k;

+

+/// M68K instruction

+typedef enum m68k_insn {

+ M68K_INS_INVALID = 0,

+

+ M68K_INS_ABCD,

+ M68K_INS_ADD,

+ M68K_INS_ADDA,

+ M68K_INS_ADDI,

+ M68K_INS_ADDQ,

+ M68K_INS_ADDX,

+ M68K_INS_AND,

+ M68K_INS_ANDI,

+ M68K_INS_ASL,

+ M68K_INS_ASR,

+ M68K_INS_BHS,

+ M68K_INS_BLO,

+ M68K_INS_BHI,

+ M68K_INS_BLS,

+ M68K_INS_BCC,

+ M68K_INS_BCS,

+ M68K_INS_BNE,

+ M68K_INS_BEQ,

+ M68K_INS_BVC,

+ M68K_INS_BVS,

+ M68K_INS_BPL,

+ M68K_INS_BMI,

+ M68K_INS_BGE,

+ M68K_INS_BLT,

+ M68K_INS_BGT,

+ M68K_INS_BLE,

+ M68K_INS_BRA,

+ M68K_INS_BSR,

+ M68K_INS_BCHG,

+ M68K_INS_BCLR,

+ M68K_INS_BSET,

+ M68K_INS_BTST,

+ M68K_INS_BFCHG,

+ M68K_INS_BFCLR,

+ M68K_INS_BFEXTS,

+ M68K_INS_BFEXTU,

+ M68K_INS_BFFFO,

+ M68K_INS_BFINS,

+ M68K_INS_BFSET,

+ M68K_INS_BFTST,

+ M68K_INS_BKPT,

+ M68K_INS_CALLM,

+ M68K_INS_CAS,

+ M68K_INS_CAS2,

+ M68K_INS_CHK,

+ M68K_INS_CHK2,

+ M68K_INS_CLR,

+ M68K_INS_CMP,

+ M68K_INS_CMPA,

+ M68K_INS_CMPI,

+ M68K_INS_CMPM,

+ M68K_INS_CMP2,

+ M68K_INS_CINVL,

+ M68K_INS_CINVP,

+ M68K_INS_CINVA,

+ M68K_INS_CPUSHL,

+ M68K_INS_CPUSHP,

+ M68K_INS_CPUSHA,

+ M68K_INS_DBT,

+ M68K_INS_DBF,

+ M68K_INS_DBHI,

+ M68K_INS_DBLS,

+ M68K_INS_DBCC,

+ M68K_INS_DBCS,

+ M68K_INS_DBNE,

+ M68K_INS_DBEQ,

+ M68K_INS_DBVC,

+ M68K_INS_DBVS,

+ M68K_INS_DBPL,

+ M68K_INS_DBMI,

+ M68K_INS_DBGE,

+ M68K_INS_DBLT,

+ M68K_INS_DBGT,

+ M68K_INS_DBLE,

+ M68K_INS_DBRA,

+ M68K_INS_DIVS,

+ M68K_INS_DIVSL,

+ M68K_INS_DIVU,

+ M68K_INS_DIVUL,

+ M68K_INS_EOR,

+ M68K_INS_EORI,

+ M68K_INS_EXG,

+ M68K_INS_EXT,

+ M68K_INS_EXTB,

+ M68K_INS_FABS,

+ M68K_INS_FSABS,

+ M68K_INS_FDABS,

+ M68K_INS_FACOS,

+ M68K_INS_FADD,

+ M68K_INS_FSADD,

+ M68K_INS_FDADD,

+ M68K_INS_FASIN,

+ M68K_INS_FATAN,

+ M68K_INS_FATANH,

+ M68K_INS_FBF,

+ M68K_INS_FBEQ,

+ M68K_INS_FBOGT,

+ M68K_INS_FBOGE,

+ M68K_INS_FBOLT,

+ M68K_INS_FBOLE,

+ M68K_INS_FBOGL,

+ M68K_INS_FBOR,

+ M68K_INS_FBUN,

+ M68K_INS_FBUEQ,

+ M68K_INS_FBUGT,

+ M68K_INS_FBUGE,

+ M68K_INS_FBULT,

+ M68K_INS_FBULE,

+ M68K_INS_FBNE,

+ M68K_INS_FBT,

+ M68K_INS_FBSF,

+ M68K_INS_FBSEQ,

+ M68K_INS_FBGT,

+ M68K_INS_FBGE,

+ M68K_INS_FBLT,

+ M68K_INS_FBLE,

+ M68K_INS_FBGL,

+ M68K_INS_FBGLE,

+ M68K_INS_FBNGLE,

+ M68K_INS_FBNGL,

+ M68K_INS_FBNLE,

+ M68K_INS_FBNLT,

+ M68K_INS_FBNGE,

+ M68K_INS_FBNGT,

+ M68K_INS_FBSNE,

+ M68K_INS_FBST,

+ M68K_INS_FCMP,

+ M68K_INS_FCOS,

+ M68K_INS_FCOSH,

+ M68K_INS_FDBF,

+ M68K_INS_FDBEQ,

+ M68K_INS_FDBOGT,

+ M68K_INS_FDBOGE,

+ M68K_INS_FDBOLT,

+ M68K_INS_FDBOLE,

+ M68K_INS_FDBOGL,

+ M68K_INS_FDBOR,

+ M68K_INS_FDBUN,

+ M68K_INS_FDBUEQ,

+ M68K_INS_FDBUGT,

+ M68K_INS_FDBUGE,

+ M68K_INS_FDBULT,

+ M68K_INS_FDBULE,

+ M68K_INS_FDBNE,

+ M68K_INS_FDBT,

+ M68K_INS_FDBSF,

+ M68K_INS_FDBSEQ,

+ M68K_INS_FDBGT,

+ M68K_INS_FDBGE,

+ M68K_INS_FDBLT,

+ M68K_INS_FDBLE,

+ M68K_INS_FDBGL,

+ M68K_INS_FDBGLE,

+ M68K_INS_FDBNGLE,

+ M68K_INS_FDBNGL,

+ M68K_INS_FDBNLE,

+ M68K_INS_FDBNLT,

+ M68K_INS_FDBNGE,

+ M68K_INS_FDBNGT,

+ M68K_INS_FDBSNE,

+ M68K_INS_FDBST,

+ M68K_INS_FDIV,

+ M68K_INS_FSDIV,

+ M68K_INS_FDDIV,

+ M68K_INS_FETOX,

+ M68K_INS_FETOXM1,

+ M68K_INS_FGETEXP,

+ M68K_INS_FGETMAN,

+ M68K_INS_FINT,

+ M68K_INS_FINTRZ,

+ M68K_INS_FLOG10,

+ M68K_INS_FLOG2,

+ M68K_INS_FLOGN,

+ M68K_INS_FLOGNP1,

+ M68K_INS_FMOD,

+ M68K_INS_FMOVE,

+ M68K_INS_FSMOVE,

+ M68K_INS_FDMOVE,

+ M68K_INS_FMOVECR,

+ M68K_INS_FMOVEM,

+ M68K_INS_FMUL,

+ M68K_INS_FSMUL,

+ M68K_INS_FDMUL,

+ M68K_INS_FNEG,

+ M68K_INS_FSNEG,

+ M68K_INS_FDNEG,

+ M68K_INS_FNOP,

+ M68K_INS_FREM,

+ M68K_INS_FRESTORE,

+ M68K_INS_FSAVE,

+ M68K_INS_FSCALE,

+ M68K_INS_FSGLDIV,

+ M68K_INS_FSGLMUL,

+ M68K_INS_FSIN,

+ M68K_INS_FSINCOS,

+ M68K_INS_FSINH,

+ M68K_INS_FSQRT,

+ M68K_INS_FSSQRT,

+ M68K_INS_FDSQRT,

+ M68K_INS_FSF,

+ M68K_INS_FSBEQ,

+ M68K_INS_FSOGT,

+ M68K_INS_FSOGE,

+ M68K_INS_FSOLT,

+ M68K_INS_FSOLE,

+ M68K_INS_FSOGL,

+ M68K_INS_FSOR,

+ M68K_INS_FSUN,

+ M68K_INS_FSUEQ,

+ M68K_INS_FSUGT,

+ M68K_INS_FSUGE,

+ M68K_INS_FSULT,

+ M68K_INS_FSULE,

+ M68K_INS_FSNE,

+ M68K_INS_FST,

+ M68K_INS_FSSF,

+ M68K_INS_FSSEQ,

+ M68K_INS_FSGT,

+ M68K_INS_FSGE,

+ M68K_INS_FSLT,

+ M68K_INS_FSLE,

+ M68K_INS_FSGL,

+ M68K_INS_FSGLE,

+ M68K_INS_FSNGLE,

+ M68K_INS_FSNGL,

+ M68K_INS_FSNLE,

+ M68K_INS_FSNLT,

+ M68K_INS_FSNGE,

+ M68K_INS_FSNGT,

+ M68K_INS_FSSNE,

+ M68K_INS_FSST,

+ M68K_INS_FSUB,

+ M68K_INS_FSSUB,

+ M68K_INS_FDSUB,

+ M68K_INS_FTAN,

+ M68K_INS_FTANH,

+ M68K_INS_FTENTOX,

+ M68K_INS_FTRAPF,

+ M68K_INS_FTRAPEQ,

+ M68K_INS_FTRAPOGT,

+ M68K_INS_FTRAPOGE,

+ M68K_INS_FTRAPOLT,

+ M68K_INS_FTRAPOLE,

+ M68K_INS_FTRAPOGL,

+ M68K_INS_FTRAPOR,

+ M68K_INS_FTRAPUN,

+ M68K_INS_FTRAPUEQ,

+ M68K_INS_FTRAPUGT,

+ M68K_INS_FTRAPUGE,

+ M68K_INS_FTRAPULT,

+ M68K_INS_FTRAPULE,

+ M68K_INS_FTRAPNE,

+ M68K_INS_FTRAPT,

+ M68K_INS_FTRAPSF,

+ M68K_INS_FTRAPSEQ,

+ M68K_INS_FTRAPGT,

+ M68K_INS_FTRAPGE,

+ M68K_INS_FTRAPLT,

+ M68K_INS_FTRAPLE,

+ M68K_INS_FTRAPGL,

+ M68K_INS_FTRAPGLE,

+ M68K_INS_FTRAPNGLE,

+ M68K_INS_FTRAPNGL,

+ M68K_INS_FTRAPNLE,

+ M68K_INS_FTRAPNLT,

+ M68K_INS_FTRAPNGE,

+ M68K_INS_FTRAPNGT,

+ M68K_INS_FTRAPSNE,

+ M68K_INS_FTRAPST,

+ M68K_INS_FTST,

+ M68K_INS_FTWOTOX,

+ M68K_INS_HALT,

+ M68K_INS_ILLEGAL,

+ M68K_INS_JMP,

+ M68K_INS_JSR,

+ M68K_INS_LEA,

+ M68K_INS_LINK,

+ M68K_INS_LPSTOP,

+ M68K_INS_LSL,

+ M68K_INS_LSR,

+ M68K_INS_MOVE,

+ M68K_INS_MOVEA,

+ M68K_INS_MOVEC,

+ M68K_INS_MOVEM,

+ M68K_INS_MOVEP,

+ M68K_INS_MOVEQ,

+ M68K_INS_MOVES,

+ M68K_INS_MOVE16,

+ M68K_INS_MULS,

+ M68K_INS_MULU,

+ M68K_INS_NBCD,

+ M68K_INS_NEG,

+ M68K_INS_NEGX,

+ M68K_INS_NOP,

+ M68K_INS_NOT,

+ M68K_INS_OR,

+ M68K_INS_ORI,

+ M68K_INS_PACK,

+ M68K_INS_PEA,

+ M68K_INS_PFLUSH,

+ M68K_INS_PFLUSHA,

+ M68K_INS_PFLUSHAN,

+ M68K_INS_PFLUSHN,

+ M68K_INS_PLOADR,

+ M68K_INS_PLOADW,

+ M68K_INS_PLPAR,

+ M68K_INS_PLPAW,

+ M68K_INS_PMOVE,

+ M68K_INS_PMOVEFD,

+ M68K_INS_PTESTR,

+ M68K_INS_PTESTW,

+ M68K_INS_PULSE,

+ M68K_INS_REMS,

+ M68K_INS_REMU,

+ M68K_INS_RESET,

+ M68K_INS_ROL,

+ M68K_INS_ROR,

+ M68K_INS_ROXL,

+ M68K_INS_ROXR,

+ M68K_INS_RTD,

+ M68K_INS_RTE,

+ M68K_INS_RTM,

+ M68K_INS_RTR,

+ M68K_INS_RTS,

+ M68K_INS_SBCD,

+ M68K_INS_ST,

+ M68K_INS_SF,

+ M68K_INS_SHI,

+ M68K_INS_SLS,

+ M68K_INS_SCC,

+ M68K_INS_SHS,

+ M68K_INS_SCS,

+ M68K_INS_SLO,

+ M68K_INS_SNE,

+ M68K_INS_SEQ,

+ M68K_INS_SVC,

+ M68K_INS_SVS,

+ M68K_INS_SPL,

+ M68K_INS_SMI,

+ M68K_INS_SGE,

+ M68K_INS_SLT,

+ M68K_INS_SGT,

+ M68K_INS_SLE,

+ M68K_INS_STOP,

+ M68K_INS_SUB,

+ M68K_INS_SUBA,

+ M68K_INS_SUBI,

+ M68K_INS_SUBQ,

+ M68K_INS_SUBX,

+ M68K_INS_SWAP,

+ M68K_INS_TAS,

+ M68K_INS_TRAP,

+ M68K_INS_TRAPV,

+ M68K_INS_TRAPT,

+ M68K_INS_TRAPF,

+ M68K_INS_TRAPHI,

+ M68K_INS_TRAPLS,

+ M68K_INS_TRAPCC,

+ M68K_INS_TRAPHS,

+ M68K_INS_TRAPCS,

+ M68K_INS_TRAPLO,

+ M68K_INS_TRAPNE,

+ M68K_INS_TRAPEQ,

+ M68K_INS_TRAPVC,

+ M68K_INS_TRAPVS,

+ M68K_INS_TRAPPL,

+ M68K_INS_TRAPMI,

+ M68K_INS_TRAPGE,

+ M68K_INS_TRAPLT,

+ M68K_INS_TRAPGT,

+ M68K_INS_TRAPLE,

+ M68K_INS_TST,

+ M68K_INS_UNLK,

+ M68K_INS_UNPK,

+ M68K_INS_ENDING, // <-- mark the end of the list of instructions

+} m68k_insn;

+

+/// Group of M68K instructions

+typedef enum m68k_group_type {

+ M68K_GRP_INVALID = 0, ///< CS_GRUP_INVALID

+ M68K_GRP_JUMP, ///< = CS_GRP_JUMP

+ M68K_GRP_RET = 3, ///< = CS_GRP_RET

+ M68K_GRP_IRET = 5, ///< = CS_GRP_IRET

+ M68K_GRP_BRANCH_RELATIVE = 7, ///< = CS_GRP_BRANCH_RELATIVE

+

+ M68K_GRP_ENDING,// <-- mark the end of the list of groups

+} m68k_group_type;

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

+#ifndef CAPSTONE_MIPS_H

+#define CAPSTONE_MIPS_H

+

+/* Capstone Disassembly Engine */

+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+#include "platform.h"

+

+// GCC MIPS toolchain has a default macro called "mips" which breaks

+// compilation

+#undef mips

+

+#ifdef _MSC_VER

+#pragma warning(disable:4201)

+#endif

+

+/// Operand type for instruction's operands

+typedef enum mips_op_type {

+ MIPS_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).

+ MIPS_OP_REG, ///< = CS_OP_REG (Register operand).

+ MIPS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).

+ MIPS_OP_MEM, ///< = CS_OP_MEM (Memory operand).

+} mips_op_type;

+

+/// MIPS registers

+typedef enum mips_reg {

+ MIPS_REG_INVALID = 0,

+ // General purpose registers

+ MIPS_REG_PC,

+

+ MIPS_REG_0,

+ MIPS_REG_1,

+ MIPS_REG_2,

+ MIPS_REG_3,

+ MIPS_REG_4,

+ MIPS_REG_5,

+ MIPS_REG_6,

+ MIPS_REG_7,

+ MIPS_REG_8,

+ MIPS_REG_9,

+ MIPS_REG_10,

+ MIPS_REG_11,

+ MIPS_REG_12,

+ MIPS_REG_13,

+ MIPS_REG_14,

+ MIPS_REG_15,

+ MIPS_REG_16,

+ MIPS_REG_17,

+ MIPS_REG_18,

+ MIPS_REG_19,

+ MIPS_REG_20,

+ MIPS_REG_21,

+ MIPS_REG_22,

+ MIPS_REG_23,

+ MIPS_REG_24,

+ MIPS_REG_25,

+ MIPS_REG_26,

+ MIPS_REG_27,

+ MIPS_REG_28,

+ MIPS_REG_29,

+ MIPS_REG_30,

+ MIPS_REG_31,

+

+ // DSP registers

+ MIPS_REG_DSPCCOND,

+ MIPS_REG_DSPCARRY,

+ MIPS_REG_DSPEFI,

+ MIPS_REG_DSPOUTFLAG,

+ MIPS_REG_DSPOUTFLAG16_19,

+ MIPS_REG_DSPOUTFLAG20,

+ MIPS_REG_DSPOUTFLAG21,

+ MIPS_REG_DSPOUTFLAG22,

+ MIPS_REG_DSPOUTFLAG23,

+ MIPS_REG_DSPPOS,

+ MIPS_REG_DSPSCOUNT,

+

+ // ACC registers

+ MIPS_REG_AC0,

+ MIPS_REG_AC1,

+ MIPS_REG_AC2,

+ MIPS_REG_AC3,

+

+ // COP registers

+ MIPS_REG_CC0,

+ MIPS_REG_CC1,

+ MIPS_REG_CC2,

+ MIPS_REG_CC3,

+ MIPS_REG_CC4,

+ MIPS_REG_CC5,

+ MIPS_REG_CC6,

+ MIPS_REG_CC7,

+

+ // FPU registers

+ MIPS_REG_F0,

+ MIPS_REG_F1,

+ MIPS_REG_F2,

+ MIPS_REG_F3,

+ MIPS_REG_F4,

+ MIPS_REG_F5,

+ MIPS_REG_F6,

+ MIPS_REG_F7,

+ MIPS_REG_F8,

+ MIPS_REG_F9,

+ MIPS_REG_F10,

+ MIPS_REG_F11,

+ MIPS_REG_F12,

+ MIPS_REG_F13,

+ MIPS_REG_F14,

+ MIPS_REG_F15,

+ MIPS_REG_F16,

+ MIPS_REG_F17,

+ MIPS_REG_F18,

+ MIPS_REG_F19,

+ MIPS_REG_F20,

+ MIPS_REG_F21,

+ MIPS_REG_F22,

+ MIPS_REG_F23,

+ MIPS_REG_F24,

+ MIPS_REG_F25,

+ MIPS_REG_F26,

+ MIPS_REG_F27,

+ MIPS_REG_F28,

+ MIPS_REG_F29,

+ MIPS_REG_F30,

+ MIPS_REG_F31,

+

+ MIPS_REG_FCC0,

+ MIPS_REG_FCC1,

+ MIPS_REG_FCC2,

+ MIPS_REG_FCC3,

+ MIPS_REG_FCC4,

+ MIPS_REG_FCC5,

+ MIPS_REG_FCC6,

+ MIPS_REG_FCC7,

+

+ // AFPR128

+ MIPS_REG_W0,

+ MIPS_REG_W1,

+ MIPS_REG_W2,

+ MIPS_REG_W3,

+ MIPS_REG_W4,

+ MIPS_REG_W5,

+ MIPS_REG_W6,

+ MIPS_REG_W7,

+ MIPS_REG_W8,

+ MIPS_REG_W9,

+ MIPS_REG_W10,

+ MIPS_REG_W11,

+ MIPS_REG_W12,

+ MIPS_REG_W13,

+ MIPS_REG_W14,

+ MIPS_REG_W15,

+ MIPS_REG_W16,

+ MIPS_REG_W17,

+ MIPS_REG_W18,

+ MIPS_REG_W19,

+ MIPS_REG_W20,

+ MIPS_REG_W21,

+ MIPS_REG_W22,

+ MIPS_REG_W23,

+ MIPS_REG_W24,

+ MIPS_REG_W25,

+ MIPS_REG_W26,

+ MIPS_REG_W27,

+ MIPS_REG_W28,

+ MIPS_REG_W29,

+ MIPS_REG_W30,

+ MIPS_REG_W31,

+

+ MIPS_REG_HI,

+ MIPS_REG_LO,

+

+ MIPS_REG_P0,

+ MIPS_REG_P1,

+ MIPS_REG_P2,

+

+ MIPS_REG_MPL0,

+ MIPS_REG_MPL1,

+ MIPS_REG_MPL2,

+

+ MIPS_REG_ENDING, // <-- mark the end of the list or registers

+

+ // alias registers

+ MIPS_REG_ZERO = MIPS_REG_0,

+ MIPS_REG_AT = MIPS_REG_1,

+ MIPS_REG_V0 = MIPS_REG_2,

+ MIPS_REG_V1 = MIPS_REG_3,

+ MIPS_REG_A0 = MIPS_REG_4,

+ MIPS_REG_A1 = MIPS_REG_5,

+ MIPS_REG_A2 = MIPS_REG_6,

+ MIPS_REG_A3 = MIPS_REG_7,

+ MIPS_REG_T0 = MIPS_REG_8,

+ MIPS_REG_T1 = MIPS_REG_9,

+ MIPS_REG_T2 = MIPS_REG_10,

+ MIPS_REG_T3 = MIPS_REG_11,

+ MIPS_REG_T4 = MIPS_REG_12,

+ MIPS_REG_T5 = MIPS_REG_13,

+ MIPS_REG_T6 = MIPS_REG_14,

+ MIPS_REG_T7 = MIPS_REG_15,

+ MIPS_REG_S0 = MIPS_REG_16,

+ MIPS_REG_S1 = MIPS_REG_17,

+ MIPS_REG_S2 = MIPS_REG_18,

+ MIPS_REG_S3 = MIPS_REG_19,

+ MIPS_REG_S4 = MIPS_REG_20,

+ MIPS_REG_S5 = MIPS_REG_21,

+ MIPS_REG_S6 = MIPS_REG_22,

+ MIPS_REG_S7 = MIPS_REG_23,

+ MIPS_REG_T8 = MIPS_REG_24,

+ MIPS_REG_T9 = MIPS_REG_25,

+ MIPS_REG_K0 = MIPS_REG_26,

+ MIPS_REG_K1 = MIPS_REG_27,

+ MIPS_REG_GP = MIPS_REG_28,

+ MIPS_REG_SP = MIPS_REG_29,

+ MIPS_REG_FP = MIPS_REG_30, MIPS_REG_S8 = MIPS_REG_30,

+ MIPS_REG_RA = MIPS_REG_31,

+

+ MIPS_REG_HI0 = MIPS_REG_AC0,

+ MIPS_REG_HI1 = MIPS_REG_AC1,

+ MIPS_REG_HI2 = MIPS_REG_AC2,

+ MIPS_REG_HI3 = MIPS_REG_AC3,

+

+ MIPS_REG_LO0 = MIPS_REG_HI0,

+ MIPS_REG_LO1 = MIPS_REG_HI1,

+ MIPS_REG_LO2 = MIPS_REG_HI2,

+ MIPS_REG_LO3 = MIPS_REG_HI3,

+} mips_reg;

+

+/// Instruction's operand referring to memory

+/// This is associated with MIPS_OP_MEM operand type above

+typedef struct mips_op_mem {

+ mips_reg base; ///< base register

+ int64_t disp; ///< displacement/offset value

+} mips_op_mem;

+

+/// Instruction operand

+typedef struct cs_mips_op {

+ mips_op_type type; ///< operand type

+ union {

+ mips_reg reg; ///< register id for REG operand

+ int64_t imm; ///< immediate value for IMM operand

+ mips_op_mem mem; ///< base/index/scale/disp value for MEM operand

+ };

+} cs_mips_op;

+

+/// Instruction structure

+typedef struct cs_mips {

+ /// Number of operands of this instruction,

+ /// or 0 when instruction has no operand.

+ uint8_t op_count;

+ cs_mips_op operands[10]; ///< operands for this instruction.

+} cs_mips;

+

+/// MIPS instruction

+typedef enum mips_insn {

+ MIPS_INS_INVALID = 0,

+

+ MIPS_INS_ABSQ_S,

+ MIPS_INS_ADD,

+ MIPS_INS_ADDIUPC,

+ MIPS_INS_ADDIUR1SP,

+ MIPS_INS_ADDIUR2,

+ MIPS_INS_ADDIUS5,

+ MIPS_INS_ADDIUSP,

+ MIPS_INS_ADDQH,

+ MIPS_INS_ADDQH_R,

+ MIPS_INS_ADDQ,

+ MIPS_INS_ADDQ_S,

+ MIPS_INS_ADDSC,

+ MIPS_INS_ADDS_A,

+ MIPS_INS_ADDS_S,

+ MIPS_INS_ADDS_U,

+ MIPS_INS_ADDU16,

+ MIPS_INS_ADDUH,

+ MIPS_INS_ADDUH_R,

+ MIPS_INS_ADDU,

+ MIPS_INS_ADDU_S,

+ MIPS_INS_ADDVI,

+ MIPS_INS_ADDV,

+ MIPS_INS_ADDWC,

+ MIPS_INS_ADD_A,

+ MIPS_INS_ADDI,

+ MIPS_INS_ADDIU,

+ MIPS_INS_ALIGN,

+ MIPS_INS_ALUIPC,

+ MIPS_INS_AND,

+ MIPS_INS_AND16,

+ MIPS_INS_ANDI16,

+ MIPS_INS_ANDI,

+ MIPS_INS_APPEND,

+ MIPS_INS_ASUB_S,

+ MIPS_INS_ASUB_U,

+ MIPS_INS_AUI,

+ MIPS_INS_AUIPC,

+ MIPS_INS_AVER_S,

+ MIPS_INS_AVER_U,

+ MIPS_INS_AVE_S,

+ MIPS_INS_AVE_U,

+ MIPS_INS_B16,

+ MIPS_INS_BADDU,

+ MIPS_INS_BAL,

+ MIPS_INS_BALC,

+ MIPS_INS_BALIGN,

+ MIPS_INS_BBIT0,

+ MIPS_INS_BBIT032,

+ MIPS_INS_BBIT1,

+ MIPS_INS_BBIT132,

+ MIPS_INS_BC,

+ MIPS_INS_BC0F,

+ MIPS_INS_BC0FL,

+ MIPS_INS_BC0T,

+ MIPS_INS_BC0TL,

+ MIPS_INS_BC1EQZ,

+ MIPS_INS_BC1F,

+ MIPS_INS_BC1FL,

+ MIPS_INS_BC1NEZ,

+ MIPS_INS_BC1T,

+ MIPS_INS_BC1TL,

+ MIPS_INS_BC2EQZ,

+ MIPS_INS_BC2F,

+ MIPS_INS_BC2FL,

+ MIPS_INS_BC2NEZ,

+ MIPS_INS_BC2T,

+ MIPS_INS_BC2TL,

+ MIPS_INS_BC3F,

+ MIPS_INS_BC3FL,

+ MIPS_INS_BC3T,

+ MIPS_INS_BC3TL,

+ MIPS_INS_BCLRI,

+ MIPS_INS_BCLR,

+ MIPS_INS_BEQ,

+ MIPS_INS_BEQC,

+ MIPS_INS_BEQL,

+ MIPS_INS_BEQZ16,

+ MIPS_INS_BEQZALC,

+ MIPS_INS_BEQZC,

+ MIPS_INS_BGEC,

+ MIPS_INS_BGEUC,

+ MIPS_INS_BGEZ,

+ MIPS_INS_BGEZAL,

+ MIPS_INS_BGEZALC,

+ MIPS_INS_BGEZALL,

+ MIPS_INS_BGEZALS,

+ MIPS_INS_BGEZC,

+ MIPS_INS_BGEZL,

+ MIPS_INS_BGTZ,

+ MIPS_INS_BGTZALC,

+ MIPS_INS_BGTZC,

+ MIPS_INS_BGTZL,

+ MIPS_INS_BINSLI,

+ MIPS_INS_BINSL,

+ MIPS_INS_BINSRI,

+ MIPS_INS_BINSR,

+ MIPS_INS_BITREV,

+ MIPS_INS_BITSWAP,

+ MIPS_INS_BLEZ,

+ MIPS_INS_BLEZALC,

+ MIPS_INS_BLEZC,

+ MIPS_INS_BLEZL,

+ MIPS_INS_BLTC,

+ MIPS_INS_BLTUC,

+ MIPS_INS_BLTZ,

+ MIPS_INS_BLTZAL,

+ MIPS_INS_BLTZALC,

+ MIPS_INS_BLTZALL,

+ MIPS_INS_BLTZALS,

+ MIPS_INS_BLTZC,

+ MIPS_INS_BLTZL,

+ MIPS_INS_BMNZI,

+ MIPS_INS_BMNZ,

+ MIPS_INS_BMZI,

+ MIPS_INS_BMZ,

+ MIPS_INS_BNE,

+ MIPS_INS_BNEC,

+ MIPS_INS_BNEGI,

+ MIPS_INS_BNEG,

+ MIPS_INS_BNEL,

+ MIPS_INS_BNEZ16,

+ MIPS_INS_BNEZALC,

+ MIPS_INS_BNEZC,

+ MIPS_INS_BNVC,

+ MIPS_INS_BNZ,

+ MIPS_INS_BOVC,

+ MIPS_INS_BPOSGE32,

+ MIPS_INS_BREAK,

+ MIPS_INS_BREAK16,

+ MIPS_INS_BSELI,

+ MIPS_INS_BSEL,

+ MIPS_INS_BSETI,

+ MIPS_INS_BSET,

+ MIPS_INS_BZ,

+ MIPS_INS_BEQZ,

+ MIPS_INS_B,

+ MIPS_INS_BNEZ,

+ MIPS_INS_BTEQZ,

+ MIPS_INS_BTNEZ,

+ MIPS_INS_CACHE,

+ MIPS_INS_CEIL,

+ MIPS_INS_CEQI,

+ MIPS_INS_CEQ,

+ MIPS_INS_CFC1,

+ MIPS_INS_CFCMSA,

+ MIPS_INS_CINS,

+ MIPS_INS_CINS32,

+ MIPS_INS_CLASS,

+ MIPS_INS_CLEI_S,

+ MIPS_INS_CLEI_U,

+ MIPS_INS_CLE_S,

+ MIPS_INS_CLE_U,

+ MIPS_INS_CLO,

+ MIPS_INS_CLTI_S,

+ MIPS_INS_CLTI_U,

+ MIPS_INS_CLT_S,

+ MIPS_INS_CLT_U,

+ MIPS_INS_CLZ,

+ MIPS_INS_CMPGDU,

+ MIPS_INS_CMPGU,

+ MIPS_INS_CMPU,

+ MIPS_INS_CMP,

+ MIPS_INS_COPY_S,

+ MIPS_INS_COPY_U,

+ MIPS_INS_CTC1,

+ MIPS_INS_CTCMSA,

+ MIPS_INS_CVT,

+ MIPS_INS_C,

+ MIPS_INS_CMPI,

+ MIPS_INS_DADD,

+ MIPS_INS_DADDI,

+ MIPS_INS_DADDIU,

+ MIPS_INS_DADDU,

+ MIPS_INS_DAHI,

+ MIPS_INS_DALIGN,

+ MIPS_INS_DATI,

+ MIPS_INS_DAUI,

+ MIPS_INS_DBITSWAP,

+ MIPS_INS_DCLO,

+ MIPS_INS_DCLZ,

+ MIPS_INS_DDIV,

+ MIPS_INS_DDIVU,

+ MIPS_INS_DERET,

+ MIPS_INS_DEXT,

+ MIPS_INS_DEXTM,

+ MIPS_INS_DEXTU,

+ MIPS_INS_DI,

+ MIPS_INS_DINS,

+ MIPS_INS_DINSM,

+ MIPS_INS_DINSU,

+ MIPS_INS_DIV,

+ MIPS_INS_DIVU,

+ MIPS_INS_DIV_S,

+ MIPS_INS_DIV_U,

+ MIPS_INS_DLSA,

+ MIPS_INS_DMFC0,

+ MIPS_INS_DMFC1,

+ MIPS_INS_DMFC2,

+ MIPS_INS_DMOD,

+ MIPS_INS_DMODU,

+ MIPS_INS_DMTC0,

+ MIPS_INS_DMTC1,

+ MIPS_INS_DMTC2,

+ MIPS_INS_DMUH,

+ MIPS_INS_DMUHU,

+ MIPS_INS_DMUL,

+ MIPS_INS_DMULT,

+ MIPS_INS_DMULTU,

+ MIPS_INS_DMULU,

+ MIPS_INS_DOTP_S,

+ MIPS_INS_DOTP_U,

+ MIPS_INS_DPADD_S,

+ MIPS_INS_DPADD_U,

+ MIPS_INS_DPAQX_SA,

+ MIPS_INS_DPAQX_S,

+ MIPS_INS_DPAQ_SA,

+ MIPS_INS_DPAQ_S,

+ MIPS_INS_DPAU,

+ MIPS_INS_DPAX,

+ MIPS_INS_DPA,

+ MIPS_INS_DPOP,

+ MIPS_INS_DPSQX_SA,

+ MIPS_INS_DPSQX_S,

+ MIPS_INS_DPSQ_SA,

+ MIPS_INS_DPSQ_S,

+ MIPS_INS_DPSUB_S,

+ MIPS_INS_DPSUB_U,

+ MIPS_INS_DPSU,

+ MIPS_INS_DPSX,

+ MIPS_INS_DPS,

+ MIPS_INS_DROTR,

+ MIPS_INS_DROTR32,

+ MIPS_INS_DROTRV,

+ MIPS_INS_DSBH,

+ MIPS_INS_DSHD,

+ MIPS_INS_DSLL,

+ MIPS_INS_DSLL32,

+ MIPS_INS_DSLLV,

+ MIPS_INS_DSRA,

+ MIPS_INS_DSRA32,

+ MIPS_INS_DSRAV,

+ MIPS_INS_DSRL,

+ MIPS_INS_DSRL32,

+ MIPS_INS_DSRLV,

+ MIPS_INS_DSUB,

+ MIPS_INS_DSUBU,

+ MIPS_INS_EHB,

+ MIPS_INS_EI,

+ MIPS_INS_ERET,

+ MIPS_INS_EXT,

+ MIPS_INS_EXTP,

+ MIPS_INS_EXTPDP,

+ MIPS_INS_EXTPDPV,

+ MIPS_INS_EXTPV,

+ MIPS_INS_EXTRV_RS,

+ MIPS_INS_EXTRV_R,

+ MIPS_INS_EXTRV_S,

+ MIPS_INS_EXTRV,

+ MIPS_INS_EXTR_RS,

+ MIPS_INS_EXTR_R,

+ MIPS_INS_EXTR_S,

+ MIPS_INS_EXTR,

+ MIPS_INS_EXTS,

+ MIPS_INS_EXTS32,

+ MIPS_INS_ABS,

+ MIPS_INS_FADD,

+ MIPS_INS_FCAF,

+ MIPS_INS_FCEQ,

+ MIPS_INS_FCLASS,

+ MIPS_INS_FCLE,

+ MIPS_INS_FCLT,

+ MIPS_INS_FCNE,

+ MIPS_INS_FCOR,

+ MIPS_INS_FCUEQ,

+ MIPS_INS_FCULE,

+ MIPS_INS_FCULT,

+ MIPS_INS_FCUNE,

+ MIPS_INS_FCUN,

+ MIPS_INS_FDIV,

+ MIPS_INS_FEXDO,

+ MIPS_INS_FEXP2,

+ MIPS_INS_FEXUPL,

+ MIPS_INS_FEXUPR,

+ MIPS_INS_FFINT_S,

+ MIPS_INS_FFINT_U,

+ MIPS_INS_FFQL,

+ MIPS_INS_FFQR,

+ MIPS_INS_FILL,

+ MIPS_INS_FLOG2,

+ MIPS_INS_FLOOR,

+ MIPS_INS_FMADD,

+ MIPS_INS_FMAX_A,

+ MIPS_INS_FMAX,

+ MIPS_INS_FMIN_A,

+ MIPS_INS_FMIN,

+ MIPS_INS_MOV,

+ MIPS_INS_FMSUB,

+ MIPS_INS_FMUL,

+ MIPS_INS_MUL,

+ MIPS_INS_NEG,

+ MIPS_INS_FRCP,

+ MIPS_INS_FRINT,

+ MIPS_INS_FRSQRT,

+ MIPS_INS_FSAF,

+ MIPS_INS_FSEQ,

+ MIPS_INS_FSLE,

+ MIPS_INS_FSLT,

+ MIPS_INS_FSNE,

+ MIPS_INS_FSOR,

+ MIPS_INS_FSQRT,

+ MIPS_INS_SQRT,

+ MIPS_INS_FSUB,

+ MIPS_INS_SUB,

+ MIPS_INS_FSUEQ,

+ MIPS_INS_FSULE,

+ MIPS_INS_FSULT,

+ MIPS_INS_FSUNE,

+ MIPS_INS_FSUN,

+ MIPS_INS_FTINT_S,

+ MIPS_INS_FTINT_U,

+ MIPS_INS_FTQ,

+ MIPS_INS_FTRUNC_S,

+ MIPS_INS_FTRUNC_U,

+ MIPS_INS_HADD_S,

+ MIPS_INS_HADD_U,

+ MIPS_INS_HSUB_S,

+ MIPS_INS_HSUB_U,

+ MIPS_INS_ILVEV,

+ MIPS_INS_ILVL,

+ MIPS_INS_ILVOD,

+ MIPS_INS_ILVR,

+ MIPS_INS_INS,

+ MIPS_INS_INSERT,

+ MIPS_INS_INSV,

+ MIPS_INS_INSVE,

+ MIPS_INS_J,

+ MIPS_INS_JAL,

+ MIPS_INS_JALR,

+ MIPS_INS_JALRS16,

+ MIPS_INS_JALRS,

+ MIPS_INS_JALS,

+ MIPS_INS_JALX,

+ MIPS_INS_JIALC,

+ MIPS_INS_JIC,

+ MIPS_INS_JR,

+ MIPS_INS_JR16,

+ MIPS_INS_JRADDIUSP,

+ MIPS_INS_JRC,

+ MIPS_INS_JALRC,

+ MIPS_INS_LB,

+ MIPS_INS_LBU16,

+ MIPS_INS_LBUX,

+ MIPS_INS_LBU,

+ MIPS_INS_LD,

+ MIPS_INS_LDC1,

+ MIPS_INS_LDC2,

+ MIPS_INS_LDC3,

+ MIPS_INS_LDI,

+ MIPS_INS_LDL,

+ MIPS_INS_LDPC,

+ MIPS_INS_LDR,

+ MIPS_INS_LDXC1,

+ MIPS_INS_LH,

+ MIPS_INS_LHU16,

+ MIPS_INS_LHX,

+ MIPS_INS_LHU,

+ MIPS_INS_LI16,

+ MIPS_INS_LL,

+ MIPS_INS_LLD,

+ MIPS_INS_LSA,

+ MIPS_INS_LUXC1,

+ MIPS_INS_LUI,

+ MIPS_INS_LW,

+ MIPS_INS_LW16,

+ MIPS_INS_LWC1,

+ MIPS_INS_LWC2,

+ MIPS_INS_LWC3,

+ MIPS_INS_LWL,

+ MIPS_INS_LWM16,

+ MIPS_INS_LWM32,

+ MIPS_INS_LWPC,

+ MIPS_INS_LWP,

+ MIPS_INS_LWR,

+ MIPS_INS_LWUPC,

+ MIPS_INS_LWU,

+ MIPS_INS_LWX,

+ MIPS_INS_LWXC1,

+ MIPS_INS_LWXS,

+ MIPS_INS_LI,

+ MIPS_INS_MADD,

+ MIPS_INS_MADDF,

+ MIPS_INS_MADDR_Q,

+ MIPS_INS_MADDU,

+ MIPS_INS_MADDV,

+ MIPS_INS_MADD_Q,

+ MIPS_INS_MAQ_SA,

+ MIPS_INS_MAQ_S,

+ MIPS_INS_MAXA,

+ MIPS_INS_MAXI_S,

+ MIPS_INS_MAXI_U,

+ MIPS_INS_MAX_A,

+ MIPS_INS_MAX,

+ MIPS_INS_MAX_S,

+ MIPS_INS_MAX_U,

+ MIPS_INS_MFC0,

+ MIPS_INS_MFC1,

+ MIPS_INS_MFC2,

+ MIPS_INS_MFHC1,

+ MIPS_INS_MFHI,

+ MIPS_INS_MFLO,

+ MIPS_INS_MINA,

+ MIPS_INS_MINI_S,

+ MIPS_INS_MINI_U,

+ MIPS_INS_MIN_A,

+ MIPS_INS_MIN,

+ MIPS_INS_MIN_S,

+ MIPS_INS_MIN_U,

+ MIPS_INS_MOD,

+ MIPS_INS_MODSUB,

+ MIPS_INS_MODU,

+ MIPS_INS_MOD_S,

+ MIPS_INS_MOD_U,

+ MIPS_INS_MOVE,

+ MIPS_INS_MOVEP,

+ MIPS_INS_MOVF,

+ MIPS_INS_MOVN,

+ MIPS_INS_MOVT,

+ MIPS_INS_MOVZ,

+ MIPS_INS_MSUB,

+ MIPS_INS_MSUBF,

+ MIPS_INS_MSUBR_Q,

+ MIPS_INS_MSUBU,

+ MIPS_INS_MSUBV,

+ MIPS_INS_MSUB_Q,

+ MIPS_INS_MTC0,

+ MIPS_INS_MTC1,

+ MIPS_INS_MTC2,

+ MIPS_INS_MTHC1,

+ MIPS_INS_MTHI,

+ MIPS_INS_MTHLIP,

+ MIPS_INS_MTLO,

+ MIPS_INS_MTM0,

+ MIPS_INS_MTM1,

+ MIPS_INS_MTM2,

+ MIPS_INS_MTP0,

+ MIPS_INS_MTP1,

+ MIPS_INS_MTP2,

+ MIPS_INS_MUH,

+ MIPS_INS_MUHU,

+ MIPS_INS_MULEQ_S,

+ MIPS_INS_MULEU_S,

+ MIPS_INS_MULQ_RS,

+ MIPS_INS_MULQ_S,

+ MIPS_INS_MULR_Q,

+ MIPS_INS_MULSAQ_S,

+ MIPS_INS_MULSA,

+ MIPS_INS_MULT,

+ MIPS_INS_MULTU,

+ MIPS_INS_MULU,

+ MIPS_INS_MULV,

+ MIPS_INS_MUL_Q,

+ MIPS_INS_MUL_S,

+ MIPS_INS_NLOC,

+ MIPS_INS_NLZC,

+ MIPS_INS_NMADD,

+ MIPS_INS_NMSUB,

+ MIPS_INS_NOR,

+ MIPS_INS_NORI,

+ MIPS_INS_NOT16,

+ MIPS_INS_NOT,

+ MIPS_INS_OR,

+ MIPS_INS_OR16,

+ MIPS_INS_ORI,

+ MIPS_INS_PACKRL,

+ MIPS_INS_PAUSE,

+ MIPS_INS_PCKEV,

+ MIPS_INS_PCKOD,

+ MIPS_INS_PCNT,

+ MIPS_INS_PICK,

+ MIPS_INS_POP,

+ MIPS_INS_PRECEQU,

+ MIPS_INS_PRECEQ,

+ MIPS_INS_PRECEU,

+ MIPS_INS_PRECRQU_S,

+ MIPS_INS_PRECRQ,

+ MIPS_INS_PRECRQ_RS,

+ MIPS_INS_PRECR,

+ MIPS_INS_PRECR_SRA,

+ MIPS_INS_PRECR_SRA_R,

+ MIPS_INS_PREF,

+ MIPS_INS_PREPEND,

+ MIPS_INS_RADDU,

+ MIPS_INS_RDDSP,

+ MIPS_INS_RDHWR,

+ MIPS_INS_REPLV,

+ MIPS_INS_REPL,

+ MIPS_INS_RINT,

+ MIPS_INS_ROTR,

+ MIPS_INS_ROTRV,

+ MIPS_INS_ROUND,

+ MIPS_INS_SAT_S,

+ MIPS_INS_SAT_U,

+ MIPS_INS_SB,

+ MIPS_INS_SB16,

+ MIPS_INS_SC,

+ MIPS_INS_SCD,

+ MIPS_INS_SD,

+ MIPS_INS_SDBBP,

+ MIPS_INS_SDBBP16,

+ MIPS_INS_SDC1,

+ MIPS_INS_SDC2,

+ MIPS_INS_SDC3,

+ MIPS_INS_SDL,

+ MIPS_INS_SDR,

+ MIPS_INS_SDXC1,

+ MIPS_INS_SEB,

+ MIPS_INS_SEH,

+ MIPS_INS_SELEQZ,

+ MIPS_INS_SELNEZ,

+ MIPS_INS_SEL,

+ MIPS_INS_SEQ,

+ MIPS_INS_SEQI,

+ MIPS_INS_SH,

+ MIPS_INS_SH16,

+ MIPS_INS_SHF,

+ MIPS_INS_SHILO,

+ MIPS_INS_SHILOV,

+ MIPS_INS_SHLLV,

+ MIPS_INS_SHLLV_S,

+ MIPS_INS_SHLL,

+ MIPS_INS_SHLL_S,

+ MIPS_INS_SHRAV,

+ MIPS_INS_SHRAV_R,

+ MIPS_INS_SHRA,

+ MIPS_INS_SHRA_R,

+ MIPS_INS_SHRLV,

+ MIPS_INS_SHRL,

+ MIPS_INS_SLDI,

+ MIPS_INS_SLD,

+ MIPS_INS_SLL,

+ MIPS_INS_SLL16,

+ MIPS_INS_SLLI,

+ MIPS_INS_SLLV,

+ MIPS_INS_SLT,

+ MIPS_INS_SLTI,

+ MIPS_INS_SLTIU,

+ MIPS_INS_SLTU,

+ MIPS_INS_SNE,

+ MIPS_INS_SNEI,

+ MIPS_INS_SPLATI,

+ MIPS_INS_SPLAT,

+ MIPS_INS_SRA,

+ MIPS_INS_SRAI,

+ MIPS_INS_SRARI,

+ MIPS_INS_SRAR,

+ MIPS_INS_SRAV,

+ MIPS_INS_SRL,

+ MIPS_INS_SRL16,

+ MIPS_INS_SRLI,

+ MIPS_INS_SRLRI,

+ MIPS_INS_SRLR,

+ MIPS_INS_SRLV,

+ MIPS_INS_SSNOP,

+ MIPS_INS_ST,

+ MIPS_INS_SUBQH,

+ MIPS_INS_SUBQH_R,

+ MIPS_INS_SUBQ,

+ MIPS_INS_SUBQ_S,

+ MIPS_INS_SUBSUS_U,

+ MIPS_INS_SUBSUU_S,

+ MIPS_INS_SUBS_S,

+ MIPS_INS_SUBS_U,

+ MIPS_INS_SUBU16,

+ MIPS_INS_SUBUH,

+ MIPS_INS_SUBUH_R,

+ MIPS_INS_SUBU,

+ MIPS_INS_SUBU_S,

+ MIPS_INS_SUBVI,

+ MIPS_INS_SUBV,

+ MIPS_INS_SUXC1,

+ MIPS_INS_SW,

+ MIPS_INS_SW16,

+ MIPS_INS_SWC1,

+ MIPS_INS_SWC2,

+ MIPS_INS_SWC3,

+ MIPS_INS_SWL,

+ MIPS_INS_SWM16,

+ MIPS_INS_SWM32,

+ MIPS_INS_SWP,

+ MIPS_INS_SWR,

+ MIPS_INS_SWXC1,

+ MIPS_INS_SYNC,

+ MIPS_INS_SYNCI,

+ MIPS_INS_SYSCALL,

+ MIPS_INS_TEQ,

+ MIPS_INS_TEQI,

+ MIPS_INS_TGE,

+ MIPS_INS_TGEI,

+ MIPS_INS_TGEIU,

+ MIPS_INS_TGEU,

+ MIPS_INS_TLBP,

+ MIPS_INS_TLBR,

+ MIPS_INS_TLBWI,

+ MIPS_INS_TLBWR,

+ MIPS_INS_TLT,

+ MIPS_INS_TLTI,

+ MIPS_INS_TLTIU,

+ MIPS_INS_TLTU,

+ MIPS_INS_TNE,

+ MIPS_INS_TNEI,

+ MIPS_INS_TRUNC,

+ MIPS_INS_V3MULU,

+ MIPS_INS_VMM0,

+ MIPS_INS_VMULU,

+ MIPS_INS_VSHF,

+ MIPS_INS_WAIT,

+ MIPS_INS_WRDSP,

+ MIPS_INS_WSBH,

+ MIPS_INS_XOR,

+ MIPS_INS_XOR16,

+ MIPS_INS_XORI,

+

+ //> some alias instructions

+ MIPS_INS_NOP,

+ MIPS_INS_NEGU,

+

+ //> special instructions

+ MIPS_INS_JALR_HB, // jump and link with Hazard Barrier

+ MIPS_INS_JR_HB, // jump register with Hazard Barrier

+

+ MIPS_INS_ENDING,

+} mips_insn;

+

+/// Group of MIPS instructions

+typedef enum mips_insn_group {

+ MIPS_GRP_INVALID = 0, ///< = CS_GRP_INVALID

+

+ // Generic groups

+ // all jump instructions (conditional+direct+indirect jumps)

+ MIPS_GRP_JUMP, ///< = CS_GRP_JUMP

+ // all call instructions

+ MIPS_GRP_CALL, ///< = CS_GRP_CALL

+ // all return instructions

+ MIPS_GRP_RET, ///< = CS_GRP_RET

+ // all interrupt instructions (int+syscall)

+ MIPS_GRP_INT, ///< = CS_GRP_INT

+ // all interrupt return instructions

+ MIPS_GRP_IRET, ///< = CS_GRP_IRET

+ // all privileged instructions

+ MIPS_GRP_PRIVILEGE, ///< = CS_GRP_PRIVILEGE

+ // all relative branching instructions

+ MIPS_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE

+

+ // Architecture-specific groups

+ MIPS_GRP_BITCOUNT = 128,

+ MIPS_GRP_DSP,

+ MIPS_GRP_DSPR2,

+ MIPS_GRP_FPIDX,

+ MIPS_GRP_MSA,

+ MIPS_GRP_MIPS32R2,

+ MIPS_GRP_MIPS64,

+ MIPS_GRP_MIPS64R2,

+ MIPS_GRP_SEINREG,

+ MIPS_GRP_STDENC,

+ MIPS_GRP_SWAP,

+ MIPS_GRP_MICROMIPS,

+ MIPS_GRP_MIPS16MODE,

+ MIPS_GRP_FP64BIT,

+ MIPS_GRP_NONANSFPMATH,

+ MIPS_GRP_NOTFP64BIT,

+ MIPS_GRP_NOTINMICROMIPS,

+ MIPS_GRP_NOTNACL,

+ MIPS_GRP_NOTMIPS32R6,

+ MIPS_GRP_NOTMIPS64R6,

+ MIPS_GRP_CNMIPS,

+ MIPS_GRP_MIPS32,

+ MIPS_GRP_MIPS32R6,

+ MIPS_GRP_MIPS64R6,

+ MIPS_GRP_MIPS2,

+ MIPS_GRP_MIPS3,

+ MIPS_GRP_MIPS3_32,

+ MIPS_GRP_MIPS3_32R2,

+ MIPS_GRP_MIPS4_32,

+ MIPS_GRP_MIPS4_32R2,

+ MIPS_GRP_MIPS5_32R2,

+ MIPS_GRP_GP32BIT,

+ MIPS_GRP_GP64BIT,

+

+ MIPS_GRP_ENDING,

+} mips_insn_group;

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif

+#ifndef CAPSTONE_MOS65XX_H

+#define CAPSTONE_MOS65XX_H

+

+/* Capstone Disassembly Engine */

+/* By Sebastian Macke <sebastian@macke.de, 2018 */

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+#include "platform.h"

+

+/// MOS65XX registers and special registers

+typedef enum mos65xx_reg {

+ MOS65XX_REG_INVALID = 0,

+ MOS65XX_REG_ACC, ///< accumulator

+ MOS65XX_REG_X, ///< X index register

+ MOS65XX_REG_Y, ///< Y index register

+ MOS65XX_REG_P, ///< status register

+ MOS65XX_REG_SP, ///< stack pointer register

+ MOS65XX_REG_DP, ///< direct page register

+ MOS65XX_REG_B, ///< data bank register

+ MOS65XX_REG_K, ///< program bank register

+ MOS65XX_REG_ENDING, // <-- mark the end of the list of registers

+} mos65xx_reg;

+

+/// MOS65XX Addressing Modes

+typedef enum mos65xx_address_mode {

+ MOS65XX_AM_NONE = 0, ///< No address mode.

+ MOS65XX_AM_IMP, ///< implied addressing (no addressing mode)

+ MOS65XX_AM_ACC, ///< accumulator addressing

+ MOS65XX_AM_IMM, ///< 8/16 Bit immediate value

+ MOS65XX_AM_REL, ///< relative addressing used by branches

+ MOS65XX_AM_INT, ///< interrupt addressing

+ MOS65XX_AM_BLOCK, ///< memory block addressing

+ MOS65XX_AM_ZP, ///< zeropage addressing

+ MOS65XX_AM_ZP_X, ///< indexed zeropage addressing by the X index register

+ MOS65XX_AM_ZP_Y, ///< indexed zeropage addressing by the Y index register

+ MOS65XX_AM_ZP_REL, ///< zero page address, branch relative address

+ MOS65XX_AM_ZP_IND, ///< indirect zeropage addressing

+ MOS65XX_AM_ZP_X_IND, ///< indexed zeropage indirect addressing by the X index register

+ MOS65XX_AM_ZP_IND_Y, ///< indirect zeropage indexed addressing by the Y index register

+ MOS65XX_AM_ZP_IND_LONG, ///< zeropage indirect long addressing

+ MOS65XX_AM_ZP_IND_LONG_Y, ///< zeropage indirect long addressing indexed by Y register

+ MOS65XX_AM_ABS, ///< absolute addressing

+ MOS65XX_AM_ABS_X, ///< indexed absolute addressing by the X index register

+ MOS65XX_AM_ABS_Y, ///< indexed absolute addressing by the Y index register

+ MOS65XX_AM_ABS_IND, ///< absolute indirect addressing

+ MOS65XX_AM_ABS_X_IND, ///< indexed absolute indirect addressing by the X index register

+ MOS65XX_AM_ABS_IND_LONG, ///< absolute indirect long addressing

+ MOS65XX_AM_ABS_LONG, ///< absolute long address mode

+ MOS65XX_AM_ABS_LONG_X, ///< absolute long address mode, indexed by X register

+ MOS65XX_AM_SR, ///< stack relative addressing

+ MOS65XX_AM_SR_IND_Y, ///< indirect stack relative addressing indexed by the Y index register

+} mos65xx_address_mode;

+

+/// MOS65XX instruction

+typedef enum mos65xx_insn {

+ MOS65XX_INS_INVALID = 0,

+ MOS65XX_INS_ADC,

+ MOS65XX_INS_AND,

+ MOS65XX_INS_ASL,

+ MOS65XX_INS_BBR,

+ MOS65XX_INS_BBS,

+ MOS65XX_INS_BCC,

+ MOS65XX_INS_BCS,

+ MOS65XX_INS_BEQ,

+ MOS65XX_INS_BIT,

+ MOS65XX_INS_BMI,

+ MOS65XX_INS_BNE,

+ MOS65XX_INS_BPL,

+ MOS65XX_INS_BRA,

+ MOS65XX_INS_BRK,

+ MOS65XX_INS_BRL,

+ MOS65XX_INS_BVC,

+ MOS65XX_INS_BVS,

+ MOS65XX_INS_CLC,

+ MOS65XX_INS_CLD,

+ MOS65XX_INS_CLI,

+ MOS65XX_INS_CLV,

+ MOS65XX_INS_CMP,

+ MOS65XX_INS_COP,

+ MOS65XX_INS_CPX,

+ MOS65XX_INS_CPY,

+ MOS65XX_INS_DEC,

+ MOS65XX_INS_DEX,

+ MOS65XX_INS_DEY,

+ MOS65XX_INS_EOR,

+ MOS65XX_INS_INC,

+ MOS65XX_INS_INX,

+ MOS65XX_INS_INY,

+ MOS65XX_INS_JML,

+ MOS65XX_INS_JMP,

+ MOS65XX_INS_JSL,

+ MOS65XX_INS_JSR,

+ MOS65XX_INS_LDA,

+ MOS65XX_INS_LDX,

+ MOS65XX_INS_LDY,

+ MOS65XX_INS_LSR,

+ MOS65XX_INS_MVN,

+ MOS65XX_INS_MVP,

+ MOS65XX_INS_NOP,

+ MOS65XX_INS_ORA,

+ MOS65XX_INS_PEA,

+ MOS65XX_INS_PEI,

+ MOS65XX_INS_PER,

+ MOS65XX_INS_PHA,

+ MOS65XX_INS_PHB,

+ MOS65XX_INS_PHD,

+ MOS65XX_INS_PHK,

+ MOS65XX_INS_PHP,

+ MOS65XX_INS_PHX,

+ MOS65XX_INS_PHY,

+ MOS65XX_INS_PLA,

+ MOS65XX_INS_PLB,

+ MOS65XX_INS_PLD,

+ MOS65XX_INS_PLP,

+ MOS65XX_INS_PLX,

+ MOS65XX_INS_PLY,

+ MOS65XX_INS_REP,

+ MOS65XX_INS_RMB,

+ MOS65XX_INS_ROL,

+ MOS65XX_INS_ROR,

+ MOS65XX_INS_RTI,

+ MOS65XX_INS_RTL,

+ MOS65XX_INS_RTS,

+ MOS65XX_INS_SBC,

+ MOS65XX_INS_SEC,

+ MOS65XX_INS_SED,

+ MOS65XX_INS_SEI,

+ MOS65XX_INS_SEP,

+ MOS65XX_INS_SMB,

+ MOS65XX_INS_STA,

+ MOS65XX_INS_STP,

+ MOS65XX_INS_STX,

+ MOS65XX_INS_STY,

+ MOS65XX_INS_STZ,

+ MOS65XX_INS_TAX,

+ MOS65XX_INS_TAY,

+ MOS65XX_INS_TCD,

+ MOS65XX_INS_TCS,

+ MOS65XX_INS_TDC,

+ MOS65XX_INS_TRB,

+ MOS65XX_INS_TSB,

+ MOS65XX_INS_TSC,

+ MOS65XX_INS_TSX,

+ MOS65XX_INS_TXA,

+ MOS65XX_INS_TXS,

+ MOS65XX_INS_TXY,

+ MOS65XX_INS_TYA,

+ MOS65XX_INS_TYX,

+ MOS65XX_INS_WAI,

+ MOS65XX_INS_WDM,

+ MOS65XX_INS_XBA,

+ MOS65XX_INS_XCE,

+ MOS65XX_INS_ENDING, // <-- mark the end of the list of instructions

+} mos65xx_insn;

+

+/// Group of MOS65XX instructions

+typedef enum mos65xx_group_type {

+ MOS65XX_GRP_INVALID = 0, ///< CS_GRP_INVALID

+ MOS65XX_GRP_JUMP, ///< = CS_GRP_JUMP

+ MOS65XX_GRP_CALL, ///< = CS_GRP_RET

+ MOS65XX_GRP_RET, ///< = CS_GRP_RET

+ MOS65XX_GRP_INT, ///< = CS_GRP_INT

+ MOS65XX_GRP_IRET = 5, ///< = CS_GRP_IRET

+ MOS65XX_GRP_BRANCH_RELATIVE = 6, ///< = CS_GRP_BRANCH_RELATIVE

+ MOS65XX_GRP_ENDING,// <-- mark the end of the list of groups

+} mos65xx_group_type;

+

+/// Operand type for instruction's operands

+typedef enum mos65xx_op_type {

+ MOS65XX_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).

+ MOS65XX_OP_REG, ///< = CS_OP_REG (Register operand).

+ MOS65XX_OP_IMM, ///< = CS_OP_IMM (Immediate operand).

+ MOS65XX_OP_MEM, ///< = CS_OP_MEM (Memory operand).

+} mos65xx_op_type;

+

+/// Instruction operand

+typedef struct cs_mos65xx_op {

+ mos65xx_op_type type; ///< operand type

+ union {

+ mos65xx_reg reg; ///< register value for REG operand

+ uint16_t imm; ///< immediate value for IMM operand

+ uint32_t mem; ///< base/index/scale/disp value for MEM operand

+ };

+} cs_mos65xx_op;

+

+/// The MOS65XX address mode and it's operands

+typedef struct cs_mos65xx {

+ mos65xx_address_mode am;

+ bool modifies_flags;

+

+ /// Number of operands of this instruction,

+ /// or 0 when instruction has no operand.

+ uint8_t op_count;

+ cs_mos65xx_op operands[3]; ///< operands for this instruction.

+} cs_mos65xx;

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif //CAPSTONE_MOS65XX_H

+/* Capstone Disassembly Engine */

+/* By Axel Souchet & Nguyen Anh Quynh, 2014 */

+

+#ifndef CAPSTONE_PLATFORM_H

+#define CAPSTONE_PLATFORM_H

+

+

+// handle C99 issue (for pre-2013 VisualStudio)

+#if !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64))

+// MSVC

+

+// stdbool.h

+#if (_MSC_VER < 1800) || defined(_KERNEL_MODE)

+// this system does not have stdbool.h

+#ifndef __cplusplus

+typedef unsigned char bool;

+#define false 0

+#define true 1

+#endif // __cplusplus

+

+#else

+// VisualStudio 2013+ -> C99 is supported

+#include <stdbool.h>

+#endif // (_MSC_VER < 1800) || defined(_KERNEL_MODE)

+

+#else

+// not MSVC -> C99 is supported

+#include <stdbool.h>

+#endif // !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64))

+

+

+// handle inttypes.h / stdint.h compatibility

+#if defined(_WIN32_WCE) && (_WIN32_WCE < 0x800)

+#include "windowsce/stdint.h"

+#endif // defined(_WIN32_WCE) && (_WIN32_WCE < 0x800)

+

+#if defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE)))

+// this system does not have inttypes.h

+

+#if defined(_MSC_VER) && (_MSC_VER <= 1600 || defined(_KERNEL_MODE))

+// this system does not have stdint.h

+typedef signed char int8_t;

+typedef signed short int16_t;

+typedef signed int int32_t;

+typedef unsigned char uint8_t;

+typedef unsigned short uint16_t;

+typedef unsigned int uint32_t;

+typedef signed long long int64_t;

+typedef unsigned long long uint64_t;

+#endif // defined(_MSC_VER) && (_MSC_VER <= 1600 || defined(_KERNEL_MODE))

+

+#if defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE))

+#define INT8_MIN (-127i8 - 1)

+#define INT16_MIN (-32767i16 - 1)

+#define INT32_MIN (-2147483647i32 - 1)

+#define INT64_MIN (-9223372036854775807i64 - 1)

+#define INT8_MAX 127i8

+#define INT16_MAX 32767i16

+#define INT32_MAX 2147483647i32

+#define INT64_MAX 9223372036854775807i64

+#define UINT8_MAX 0xffui8

+#define UINT16_MAX 0xffffui16

+#define UINT32_MAX 0xffffffffui32

+#define UINT64_MAX 0xffffffffffffffffui64

+#endif // defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE))

+

+#ifdef CAPSTONE_HAS_OSXKERNEL

+// this system has stdint.h

+#include <stdint.h>

+#endif

+

+#define __PRI_8_LENGTH_MODIFIER__ "hh"

+#define __PRI_64_LENGTH_MODIFIER__ "ll"

+

+#define PRId8 __PRI_8_LENGTH_MODIFIER__ "d"

+#define PRIi8 __PRI_8_LENGTH_MODIFIER__ "i"

+#define PRIo8 __PRI_8_LENGTH_MODIFIER__ "o"

+#define PRIu8 __PRI_8_LENGTH_MODIFIER__ "u"

+#define PRIx8 __PRI_8_LENGTH_MODIFIER__ "x"

+#define PRIX8 __PRI_8_LENGTH_MODIFIER__ "X"

+

+#define PRId16 "hd"

+#define PRIi16 "hi"

+#define PRIo16 "ho"

+#define PRIu16 "hu"

+#define PRIx16 "hx"

+#define PRIX16 "hX"

+

+#if defined(_MSC_VER) && _MSC_VER <= 1700

+#define PRId32 "ld"

+#define PRIi32 "li"

+#define PRIo32 "lo"

+#define PRIu32 "lu"

+#define PRIx32 "lx"

+#define PRIX32 "lX"

+#else // OSX

+#define PRId32 "d"

+#define PRIi32 "i"

+#define PRIo32 "o"

+#define PRIu32 "u"

+#define PRIx32 "x"

+#define PRIX32 "X"

+#endif // defined(_MSC_VER) && _MSC_VER <= 1700

+

+#if defined(_MSC_VER) && _MSC_VER <= 1700

+// redefine functions from inttypes.h used in cstool

+#define strtoull _strtoui64

+#endif

+

+#define PRId64 __PRI_64_LENGTH_MODIFIER__ "d"

+#define PRIi64 __PRI_64_LENGTH_MODIFIER__ "i"

+#define PRIo64 __PRI_64_LENGTH_MODIFIER__ "o"

+#define PRIu64 __PRI_64_LENGTH_MODIFIER__ "u"

+#define PRIx64 __PRI_64_LENGTH_MODIFIER__ "x"

+#define PRIX64 __PRI_64_LENGTH_MODIFIER__ "X"

+

+#else

+// this system has inttypes.h by default

+#include <inttypes.h>

+#endif // defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE)))

+

+#endif

+#ifndef CAPSTONE_PPC_H

+#define CAPSTONE_PPC_H

+

+/* Capstone Disassembly Engine */

+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+#include "platform.h"

+

+#ifdef _MSC_VER

+#pragma warning(disable:4201)

+#endif

+

+/// PPC branch codes for some branch instructions

+typedef enum ppc_bc {

+ PPC_BC_INVALID = 0,

+ PPC_BC_LT = (0 << 5) | 12,

+ PPC_BC_LE = (1 << 5) | 4,

+ PPC_BC_EQ = (2 << 5) | 12,

+ PPC_BC_GE = (0 << 5) | 4,

+ PPC_BC_GT = (1 << 5) | 12,

+ PPC_BC_NE = (2 << 5) | 4,

+ PPC_BC_UN = (3 << 5) | 12,

+ PPC_BC_NU = (3 << 5) | 4,

+

+ // extra conditions

+ PPC_BC_SO = (4 << 5) | 12, ///< summary overflow

+ PPC_BC_NS = (4 << 5) | 4, ///< not summary overflow

+} ppc_bc;

+

+/// PPC branch hint for some branch instructions

+typedef enum ppc_bh {

+ PPC_BH_INVALID = 0, ///< no hint

+ PPC_BH_PLUS, ///< PLUS hint

+ PPC_BH_MINUS, ///< MINUS hint

+} ppc_bh;

+

+/// Operand type for instruction's operands

+typedef enum ppc_op_type {

+ PPC_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).

+ PPC_OP_REG, ///< = CS_OP_REG (Register operand).

+ PPC_OP_IMM, ///< = CS_OP_IMM (Immediate operand).

+ PPC_OP_MEM, ///< = CS_OP_MEM (Memory operand).

+ PPC_OP_CRX = 64, ///< Condition Register field

+} ppc_op_type;

+

+/// PPC registers

+typedef enum ppc_reg {

+ PPC_REG_INVALID = 0,

+

+ PPC_REG_CARRY = 2,

+ PPC_REG_CTR = 3,

+ PPC_REG_LR = 5,

+ PPC_REG_RM = 6,

+ PPC_REG_VRSAVE = 8,

+ PPC_REG_XER = 9,

+ PPC_REG_ZERO = 10,

+ PPC_REG_CR0 = 12,

+ PPC_REG_CR1 = 13,

+ PPC_REG_CR2 = 14,

+ PPC_REG_CR3 = 15,

+ PPC_REG_CR4 = 16,

+ PPC_REG_CR5 = 17,

+ PPC_REG_CR6 = 18,

+ PPC_REG_CR7 = 19,

+ PPC_REG_CTR8 = 20,

+ PPC_REG_F0 = 21,

+ PPC_REG_F1 = 22,

+ PPC_REG_F2 = 23,

+ PPC_REG_F3 = 24,

+ PPC_REG_F4 = 25,

+ PPC_REG_F5 = 26,

+ PPC_REG_F6 = 27,

+ PPC_REG_F7 = 28,

+ PPC_REG_F8 = 29,

+ PPC_REG_F9 = 30,

+ PPC_REG_F10 = 31,

+ PPC_REG_F11 = 32,

+ PPC_REG_F12 = 33,

+ PPC_REG_F13 = 34,

+ PPC_REG_F14 = 35,

+ PPC_REG_F15 = 36,

+ PPC_REG_F16 = 37,

+ PPC_REG_F17 = 38,

+ PPC_REG_F18 = 39,

+ PPC_REG_F19 = 40,

+ PPC_REG_F20 = 41,

+ PPC_REG_F21 = 42,

+ PPC_REG_F22 = 43,

+ PPC_REG_F23 = 44,

+ PPC_REG_F24 = 45,

+ PPC_REG_F25 = 46,

+ PPC_REG_F26 = 47,

+ PPC_REG_F27 = 48,

+ PPC_REG_F28 = 49,

+ PPC_REG_F29 = 50,

+ PPC_REG_F30 = 51,

+ PPC_REG_F31 = 52,

+ PPC_REG_LR8 = 54,

+ PPC_REG_Q0 = 55,

+ PPC_REG_Q1 = 56,

+ PPC_REG_Q2 = 57,

+ PPC_REG_Q3 = 58,

+ PPC_REG_Q4 = 59,

+ PPC_REG_Q5 = 60,

+ PPC_REG_Q6 = 61,

+ PPC_REG_Q7 = 62,

+ PPC_REG_Q8 = 63,

+ PPC_REG_Q9 = 64,

+ PPC_REG_Q10 = 65,

+ PPC_REG_Q11 = 66,

+ PPC_REG_Q12 = 67,

+ PPC_REG_Q13 = 68,

+ PPC_REG_Q14 = 69,

+ PPC_REG_Q15 = 70,

+ PPC_REG_Q16 = 71,

+ PPC_REG_Q17 = 72,

+ PPC_REG_Q18 = 73,

+ PPC_REG_Q19 = 74,

+ PPC_REG_Q20 = 75,

+ PPC_REG_Q21 = 76,

+ PPC_REG_Q22 = 77,

+ PPC_REG_Q23 = 78,

+ PPC_REG_Q24 = 79,

+ PPC_REG_Q25 = 80,

+ PPC_REG_Q26 = 81,

+ PPC_REG_Q27 = 82,

+ PPC_REG_Q28 = 83,

+ PPC_REG_Q29 = 84,

+ PPC_REG_Q30 = 85,

+ PPC_REG_Q31 = 86,

+ PPC_REG_R0 = 87,

+ PPC_REG_R1 = 88,

+ PPC_REG_R2 = 89,

+ PPC_REG_R3 = 90,

+ PPC_REG_R4 = 91,

+ PPC_REG_R5 = 92,

+ PPC_REG_R6 = 93,

+ PPC_REG_R7 = 94,

+ PPC_REG_R8 = 95,

+ PPC_REG_R9 = 96,

+ PPC_REG_R10 = 97,

+ PPC_REG_R11 = 98,

+ PPC_REG_R12 = 99,

+ PPC_REG_R13 = 100,

+ PPC_REG_R14 = 101,

+ PPC_REG_R15 = 102,

+ PPC_REG_R16 = 103,

+ PPC_REG_R17 = 104,

+ PPC_REG_R18 = 105,

+ PPC_REG_R19 = 106,

+ PPC_REG_R20 = 107,

+ PPC_REG_R21 = 108,

+ PPC_REG_R22 = 109,

+ PPC_REG_R23 = 110,

+ PPC_REG_R24 = 111,

+ PPC_REG_R25 = 112,

+ PPC_REG_R26 = 113,

+ PPC_REG_R27 = 114,

+ PPC_REG_R28 = 115,

+ PPC_REG_R29 = 116,

+ PPC_REG_R30 = 117,

+ PPC_REG_R31 = 118,

+ PPC_REG_V0 = 151,

+ PPC_REG_V1 = 152,

+ PPC_REG_V2 = 153,

+ PPC_REG_V3 = 154,

+ PPC_REG_V4 = 155,

+ PPC_REG_V5 = 156,

+ PPC_REG_V6 = 157,

+ PPC_REG_V7 = 158,

+ PPC_REG_V8 = 159,

+ PPC_REG_V9 = 160,

+ PPC_REG_V10 = 161,

+ PPC_REG_V11 = 162,

+ PPC_REG_V12 = 163,

+ PPC_REG_V13 = 164,

+ PPC_REG_V14 = 165,

+ PPC_REG_V15 = 166,

+ PPC_REG_V16 = 167,

+ PPC_REG_V17 = 168,

+ PPC_REG_V18 = 169,

+ PPC_REG_V19 = 170,

+ PPC_REG_V20 = 171,

+ PPC_REG_V21 = 172,

+ PPC_REG_V22 = 173,

+ PPC_REG_V23 = 174,

+ PPC_REG_V24 = 175,

+ PPC_REG_V25 = 176,

+ PPC_REG_V26 = 177,

+ PPC_REG_V27 = 178,

+ PPC_REG_V28 = 179,

+ PPC_REG_V29 = 180,

+ PPC_REG_V30 = 181,

+ PPC_REG_V31 = 182,

+ PPC_REG_VS0 = 215,

+ PPC_REG_VS1 = 216,

+ PPC_REG_VS2 = 217,

+ PPC_REG_VS3 = 218,

+ PPC_REG_VS4 = 219,

+ PPC_REG_VS5 = 220,

+ PPC_REG_VS6 = 221,

+ PPC_REG_VS7 = 222,

+ PPC_REG_VS8 = 223,

+ PPC_REG_VS9 = 224,

+ PPC_REG_VS10 = 225,

+ PPC_REG_VS11 = 226,

+ PPC_REG_VS12 = 227,

+ PPC_REG_VS13 = 228,

+ PPC_REG_VS14 = 229,

+ PPC_REG_VS15 = 230,

+ PPC_REG_VS16 = 231,

+ PPC_REG_VS17 = 232,

+ PPC_REG_VS18 = 233,

+ PPC_REG_VS19 = 234,

+ PPC_REG_VS20 = 235,

+ PPC_REG_VS21 = 236,

+ PPC_REG_VS22 = 237,

+ PPC_REG_VS23 = 238,

+ PPC_REG_VS24 = 239,

+ PPC_REG_VS25 = 240,

+ PPC_REG_VS26 = 241,

+ PPC_REG_VS27 = 242,

+ PPC_REG_VS28 = 243,

+ PPC_REG_VS29 = 244,

+ PPC_REG_VS30 = 245,

+ PPC_REG_VS31 = 246,

+ PPC_REG_VS32 = 247,

+ PPC_REG_VS33 = 248,

+ PPC_REG_VS34 = 249,

+ PPC_REG_VS35 = 250,

+ PPC_REG_VS36 = 251,

+ PPC_REG_VS37 = 252,

+ PPC_REG_VS38 = 253,

+ PPC_REG_VS39 = 254,

+ PPC_REG_VS40 = 255,

+ PPC_REG_VS41 = 256,

+ PPC_REG_VS42 = 257,

+ PPC_REG_VS43 = 258,

+ PPC_REG_VS44 = 259,

+ PPC_REG_VS45 = 260,

+ PPC_REG_VS46 = 261,

+ PPC_REG_VS47 = 262,

+ PPC_REG_VS48 = 263,

+ PPC_REG_VS49 = 264,

+ PPC_REG_VS50 = 265,

+ PPC_REG_VS51 = 266,

+ PPC_REG_VS52 = 267,

+ PPC_REG_VS53 = 268,

+ PPC_REG_VS54 = 269,

+ PPC_REG_VS55 = 270,

+ PPC_REG_VS56 = 271,

+ PPC_REG_VS57 = 272,

+ PPC_REG_VS58 = 273,

+ PPC_REG_VS59 = 274,

+ PPC_REG_VS60 = 275,

+ PPC_REG_VS61 = 276,

+ PPC_REG_VS62 = 277,

+ PPC_REG_VS63 = 278,

+

+ PPC_REG_CR0EQ = 312,

+ PPC_REG_CR1EQ = 313,

+ PPC_REG_CR2EQ = 314,

+ PPC_REG_CR3EQ = 315,

+ PPC_REG_CR4EQ = 316,

+ PPC_REG_CR5EQ = 317,

+ PPC_REG_CR6EQ = 318,

+ PPC_REG_CR7EQ = 319,

+ PPC_REG_CR0GT = 320,

+ PPC_REG_CR1GT = 321,

+ PPC_REG_CR2GT = 322,

+ PPC_REG_CR3GT = 323,

+ PPC_REG_CR4GT = 324,

+ PPC_REG_CR5GT = 325,

+ PPC_REG_CR6GT = 326,

+ PPC_REG_CR7GT = 327,

+ PPC_REG_CR0LT = 328,

+ PPC_REG_CR1LT = 329,

+ PPC_REG_CR2LT = 330,

+ PPC_REG_CR3LT = 331,

+ PPC_REG_CR4LT = 332,

+ PPC_REG_CR5LT = 333,

+ PPC_REG_CR6LT = 334,

+ PPC_REG_CR7LT = 335,

+ PPC_REG_CR0UN = 336,

+ PPC_REG_CR1UN = 337,

+ PPC_REG_CR2UN = 338,

+ PPC_REG_CR3UN = 339,

+ PPC_REG_CR4UN = 340,

+ PPC_REG_CR5UN = 341,

+ PPC_REG_CR6UN = 342,

+ PPC_REG_CR7UN = 343,

+

+ PPC_REG_ENDING, // <-- mark the end of the list of registers

+} ppc_reg;

+

+/// Instruction's operand referring to memory

+/// This is associated with PPC_OP_MEM operand type above

+typedef struct ppc_op_mem {

+ ppc_reg base; ///< base register

+ int32_t disp; ///< displacement/offset value

+} ppc_op_mem;

+

+typedef struct ppc_op_crx {

+ unsigned int scale;

+ ppc_reg reg;

+ ppc_bc cond;

+} ppc_op_crx;

+

+/// Instruction operand

+typedef struct cs_ppc_op {

+ ppc_op_type type; ///< operand type

+ union {

+ ppc_reg reg; ///< register value for REG operand

+ int64_t imm; ///< immediate value for IMM operand

+ ppc_op_mem mem; ///< base/disp value for MEM operand

+ ppc_op_crx crx; ///< operand with condition register

+ };

+} cs_ppc_op;

+

+/// Instruction structure

+typedef struct cs_ppc {

+ /// branch code for branch instructions

+ ppc_bc bc;

+

+ /// branch hint for branch instructions

+ ppc_bh bh;

+

+ /// if update_cr0 = True, then this 'dot' insn updates CR0

+ bool update_cr0;

+

+ /// Number of operands of this instruction,

+ /// or 0 when instruction has no operand.

+ uint8_t op_count;

+ cs_ppc_op operands[8]; ///< operands for this instruction.

+} cs_ppc;

+

+/// PPC instruction

+typedef enum ppc_insn {

+ PPC_INS_INVALID = 0,

+

+ PPC_INS_ADD,

+ PPC_INS_ADDC,

+ PPC_INS_ADDE,

+ PPC_INS_ADDI,

+ PPC_INS_ADDIC,

+ PPC_INS_ADDIS,

+ PPC_INS_ADDME,

+ PPC_INS_ADDPCIS,

+ PPC_INS_ADDZE,

+ PPC_INS_AND,

+ PPC_INS_ANDC,

+ PPC_INS_ANDI,

+ PPC_INS_ANDIS,

+ PPC_INS_ATTN,

+ PPC_INS_B,

+ PPC_INS_BA,

+ PPC_INS_BC,

+ PPC_INS_BCA,

+ PPC_INS_BCCTR,

+ PPC_INS_BCCTRL,

+ PPC_INS_BCDCFN,

+ PPC_INS_BCDCFSQ,

+ PPC_INS_BCDCFZ,

+ PPC_INS_BCDCPSGN,

+ PPC_INS_BCDCTN,

+ PPC_INS_BCDCTSQ,

+ PPC_INS_BCDCTZ,

+ PPC_INS_BCDS,

+ PPC_INS_BCDSETSGN,

+ PPC_INS_BCDSR,

+ PPC_INS_BCDTRUNC,

+ PPC_INS_BCDUS,

+ PPC_INS_BCDUTRUNC,

+ PPC_INS_BCL,

+ PPC_INS_BCLA,

+ PPC_INS_BCLR,

+ PPC_INS_BCLRL,

+ PPC_INS_BCTR,

+ PPC_INS_BCTRL,

+ PPC_INS_BDNZ,

+ PPC_INS_BDNZA,

+ PPC_INS_BDNZF,

+ PPC_INS_BDNZFA,

+ PPC_INS_BDNZFL,

+ PPC_INS_BDNZFLA,

+ PPC_INS_BDNZFLR,

+ PPC_INS_BDNZFLRL,

+ PPC_INS_BDNZL,

+ PPC_INS_BDNZLA,

+ PPC_INS_BDNZLR,

+ PPC_INS_BDNZLRL,

+ PPC_INS_BDNZT,

+ PPC_INS_BDNZTA,

+ PPC_INS_BDNZTL,

+ PPC_INS_BDNZTLA,

+ PPC_INS_BDNZTLR,

+ PPC_INS_BDNZTLRL,

+ PPC_INS_BDZ,

+ PPC_INS_BDZA,

+ PPC_INS_BDZF,

+ PPC_INS_BDZFA,

+ PPC_INS_BDZFL,

+ PPC_INS_BDZFLA,

+ PPC_INS_BDZFLR,

+ PPC_INS_BDZFLRL,

+ PPC_INS_BDZL,

+ PPC_INS_BDZLA,

+ PPC_INS_BDZLR,

+ PPC_INS_BDZLRL,

+ PPC_INS_BDZT,

+ PPC_INS_BDZTA,

+ PPC_INS_BDZTL,

+ PPC_INS_BDZTLA,

+ PPC_INS_BDZTLR,

+ PPC_INS_BDZTLRL,

+ PPC_INS_BEQ,

+ PPC_INS_BEQA,

+ PPC_INS_BEQCTR,

+ PPC_INS_BEQCTRL,

+ PPC_INS_BEQL,

+ PPC_INS_BEQLA,

+ PPC_INS_BEQLR,

+ PPC_INS_BEQLRL,

+ PPC_INS_BF,

+ PPC_INS_BFA,

+ PPC_INS_BFCTR,

+ PPC_INS_BFCTRL,

+ PPC_INS_BFL,

+ PPC_INS_BFLA,

+ PPC_INS_BFLR,

+ PPC_INS_BFLRL,

+ PPC_INS_BGE,

+ PPC_INS_BGEA,

+ PPC_INS_BGECTR,

+ PPC_INS_BGECTRL,

+ PPC_INS_BGEL,

+ PPC_INS_BGELA,

+ PPC_INS_BGELR,

+ PPC_INS_BGELRL,

+ PPC_INS_BGT,

+ PPC_INS_BGTA,

+ PPC_INS_BGTCTR,

+ PPC_INS_BGTCTRL,

+ PPC_INS_BGTL,

+ PPC_INS_BGTLA,

+ PPC_INS_BGTLR,

+ PPC_INS_BGTLRL,

+ PPC_INS_BL,

+ PPC_INS_BLA,

+ PPC_INS_BLE,

+ PPC_INS_BLEA,

+ PPC_INS_BLECTR,

+ PPC_INS_BLECTRL,

+ PPC_INS_BLEL,

+ PPC_INS_BLELA,

+ PPC_INS_BLELR,

+ PPC_INS_BLELRL,

+ PPC_INS_BLR,

+ PPC_INS_BLRL,

+ PPC_INS_BLT,

+ PPC_INS_BLTA,

+ PPC_INS_BLTCTR,

+ PPC_INS_BLTCTRL,

+ PPC_INS_BLTL,

+ PPC_INS_BLTLA,

+ PPC_INS_BLTLR,

+ PPC_INS_BLTLRL,

+ PPC_INS_BNE,

+ PPC_INS_BNEA,

+ PPC_INS_BNECTR,

+ PPC_INS_BNECTRL,

+ PPC_INS_BNEL,

+ PPC_INS_BNELA,

+ PPC_INS_BNELR,

+ PPC_INS_BNELRL,

+ PPC_INS_BNG,

+ PPC_INS_BNGA,

+ PPC_INS_BNGCTR,

+ PPC_INS_BNGCTRL,

+ PPC_INS_BNGL,

+ PPC_INS_BNGLA,

+ PPC_INS_BNGLR,

+ PPC_INS_BNGLRL,

+ PPC_INS_BNL,

+ PPC_INS_BNLA,

+ PPC_INS_BNLCTR,

+ PPC_INS_BNLCTRL,

+ PPC_INS_BNLL,

+ PPC_INS_BNLLA,

+ PPC_INS_BNLLR,

+ PPC_INS_BNLLRL,

+ PPC_INS_BNS,

+ PPC_INS_BNSA,

+ PPC_INS_BNSCTR,

+ PPC_INS_BNSCTRL,

+ PPC_INS_BNSL,

+ PPC_INS_BNSLA,

+ PPC_INS_BNSLR,

+ PPC_INS_BNSLRL,

+ PPC_INS_BNU,

+ PPC_INS_BNUA,

+ PPC_INS_BNUCTR,

+ PPC_INS_BNUCTRL,

+ PPC_INS_BNUL,

+ PPC_INS_BNULA,

+ PPC_INS_BNULR,

+ PPC_INS_BNULRL,

+ PPC_INS_BPERMD,

+ PPC_INS_BRINC,

+ PPC_INS_BSO,

+ PPC_INS_BSOA,

+ PPC_INS_BSOCTR,

+ PPC_INS_BSOCTRL,

+ PPC_INS_BSOL,

+ PPC_INS_BSOLA,

+ PPC_INS_BSOLR,

+ PPC_INS_BSOLRL,

+ PPC_INS_BT,

+ PPC_INS_BTA,

+ PPC_INS_BTCTR,

+ PPC_INS_BTCTRL,

+ PPC_INS_BTL,

+ PPC_INS_BTLA,

+ PPC_INS_BTLR,

+ PPC_INS_BTLRL,

+ PPC_INS_BUN,

+ PPC_INS_BUNA,

+ PPC_INS_BUNCTR,

+ PPC_INS_BUNCTRL,

+ PPC_INS_BUNL,

+ PPC_INS_BUNLA,

+ PPC_INS_BUNLR,

+ PPC_INS_BUNLRL,

+ PPC_INS_CLRBHRB,

+ PPC_INS_CLRLDI,

+ PPC_INS_CLRLSLDI,

+ PPC_INS_CLRLSLWI,

+ PPC_INS_CLRLWI,

+ PPC_INS_CLRRDI,

+ PPC_INS_CLRRWI,

+ PPC_INS_CMP,