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author | 2023-10-10 14:33:42 +0000 | |
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committer | 2023-10-10 14:33:42 +0000 | |
commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /capstone/suite/synctools/tablegen/ARM/ARMRegisterBanks.td | |
parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'capstone/suite/synctools/tablegen/ARM/ARMRegisterBanks.td')
-rw-r--r-- | capstone/suite/synctools/tablegen/ARM/ARMRegisterBanks.td | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/capstone/suite/synctools/tablegen/ARM/ARMRegisterBanks.td b/capstone/suite/synctools/tablegen/ARM/ARMRegisterBanks.td new file mode 100644 index 000000000..6e3834da3 --- /dev/null +++ b/capstone/suite/synctools/tablegen/ARM/ARMRegisterBanks.td @@ -0,0 +1,14 @@ +//=- ARMRegisterBank.td - Describe the AArch64 Banks ---------*- tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + +def GPRRegBank : RegisterBank<"GPRB", [GPR, GPRwithAPSR]>; +def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>; |