diff options
| author |   Timos Ampelikiotis <t.ampelikiotis@virtualopensystems.com> | 2023-10-10 11:40:56 +0000 |
|---|---|---|
| committer | Timos Ampelikiotis <t.ampelikiotis@virtualopensystems.com> | 2023-10-10 11:40:56 +0000 |
| commit | e02cda008591317b1625707ff8e115a4841aa889 (patch) | |
| tree | aee302e3cf8b59ec2d32ec481be3d1afddfc8968 /gdb-xml/riscv-64bit-cpu.xml | |
| parent | cc668e6b7e0ffd8c9d130513d12053cf5eda1d3b (diff) | |
Introduce Virtio-loopback epsilon release:
Epsilon release introduces a new compatibility layer which make virtio-loopback
design to work with QEMU and rust-vmm vhost-user backend without require any
changes.
Signed-off-by: Timos Ampelikiotis <t.ampelikiotis@virtualopensystems.com>
Change-Id: I52e57563e08a7d0bdc002f8e928ee61ba0c53dd9
Diffstat (limited to 'gdb-xml/riscv-64bit-cpu.xml')
| -rw-r--r-- | gdb-xml/riscv-64bit-cpu.xml | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/gdb-xml/riscv-64bit-cpu.xml b/gdb-xml/riscv-64bit-cpu.xml new file mode 100644 index 000000000..b8aa424ae --- /dev/null +++ b/gdb-xml/riscv-64bit-cpu.xml @@ -0,0 +1,47 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!-- Register numbers are hard-coded in order to maintain backward + compatibility with older versions of tools that didn't use xml + register descriptions. --> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.riscv.cpu"> + <reg name="zero" bitsize="64" type="int" regnum="0"/> + <reg name="ra" bitsize="64" type="code_ptr"/> + <reg name="sp" bitsize="64" type="data_ptr"/> + <reg name="gp" bitsize="64" type="data_ptr"/> + <reg name="tp" bitsize="64" type="data_ptr"/> + <reg name="t0" bitsize="64" type="int"/> + <reg name="t1" bitsize="64" type="int"/> + <reg name="t2" bitsize="64" type="int"/> + <reg name="fp" bitsize="64" type="data_ptr"/> + <reg name="s1" bitsize="64" type="int"/> + <reg name="a0" bitsize="64" type="int"/> + <reg name="a1" bitsize="64" type="int"/> + <reg name="a2" bitsize="64" type="int"/> + <reg name="a3" bitsize="64" type="int"/> + <reg name="a4" bitsize="64" type="int"/> + <reg name="a5" bitsize="64" type="int"/> + <reg name="a6" bitsize="64" type="int"/> + <reg name="a7" bitsize="64" type="int"/> + <reg name="s2" bitsize="64" type="int"/> + <reg name="s3" bitsize="64" type="int"/> + <reg name="s4" bitsize="64" type="int"/> + <reg name="s5" bitsize="64" type="int"/> + <reg name="s6" bitsize="64" type="int"/> + <reg name="s7" bitsize="64" type="int"/> + <reg name="s8" bitsize="64" type="int"/> + <reg name="s9" bitsize="64" type="int"/> + <reg name="s10" bitsize="64" type="int"/> + <reg name="s11" bitsize="64" type="int"/> + <reg name="t3" bitsize="64" type="int"/> + <reg name="t4" bitsize="64" type="int"/> + <reg name="t5" bitsize="64" type="int"/> + <reg name="t6" bitsize="64" type="int"/> + <reg name="pc" bitsize="64" type="code_ptr"/> +</feature> |