Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

3 files changed, 47 insertions, 0 deletions

diff --git a/meson/test cases/fpga/1 simple/meson.build b/meson/test cases/fpga/1 simple/meson.build
new file mode 100644
index 000000000..eff8088ba
--- /dev/null
+++ b/meson/test cases/fpga/1 simple/meson.build
@@ -0,0 +1,9 @@
+project('lattice', 'c')
+
+is = import('unstable_icestorm')
+
+is.project('spin',
+  'spin.v',
+  constraint_file : 'spin.pcf',
+)
+
diff --git a/meson/test cases/fpga/1 simple/spin.pcf b/meson/test cases/fpga/1 simple/spin.pcf
new file mode 100644
index 000000000..de06f5ddb
--- /dev/null
+++ b/meson/test cases/fpga/1 simple/spin.pcf
@@ -0,0 +1,6 @@
+set_io LED1 99
+set_io LED2 98
+set_io LED3 97
+set_io LED4 96
+set_io LED5 95
+set_io clk 21
diff --git a/meson/test cases/fpga/1 simple/spin.v b/meson/test cases/fpga/1 simple/spin.v
new file mode 100644
index 000000000..edc40c426
--- /dev/null
+++ b/meson/test cases/fpga/1 simple/spin.v
@@ -0,0 +1,32 @@
+
+module top(input clk, output LED1, output LED2, output LED3, output LED4, output LED5);
+   
+   reg ready = 0;
+   reg [23:0] divider;
+   reg [3:0] spin;
+   
+   always @(posedge clk) begin
+      if (ready) 
+        begin
+           if (divider == 6000000) 
+             begin
+                divider <= 0;
+                spin <= {spin[2], spin[3], spin[0], spin[1]};
+             end
+           else 
+             divider <= divider + 1;
+        end
+      else 
+        begin
+           ready <= 1;
+           spin <= 4'b1010;
+           divider <= 0;
+        end
+   end
+   
+   assign LED1 = spin[0];
+   assign LED2 = spin[1];
+   assign LED3 = spin[2];
+   assign LED4 = spin[3];
+   assign LED5 = 1;
+endmodule