diff options
| author |   Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
|---|---|---|
| committer | Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
| commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
| tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/edk2/ArmPkg/Drivers | |
| parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) | |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/edk2/ArmPkg/Drivers')
49 files changed, 8329 insertions, 0 deletions
diff --git a/roms/edk2/ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.c b/roms/edk2/ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.c new file mode 100644 index 000000000..137dd787e --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.c @@ -0,0 +1,32 @@ +/** @file
+
+ Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiDxe.h>
+#include <Library/DebugLib.h>
+#include <Library/DefaultExceptionHandlerLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/Cpu.h>
+
+STATIC EFI_CPU_ARCH_PROTOCOL *mCpu;
+
+EFI_STATUS
+EFIAPI
+ArmCrashDumpDxeInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&mCpu);
+ ASSERT_EFI_ERROR(Status);
+
+ return mCpu->RegisterInterruptHandler (mCpu,
+ EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS,
+ &DefaultExceptionHandler);
+}
diff --git a/roms/edk2/ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.dsc b/roms/edk2/ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.dsc new file mode 100644 index 000000000..2818ce65d --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.dsc @@ -0,0 +1,50 @@ +#/** @file
+#
+# Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = ArmCrashDumpDxe
+ PLATFORM_GUID = 8dc3c2f8-988e-4e32-8fb7-0df43f6d0d8a
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010019
+ OUTPUT_DIRECTORY = Build/ArmCrashDumpDxe
+ SUPPORTED_ARCHITECTURES = AARCH64
+ BUILD_TARGETS = DEBUG
+ SKUID_IDENTIFIER = DEFAULT
+
+[PcdsFixedAtBuild]
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
+
+[LibraryClasses]
+ ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ DebugLib|MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+ DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+ NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+
+[Components.common]
+ ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.inf
diff --git a/roms/edk2/ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.inf b/roms/edk2/ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.inf new file mode 100644 index 000000000..4dc92a1d6 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.inf @@ -0,0 +1,34 @@ +#/** @file
+#
+# Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010018
+ BASE_NAME = ArmCrashDumpDxe
+ FILE_GUID = 0bda00b0-05d6-4bb8-bfc7-058ad13615cf
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = ArmCrashDumpDxeInitialize
+
+[Sources]
+ ArmCrashDumpDxe.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ DebugLib
+ DefaultExceptionHandlerLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[Protocols]
+ gEfiCpuArchProtocolGuid
+
+[Depex]
+ gEfiCpuArchProtocolGuid
diff --git a/roms/edk2/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c b/roms/edk2/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c new file mode 100644 index 000000000..5fb33c546 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c @@ -0,0 +1,206 @@ +/*++
+
+Copyright (c) 2013-2017, ARM Ltd. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+--*/
+
+#include "ArmGicDxe.h"
+
+VOID
+EFIAPI
+IrqInterruptHandler (
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ );
+
+VOID
+EFIAPI
+ExitBootServicesEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ );
+
+// Making this global saves a few bytes in image size
+EFI_HANDLE gHardwareInterruptHandle = NULL;
+
+// Notifications
+EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
+
+// Maximum Number of Interrupts
+UINTN mGicNumInterrupts = 0;
+
+HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers = NULL;
+
+
+/**
+ Calculate GICD_ICFGRn base address and corresponding bit
+ field Int_config[1] of the GIC distributor register.
+
+ @param Source Hardware source of the interrupt.
+ @param RegAddress Corresponding GICD_ICFGRn base address.
+ @param Config1Bit Bit number of F Int_config[1] bit in the register.
+
+ @retval EFI_SUCCESS Source interrupt supported.
+ @retval EFI_UNSUPPORTED Source interrupt is not supported.
+**/
+EFI_STATUS
+GicGetDistributorIcfgBaseAndBit (
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ OUT UINTN *RegAddress,
+ OUT UINTN *Config1Bit
+ )
+{
+ UINTN RegIndex;
+ UINTN Field;
+
+ if (Source >= mGicNumInterrupts) {
+ ASSERT(Source < mGicNumInterrupts);
+ return EFI_UNSUPPORTED;
+ }
+
+ RegIndex = Source / ARM_GIC_ICDICFR_F_STRIDE; // NOTE: truncation is significant
+ Field = Source % ARM_GIC_ICDICFR_F_STRIDE;
+ *RegAddress = PcdGet64 (PcdGicDistributorBase)
+ + ARM_GIC_ICDICFR
+ + (ARM_GIC_ICDICFR_BYTES * RegIndex);
+ *Config1Bit = ((Field * ARM_GIC_ICDICFR_F_WIDTH)
+ + ARM_GIC_ICDICFR_F_CONFIG1_BIT);
+
+ return EFI_SUCCESS;
+}
+
+
+
+/**
+ Register Handler for the specified interrupt source.
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt
+ @param Handler Callback for interrupt. NULL to unregister
+
+ @retval EFI_SUCCESS Source was updated to support Handler.
+ @retval EFI_DEVICE_ERROR Hardware could not be programmed.
+
+**/
+EFI_STATUS
+EFIAPI
+RegisterInterruptSource (
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ IN HARDWARE_INTERRUPT_HANDLER Handler
+ )
+{
+ if (Source >= mGicNumInterrupts) {
+ ASSERT(FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((Handler != NULL) && (gRegisteredInterruptHandlers[Source] != NULL)) {
+ return EFI_ALREADY_STARTED;
+ }
+
+ gRegisteredInterruptHandlers[Source] = Handler;
+
+ // If the interrupt handler is unregistered then disable the interrupt
+ if (NULL == Handler){
+ return This->DisableInterruptSource (This, Source);
+ } else {
+ return This->EnableInterruptSource (This, Source);
+ }
+}
+
+STATIC VOID *mCpuArchProtocolNotifyEventRegistration;
+
+STATIC
+VOID
+EFIAPI
+CpuArchEventProtocolNotify (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_CPU_ARCH_PROTOCOL *Cpu;
+ EFI_STATUS Status;
+
+ // Get the CPU protocol that this driver requires.
+ Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ // Unregister the default exception handler.
+ Status = Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Cpu->RegisterInterruptHandler() - %r\n",
+ __FUNCTION__, Status));
+ return;
+ }
+
+ // Register to receive interrupts
+ Status = Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ,
+ Context);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Cpu->RegisterInterruptHandler() - %r\n",
+ __FUNCTION__, Status));
+ }
+
+ gBS->CloseEvent (Event);
+}
+
+EFI_STATUS
+InstallAndRegisterInterruptService (
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *InterruptProtocol,
+ IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *Interrupt2Protocol,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,
+ IN EFI_EVENT_NOTIFY ExitBootServicesEvent
+ )
+{
+ EFI_STATUS Status;
+ CONST UINTN RihArraySize =
+ (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);
+
+ // Initialize the array for the Interrupt Handlers
+ gRegisteredInterruptHandlers = AllocateZeroPool (RihArraySize);
+ if (gRegisteredInterruptHandlers == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &gHardwareInterruptHandle,
+ &gHardwareInterruptProtocolGuid,
+ InterruptProtocol,
+ &gHardwareInterrupt2ProtocolGuid,
+ Interrupt2Protocol,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Install the interrupt handler as soon as the CPU arch protocol appears.
+ //
+ EfiCreateProtocolNotifyEvent (
+ &gEfiCpuArchProtocolGuid,
+ TPL_CALLBACK,
+ CpuArchEventProtocolNotify,
+ InterruptHandler,
+ &mCpuArchProtocolNotifyEventRegistration);
+
+ // Register for an ExitBootServicesEvent
+ Status = gBS->CreateEvent (
+ EVT_SIGNAL_EXIT_BOOT_SERVICES,
+ TPL_NOTIFY,
+ ExitBootServicesEvent,
+ NULL,
+ &EfiExitBootServicesEvent
+ );
+
+ return Status;
+}
diff --git a/roms/edk2/ArmPkg/Drivers/ArmGic/ArmGicDxe.c b/roms/edk2/ArmPkg/Drivers/ArmGic/ArmGicDxe.c new file mode 100644 index 000000000..a210a6af1 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmGic/ArmGicDxe.c @@ -0,0 +1,53 @@ +/*++
+
+Copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+Module Name:
+
+ ArmGicDxe.c
+
+Abstract:
+
+ Driver implementing the GIC interrupt controller protocol
+
+--*/
+
+#include <PiDxe.h>
+
+#include "ArmGicDxe.h"
+
+/**
+ Initialize the state information for the CPU Architectural Protocol
+
+ @param ImageHandle of the loaded driver
+ @param SystemTable Pointer to the System Table
+
+ @retval EFI_SUCCESS Protocol registered
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
+ @retval EFI_DEVICE_ERROR Hardware problems
+ @retval EFI_UNSUPPORTED GIC version not supported
+
+**/
+EFI_STATUS
+InterruptDxeInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ ARM_GIC_ARCH_REVISION Revision;
+
+ Revision = ArmGicGetSupportedArchRevision ();
+
+ if (Revision == ARM_GIC_ARCH_REVISION_2) {
+ Status = GicV2DxeInitialize (ImageHandle, SystemTable);
+ } else if (Revision == ARM_GIC_ARCH_REVISION_3) {
+ Status = GicV3DxeInitialize (ImageHandle, SystemTable);
+ } else {
+ Status = EFI_UNSUPPORTED;
+ }
+
+ return Status;
+}
diff --git a/roms/edk2/ArmPkg/Drivers/ArmGic/ArmGicDxe.h b/roms/edk2/ArmPkg/Drivers/ArmGic/ArmGicDxe.h new file mode 100644 index 000000000..bf067ae03 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmGic/ArmGicDxe.h @@ -0,0 +1,79 @@ +/*++
+
+Copyright (c) 2013-2017, ARM Ltd. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+--*/
+
+#ifndef __ARM_GIC_DXE_H__
+#define __ARM_GIC_DXE_H__
+
+#include <Library/ArmGicLib.h>
+#include <Library/ArmLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+
+#include <Protocol/Cpu.h>
+#include <Protocol/HardwareInterrupt.h>
+#include <Protocol/HardwareInterrupt2.h>
+
+extern UINTN mGicNumInterrupts;
+extern HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers;
+
+// Common API
+EFI_STATUS
+InstallAndRegisterInterruptService (
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *InterruptProtocol,
+ IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *Interrupt2Protocol,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,
+ IN EFI_EVENT_NOTIFY ExitBootServicesEvent
+ );
+
+EFI_STATUS
+EFIAPI
+RegisterInterruptSource (
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ IN HARDWARE_INTERRUPT_HANDLER Handler
+ );
+
+// GicV2 API
+EFI_STATUS
+GicV2DxeInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+// GicV3 API
+EFI_STATUS
+GicV3DxeInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+
+// Shared code
+
+/**
+ Calculate GICD_ICFGRn base address and corresponding bit
+ field Int_config[1] of the GIC distributor register.
+
+ @param Source Hardware source of the interrupt.
+ @param RegAddress Corresponding GICD_ICFGRn base address.
+ @param Config1Bit Bit number of F Int_config[1] bit in the register.
+
+ @retval EFI_SUCCESS Source interrupt supported.
+ @retval EFI_UNSUPPORTED Source interrupt is not supported.
+**/
+EFI_STATUS
+GicGetDistributorIcfgBaseAndBit (
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ OUT UINTN *RegAddress,
+ OUT UINTN *Config1Bit
+ );
+
+#endif
diff --git a/roms/edk2/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf b/roms/edk2/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf new file mode 100644 index 000000000..cd2cec248 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf @@ -0,0 +1,57 @@ +#/** @file
+#
+# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+# Copyright (c) 2012 - 2017, ARM Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmGicDxe
+ FILE_GUID = DE371F7C-DEC4-4D21-ADF1-593ABCC15882
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = InterruptDxeInitialize
+
+[Sources.common]
+ ArmGicDxe.h
+ ArmGicDxe.c
+ ArmGicCommonDxe.c
+
+ GicV2/ArmGicV2Dxe.c
+ GicV3/ArmGicV3Dxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+
+[LibraryClasses]
+ ArmGicLib
+ BaseLib
+ UefiLib
+ UefiBootServicesTableLib
+ DebugLib
+ PrintLib
+ MemoryAllocationLib
+ UefiDriverEntryPoint
+ IoLib
+ PcdLib
+ UefiLib
+
+[Protocols]
+ gHardwareInterruptProtocolGuid ## PRODUCES
+ gHardwareInterrupt2ProtocolGuid ## PRODUCES
+ gEfiCpuArchProtocolGuid ## CONSUMES ## NOTIFY
+
+[Pcd.common]
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+ gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy
+
+[Depex]
+ TRUE
diff --git a/roms/edk2/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/roms/edk2/ArmPkg/Drivers/ArmGic/ArmGicLib.c new file mode 100644 index 000000000..001e6b143 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmGic/ArmGicLib.c @@ -0,0 +1,377 @@ +/** @file
+*
+* Copyright (c) 2011-2018, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Base.h>
+#include <Library/ArmGicLib.h>
+#include <Library/ArmLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+
+// In GICv3, there are 2 x 64KB frames:
+// Redistributor control frame + SGI Control & Generation frame
+#define GIC_V3_REDISTRIBUTOR_GRANULARITY (ARM_GICR_CTLR_FRAME_SIZE \
+ + ARM_GICR_SGI_PPI_FRAME_SIZE)
+
+// In GICv4, there are 2 additional 64KB frames:
+// VLPI frame + Reserved page frame
+#define GIC_V4_REDISTRIBUTOR_GRANULARITY (GIC_V3_REDISTRIBUTOR_GRANULARITY \
+ + ARM_GICR_SGI_VLPI_FRAME_SIZE \
+ + ARM_GICR_SGI_RESERVED_FRAME_SIZE)
+
+#define ISENABLER_ADDRESS(base,offset) ((base) + \
+ ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + (4 * offset))
+
+#define ICENABLER_ADDRESS(base,offset) ((base) + \
+ ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + (4 * offset))
+
+/**
+ *
+ * Return whether the Source interrupt index refers to a shared interrupt (SPI)
+ */
+STATIC
+BOOLEAN
+SourceIsSpi (
+ IN UINTN Source
+ )
+{
+ return Source >= 32 && Source < 1020;
+}
+
+/**
+ * Return the base address of the GIC redistributor for the current CPU
+ *
+ * @param Revision GIC Revision. The GIC redistributor might have a different
+ * granularity following the GIC revision.
+ *
+ * @retval Base address of the associated GIC Redistributor
+ */
+STATIC
+UINTN
+GicGetCpuRedistributorBase (
+ IN UINTN GicRedistributorBase,
+ IN ARM_GIC_ARCH_REVISION Revision
+ )
+{
+ UINTN MpId;
+ UINTN CpuAffinity;
+ UINTN Affinity;
+ UINTN GicCpuRedistributorBase;
+ UINT64 TypeRegister;
+
+ MpId = ArmReadMpidr ();
+ // Define CPU affinity as:
+ // Affinity0[0:8], Affinity1[9:15], Affinity2[16:23], Affinity3[24:32]
+ // whereas Affinity3 is defined at [32:39] in MPIDR
+ CpuAffinity = (MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2)) |
+ ((MpId & ARM_CORE_AFF3) >> 8);
+
+ if (Revision < ARM_GIC_ARCH_REVISION_3) {
+ ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
+ return 0;
+ }
+
+ GicCpuRedistributorBase = GicRedistributorBase;
+
+ do {
+ TypeRegister = MmioRead64 (GicCpuRedistributorBase + ARM_GICR_TYPER);
+ Affinity = ARM_GICR_TYPER_GET_AFFINITY (TypeRegister);
+ if (Affinity == CpuAffinity) {
+ return GicCpuRedistributorBase;
+ }
+
+ // Move to the next GIC Redistributor frame.
+ // The GIC specification does not forbid a mixture of redistributors
+ // with or without support for virtual LPIs, so we test Virtual LPIs
+ // Support (VLPIS) bit for each frame to decide the granularity.
+ // Note: The assumption here is that the redistributors are adjacent
+ // for all CPUs. However this may not be the case for NUMA systems.
+ GicCpuRedistributorBase += (((ARM_GICR_TYPER_VLPIS & TypeRegister) != 0)
+ ? GIC_V4_REDISTRIBUTOR_GRANULARITY
+ : GIC_V3_REDISTRIBUTOR_GRANULARITY);
+ } while ((TypeRegister & ARM_GICR_TYPER_LAST) == 0);
+
+ // The Redistributor has not been found for the current CPU
+ ASSERT_EFI_ERROR (EFI_NOT_FOUND);
+ return 0;
+}
+
+UINTN
+EFIAPI
+ArmGicGetInterfaceIdentification (
+ IN INTN GicInterruptInterfaceBase
+ )
+{
+ // Read the GIC Identification Register
+ return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIIDR);
+}
+
+UINTN
+EFIAPI
+ArmGicGetMaxNumInterrupts (
+ IN INTN GicDistributorBase
+ )
+{
+ return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1);
+}
+
+VOID
+EFIAPI
+ArmGicSendSgiTo (
+ IN INTN GicDistributorBase,
+ IN INTN TargetListFilter,
+ IN INTN CPUTargetList,
+ IN INTN SgiId
+ )
+{
+ MmioWrite32 (
+ GicDistributorBase + ARM_GIC_ICDSGIR,
+ ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId
+ );
+}
+
+/*
+ * Acknowledge and return the value of the Interrupt Acknowledge Register
+ *
+ * InterruptId is returned separately from the register value because in
+ * the GICv2 the register value contains the CpuId and InterruptId while
+ * in the GICv3 the register value is only the InterruptId.
+ *
+ * @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface
+ * @param InterruptId InterruptId read from the Interrupt
+ * Acknowledge Register
+ *
+ * @retval value returned by the Interrupt Acknowledge Register
+ *
+ */
+UINTN
+EFIAPI
+ArmGicAcknowledgeInterrupt (
+ IN UINTN GicInterruptInterfaceBase,
+ OUT UINTN *InterruptId
+ )
+{
+ UINTN Value;
+ ARM_GIC_ARCH_REVISION Revision;
+
+ Revision = ArmGicGetSupportedArchRevision ();
+ if (Revision == ARM_GIC_ARCH_REVISION_2) {
+ Value = ArmGicV2AcknowledgeInterrupt (GicInterruptInterfaceBase);
+ // InterruptId is required for the caller to know if a valid or spurious
+ // interrupt has been read
+ ASSERT (InterruptId != NULL);
+ if (InterruptId != NULL) {
+ *InterruptId = Value & ARM_GIC_ICCIAR_ACKINTID;
+ }
+ } else if (Revision == ARM_GIC_ARCH_REVISION_3) {
+ Value = ArmGicV3AcknowledgeInterrupt ();
+ } else {
+ ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
+ // Report Spurious interrupt which is what the above controllers would
+ // return if no interrupt was available
+ Value = 1023;
+ }
+
+ return Value;
+}
+
+VOID
+EFIAPI
+ArmGicEndOfInterrupt (
+ IN UINTN GicInterruptInterfaceBase,
+ IN UINTN Source
+ )
+{
+ ARM_GIC_ARCH_REVISION Revision;
+
+ Revision = ArmGicGetSupportedArchRevision ();
+ if (Revision == ARM_GIC_ARCH_REVISION_2) {
+ ArmGicV2EndOfInterrupt (GicInterruptInterfaceBase, Source);
+ } else if (Revision == ARM_GIC_ARCH_REVISION_3) {
+ ArmGicV3EndOfInterrupt (Source);
+ } else {
+ ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
+ }
+}
+
+VOID
+EFIAPI
+ArmGicEnableInterrupt (
+ IN UINTN GicDistributorBase,
+ IN UINTN GicRedistributorBase,
+ IN UINTN Source
+ )
+{
+ UINT32 RegOffset;
+ UINTN RegShift;
+ ARM_GIC_ARCH_REVISION Revision;
+ UINTN GicCpuRedistributorBase;
+
+ // Calculate enable register offset and bit position
+ RegOffset = Source / 32;
+ RegShift = Source % 32;
+
+ Revision = ArmGicGetSupportedArchRevision ();
+ if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
+ FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
+ SourceIsSpi (Source)) {
+ // Write set-enable register
+ MmioWrite32 (
+ GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset),
+ 1 << RegShift
+ );
+ } else {
+ GicCpuRedistributorBase = GicGetCpuRedistributorBase (
+ GicRedistributorBase,
+ Revision
+ );
+ if (GicCpuRedistributorBase == 0) {
+ ASSERT_EFI_ERROR (EFI_NOT_FOUND);
+ return;
+ }
+
+ // Write set-enable register
+ MmioWrite32 (
+ ISENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset),
+ 1 << RegShift
+ );
+ }
+}
+
+VOID
+EFIAPI
+ArmGicDisableInterrupt (
+ IN UINTN GicDistributorBase,
+ IN UINTN GicRedistributorBase,
+ IN UINTN Source
+ )
+{
+ UINT32 RegOffset;
+ UINTN RegShift;
+ ARM_GIC_ARCH_REVISION Revision;
+ UINTN GicCpuRedistributorBase;
+
+ // Calculate enable register offset and bit position
+ RegOffset = Source / 32;
+ RegShift = Source % 32;
+
+ Revision = ArmGicGetSupportedArchRevision ();
+ if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
+ FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
+ SourceIsSpi (Source)) {
+ // Write clear-enable register
+ MmioWrite32 (
+ GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset),
+ 1 << RegShift
+ );
+ } else {
+ GicCpuRedistributorBase = GicGetCpuRedistributorBase (
+ GicRedistributorBase,
+ Revision
+ );
+ if (GicCpuRedistributorBase == 0) {
+ return;
+ }
+
+ // Write clear-enable register
+ MmioWrite32 (
+ ICENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset),
+ 1 << RegShift
+ );
+ }
+}
+
+BOOLEAN
+EFIAPI
+ArmGicIsInterruptEnabled (
+ IN UINTN GicDistributorBase,
+ IN UINTN GicRedistributorBase,
+ IN UINTN Source
+ )
+{
+ UINT32 RegOffset;
+ UINTN RegShift;
+ ARM_GIC_ARCH_REVISION Revision;
+ UINTN GicCpuRedistributorBase;
+ UINT32 Interrupts;
+
+ // Calculate enable register offset and bit position
+ RegOffset = Source / 32;
+ RegShift = Source % 32;
+
+ Revision = ArmGicGetSupportedArchRevision ();
+ if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
+ FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
+ SourceIsSpi (Source)) {
+ Interrupts = ((MmioRead32 (
+ GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)
+ )
+ & (1 << RegShift)) != 0);
+ } else {
+ GicCpuRedistributorBase = GicGetCpuRedistributorBase (
+ GicRedistributorBase,
+ Revision
+ );
+ if (GicCpuRedistributorBase == 0) {
+ return 0;
+ }
+
+ // Read set-enable register
+ Interrupts = MmioRead32 (
+ ISENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset)
+ );
+ }
+
+ return ((Interrupts & (1 << RegShift)) != 0);
+}
+
+VOID
+EFIAPI
+ArmGicDisableDistributor (
+ IN INTN GicDistributorBase
+ )
+{
+ // Disable Gic Distributor
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x0);
+}
+
+VOID
+EFIAPI
+ArmGicEnableInterruptInterface (
+ IN INTN GicInterruptInterfaceBase
+ )
+{
+ ARM_GIC_ARCH_REVISION Revision;
+
+ Revision = ArmGicGetSupportedArchRevision ();
+ if (Revision == ARM_GIC_ARCH_REVISION_2) {
+ ArmGicV2EnableInterruptInterface (GicInterruptInterfaceBase);
+ } else if (Revision == ARM_GIC_ARCH_REVISION_3) {
+ ArmGicV3EnableInterruptInterface ();
+ } else {
+ ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
+ }
+}
+
+VOID
+EFIAPI
+ArmGicDisableInterruptInterface (
+ IN INTN GicInterruptInterfaceBase
+ )
+{
+ ARM_GIC_ARCH_REVISION Revision;
+
+ Revision = ArmGicGetSupportedArchRevision ();
+ if (Revision == ARM_GIC_ARCH_REVISION_2) {
+ ArmGicV2DisableInterruptInterface (GicInterruptInterfaceBase);
+ } else if (Revision == ARM_GIC_ARCH_REVISION_3) {
+ ArmGicV3DisableInterruptInterface ();
+ } else {
+ ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
+ }
+}
diff --git a/roms/edk2/ArmPkg/Drivers/ArmGic/ArmGicLib.inf b/roms/edk2/ArmPkg/Drivers/ArmGic/ArmGicLib.inf new file mode 100644 index 000000000..5e23c732b --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmGic/ArmGicLib.inf @@ -0,0 +1,42 @@ +#/* @file
+# Copyright (c) 2011-2018, ARM Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#*/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmGicLib
+ FILE_GUID = 03d05ee4-cdeb-458c-9dfc-993f09bdf405
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmGicLib
+
+[Sources]
+ ArmGicLib.c
+ ArmGicNonSecLib.c
+
+ GicV2/ArmGicV2Lib.c
+ GicV2/ArmGicV2NonSecLib.c
+
+[Sources.ARM]
+ GicV3/Arm/ArmGicV3.S | GCC
+ GicV3/Arm/ArmGicV3.asm | RVCT
+
+[Sources.AARCH64]
+ GicV3/AArch64/ArmGicV3.S
+
+[LibraryClasses]
+ ArmLib
+ DebugLib
+ IoLib
+ ArmGicArchLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdePkg/MdePkg.dec
+
+[FeaturePcd]
+ gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy
diff --git a/roms/edk2/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c b/roms/edk2/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c new file mode 100644 index 000000000..7e8ae5ac2 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c @@ -0,0 +1,35 @@ +/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/ArmGicLib.h>
+
+VOID
+EFIAPI
+ArmGicEnableDistributor (
+ IN INTN GicDistributorBase
+ )
+{
+ ARM_GIC_ARCH_REVISION Revision;
+
+ /*
+ * Enable GIC distributor in Non-Secure world.
+ * Note: The ICDDCR register is banked when Security extensions are implemented
+ */
+ Revision = ArmGicGetSupportedArchRevision ();
+ if (Revision == ARM_GIC_ARCH_REVISION_2) {
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1);
+ } else {
+ if (MmioRead32 (GicDistributorBase + ARM_GIC_ICDDCR) & ARM_GIC_ICDDCR_ARE) {
+ MmioOr32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x2);
+ } else {
+ MmioOr32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1);
+ }
+ }
+}
diff --git a/roms/edk2/ArmPkg/Drivers/ArmGic/ArmGicSecLib.c b/roms/edk2/ArmPkg/Drivers/ArmGic/ArmGicSecLib.c new file mode 100644 index 000000000..4af98bb6e --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmGic/ArmGicSecLib.c @@ -0,0 +1,58 @@ +/** @file
+*
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/ArmGicLib.h>
+
+/*
+ * This function configures the interrupts set by the mask to be secure.
+ *
+ */
+VOID
+EFIAPI
+ArmGicSetSecureInterrupts (
+ IN UINTN GicDistributorBase,
+ IN UINTN* GicSecureInterruptMask,
+ IN UINTN GicSecureInterruptMaskSize
+ )
+{
+ UINTN Index;
+ UINT32 InterruptStatus;
+
+ // We must not have more interrupts defined by the mask than the number of available interrupts
+ ASSERT(GicSecureInterruptMaskSize <= (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32));
+
+ // Set all the interrupts defined by the mask as Secure
+ for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) {
+ InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4));
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index]));
+ }
+}
+
+VOID
+EFIAPI
+ArmGicEnableDistributor (
+ IN INTN GicDistributorBase
+ )
+{
+ // Turn on the GIC distributor
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);
+}
+
+VOID
+EFIAPI
+ArmGicSetupNonSecure (
+ IN UINTN MpId,
+ IN INTN GicDistributorBase,
+ IN INTN GicInterruptInterfaceBase
+ )
+{
+ ArmGicV2SetupNonSecure (MpId, GicDistributorBase, GicInterruptInterfaceBase);
+}
diff --git a/roms/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c b/roms/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c new file mode 100644 index 000000000..a96dc7829 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c @@ -0,0 +1,460 @@ +/*++
+
+Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
+Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
+Portions copyright (c) 2011-2017, ARM Ltd. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+Module Name:
+
+ GicV2/ArmGicV2Dxe.c
+
+Abstract:
+
+ Driver implementing the GicV2 interrupt controller protocol
+
+--*/
+
+#include <Library/ArmGicLib.h>
+
+#include "ArmGicDxe.h"
+
+#define ARM_GIC_DEFAULT_PRIORITY 0x80
+
+extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol;
+extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol;
+
+STATIC UINT32 mGicInterruptInterfaceBase;
+STATIC UINT32 mGicDistributorBase;
+
+/**
+ Enable interrupt source Source.
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt
+
+ @retval EFI_SUCCESS Source interrupt enabled.
+ @retval EFI_UNSUPPORTED Source interrupt is not supported
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GicV2EnableInterruptSource (
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source
+ )
+{
+ if (Source >= mGicNumInterrupts) {
+ ASSERT(FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ ArmGicEnableInterrupt (mGicDistributorBase, 0, Source);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Disable interrupt source Source.
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt
+
+ @retval EFI_SUCCESS Source interrupt disabled.
+ @retval EFI_UNSUPPORTED Source interrupt is not supported
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GicV2DisableInterruptSource (
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source
+ )
+{
+ if (Source >= mGicNumInterrupts) {
+ ASSERT(FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ ArmGicDisableInterrupt (mGicDistributorBase, 0, Source);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Return current state of interrupt source Source.
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt
+ @param InterruptState TRUE: source enabled, FALSE: source disabled.
+
+ @retval EFI_SUCCESS InterruptState is valid
+ @retval EFI_UNSUPPORTED Source interrupt is not supported
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GicV2GetInterruptSourceState (
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ IN BOOLEAN *InterruptState
+ )
+{
+ if (Source >= mGicNumInterrupts) {
+ ASSERT(FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ *InterruptState = ArmGicIsInterruptEnabled (mGicDistributorBase, 0, Source);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Signal to the hardware that the End Of Interrupt state
+ has been reached.
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt
+
+ @retval EFI_SUCCESS Source interrupt EOI'ed.
+ @retval EFI_UNSUPPORTED Source interrupt is not supported
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GicV2EndOfInterrupt (
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source
+ )
+{
+ if (Source >= mGicNumInterrupts) {
+ ASSERT(FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ ArmGicV2EndOfInterrupt (mGicInterruptInterfaceBase, Source);
+ return EFI_SUCCESS;
+}
+
+/**
+ EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.
+
+ @param InterruptType Defines the type of interrupt or exception that
+ occurred on the processor.This parameter is
+ processor architecture specific.
+ @param SystemContext A pointer to the processor context when
+ the interrupt occurred on the processor.
+
+ @return None
+
+**/
+STATIC
+VOID
+EFIAPI
+GicV2IrqInterruptHandler (
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ )
+{
+ UINT32 GicInterrupt;
+ HARDWARE_INTERRUPT_HANDLER InterruptHandler;
+
+ GicInterrupt = ArmGicV2AcknowledgeInterrupt (mGicInterruptInterfaceBase);
+
+ // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the
+ // number of interrupt (ie: Spurious interrupt).
+ if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) {
+ // The special interrupts do not need to be acknowledged
+ return;
+ }
+
+ InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];
+ if (InterruptHandler != NULL) {
+ // Call the registered interrupt handler.
+ InterruptHandler (GicInterrupt, SystemContext);
+ } else {
+ DEBUG ((DEBUG_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));
+ GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt);
+ }
+}
+
+// The protocol instance produced by this driver
+EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol = {
+ RegisterInterruptSource,
+ GicV2EnableInterruptSource,
+ GicV2DisableInterruptSource,
+ GicV2GetInterruptSourceState,
+ GicV2EndOfInterrupt
+};
+
+/**
+ Get interrupt trigger type of an interrupt
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt.
+ @param TriggerType Returns interrupt trigger type.
+
+ @retval EFI_SUCCESS Source interrupt supported.
+ @retval EFI_UNSUPPORTED Source interrupt is not supported.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GicV2GetTriggerType (
+ IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType
+ )
+{
+ UINTN RegAddress;
+ UINTN Config1Bit;
+ EFI_STATUS Status;
+
+ Status = GicGetDistributorIcfgBaseAndBit (
+ Source,
+ &RegAddress,
+ &Config1Bit
+ );
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if ((MmioRead32 (RegAddress) & (1 << Config1Bit)) == 0) {
+ *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;
+ } else {
+ *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Set interrupt trigger type of an interrupt
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt.
+ @param TriggerType Interrupt trigger type.
+
+ @retval EFI_SUCCESS Source interrupt supported.
+ @retval EFI_UNSUPPORTED Source interrupt is not supported.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GicV2SetTriggerType (
+ IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType
+ )
+{
+ UINTN RegAddress;
+ UINTN Config1Bit;
+ UINT32 Value;
+ EFI_STATUS Status;
+ BOOLEAN SourceEnabled;
+
+ if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
+ && (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH)) {
+ DEBUG ((DEBUG_ERROR, "Invalid interrupt trigger type: %d\n", \
+ TriggerType));
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ Status = GicGetDistributorIcfgBaseAndBit (
+ Source,
+ &RegAddress,
+ &Config1Bit
+ );
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = GicV2GetInterruptSourceState (
+ (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
+ Source,
+ &SourceEnabled
+ );
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Value = (TriggerType == EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
+ ? ARM_GIC_ICDICFR_EDGE_TRIGGERED
+ : ARM_GIC_ICDICFR_LEVEL_TRIGGERED;
+
+ // Before changing the value, we must disable the interrupt,
+ // otherwise GIC behavior is UNPREDICTABLE.
+ if (SourceEnabled) {
+ GicV2DisableInterruptSource (
+ (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
+ Source
+ );
+ }
+
+ MmioAndThenOr32 (
+ RegAddress,
+ ~(0x1 << Config1Bit),
+ Value << Config1Bit
+ );
+
+ // Restore interrupt state
+ if (SourceEnabled) {
+ GicV2EnableInterruptSource (
+ (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
+ Source
+ );
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol = {
+ (HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource,
+ (HARDWARE_INTERRUPT2_ENABLE)GicV2EnableInterruptSource,
+ (HARDWARE_INTERRUPT2_DISABLE)GicV2DisableInterruptSource,
+ (HARDWARE_INTERRUPT2_INTERRUPT_STATE)GicV2GetInterruptSourceState,
+ (HARDWARE_INTERRUPT2_END_OF_INTERRUPT)GicV2EndOfInterrupt,
+ GicV2GetTriggerType,
+ GicV2SetTriggerType
+};
+
+/**
+ Shutdown our hardware
+
+ DXE Core will disable interrupts and turn off the timer and disable
+ interrupts after all the event handlers have run.
+
+ @param[in] Event The Event that is being processed
+ @param[in] Context Event Context
+**/
+STATIC
+VOID
+EFIAPI
+GicV2ExitBootServicesEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ UINTN Index;
+ UINT32 GicInterrupt;
+
+ // Disable all the interrupts
+ for (Index = 0; Index < mGicNumInterrupts; Index++) {
+ GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index);
+ }
+
+ // Acknowledge all pending interrupts
+ do {
+ GicInterrupt = ArmGicV2AcknowledgeInterrupt (mGicInterruptInterfaceBase);
+
+ if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) < mGicNumInterrupts) {
+ GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt);
+ }
+ } while (!ARM_GIC_IS_SPECIAL_INTERRUPTS (GicInterrupt));
+
+ // Disable Gic Interface
+ ArmGicV2DisableInterruptInterface (mGicInterruptInterfaceBase);
+
+ // Disable Gic Distributor
+ ArmGicDisableDistributor (mGicDistributorBase);
+}
+
+/**
+ Initialize the state information for the CPU Architectural Protocol
+
+ @param ImageHandle of the loaded driver
+ @param SystemTable Pointer to the System Table
+
+ @retval EFI_SUCCESS Protocol registered
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
+ @retval EFI_DEVICE_ERROR Hardware problems
+
+**/
+EFI_STATUS
+GicV2DxeInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ UINT32 RegOffset;
+ UINTN RegShift;
+ UINT32 CpuTarget;
+
+ // Make sure the Interrupt Controller Protocol is not already installed in
+ // the system.
+ ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
+
+ mGicInterruptInterfaceBase = PcdGet64 (PcdGicInterruptInterfaceBase);
+ mGicDistributorBase = PcdGet64 (PcdGicDistributorBase);
+ mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase);
+
+ for (Index = 0; Index < mGicNumInterrupts; Index++) {
+ GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index);
+
+ // Set Priority
+ RegOffset = Index / 4;
+ RegShift = (Index % 4) * 8;
+ MmioAndThenOr32 (
+ mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
+ ~(0xff << RegShift),
+ ARM_GIC_DEFAULT_PRIORITY << RegShift
+ );
+ }
+
+ // Targets the interrupts to the Primary Cpu
+
+ // Only Primary CPU will run this code. We can identify our GIC CPU ID by
+ // reading the GIC Distributor Target register. The 8 first GICD_ITARGETSRn
+ // are banked to each connected CPU. These 8 registers hold the CPU targets
+ // fields for interrupts 0-31. More Info in the GIC Specification about
+ // "Interrupt Processor Targets Registers"
+
+ // Read the first Interrupt Processor Targets Register (that corresponds to
+ // the 4 first SGIs)
+ CpuTarget = MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR);
+
+ // The CPU target is a bit field mapping each CPU to a GIC CPU Interface.
+ // This value is 0 when we run on a uniprocessor platform.
+ if (CpuTarget != 0) {
+ // The 8 first Interrupt Processor Targets Registers are read-only
+ for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {
+ MmioWrite32 (
+ mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4),
+ CpuTarget
+ );
+ }
+ }
+
+ // Set binary point reg to 0x7 (no preemption)
+ MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCBPR, 0x7);
+
+ // Set priority mask reg to 0xff to allow all priorities through
+ MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0xff);
+
+ // Enable gic cpu interface
+ ArmGicEnableInterruptInterface (mGicInterruptInterfaceBase);
+
+ // Enable gic distributor
+ ArmGicEnableDistributor (mGicDistributorBase);
+
+ Status = InstallAndRegisterInterruptService (
+ &gHardwareInterruptV2Protocol,
+ &gHardwareInterrupt2V2Protocol,
+ GicV2IrqInterruptHandler,
+ GicV2ExitBootServicesEvent
+ );
+
+ return Status;
+}
diff --git a/roms/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c b/roms/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c new file mode 100644 index 000000000..ff910c175 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c @@ -0,0 +1,30 @@ +/** @file
+*
+* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Library/ArmGicLib.h>
+#include <Library/IoLib.h>
+
+UINTN
+EFIAPI
+ArmGicV2AcknowledgeInterrupt (
+ IN UINTN GicInterruptInterfaceBase
+ )
+{
+ // Read the Interrupt Acknowledge Register
+ return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
+}
+
+VOID
+EFIAPI
+ArmGicV2EndOfInterrupt (
+ IN UINTN GicInterruptInterfaceBase,
+ IN UINTN Source
+ )
+{
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Source);
+}
diff --git a/roms/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c b/roms/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c new file mode 100644 index 000000000..08f219c10 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c @@ -0,0 +1,36 @@ +/** @file
+*
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/ArmGicLib.h>
+
+
+VOID
+EFIAPI
+ArmGicV2EnableInterruptInterface (
+ IN INTN GicInterruptInterfaceBase
+ )
+{
+ /*
+ * Enable the CPU interface in Non-Secure world
+ * Note: The ICCICR register is banked when Security extensions are implemented
+ */
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1);
+}
+
+VOID
+EFIAPI
+ArmGicV2DisableInterruptInterface (
+ IN INTN GicInterruptInterfaceBase
+ )
+{
+ // Disable Gic Interface
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x0);
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x0);
+}
diff --git a/roms/edk2/ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.S b/roms/edk2/ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.S new file mode 100644 index 000000000..20f83aa85 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.S @@ -0,0 +1,106 @@ +#
+# Copyright (c) 2014, ARM Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+#include <AsmMacroIoLibV8.h>
+
+#if !defined(__clang__)
+
+//
+// Clang versions before v3.6 do not support the GNU extension that allows
+// system registers outside of the IMPLEMENTATION DEFINED range to be specified
+// using the generic notation below. However, clang knows these registers by
+// their architectural names, so it has no need for these aliases anyway.
+//
+#define ICC_SRE_EL1 S3_0_C12_C12_5
+#define ICC_SRE_EL2 S3_4_C12_C9_5
+#define ICC_SRE_EL3 S3_6_C12_C12_5
+#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
+#define ICC_EOIR1_EL1 S3_0_C12_C12_1
+#define ICC_IAR1_EL1 S3_0_C12_C12_0
+#define ICC_PMR_EL1 S3_0_C4_C6_0
+#define ICC_BPR1_EL1 S3_0_C12_C12_3
+
+#endif
+
+//UINT32
+//EFIAPI
+//ArmGicV3GetControlSystemRegisterEnable (
+// VOID
+// );
+ASM_FUNC(ArmGicV3GetControlSystemRegisterEnable)
+ EL1_OR_EL2_OR_EL3(x1)
+1: mrs x0, ICC_SRE_EL1
+ b 4f
+2: mrs x0, ICC_SRE_EL2
+ b 4f
+3: mrs x0, ICC_SRE_EL3
+4: ret
+
+//VOID
+//EFIAPI
+//ArmGicV3SetControlSystemRegisterEnable (
+// IN UINT32 ControlSystemRegisterEnable
+// );
+ASM_FUNC(ArmGicV3SetControlSystemRegisterEnable)
+ EL1_OR_EL2_OR_EL3(x1)
+1: msr ICC_SRE_EL1, x0
+ b 4f
+2: msr ICC_SRE_EL2, x0
+ b 4f
+3: msr ICC_SRE_EL3, x0
+4: isb
+ ret
+
+//VOID
+//ArmGicV3EnableInterruptInterface (
+// VOID
+// );
+ASM_FUNC(ArmGicV3EnableInterruptInterface)
+ mov x0, #1
+ msr ICC_IGRPEN1_EL1, x0
+ ret
+
+//VOID
+//ArmGicV3DisableInterruptInterface (
+// VOID
+// );
+ASM_FUNC(ArmGicV3DisableInterruptInterface)
+ mov x0, #0
+ msr ICC_IGRPEN1_EL1, x0
+ ret
+
+//VOID
+//ArmGicV3EndOfInterrupt (
+// IN UINTN InterruptId
+// );
+ASM_FUNC(ArmGicV3EndOfInterrupt)
+ msr ICC_EOIR1_EL1, x0
+ ret
+
+//UINTN
+//ArmGicV3AcknowledgeInterrupt (
+// VOID
+// );
+ASM_FUNC(ArmGicV3AcknowledgeInterrupt)
+ mrs x0, ICC_IAR1_EL1
+ ret
+
+//VOID
+//ArmGicV3SetPriorityMask (
+// IN UINTN Priority
+// );
+ASM_FUNC(ArmGicV3SetPriorityMask)
+ msr ICC_PMR_EL1, x0
+ ret
+
+//VOID
+//ArmGicV3SetBinaryPointer (
+// IN UINTN BinaryPoint
+// );
+ASM_FUNC(ArmGicV3SetBinaryPointer)
+ msr ICC_BPR1_EL1, x0
+ ret
diff --git a/roms/edk2/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S b/roms/edk2/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S new file mode 100644 index 000000000..8c43a613d --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S @@ -0,0 +1,80 @@ +#
+# Copyright (c) 2014, ARM Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+#include <AsmMacroIoLib.h>
+#include <Library/ArmLib.h>
+
+// For the moment we assume this will run in SVC mode on ARMv7
+
+//UINT32
+//EFIAPI
+//ArmGicGetControlSystemRegisterEnable (
+// VOID
+// );
+ASM_FUNC(ArmGicV3GetControlSystemRegisterEnable)
+ mrc p15, 0, r0, c12, c12, 5 // ICC_SRE
+ bx lr
+
+//VOID
+//EFIAPI
+//ArmGicSetControlSystemRegisterEnable (
+// IN UINT32 ControlSystemRegisterEnable
+// );
+ASM_FUNC(ArmGicV3SetControlSystemRegisterEnable)
+ mcr p15, 0, r0, c12, c12, 5 // ICC_SRE
+ isb
+ bx lr
+
+//VOID
+//ArmGicV3EnableInterruptInterface (
+// VOID
+// );
+ASM_FUNC(ArmGicV3EnableInterruptInterface)
+ mov r0, #1
+ mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1
+ bx lr
+
+//VOID
+//ArmGicV3DisableInterruptInterface (
+// VOID
+// );
+ASM_FUNC(ArmGicV3DisableInterruptInterface)
+ mov r0, #0
+ mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1
+ bx lr
+
+//VOID
+//ArmGicV3EndOfInterrupt (
+// IN UINTN InterruptId
+// );
+ASM_FUNC(ArmGicV3EndOfInterrupt)
+ mcr p15, 0, r0, c12, c12, 1 //ICC_EOIR1
+ bx lr
+
+//UINTN
+//ArmGicV3AcknowledgeInterrupt (
+// VOID
+// );
+ASM_FUNC(ArmGicV3AcknowledgeInterrupt)
+ mrc p15, 0, r0, c12, c12, 0 //ICC_IAR1
+ bx lr
+
+//VOID
+//ArmGicV3SetPriorityMask (
+// IN UINTN Priority
+// );
+ASM_FUNC(ArmGicV3SetPriorityMask)
+ mcr p15, 0, r0, c4, c6, 0 //ICC_PMR
+ bx lr
+
+//VOID
+//ArmGicV3SetBinaryPointer (
+// IN UINTN BinaryPoint
+// );
+ASM_FUNC(ArmGicV3SetBinaryPointer)
+ mcr p15, 0, r0, c12, c12, 3 //ICC_BPR1
+ bx lr
diff --git a/roms/edk2/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm b/roms/edk2/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm new file mode 100644 index 000000000..bf79c1350 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm @@ -0,0 +1,82 @@ +//
+// Copyright (c) 2014, ARM Limited. All rights reserved.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//
+
+// For the moment we assume this will run in SVC mode on ARMv7
+
+
+ INCLUDE AsmMacroExport.inc
+
+//UINT32
+//EFIAPI
+//ArmGicGetControlSystemRegisterEnable (
+// VOID
+// );
+ RVCT_ASM_EXPORT ArmGicV3GetControlSystemRegisterEnable
+ mrc p15, 0, r0, c12, c12, 5 // ICC_SRE
+ bx lr
+
+//VOID
+//EFIAPI
+//ArmGicSetControlSystemRegisterEnable (
+// IN UINT32 ControlSystemRegisterEnable
+// );
+ RVCT_ASM_EXPORT ArmGicV3SetControlSystemRegisterEnable
+ mcr p15, 0, r0, c12, c12, 5 // ICC_SRE
+ isb
+ bx lr
+
+//VOID
+//ArmGicV3EnableInterruptInterface (
+// VOID
+// );
+ RVCT_ASM_EXPORT ArmGicV3EnableInterruptInterface
+ mov r0, #1
+ mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1
+ bx lr
+
+//VOID
+//ArmGicV3DisableInterruptInterface (
+// VOID
+// );
+ RVCT_ASM_EXPORT ArmGicV3DisableInterruptInterface
+ mov r0, #0
+ mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1
+ bx lr
+
+//VOID
+//ArmGicV3EndOfInterrupt (
+// IN UINTN InterruptId
+// );
+ RVCT_ASM_EXPORT ArmGicV3EndOfInterrupt
+ mcr p15, 0, r0, c12, c12, 1 //ICC_EOIR1
+ bx lr
+
+//UINTN
+//ArmGicV3AcknowledgeInterrupt (
+// VOID
+// );
+ RVCT_ASM_EXPORT ArmGicV3AcknowledgeInterrupt
+ mrc p15, 0, r0, c12, c12, 0 //ICC_IAR1
+ bx lr
+
+//VOID
+//ArmGicV3SetPriorityMask (
+// IN UINTN Priority
+// );
+ RVCT_ASM_EXPORT ArmGicV3SetPriorityMask
+ mcr p15, 0, r0, c4, c6, 0 //ICC_PMR
+ bx lr
+
+//VOID
+//ArmGicV3SetBinaryPointer (
+// IN UINTN BinaryPoint
+// );
+ RVCT_ASM_EXPORT ArmGicV3SetBinaryPointer
+ mcr p15, 0, r0, c12, c12, 3 //ICC_BPR1
+ bx lr
+
+ END
diff --git a/roms/edk2/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/roms/edk2/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c new file mode 100644 index 000000000..d7da1f198 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c @@ -0,0 +1,491 @@ +/** @file
+*
+* Copyright (c) 2011-2018, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Library/ArmGicLib.h>
+
+#include "ArmGicDxe.h"
+
+#define ARM_GIC_DEFAULT_PRIORITY 0x80
+
+extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol;
+extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol;
+
+STATIC UINTN mGicDistributorBase;
+STATIC UINTN mGicRedistributorsBase;
+
+/**
+ Enable interrupt source Source.
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt
+
+ @retval EFI_SUCCESS Source interrupt enabled.
+ @retval EFI_DEVICE_ERROR Hardware could not be programmed.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GicV3EnableInterruptSource (
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source
+ )
+{
+ if (Source >= mGicNumInterrupts) {
+ ASSERT(FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ ArmGicEnableInterrupt (mGicDistributorBase, mGicRedistributorsBase, Source);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Disable interrupt source Source.
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt
+
+ @retval EFI_SUCCESS Source interrupt disabled.
+ @retval EFI_DEVICE_ERROR Hardware could not be programmed.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GicV3DisableInterruptSource (
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source
+ )
+{
+ if (Source >= mGicNumInterrupts) {
+ ASSERT(FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ ArmGicDisableInterrupt (mGicDistributorBase, mGicRedistributorsBase, Source);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Return current state of interrupt source Source.
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt
+ @param InterruptState TRUE: source enabled, FALSE: source disabled.
+
+ @retval EFI_SUCCESS InterruptState is valid
+ @retval EFI_DEVICE_ERROR InterruptState is not valid
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GicV3GetInterruptSourceState (
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ IN BOOLEAN *InterruptState
+ )
+{
+ if (Source >= mGicNumInterrupts) {
+ ASSERT(FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ *InterruptState = ArmGicIsInterruptEnabled (
+ mGicDistributorBase,
+ mGicRedistributorsBase,
+ Source
+ );
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Signal to the hardware that the End Of Interrupt state
+ has been reached.
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt
+
+ @retval EFI_SUCCESS Source interrupt EOI'ed.
+ @retval EFI_DEVICE_ERROR Hardware could not be programmed.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GicV3EndOfInterrupt (
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source
+ )
+{
+ if (Source >= mGicNumInterrupts) {
+ ASSERT(FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ ArmGicV3EndOfInterrupt (Source);
+ return EFI_SUCCESS;
+}
+
+/**
+ EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.
+
+ @param InterruptType Defines the type of interrupt or exception that
+ occurred on the processor. This parameter is
+ processor architecture specific.
+ @param SystemContext A pointer to the processor context when
+ the interrupt occurred on the processor.
+
+ @return None
+
+**/
+STATIC
+VOID
+EFIAPI
+GicV3IrqInterruptHandler (
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ )
+{
+ UINT32 GicInterrupt;
+ HARDWARE_INTERRUPT_HANDLER InterruptHandler;
+
+ GicInterrupt = ArmGicV3AcknowledgeInterrupt ();
+
+ // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the
+ // number of interrupt (ie: Spurious interrupt).
+ if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) {
+ // The special interrupt do not need to be acknowledge
+ return;
+ }
+
+ InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];
+ if (InterruptHandler != NULL) {
+ // Call the registered interrupt handler.
+ InterruptHandler (GicInterrupt, SystemContext);
+ } else {
+ DEBUG ((DEBUG_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));
+ GicV3EndOfInterrupt (&gHardwareInterruptV3Protocol, GicInterrupt);
+ }
+}
+
+// The protocol instance produced by this driver
+EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol = {
+ RegisterInterruptSource,
+ GicV3EnableInterruptSource,
+ GicV3DisableInterruptSource,
+ GicV3GetInterruptSourceState,
+ GicV3EndOfInterrupt
+};
+
+/**
+ Get interrupt trigger type of an interrupt
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt.
+ @param TriggerType Returns interrupt trigger type.
+
+ @retval EFI_SUCCESS Source interrupt supported.
+ @retval EFI_UNSUPPORTED Source interrupt is not supported.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GicV3GetTriggerType (
+ IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType
+ )
+{
+ UINTN RegAddress;
+ UINTN Config1Bit;
+ EFI_STATUS Status;
+
+ Status = GicGetDistributorIcfgBaseAndBit (
+ Source,
+ &RegAddress,
+ &Config1Bit
+ );
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if ((MmioRead32 (RegAddress) & (1 << Config1Bit)) == 0) {
+ *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;
+ } else {
+ *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Set interrupt trigger type of an interrupt
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt.
+ @param TriggerType Interrupt trigger type.
+
+ @retval EFI_SUCCESS Source interrupt supported.
+ @retval EFI_UNSUPPORTED Source interrupt is not supported.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GicV3SetTriggerType (
+ IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType
+ )
+{
+ UINTN RegAddress;
+ UINTN Config1Bit;
+ UINT32 Value;
+ EFI_STATUS Status;
+ BOOLEAN SourceEnabled;
+
+ if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
+ && (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH)) {
+ DEBUG ((DEBUG_ERROR, "Invalid interrupt trigger type: %d\n", \
+ TriggerType));
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ Status = GicGetDistributorIcfgBaseAndBit (
+ Source,
+ &RegAddress,
+ &Config1Bit
+ );
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = GicV3GetInterruptSourceState (
+ (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
+ Source,
+ &SourceEnabled
+ );
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Value = (TriggerType == EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
+ ? ARM_GIC_ICDICFR_EDGE_TRIGGERED
+ : ARM_GIC_ICDICFR_LEVEL_TRIGGERED;
+
+ // Before changing the value, we must disable the interrupt,
+ // otherwise GIC behavior is UNPREDICTABLE.
+ if (SourceEnabled) {
+ GicV3DisableInterruptSource (
+ (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
+ Source
+ );
+ }
+
+ MmioAndThenOr32 (
+ RegAddress,
+ ~(0x1 << Config1Bit),
+ Value << Config1Bit
+ );
+ // Restore interrupt state
+ if (SourceEnabled) {
+ GicV3EnableInterruptSource (
+ (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
+ Source
+ );
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol = {
+ (HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource,
+ (HARDWARE_INTERRUPT2_ENABLE)GicV3EnableInterruptSource,
+ (HARDWARE_INTERRUPT2_DISABLE)GicV3DisableInterruptSource,
+ (HARDWARE_INTERRUPT2_INTERRUPT_STATE)GicV3GetInterruptSourceState,
+ (HARDWARE_INTERRUPT2_END_OF_INTERRUPT)GicV3EndOfInterrupt,
+ GicV3GetTriggerType,
+ GicV3SetTriggerType
+};
+
+/**
+ Shutdown our hardware
+
+ DXE Core will disable interrupts and turn off the timer and disable interrupts
+ after all the event handlers have run.
+
+ @param[in] Event The Event that is being processed
+ @param[in] Context Event Context
+**/
+VOID
+EFIAPI
+GicV3ExitBootServicesEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ UINTN Index;
+
+ // Acknowledge all pending interrupts
+ for (Index = 0; Index < mGicNumInterrupts; Index++) {
+ GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index);
+ }
+
+ for (Index = 0; Index < mGicNumInterrupts; Index++) {
+ GicV3EndOfInterrupt (&gHardwareInterruptV3Protocol, Index);
+ }
+
+ // Disable Gic Interface
+ ArmGicV3DisableInterruptInterface ();
+
+ // Disable Gic Distributor
+ ArmGicDisableDistributor (mGicDistributorBase);
+}
+
+/**
+ Initialize the state information for the CPU Architectural Protocol
+
+ @param ImageHandle of the loaded driver
+ @param SystemTable Pointer to the System Table
+
+ @retval EFI_SUCCESS Protocol registered
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
+ @retval EFI_DEVICE_ERROR Hardware problems
+
+**/
+EFI_STATUS
+GicV3DxeInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ UINT32 RegOffset;
+ UINTN RegShift;
+ UINT64 CpuTarget;
+ UINT64 MpId;
+
+ // Make sure the Interrupt Controller Protocol is not already installed in
+ // the system.
+ ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
+
+ mGicDistributorBase = PcdGet64 (PcdGicDistributorBase);
+ mGicRedistributorsBase = PcdGet64 (PcdGicRedistributorsBase);
+ mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase);
+
+ // We will be driving this GIC in native v3 mode, i.e., with Affinity
+ // Routing enabled. So ensure that the ARE bit is set.
+ if (!FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
+ MmioOr32 (mGicDistributorBase + ARM_GIC_ICDDCR, ARM_GIC_ICDDCR_ARE);
+ }
+
+ for (Index = 0; Index < mGicNumInterrupts; Index++) {
+ GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index);
+
+ // Set Priority
+ RegOffset = Index / 4;
+ RegShift = (Index % 4) * 8;
+ MmioAndThenOr32 (
+ mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
+ ~(0xff << RegShift),
+ ARM_GIC_DEFAULT_PRIORITY << RegShift
+ );
+ }
+
+ // Targets the interrupts to the Primary Cpu
+
+ if (FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
+ // Only Primary CPU will run this code. We can identify our GIC CPU ID by
+ // reading the GIC Distributor Target register. The 8 first
+ // GICD_ITARGETSRn are banked to each connected CPU. These 8 registers
+ // hold the CPU targets fields for interrupts 0-31. More Info in the GIC
+ // Specification about "Interrupt Processor Targets Registers"
+
+ // Read the first Interrupt Processor Targets Register (that corresponds
+ // to the 4 first SGIs)
+ CpuTarget = MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR);
+
+ // The CPU target is a bit field mapping each CPU to a GIC CPU Interface.
+ // This value is 0 when we run on a uniprocessor platform.
+ if (CpuTarget != 0) {
+ // The 8 first Interrupt Processor Targets Registers are read-only
+ for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {
+ MmioWrite32 (
+ mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4),
+ CpuTarget
+ );
+ }
+ }
+ } else {
+ MpId = ArmReadMpidr ();
+ CpuTarget = MpId &
+ (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);
+
+ if ((MmioRead32 (
+ mGicDistributorBase + ARM_GIC_ICDDCR
+ ) & ARM_GIC_ICDDCR_DS) != 0) {
+
+ // If the Disable Security (DS) control bit is set, we are dealing with a
+ // GIC that has only one security state. In this case, let's assume we are
+ // executing in non-secure state (which is appropriate for DXE modules)
+ // and that no other firmware has performed any configuration on the GIC.
+ // This means we need to reconfigure all interrupts to non-secure Group 1
+ // first.
+
+ MmioWrite32 (
+ mGicRedistributorsBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDISR,
+ 0xffffffff
+ );
+
+ for (Index = 32; Index < mGicNumInterrupts; Index += 32) {
+ MmioWrite32 (
+ mGicDistributorBase + ARM_GIC_ICDISR + Index / 8,
+ 0xffffffff
+ );
+ }
+ }
+
+ // Route the SPIs to the primary CPU. SPIs start at the INTID 32
+ for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) {
+ MmioWrite64 (
+ mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8),
+ CpuTarget
+ );
+ }
+ }
+
+ // Set binary point reg to 0x7 (no preemption)
+ ArmGicV3SetBinaryPointer (0x7);
+
+ // Set priority mask reg to 0xff to allow all priorities through
+ ArmGicV3SetPriorityMask (0xff);
+
+ // Enable gic cpu interface
+ ArmGicV3EnableInterruptInterface ();
+
+ // Enable gic distributor
+ ArmGicEnableDistributor (mGicDistributorBase);
+
+ Status = InstallAndRegisterInterruptService (
+ &gHardwareInterruptV3Protocol,
+ &gHardwareInterrupt2V3Protocol,
+ GicV3IrqInterruptHandler,
+ GicV3ExitBootServicesEvent
+ );
+
+ return Status;
+}
diff --git a/roms/edk2/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c b/roms/edk2/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c new file mode 100644 index 000000000..d8625e159 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c @@ -0,0 +1,553 @@ +/** @file
+ Produces the CPU I/O 2 Protocol.
+
+Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiDxe.h>
+
+#include <Protocol/CpuIo2.h>
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#define MAX_IO_PORT_ADDRESS 0xFFFF
+
+//
+// Handle for the CPU I/O 2 Protocol
+//
+STATIC EFI_HANDLE mHandle = NULL;
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mInStride[] = {
+ 1, // EfiCpuIoWidthUint8
+ 2, // EfiCpuIoWidthUint16
+ 4, // EfiCpuIoWidthUint32
+ 8, // EfiCpuIoWidthUint64
+ 0, // EfiCpuIoWidthFifoUint8
+ 0, // EfiCpuIoWidthFifoUint16
+ 0, // EfiCpuIoWidthFifoUint32
+ 0, // EfiCpuIoWidthFifoUint64
+ 1, // EfiCpuIoWidthFillUint8
+ 2, // EfiCpuIoWidthFillUint16
+ 4, // EfiCpuIoWidthFillUint32
+ 8 // EfiCpuIoWidthFillUint64
+};
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mOutStride[] = {
+ 1, // EfiCpuIoWidthUint8
+ 2, // EfiCpuIoWidthUint16
+ 4, // EfiCpuIoWidthUint32
+ 8, // EfiCpuIoWidthUint64
+ 1, // EfiCpuIoWidthFifoUint8
+ 2, // EfiCpuIoWidthFifoUint16
+ 4, // EfiCpuIoWidthFifoUint32
+ 8, // EfiCpuIoWidthFifoUint64
+ 0, // EfiCpuIoWidthFillUint8
+ 0, // EfiCpuIoWidthFillUint16
+ 0, // EfiCpuIoWidthFillUint32
+ 0 // EfiCpuIoWidthFillUint64
+};
+
+/**
+ Check parameters to a CPU I/O 2 Protocol service request.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The parameters for this request pass the checks.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+CpuIoCheckParameter (
+ IN BOOLEAN MmioOperation,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ UINT64 MaxCount;
+ UINT64 Limit;
+
+ //
+ // Check to see if Buffer is NULL
+ //
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check to see if Width is in the valid range
+ //
+ if ((UINT32)Width >= EfiCpuIoWidthMaximum) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // For FIFO type, the target address won't increase during the access,
+ // so treat Count as 1
+ //
+ if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
+ Count = 1;
+ }
+
+ //
+ // Check to see if Width is in the valid range for I/O Port operations
+ //
+ Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check to see if Address is aligned
+ //
+ if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // Check to see if any address associated with this transfer exceeds the maximum
+ // allowed address. The maximum address implied by the parameters passed in is
+ // Address + Size * Count. If the following condition is met, then the transfer
+ // is not supported.
+ //
+ // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1
+ //
+ // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count
+ // can also be the maximum integer value supported by the CPU, this range
+ // check must be adjusted to avoid all overflow conditions.
+ //
+ // The following form of the range check is equivalent but assumes that
+ // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).
+ //
+ Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS);
+ if (Count == 0) {
+ if (Address > Limit) {
+ return EFI_UNSUPPORTED;
+ }
+ } else {
+ MaxCount = RShiftU64 (Limit, Width);
+ if (MaxCount < (Count - 1)) {
+ return EFI_UNSUPPORTED;
+ }
+ if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
+ return EFI_UNSUPPORTED;
+ }
+ }
+
+ //
+ // Check to see if Buffer is aligned
+ //
+ if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != 0) {
+ return EFI_UNSUPPORTED;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Reads memory-mapped registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[out] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuMemoryServiceRead (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ *Uint8Buffer = MmioRead8 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint64) {
+ *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Writes memory-mapped registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuMemoryServiceWrite (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ MmioWrite8 ((UINTN)Address, *Uint8Buffer);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
+ } else if (OperationWidth == EfiCpuIoWidthUint64) {
+ MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Reads I/O registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[out] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuIoServiceRead (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Address += PcdGet64 (PcdPciIoTranslation);
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ *Uint8Buffer = MmioRead8 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Write I/O registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuIoServiceWrite (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ //
+ // Make sure the parameters are valid
+ //
+ Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Address += PcdGet64 (PcdPciIoTranslation);
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+
+ for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ MmioWrite8 ((UINTN)Address, *Uint8Buffer);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+//
+// CPU I/O 2 Protocol instance
+//
+STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
+ {
+ CpuMemoryServiceRead,
+ CpuMemoryServiceWrite
+ },
+ {
+ CpuIoServiceRead,
+ CpuIoServiceWrite
+ }
+};
+
+
+/**
+ The user Entry Point for module CpuIo2Dxe. The user code starts with this function.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The entry point is executed successfully.
+ @retval other Some error occurs when executing this entry point.
+
+**/
+EFI_STATUS
+EFIAPI
+ArmPciCpuIo2Initialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mHandle,
+ &gEfiCpuIo2ProtocolGuid, &mCpuIo2,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
diff --git a/roms/edk2/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf b/roms/edk2/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf new file mode 100644 index 000000000..2bc4571d0 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf @@ -0,0 +1,47 @@ +## @file
+# Produces the CPU I/O 2 Protocol by using the services of the I/O Library.
+#
+# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmPciCpuIo2Dxe
+ FILE_GUID = 168D1A6E-F4A5-448A-9E95-795661BB3067
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = ArmPciCpuIo2Initialize
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = ARM AARCH64
+#
+
+[Sources]
+ ArmPciCpuIo2Dxe.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ BaseLib
+ DebugLib
+ IoLib
+ PcdLib
+ UefiBootServicesTableLib
+
+[Pcd]
+ gArmTokenSpaceGuid.PcdPciIoTranslation
+
+[Protocols]
+ gEfiCpuIo2ProtocolGuid ## PRODUCES
+
+[Depex]
+ TRUE
diff --git a/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ArmScmiBaseProtocolPrivate.h b/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ArmScmiBaseProtocolPrivate.h new file mode 100644 index 000000000..b99ec465b --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ArmScmiBaseProtocolPrivate.h @@ -0,0 +1,40 @@ +/** @file
+
+ Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ System Control and Management Interface V1.0
+ http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
+ DEN0056A_System_Control_and_Management_Interface.pdf
+**/
+
+#ifndef ARM_SCMI_BASE_PROTOCOL_PRIVATE_H_
+#define ARM_SCMI_BASE_PROTOCOL_PRIVATE_H_
+
+// Return values of BASE_DISCOVER_LIST_PROTOCOLS command.
+typedef struct {
+ UINT32 NumProtocols;
+
+ // Array of four protocols in each element
+ // Total elements = 1 + (NumProtocols-1)/4
+
+ // NOTE: Since EDK2 does not allow flexible array member [] we declare
+ // here array of 1 element length. However below is used as a variable
+ // length array.
+ UINT8 Protocols[1];
+} BASE_DISCOVER_LIST;
+
+/** Initialize Base protocol and install protocol on a given handle.
+
+ @param[in] Handle Handle to install Base protocol.
+
+ @retval EFI_SUCCESS Base protocol interface installed
+ successfully.
+**/
+EFI_STATUS
+ScmiBaseProtocolInit (
+ IN OUT EFI_HANDLE* Handle
+ );
+
+#endif /* ARM_SCMI_BASE_PROTOCOL_PRIVATE_H_ */
diff --git a/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ArmScmiClockProtocolPrivate.h b/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ArmScmiClockProtocolPrivate.h new file mode 100644 index 000000000..43cc3bff8 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ArmScmiClockProtocolPrivate.h @@ -0,0 +1,85 @@ +/** @file
+
+ Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ System Control and Management Interface V1.0
+ http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
+ DEN0056A_System_Control_and_Management_Interface.pdf
+**/
+
+#ifndef ARM_SCMI_CLOCK_PROTOCOL_PRIVATE_H_
+#define ARM_SCMI_CLOCK_PROTOCOL_PRIVATE_H_
+
+#pragma pack(1)
+
+// Clock rate in two 32bit words.
+typedef struct {
+ UINT32 Low;
+ UINT32 High;
+} CLOCK_RATE_DWORD;
+
+// Format of the returned rate array. Linear or Non-linear,.RatesFlag Bit[12]
+#define RATE_FORMAT_SHIFT 12
+#define RATE_FORMAT_MASK 0x0001
+#define RATE_FORMAT(RatesFlags) ((RatesFlags >> RATE_FORMAT_SHIFT) \
+ & RATE_FORMAT_MASK)
+
+// Number of remaining rates after a call to the SCP, RatesFlag Bits[31:16]
+#define NUM_REMAIN_RATES_SHIFT 16
+#define NUM_REMAIN_RATES(RatesFlags) ((RatesFlags >> NUM_REMAIN_RATES_SHIFT))
+
+// Number of rates that are returned by a call.to the SCP, RatesFlag Bits[11:0]
+#define NUM_RATES_MASK 0x0FFF
+#define NUM_RATES(RatesFlags) (RatesFlags & NUM_RATES_MASK)
+
+// Return values for the CLOCK_DESCRIBER_RATE command.
+typedef struct {
+ UINT32 NumRatesFlags;
+
+ // NOTE: Since EDK2 does not allow flexible array member [] we declare
+ // here array of 1 element length. However below is used as a variable
+ // length array.
+ CLOCK_RATE_DWORD Rates[1];
+} CLOCK_DESCRIBE_RATES;
+
+#define CLOCK_SET_DEFAULT_FLAGS 0
+
+// Message parameters for CLOCK_RATE_SET command.
+typedef struct {
+ UINT32 Flags;
+ UINT32 ClockId;
+ CLOCK_RATE_DWORD Rate;
+} CLOCK_RATE_SET_ATTRIBUTES;
+
+
+// Message parameters for CLOCK_CONFIG_SET command.
+typedef struct {
+ UINT32 ClockId;
+ UINT32 Attributes;
+} CLOCK_CONFIG_SET_ATTRIBUTES;
+
+// if ClockAttr Bit[0] is set then clock device is enabled.
+#define CLOCK_ENABLE_MASK 0x1
+#define CLOCK_ENABLED(ClockAttr) ((ClockAttr & CLOCK_ENABLE_MASK) == 1)
+
+typedef struct {
+ UINT32 Attributes;
+ UINT8 ClockName[SCMI_MAX_STR_LEN];
+} CLOCK_ATTRIBUTES;
+
+#pragma pack()
+
+/** Initialize clock management protocol and install protocol on a given handle.
+
+ @param[in] Handle Handle to install clock management protocol.
+
+ @retval EFI_SUCCESS Clock protocol interface installed successfully.
+**/
+EFI_STATUS
+ScmiClockProtocolInit (
+ IN EFI_HANDLE *Handle
+ );
+
+#endif /* ARM_SCMI_CLOCK_PROTOCOL_PRIVATE_H_ */
diff --git a/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf b/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf new file mode 100644 index 000000000..6cd3aa1c8 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf @@ -0,0 +1,48 @@ +#/** @file
+#
+# Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+# System Control and Management Interface V1.0
+# http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
+# DEN0056A_System_Control_and_Management_Interface.pdf
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = ArmScmiDxe
+ FILE_GUID = 9585984C-F027-45E9-AFDF-ADAA6DFAAAC7
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = ArmScmiDxeEntryPoint
+
+[Sources.common]
+ Scmi.c
+ ScmiBaseProtocol.c
+ ScmiClockProtocol.c
+ ScmiDxe.c
+ ScmiPerformanceProtocol.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ ArmLib
+ ArmMtlLib
+ DebugLib
+ IoLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[Protocols]
+ gArmScmiBaseProtocolGuid
+ gArmScmiClockProtocolGuid
+ gArmScmiClock2ProtocolGuid
+ gArmScmiPerformanceProtocolGuid
+
+[Depex]
+ TRUE
+
diff --git a/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ArmScmiPerformanceProtocolPrivate.h b/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ArmScmiPerformanceProtocolPrivate.h new file mode 100644 index 000000000..b274b5ab2 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ArmScmiPerformanceProtocolPrivate.h @@ -0,0 +1,49 @@ +/** @file
+
+ Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ System Control and Management Interface V1.0
+ http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
+ DEN0056A_System_Control_and_Management_Interface.pdf
+**/
+
+#ifndef ARM_SCMI_PERFORMANCE_PROTOCOL_PRIVATE_H_
+#define ARM_SCMI_PERFORMANCE_PROTOCOL_PRIVATE_H_
+
+#include <Protocol/ArmScmiPerformanceProtocol.h>
+
+// Number of performance levels returned by a call to the SCP, Lvls Bits[11:0]
+#define NUM_PERF_LEVELS_MASK 0x0FFF
+#define NUM_PERF_LEVELS(Lvls) (Lvls & NUM_PERF_LEVELS_MASK)
+
+// Number of performance levels remaining after a call to the SCP, Lvls Bits[31:16]
+#define NUM_REMAIN_PERF_LEVELS_SHIFT 16
+#define NUM_REMAIN_PERF_LEVELS(Lvls) (Lvls >> NUM_REMAIN_PERF_LEVELS_SHIFT)
+
+/** Return values for SCMI_MESSAGE_ID_PERFORMANCE_DESCRIBE_LEVELS command.
+ SCMI Spec section 4.5.2.5
+**/
+typedef struct {
+ UINT32 NumLevels;
+
+ // NOTE: Since EDK2 does not allow flexible array member [] we declare
+ // here array of 1 element length. However below is used as a variable
+ // length array.
+ SCMI_PERFORMANCE_LEVEL PerfLevel[1]; // Offset to array of performance levels
+} PERF_DESCRIBE_LEVELS;
+
+/** Initialize performance management protocol and install on a given Handle.
+
+ @param[in] Handle Handle to install performance management
+ protocol.
+
+ @retval EFI_SUCCESS Performance protocol installed successfully.
+**/
+EFI_STATUS
+ScmiPerformanceProtocolInit (
+ IN EFI_HANDLE* Handle
+ );
+
+#endif /* ARM_SCMI_PERFORMANCE_PROTOCOL_PRIVATE_H_ */
diff --git a/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/Scmi.c b/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/Scmi.c new file mode 100644 index 000000000..c4af3ec4e --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/Scmi.c @@ -0,0 +1,251 @@ +/** @file
+
+ Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ System Control and Management Interface V1.0
+ http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
+ DEN0056A_System_Control_and_Management_Interface.pdf
+**/
+
+#include <Library/ArmMtlLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include "ScmiPrivate.h"
+
+// Arbitrary timeout value 20ms.
+#define RESPONSE_TIMEOUT 20000
+
+/** Return a pointer to the message payload.
+
+ @param[out] Payload Holds pointer to the message payload.
+
+ @retval EFI_SUCCESS Payload holds a valid message payload pointer.
+ @retval EFI_TIMEOUT Time out error if MTL channel is busy.
+ @retval EFI_UNSUPPORTED If MTL channel is unsupported.
+**/
+EFI_STATUS
+ScmiCommandGetPayload (
+ OUT UINT32** Payload
+ )
+{
+ EFI_STATUS Status;
+ MTL_CHANNEL *Channel;
+
+ // Get handle to the Channel.
+ Status = MtlGetChannel (MTL_CHANNEL_TYPE_LOW, &Channel);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Payload will not be populated until channel is free.
+ Status = MtlWaitUntilChannelFree (Channel, RESPONSE_TIMEOUT);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Get the address of the payload.
+ *Payload = MtlGetChannelPayload (Channel);
+
+ return EFI_SUCCESS;
+}
+
+/** Execute a SCMI command and receive a response.
+
+ This function uses a MTL channel to transfer message to SCP
+ and waits for a response.
+
+ @param[in] Command Pointer to the SCMI command (Protocol ID
+ and Message ID)
+
+ @param[in,out] PayloadLength SCMI command message length.
+
+ @param[out] OPTIONAL ReturnValues Pointer to SCMI response.
+
+ @retval OUT EFI_SUCCESS Command sent and message received successfully.
+ @retval OUT EFI_UNSUPPORTED Channel not supported.
+ @retval OUT EFI_TIMEOUT Timeout on the channel.
+ @retval OUT EFI_DEVICE_ERROR Channel not ready.
+ @retval OUT EFI_DEVICE_ERROR Message Header corrupted.
+ @retval OUT EFI_DEVICE_ERROR SCMI error.
+**/
+EFI_STATUS
+ScmiCommandExecute (
+ IN SCMI_COMMAND *Command,
+ IN OUT UINT32 *PayloadLength,
+ OUT UINT32 **ReturnValues OPTIONAL
+ )
+{
+ EFI_STATUS Status;
+ SCMI_MESSAGE_RESPONSE *Response;
+ UINT32 MessageHeader;
+ UINT32 ResponseHeader;
+ MTL_CHANNEL *Channel;
+
+ ASSERT (PayloadLength != NULL);
+
+ Status = MtlGetChannel (MTL_CHANNEL_TYPE_LOW, &Channel);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Fill in message header.
+ MessageHeader = SCMI_MESSAGE_HEADER (
+ Command->MessageId,
+ SCMI_MESSAGE_TYPE_COMMAND,
+ Command->ProtocolId
+ );
+
+ // Send payload using MTL channel.
+ Status = MtlSendMessage (
+ Channel,
+ MessageHeader,
+ *PayloadLength
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Wait for the response on the channel.
+ Status = MtlReceiveMessage (Channel, &ResponseHeader, PayloadLength);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // SCMI must return MessageHeader unmodified.
+ if (MessageHeader != ResponseHeader) {
+ ASSERT (FALSE);
+ return EFI_DEVICE_ERROR;
+ }
+
+ Response = (SCMI_MESSAGE_RESPONSE*)MtlGetChannelPayload (Channel);
+
+ if (Response->Status != SCMI_SUCCESS) {
+ DEBUG ((DEBUG_ERROR, "SCMI error: ProtocolId = 0x%x, MessageId = 0x%x, error = %d\n",
+ Command->ProtocolId,
+ Command->MessageId,
+ Response->Status
+ ));
+
+ ASSERT (FALSE);
+ return EFI_DEVICE_ERROR;
+ }
+
+ if (ReturnValues != NULL) {
+ *ReturnValues = Response->ReturnValues;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/** Internal common function useful for common protocol discovery messages.
+
+ @param[in] ProtocolId Protocol Id of the the protocol.
+ @param[in] MesaageId Message Id of the message.
+
+ @param[out] ReturnValues SCMI response return values.
+
+ @retval EFI_SUCCESS Success with valid return values.
+ @retval EFI_DEVICE_ERROR SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+STATIC
+EFI_STATUS
+ScmiProtocolDiscoveryCommon (
+ IN SCMI_PROTOCOL_ID ProtocolId,
+ IN SCMI_MESSAGE_ID MessageId,
+ OUT UINT32 **ReturnValues
+ )
+{
+ SCMI_COMMAND Command;
+ UINT32 PayloadLength = 0;
+
+ Command.ProtocolId = ProtocolId;
+ Command.MessageId = MessageId;
+
+ return ScmiCommandExecute (
+ &Command,
+ &PayloadLength,
+ ReturnValues
+ );
+}
+
+/** Return protocol version from SCP for a given protocol ID.
+
+ @param[in] Protocol ID Protocol ID.
+ @param[out] Version Pointer to version of the protocol.
+
+ @retval EFI_SUCCESS Version holds a valid version received
+ from the SCP.
+ @retval EFI_DEVICE_ERROR SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+EFI_STATUS
+ScmiGetProtocolVersion (
+ IN SCMI_PROTOCOL_ID ProtocolId,
+ OUT UINT32 *Version
+ )
+{
+ EFI_STATUS Status;
+ UINT32 *ProtocolVersion;
+
+ Status = ScmiProtocolDiscoveryCommon (
+ ProtocolId,
+ SCMI_MESSAGE_ID_PROTOCOL_VERSION,
+ (UINT32**)&ProtocolVersion
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ *Version = *ProtocolVersion;
+
+ return EFI_SUCCESS;
+}
+
+/** Return protocol attributes from SCP for a given protocol ID.
+
+ @param[in] Protocol ID Protocol ID.
+ @param[out] ReturnValues Pointer to attributes of the protocol.
+
+ @retval EFI_SUCCESS ReturnValues points to protocol attributes.
+ @retval EFI_DEVICE_ERROR SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+EFI_STATUS
+ScmiGetProtocolAttributes (
+ IN SCMI_PROTOCOL_ID ProtocolId,
+ OUT UINT32 **ReturnValues
+ )
+{
+ return ScmiProtocolDiscoveryCommon (
+ ProtocolId,
+ SCMI_MESSAGE_ID_PROTOCOL_ATTRIBUTES,
+ ReturnValues
+ );
+}
+
+/** Return protocol message attributes from SCP for a given protocol ID.
+
+ @param[in] Protocol ID Protocol ID.
+ @param[out] Attributes Pointer to attributes of the protocol.
+
+ @retval EFI_SUCCESS ReturnValues points to protocol message attributes.
+ @retval EFI_DEVICE_ERROR SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+EFI_STATUS
+ScmiGetProtocolMessageAttributes (
+ IN SCMI_PROTOCOL_ID ProtocolId,
+ OUT UINT32 **ReturnValues
+ )
+{
+ return ScmiProtocolDiscoveryCommon (
+ ProtocolId,
+ SCMI_MESSAGE_ID_PROTOCOL_MESSAGE_ATTRIBUTES,
+ ReturnValues
+ );
+}
diff --git a/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ScmiBaseProtocol.c b/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ScmiBaseProtocol.c new file mode 100644 index 000000000..d89587f9e --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ScmiBaseProtocol.c @@ -0,0 +1,312 @@ +/** @file
+
+ Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ System Control and Management Interface V1.0
+ http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
+ DEN0056A_System_Control_and_Management_Interface.pdf
+**/
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/ArmScmiBaseProtocol.h>
+
+#include "ArmScmiBaseProtocolPrivate.h"
+#include "ScmiPrivate.h"
+
+/** Return version of the Base protocol supported by SCP firmware.
+
+ @param[in] This A Pointer to SCMI_BASE_PROTOCOL Instance.
+
+ @param[out] Version Version of the supported SCMI Base protocol.
+
+ @retval EFI_SUCCESS The version of the protocol is returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+STATIC
+EFI_STATUS
+BaseGetVersion (
+ IN SCMI_BASE_PROTOCOL *This,
+ OUT UINT32 *Version
+ )
+{
+ return ScmiGetProtocolVersion (SCMI_PROTOCOL_ID_BASE, Version);
+}
+
+/** Return total number of SCMI protocols supported by the SCP firmware.
+
+ @param[in] This A Pointer to SCMI_BASE_PROTOCOL Instance.
+
+ @param[out] TotalProtocols Total number of SCMI protocols supported.
+
+ @retval EFI_SUCCESS Total number of protocols supported are returned.
+ @retval EFI_DEVICE_ERROR SCP returns a SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+STATIC
+EFI_STATUS
+BaseGetTotalProtocols (
+ IN SCMI_BASE_PROTOCOL *This,
+ OUT UINT32 *TotalProtocols
+ )
+{
+ EFI_STATUS Status;
+ UINT32 *ReturnValues;
+
+ Status = ScmiGetProtocolAttributes (SCMI_PROTOCOL_ID_BASE, &ReturnValues);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ *TotalProtocols = SCMI_TOTAL_PROTOCOLS (ReturnValues[0]);
+
+ return EFI_SUCCESS;
+}
+
+/** Common function which returns vendor details.
+
+ @param[in] MessageId SCMI_MESSAGE_ID_BASE_DISCOVER_VENDOR
+ OR
+ SCMI_MESSAGE_ID_BASE_DISCOVER_SUB_VENDOR
+
+ @param[out] VendorIdentifier ASCII name of the vendor/subvendor.
+
+ @retval EFI_SUCCESS VendorIdentifier is returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+STATIC
+EFI_STATUS
+BaseDiscoverVendorDetails (
+ IN SCMI_MESSAGE_ID_BASE MessageId,
+ OUT UINT8 VendorIdentifier[SCMI_MAX_STR_LEN]
+ )
+{
+ EFI_STATUS Status;
+ UINT32 *ReturnValues;
+ SCMI_COMMAND Cmd;
+ UINT32 PayloadLength;
+
+ Cmd.ProtocolId = SCMI_PROTOCOL_ID_BASE;
+ Cmd.MessageId = MessageId;
+
+ PayloadLength = 0;
+
+ Status = ScmiCommandExecute (
+ &Cmd,
+ &PayloadLength,
+ &ReturnValues
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ AsciiStrCpyS (
+ (CHAR8*)VendorIdentifier,
+ SCMI_MAX_STR_LEN,
+ (CONST CHAR8*)ReturnValues
+ );
+
+ return EFI_SUCCESS;
+}
+
+/** Return vendor name.
+
+ @param[in] This A Pointer to SCMI_BASE_PROTOCOL Instance.
+
+ @param[out] VendorIdentifier Null terminated ASCII string of up to
+ 16 bytes with a vendor name.
+
+ @retval EFI_SUCCESS VendorIdentifier is returned.
+ @retval EFI_DEVICE_ERROR SCP returns a SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+STATIC
+EFI_STATUS
+BaseDiscoverVendor (
+ IN SCMI_BASE_PROTOCOL *This,
+ OUT UINT8 VendorIdentifier[SCMI_MAX_STR_LEN]
+ )
+{
+ return BaseDiscoverVendorDetails (
+ SCMI_MESSAGE_ID_BASE_DISCOVER_VENDOR,
+ VendorIdentifier
+ );
+}
+
+/** Return sub vendor name.
+
+ @param[in] This A Pointer to SCMI_BASE_PROTOCOL Instance.
+
+ @param[out] VendorIdentifier Null terminated ASCII string of up to
+ 16 bytes with a sub vendor name.
+
+ @retval EFI_SUCCESS VendorIdentifier is returned.
+ @retval EFI_DEVICE_ERROR SCP returns a SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+EFI_STATUS
+BaseDiscoverSubVendor (
+ IN SCMI_BASE_PROTOCOL *This,
+ OUT UINT8 VendorIdentifier[SCMI_MAX_STR_LEN]
+ )
+{
+ return BaseDiscoverVendorDetails (
+ SCMI_MESSAGE_ID_BASE_DISCOVER_SUB_VENDOR,
+ VendorIdentifier
+ );
+}
+
+/** Return implementation version.
+
+ @param[in] This A Pointer to SCMI_BASE_PROTOCOL Instance.
+
+ @param[out] ImplementationVersion Vendor specific implementation version.
+
+ @retval EFI_SUCCESS Implementation version is returned.
+ @retval EFI_DEVICE_ERROR SCP returns a SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+STATIC
+EFI_STATUS
+BaseDiscoverImplVersion (
+ IN SCMI_BASE_PROTOCOL *This,
+ OUT UINT32 *ImplementationVersion
+ )
+{
+ EFI_STATUS Status;
+ UINT32 *ReturnValues;
+ SCMI_COMMAND Cmd;
+ UINT32 PayloadLength;
+
+ Cmd.ProtocolId = SCMI_PROTOCOL_ID_BASE;
+ Cmd.MessageId = SCMI_MESSAGE_ID_BASE_DISCOVER_IMPLEMENTATION_VERSION;
+
+ PayloadLength = 0;
+
+ Status = ScmiCommandExecute (
+ &Cmd,
+ &PayloadLength,
+ &ReturnValues
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ *ImplementationVersion = ReturnValues[0];
+
+ return EFI_SUCCESS;
+}
+
+/** Return list of protocols.
+
+ @param[in] This A Pointer to SCMI_BASE_PROTOCOL Instance.
+
+ @param[out] ProtocolListSize Size of the ProtocolList.
+
+ @param[out] ProtocolList Protocol list.
+
+ @retval EFI_SUCCESS List of protocols is returned.
+ @retval EFI_BUFFER_TOO_SMALL ProtocolListSize is too small for the result.
+ It has been updated to the size needed.
+ @retval EFI_DEVICE_ERROR SCP returns a SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+STATIC
+EFI_STATUS
+BaseDiscoverListProtocols (
+ IN SCMI_BASE_PROTOCOL *This,
+ IN OUT UINT32 *ProtocolListSize,
+ OUT UINT8 *ProtocolList
+ )
+{
+ EFI_STATUS Status;
+ UINT32 TotalProtocols;
+ UINT32 *MessageParams;
+ BASE_DISCOVER_LIST *DiscoverList;
+ UINT32 Skip;
+ UINT32 Index;
+ SCMI_COMMAND Cmd;
+ UINT32 PayloadLength;
+ UINT32 RequiredSize;
+
+ Status = BaseGetTotalProtocols (This, &TotalProtocols);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = ScmiCommandGetPayload (&MessageParams);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ RequiredSize = sizeof (UINT8) * TotalProtocols;
+ if (*ProtocolListSize < RequiredSize) {
+ *ProtocolListSize = RequiredSize;
+ return EFI_BUFFER_TOO_SMALL;
+ }
+
+ Cmd.ProtocolId = SCMI_PROTOCOL_ID_BASE;
+ Cmd.MessageId = SCMI_MESSAGE_ID_BASE_DISCOVER_LIST_PROTOCOLS;
+
+ Skip = 0;
+
+ while (Skip < TotalProtocols) {
+
+ *MessageParams = Skip;
+
+ // Note PayloadLength is a IN/OUT parameter.
+ PayloadLength = sizeof (Skip);
+
+ Status = ScmiCommandExecute (
+ &Cmd,
+ &PayloadLength,
+ (UINT32**)&DiscoverList
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ for (Index = 0; Index < DiscoverList->NumProtocols; Index++) {
+ ProtocolList[Skip++] = DiscoverList->Protocols[Index];
+ }
+ }
+
+ *ProtocolListSize = RequiredSize;
+
+ return EFI_SUCCESS;
+}
+
+// Instance of the SCMI Base protocol.
+STATIC CONST SCMI_BASE_PROTOCOL BaseProtocol = {
+ BaseGetVersion,
+ BaseGetTotalProtocols,
+ BaseDiscoverVendor,
+ BaseDiscoverSubVendor,
+ BaseDiscoverImplVersion,
+ BaseDiscoverListProtocols
+};
+
+/** Initialize Base protocol and install protocol on a given handle.
+
+ @param[in] Handle Handle to install Base protocol.
+
+ @retval EFI_SUCCESS Base protocol interface installed
+ successfully.
+**/
+EFI_STATUS
+ScmiBaseProtocolInit (
+ IN OUT EFI_HANDLE* Handle
+ )
+{
+ return gBS->InstallMultipleProtocolInterfaces (
+ Handle,
+ &gArmScmiBaseProtocolGuid,
+ &BaseProtocol,
+ NULL
+ );
+}
diff --git a/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ScmiClockProtocol.c b/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ScmiClockProtocol.c new file mode 100644 index 000000000..ac0d21d86 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ScmiClockProtocol.c @@ -0,0 +1,474 @@ +/** @file
+
+ Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ System Control and Management Interface V1.0
+ http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
+ DEN0056A_System_Control_and_Management_Interface.pdf
+**/
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/ArmScmiClockProtocol.h>
+#include <Protocol/ArmScmiClock2Protocol.h>
+
+#include "ArmScmiClockProtocolPrivate.h"
+#include "ScmiPrivate.h"
+
+/** Convert to 64 bit value from two 32 bit words.
+
+ @param[in] Low Lower 32 bits.
+ @param[in] High Higher 32 bits.
+
+ @retval UINT64 64 bit value.
+**/
+STATIC
+UINT64
+ConvertTo64Bit (
+ IN UINT32 Low,
+ IN UINT32 High
+ )
+{
+ return (Low | ((UINT64)High << 32));
+}
+
+/** Return version of the clock management protocol supported by SCP firmware.
+
+ @param[in] This A Pointer to SCMI_CLOCK_PROTOCOL Instance.
+
+ @param[out] Version Version of the supported SCMI Clock management protocol.
+
+ @retval EFI_SUCCESS The version is returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+STATIC
+EFI_STATUS
+ClockGetVersion (
+ IN SCMI_CLOCK_PROTOCOL *This,
+ OUT UINT32 *Version
+ )
+{
+ return ScmiGetProtocolVersion (SCMI_PROTOCOL_ID_CLOCK, Version);
+}
+
+/** Return total number of clock devices supported by the clock management
+ protocol.
+
+ @param[in] This A Pointer to SCMI_CLOCK_PROTOCOL Instance.
+
+ @param[out] TotalClocks Total number of clocks supported.
+
+ @retval EFI_SUCCESS Total number of clocks supported is returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+STATIC
+EFI_STATUS
+ClockGetTotalClocks (
+ IN SCMI_CLOCK_PROTOCOL *This,
+ OUT UINT32 *TotalClocks
+ )
+{
+ EFI_STATUS Status;
+ UINT32 *ReturnValues;
+
+ Status = ScmiGetProtocolAttributes (SCMI_PROTOCOL_ID_CLOCK, &ReturnValues);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ *TotalClocks = SCMI_CLOCK_PROTOCOL_TOTAL_CLKS (ReturnValues[0]);
+
+ return EFI_SUCCESS;
+}
+
+/** Return attributes of a clock device.
+
+ @param[in] This A Pointer to SCMI_CLOCK_PROTOCOL Instance.
+ @param[in] ClockId Identifier for the clock device.
+
+ @param[out] Enabled If TRUE, the clock device is enabled.
+ @param[out] ClockAsciiName A NULL terminated ASCII string with the clock
+ name, of up to 16 bytes.
+
+ @retval EFI_SUCCESS Clock device attributes are returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+STATIC
+EFI_STATUS
+ClockGetClockAttributes (
+ IN SCMI_CLOCK_PROTOCOL *This,
+ IN UINT32 ClockId,
+ OUT BOOLEAN *Enabled,
+ OUT CHAR8 *ClockAsciiName
+ )
+{
+ EFI_STATUS Status;
+
+ UINT32 *MessageParams;
+ CLOCK_ATTRIBUTES *ClockAttributes;
+ SCMI_COMMAND Cmd;
+ UINT32 PayloadLength;
+
+ Status = ScmiCommandGetPayload (&MessageParams);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ *MessageParams = ClockId;
+
+ Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK;
+ Cmd.MessageId = SCMI_MESSAGE_ID_CLOCK_ATTRIBUTES;
+
+ PayloadLength = sizeof (ClockId);
+
+ Status = ScmiCommandExecute (
+ &Cmd,
+ &PayloadLength,
+ (UINT32**)&ClockAttributes
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ // TRUE if bit 0 of ClockAttributes->Attributes is set.
+ *Enabled = CLOCK_ENABLED (ClockAttributes->Attributes);
+
+ AsciiStrCpyS (
+ ClockAsciiName,
+ SCMI_MAX_STR_LEN,
+ (CONST CHAR8*)ClockAttributes->ClockName
+ );
+
+ return EFI_SUCCESS;
+}
+
+/** Return list of rates supported by a given clock device.
+
+ @param[in] This A pointer to SCMI_CLOCK_PROTOCOL Instance.
+ @param[in] ClockId Identifier for the clock device.
+
+ @param[out] Format SCMI_CLOCK_RATE_FORMAT_DISCRETE: Clock device
+ supports range of clock rates which are non-linear.
+
+ SCMI_CLOCK_RATE_FORMAT_LINEAR: Clock device supports
+ range of linear clock rates from Min to Max in steps.
+
+ @param[out] TotalRates Total number of rates.
+
+ @param[in,out] RateArraySize Size of the RateArray.
+
+ @param[out] RateArray List of clock rates.
+
+ @retval EFI_SUCCESS List of clock rates is returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval EFI_BUFFER_TOO_SMALL RateArraySize is too small for the result.
+ It has been updated to the size needed.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+STATIC
+EFI_STATUS
+ClockDescribeRates (
+ IN SCMI_CLOCK_PROTOCOL *This,
+ IN UINT32 ClockId,
+ OUT SCMI_CLOCK_RATE_FORMAT *Format,
+ OUT UINT32 *TotalRates,
+ IN OUT UINT32 *RateArraySize,
+ OUT SCMI_CLOCK_RATE *RateArray
+ )
+{
+ EFI_STATUS Status;
+
+ UINT32 PayloadLength;
+ SCMI_COMMAND Cmd;
+ UINT32 *MessageParams;
+ CLOCK_DESCRIBE_RATES *DescribeRates;
+ CLOCK_RATE_DWORD *Rate;
+
+ UINT32 RequiredArraySize = 0;
+ UINT32 RateIndex = 0;
+ UINT32 RateNo;
+ UINT32 RateOffset;
+
+ *TotalRates = 0;
+
+ Status = ScmiCommandGetPayload (&MessageParams);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK;
+ Cmd.MessageId = SCMI_MESSAGE_ID_CLOCK_DESCRIBE_RATES;
+
+ *MessageParams++ = ClockId;
+
+ do {
+
+ *MessageParams = RateIndex;
+
+ // Set Payload length, note PayloadLength is a IN/OUT parameter.
+ PayloadLength = sizeof (ClockId) + sizeof (RateIndex);
+
+ // Execute and wait for response on a SCMI channel.
+ Status = ScmiCommandExecute (
+ &Cmd,
+ &PayloadLength,
+ (UINT32**)&DescribeRates
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if (*TotalRates == 0) {
+ // In the first iteration we will get number of returned rates and number
+ // of remaining rates. With this information calculate required size
+ // for rate array. If provided RateArraySize is less, return an
+ // error.
+
+ *Format = RATE_FORMAT (DescribeRates->NumRatesFlags);
+
+ *TotalRates = NUM_RATES (DescribeRates->NumRatesFlags)
+ + NUM_REMAIN_RATES (DescribeRates->NumRatesFlags);
+
+ if (*Format == SCMI_CLOCK_RATE_FORMAT_DISCRETE) {
+ RequiredArraySize = (*TotalRates) * sizeof (UINT64);
+ } else {
+ // We need to return triplet of 64 bit value for each rate
+ RequiredArraySize = (*TotalRates) * 3 * sizeof (UINT64);
+ }
+
+ if (RequiredArraySize > (*RateArraySize)) {
+ *RateArraySize = RequiredArraySize;
+ return EFI_BUFFER_TOO_SMALL;
+ }
+ }
+
+ RateOffset = 0;
+
+ if (*Format == SCMI_CLOCK_RATE_FORMAT_DISCRETE) {
+ for (RateNo = 0; RateNo < NUM_RATES (DescribeRates->NumRatesFlags); RateNo++) {
+ Rate = &DescribeRates->Rates[RateOffset++];
+ // Non-linear discrete rates.
+ RateArray[RateIndex++].Rate = ConvertTo64Bit (Rate->Low, Rate->High);
+ }
+ } else {
+ for (RateNo = 0; RateNo < NUM_RATES (DescribeRates->NumRatesFlags); RateNo++) {
+ // Linear clock rates from minimum to maximum in steps
+ // Minimum clock rate.
+ Rate = &DescribeRates->Rates[RateOffset++];
+ RateArray[RateIndex].Min = ConvertTo64Bit (Rate->Low, Rate->High);
+
+ Rate = &DescribeRates->Rates[RateOffset++];
+ // Maximum clock rate.
+ RateArray[RateIndex].Max = ConvertTo64Bit (Rate->Low, Rate->High);
+
+ Rate = &DescribeRates->Rates[RateOffset++];
+ // Step.
+ RateArray[RateIndex++].Step = ConvertTo64Bit (Rate->Low, Rate->High);
+ }
+ }
+ } while (NUM_REMAIN_RATES (DescribeRates->NumRatesFlags) != 0);
+
+ // Update RateArraySize with RequiredArraySize.
+ *RateArraySize = RequiredArraySize;
+
+ return EFI_SUCCESS;
+}
+
+/** Get clock rate.
+
+ @param[in] This A Pointer to SCMI_CLOCK_PROTOCOL Instance.
+ @param[in] ClockId Identifier for the clock device.
+
+ @param[out] Rate Clock rate.
+
+ @retval EFI_SUCCESS Clock rate is returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+STATIC
+EFI_STATUS
+ClockRateGet (
+ IN SCMI_CLOCK_PROTOCOL *This,
+ IN UINT32 ClockId,
+ OUT UINT64 *Rate
+ )
+{
+ EFI_STATUS Status;
+
+ UINT32 *MessageParams;
+ CLOCK_RATE_DWORD *ClockRate;
+ SCMI_COMMAND Cmd;
+
+ UINT32 PayloadLength;
+
+ Status = ScmiCommandGetPayload (&MessageParams);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Fill arguments for clock protocol command.
+ *MessageParams = ClockId;
+
+ Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK;
+ Cmd.MessageId = SCMI_MESSAGE_ID_CLOCK_RATE_GET;
+
+ PayloadLength = sizeof (ClockId);
+
+ // Execute and wait for response on a SCMI channel.
+ Status = ScmiCommandExecute (
+ &Cmd,
+ &PayloadLength,
+ (UINT32**)&ClockRate
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ *Rate = ConvertTo64Bit (ClockRate->Low, ClockRate->High);
+
+ return EFI_SUCCESS;
+}
+
+/** Set clock rate.
+
+ @param[in] This A Pointer to SCMI_CLOCK_PROTOCOL Instance.
+ @param[in] ClockId Identifier for the clock device.
+ @param[in] Rate Clock rate.
+
+ @retval EFI_SUCCESS Clock rate set success.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+STATIC
+EFI_STATUS
+ClockRateSet (
+ IN SCMI_CLOCK_PROTOCOL *This,
+ IN UINT32 ClockId,
+ IN UINT64 Rate
+ )
+{
+ EFI_STATUS Status;
+ CLOCK_RATE_SET_ATTRIBUTES *ClockRateSetAttributes;
+ SCMI_COMMAND Cmd;
+ UINT32 PayloadLength;
+
+ Status = ScmiCommandGetPayload ((UINT32**)&ClockRateSetAttributes);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Fill arguments for clock protocol command.
+ ClockRateSetAttributes->ClockId = ClockId;
+ ClockRateSetAttributes->Flags = CLOCK_SET_DEFAULT_FLAGS;
+ ClockRateSetAttributes->Rate.Low = (UINT32)Rate;
+ ClockRateSetAttributes->Rate.High = (UINT32)(Rate >> 32);
+
+ Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK;
+ Cmd.MessageId = SCMI_MESSAGE_ID_CLOCK_RATE_SET;
+
+ PayloadLength = sizeof (CLOCK_RATE_SET_ATTRIBUTES);
+
+ // Execute and wait for response on a SCMI channel.
+ Status = ScmiCommandExecute (
+ &Cmd,
+ &PayloadLength,
+ NULL
+ );
+
+ return Status;
+}
+
+/** Enable/Disable specified clock.
+
+ @param[in] This A Pointer to SCMI_CLOCK_PROTOCOL Instance.
+ @param[in] ClockId Identifier for the clock device.
+ @param[in] Enable TRUE to enable, FALSE to disable.
+
+ @retval EFI_SUCCESS Clock enable/disable successful.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+STATIC
+EFI_STATUS
+ClockEnable (
+ IN SCMI_CLOCK2_PROTOCOL *This,
+ IN UINT32 ClockId,
+ IN BOOLEAN Enable
+ )
+{
+ EFI_STATUS Status;
+ CLOCK_CONFIG_SET_ATTRIBUTES *ClockConfigSetAttributes;
+ SCMI_COMMAND Cmd;
+ UINT32 PayloadLength;
+
+ Status = ScmiCommandGetPayload ((UINT32**)&ClockConfigSetAttributes);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Fill arguments for clock protocol command.
+ ClockConfigSetAttributes->ClockId = ClockId;
+ ClockConfigSetAttributes->Attributes = Enable ? BIT0 : 0;
+
+ Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK;
+ Cmd.MessageId = SCMI_MESSAGE_ID_CLOCK_CONFIG_SET;
+
+ PayloadLength = sizeof (CLOCK_CONFIG_SET_ATTRIBUTES);
+
+ // Execute and wait for response on a SCMI channel.
+ Status = ScmiCommandExecute (
+ &Cmd,
+ &PayloadLength,
+ NULL
+ );
+
+ return Status;
+}
+
+// Instance of the SCMI clock management protocol.
+STATIC CONST SCMI_CLOCK_PROTOCOL ScmiClockProtocol = {
+ ClockGetVersion,
+ ClockGetTotalClocks,
+ ClockGetClockAttributes,
+ ClockDescribeRates,
+ ClockRateGet,
+ ClockRateSet
+ };
+
+// Instance of the SCMI clock management protocol.
+STATIC CONST SCMI_CLOCK2_PROTOCOL ScmiClock2Protocol = {
+ (SCMI_CLOCK2_GET_VERSION)ClockGetVersion,
+ (SCMI_CLOCK2_GET_TOTAL_CLOCKS)ClockGetTotalClocks,
+ (SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES)ClockGetClockAttributes,
+ (SCMI_CLOCK2_DESCRIBE_RATES)ClockDescribeRates,
+ (SCMI_CLOCK2_RATE_GET)ClockRateGet,
+ (SCMI_CLOCK2_RATE_SET)ClockRateSet,
+ SCMI_CLOCK2_PROTOCOL_VERSION,
+ ClockEnable
+ };
+
+/** Initialize clock management protocol and install protocol on a given handle.
+
+ @param[in] Handle Handle to install clock management protocol.
+
+ @retval EFI_SUCCESS Clock protocol interface installed successfully.
+**/
+EFI_STATUS
+ScmiClockProtocolInit (
+ IN EFI_HANDLE* Handle
+ )
+{
+ return gBS->InstallMultipleProtocolInterfaces (
+ Handle,
+ &gArmScmiClockProtocolGuid,
+ &ScmiClockProtocol,
+ &gArmScmiClock2ProtocolGuid,
+ &ScmiClock2Protocol,
+ NULL
+ );
+}
diff --git a/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ScmiDxe.c b/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ScmiDxe.c new file mode 100644 index 000000000..e95f56e67 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ScmiDxe.c @@ -0,0 +1,147 @@ +/** @file
+
+ Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ System Control and Management Interface V1.0
+ http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
+ DEN0056A_System_Control_and_Management_Interface.pdf
+**/
+
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/ArmScmiBaseProtocol.h>
+#include <Protocol/ArmScmiClockProtocol.h>
+#include <Protocol/ArmScmiPerformanceProtocol.h>
+
+#include "ArmScmiBaseProtocolPrivate.h"
+#include "ArmScmiClockProtocolPrivate.h"
+#include "ArmScmiPerformanceProtocolPrivate.h"
+#include "ScmiDxe.h"
+#include "ScmiPrivate.h"
+
+STATIC CONST SCMI_PROTOCOL_ENTRY Protocols[] = {
+ { SCMI_PROTOCOL_ID_BASE, ScmiBaseProtocolInit },
+ { SCMI_PROTOCOL_ID_PERFORMANCE, ScmiPerformanceProtocolInit },
+ { SCMI_PROTOCOL_ID_CLOCK, ScmiClockProtocolInit }
+};
+
+/** ARM SCMI driver entry point function.
+
+ This function installs the SCMI Base protocol and a list of other
+ protocols is queried using the Base protocol. If protocol is supported,
+ driver will call each protocol init function to install the protocol on
+ the ImageHandle.
+
+ @param[in] ImageHandle Handle to this EFI Image which will be used to
+ install Base, Clock and Performance protocols.
+ @param[in] SystemTable A pointer to boot time system table.
+
+ @retval EFI_SUCCESS Driver initalized successfully.
+ @retval EFI_UNSUPPORTED If SCMI base protocol version is not supported.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+EFI_STATUS
+EFIAPI
+ArmScmiDxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ SCMI_BASE_PROTOCOL *BaseProtocol;
+ UINT32 Version;
+ UINT32 Index;
+ UINT32 NumProtocols;
+ UINT32 ProtocolIndex;
+ UINT8 *SupportedList;
+ UINT32 SupportedListSize;
+
+ // Every SCMI implementation must implement the base protocol.
+ ASSERT (Protocols[0].Id == SCMI_PROTOCOL_ID_BASE);
+
+ Status = ScmiBaseProtocolInit (&ImageHandle);
+ if (EFI_ERROR (Status)) {
+ ASSERT (FALSE);
+ return Status;
+ }
+
+ Status = gBS->LocateProtocol (
+ &gArmScmiBaseProtocolGuid,
+ NULL,
+ (VOID**)&BaseProtocol
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT (FALSE);
+ return Status;
+ }
+
+ // Get SCMI Base protocol version.
+ Status = BaseProtocol->GetVersion (BaseProtocol, &Version);
+ if (EFI_ERROR (Status)) {
+ ASSERT (FALSE);
+ return Status;
+ }
+
+ if (Version != BASE_PROTOCOL_VERSION) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ // Apart from Base protocol, SCMI may implement various other protocols,
+ // query total protocols implemented by the SCP firmware.
+ NumProtocols = 0;
+ Status = BaseProtocol->GetTotalProtocols (BaseProtocol, &NumProtocols);
+ if (EFI_ERROR (Status)) {
+ ASSERT (FALSE);
+ return Status;
+ }
+
+ ASSERT (NumProtocols != 0);
+
+ SupportedListSize = (NumProtocols * sizeof (*SupportedList));
+
+ Status = gBS->AllocatePool (
+ EfiBootServicesData,
+ SupportedListSize,
+ (VOID**)&SupportedList
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT (FALSE);
+ return Status;
+ }
+
+ // Get the list of protocols supported by SCP firmware on the platform.
+ Status = BaseProtocol->DiscoverListProtocols (
+ BaseProtocol,
+ &SupportedListSize,
+ SupportedList
+ );
+ if (EFI_ERROR (Status)) {
+ gBS->FreePool (SupportedList);
+ ASSERT (FALSE);
+ return Status;
+ }
+
+ // Install supported protocol on ImageHandle.
+ for (ProtocolIndex = 1; ProtocolIndex < ARRAY_SIZE (Protocols);
+ ProtocolIndex++) {
+ for (Index = 0; Index < NumProtocols; Index++) {
+ if (Protocols[ProtocolIndex].Id == SupportedList[Index]) {
+ Status = Protocols[ProtocolIndex].InitFn (&ImageHandle);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+ break;
+ }
+ }
+ }
+
+ gBS->FreePool (SupportedList);
+
+ return EFI_SUCCESS;
+}
diff --git a/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ScmiDxe.h b/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ScmiDxe.h new file mode 100644 index 000000000..28242aab1 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ScmiDxe.h @@ -0,0 +1,36 @@ +/** @file
+
+ Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ System Control and Management Interface V1.0
+ http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
+ DEN0056A_System_Control_and_Management_Interface.pdf
+**/
+#ifndef SCMI_DXE_H_
+#define SCMI_DXE_H_
+
+#include "ScmiPrivate.h"
+
+#define MAX_VENDOR_LEN SCMI_MAX_STR_LEN
+
+/** Pointer to protocol initialization function.
+
+ @param[in] Handle A pointer to the EFI_HANDLE on which the protocol
+ interface is to be installed.
+
+ @retval EFI_SUCCESS Protocol interface installed successfully.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *SCMI_PROTOCOL_INIT_FXN)(
+ IN EFI_HANDLE *Handle
+ );
+
+typedef struct {
+ SCMI_PROTOCOL_ID Id; // Protocol Id.
+ SCMI_PROTOCOL_INIT_FXN InitFn; // Protocol init function.
+} SCMI_PROTOCOL_ENTRY;
+
+#endif /* SCMI_DXE_H_ */
diff --git a/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ScmiPerformanceProtocol.c b/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ScmiPerformanceProtocol.c new file mode 100644 index 000000000..712f95d6e --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ScmiPerformanceProtocol.c @@ -0,0 +1,451 @@ +/** @file
+
+ Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ System Control and Management Interface V1.0
+ http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
+ DEN0056A_System_Control_and_Management_Interface.pdf
+**/
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/ArmScmiPerformanceProtocol.h>
+
+#include "ArmScmiPerformanceProtocolPrivate.h"
+#include "ScmiPrivate.h"
+
+/** Return version of the performance management protocol supported by SCP.
+ firmware.
+
+ @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance.
+
+ @param[out] Version Version of the supported SCMI performance management
+ protocol.
+
+ @retval EFI_SUCCESS The version is returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+STATIC
+EFI_STATUS
+PerformanceGetVersion (
+ IN SCMI_PERFORMANCE_PROTOCOL *This,
+ OUT UINT32 *Version
+ )
+{
+ return ScmiGetProtocolVersion (SCMI_PROTOCOL_ID_PERFORMANCE, Version);
+}
+
+/** Return protocol attributes of the performance management protocol.
+
+ @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance.
+
+ @param[out] Attributes Protocol attributes.
+
+ @retval EFI_SUCCESS Protocol attributes are returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+STATIC
+EFI_STATUS
+PerformanceGetAttributes (
+ IN SCMI_PERFORMANCE_PROTOCOL *This,
+ OUT SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES *Attributes
+ )
+{
+ EFI_STATUS Status;
+ UINT32* ReturnValues;
+
+ Status = ScmiGetProtocolAttributes (
+ SCMI_PROTOCOL_ID_PERFORMANCE,
+ &ReturnValues
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ CopyMem (
+ Attributes,
+ ReturnValues,
+ sizeof (SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES)
+ );
+
+ return EFI_SUCCESS;
+}
+
+/** Return performance domain attributes.
+
+ @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance.
+ @param[in] DomainId Identifier for the performance domain.
+
+ @param[out] Attributes Performance domain attributes.
+
+ @retval EFI_SUCCESS Domain attributes are returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+STATIC
+EFI_STATUS
+PerformanceDomainAttributes (
+ IN SCMI_PERFORMANCE_PROTOCOL *This,
+ IN UINT32 DomainId,
+ OUT SCMI_PERFORMANCE_DOMAIN_ATTRIBUTES *DomainAttributes
+ )
+{
+ EFI_STATUS Status;
+ UINT32 *MessageParams;
+ UINT32 *ReturnValues;
+ UINT32 PayloadLength;
+ SCMI_COMMAND Cmd;
+
+ Status = ScmiCommandGetPayload (&MessageParams);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ *MessageParams = DomainId;
+
+ Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE;
+ Cmd.MessageId = SCMI_MESSAGE_ID_PERFORMANCE_DOMAIN_ATTRIBUTES;
+
+ PayloadLength = sizeof (DomainId);
+
+ Status = ScmiCommandExecute (
+ &Cmd,
+ &PayloadLength,
+ &ReturnValues
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ CopyMem (
+ DomainAttributes,
+ ReturnValues,
+ sizeof (SCMI_PERFORMANCE_DOMAIN_ATTRIBUTES)
+ );
+
+ return EFI_SUCCESS;
+}
+
+/** Return list of performance domain levels of a given domain.
+
+ @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance.
+ @param[in] DomainId Identifier for the performance domain.
+
+ @param[out] NumLevels Total number of levels a domain can support.
+
+ @param[in,out] LevelArraySize Size of the performance level array.
+
+ @param[out] LevelArray Array of the performance levels.
+
+ @retval EFI_SUCCESS Domain levels are returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval EFI_BUFFER_TOO_SMALL LevelArraySize is too small for the result.
+ It has been updated to the size needed.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+STATIC
+EFI_STATUS
+PerformanceDescribeLevels (
+ IN SCMI_PERFORMANCE_PROTOCOL *This,
+ IN UINT32 DomainId,
+ OUT UINT32 *NumLevels,
+ IN OUT UINT32 *LevelArraySize,
+ OUT SCMI_PERFORMANCE_LEVEL *LevelArray
+ )
+{
+ EFI_STATUS Status;
+ UINT32 PayloadLength;
+ SCMI_COMMAND Cmd;
+ UINT32* MessageParams;
+ UINT32 LevelIndex;
+ UINT32 RequiredSize;
+ UINT32 LevelNo;
+ UINT32 ReturnNumLevels;
+ UINT32 ReturnRemainNumLevels;
+
+ PERF_DESCRIBE_LEVELS *Levels;
+
+ Status = ScmiCommandGetPayload (&MessageParams);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ LevelIndex = 0;
+ RequiredSize = 0;
+
+ *MessageParams++ = DomainId;
+
+ Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE;
+ Cmd.MessageId = SCMI_MESSAGE_ID_PERFORMANCE_DESCRIBE_LEVELS;
+
+ do {
+
+ *MessageParams = LevelIndex;
+
+ // Note, PayloadLength is an IN/OUT parameter.
+ PayloadLength = sizeof (DomainId) + sizeof (LevelIndex);
+
+ Status = ScmiCommandExecute (
+ &Cmd,
+ &PayloadLength,
+ (UINT32**)&Levels
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ ReturnNumLevels = NUM_PERF_LEVELS (Levels->NumLevels);
+ ReturnRemainNumLevels = NUM_REMAIN_PERF_LEVELS (Levels->NumLevels);
+
+ if (RequiredSize == 0) {
+ *NumLevels = ReturnNumLevels + ReturnRemainNumLevels;
+
+ RequiredSize = (*NumLevels) * sizeof (SCMI_PERFORMANCE_LEVEL);
+ if (RequiredSize > (*LevelArraySize)) {
+ // Update LevelArraySize with required size.
+ *LevelArraySize = RequiredSize;
+ return EFI_BUFFER_TOO_SMALL;
+ }
+ }
+
+ for (LevelNo = 0; LevelNo < ReturnNumLevels; LevelNo++) {
+ CopyMem (
+ &LevelArray[LevelIndex++],
+ &Levels->PerfLevel[LevelNo],
+ sizeof (SCMI_PERFORMANCE_LEVEL)
+ );
+ }
+
+ } while (ReturnRemainNumLevels != 0);
+
+ *LevelArraySize = RequiredSize;
+
+ return EFI_SUCCESS;
+}
+
+/** Set performance limits of a domain.
+
+ @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance.
+ @param[in] DomainId Identifier for the performance domain.
+ @param[in] Limit Performance limit to set.
+
+ @retval EFI_SUCCESS Performance limits set successfully.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+EFI_STATUS
+PerformanceLimitsSet (
+ IN SCMI_PERFORMANCE_PROTOCOL *This,
+ IN UINT32 DomainId,
+ IN SCMI_PERFORMANCE_LIMITS *Limits
+ )
+{
+ EFI_STATUS Status;
+ UINT32 PayloadLength;
+ SCMI_COMMAND Cmd;
+ UINT32 *MessageParams;
+
+ Status = ScmiCommandGetPayload (&MessageParams);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ *MessageParams++ = DomainId;
+ *MessageParams++ = Limits->RangeMax;
+ *MessageParams = Limits->RangeMin;
+
+ Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE;
+ Cmd.MessageId = SCMI_MESSAGE_ID_PERFORMANCE_LIMITS_SET;
+
+ PayloadLength = sizeof (DomainId) + sizeof (SCMI_PERFORMANCE_LIMITS);
+
+ Status = ScmiCommandExecute (
+ &Cmd,
+ &PayloadLength,
+ NULL
+ );
+
+ return Status;
+}
+
+/** Get performance limits of a domain.
+
+ @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance.
+ @param[in] DomainId Identifier for the performance domain.
+
+ @param[out] Limit Performance Limits of the domain.
+
+ @retval EFI_SUCCESS Performance limits are returned.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+EFI_STATUS
+PerformanceLimitsGet (
+ SCMI_PERFORMANCE_PROTOCOL *This,
+ UINT32 DomainId,
+ SCMI_PERFORMANCE_LIMITS *Limits
+ )
+{
+ EFI_STATUS Status;
+ UINT32 PayloadLength;
+ SCMI_COMMAND Cmd;
+ UINT32 *MessageParams;
+
+ SCMI_PERFORMANCE_LIMITS *ReturnValues;
+
+ Status = ScmiCommandGetPayload (&MessageParams);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ *MessageParams = DomainId;
+
+ Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE;
+ Cmd.MessageId = SCMI_MESSAGE_ID_PERFORMANCE_LIMITS_GET;
+
+ PayloadLength = sizeof (DomainId);
+
+ Status = ScmiCommandExecute (
+ &Cmd,
+ &PayloadLength,
+ (UINT32**)&ReturnValues
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Limits->RangeMax = ReturnValues->RangeMax;
+ Limits->RangeMin = ReturnValues->RangeMin;
+
+ return EFI_SUCCESS;
+}
+
+/** Set performance level of a domain.
+
+ @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance.
+ @param[in] DomainId Identifier for the performance domain.
+ @param[in] Level Performance level of the domain.
+
+ @retval EFI_SUCCESS Performance level set successfully.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+EFI_STATUS
+PerformanceLevelSet (
+ IN SCMI_PERFORMANCE_PROTOCOL *This,
+ IN UINT32 DomainId,
+ IN UINT32 Level
+ )
+{
+ EFI_STATUS Status;
+ UINT32 PayloadLength;
+ SCMI_COMMAND Cmd;
+ UINT32 *MessageParams;
+
+ Status = ScmiCommandGetPayload (&MessageParams);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ *MessageParams++ = DomainId;
+ *MessageParams = Level;
+
+ Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE;
+ Cmd.MessageId = SCMI_MESSAGE_ID_PERFORMANCE_LEVEL_SET;
+
+ PayloadLength = sizeof (DomainId) + sizeof (Level);
+
+ Status = ScmiCommandExecute (
+ &Cmd,
+ &PayloadLength,
+ NULL
+ );
+
+ return Status;
+}
+
+/** Get performance level of a domain.
+
+ @param[in] This A Pointer to SCMI_PERFORMANCE_PROTOCOL Instance.
+ @param[in] DomainId Identifier for the performance domain.
+
+ @param[out] Level Performance level of the domain.
+
+ @retval EFI_SUCCESS Performance level got successfully.
+ @retval EFI_DEVICE_ERROR SCP returns an SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+EFI_STATUS
+PerformanceLevelGet (
+ IN SCMI_PERFORMANCE_PROTOCOL *This,
+ IN UINT32 DomainId,
+ OUT UINT32 *Level
+ )
+{
+ EFI_STATUS Status;
+ UINT32 PayloadLength;
+ SCMI_COMMAND Cmd;
+ UINT32 *ReturnValues;
+ UINT32 *MessageParams;
+
+ Status = ScmiCommandGetPayload (&MessageParams);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ *MessageParams = DomainId;
+
+ Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE;
+ Cmd.MessageId = SCMI_MESSAGE_ID_PERFORMANCE_LEVEL_GET;
+
+ PayloadLength = sizeof (DomainId);
+
+ Status = ScmiCommandExecute (
+ &Cmd,
+ &PayloadLength,
+ &ReturnValues
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ *Level = *ReturnValues;
+
+ return EFI_SUCCESS;
+}
+
+// Instance of the SCMI performance management protocol.
+STATIC CONST SCMI_PERFORMANCE_PROTOCOL PerformanceProtocol = {
+ PerformanceGetVersion,
+ PerformanceGetAttributes,
+ PerformanceDomainAttributes,
+ PerformanceDescribeLevels,
+ PerformanceLimitsSet,
+ PerformanceLimitsGet,
+ PerformanceLevelSet,
+ PerformanceLevelGet
+};
+
+/** Initialize performance management protocol and install on a given Handle.
+
+ @param[in] Handle Handle to install performance management
+ protocol.
+
+ @retval EFI_SUCCESS Performance protocol installed successfully.
+**/
+EFI_STATUS
+ScmiPerformanceProtocolInit (
+ IN EFI_HANDLE* Handle
+ )
+{
+ return gBS->InstallMultipleProtocolInterfaces (
+ Handle,
+ &gArmScmiPerformanceProtocolGuid,
+ &PerformanceProtocol,
+ NULL
+ );
+}
diff --git a/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ScmiPrivate.h b/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ScmiPrivate.h new file mode 100644 index 000000000..7763c848a --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/ArmScmiDxe/ScmiPrivate.h @@ -0,0 +1,168 @@ +/** @file
+
+ Copyright (c) 2017-2018, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ System Control and Management Interface V1.0
+ http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
+ DEN0056A_System_Control_and_Management_Interface.pdf
+**/
+#ifndef SCMI_PRIVATE_H_
+#define SCMI_PRIVATE_H_
+
+// SCMI protocol IDs.
+typedef enum {
+ SCMI_PROTOCOL_ID_BASE = 0x10,
+ SCMI_PROTOCOL_ID_POWER_DOMAIN = 0x11,
+ SCMI_PROTOCOL_ID_SYSTEM_POWER = 0x12,
+ SCMI_PROTOCOL_ID_PERFORMANCE = 0x13,
+ SCMI_PROTOCOL_ID_CLOCK = 0x14,
+ SCMI_PROTOCOL_ID_SENSOR = 0x15
+} SCMI_PROTOCOL_ID;
+
+// SCMI message types.
+typedef enum {
+ SCMI_MESSAGE_TYPE_COMMAND = 0,
+ SCMI_MESSAGE_TYPE_DELAYED_RESPONSE = 2, // Skipping 1 is deliberate.
+ SCMI_MESSAGE_TYPE_NOTIFICATION = 3
+} SCMI_MESSAGE_TYPE;
+
+// SCMI response error codes.
+typedef enum {
+ SCMI_SUCCESS = 0,
+ SCMI_NOT_SUPPORTED = -1,
+ SCMI_INVALID_PARAMETERS = -2,
+ SCMI_DENIED = -3,
+ SCMI_NOT_FOUND = -4,
+ SCMI_OUT_OF_RANGE = -5,
+ SCMI_BUSY = -6,
+ SCMI_COMMS_ERROR = -7,
+ SCMI_GENERIC_ERROR = -8,
+ SCMI_HARDWARE_ERROR = -9,
+ SCMI_PROTOCOL_ERROR = -10
+} SCMI_STATUS;
+
+// SCMI message IDs common to all protocols.
+typedef enum {
+ SCMI_MESSAGE_ID_PROTOCOL_VERSION = 0x0,
+ SCMI_MESSAGE_ID_PROTOCOL_ATTRIBUTES = 0x1,
+ SCMI_MESSAGE_ID_PROTOCOL_MESSAGE_ATTRIBUTES = 0x2
+} SCMI_MESSAGE_ID;
+
+// Not defined in SCMI specification but will help to identify a message.
+typedef struct {
+ SCMI_PROTOCOL_ID ProtocolId;
+ UINT32 MessageId;
+} SCMI_COMMAND;
+
+#pragma pack(1)
+
+// Response to a SCMI command.
+typedef struct {
+ INT32 Status;
+ UINT32 ReturnValues[];
+} SCMI_MESSAGE_RESPONSE;
+
+// Message header. MsgId[7:0], MsgType[9:8], ProtocolId[17:10]
+#define MESSAGE_TYPE_SHIFT 8
+#define PROTOCOL_ID_SHIFT 10
+#define SCMI_MESSAGE_HEADER(MsgId, MsgType, ProtocolId) ( \
+ MsgType << MESSAGE_TYPE_SHIFT | \
+ ProtocolId << PROTOCOL_ID_SHIFT | \
+ MsgId \
+ )
+// SCMI message header.
+typedef struct {
+ UINT32 MessageHeader;
+} SCMI_MESSAGE_HEADER;
+
+#pragma pack()
+
+/** Return a pointer to the message payload.
+
+ @param[out] Payload Holds pointer to the message payload.
+
+ @retval EFI_SUCCESS Payload holds a valid message payload pointer.
+ @retval EFI_TIMEOUT Time out error if MTL channel is busy.
+ @retval EFI_UNSUPPORTED If MTL channel is unsupported.
+**/
+EFI_STATUS
+ScmiCommandGetPayload (
+ OUT UINT32** Payload
+ );
+
+/** Execute a SCMI command and receive a response.
+
+ This function uses a MTL channel to transfer message to SCP
+ and waits for a response.
+
+ @param[in] Command Pointer to the SCMI command (Protocol ID
+ and Message ID)
+
+ @param[in,out] PayloadLength SCMI command message length.
+
+ @param[out] OPTIONAL ReturnValues Pointer to SCMI response.
+
+ @retval OUT EFI_SUCCESS Command sent and message received successfully.
+ @retval OUT EFI_UNSUPPORTED Channel not supported.
+ @retval OUT EFI_TIMEOUT Timeout on the channel.
+ @retval OUT EFI_DEVICE_ERROR Channel not ready.
+ @retval OUT EFI_DEVICE_ERROR Message Header corrupted.
+ @retval OUT EFI_DEVICE_ERROR SCMI error.
+**/
+EFI_STATUS
+ScmiCommandExecute (
+ IN SCMI_COMMAND *Command,
+ IN OUT UINT32 *PayloadLength,
+ OUT UINT32 **ReturnValues OPTIONAL
+ );
+
+/** Return protocol version from SCP for a given protocol ID.
+
+ @param[in] Protocol ID Protocol ID.
+ @param[out] Version Pointer to version of the protocol.
+
+ @retval EFI_SUCCESS Version holds a valid version received
+ from the SCP.
+ @retval EFI_DEVICE_ERROR SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+EFI_STATUS
+ScmiGetProtocolVersion (
+ IN SCMI_PROTOCOL_ID ProtocolId,
+ OUT UINT32 *Version
+ );
+
+/** Return protocol attributes from SCP for a given protocol ID.
+
+ @param[in] Protocol ID Protocol ID.
+ @param[out] ReturnValues Pointer to attributes of the protocol.
+
+ @retval EFI_SUCCESS ReturnValues points to protocol attributes.
+ @retval EFI_DEVICE_ERROR SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+EFI_STATUS
+ScmiGetProtocolAttributes (
+ IN SCMI_PROTOCOL_ID ProtocolId,
+ OUT UINT32 **ReturnValues
+ );
+
+/** Return protocol message attributes from SCP for a given protocol ID.
+
+ @param[in] Protocol ID Protocol ID.
+
+ @param[out] Attributes Pointer to attributes of the protocol.
+
+ @retval EFI_SUCCESS ReturnValues points to protocol message attributes.
+ @retval EFI_DEVICE_ERROR SCMI error.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+EFI_STATUS
+ScmiGetProtocolMessageAttributes (
+ IN SCMI_PROTOCOL_ID ProtocolId,
+ OUT UINT32 **ReturnValues
+ );
+
+#endif /* SCMI_PRIVATE_H_ */
diff --git a/roms/edk2/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c b/roms/edk2/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c new file mode 100644 index 000000000..fca2d4f76 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c @@ -0,0 +1,402 @@ +/*++
+
+Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
+Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
+Portions copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR>
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+
+--*/
+
+#include <Library/MemoryAllocationLib.h>
+#include "CpuDxe.h"
+
+#define INVALID_ENTRY ((UINT32)~0)
+
+#define MIN_T0SZ 16
+#define BITS_PER_LEVEL 9
+
+STATIC
+VOID
+GetRootTranslationTableInfo (
+ IN UINTN T0SZ,
+ OUT UINTN *RootTableLevel,
+ OUT UINTN *RootTableEntryCount
+ )
+{
+ *RootTableLevel = (T0SZ - MIN_T0SZ) / BITS_PER_LEVEL;
+ *RootTableEntryCount = TT_ENTRY_COUNT >> (T0SZ - MIN_T0SZ) % BITS_PER_LEVEL;
+}
+
+STATIC
+UINT64
+PageAttributeToGcdAttribute (
+ IN UINT64 PageAttributes
+ )
+{
+ UINT64 GcdAttributes;
+
+ switch (PageAttributes & TT_ATTR_INDX_MASK) {
+ case TT_ATTR_INDX_DEVICE_MEMORY:
+ GcdAttributes = EFI_MEMORY_UC;
+ break;
+ case TT_ATTR_INDX_MEMORY_NON_CACHEABLE:
+ GcdAttributes = EFI_MEMORY_WC;
+ break;
+ case TT_ATTR_INDX_MEMORY_WRITE_THROUGH:
+ GcdAttributes = EFI_MEMORY_WT;
+ break;
+ case TT_ATTR_INDX_MEMORY_WRITE_BACK:
+ GcdAttributes = EFI_MEMORY_WB;
+ break;
+ default:
+ DEBUG ((DEBUG_ERROR,
+ "PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n",
+ PageAttributes));
+ ASSERT (0);
+ // The Global Coherency Domain (GCD) value is defined as a bit set.
+ // Returning 0 means no attribute has been set.
+ GcdAttributes = 0;
+ }
+
+ // Determine protection attributes
+ if (((PageAttributes & TT_AP_MASK) == TT_AP_NO_RO) ||
+ ((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO)) {
+ // Read only cases map to write-protect
+ GcdAttributes |= EFI_MEMORY_RO;
+ }
+
+ // Process eXecute Never attribute
+ if ((PageAttributes & (TT_PXN_MASK | TT_UXN_MASK)) != 0) {
+ GcdAttributes |= EFI_MEMORY_XP;
+ }
+
+ return GcdAttributes;
+}
+
+STATIC
+UINT64
+GetFirstPageAttribute (
+ IN UINT64 *FirstLevelTableAddress,
+ IN UINTN TableLevel
+ )
+{
+ UINT64 FirstEntry;
+
+ // Get the first entry of the table
+ FirstEntry = *FirstLevelTableAddress;
+
+ if ((TableLevel != 3) && (FirstEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) {
+ // Only valid for Levels 0, 1 and 2
+
+ // Get the attribute of the subsequent table
+ return GetFirstPageAttribute ((UINT64*)(FirstEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE), TableLevel + 1);
+ } else if (((FirstEntry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY) ||
+ ((TableLevel == 3) && ((FirstEntry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY_LEVEL3)))
+ {
+ return FirstEntry & TT_ATTR_INDX_MASK;
+ } else {
+ return INVALID_ENTRY;
+ }
+}
+
+STATIC
+UINT64
+GetNextEntryAttribute (
+ IN UINT64 *TableAddress,
+ IN UINTN EntryCount,
+ IN UINTN TableLevel,
+ IN UINT64 BaseAddress,
+ IN OUT UINT32 *PrevEntryAttribute,
+ IN OUT UINT64 *StartGcdRegion
+ )
+{
+ UINTN Index;
+ UINT64 Entry;
+ UINT32 EntryAttribute;
+ UINT32 EntryType;
+ EFI_STATUS Status;
+ UINTN NumberOfDescriptors;
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
+
+ // Get the memory space map from GCD
+ MemorySpaceMap = NULL;
+ Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
+ ASSERT_EFI_ERROR (Status);
+
+ // We cannot get more than 3-level page table
+ ASSERT (TableLevel <= 3);
+
+ // While the top level table might not contain TT_ENTRY_COUNT entries;
+ // the subsequent ones should be filled up
+ for (Index = 0; Index < EntryCount; Index++) {
+ Entry = TableAddress[Index];
+ EntryType = Entry & TT_TYPE_MASK;
+ EntryAttribute = Entry & TT_ATTR_INDX_MASK;
+
+ // If Entry is a Table Descriptor type entry then go through the sub-level table
+ if ((EntryType == TT_TYPE_BLOCK_ENTRY) ||
+ ((TableLevel == 3) && (EntryType == TT_TYPE_BLOCK_ENTRY_LEVEL3))) {
+ if ((*PrevEntryAttribute == INVALID_ENTRY) || (EntryAttribute != *PrevEntryAttribute)) {
+ if (*PrevEntryAttribute != INVALID_ENTRY) {
+ // Update GCD with the last region
+ SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors,
+ *StartGcdRegion,
+ (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))) - *StartGcdRegion,
+ PageAttributeToGcdAttribute (*PrevEntryAttribute));
+ }
+
+ // Start of the new region
+ *StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel));
+ *PrevEntryAttribute = EntryAttribute;
+ } else {
+ continue;
+ }
+ } else if (EntryType == TT_TYPE_TABLE_ENTRY) {
+ // Table Entry type is only valid for Level 0, 1, 2
+ ASSERT (TableLevel < 3);
+
+ // Increase the level number and scan the sub-level table
+ GetNextEntryAttribute ((UINT64*)(Entry & TT_ADDRESS_MASK_DESCRIPTION_TABLE),
+ TT_ENTRY_COUNT, TableLevel + 1,
+ (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))),
+ PrevEntryAttribute, StartGcdRegion);
+ } else {
+ if (*PrevEntryAttribute != INVALID_ENTRY) {
+ // Update GCD with the last region
+ SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors,
+ *StartGcdRegion,
+ (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))) - *StartGcdRegion,
+ PageAttributeToGcdAttribute (*PrevEntryAttribute));
+
+ // Start of the new region
+ *StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel));
+ *PrevEntryAttribute = INVALID_ENTRY;
+ }
+ }
+ }
+
+ FreePool (MemorySpaceMap);
+
+ return BaseAddress + (EntryCount * TT_ADDRESS_AT_LEVEL(TableLevel));
+}
+
+EFI_STATUS
+SyncCacheConfig (
+ IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
+ )
+{
+ EFI_STATUS Status;
+ UINT32 PageAttribute = 0;
+ UINT64 *FirstLevelTableAddress;
+ UINTN TableLevel;
+ UINTN TableCount;
+ UINTN NumberOfDescriptors;
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
+ UINTN Tcr;
+ UINTN T0SZ;
+ UINT64 BaseAddressGcdRegion;
+ UINT64 EndAddressGcdRegion;
+
+ // This code assumes MMU is enabled and filed with section translations
+ ASSERT (ArmMmuEnabled ());
+
+ //
+ // Get the memory space map from GCD
+ //
+ MemorySpaceMap = NULL;
+ Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
+ ASSERT_EFI_ERROR (Status);
+
+ // The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs
+ // to know what the initial memory space attributes are. The CPU Arch. Protocol does not provide a
+ // GetMemoryAttributes function for GCD to get this so we must resort to calling GCD (as if we were
+ // a client) to update its copy of the attributes. This is bad architecture and should be replaced
+ // with a way for GCD to query the CPU Arch. driver of the existing memory space attributes instead.
+
+ // Obtain page table base
+ FirstLevelTableAddress = (UINT64*)(ArmGetTTBR0BaseAddress ());
+
+ // Get Translation Control Register value
+ Tcr = ArmGetTCR ();
+ // Get Address Region Size
+ T0SZ = Tcr & TCR_T0SZ_MASK;
+
+ // Get the level of the first table for the indicated Address Region Size
+ GetRootTranslationTableInfo (T0SZ, &TableLevel, &TableCount);
+
+ // First Attribute of the Page Tables
+ PageAttribute = GetFirstPageAttribute (FirstLevelTableAddress, TableLevel);
+
+ // We scan from the start of the memory map (ie: at the address 0x0)
+ BaseAddressGcdRegion = 0x0;
+ EndAddressGcdRegion = GetNextEntryAttribute (FirstLevelTableAddress,
+ TableCount, TableLevel,
+ BaseAddressGcdRegion,
+ &PageAttribute, &BaseAddressGcdRegion);
+
+ // Update GCD with the last region if valid
+ if (PageAttribute != INVALID_ENTRY) {
+ SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors,
+ BaseAddressGcdRegion,
+ EndAddressGcdRegion - BaseAddressGcdRegion,
+ PageAttributeToGcdAttribute (PageAttribute));
+ }
+
+ FreePool (MemorySpaceMap);
+
+ return EFI_SUCCESS;
+}
+
+UINT64
+EfiAttributeToArmAttribute (
+ IN UINT64 EfiAttributes
+ )
+{
+ UINT64 ArmAttributes;
+
+ switch (EfiAttributes & EFI_MEMORY_CACHETYPE_MASK) {
+ case EFI_MEMORY_UC:
+ if (ArmReadCurrentEL () == AARCH64_EL2) {
+ ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK;
+ } else {
+ ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK;
+ }
+ break;
+ case EFI_MEMORY_WC:
+ ArmAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
+ break;
+ case EFI_MEMORY_WT:
+ ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
+ break;
+ case EFI_MEMORY_WB:
+ ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
+ break;
+ default:
+ ArmAttributes = TT_ATTR_INDX_MASK;
+ }
+
+ // Set the access flag to match the block attributes
+ ArmAttributes |= TT_AF;
+
+ // Determine protection attributes
+ if (EfiAttributes & EFI_MEMORY_RO) {
+ ArmAttributes |= TT_AP_RO_RO;
+ }
+
+ // Process eXecute Never attribute
+ if (EfiAttributes & EFI_MEMORY_XP) {
+ ArmAttributes |= TT_PXN_MASK;
+ }
+
+ return ArmAttributes;
+}
+
+// This function will recursively go down the page table to find the first block address linked to 'BaseAddress'.
+// And then the function will identify the size of the region that has the same page table attribute.
+EFI_STATUS
+GetMemoryRegionRec (
+ IN UINT64 *TranslationTable,
+ IN UINTN TableLevel,
+ IN UINT64 *LastBlockEntry,
+ IN OUT UINTN *BaseAddress,
+ OUT UINTN *RegionLength,
+ OUT UINTN *RegionAttributes
+ )
+{
+ EFI_STATUS Status;
+ UINT64 *NextTranslationTable;
+ UINT64 *BlockEntry;
+ UINT64 BlockEntryType;
+ UINT64 EntryType;
+
+ if (TableLevel != 3) {
+ BlockEntryType = TT_TYPE_BLOCK_ENTRY;
+ } else {
+ BlockEntryType = TT_TYPE_BLOCK_ENTRY_LEVEL3;
+ }
+
+ // Find the block entry linked to the Base Address
+ BlockEntry = (UINT64*)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, TableLevel, *BaseAddress);
+ EntryType = *BlockEntry & TT_TYPE_MASK;
+
+ if ((TableLevel < 3) && (EntryType == TT_TYPE_TABLE_ENTRY)) {
+ NextTranslationTable = (UINT64*)(*BlockEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE);
+
+ // The entry is a page table, so we go to the next level
+ Status = GetMemoryRegionRec (
+ NextTranslationTable, // Address of the next level page table
+ TableLevel + 1, // Next Page Table level
+ (UINTN*)TT_LAST_BLOCK_ADDRESS(NextTranslationTable, TT_ENTRY_COUNT),
+ BaseAddress, RegionLength, RegionAttributes);
+
+ // In case of 'Success', it means the end of the block region has been found into the upper
+ // level translation table
+ if (!EFI_ERROR(Status)) {
+ return EFI_SUCCESS;
+ }
+
+ // Now we processed the table move to the next entry
+ BlockEntry++;
+ } else if (EntryType == BlockEntryType) {
+ // We have found the BlockEntry attached to the address. We save its start address (the start
+ // address might be before the 'BaseAddress') and attributes
+ *BaseAddress = *BaseAddress & ~(TT_ADDRESS_AT_LEVEL(TableLevel) - 1);
+ *RegionLength = 0;
+ *RegionAttributes = *BlockEntry & TT_ATTRIBUTES_MASK;
+ } else {
+ // We have an 'Invalid' entry
+ return EFI_UNSUPPORTED;
+ }
+
+ while (BlockEntry <= LastBlockEntry) {
+ if ((*BlockEntry & TT_ATTRIBUTES_MASK) == *RegionAttributes) {
+ *RegionLength = *RegionLength + TT_BLOCK_ENTRY_SIZE_AT_LEVEL(TableLevel);
+ } else {
+ // In case we have found the end of the region we return success
+ return EFI_SUCCESS;
+ }
+ BlockEntry++;
+ }
+
+ // If we have reached the end of the TranslationTable and we have not found the end of the region then
+ // we return EFI_NOT_FOUND.
+ // The caller will continue to look for the memory region at its level
+ return EFI_NOT_FOUND;
+}
+
+EFI_STATUS
+GetMemoryRegion (
+ IN OUT UINTN *BaseAddress,
+ OUT UINTN *RegionLength,
+ OUT UINTN *RegionAttributes
+ )
+{
+ EFI_STATUS Status;
+ UINT64 *TranslationTable;
+ UINTN TableLevel;
+ UINTN EntryCount;
+ UINTN T0SZ;
+
+ ASSERT ((BaseAddress != NULL) && (RegionLength != NULL) && (RegionAttributes != NULL));
+
+ TranslationTable = ArmGetTTBR0BaseAddress ();
+
+ T0SZ = ArmGetTCR () & TCR_T0SZ_MASK;
+ // Get the Table info from T0SZ
+ GetRootTranslationTableInfo (T0SZ, &TableLevel, &EntryCount);
+
+ Status = GetMemoryRegionRec (TranslationTable, TableLevel,
+ (UINTN*)TT_LAST_BLOCK_ADDRESS(TranslationTable, EntryCount),
+ BaseAddress, RegionLength, RegionAttributes);
+
+ // If the region continues up to the end of the root table then GetMemoryRegionRec()
+ // will return EFI_NOT_FOUND
+ if (Status == EFI_NOT_FOUND) {
+ return EFI_SUCCESS;
+ } else {
+ return Status;
+ }
+}
diff --git a/roms/edk2/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/roms/edk2/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c new file mode 100644 index 000000000..6fb5112a1 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c @@ -0,0 +1,511 @@ +/*++
+
+Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
+Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
+Portions copyright (c) 2013, ARM Ltd. All rights reserved.<BR>
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+
+--*/
+
+#include <Library/MemoryAllocationLib.h>
+#include "CpuDxe.h"
+
+EFI_STATUS
+SectionToGcdAttributes (
+ IN UINT32 SectionAttributes,
+ OUT UINT64 *GcdAttributes
+ )
+{
+ *GcdAttributes = 0;
+
+ // determine cacheability attributes
+ switch(SectionAttributes & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) {
+ case TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED:
+ *GcdAttributes |= EFI_MEMORY_UC;
+ break;
+ case TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE:
+ *GcdAttributes |= EFI_MEMORY_UC;
+ break;
+ case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC:
+ *GcdAttributes |= EFI_MEMORY_WT;
+ break;
+ case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC:
+ *GcdAttributes |= EFI_MEMORY_WB;
+ break;
+ case TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE:
+ *GcdAttributes |= EFI_MEMORY_WC;
+ break;
+ case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC:
+ *GcdAttributes |= EFI_MEMORY_WB;
+ break;
+ case TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE:
+ *GcdAttributes |= EFI_MEMORY_UC;
+ break;
+ default:
+ return EFI_UNSUPPORTED;
+ }
+
+ // determine protection attributes
+ switch(SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) {
+ case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write
+ //*GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP;
+ break;
+
+ case TT_DESCRIPTOR_SECTION_AP_RW_NO:
+ case TT_DESCRIPTOR_SECTION_AP_RW_RW:
+ // normal read/write access, do not add additional attributes
+ break;
+
+ // read only cases map to write-protect
+ case TT_DESCRIPTOR_SECTION_AP_RO_NO:
+ case TT_DESCRIPTOR_SECTION_AP_RO_RO:
+ *GcdAttributes |= EFI_MEMORY_RO;
+ break;
+
+ default:
+ return EFI_UNSUPPORTED;
+ }
+
+ // now process eXectue Never attribute
+ if ((SectionAttributes & TT_DESCRIPTOR_SECTION_XN_MASK) != 0 ) {
+ *GcdAttributes |= EFI_MEMORY_XP;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PageToGcdAttributes (
+ IN UINT32 PageAttributes,
+ OUT UINT64 *GcdAttributes
+ )
+{
+ *GcdAttributes = 0;
+
+ // determine cacheability attributes
+ switch(PageAttributes & TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK) {
+ case TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED:
+ *GcdAttributes |= EFI_MEMORY_UC;
+ break;
+ case TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE:
+ *GcdAttributes |= EFI_MEMORY_UC;
+ break;
+ case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC:
+ *GcdAttributes |= EFI_MEMORY_WT;
+ break;
+ case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC:
+ *GcdAttributes |= EFI_MEMORY_WB;
+ break;
+ case TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE:
+ *GcdAttributes |= EFI_MEMORY_WC;
+ break;
+ case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC:
+ *GcdAttributes |= EFI_MEMORY_WB;
+ break;
+ case TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE:
+ *GcdAttributes |= EFI_MEMORY_UC;
+ break;
+ default:
+ return EFI_UNSUPPORTED;
+ }
+
+ // determine protection attributes
+ switch(PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) {
+ case TT_DESCRIPTOR_PAGE_AP_NO_NO: // no read, no write
+ //*GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP;
+ break;
+
+ case TT_DESCRIPTOR_PAGE_AP_RW_NO:
+ case TT_DESCRIPTOR_PAGE_AP_RW_RW:
+ // normal read/write access, do not add additional attributes
+ break;
+
+ // read only cases map to write-protect
+ case TT_DESCRIPTOR_PAGE_AP_RO_NO:
+ case TT_DESCRIPTOR_PAGE_AP_RO_RO:
+ *GcdAttributes |= EFI_MEMORY_RO;
+ break;
+
+ default:
+ return EFI_UNSUPPORTED;
+ }
+
+ // now process eXectue Never attribute
+ if ((PageAttributes & TT_DESCRIPTOR_PAGE_XN_MASK) != 0 ) {
+ *GcdAttributes |= EFI_MEMORY_XP;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+SyncCacheConfigPage (
+ IN UINT32 SectionIndex,
+ IN UINT32 FirstLevelDescriptor,
+ IN UINTN NumberOfDescriptors,
+ IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
+ IN OUT EFI_PHYSICAL_ADDRESS *NextRegionBase,
+ IN OUT UINT64 *NextRegionLength,
+ IN OUT UINT32 *NextSectionAttributes
+ )
+{
+ EFI_STATUS Status;
+ UINT32 i;
+ volatile ARM_PAGE_TABLE_ENTRY *SecondLevelTable;
+ UINT32 NextPageAttributes = 0;
+ UINT32 PageAttributes = 0;
+ UINT32 BaseAddress;
+ UINT64 GcdAttributes;
+
+ // Get the Base Address from FirstLevelDescriptor;
+ BaseAddress = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(SectionIndex << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
+
+ // Convert SectionAttributes into PageAttributes
+ NextPageAttributes =
+ TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(*NextSectionAttributes,0) |
+ TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(*NextSectionAttributes);
+
+ // obtain page table base
+ SecondLevelTable = (ARM_PAGE_TABLE_ENTRY *)(FirstLevelDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);
+
+ for (i=0; i < TRANSLATION_TABLE_PAGE_COUNT; i++) {
+ if ((SecondLevelTable[i] & TT_DESCRIPTOR_PAGE_TYPE_MASK) == TT_DESCRIPTOR_PAGE_TYPE_PAGE) {
+ // extract attributes (cacheability and permissions)
+ PageAttributes = SecondLevelTable[i] & (TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK | TT_DESCRIPTOR_PAGE_AP_MASK);
+
+ if (NextPageAttributes == 0) {
+ // start on a new region
+ *NextRegionLength = 0;
+ *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);
+ NextPageAttributes = PageAttributes;
+ } else if (PageAttributes != NextPageAttributes) {
+ // Convert Section Attributes into GCD Attributes
+ Status = PageToGcdAttributes (NextPageAttributes, &GcdAttributes);
+ ASSERT_EFI_ERROR (Status);
+
+ // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
+ SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes);
+
+ // start on a new region
+ *NextRegionLength = 0;
+ *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);
+ NextPageAttributes = PageAttributes;
+ }
+ } else if (NextPageAttributes != 0) {
+ // Convert Page Attributes into GCD Attributes
+ Status = PageToGcdAttributes (NextPageAttributes, &GcdAttributes);
+ ASSERT_EFI_ERROR (Status);
+
+ // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
+ SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes);
+
+ *NextRegionLength = 0;
+ *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);
+ NextPageAttributes = 0;
+ }
+ *NextRegionLength += TT_DESCRIPTOR_PAGE_SIZE;
+ }
+
+ // Convert back PageAttributes into SectionAttributes
+ *NextSectionAttributes =
+ TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(NextPageAttributes,0) |
+ TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(NextPageAttributes);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+SyncCacheConfig (
+ IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
+ )
+{
+ EFI_STATUS Status;
+ UINT32 i;
+ EFI_PHYSICAL_ADDRESS NextRegionBase;
+ UINT64 NextRegionLength;
+ UINT32 NextSectionAttributes = 0;
+ UINT32 SectionAttributes = 0;
+ UINT64 GcdAttributes;
+ volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
+ UINTN NumberOfDescriptors;
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
+
+
+ DEBUG ((DEBUG_PAGE, "SyncCacheConfig()\n"));
+
+ // This code assumes MMU is enabled and filed with section translations
+ ASSERT (ArmMmuEnabled ());
+
+ //
+ // Get the memory space map from GCD
+ //
+ MemorySpaceMap = NULL;
+ Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
+ ASSERT_EFI_ERROR (Status);
+
+
+ // The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs
+ // to know what the initial memory space attributes are. The CPU Arch. Protocol does not provide a
+ // GetMemoryAttributes function for GCD to get this so we must resort to calling GCD (as if we were
+ // a client) to update its copy of the attributes. This is bad architecture and should be replaced
+ // with a way for GCD to query the CPU Arch. driver of the existing memory space attributes instead.
+
+ // obtain page table base
+ FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)(ArmGetTTBR0BaseAddress ());
+
+ // Get the first region
+ NextSectionAttributes = FirstLevelTable[0] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);
+
+ // iterate through each 1MB descriptor
+ NextRegionBase = NextRegionLength = 0;
+ for (i=0; i < TRANSLATION_TABLE_SECTION_COUNT; i++) {
+ if ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {
+ // extract attributes (cacheability and permissions)
+ SectionAttributes = FirstLevelTable[i] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);
+
+ if (NextSectionAttributes == 0) {
+ // start on a new region
+ NextRegionLength = 0;
+ NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
+ NextSectionAttributes = SectionAttributes;
+ } else if (SectionAttributes != NextSectionAttributes) {
+ // Convert Section Attributes into GCD Attributes
+ Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes);
+ ASSERT_EFI_ERROR (Status);
+
+ // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
+ SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);
+
+ // start on a new region
+ NextRegionLength = 0;
+ NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
+ NextSectionAttributes = SectionAttributes;
+ }
+ NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE;
+ } else if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(FirstLevelTable[i])) {
+ // In this case any bits set in the 'NextSectionAttributes' are garbage and were set from
+ // bits that are actually part of the pagetable address. We clear it out to zero so that
+ // the SyncCacheConfigPage will use the page attributes instead of trying to convert the
+ // section attributes into page attributes
+ NextSectionAttributes = 0;
+ Status = SyncCacheConfigPage (
+ i,FirstLevelTable[i],
+ NumberOfDescriptors, MemorySpaceMap,
+ &NextRegionBase,&NextRegionLength,&NextSectionAttributes);
+ ASSERT_EFI_ERROR (Status);
+ } else {
+ // We do not support yet 16MB sections
+ ASSERT ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) != TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION);
+
+ // start on a new region
+ if (NextSectionAttributes != 0) {
+ // Convert Section Attributes into GCD Attributes
+ Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes);
+ ASSERT_EFI_ERROR (Status);
+
+ // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
+ SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);
+
+ NextRegionLength = 0;
+ NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
+ NextSectionAttributes = 0;
+ }
+ NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE;
+ }
+ } // section entry loop
+
+ if (NextSectionAttributes != 0) {
+ // Convert Section Attributes into GCD Attributes
+ Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes);
+ ASSERT_EFI_ERROR (Status);
+
+ // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
+ SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);
+ }
+
+ FreePool (MemorySpaceMap);
+
+ return EFI_SUCCESS;
+}
+
+UINT64
+EfiAttributeToArmAttribute (
+ IN UINT64 EfiAttributes
+ )
+{
+ UINT64 ArmAttributes;
+
+ switch (EfiAttributes & EFI_MEMORY_CACHETYPE_MASK) {
+ case EFI_MEMORY_UC:
+ // Map to strongly ordered
+ ArmAttributes = TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
+ break;
+
+ case EFI_MEMORY_WC:
+ // Map to normal non-cachable
+ ArmAttributes = TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
+ break;
+
+ case EFI_MEMORY_WT:
+ // Write through with no-allocate
+ ArmAttributes = TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0
+ break;
+
+ case EFI_MEMORY_WB:
+ // Write back (with allocate)
+ ArmAttributes = TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1
+ break;
+
+ case EFI_MEMORY_UCE:
+ default:
+ ArmAttributes = TT_DESCRIPTOR_SECTION_TYPE_FAULT;
+ break;
+ }
+
+ // Determine protection attributes
+ if (EfiAttributes & EFI_MEMORY_RO) {
+ ArmAttributes |= TT_DESCRIPTOR_SECTION_AP_RO_RO;
+ } else {
+ ArmAttributes |= TT_DESCRIPTOR_SECTION_AP_RW_RW;
+ }
+
+ // Determine eXecute Never attribute
+ if (EfiAttributes & EFI_MEMORY_XP) {
+ ArmAttributes |= TT_DESCRIPTOR_SECTION_XN_MASK;
+ }
+
+ return ArmAttributes;
+}
+
+EFI_STATUS
+GetMemoryRegionPage (
+ IN UINT32 *PageTable,
+ IN OUT UINTN *BaseAddress,
+ OUT UINTN *RegionLength,
+ OUT UINTN *RegionAttributes
+ )
+{
+ UINT32 PageAttributes;
+ UINT32 TableIndex;
+ UINT32 PageDescriptor;
+
+ // Convert the section attributes into page attributes
+ PageAttributes = ConvertSectionAttributesToPageAttributes (*RegionAttributes, 0);
+
+ // Calculate index into first level translation table for start of modification
+ TableIndex = ((*BaseAddress) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;
+ ASSERT (TableIndex < TRANSLATION_TABLE_PAGE_COUNT);
+
+ // Go through the page table to find the end of the section
+ for (; TableIndex < TRANSLATION_TABLE_PAGE_COUNT; TableIndex++) {
+ // Get the section at the given index
+ PageDescriptor = PageTable[TableIndex];
+
+ if ((PageDescriptor & TT_DESCRIPTOR_PAGE_TYPE_MASK) == TT_DESCRIPTOR_PAGE_TYPE_FAULT) {
+ // Case: End of the boundary of the region
+ return EFI_SUCCESS;
+ } else if ((PageDescriptor & TT_DESCRIPTOR_PAGE_TYPE_PAGE) == TT_DESCRIPTOR_PAGE_TYPE_PAGE) {
+ if ((PageDescriptor & TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK) == PageAttributes) {
+ *RegionLength = *RegionLength + TT_DESCRIPTOR_PAGE_SIZE;
+ } else {
+ // Case: End of the boundary of the region
+ return EFI_SUCCESS;
+ }
+ } else {
+ // We do not support Large Page yet. We return EFI_SUCCESS that means end of the region.
+ ASSERT(0);
+ return EFI_SUCCESS;
+ }
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+EFI_STATUS
+GetMemoryRegion (
+ IN OUT UINTN *BaseAddress,
+ OUT UINTN *RegionLength,
+ OUT UINTN *RegionAttributes
+ )
+{
+ EFI_STATUS Status;
+ UINT32 TableIndex;
+ UINT32 PageAttributes;
+ UINT32 PageTableIndex;
+ UINT32 SectionDescriptor;
+ ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
+ UINT32 *PageTable;
+
+ // Initialize the arguments
+ *RegionLength = 0;
+
+ // Obtain page table base
+ FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
+
+ // Calculate index into first level translation table for start of modification
+ TableIndex = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (*BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
+ ASSERT (TableIndex < TRANSLATION_TABLE_SECTION_COUNT);
+
+ // Get the section at the given index
+ SectionDescriptor = FirstLevelTable[TableIndex];
+ if (!SectionDescriptor) {
+ return EFI_NOT_FOUND;
+ }
+
+ // If 'BaseAddress' belongs to the section then round it to the section boundary
+ if (((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) ||
+ ((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION))
+ {
+ *BaseAddress = (*BaseAddress) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK;
+ *RegionAttributes = SectionDescriptor & TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK;
+ } else {
+ // Otherwise, we round it to the page boundary
+ *BaseAddress = (*BaseAddress) & TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK;
+
+ // Get the attribute at the page table level (Level 2)
+ PageTable = (UINT32*)(SectionDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);
+
+ // Calculate index into first level translation table for start of modification
+ PageTableIndex = ((*BaseAddress) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;
+ ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT);
+
+ PageAttributes = PageTable[PageTableIndex] & TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK;
+ *RegionAttributes = TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY (PageAttributes, 0) |
+ TT_DESCRIPTOR_CONVERT_TO_SECTION_AP (PageAttributes);
+ }
+
+ for (;TableIndex < TRANSLATION_TABLE_SECTION_COUNT; TableIndex++) {
+ // Get the section at the given index
+ SectionDescriptor = FirstLevelTable[TableIndex];
+
+ // If the entry is a level-2 page table then we scan it to find the end of the region
+ if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (SectionDescriptor)) {
+ // Extract the page table location from the descriptor
+ PageTable = (UINT32*)(SectionDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);
+
+ // Scan the page table to find the end of the region.
+ Status = GetMemoryRegionPage (PageTable, BaseAddress, RegionLength, RegionAttributes);
+
+ // If we have found the end of the region (Status == EFI_SUCCESS) then we exit the for-loop
+ if (Status == EFI_SUCCESS) {
+ break;
+ }
+ } else if (((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) ||
+ ((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION)) {
+ if ((SectionDescriptor & TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK) != *RegionAttributes) {
+ // If the attributes of the section differ from the one targeted then we exit the loop
+ break;
+ } else {
+ *RegionLength = *RegionLength + TT_DESCRIPTOR_SECTION_SIZE;
+ }
+ } else {
+ // If we are on an invalid section then it means it is the end of our section.
+ break;
+ }
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/roms/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.c b/roms/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.c new file mode 100644 index 000000000..082ef30fb --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.c @@ -0,0 +1,283 @@ +/** @file
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2011, ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "CpuDxe.h"
+
+#include <Guid/IdleLoopEvent.h>
+
+BOOLEAN mIsFlushingGCD;
+
+/**
+ This function flushes the range of addresses from Start to Start+Length
+ from the processor's data cache. If Start is not aligned to a cache line
+ boundary, then the bytes before Start to the preceding cache line boundary
+ are also flushed. If Start+Length is not aligned to a cache line boundary,
+ then the bytes past Start+Length to the end of the next cache line boundary
+ are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be
+ supported. If the data cache is fully coherent with all DMA operations, then
+ this function can just return EFI_SUCCESS. If the processor does not support
+ flushing a range of the data cache, then the entire data cache can be flushed.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+ @param Start The beginning physical address to flush from the processor's data
+ cache.
+ @param Length The number of bytes to flush from the processor's data cache. This
+ function may flush more bytes than Length specifies depending upon
+ the granularity of the flush operation that the processor supports.
+ @param FlushType Specifies the type of flush operation to perform.
+
+ @retval EFI_SUCCESS The address range from Start to Start+Length was flushed from
+ the processor's data cache.
+ @retval EFI_UNSUPPORTED The processor does not support the cache flush type specified
+ by FlushType.
+ @retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed
+ from the processor's data cache.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuFlushCpuDataCache (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS Start,
+ IN UINT64 Length,
+ IN EFI_CPU_FLUSH_TYPE FlushType
+ )
+{
+
+ switch (FlushType) {
+ case EfiCpuFlushTypeWriteBack:
+ WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
+ break;
+ case EfiCpuFlushTypeInvalidate:
+ InvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
+ break;
+ case EfiCpuFlushTypeWriteBackInvalidate:
+ WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
+ break;
+ default:
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function enables interrupt processing by the processor.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+
+ @retval EFI_SUCCESS Interrupts are enabled on the processor.
+ @retval EFI_DEVICE_ERROR Interrupts could not be enabled on the processor.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuEnableInterrupt (
+ IN EFI_CPU_ARCH_PROTOCOL *This
+ )
+{
+ ArmEnableInterrupts ();
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function disables interrupt processing by the processor.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+
+ @retval EFI_SUCCESS Interrupts are disabled on the processor.
+ @retval EFI_DEVICE_ERROR Interrupts could not be disabled on the processor.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuDisableInterrupt (
+ IN EFI_CPU_ARCH_PROTOCOL *This
+ )
+{
+ ArmDisableInterrupts ();
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function retrieves the processor's current interrupt state a returns it in
+ State. If interrupts are currently enabled, then TRUE is returned. If interrupts
+ are currently disabled, then FALSE is returned.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+ @param State A pointer to the processor's current interrupt state. Set to TRUE if
+ interrupts are enabled and FALSE if interrupts are disabled.
+
+ @retval EFI_SUCCESS The processor's current interrupt state was returned in State.
+ @retval EFI_INVALID_PARAMETER State is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuGetInterruptState (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ OUT BOOLEAN *State
+ )
+{
+ if (State == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *State = ArmGetInterruptState();
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function generates an INIT on the processor. If this function succeeds, then the
+ processor will be reset, and control will not be returned to the caller. If InitType is
+ not supported by this processor, or the processor cannot programmatically generate an
+ INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error
+ occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+ @param InitType The type of processor INIT to perform.
+
+ @retval EFI_SUCCESS The processor INIT was performed. This return code should never be seen.
+ @retval EFI_UNSUPPORTED The processor INIT operation specified by InitType is not supported
+ by this processor.
+ @retval EFI_DEVICE_ERROR The processor INIT failed.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuInit (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_CPU_INIT_TYPE InitType
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+EFIAPI
+CpuRegisterInterruptHandler (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ )
+{
+ return RegisterInterruptHandler (InterruptType, InterruptHandler);
+}
+
+EFI_STATUS
+EFIAPI
+CpuGetTimerValue (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN UINT32 TimerIndex,
+ OUT UINT64 *TimerValue,
+ OUT UINT64 *TimerPeriod OPTIONAL
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Callback function for idle events.
+
+ @param Event Event whose notification function is being invoked.
+ @param Context The pointer to the notification function's context,
+ which is implementation-dependent.
+
+**/
+VOID
+EFIAPI
+IdleLoopEventCallback (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ CpuSleep ();
+}
+
+//
+// Globals used to initialize the protocol
+//
+EFI_HANDLE mCpuHandle = NULL;
+EFI_CPU_ARCH_PROTOCOL mCpu = {
+ CpuFlushCpuDataCache,
+ CpuEnableInterrupt,
+ CpuDisableInterrupt,
+ CpuGetInterruptState,
+ CpuInit,
+ CpuRegisterInterruptHandler,
+ CpuGetTimerValue,
+ CpuSetMemoryAttributes,
+ 0, // NumberOfTimers
+ 2048, // DmaBufferAlignment
+};
+
+STATIC
+VOID
+InitializeDma (
+ IN OUT EFI_CPU_ARCH_PROTOCOL *CpuArchProtocol
+ )
+{
+ CpuArchProtocol->DmaBufferAlignment = ArmCacheWritebackGranule ();
+}
+
+EFI_STATUS
+CpuDxeInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_EVENT IdleLoopEvent;
+
+ InitializeExceptions (&mCpu);
+
+ InitializeDma (&mCpu);
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mCpuHandle,
+ &gEfiCpuArchProtocolGuid, &mCpu,
+ NULL
+ );
+
+ //
+ // Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes ()
+ // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go
+ // after the protocol is installed
+ //
+ mIsFlushingGCD = TRUE;
+ SyncCacheConfig (&mCpu);
+ mIsFlushingGCD = FALSE;
+
+ // If the platform is a MPCore system then install the Configuration Table describing the
+ // secondary core states
+ if (ArmIsMpCore()) {
+ PublishArmProcessorTable();
+ }
+
+ //
+ // Setup a callback for idle events
+ //
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ IdleLoopEventCallback,
+ NULL,
+ &gIdleLoopEventGuid,
+ &IdleLoopEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
diff --git a/roms/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.h b/roms/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.h new file mode 100644 index 000000000..3fe5c24d5 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.h @@ -0,0 +1,146 @@ +/** @file
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __CPU_DXE_ARM_EXCEPTION_H__
+#define __CPU_DXE_ARM_EXCEPTION_H__
+
+#include <Uefi.h>
+
+#include <Library/ArmLib.h>
+#include <Library/ArmMmuLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/PeCoffGetEntryPointLib.h>
+#include <Library/UefiLib.h>
+#include <Library/CpuLib.h>
+#include <Library/DefaultExceptionHandlerLib.h>
+#include <Library/DebugLib.h>
+
+#include <Guid/DebugImageInfoTable.h>
+#include <Protocol/Cpu.h>
+#include <Protocol/DebugSupport.h>
+#include <Protocol/LoadedImage.h>
+
+extern BOOLEAN mIsFlushingGCD;
+
+/**
+ This function registers and enables the handler specified by InterruptHandler for a processor
+ interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
+ handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
+ The installed handler is called once for each processor interrupt or exception.
+
+ @param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts
+ are enabled and FALSE if interrupts are disabled.
+ @param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
+ when a processor interrupt occurs. If this parameter is NULL, then the handler
+ will be uninstalled.
+
+ @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.
+ @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was
+ previously installed.
+ @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
+ previously installed.
+ @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported.
+
+**/
+EFI_STATUS
+RegisterInterruptHandler (
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ );
+
+
+/**
+ This function registers and enables the handler specified by InterruptHandler for a processor
+ interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
+ handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
+ The installed handler is called once for each processor interrupt or exception.
+
+ @param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts
+ are enabled and FALSE if interrupts are disabled.
+ @param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
+ when a processor interrupt occurs. If this parameter is NULL, then the handler
+ will be uninstalled.
+
+ @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.
+ @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was
+ previously installed.
+ @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
+ previously installed.
+ @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported.
+
+**/
+EFI_STATUS
+RegisterDebuggerInterruptHandler (
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ );
+
+
+EFI_STATUS
+EFIAPI
+CpuSetMemoryAttributes (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
+ );
+
+EFI_STATUS
+InitializeExceptions (
+ IN EFI_CPU_ARCH_PROTOCOL *Cpu
+ );
+
+EFI_STATUS
+SyncCacheConfig (
+ IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
+ );
+
+/**
+ * Publish ARM Processor Data table in UEFI SYSTEM Table.
+ * @param HobStart Pointer to the beginning of the HOB List from PEI.
+ *
+ * Description : This function iterates through HOB list and finds ARM processor Table Entry HOB.
+ * If the ARM processor Table Entry HOB is found, the HOB data is copied to run-time memory
+ * and a pointer is assigned to it in ARM processor table. Then the ARM processor table is
+ * installed in EFI configuration table.
+**/
+VOID
+EFIAPI
+PublishArmProcessorTable(
+ VOID
+ );
+
+// The ARM Attributes might be defined on 64-bit (case of the long format description table)
+UINT64
+EfiAttributeToArmAttribute (
+ IN UINT64 EfiAttributes
+ );
+
+EFI_STATUS
+GetMemoryRegion (
+ IN OUT UINTN *BaseAddress,
+ OUT UINTN *RegionLength,
+ OUT UINTN *RegionAttributes
+ );
+
+EFI_STATUS
+SetGcdMemorySpaceAttributes (
+ IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
+ IN UINTN NumberOfDescriptors,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
+ );
+
+#endif // __CPU_DXE_ARM_EXCEPTION_H__
diff --git a/roms/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.inf b/roms/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.inf new file mode 100644 index 000000000..e5549fc71 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.inf @@ -0,0 +1,71 @@ +#/** @file
+#
+# DXE CPU driver
+#
+# Copyright (c) 2009, Apple Inc. All rights reserved.<BR>
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmCpuDxe
+ FILE_GUID = B8D9777E-D72A-451F-9BDB-BAFB52A68415
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = CpuDxeInitialize
+
+[Sources.Common]
+ CpuDxe.c
+ CpuDxe.h
+ CpuMpCore.c
+ CpuMmuCommon.c
+ Exception.c
+
+[Sources.ARM]
+ Arm/Mmu.c
+
+[Sources.AARCH64]
+ AArch64/Mmu.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+
+[LibraryClasses]
+ ArmLib
+ ArmMmuLib
+ BaseMemoryLib
+ CacheMaintenanceLib
+ CpuLib
+ CpuExceptionHandlerLib
+ DebugLib
+ DefaultExceptionHandlerLib
+ DxeServicesTableLib
+ HobLib
+ PeCoffGetEntryPointLib
+ UefiDriverEntryPoint
+ UefiLib
+
+[Protocols]
+ gEfiCpuArchProtocolGuid
+
+[Guids]
+ gEfiDebugImageInfoTableGuid
+ gArmMpCoreInfoGuid
+ gIdleLoopEventGuid
+ gEfiVectorHandoffTableGuid
+
+[Pcd.common]
+ gArmTokenSpaceGuid.PcdVFPEnabled
+
+[FeaturePcd.common]
+ gArmTokenSpaceGuid.PcdDebuggerExceptionSupport
+
+[Depex]
+ gHardwareInterruptProtocolGuid OR gHardwareInterrupt2ProtocolGuid
diff --git a/roms/edk2/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c b/roms/edk2/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c new file mode 100644 index 000000000..cdb1d6786 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c @@ -0,0 +1,211 @@ +/** @file
+*
+* Copyright (c) 2013, ARM Limited. All rights reserved.
+* Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include "CpuDxe.h"
+
+/**
+ Searches memory descriptors covered by given memory range.
+
+ This function searches into the Gcd Memory Space for descriptors
+ (from StartIndex to EndIndex) that contains the memory range
+ specified by BaseAddress and Length.
+
+ @param MemorySpaceMap Gcd Memory Space Map as array.
+ @param NumberOfDescriptors Number of descriptors in map.
+ @param BaseAddress BaseAddress for the requested range.
+ @param Length Length for the requested range.
+ @param StartIndex Start index into the Gcd Memory Space Map.
+ @param EndIndex End index into the Gcd Memory Space Map.
+
+ @retval EFI_SUCCESS Search successfully.
+ @retval EFI_NOT_FOUND The requested descriptors does not exist.
+
+**/
+EFI_STATUS
+SearchGcdMemorySpaces (
+ IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
+ IN UINTN NumberOfDescriptors,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ OUT UINTN *StartIndex,
+ OUT UINTN *EndIndex
+ )
+{
+ UINTN Index;
+
+ *StartIndex = 0;
+ *EndIndex = 0;
+ for (Index = 0; Index < NumberOfDescriptors; Index++) {
+ if ((BaseAddress >= MemorySpaceMap[Index].BaseAddress) &&
+ (BaseAddress < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length))) {
+ *StartIndex = Index;
+ }
+ if (((BaseAddress + Length - 1) >= MemorySpaceMap[Index].BaseAddress) &&
+ ((BaseAddress + Length - 1) < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length))) {
+ *EndIndex = Index;
+ return EFI_SUCCESS;
+ }
+ }
+ return EFI_NOT_FOUND;
+}
+
+
+/**
+ Sets the attributes for a specified range in Gcd Memory Space Map.
+
+ This function sets the attributes for a specified range in
+ Gcd Memory Space Map.
+
+ @param MemorySpaceMap Gcd Memory Space Map as array
+ @param NumberOfDescriptors Number of descriptors in map
+ @param BaseAddress BaseAddress for the range
+ @param Length Length for the range
+ @param Attributes Attributes to set
+
+ @retval EFI_SUCCESS Memory attributes set successfully
+ @retval EFI_NOT_FOUND The specified range does not exist in Gcd Memory Space
+
+**/
+EFI_STATUS
+SetGcdMemorySpaceAttributes (
+ IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
+ IN UINTN NumberOfDescriptors,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
+ )
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ UINTN StartIndex;
+ UINTN EndIndex;
+ EFI_PHYSICAL_ADDRESS RegionStart;
+ UINT64 RegionLength;
+
+ DEBUG ((DEBUG_GCD, "SetGcdMemorySpaceAttributes[0x%lX; 0x%lX] = 0x%lX\n",
+ BaseAddress, BaseAddress + Length, Attributes));
+
+ // We do not support a smaller granularity than 4KB on ARM Architecture
+ if ((Length & EFI_PAGE_MASK) != 0) {
+ DEBUG ((DEBUG_WARN,
+ "Warning: We do not support smaller granularity than 4KB on ARM Architecture (passed length: 0x%lX).\n",
+ Length));
+ }
+
+ //
+ // Get all memory descriptors covered by the memory range
+ //
+ Status = SearchGcdMemorySpaces (
+ MemorySpaceMap,
+ NumberOfDescriptors,
+ BaseAddress,
+ Length,
+ &StartIndex,
+ &EndIndex
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Go through all related descriptors and set attributes accordingly
+ //
+ for (Index = StartIndex; Index <= EndIndex; Index++) {
+ if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
+ continue;
+ }
+ //
+ // Calculate the start and end address of the overlapping range
+ //
+ if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {
+ RegionStart = BaseAddress;
+ } else {
+ RegionStart = MemorySpaceMap[Index].BaseAddress;
+ }
+ if ((BaseAddress + Length - 1) < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length)) {
+ RegionLength = BaseAddress + Length - RegionStart;
+ } else {
+ RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
+ }
+ //
+ // Set memory attributes according to MTRR attribute and the original attribute of descriptor
+ //
+ gDS->SetMemorySpaceAttributes (
+ RegionStart,
+ RegionLength,
+ (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)
+ );
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function modifies the attributes for the memory region specified by BaseAddress and
+ Length from their current attributes to the attributes specified by Attributes.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+ @param BaseAddress The physical address that is the start address of a memory region.
+ @param Length The size in bytes of the memory region.
+ @param Attributes The bit mask of attributes to set for the memory region.
+
+ @retval EFI_SUCCESS The attributes were set for the memory region.
+ @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by
+ BaseAddress and Length cannot be modified.
+ @retval EFI_INVALID_PARAMETER Length is zero.
+ @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
+ the memory resource range.
+ @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory
+ resource range specified by BaseAddress and Length.
+ The bit mask of attributes is not support for the memory resource
+ range specified by BaseAddress and Length.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuSetMemoryAttributes (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 EfiAttributes
+ )
+{
+ EFI_STATUS Status;
+ UINTN ArmAttributes;
+ UINTN RegionBaseAddress;
+ UINTN RegionLength;
+ UINTN RegionArmAttributes;
+
+ if (mIsFlushingGCD) {
+ return EFI_SUCCESS;
+ }
+
+ if ((BaseAddress & (SIZE_4KB - 1)) != 0) {
+ // Minimum granularity is SIZE_4KB (4KB on ARM)
+ DEBUG ((DEBUG_PAGE, "CpuSetMemoryAttributes(%lx, %lx, %lx): Minimum granularity is SIZE_4KB\n", BaseAddress, Length, EfiAttributes));
+ return EFI_UNSUPPORTED;
+ }
+
+ // Convert the 'Attribute' into ARM Attribute
+ ArmAttributes = EfiAttributeToArmAttribute (EfiAttributes);
+
+ // Get the region starting from 'BaseAddress' and its 'Attribute'
+ RegionBaseAddress = BaseAddress;
+ Status = GetMemoryRegion (&RegionBaseAddress, &RegionLength, &RegionArmAttributes);
+
+ // Data & Instruction Caches are flushed when we set new memory attributes.
+ // So, we only set the attributes if the new region is different.
+ if (EFI_ERROR (Status) || (RegionArmAttributes != ArmAttributes) ||
+ ((BaseAddress + Length) > (RegionBaseAddress + RegionLength)))
+ {
+ return ArmSetMemoryAttributes (BaseAddress, Length, EfiAttributes);
+ } else {
+ return EFI_SUCCESS;
+ }
+}
diff --git a/roms/edk2/ArmPkg/Drivers/CpuDxe/CpuMpCore.c b/roms/edk2/ArmPkg/Drivers/CpuDxe/CpuMpCore.c new file mode 100644 index 000000000..d16ae3979 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/CpuDxe/CpuMpCore.c @@ -0,0 +1,97 @@ +/** @file
+*
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/HobLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#include <Guid/ArmMpCoreInfo.h>
+
+ARM_PROCESSOR_TABLE mArmProcessorTableTemplate = {
+ {
+ EFI_ARM_PROCESSOR_TABLE_SIGNATURE,
+ 0,
+ EFI_ARM_PROCESSOR_TABLE_REVISION,
+ EFI_ARM_PROCESSOR_TABLE_OEM_ID,
+ EFI_ARM_PROCESSOR_TABLE_OEM_TABLE_ID,
+ EFI_ARM_PROCESSOR_TABLE_OEM_REVISION,
+ EFI_ARM_PROCESSOR_TABLE_CREATOR_ID,
+ EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION,
+ { 0 },
+ 0
+ }, //ARM Processor table header
+ 0, // Number of entries in ARM processor Table
+ NULL // ARM Processor Table
+};
+
+/** Publish ARM Processor Data table in UEFI SYSTEM Table.
+ * @param: HobStart Pointer to the beginning of the HOB List from PEI.
+ *
+ * Description : This function iterates through HOB list and finds ARM processor Table Entry HOB.
+ * If the ARM processor Table Entry HOB is found, the HOB data is copied to run-time memory
+ * and a pointer is assigned to it in ARM processor table. Then the ARM processor table is
+ * installed in EFI configuration table.
+**/
+VOID
+EFIAPI
+PublishArmProcessorTable (
+ VOID
+ )
+{
+ EFI_PEI_HOB_POINTERS Hob;
+
+ Hob.Raw = GetHobList ();
+
+ // Iterate through the HOBs and find if there is ARM PROCESSOR ENTRY HOB
+ for (; !END_OF_HOB_LIST(Hob); Hob.Raw = GET_NEXT_HOB(Hob)) {
+ // Check for Correct HOB type
+ if ((GET_HOB_TYPE (Hob)) == EFI_HOB_TYPE_GUID_EXTENSION) {
+ // Check for correct GUID type
+ if (CompareGuid(&(Hob.Guid->Name), &gArmMpCoreInfoGuid)) {
+ ARM_PROCESSOR_TABLE *ArmProcessorTable;
+ EFI_STATUS Status;
+
+ // Allocate Runtime memory for ARM processor table
+ ArmProcessorTable = (ARM_PROCESSOR_TABLE*)AllocateRuntimePool(sizeof(ARM_PROCESSOR_TABLE));
+
+ // Check if the memory allocation is successful or not
+ ASSERT(NULL != ArmProcessorTable);
+
+ // Set ARM processor table to default values
+ CopyMem(ArmProcessorTable,&mArmProcessorTableTemplate,sizeof(ARM_PROCESSOR_TABLE));
+
+ // Fill in Length fields of ARM processor table
+ ArmProcessorTable->Header.Length = sizeof(ARM_PROCESSOR_TABLE);
+ ArmProcessorTable->Header.DataLen = GET_GUID_HOB_DATA_SIZE(Hob);
+
+ // Fill in Identifier(ARM processor table GUID)
+ ArmProcessorTable->Header.Identifier = gArmMpCoreInfoGuid;
+
+ // Set Number of ARM core entries in the Table
+ ArmProcessorTable->NumberOfEntries = GET_GUID_HOB_DATA_SIZE(Hob)/sizeof(ARM_CORE_INFO);
+
+ // Allocate runtime memory for ARM processor Table entries
+ ArmProcessorTable->ArmCpus = (ARM_CORE_INFO*)AllocateRuntimePool (
+ ArmProcessorTable->NumberOfEntries * sizeof(ARM_CORE_INFO));
+
+ // Check if the memory allocation is successful or not
+ ASSERT(NULL != ArmProcessorTable->ArmCpus);
+
+ // Copy ARM Processor Table data from HOB list to newly allocated memory
+ CopyMem(ArmProcessorTable->ArmCpus,GET_GUID_HOB_DATA(Hob), ArmProcessorTable->Header.DataLen);
+
+ // Install the ARM Processor table into EFI system configuration table
+ Status = gBS->InstallConfigurationTable (&gArmMpCoreInfoGuid, ArmProcessorTable);
+
+ ASSERT_EFI_ERROR (Status);
+ }
+ }
+ }
+}
diff --git a/roms/edk2/ArmPkg/Drivers/CpuDxe/Exception.c b/roms/edk2/ArmPkg/Drivers/CpuDxe/Exception.c new file mode 100644 index 000000000..50ed50ebb --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/CpuDxe/Exception.c @@ -0,0 +1,98 @@ +/** @file
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Portions Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "CpuDxe.h"
+#include <Library/CpuExceptionHandlerLib.h>
+#include <Guid/VectorHandoffTable.h>
+
+EFI_STATUS
+InitializeExceptions (
+ IN EFI_CPU_ARCH_PROTOCOL *Cpu
+ ) {
+ EFI_STATUS Status;
+ EFI_VECTOR_HANDOFF_INFO *VectorInfoList;
+ EFI_VECTOR_HANDOFF_INFO *VectorInfo;
+ BOOLEAN IrqEnabled;
+ BOOLEAN FiqEnabled;
+
+ VectorInfo = (EFI_VECTOR_HANDOFF_INFO *)NULL;
+ Status = EfiGetSystemConfigurationTable(&gEfiVectorHandoffTableGuid, (VOID **)&VectorInfoList);
+ if (Status == EFI_SUCCESS && VectorInfoList != NULL) {
+ VectorInfo = VectorInfoList;
+ }
+
+ // initialize the CpuExceptionHandlerLib so we take over the exception vector table from the DXE Core
+ InitializeCpuExceptionHandlers(VectorInfo);
+
+ Status = EFI_SUCCESS;
+
+ //
+ // Disable interrupts
+ //
+ Cpu->GetInterruptState (Cpu, &IrqEnabled);
+ Cpu->DisableInterrupt (Cpu);
+
+ //
+ // EFI does not use the FIQ, but a debugger might so we must disable
+ // as we take over the exception vectors.
+ //
+ FiqEnabled = ArmGetFiqState ();
+ ArmDisableFiq ();
+
+ if (FiqEnabled) {
+ ArmEnableFiq ();
+ }
+
+ if (IrqEnabled) {
+ //
+ // Restore interrupt state
+ //
+ Status = Cpu->EnableInterrupt (Cpu);
+ }
+
+ //
+ // On a DEBUG build, unmask SErrors so they are delivered right away rather
+ // than when the OS unmasks them. This gives us a better chance of figuring
+ // out the cause.
+ //
+ DEBUG_CODE (
+ ArmEnableAsynchronousAbort ();
+ );
+
+ return Status;
+}
+
+/**
+This function registers and enables the handler specified by InterruptHandler for a processor
+interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
+handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
+The installed handler is called once for each processor interrupt or exception.
+
+@param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts
+are enabled and FALSE if interrupts are disabled.
+@param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
+when a processor interrupt occurs. If this parameter is NULL, then the handler
+will be uninstalled.
+
+@retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.
+@retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was
+previously installed.
+@retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
+previously installed.
+@retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported.
+
+**/
+EFI_STATUS
+RegisterInterruptHandler(
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ ) {
+ // pass down to CpuExceptionHandlerLib
+ return (EFI_STATUS)RegisterCpuInterruptHandler(InterruptType, InterruptHandler);
+}
diff --git a/roms/edk2/ArmPkg/Drivers/CpuPei/CpuPei.c b/roms/edk2/ArmPkg/Drivers/CpuPei/CpuPei.c new file mode 100644 index 000000000..c44311d6b --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/CpuPei/CpuPei.c @@ -0,0 +1,85 @@ +/**@file
+
+Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2011 Hewlett Packard Corporation. All rights reserved.<BR>
+Copyright (c) 2011-2013, ARM Limited. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+Module Name:
+
+ MemoryInit.c
+
+Abstract:
+
+ PEIM to provide fake memory init
+
+**/
+
+
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+//
+// The protocols, PPI and GUID definitions for this module
+//
+#include <Ppi/ArmMpCoreInfo.h>
+
+//
+// The Library classes this module consumes
+//
+#include <Library/DebugLib.h>
+#include <Library/PeimEntryPoint.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PcdLib.h>
+#include <Library/HobLib.h>
+#include <Library/ArmLib.h>
+
+/*++
+
+Routine Description:
+
+Arguments:
+
+ FileHandle - Handle of the file being invoked.
+ PeiServices - Describes the list of possible PEI Services.
+
+Returns:
+
+ Status - EFI_SUCCESS if the boot mode could be set
+
+--*/
+EFI_STATUS
+EFIAPI
+InitializeCpuPeim (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;
+ UINTN ArmCoreCount;
+ ARM_CORE_INFO *ArmCoreInfoTable;
+
+ // Enable program flow prediction, if supported.
+ ArmEnableBranchPrediction ();
+
+ // Publish the CPU memory and io spaces sizes
+ BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize));
+
+ // Only MP Core platform need to produce gArmMpCoreInfoPpiGuid
+ Status = PeiServicesLocatePpi (&gArmMpCoreInfoPpiGuid, 0, NULL, (VOID**)&ArmMpCoreInfoPpi);
+ if (!EFI_ERROR(Status)) {
+ // Build the MP Core Info Table
+ ArmCoreCount = 0;
+ Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
+ if (!EFI_ERROR(Status) && (ArmCoreCount > 0)) {
+ // Build MPCore Info HOB
+ BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/roms/edk2/ArmPkg/Drivers/CpuPei/CpuPei.inf b/roms/edk2/ArmPkg/Drivers/CpuPei/CpuPei.inf new file mode 100644 index 000000000..a9f85cbc6 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/CpuPei/CpuPei.inf @@ -0,0 +1,52 @@ +## @file
+# Component description file for BootMode module
+#
+# This module provides platform specific function to detect boot mode.
+# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = CpuPei
+ FILE_GUID = 2FD8B7AD-F8FA-4021-9FC0-0AA572147CDC
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = InitializeCpuPeim
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = ARM
+#
+
+[Sources]
+ CpuPei.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+
+[LibraryClasses]
+ PeimEntryPoint
+ DebugLib
+ HobLib
+ ArmLib
+
+[Ppis]
+ gArmMpCoreInfoPpiGuid
+
+[Guids]
+ gArmMpCoreInfoGuid
+
+[FixedPcd]
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize
+
+[Depex]
+ gEfiPeiMemoryDiscoveredPpiGuid
+
diff --git a/roms/edk2/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h b/roms/edk2/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h new file mode 100644 index 000000000..c64bc5c46 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h @@ -0,0 +1,24 @@ +/** @file
+*
+* Copyright (c) 2013-2017, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#ifndef __GENERIC_WATCHDOG_H__
+#define __GENERIC_WATCHDOG_H__
+
+// Refresh Frame:
+#define GENERIC_WDOG_REFRESH_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogRefreshBase) + 0x000)
+
+// Control Frame:
+#define GENERIC_WDOG_CONTROL_STATUS_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x000)
+#define GENERIC_WDOG_OFFSET_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x008)
+#define GENERIC_WDOG_COMPARE_VALUE_REG_LOW ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x010)
+#define GENERIC_WDOG_COMPARE_VALUE_REG_HIGH ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x014)
+
+// Values of bit 0 of the Control/Status Register
+#define GENERIC_WDOG_ENABLED 1
+#define GENERIC_WDOG_DISABLED 0
+
+#endif // __GENERIC_WATCHDOG_H__
diff --git a/roms/edk2/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c b/roms/edk2/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c new file mode 100644 index 000000000..f79cc9170 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c @@ -0,0 +1,363 @@ +/** @file
+*
+* Copyright (c) 2013-2018, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <PiDxe.h>
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/ArmGenericTimerCounterLib.h>
+
+#include <Protocol/HardwareInterrupt2.h>
+#include <Protocol/WatchdogTimer.h>
+
+#include "GenericWatchdog.h"
+
+/* The number of 100ns periods (the unit of time passed to these functions)
+ in a second */
+#define TIME_UNITS_PER_SECOND 10000000
+
+// Tick frequency of the generic timer basis of the generic watchdog.
+STATIC UINTN mTimerFrequencyHz = 0;
+
+/* In cases where the compare register was set manually, information about
+ how long the watchdog was asked to wait cannot be retrieved from hardware.
+ It is therefore stored here. 0 means the timer is not running. */
+STATIC UINT64 mNumTimerTicks = 0;
+
+STATIC EFI_HARDWARE_INTERRUPT2_PROTOCOL *mInterruptProtocol;
+STATIC EFI_WATCHDOG_TIMER_NOTIFY mWatchdogNotify;
+
+STATIC
+VOID
+WatchdogWriteOffsetRegister (
+ UINT32 Value
+ )
+{
+ MmioWrite32 (GENERIC_WDOG_OFFSET_REG, Value);
+}
+
+STATIC
+VOID
+WatchdogWriteCompareRegister (
+ UINT64 Value
+ )
+{
+ MmioWrite32 (GENERIC_WDOG_COMPARE_VALUE_REG_LOW, Value & MAX_UINT32);
+ MmioWrite32 (GENERIC_WDOG_COMPARE_VALUE_REG_HIGH, (Value >> 32) & MAX_UINT32);
+}
+
+STATIC
+VOID
+WatchdogEnable (
+ VOID
+ )
+{
+ MmioWrite32 (GENERIC_WDOG_CONTROL_STATUS_REG, GENERIC_WDOG_ENABLED);
+}
+
+STATIC
+VOID
+WatchdogDisable (
+ VOID
+ )
+{
+ MmioWrite32 (GENERIC_WDOG_CONTROL_STATUS_REG, GENERIC_WDOG_DISABLED);
+}
+
+/** On exiting boot services we must make sure the Watchdog Timer
+ is stopped.
+**/
+STATIC
+VOID
+EFIAPI
+WatchdogExitBootServicesEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ WatchdogDisable ();
+ mNumTimerTicks = 0;
+}
+
+/* This function is called when the watchdog's first signal (WS0) goes high.
+ It uses the ResetSystem Runtime Service to reset the board.
+*/
+STATIC
+VOID
+EFIAPI
+WatchdogInterruptHandler (
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ )
+{
+ STATIC CONST CHAR16 ResetString[]= L"The generic watchdog timer ran out.";
+ UINT64 TimerPeriod;
+
+ WatchdogDisable ();
+
+ mInterruptProtocol->EndOfInterrupt (mInterruptProtocol, Source);
+
+ //
+ // The notify function should be called with the elapsed number of ticks
+ // since the watchdog was armed, which should exceed the timer period.
+ // We don't actually know the elapsed number of ticks, so let's return
+ // the timer period plus 1.
+ //
+ if (mWatchdogNotify != NULL) {
+ TimerPeriod = ((TIME_UNITS_PER_SECOND / mTimerFrequencyHz) * mNumTimerTicks);
+ mWatchdogNotify (TimerPeriod + 1);
+ }
+
+ gRT->ResetSystem (EfiResetCold, EFI_TIMEOUT, StrSize (ResetString),
+ (CHAR16 *)ResetString);
+
+ // If we got here then the reset didn't work
+ ASSERT (FALSE);
+}
+
+/**
+ This function registers the handler NotifyFunction so it is called every time
+ the watchdog timer expires. It also passes the amount of time since the last
+ handler call to the NotifyFunction.
+ If NotifyFunction is not NULL and a handler is not already registered,
+ then the new handler is registered and EFI_SUCCESS is returned.
+ If NotifyFunction is NULL, and a handler is already registered,
+ then that handler is unregistered.
+ If an attempt is made to register a handler when a handler is already
+ registered, then EFI_ALREADY_STARTED is returned.
+ If an attempt is made to unregister a handler when a handler is not
+ registered, then EFI_INVALID_PARAMETER is returned.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param NotifyFunction The function to call when a timer interrupt fires.
+ This function executes at TPL_HIGH_LEVEL. The DXE
+ Core will register a handler for the timer interrupt,
+ so it can know how much time has passed. This
+ information is used to signal timer based events.
+ NULL will unregister the handler.
+
+ @retval EFI_UNSUPPORTED The code does not support NotifyFunction.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+WatchdogRegisterHandler (
+ IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
+ IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction
+ )
+{
+ if (mWatchdogNotify == NULL && NotifyFunction == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (mWatchdogNotify != NULL && NotifyFunction != NULL) {
+ return EFI_ALREADY_STARTED;
+ }
+
+ mWatchdogNotify = NotifyFunction;
+ return EFI_SUCCESS;
+}
+
+/**
+ This function sets the amount of time to wait before firing the watchdog
+ timer to TimerPeriod 100ns units. If TimerPeriod is 0, then the watchdog
+ timer is disabled.
+
+ @param This The EFI_WATCHDOG_TIMER_ARCH_PROTOCOL instance.
+ @param TimerPeriod The amount of time in 100ns units to wait before
+ the watchdog timer is fired. If TimerPeriod is zero,
+ then the watchdog timer is disabled.
+
+ @retval EFI_SUCCESS The watchdog timer has been programmed to fire
+ in TimerPeriod 100ns units.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+WatchdogSetTimerPeriod (
+ IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
+ IN UINT64 TimerPeriod // In 100ns units
+ )
+{
+ UINTN SystemCount;
+
+ // if TimerPeriod is 0, this is a request to stop the watchdog.
+ if (TimerPeriod == 0) {
+ mNumTimerTicks = 0;
+ WatchdogDisable ();
+ return EFI_SUCCESS;
+ }
+
+ // Work out how many timer ticks will equate to TimerPeriod
+ mNumTimerTicks = (mTimerFrequencyHz * TimerPeriod) / TIME_UNITS_PER_SECOND;
+
+ /* If the number of required ticks is greater than the max the watchdog's
+ offset register (WOR) can hold, we need to manually compute and set
+ the compare register (WCV) */
+ if (mNumTimerTicks > MAX_UINT32) {
+ /* We need to enable the watchdog *before* writing to the compare register,
+ because enabling the watchdog causes an "explicit refresh", which
+ clobbers the compare register (WCV). In order to make sure this doesn't
+ trigger an interrupt, set the offset to max. */
+ WatchdogWriteOffsetRegister (MAX_UINT32);
+ WatchdogEnable ();
+ SystemCount = ArmGenericTimerGetSystemCount ();
+ WatchdogWriteCompareRegister (SystemCount + mNumTimerTicks);
+ } else {
+ WatchdogWriteOffsetRegister ((UINT32)mNumTimerTicks);
+ WatchdogEnable ();
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function retrieves the period of timer interrupts in 100ns units,
+ returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
+ is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
+ returned, then the timer is currently disabled.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param TimerPeriod A pointer to the timer period to retrieve in
+ 100ns units. If 0 is returned, then the timer is
+ currently disabled.
+
+
+ @retval EFI_SUCCESS The timer period was returned in TimerPeriod.
+ @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+WatchdogGetTimerPeriod (
+ IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
+ OUT UINT64 *TimerPeriod
+ )
+{
+ if (TimerPeriod == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *TimerPeriod = ((TIME_UNITS_PER_SECOND / mTimerFrequencyHz) * mNumTimerTicks);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Interface structure for the Watchdog Architectural Protocol.
+
+ @par Protocol Description:
+ This protocol provides a service to set the amount of time to wait
+ before firing the watchdog timer, and it also provides a service to
+ register a handler that is invoked when the watchdog timer fires.
+
+ @par When the watchdog timer fires, control will be passed to a handler
+ if one has been registered. If no handler has been registered,
+ or the registered handler returns, then the system will be
+ reset by calling the Runtime Service ResetSystem().
+
+ @param RegisterHandler
+ Registers a handler that will be called each time the
+ watchdogtimer interrupt fires. TimerPeriod defines the minimum
+ time between timer interrupts, so TimerPeriod will also
+ be the minimum time between calls to the registered
+ handler.
+ NOTE: If the watchdog resets the system in hardware, then
+ this function will not have any chance of executing.
+
+ @param SetTimerPeriod
+ Sets the period of the timer interrupt in 100ns units.
+ This function is optional, and may return EFI_UNSUPPORTED.
+ If this function is supported, then the timer period will
+ be rounded up to the nearest supported timer period.
+
+ @param GetTimerPeriod
+ Retrieves the period of the timer interrupt in 100ns units.
+
+**/
+STATIC EFI_WATCHDOG_TIMER_ARCH_PROTOCOL mWatchdogTimer = {
+ WatchdogRegisterHandler,
+ WatchdogSetTimerPeriod,
+ WatchdogGetTimerPeriod
+};
+
+STATIC EFI_EVENT mEfiExitBootServicesEvent;
+
+EFI_STATUS
+EFIAPI
+GenericWatchdogEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+
+ Status = gBS->LocateProtocol (&gHardwareInterrupt2ProtocolGuid, NULL,
+ (VOID **)&mInterruptProtocol);
+ ASSERT_EFI_ERROR (Status);
+
+ /* Make sure the Watchdog Timer Architectural Protocol has not been installed
+ in the system yet.
+ This will avoid conflicts with the universal watchdog */
+ ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiWatchdogTimerArchProtocolGuid);
+
+ mTimerFrequencyHz = ArmGenericTimerGetTimerFreq ();
+ ASSERT (mTimerFrequencyHz != 0);
+
+ // Install interrupt handler
+ Status = mInterruptProtocol->RegisterInterruptSource (mInterruptProtocol,
+ FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),
+ WatchdogInterruptHandler);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = mInterruptProtocol->SetTriggerType (mInterruptProtocol,
+ FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),
+ EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING);
+ if (EFI_ERROR (Status)) {
+ goto UnregisterHandler;
+ }
+
+ // Install the Timer Architectural Protocol onto a new handle
+ Handle = NULL;
+ Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
+ &gEfiWatchdogTimerArchProtocolGuid, &mWatchdogTimer,
+ NULL);
+ if (EFI_ERROR (Status)) {
+ goto UnregisterHandler;
+ }
+
+ // Register for an ExitBootServicesEvent
+ Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY,
+ WatchdogExitBootServicesEvent, NULL,
+ &mEfiExitBootServicesEvent);
+ ASSERT_EFI_ERROR (Status);
+
+ mNumTimerTicks = 0;
+ WatchdogDisable ();
+
+ return EFI_SUCCESS;
+
+UnregisterHandler:
+ // Unregister the handler
+ mInterruptProtocol->RegisterInterruptSource (mInterruptProtocol,
+ FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),
+ NULL);
+ return Status;
+}
diff --git a/roms/edk2/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf b/roms/edk2/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf new file mode 100644 index 000000000..d725a2c85 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf @@ -0,0 +1,46 @@ +#
+# Copyright (c) 2013-2017, ARM Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+ INF_VERSION = 0x00010016
+ BASE_NAME = GenericWatchdogDxe
+ FILE_GUID = 0619f5c2-4858-4caa-a86a-73a21a18df6b
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = GenericWatchdogEntry
+
+[Sources.common]
+ GenericWatchdogDxe.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ ArmGenericTimerCounterLib
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ IoLib
+ PcdLib
+ UefiLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiRuntimeServicesTableLib
+
+[Pcd.common]
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum
+
+[Protocols]
+ gEfiWatchdogTimerArchProtocolGuid ## ALWAYS_PRODUCES
+ gHardwareInterrupt2ProtocolGuid ## ALWAYS_CONSUMES
+
+[Depex]
+ gHardwareInterrupt2ProtocolGuid
diff --git a/roms/edk2/ArmPkg/Drivers/MmCommunicationDxe/MmCommunicate.h b/roms/edk2/ArmPkg/Drivers/MmCommunicationDxe/MmCommunicate.h new file mode 100644 index 000000000..fcc346ba7 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/MmCommunicationDxe/MmCommunicate.h @@ -0,0 +1,22 @@ +/** @file
+
+ Copyright (c) 2016-2018, ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#if !defined _MM_COMMUNICATE_H_
+#define _MM_COMMUNICATE_H_
+
+#define MM_MAJOR_VER_MASK 0xEFFF0000
+#define MM_MINOR_VER_MASK 0x0000FFFF
+#define MM_MAJOR_VER_SHIFT 16
+
+#define MM_MAJOR_VER(x) (((x) & MM_MAJOR_VER_MASK) >> MM_MAJOR_VER_SHIFT)
+#define MM_MINOR_VER(x) ((x) & MM_MINOR_VER_MASK)
+
+#define MM_CALLER_MAJOR_VER 0x1UL
+#define MM_CALLER_MINOR_VER 0x0
+
+#endif /* _MM_COMMUNICATE_H_ */
diff --git a/roms/edk2/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c b/roms/edk2/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c new file mode 100644 index 000000000..9457eaf1d --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c @@ -0,0 +1,412 @@ +/** @file
+
+ Copyright (c) 2016-2019, ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/ArmLib.h>
+#include <Library/ArmSmcLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+
+#include <Protocol/MmCommunication2.h>
+
+#include <IndustryStandard/ArmStdSmc.h>
+
+#include "MmCommunicate.h"
+
+//
+// Address, Length of the pre-allocated buffer for communication with the secure
+// world.
+//
+STATIC ARM_MEMORY_REGION_DESCRIPTOR mNsCommBuffMemRegion;
+
+// Notification event when virtual address map is set.
+STATIC EFI_EVENT mSetVirtualAddressMapEvent;
+
+//
+// Handle to install the MM Communication Protocol
+//
+STATIC EFI_HANDLE mMmCommunicateHandle;
+
+/**
+ Communicates with a registered handler.
+
+ This function provides a service to send and receive messages from a registered UEFI service.
+
+ @param[in] This The EFI_MM_COMMUNICATION_PROTOCOL instance.
+ @param[in] CommBufferPhysical Physical address of the MM communication buffer
+ @param[in] CommBufferVirtual Virtual address of the MM communication buffer
+ @param[in] CommSize The size of the data buffer being passed in. On exit, the size of data
+ being returned. Zero if the handler does not wish to reply with any data.
+ This parameter is optional and may be NULL.
+
+ @retval EFI_SUCCESS The message was successfully posted.
+ @retval EFI_INVALID_PARAMETER CommBufferPhysical was NULL or CommBufferVirtual was NULL.
+ @retval EFI_BAD_BUFFER_SIZE The buffer is too large for the MM implementation.
+ If this error is returned, the MessageLength field
+ in the CommBuffer header or the integer pointed by
+ CommSize, are updated to reflect the maximum payload
+ size the implementation can accommodate.
+ @retval EFI_ACCESS_DENIED The CommunicateBuffer parameter or CommSize parameter,
+ if not omitted, are in address range that cannot be
+ accessed by the MM environment.
+
+**/
+EFI_STATUS
+EFIAPI
+MmCommunication2Communicate (
+ IN CONST EFI_MM_COMMUNICATION2_PROTOCOL *This,
+ IN OUT VOID *CommBufferPhysical,
+ IN OUT VOID *CommBufferVirtual,
+ IN OUT UINTN *CommSize OPTIONAL
+ )
+{
+ EFI_MM_COMMUNICATE_HEADER *CommunicateHeader;
+ ARM_SMC_ARGS CommunicateSmcArgs;
+ EFI_STATUS Status;
+ UINTN BufferSize;
+
+ Status = EFI_ACCESS_DENIED;
+ BufferSize = 0;
+
+ ZeroMem (&CommunicateSmcArgs, sizeof (ARM_SMC_ARGS));
+
+ //
+ // Check parameters
+ //
+ if (CommBufferVirtual == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ CommunicateHeader = CommBufferVirtual;
+ // CommBuffer is a mandatory parameter. Hence, Rely on
+ // MessageLength + Header to ascertain the
+ // total size of the communication payload rather than
+ // rely on optional CommSize parameter
+ BufferSize = CommunicateHeader->MessageLength +
+ sizeof (CommunicateHeader->HeaderGuid) +
+ sizeof (CommunicateHeader->MessageLength);
+
+ // If the length of the CommBuffer is 0 then return the expected length.
+ if (CommSize) {
+ // This case can be used by the consumer of this driver to find out the
+ // max size that can be used for allocating CommBuffer.
+ if ((*CommSize == 0) ||
+ (*CommSize > mNsCommBuffMemRegion.Length)) {
+ *CommSize = mNsCommBuffMemRegion.Length;
+ return EFI_BAD_BUFFER_SIZE;
+ }
+ //
+ // CommSize must match MessageLength + sizeof (EFI_MM_COMMUNICATE_HEADER);
+ //
+ if (*CommSize != BufferSize) {
+ return EFI_INVALID_PARAMETER;
+ }
+ }
+
+ //
+ // If the buffer size is 0 or greater than what can be tolerated by the MM
+ // environment then return the expected size.
+ //
+ if ((BufferSize == 0) ||
+ (BufferSize > mNsCommBuffMemRegion.Length)) {
+ CommunicateHeader->MessageLength = mNsCommBuffMemRegion.Length -
+ sizeof (CommunicateHeader->HeaderGuid) -
+ sizeof (CommunicateHeader->MessageLength);
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // SMC Function ID
+ CommunicateSmcArgs.Arg0 = ARM_SMC_ID_MM_COMMUNICATE_AARCH64;
+
+ // Cookie
+ CommunicateSmcArgs.Arg1 = 0;
+
+ // Copy Communication Payload
+ CopyMem ((VOID *)mNsCommBuffMemRegion.VirtualBase, CommBufferVirtual, BufferSize);
+
+ // comm_buffer_address (64-bit physical address)
+ CommunicateSmcArgs.Arg2 = (UINTN)mNsCommBuffMemRegion.PhysicalBase;
+
+ // comm_size_address (not used, indicated by setting to zero)
+ CommunicateSmcArgs.Arg3 = 0;
+
+ // Call the Standalone MM environment.
+ ArmCallSmc (&CommunicateSmcArgs);
+
+ switch (CommunicateSmcArgs.Arg0) {
+ case ARM_SMC_MM_RET_SUCCESS:
+ ZeroMem (CommBufferVirtual, BufferSize);
+ // On successful return, the size of data being returned is inferred from
+ // MessageLength + Header.
+ CommunicateHeader = (EFI_MM_COMMUNICATE_HEADER *)mNsCommBuffMemRegion.VirtualBase;
+ BufferSize = CommunicateHeader->MessageLength +
+ sizeof (CommunicateHeader->HeaderGuid) +
+ sizeof (CommunicateHeader->MessageLength);
+
+ CopyMem (
+ CommBufferVirtual,
+ (VOID *)mNsCommBuffMemRegion.VirtualBase,
+ BufferSize
+ );
+ Status = EFI_SUCCESS;
+ break;
+
+ case ARM_SMC_MM_RET_INVALID_PARAMS:
+ Status = EFI_INVALID_PARAMETER;
+ break;
+
+ case ARM_SMC_MM_RET_DENIED:
+ Status = EFI_ACCESS_DENIED;
+ break;
+
+ case ARM_SMC_MM_RET_NO_MEMORY:
+ // Unexpected error since the CommSize was checked for zero length
+ // prior to issuing the SMC
+ Status = EFI_OUT_OF_RESOURCES;
+ ASSERT (0);
+ break;
+
+ default:
+ Status = EFI_ACCESS_DENIED;
+ ASSERT (0);
+ }
+
+ return Status;
+}
+
+//
+// MM Communication Protocol instance
+//
+STATIC EFI_MM_COMMUNICATION2_PROTOCOL mMmCommunication2 = {
+ MmCommunication2Communicate
+};
+
+/**
+ Notification callback on SetVirtualAddressMap event.
+
+ This function notifies the MM communication protocol interface on
+ SetVirtualAddressMap event and converts pointers used in this driver
+ from physical to virtual address.
+
+ @param Event SetVirtualAddressMap event.
+ @param Context A context when the SetVirtualAddressMap triggered.
+
+ @retval EFI_SUCCESS The function executed successfully.
+ @retval Other Some error occurred when executing this function.
+
+**/
+STATIC
+VOID
+EFIAPI
+NotifySetVirtualAddressMap (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_STATUS Status;
+
+ Status = gRT->ConvertPointer (
+ EFI_OPTIONAL_PTR,
+ (VOID **)&mNsCommBuffMemRegion.VirtualBase
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "NotifySetVirtualAddressMap():"
+ " Unable to convert MM runtime pointer. Status:0x%r\n", Status));
+ }
+
+}
+
+STATIC
+EFI_STATUS
+GetMmCompatibility ()
+{
+ EFI_STATUS Status;
+ UINT32 MmVersion;
+ ARM_SMC_ARGS MmVersionArgs;
+
+ // MM_VERSION uses SMC32 calling conventions
+ MmVersionArgs.Arg0 = ARM_SMC_ID_MM_VERSION_AARCH32;
+
+ ArmCallSmc (&MmVersionArgs);
+
+ MmVersion = MmVersionArgs.Arg0;
+
+ if ((MM_MAJOR_VER(MmVersion) == MM_CALLER_MAJOR_VER) &&
+ (MM_MINOR_VER(MmVersion) >= MM_CALLER_MINOR_VER)) {
+ DEBUG ((DEBUG_INFO, "MM Version: Major=0x%x, Minor=0x%x\n",
+ MM_MAJOR_VER(MmVersion), MM_MINOR_VER(MmVersion)));
+ Status = EFI_SUCCESS;
+ } else {
+ DEBUG ((DEBUG_ERROR, "Incompatible MM Versions.\n Current Version: Major=0x%x, Minor=0x%x.\n Expected: Major=0x%x, Minor>=0x%x.\n",
+ MM_MAJOR_VER(MmVersion), MM_MINOR_VER(MmVersion), MM_CALLER_MAJOR_VER, MM_CALLER_MINOR_VER));
+ Status = EFI_UNSUPPORTED;
+ }
+
+ return Status;
+}
+
+STATIC EFI_GUID* CONST mGuidedEventGuid[] = {
+ &gEfiEndOfDxeEventGroupGuid,
+ &gEfiEventExitBootServicesGuid,
+ &gEfiEventReadyToBootGuid,
+};
+
+STATIC EFI_EVENT mGuidedEvent[ARRAY_SIZE (mGuidedEventGuid)];
+
+/**
+ Event notification that is fired when GUIDed Event Group is signaled.
+
+ @param Event The Event that is being processed, not used.
+ @param Context Event Context, not used.
+
+**/
+STATIC
+VOID
+EFIAPI
+MmGuidedEventNotify (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_MM_COMMUNICATE_HEADER Header;
+ UINTN Size;
+
+ //
+ // Use Guid to initialize EFI_SMM_COMMUNICATE_HEADER structure
+ //
+ CopyGuid (&Header.HeaderGuid, Context);
+ Header.MessageLength = 1;
+ Header.Data[0] = 0;
+
+ Size = sizeof (Header);
+ MmCommunication2Communicate (&mMmCommunication2, &Header, &Header, &Size);
+}
+
+/**
+ The Entry Point for MM Communication
+
+ This function installs the MM communication protocol interface and finds out
+ what type of buffer management will be required prior to invoking the
+ communication SMC.
+
+ @param ImageHandle The firmware allocated handle for the EFI image.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The entry point is executed successfully.
+ @retval Other Some error occurred when executing this entry point.
+
+**/
+EFI_STATUS
+EFIAPI
+MmCommunication2Initialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ UINTN Index;
+
+ // Check if we can make the MM call
+ Status = GetMmCompatibility ();
+ if (EFI_ERROR(Status)) {
+ goto ReturnErrorStatus;
+ }
+
+ mNsCommBuffMemRegion.PhysicalBase = PcdGet64 (PcdMmBufferBase);
+ // During boot , Virtual and Physical are same
+ mNsCommBuffMemRegion.VirtualBase = mNsCommBuffMemRegion.PhysicalBase;
+ mNsCommBuffMemRegion.Length = PcdGet64 (PcdMmBufferSize);
+
+ ASSERT (mNsCommBuffMemRegion.PhysicalBase != 0);
+
+ ASSERT (mNsCommBuffMemRegion.Length != 0);
+
+ Status = gDS->AddMemorySpace (
+ EfiGcdMemoryTypeReserved,
+ mNsCommBuffMemRegion.PhysicalBase,
+ mNsCommBuffMemRegion.Length,
+ EFI_MEMORY_WB |
+ EFI_MEMORY_XP |
+ EFI_MEMORY_RUNTIME
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "MmCommunicateInitialize: "
+ "Failed to add MM-NS Buffer Memory Space\n"));
+ goto ReturnErrorStatus;
+ }
+
+ Status = gDS->SetMemorySpaceAttributes (
+ mNsCommBuffMemRegion.PhysicalBase,
+ mNsCommBuffMemRegion.Length,
+ EFI_MEMORY_WB | EFI_MEMORY_XP | EFI_MEMORY_RUNTIME
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "MmCommunicateInitialize: "
+ "Failed to set MM-NS Buffer Memory attributes\n"));
+ goto CleanAddedMemorySpace;
+ }
+
+ // Install the communication protocol
+ Status = gBS->InstallProtocolInterface (
+ &mMmCommunicateHandle,
+ &gEfiMmCommunication2ProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &mMmCommunication2
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "MmCommunicationInitialize: "
+ "Failed to install MM communication protocol\n"));
+ goto CleanAddedMemorySpace;
+ }
+
+ // Register notification callback when virtual address is associated
+ // with the physical address.
+ // Create a Set Virtual Address Map event.
+ Status = gBS->CreateEvent (
+ EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE,
+ TPL_NOTIFY,
+ NotifySetVirtualAddressMap,
+ NULL,
+ &mSetVirtualAddressMapEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ for (Index = 0; Index < ARRAY_SIZE (mGuidedEventGuid); Index++) {
+ Status = gBS->CreateEventEx (EVT_NOTIFY_SIGNAL, TPL_CALLBACK,
+ MmGuidedEventNotify, mGuidedEventGuid[Index],
+ mGuidedEventGuid[Index], &mGuidedEvent[Index]);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ while (Index-- > 0) {
+ gBS->CloseEvent (mGuidedEvent[Index]);
+ }
+ goto UninstallProtocol;
+ }
+ }
+ return EFI_SUCCESS;
+
+UninstallProtocol:
+ gBS->UninstallProtocolInterface (
+ mMmCommunicateHandle,
+ &gEfiMmCommunication2ProtocolGuid,
+ &mMmCommunication2
+ );
+
+CleanAddedMemorySpace:
+ gDS->RemoveMemorySpace (
+ mNsCommBuffMemRegion.PhysicalBase,
+ mNsCommBuffMemRegion.Length
+ );
+
+ReturnErrorStatus:
+ return EFI_INVALID_PARAMETER;
+}
diff --git a/roms/edk2/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf b/roms/edk2/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf new file mode 100644 index 000000000..2465fb77c --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf @@ -0,0 +1,55 @@ +#/** @file
+#
+# DXE MM Communicate driver
+#
+# Copyright (c) 2016 - 2019, ARM Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = ArmMmCommunication
+ FILE_GUID = 09EE81D3-F15E-43F4-85B4-CB9873DA5D6B
+ MODULE_TYPE = DXE_RUNTIME_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = MmCommunication2Initialize
+
+#
+# The following is for reference only and not required by
+# build tools
+#
+# VALID_ARCHITECTURES = AARCH64
+#
+
+[Sources.AARCH64]
+ MmCommunication.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ ArmLib
+ ArmSmcLib
+ BaseMemoryLib
+ DebugLib
+ DxeServicesTableLib
+ HobLib
+ UefiDriverEntryPoint
+
+[Protocols]
+ gEfiMmCommunication2ProtocolGuid ## PRODUCES
+
+[Guids]
+ gEfiEndOfDxeEventGroupGuid
+ gEfiEventExitBootServicesGuid
+ gEfiEventReadyToBootGuid
+
+[Pcd.common]
+ gArmTokenSpaceGuid.PcdMmBufferBase
+ gArmTokenSpaceGuid.PcdMmBufferSize
+
+[Depex]
+ gEfiCpuArchProtocolGuid
diff --git a/roms/edk2/ArmPkg/Drivers/TimerDxe/TimerDxe.c b/roms/edk2/ArmPkg/Drivers/TimerDxe/TimerDxe.c new file mode 100644 index 000000000..dccaeae23 --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/TimerDxe/TimerDxe.c @@ -0,0 +1,428 @@ +/** @file
+ Timer Architecture Protocol driver of the ARM flavor
+
+ Copyright (c) 2011-2013 ARM Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include <PiDxe.h>
+
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/ArmGenericTimerCounterLib.h>
+
+#include <Protocol/Timer.h>
+#include <Protocol/HardwareInterrupt.h>
+
+// The notification function to call on every timer interrupt.
+EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL;
+EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
+
+// The current period of the timer interrupt
+UINT64 mTimerPeriod = 0;
+// The latest Timer Tick calculated for mTimerPeriod
+UINT64 mTimerTicks = 0;
+// Number of elapsed period since the last Timer interrupt
+UINT64 mElapsedPeriod = 1;
+
+// Cached copy of the Hardware Interrupt protocol instance
+EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL;
+
+/**
+ This function registers the handler NotifyFunction so it is called every time
+ the timer interrupt fires. It also passes the amount of time since the last
+ handler call to the NotifyFunction. If NotifyFunction is NULL, then the
+ handler is unregistered. If the handler is registered, then EFI_SUCCESS is
+ returned. If the CPU does not support registering a timer interrupt handler,
+ then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler
+ when a handler is already registered, then EFI_ALREADY_STARTED is returned.
+ If an attempt is made to unregister a handler when a handler is not registered,
+ then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to
+ register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
+ is returned.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param NotifyFunction The function to call when a timer interrupt fires. This
+ function executes at TPL_HIGH_LEVEL. The DXE Core will
+ register a handler for the timer interrupt, so it can know
+ how much time has passed. This information is used to
+ signal timer based events. NULL will unregister the handler.
+ @retval EFI_SUCCESS The timer handler was registered.
+ @retval EFI_UNSUPPORTED The platform does not support timer interrupts.
+ @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already
+ registered.
+ @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
+ previously registered.
+ @retval EFI_DEVICE_ERROR The timer handler could not be registered.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverRegisterHandler (
+ IN EFI_TIMER_ARCH_PROTOCOL *This,
+ IN EFI_TIMER_NOTIFY NotifyFunction
+ )
+{
+ if ((NotifyFunction == NULL) && (mTimerNotifyFunction == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((NotifyFunction != NULL) && (mTimerNotifyFunction != NULL)) {
+ return EFI_ALREADY_STARTED;
+ }
+
+ mTimerNotifyFunction = NotifyFunction;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Disable the timer
+**/
+VOID
+EFIAPI
+ExitBootServicesEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ ArmGenericTimerDisableTimer ();
+}
+
+/**
+
+ This function adjusts the period of timer interrupts to the value specified
+ by TimerPeriod. If the timer period is updated, then the selected timer
+ period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
+ If an error occurs while attempting to update the timer period, then the
+ timer hardware will be put back in its state prior to this call, and
+ EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
+ is disabled. This is not the same as disabling the CPU's interrupts.
+ Instead, it must either turn off the timer hardware, or it must adjust the
+ interrupt controller so that a CPU interrupt is not generated when the timer
+ interrupt fires.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is
+ returned. If the timer is programmable, then the timer period
+ will be rounded up to the nearest timer period that is supported
+ by the timer hardware. If TimerPeriod is set to 0, then the
+ timer interrupts will be disabled.
+
+
+ @retval EFI_SUCCESS The timer period was changed.
+ @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
+ @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverSetTimerPeriod (
+ IN EFI_TIMER_ARCH_PROTOCOL *This,
+ IN UINT64 TimerPeriod
+ )
+{
+ UINT64 CounterValue;
+ UINT64 TimerTicks;
+ EFI_TPL OriginalTPL;
+
+ // Always disable the timer
+ ArmGenericTimerDisableTimer ();
+
+ if (TimerPeriod != 0) {
+ // mTimerTicks = TimerPeriod in 1ms unit x Frequency.10^-3
+ // = TimerPeriod.10^-4 x Frequency.10^-3
+ // = (TimerPeriod x Frequency) x 10^-7
+ TimerTicks = MultU64x32 (TimerPeriod, ArmGenericTimerGetTimerFreq ());
+ TimerTicks = DivU64x32 (TimerTicks, 10000000U);
+
+ // Raise TPL to update the mTimerTicks and mTimerPeriod to ensure these values
+ // are coherent in the interrupt handler
+ OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+
+ mTimerTicks = TimerTicks;
+ mTimerPeriod = TimerPeriod;
+ mElapsedPeriod = 1;
+
+ gBS->RestoreTPL (OriginalTPL);
+
+ // Get value of the current timer
+ CounterValue = ArmGenericTimerGetSystemCount ();
+ // Set the interrupt in Current Time + mTimerTick
+ ArmGenericTimerSetCompareVal (CounterValue + mTimerTicks);
+
+ // Enable the timer
+ ArmGenericTimerEnableTimer ();
+ } else {
+ // Save the new timer period
+ mTimerPeriod = TimerPeriod;
+ // Reset the elapsed period
+ mElapsedPeriod = 1;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function retrieves the period of timer interrupts in 100 ns units,
+ returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
+ is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
+ returned, then the timer is currently disabled.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
+ 0 is returned, then the timer is currently disabled.
+
+
+ @retval EFI_SUCCESS The timer period was returned in TimerPeriod.
+ @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverGetTimerPeriod (
+ IN EFI_TIMER_ARCH_PROTOCOL *This,
+ OUT UINT64 *TimerPeriod
+ )
+{
+ if (TimerPeriod == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *TimerPeriod = mTimerPeriod;
+ return EFI_SUCCESS;
+}
+
+/**
+ This function generates a soft timer interrupt. If the platform does not support soft
+ timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
+ If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
+ service, then a soft timer interrupt will be generated. If the timer interrupt is
+ enabled when this service is called, then the registered handler will be invoked. The
+ registered handler should not be able to distinguish a hardware-generated timer
+ interrupt from a software-generated timer interrupt.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+
+ @retval EFI_SUCCESS The soft timer interrupt was generated.
+ @retval EFI_UNSUPPORTED The platform does not support the generation of soft timer interrupts.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverGenerateSoftInterrupt (
+ IN EFI_TIMER_ARCH_PROTOCOL *This
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Interface structure for the Timer Architectural Protocol.
+
+ @par Protocol Description:
+ This protocol provides the services to initialize a periodic timer
+ interrupt, and to register a handler that is called each time the timer
+ interrupt fires. It may also provide a service to adjust the rate of the
+ periodic timer interrupt. When a timer interrupt occurs, the handler is
+ passed the amount of time that has passed since the previous timer
+ interrupt.
+
+ @param RegisterHandler
+ Registers a handler that will be called each time the
+ timer interrupt fires. TimerPeriod defines the minimum
+ time between timer interrupts, so TimerPeriod will also
+ be the minimum time between calls to the registered
+ handler.
+
+ @param SetTimerPeriod
+ Sets the period of the timer interrupt in 100 nS units.
+ This function is optional, and may return EFI_UNSUPPORTED.
+ If this function is supported, then the timer period will
+ be rounded up to the nearest supported timer period.
+
+
+ @param GetTimerPeriod
+ Retrieves the period of the timer interrupt in 100 nS units.
+
+ @param GenerateSoftInterrupt
+ Generates a soft timer interrupt that simulates the firing of
+ the timer interrupt. This service can be used to invoke the registered handler if the timer interrupt has been masked for
+ a period of time.
+
+**/
+EFI_TIMER_ARCH_PROTOCOL gTimer = {
+ TimerDriverRegisterHandler,
+ TimerDriverSetTimerPeriod,
+ TimerDriverGetTimerPeriod,
+ TimerDriverGenerateSoftInterrupt
+};
+
+/**
+
+ C Interrupt Handler called in the interrupt context when Source interrupt is active.
+
+
+ @param Source Source of the interrupt. Hardware routing off a specific platform defines
+ what source means.
+
+ @param SystemContext Pointer to system register context. Mostly used by debuggers and will
+ update the system context after the return from the interrupt if
+ modified. Don't change these values unless you know what you are doing
+
+**/
+VOID
+EFIAPI
+TimerInterruptHandler (
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ )
+{
+ EFI_TPL OriginalTPL;
+ UINT64 CurrentValue;
+ UINT64 CompareValue;
+
+ //
+ // DXE core uses this callback for the EFI timer tick. The DXE core uses locks
+ // that raise to TPL_HIGH and then restore back to current level. Thus we need
+ // to make sure TPL level is set to TPL_HIGH while we are handling the timer tick.
+ //
+ OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+
+ // Signal end of interrupt early to help avoid losing subsequent ticks
+ // from long duration handlers
+ gInterrupt->EndOfInterrupt (gInterrupt, Source);
+
+ // Check if the timer interrupt is active
+ if ((ArmGenericTimerGetTimerCtrlReg () ) & ARM_ARCH_TIMER_ISTATUS) {
+
+ if (mTimerNotifyFunction) {
+ mTimerNotifyFunction (mTimerPeriod * mElapsedPeriod);
+ }
+
+ //
+ // Reload the Timer
+ //
+
+ // Get current counter value
+ CurrentValue = ArmGenericTimerGetSystemCount ();
+ // Get the counter value to compare with
+ CompareValue = ArmGenericTimerGetCompareVal ();
+
+ // This loop is needed in case we missed interrupts (eg: case when the interrupt handling
+ // has taken longer than mTickPeriod).
+ // Note: Physical Counter is counting up
+ mElapsedPeriod = 0;
+ do {
+ CompareValue += mTimerTicks;
+ mElapsedPeriod++;
+ } while (CompareValue < CurrentValue);
+
+ // Set next compare value
+ ArmGenericTimerSetCompareVal (CompareValue);
+ ArmGenericTimerReenableTimer ();
+ ArmInstructionSynchronizationBarrier ();
+ }
+
+ gBS->RestoreTPL (OriginalTPL);
+}
+
+
+/**
+ Initialize the state information for the Timer Architectural Protocol and
+ the Timer Debug support protocol that allows the debugger to break into a
+ running program.
+
+ @param ImageHandle of the loaded driver
+ @param SystemTable Pointer to the System Table
+
+ @retval EFI_SUCCESS Protocol registered
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
+ @retval EFI_DEVICE_ERROR Hardware problems
+
+**/
+EFI_STATUS
+EFIAPI
+TimerInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_HANDLE Handle = NULL;
+ EFI_STATUS Status;
+ UINTN TimerCtrlReg;
+ UINT32 TimerHypIntrNum;
+
+ if (ArmIsArchTimerImplemented () == 0) {
+ DEBUG ((DEBUG_ERROR, "ARM Architectural Timer is not available in the CPU, hence can't use this Driver \n"));
+ ASSERT (0);
+ }
+
+ // Find the interrupt controller protocol. ASSERT if not found.
+ Status = gBS->LocateProtocol (&gHardwareInterruptProtocolGuid, NULL, (VOID **)&gInterrupt);
+ ASSERT_EFI_ERROR (Status);
+
+ // Disable the timer
+ TimerCtrlReg = ArmGenericTimerGetTimerCtrlReg ();
+ TimerCtrlReg |= ARM_ARCH_TIMER_IMASK;
+ TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;
+ ArmGenericTimerSetTimerCtrlReg (TimerCtrlReg);
+ Status = TimerDriverSetTimerPeriod (&gTimer, 0);
+ ASSERT_EFI_ERROR (Status);
+
+ // Install secure and Non-secure interrupt handlers
+ // Note: Because it is not possible to determine the security state of the
+ // CPU dynamically, we just install interrupt handler for both sec and non-sec
+ // timer PPI
+ Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerVirtIntrNum), TimerInterruptHandler);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // The hypervisor timer interrupt may be omitted by implementations that
+ // execute under virtualization.
+ //
+ TimerHypIntrNum = PcdGet32 (PcdArmArchTimerHypIntrNum);
+ if (TimerHypIntrNum != 0) {
+ Status = gInterrupt->RegisterInterruptSource (gInterrupt, TimerHypIntrNum, TimerInterruptHandler);
+ ASSERT_EFI_ERROR (Status);
+ }
+
+ Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerSecIntrNum), TimerInterruptHandler);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerIntrNum), TimerInterruptHandler);
+ ASSERT_EFI_ERROR (Status);
+
+ // Set up default timer
+ Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod)); // TIMER_DEFAULT_PERIOD
+ ASSERT_EFI_ERROR (Status);
+
+ // Install the Timer Architectural Protocol onto a new handle
+ Status = gBS->InstallMultipleProtocolInterfaces(
+ &Handle,
+ &gEfiTimerArchProtocolGuid, &gTimer,
+ NULL
+ );
+ ASSERT_EFI_ERROR(Status);
+
+ // Everything is ready, unmask and enable timer interrupts
+ TimerCtrlReg = ARM_ARCH_TIMER_ENABLE;
+ ArmGenericTimerSetTimerCtrlReg (TimerCtrlReg);
+
+ // Register for an ExitBootServicesEvent
+ Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
diff --git a/roms/edk2/ArmPkg/Drivers/TimerDxe/TimerDxe.inf b/roms/edk2/ArmPkg/Drivers/TimerDxe/TimerDxe.inf new file mode 100644 index 000000000..8b2d4b0fa --- /dev/null +++ b/roms/edk2/ArmPkg/Drivers/TimerDxe/TimerDxe.inf @@ -0,0 +1,54 @@ +#/** @file
+#
+# Component description file for Timer DXE module
+#
+# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmTimerDxe
+ FILE_GUID = 49ea041e-6752-42ca-b0b1-7344fe2546b7
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = TimerInitialize
+
+[Sources.common]
+ TimerDxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+ ArmLib
+ BaseLib
+ UefiRuntimeServicesTableLib
+ UefiLib
+ UefiBootServicesTableLib
+ BaseMemoryLib
+ DebugLib
+ UefiDriverEntryPoint
+ IoLib
+ ArmGenericTimerCounterLib
+
+[Guids]
+
+[Protocols]
+ gEfiTimerArchProtocolGuid
+ gHardwareInterruptProtocolGuid
+
+[Pcd.common]
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+
+[Depex]
+ gHardwareInterruptProtocolGuid
|