diff options
| author |   Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
|---|---|---|
| committer | Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
| commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
| tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/edk2/ArmPkg/Library/ArmGicArchSecLib | |
| parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) | |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/edk2/ArmPkg/Library/ArmGicArchSecLib')
3 files changed, 117 insertions, 0 deletions
diff --git a/roms/edk2/ArmPkg/Library/ArmGicArchSecLib/AArch64/ArmGicArchLib.c b/roms/edk2/ArmPkg/Library/ArmGicArchSecLib/AArch64/ArmGicArchLib.c new file mode 100644 index 000000000..4f2479e70 --- /dev/null +++ b/roms/edk2/ArmPkg/Library/ArmGicArchSecLib/AArch64/ArmGicArchLib.c @@ -0,0 +1,45 @@ +/** @file
+*
+* Copyright (c) 2014, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Library/ArmLib.h>
+#include <Library/ArmGicLib.h>
+
+ARM_GIC_ARCH_REVISION
+EFIAPI
+ArmGicGetSupportedArchRevision (
+ VOID
+ )
+{
+ UINT32 IccSre;
+
+ // Ideally we would like to use the GICC IIDR Architecture version here, but
+ // this does not seem to be very reliable as the implementation could easily
+ // get it wrong. It is more reliable to check if the GICv3 System Register
+ // feature is implemented on the CPU. This is also convenient as our GICv3
+ // driver requires SRE. If only Memory mapped access is available we try to
+ // drive the GIC as a v2.
+ if (ArmReadIdPfr0 () & AARCH64_PFR0_GIC) {
+ // Make sure System Register access is enabled (SRE). This depends on the
+ // higher privilege level giving us permission, otherwise we will either
+ // cause an exception here, or the write doesn't stick in which case we need
+ // to fall back to the GICv2 MMIO interface.
+ // Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started
+ // at the same exception level.
+ // It is the OS responsibility to set this bit.
+ IccSre = ArmGicV3GetControlSystemRegisterEnable ();
+ if (!(IccSre & ICC_SRE_EL2_SRE)) {
+ ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE);
+ IccSre = ArmGicV3GetControlSystemRegisterEnable ();
+ }
+ if (IccSre & ICC_SRE_EL2_SRE) {
+ return ARM_GIC_ARCH_REVISION_3;
+ }
+ }
+
+ return ARM_GIC_ARCH_REVISION_2;
+}
diff --git a/roms/edk2/ArmPkg/Library/ArmGicArchSecLib/Arm/ArmGicArchLib.c b/roms/edk2/ArmPkg/Library/ArmGicArchSecLib/Arm/ArmGicArchLib.c new file mode 100644 index 000000000..8e1baeee2 --- /dev/null +++ b/roms/edk2/ArmPkg/Library/ArmGicArchSecLib/Arm/ArmGicArchLib.c @@ -0,0 +1,45 @@ +/** @file
+*
+* Copyright (c) 2014, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Library/ArmLib.h>
+#include <Library/ArmGicLib.h>
+
+ARM_GIC_ARCH_REVISION
+EFIAPI
+ArmGicGetSupportedArchRevision (
+ VOID
+ )
+{
+ UINT32 IccSre;
+
+ // Ideally we would like to use the GICC IIDR Architecture version here, but
+ // this does not seem to be very reliable as the implementation could easily
+ // get it wrong. It is more reliable to check if the GICv3 System Register
+ // feature is implemented on the CPU. This is also convenient as our GICv3
+ // driver requires SRE. If only Memory mapped access is available we try to
+ // drive the GIC as a v2.
+ if (ArmReadIdPfr1 () & ARM_PFR1_GIC) {
+ // Make sure System Register access is enabled (SRE). This depends on the
+ // higher privilege level giving us permission, otherwise we will either
+ // cause an exception here, or the write doesn't stick in which case we need
+ // to fall back to the GICv2 MMIO interface.
+ // Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started
+ // at the same exception level.
+ // It is the OS responsibility to set this bit.
+ IccSre = ArmGicV3GetControlSystemRegisterEnable ();
+ if (!(IccSre & ICC_SRE_EL2_SRE)) {
+ ArmGicV3SetControlSystemRegisterEnable (IccSre| ICC_SRE_EL2_SRE);
+ IccSre = ArmGicV3GetControlSystemRegisterEnable ();
+ }
+ if (IccSre & ICC_SRE_EL2_SRE) {
+ return ARM_GIC_ARCH_REVISION_3;
+ }
+ }
+
+ return ARM_GIC_ARCH_REVISION_2;
+}
diff --git a/roms/edk2/ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf b/roms/edk2/ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf new file mode 100644 index 000000000..1a1179a98 --- /dev/null +++ b/roms/edk2/ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf @@ -0,0 +1,27 @@ +#/* @file
+# Copyright (c) 2015, Linaro Ltd. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#*/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmGicArchSecLib
+ FILE_GUID = c1dd9745-9459-4e9a-9f5b-99cbd233c27d
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmGicArchLib|SEC
+
+[Sources.ARM]
+ Arm/ArmGicArchLib.c
+
+[Sources.AARCH64]
+ AArch64/ArmGicArchLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+
+[LibraryClasses]
+ ArmGicLib
|