diff options
| author |   Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
|---|---|---|
| committer | Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
| commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
| tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/edk2/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.h | |
| parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) | |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/edk2/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.h')
| -rw-r--r-- | roms/edk2/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/roms/edk2/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.h b/roms/edk2/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.h new file mode 100644 index 000000000..df711400e --- /dev/null +++ b/roms/edk2/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.h @@ -0,0 +1,42 @@ +/** @file
+*
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+
+#ifndef __SP805_WATCHDOG_H__
+#define __SP805_WATCHDOG_H__
+
+// SP805 Watchdog Registers
+#define SP805_WDOG_LOAD_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x000)
+#define SP805_WDOG_CURRENT_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x004)
+#define SP805_WDOG_CONTROL_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x008)
+#define SP805_WDOG_INT_CLR_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x00C)
+#define SP805_WDOG_RAW_INT_STS_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x010)
+#define SP805_WDOG_MSK_INT_STS_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x014)
+#define SP805_WDOG_LOCK_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xC00)
+
+#define SP805_WDOG_PERIPH_ID0 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE0)
+#define SP805_WDOG_PERIPH_ID1 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE4)
+#define SP805_WDOG_PERIPH_ID2 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE8)
+#define SP805_WDOG_PERIPH_ID3 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFEC)
+
+#define SP805_WDOG_PCELL_ID0 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF0)
+#define SP805_WDOG_PCELL_ID1 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF4)
+#define SP805_WDOG_PCELL_ID2 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF8)
+#define SP805_WDOG_PCELL_ID3 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFFC)
+
+// Timer control register bit definitions
+#define SP805_WDOG_CTRL_INTEN BIT0
+#define SP805_WDOG_CTRL_RESEN BIT1
+#define SP805_WDOG_RAW_INT_STS_WDOGRIS BIT0
+#define SP805_WDOG_MSK_INT_STS_WDOGMIS BIT0
+
+#define SP805_WDOG_LOCK_IS_UNLOCKED 0x00000000
+#define SP805_WDOG_LOCK_IS_LOCKED 0x00000001
+#define SP805_WDOG_SPECIAL_UNLOCK_CODE 0x1ACCE551
+
+#endif // __SP805_WATCHDOG_H__
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