diff options
| author |   Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
|---|---|---|
| committer | Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
| commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
| tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/edk2/ArmPlatformPkg/Library/HdLcd | |
| parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) | |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/edk2/ArmPlatformPkg/Library/HdLcd')
| -rw-r--r-- | roms/edk2/ArmPlatformPkg/Library/HdLcd/HdLcd.c | 174 | ||||
| -rw-r--r-- | roms/edk2/ArmPlatformPkg/Library/HdLcd/HdLcd.h | 84 | ||||
| -rw-r--r-- | roms/edk2/ArmPlatformPkg/Library/HdLcd/HdLcd.inf | 39 |
3 files changed, 297 insertions, 0 deletions
diff --git a/roms/edk2/ArmPlatformPkg/Library/HdLcd/HdLcd.c b/roms/edk2/ArmPlatformPkg/Library/HdLcd/HdLcd.c new file mode 100644 index 000000000..0247057e6 --- /dev/null +++ b/roms/edk2/ArmPlatformPkg/Library/HdLcd/HdLcd.c @@ -0,0 +1,174 @@ +/** @file
+ This file contains the platform independent parts of HdLcd
+
+ Copyright (c) 2011-2018, ARM Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/LcdHwLib.h>
+#include <Library/LcdPlatformLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+
+#include "HdLcd.h"
+
+#define BYTES_PER_PIXEL 4
+
+/** Initialize display.
+
+ @param[in] VramBaseAddress Address of the framebuffer.
+
+ @retval EFI_SUCCESS Display initialization successful.
+**/
+EFI_STATUS
+LcdInitialize (
+ IN EFI_PHYSICAL_ADDRESS VramBaseAddress
+ )
+{
+ // Disable the controller
+ MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE);
+
+ // Disable all interrupts
+ MmioWrite32 (HDLCD_REG_INT_MASK, 0);
+
+ // Define start of the VRAM. This never changes for any graphics mode
+ MmioWrite32 (HDLCD_REG_FB_BASE, (UINT32)VramBaseAddress);
+
+ // Setup various registers that never change
+ MmioWrite32 (HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8);
+
+ MmioWrite32 (HDLCD_REG_POLARITIES, HDLCD_DEFAULT_POLARITIES);
+
+ MmioWrite32 (
+ HDLCD_REG_PIXEL_FORMAT,
+ HDLCD_LITTLE_ENDIAN | HDLCD_4BYTES_PER_PIXEL
+ );
+
+ return EFI_SUCCESS;
+}
+
+/** Set requested mode of the display.
+
+ @param[in] ModeNumber Display mode number.
+
+ @retval EFI_SUCCESS Display mode set successfully.
+ @retval !(EFI_SUCCESS) Other errors.
+**/
+EFI_STATUS
+LcdSetMode (
+ IN UINT32 ModeNumber
+ )
+{
+ EFI_STATUS Status;
+ SCAN_TIMINGS *Horizontal;
+ SCAN_TIMINGS *Vertical;
+
+ EFI_GRAPHICS_PIXEL_FORMAT PixelFormat;
+
+ EFI_GRAPHICS_OUTPUT_MODE_INFORMATION ModeInfo;
+
+ // Set the video mode timings and other relevant information
+ Status = LcdPlatformGetTimings (
+ ModeNumber,
+ &Horizontal,
+ &Vertical
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ ASSERT (Horizontal != NULL);
+ ASSERT (Vertical != NULL);
+
+ // Get the pixel format information.
+ Status = LcdPlatformQueryMode (ModeNumber, &ModeInfo);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ // By default PcdArmHdLcdSwapBlueRedSelect is set to false
+ // However on the Juno platform HW lines for BLUE and RED are swapped
+ // Therefore PcdArmHdLcdSwapBlueRedSelect is set to TRUE for the Juno platform
+ PixelFormat = FixedPcdGetBool (PcdArmHdLcdSwapBlueRedSelect)
+ ? PixelRedGreenBlueReserved8BitPerColor
+ : PixelBlueGreenRedReserved8BitPerColor;
+
+ if (ModeInfo.PixelFormat == PixelFormat) {
+ MmioWrite32 (HDLCD_REG_RED_SELECT, (8 << 8) | 16);
+ MmioWrite32 (HDLCD_REG_BLUE_SELECT, (8 << 8) | 0);
+ } else {
+ MmioWrite32 (HDLCD_REG_BLUE_SELECT, (8 << 8) | 16);
+ MmioWrite32 (HDLCD_REG_RED_SELECT, (8 << 8) | 0);
+ }
+
+ MmioWrite32 (HDLCD_REG_GREEN_SELECT, (8 << 8) | 8);
+
+ // Disable the controller
+ MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE);
+
+ // Update the frame buffer information with the new settings
+ MmioWrite32 (
+ HDLCD_REG_FB_LINE_LENGTH,
+ Horizontal->Resolution * BYTES_PER_PIXEL
+ );
+
+ MmioWrite32 (
+ HDLCD_REG_FB_LINE_PITCH,
+ Horizontal->Resolution * BYTES_PER_PIXEL
+ );
+
+ MmioWrite32 (HDLCD_REG_FB_LINE_COUNT, Vertical->Resolution - 1);
+
+ // Set the vertical timing information
+ MmioWrite32 (HDLCD_REG_V_SYNC, Vertical->Sync);
+ MmioWrite32 (HDLCD_REG_V_BACK_PORCH, Vertical->BackPorch);
+ MmioWrite32 (HDLCD_REG_V_DATA, Vertical->Resolution - 1);
+ MmioWrite32 (HDLCD_REG_V_FRONT_PORCH, Vertical->FrontPorch);
+
+ // Set the horizontal timing information
+ MmioWrite32 (HDLCD_REG_H_SYNC, Horizontal->Sync);
+ MmioWrite32 (HDLCD_REG_H_BACK_PORCH, Horizontal->BackPorch);
+ MmioWrite32 (HDLCD_REG_H_DATA, Horizontal->Resolution - 1);
+ MmioWrite32 (HDLCD_REG_H_FRONT_PORCH, Horizontal->FrontPorch);
+
+ // Enable the controller
+ MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_ENABLE);
+
+ return EFI_SUCCESS;
+}
+
+/** De-initializes the display.
+**/
+VOID
+LcdShutdown (
+ VOID
+ )
+{
+ // Disable the controller
+ MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE);
+}
+
+/** Check for presence of HDLCD.
+
+ @retval EFI_SUCCESS Returns success if platform implements a HDLCD
+ controller.
+ @retval EFI_NOT_FOUND HDLCD display controller not found on the
+ platform.
+**/
+EFI_STATUS
+LcdIdentify (
+ VOID
+ )
+{
+ if ((MmioRead32 (HDLCD_REG_VERSION) >> 16) == HDLCD_PRODUCT_ID) {
+ return EFI_SUCCESS;
+ }
+
+ return EFI_NOT_FOUND;
+}
diff --git a/roms/edk2/ArmPlatformPkg/Library/HdLcd/HdLcd.h b/roms/edk2/ArmPlatformPkg/Library/HdLcd/HdLcd.h new file mode 100644 index 000000000..ca5c6676c --- /dev/null +++ b/roms/edk2/ArmPlatformPkg/Library/HdLcd/HdLcd.h @@ -0,0 +1,84 @@ +/** @file
+
+ Copyright (c) 2011-2018, ARM Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ **/
+
+#ifndef HDLCD_H_
+#define HDLCD_H_
+
+// HDLCD Controller Register Offsets
+#define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)
+#define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)
+#define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)
+#define HDLCD_REG_INT_MASK ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018)
+#define HDLCD_REG_INT_STATUS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C)
+#define HDLCD_REG_FB_BASE ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100)
+#define HDLCD_REG_FB_LINE_LENGTH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104)
+#define HDLCD_REG_FB_LINE_COUNT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108)
+#define HDLCD_REG_FB_LINE_PITCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C)
+#define HDLCD_REG_BUS_OPTIONS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110)
+#define HDLCD_REG_V_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200)
+#define HDLCD_REG_V_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204)
+#define HDLCD_REG_V_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208)
+#define HDLCD_REG_V_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C)
+#define HDLCD_REG_H_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210)
+#define HDLCD_REG_H_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214)
+#define HDLCD_REG_H_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218)
+#define HDLCD_REG_H_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C)
+#define HDLCD_REG_POLARITIES ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220)
+#define HDLCD_REG_COMMAND ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230)
+#define HDLCD_REG_PIXEL_FORMAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240)
+#define HDLCD_REG_RED_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244)
+#define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)
+#define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)
+
+// HDLCD Values of registers
+
+// HDLCD Interrupt mask, clear and status register
+#define HDLCD_DMA_END BIT0 /* DMA has finished reading a frame */
+#define HDLCD_BUS_ERROR BIT1 /* DMA bus error */
+#define HDLCD_SYNC BIT2 /* Vertical sync */
+#define HDLCD_UNDERRUN BIT3 /* No Data available while DATAEN active */
+
+// CLCD_CONTROL Control register
+#define HDLCD_DISABLE 0
+#define HDLCD_ENABLE BIT0
+
+// Bus Options
+#define HDLCD_BURST_1 BIT0
+#define HDLCD_BURST_2 BIT1
+#define HDLCD_BURST_4 BIT2
+#define HDLCD_BURST_8 BIT3
+#define HDLCD_BURST_16 BIT4
+
+// Polarities - HIGH
+#define HDLCD_VSYNC_HIGH BIT0
+#define HDLCD_HSYNC_HIGH BIT1
+#define HDLCD_DATEN_HIGH BIT2
+#define HDLCD_DATA_HIGH BIT3
+#define HDLCD_PXCLK_HIGH BIT4
+// Polarities - LOW (for completion and for ease of understanding the hardware settings)
+#define HDLCD_VSYNC_LOW 0
+#define HDLCD_HSYNC_LOW 0
+#define HDLCD_DATEN_LOW 0
+#define HDLCD_DATA_LOW 0
+#define HDLCD_PXCLK_LOW 0
+
+// Default polarities
+#define HDLCD_DEFAULT_POLARITIES (HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | \
+ HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW | \
+ HDLCD_VSYNC_HIGH)
+
+// Pixel Format
+#define HDLCD_LITTLE_ENDIAN (0 << 31)
+#define HDLCD_BIG_ENDIAN (1 << 31)
+
+// Number of bytes per pixel
+#define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3)
+
+#define HDLCD_PRODUCT_ID 0x1CDC
+
+#endif /* HDLCD_H_ */
diff --git a/roms/edk2/ArmPlatformPkg/Library/HdLcd/HdLcd.inf b/roms/edk2/ArmPlatformPkg/Library/HdLcd/HdLcd.inf new file mode 100644 index 000000000..bc80e1ade --- /dev/null +++ b/roms/edk2/ArmPlatformPkg/Library/HdLcd/HdLcd.inf @@ -0,0 +1,39 @@ +#/** @file
+#
+# Component description file for HDLCD module
+#
+# Copyright (c) 2011-2018, ARM Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = HdLcd
+ FILE_GUID = ce660500-824d-11e0-ac72-0002a5d5c51b
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = LcdHwLib
+
+[Sources.common]
+ HdLcd.h
+ HdLcd.c
+
+[Packages]
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ ArmPkg/ArmPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ ArmLib
+ UefiLib
+ BaseLib
+ DebugLib
+ IoLib
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase
+ gArmPlatformTokenSpaceGuid.PcdArmHdLcdSwapBlueRedSelect
+
|