diff options
| author |   Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
|---|---|---|
| committer | Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
| commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
| tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/edk2/ArmPlatformPkg/PrePeiCore/PrePeiCore.h | |
| parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) | |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/edk2/ArmPlatformPkg/PrePeiCore/PrePeiCore.h')
| -rw-r--r-- | roms/edk2/ArmPlatformPkg/PrePeiCore/PrePeiCore.h | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/roms/edk2/ArmPlatformPkg/PrePeiCore/PrePeiCore.h b/roms/edk2/ArmPlatformPkg/PrePeiCore/PrePeiCore.h new file mode 100644 index 000000000..7140c7f5b --- /dev/null +++ b/roms/edk2/ArmPlatformPkg/PrePeiCore/PrePeiCore.h @@ -0,0 +1,72 @@ +/** @file
+* Main file supporting the transition to PEI Core in Normal World for Versatile Express
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#ifndef __PREPEICORE_H_
+#define __PREPEICORE_H_
+
+#include <Library/ArmLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+
+#include <PiPei.h>
+#include <Ppi/TemporaryRamSupport.h>
+
+VOID
+CreatePpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ );
+
+EFI_STATUS
+EFIAPI
+PrePeiCoreTemporaryRamSupport (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
+ IN UINTN CopySize
+ );
+
+VOID
+SecSwitchStack (
+ INTN StackDelta
+ );
+
+// Vector Table for Pei Phase
+VOID PeiVectorTable (VOID);
+
+VOID
+EFIAPI
+PrimaryMain (
+ IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
+ );
+
+/*
+ * This is the main function for secondary cores. They loop around until a non Null value is written to
+ * SYS_FLAGS register.The SYS_FLAGS register is platform specific.
+ * Note:The secondary cores, while executing secondary_main, assumes that:
+ * : SGI 0 is configured as Non-secure interrupt
+ * : Priority Mask is configured to allow SGI 0
+ * : Interrupt Distributor and CPU interfaces are enabled
+ *
+ */
+VOID
+EFIAPI
+SecondaryMain (
+ IN UINTN MpId
+ );
+
+VOID
+PeiCommonExceptionEntry (
+ IN UINT32 Entry,
+ IN UINTN LR
+ );
+
+#endif
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