Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

5 files changed, 366 insertions, 0 deletions

diff --git a/roms/edk2/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.c b/roms/edk2/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.c
new file mode 100644
index 000000000..3aa11f8ee
--- /dev/null
+++ b/roms/edk2/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.c
@@ -0,0 +1,206 @@
+/** @file

+  SdMmcPciHcPei driver is used to provide platform-dependent info, mainly SD/MMC

+  host controller MMIO base, to upper layer SD/MMC drivers.

+

+  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+

+**/

+

+#include "SdMmcPciHcPei.h"

+

+EDKII_SD_MMC_HOST_CONTROLLER_PPI  mSdMmcHostControllerPpi = { GetSdMmcHcMmioBar };

+

+EFI_PEI_PPI_DESCRIPTOR   mPpiList = {

+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),

+  &gEdkiiPeiSdMmcHostControllerPpiGuid,

+  &mSdMmcHostControllerPpi

+};

+

+/**

+  Get the MMIO base address of SD/MMC host controller.

+

+  @param[in]     This            The protocol instance pointer.

+  @param[in]     ControllerId    The ID of the SD/MMC host controller.

+  @param[in,out] MmioBar         The pointer to store the array of available

+                                 SD/MMC host controller slot MMIO base addresses.

+                                 The entry number of the array is specified by BarNum.

+  @param[out]    BarNum          The pointer to store the supported bar number.

+

+  @retval EFI_SUCCESS            The operation succeeds.

+  @retval EFI_INVALID_PARAMETER  The parameters are invalid.

+

+**/

+EFI_STATUS

+EFIAPI

+GetSdMmcHcMmioBar (

+  IN     EDKII_SD_MMC_HOST_CONTROLLER_PPI *This,

+  IN     UINT8                            ControllerId,

+  IN OUT UINTN                            **MmioBar,

+     OUT UINT8                            *BarNum

+  )

+{

+  SD_MMC_HC_PEI_PRIVATE_DATA  *Private;

+

+  if ((This == NULL) || (MmioBar == NULL) || (BarNum == NULL)) {

+    return EFI_INVALID_PARAMETER;

+  }

+

+  Private = SD_MMC_HC_PEI_PRIVATE_DATA_FROM_THIS (This);

+

+  if (ControllerId >= Private->TotalSdMmcHcs) {

+    return EFI_INVALID_PARAMETER;

+  }

+

+  *MmioBar = &Private->MmioBar[ControllerId].MmioBarAddr[0];

+  *BarNum  = (UINT8)Private->MmioBar[ControllerId].SlotNum;

+  return EFI_SUCCESS;

+}

+

+/**

+  The user code starts with this function.

+

+  @param  FileHandle             Handle of the file being invoked.

+  @param  PeiServices            Describes the list of possible PEI Services.

+

+  @retval EFI_SUCCESS            The driver is successfully initialized.

+  @retval Others                 Can't initialize the driver.

+

+**/

+EFI_STATUS

+EFIAPI

+InitializeSdMmcHcPeim (

+  IN EFI_PEI_FILE_HANDLE       FileHandle,

+  IN CONST EFI_PEI_SERVICES    **PeiServices

+  )

+{

+  EFI_BOOT_MODE                BootMode;

+  EFI_STATUS                   Status;

+  UINT16                       Bus;

+  UINT16                       Device;

+  UINT16                       Function;

+  UINT32                       Size;

+  UINT64                       MmioSize;

+  UINT8                        SubClass;

+  UINT8                        BaseClass;

+  UINT8                        SlotInfo;

+  UINT8                        SlotNum;

+  UINT8                        FirstBar;

+  UINT8                        Index;

+  UINT8                        Slot;

+  UINT32                       BarAddr;

+  SD_MMC_HC_PEI_PRIVATE_DATA   *Private;

+

+  //

+  // Shadow this PEIM to run from memory

+  //

+  if (!EFI_ERROR (PeiServicesRegisterForShadow (FileHandle))) {

+    return EFI_SUCCESS;

+  }

+

+  Status = PeiServicesGetBootMode (&BootMode);

+  ///

+  /// We do not expose this in S3 boot path, because it is only for recovery.

+  ///

+  if (BootMode == BOOT_ON_S3_RESUME) {

+    return EFI_SUCCESS;

+  }

+

+  Private = (SD_MMC_HC_PEI_PRIVATE_DATA *) AllocateZeroPool (sizeof (SD_MMC_HC_PEI_PRIVATE_DATA));

+  if (Private == NULL) {

+    DEBUG ((EFI_D_ERROR, "Failed to allocate memory for SD_MMC_HC_PEI_PRIVATE_DATA! \n"));

+    return EFI_OUT_OF_RESOURCES;

+  }

+

+  Private->Signature              = SD_MMC_HC_PEI_SIGNATURE;

+  Private->SdMmcHostControllerPpi = mSdMmcHostControllerPpi;

+  Private->PpiList                = mPpiList;

+  Private->PpiList.Ppi            = &Private->SdMmcHostControllerPpi;

+

+  BarAddr = PcdGet32 (PcdSdMmcPciHostControllerMmioBase);

+  for (Bus = 0; Bus < 256; Bus++) {

+    for (Device = 0; Device < 32; Device++) {

+      for (Function = 0; Function < 8; Function++) {

+        SubClass  = PciRead8 (PCI_LIB_ADDRESS (Bus, Device, Function, 0x0A));

+        BaseClass = PciRead8 (PCI_LIB_ADDRESS (Bus, Device, Function, 0x0B));

+

+        if ((SubClass == PCI_SUBCLASS_SD_HOST_CONTROLLER) && (BaseClass == PCI_CLASS_SYSTEM_PERIPHERAL)) {

+          //

+          // Get the SD/MMC Pci host controller's Slot Info.

+          //

+          SlotInfo = PciRead8 (PCI_LIB_ADDRESS (Bus, Device, Function, SD_MMC_HC_PEI_SLOT_OFFSET));

+          FirstBar = (*(SD_MMC_HC_PEI_SLOT_INFO*)&SlotInfo).FirstBar;

+          SlotNum  = (*(SD_MMC_HC_PEI_SLOT_INFO*)&SlotInfo).SlotNum + 1;

+          ASSERT ((FirstBar + SlotNum) < MAX_SD_MMC_SLOTS);

+

+          for (Index = 0, Slot = FirstBar; Slot < (FirstBar + SlotNum); Index++, Slot++) {

+            //

+            // Get the SD/MMC Pci host controller's MMIO region size.

+            //

+            PciAnd16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), (UINT16)~(EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE));

+            PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4 * Slot), 0xFFFFFFFF);

+            Size = PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4 * Slot));

+

+            switch (Size & 0x07) {

+              case 0x0:

+                //

+                // Memory space: anywhere in 32 bit address space

+                //

+                MmioSize = (~(Size & 0xFFFFFFF0)) + 1;

+                break;

+              case 0x4:

+                //

+                // Memory space: anywhere in 64 bit address space

+                //

+                MmioSize = Size & 0xFFFFFFF0;

+                PciWrite32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4), 0xFFFFFFFF);

+                Size = PciRead32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4));

+                //

+                // Fix the length to support some spefic 64 bit BAR

+                //

+                Size |= ((UINT32)(-1) << HighBitSet32 (Size));

+                //

+                // Calculate the size of 64bit bar

+                //

+                MmioSize  |= LShiftU64 ((UINT64) Size, 32);

+                MmioSize  = (~(MmioSize)) + 1;

+                //

+                // Clean the high 32bits of this 64bit BAR to 0 as we only allow a 32bit BAR.

+                //

+                PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4 * Slot + 4), 0);

+                break;

+              default:

+                //

+                // Unknown BAR type

+                //

+                ASSERT (FALSE);

+                continue;

+            };

+            //

+            // Assign resource to the SdMmc Pci host controller's MMIO BAR.

+            // Enable the SdMmc Pci host controller by setting BME and MSE bits of PCI_CMD register.

+            //

+            PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4 * Slot), BarAddr);

+            PciOr16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), (EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE));

+            //

+            // Record the allocated Mmio base address.

+            //

+            Private->MmioBar[Private->TotalSdMmcHcs].SlotNum++;

+            Private->MmioBar[Private->TotalSdMmcHcs].MmioBarAddr[Index] = BarAddr;

+            BarAddr += (UINT32)MmioSize;

+          }

+          Private->TotalSdMmcHcs++;

+          ASSERT (Private->TotalSdMmcHcs < MAX_SD_MMC_HCS);

+        }

+      }

+    }

+  }

+

+  ///

+  /// Install SdMmc Host Controller PPI

+  ///

+  Status = PeiServicesInstallPpi (&Private->PpiList);

+

+  ASSERT_EFI_ERROR (Status);

+  return Status;

+}

diff --git a/roms/edk2/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.h b/roms/edk2/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.h
new file mode 100644
index 000000000..ee04a6b89
--- /dev/null
+++ b/roms/edk2/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.h
@@ -0,0 +1,80 @@
+/** @file

+

+  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+

+**/

+

+#ifndef _SD_MMC_PCI_HOST_CONTROLLER_PEI_H_

+#define _SD_MMC_PCI_HOST_CONTROLLER_PEI_H_

+

+#include <PiPei.h>

+

+#include <Ppi/MasterBootMode.h>

+#include <Ppi/SdMmcHostController.h>

+

+#include <IndustryStandard/Pci.h>

+

+#include <Library/DebugLib.h>

+#include <Library/BaseLib.h>

+#include <Library/BaseMemoryLib.h>

+#include <Library/PciLib.h>

+#include <Library/PeiServicesLib.h>

+#include <Library/MemoryAllocationLib.h>

+

+#define SD_MMC_HC_PEI_SIGNATURE    SIGNATURE_32 ('S', 'D', 'M', 'C')

+

+#define MAX_SD_MMC_HCS             8

+#define MAX_SD_MMC_SLOTS           6

+

+//

+// SD Host Controller SlotInfo Register Offset

+//

+#define SD_MMC_HC_PEI_SLOT_OFFSET  0x40

+

+typedef struct {

+  UINT8    FirstBar:3;        // bit 0:2

+  UINT8    Reserved:1;        // bit 3

+  UINT8    SlotNum:3;         // bit 4:6

+  UINT8    Reserved1:1;       // bit 7

+} SD_MMC_HC_PEI_SLOT_INFO;

+

+typedef struct {

+  UINTN                            SlotNum;

+  UINTN                            MmioBarAddr[MAX_SD_MMC_SLOTS];

+} SD_MMC_HC_PEI_BAR;

+

+typedef struct {

+  UINTN                            Signature;

+  EDKII_SD_MMC_HOST_CONTROLLER_PPI SdMmcHostControllerPpi;

+  EFI_PEI_PPI_DESCRIPTOR           PpiList;

+  UINTN                            TotalSdMmcHcs;

+  SD_MMC_HC_PEI_BAR                MmioBar[MAX_SD_MMC_HCS];

+} SD_MMC_HC_PEI_PRIVATE_DATA;

+

+#define SD_MMC_HC_PEI_PRIVATE_DATA_FROM_THIS(a)  CR (a, SD_MMC_HC_PEI_PRIVATE_DATA, SdMmcHostControllerPpi, SD_MMC_HC_PEI_SIGNATURE)

+

+/**

+  Get the MMIO base address of SD/MMC host controller.

+

+  @param[in]     This            The protocol instance pointer.

+  @param[in]     ControllerId    The ID of the SD/MMC host controller.

+  @param[in,out] MmioBar         The pointer to store the array of available

+                                 SD/MMC host controller slot MMIO base addresses.

+                                 The entry number of the array is specified by BarNum.

+  @param[out]    BarNum          The pointer to store the supported bar number.

+

+  @retval EFI_SUCCESS            The operation succeeds.

+  @retval EFI_INVALID_PARAMETER  The parameters are invalid.

+

+**/

+EFI_STATUS

+EFIAPI

+GetSdMmcHcMmioBar (

+  IN     EDKII_SD_MMC_HOST_CONTROLLER_PPI *This,

+  IN     UINT8                            ControllerId,

+  IN OUT UINTN                            **MmioBar,

+     OUT UINT8                            *BarNum

+  );

+

+#endif

diff --git a/roms/edk2/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.inf b/roms/edk2/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.inf
new file mode 100644
index 000000000..687905530
--- /dev/null
+++ b/roms/edk2/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.inf
@@ -0,0 +1,51 @@
+## @file

+#  Component Description File For SD/MMC Pci Host Controller Pei Module.

+#

+#  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>

+#

+#  SPDX-License-Identifier: BSD-2-Clause-Patent

+#

+##

+

+[Defines]

+  INF_VERSION                    = 0x00010005

+  BASE_NAME                      = SdMmcPciHcPei

+  MODULE_UNI_FILE                = SdMmcPciHcPei.uni

+  FILE_GUID                      = 1BB737EF-427A-4144-8B3B-B76EF38515E6

+  MODULE_TYPE                    = PEIM

+  VERSION_STRING                 = 1.0

+

+  ENTRY_POINT                    = InitializeSdMmcHcPeim

+

+#

+# The following information is for reference only and not required by the build tools.

+#

+#  VALID_ARCHITECTURES           = IA32 X64 EBC

+#

+

+[Sources]

+  SdMmcPciHcPei.c

+  SdMmcPciHcPei.h

+

+[Packages]

+  MdePkg/MdePkg.dec

+  MdeModulePkg/MdeModulePkg.dec

+

+[LibraryClasses]

+  PciLib

+  DebugLib

+  PeiServicesLib

+  MemoryAllocationLib

+  PeimEntryPoint

+

+[Pcd]

+  gEfiMdeModulePkgTokenSpaceGuid.PcdSdMmcPciHostControllerMmioBase   ## CONSUMES

+

+[Ppis]

+  gEdkiiPeiSdMmcHostControllerPpiGuid         ## PRODUCES

+

+[Depex]

+  gEfiPeiMasterBootModePpiGuid AND gEfiPeiMemoryDiscoveredPpiGuid

+

+[UserExtensions.TianoCore."ExtraFiles"]

+  SdMmcPciHcPeiExtra.uni

diff --git a/roms/edk2/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.uni b/roms/edk2/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.uni
new file mode 100644
index 000000000..bc2768648
--- /dev/null
+++ b/roms/edk2/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPei.uni
@@ -0,0 +1,15 @@
+// /** @file

+// The SdMmcPciHcPei driver is used by upper layer to retrieve mmio base address

+// of managed pci-based SD/MMC host controller at PEI phase.

+//

+// Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>

+//

+// SPDX-License-Identifier: BSD-2-Clause-Patent

+//

+// **/

+

+

+#string STR_MODULE_ABSTRACT             #language en-US "Providing interface for upper layer to retrieve mmio base address of managed pci-based SD/MMC host controller at PEI phase."

+

+#string STR_MODULE_DESCRIPTION          #language en-US "It implements the interface of getting mmio base address of managed pci-based SD/MMC host controller at PEI phase."

+

diff --git a/roms/edk2/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPeiExtra.uni b/roms/edk2/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPeiExtra.uni
new file mode 100644
index 000000000..9118ac3cd
--- /dev/null
+++ b/roms/edk2/MdeModulePkg/Bus/Pci/SdMmcPciHcPei/SdMmcPciHcPeiExtra.uni
@@ -0,0 +1,14 @@
+// /** @file

+// SdMmcPciHcPei Localized Strings and Content

+//

+// Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>

+//

+// SPDX-License-Identifier: BSD-2-Clause-Patent

+//

+// **/

+

+#string STR_PROPERTIES_MODULE_NAME

+#language en-US

+"SD/MMC PCI-Based HC Module for Recovery"

+

+