diff options
| author |   Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
|---|---|---|
| committer | Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
| commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
| tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/edk2/MdePkg/Library/BaseCpuLib | |
| parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) | |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/edk2/MdePkg/Library/BaseCpuLib')
20 files changed, 649 insertions, 0 deletions
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.S b/roms/edk2/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.S new file mode 100644 index 000000000..82a723226 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.S @@ -0,0 +1,32 @@ +#------------------------------------------------------------------------------
+#
+# CpuFlushTlb() for ARM
+#
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(CpuFlushTlb)
+
+#/**
+# Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+#
+# Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+#
+#**/
+#VOID
+#EFIAPI
+#CpuFlushTlb (
+# VOID
+# )#
+#
+ASM_PFX(CpuFlushTlb):
+ tlbi vmalle1 // Invalidate Inst TLB and Data TLB
+ dsb sy
+ isb
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.asm b/roms/edk2/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.asm new file mode 100644 index 000000000..a72c9aef1 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.asm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; CpuFlushTlb() for ARM
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT CpuFlushTlb
+ AREA BaseCpuLib_LowLevel, CODE, READONLY
+
+;/**
+; Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+;
+; Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+;
+;**/
+;VOID
+;EFIAPI
+;CpuFlushTlb (
+; VOID
+; );
+;
+CpuFlushTlb
+ tlbi vmalle1 // Invalidate Inst TLB and Data TLB
+ dsb sy
+ isb
+ ret
+
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.S b/roms/edk2/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.S new file mode 100644 index 000000000..410a27156 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.S @@ -0,0 +1,33 @@ +#------------------------------------------------------------------------------
+#
+# CpuSleep() for AArch64
+#
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2013, ARM LTD. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.align 3
+GCC_ASM_EXPORT(CpuSleep)
+
+#/**
+# Places the CPU in a sleep state until an interrupt is received.
+#
+# Places the CPU in a sleep state until an interrupt is received. If interrupts
+# are disabled prior to calling this function, then the CPU will be placed in a
+# sleep state indefinitely.
+#
+#**/
+#VOID
+#EFIAPI
+#CpuSleep (
+# VOID
+# );
+#
+
+ASM_PFX(CpuSleep):
+ wfi
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.asm b/roms/edk2/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.asm new file mode 100644 index 000000000..c6e4d7e65 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.asm @@ -0,0 +1,34 @@ +;------------------------------------------------------------------------------
+;
+; CpuSleep() for AArch64
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM LTD. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT CpuSleep
+ AREA BaseCpuLib_LowLevel, CODE, READONLY
+
+;/**
+; Places the CPU in a sleep state until an interrupt is received.
+;
+; Places the CPU in a sleep state until an interrupt is received. If interrupts
+; are disabled prior to calling this function, then the CPU will be placed in a
+; sleep state indefinitely.
+;
+;**/
+;VOID
+;EFIAPI
+;CpuSleep (
+; VOID
+; );
+;
+
+CpuSleep
+ wfi
+ ret
+
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.S b/roms/edk2/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.S new file mode 100644 index 000000000..3bafce6f3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.S @@ -0,0 +1,30 @@ +#------------------------------------------------------------------------------
+#
+# CpuFlushTlb() for ARM
+#
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(CpuFlushTlb)
+
+#/**
+# Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+#
+# Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+#
+#**/
+#VOID
+#EFIAPI
+#CpuFlushTlb (
+# VOID
+# )#
+#
+ASM_PFX(CpuFlushTlb):
+ mov r0,#0
+ mcr p15,0,r0,c8,c5,0 // Invalidate all the unlocked entried in TLB
+ bx LR
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.asm b/roms/edk2/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.asm new file mode 100644 index 000000000..1f77fc7d5 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.asm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; CpuFlushTlb() for ARM
+;
+; Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT CpuFlushTlb
+ AREA cpu_flush_tlb, CODE, READONLY
+
+;/**
+; Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+;
+; Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+;
+;**/
+;VOID
+;EFIAPI
+;CpuFlushTlb (
+; VOID
+; );
+;
+CpuFlushTlb
+ MOV r0,#0
+ MCR p15,0,r0,c8,c5,0 ;Invalidate all the unlocked entried in TLB
+ BX LR
+
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.S b/roms/edk2/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.S new file mode 100644 index 000000000..e2b734900 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.S @@ -0,0 +1,37 @@ +#------------------------------------------------------------------------------
+#
+# CpuSleep() for ARMv7
+#
+# ARMv6 versions was:
+# MOV r0,#0
+# MCR p15,0,r0,c7,c0,4 ;Wait for Interrupt instruction
+#
+# But this is a no-op on ARMv7
+#
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(CpuSleep)
+
+#/**
+# Places the CPU in a sleep state until an interrupt is received.
+#
+# Places the CPU in a sleep state until an interrupt is received. If interrupts
+# are disabled prior to calling this function, then the CPU will be placed in a
+# sleep state indefinitely.
+#
+#**/
+#VOID
+#EFIAPI
+#CpuSleep (
+# VOID
+# );
+#
+ASM_PFX(CpuSleep):
+ wfi
+ bx lr
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm b/roms/edk2/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm new file mode 100644 index 000000000..ae32705a6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm @@ -0,0 +1,38 @@ +;------------------------------------------------------------------------------
+;
+; CpuSleep() for ARMv7
+;
+; ARMv6 versions was:
+; MOV r0,#0
+; MCR p15,0,r0,c7,c0,4 ;Wait for Interrupt instruction
+;
+; But this is a no-op on ARMv7
+;
+; Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2011, Apple Inc. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT CpuSleep
+ AREA cpu_sleep, CODE, READONLY
+
+;/**
+; Places the CPU in a sleep state until an interrupt is received.
+;
+; Places the CPU in a sleep state until an interrupt is received. If interrupts
+; are disabled prior to calling this function, then the CPU will be placed in a
+; sleep state indefinitely.
+;
+;**/
+;VOID
+;EFIAPI
+;CpuSleep (
+; VOID
+; );
+;
+CpuSleep
+ WFI
+ BX LR
+
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/roms/edk2/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf new file mode 100644 index 000000000..950f5229b --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf @@ -0,0 +1,69 @@ +## @file
+# Instance of CPU Library for various architecture.
+#
+# CPU Library implemented using ASM functions for IA32, X64, ARM, AARCH64,
+# PAL CALLs for IPF, and empty functions for EBC.
+#
+# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseCpuLib
+ MODULE_UNI_FILE = BaseCpuLib.uni
+ FILE_GUID = 4FBD2538-249C-4b50-8F4A-A9E66609CBF6
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = CpuLib
+
+
+#
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
+#
+
+[Sources.IA32]
+ Ia32/CpuSleep.c | MSFT
+ Ia32/CpuFlushTlb.c | MSFT
+
+ Ia32/CpuSleep.nasm| INTEL
+ Ia32/CpuFlushTlb.nasm| INTEL
+
+ Ia32/CpuSleepGcc.c | GCC
+ Ia32/CpuFlushTlbGcc.c | GCC
+
+[Sources.X64]
+ X64/CpuFlushTlb.nasm
+ X64/CpuSleep.nasm
+
+
+[Sources.EBC]
+ Ebc/CpuSleepFlushTlb.c
+
+[Sources.ARM]
+ Arm/CpuFlushTlb.asm | RVCT
+ Arm/CpuSleep.asm | RVCT
+ Arm/CpuFlushTlb.asm | MSFT
+ Arm/CpuSleep.asm | MSFT
+ Arm/CpuFlushTlb.S | GCC
+ Arm/CpuSleep.S | GCC
+
+[Sources.AARCH64]
+ AArch64/CpuFlushTlb.S | GCC
+ AArch64/CpuSleep.S | GCC
+ AArch64/CpuFlushTlb.asm | MSFT
+ AArch64/CpuSleep.asm | MSFT
+
+[Sources.RISCV64]
+ RiscV/Cpu.S
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni b/roms/edk2/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni new file mode 100644 index 000000000..80dc49578 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni @@ -0,0 +1,20 @@ +// /** @file
+// Instance of CPU Library for various architecture.
+//
+// CPU Library implemented using ASM functions for IA-32, X64 and RISCV64,
+// PAL CALLs for IPF, and empty functions for EBC.
+//
+// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
+// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+// Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Instance of CPU Library for various architectures"
+
+#string STR_MODULE_DESCRIPTION #language en-US "CPU Library implemented using ASM functions for IA-32, X64 and RISCV64, PAL CALLs for IPF, and empty functions for EBC."
+
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/Ebc/CpuSleepFlushTlb.c b/roms/edk2/MdePkg/Library/BaseCpuLib/Ebc/CpuSleepFlushTlb.c new file mode 100644 index 000000000..77e0ef605 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/Ebc/CpuSleepFlushTlb.c @@ -0,0 +1,40 @@ +/** @file
+ Base Library CPU Functions for EBC
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include <Base.h>
+#include <Library/DebugLib.h>
+
+/**
+ Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+
+ Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+
+**/
+VOID
+EFIAPI
+CpuFlushTlb (
+ VOID
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Places the CPU in a sleep state until an interrupt is received.
+
+ Places the CPU in a sleep state until an interrupt is received. If interrupts
+ are disabled prior to calling this function, then the CPU will be placed in a
+ sleep state indefinitely.
+
+**/
+VOID
+EFIAPI
+CpuSleep (
+ VOID
+ )
+{
+}
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlb.c b/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlb.c new file mode 100644 index 000000000..89341c2f0 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlb.c @@ -0,0 +1,28 @@ +/** @file
+ CpuFlushTlb function.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+/**
+ Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+
+ Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+
+**/
+VOID
+EFIAPI
+CpuFlushTlb (
+ VOID
+ )
+{
+ _asm {
+ mov eax, cr3
+ mov cr3, eax
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlb.nasm b/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlb.nasm new file mode 100644 index 000000000..bc3b68e3f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlb.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ ;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; CpuFlushTlb.Asm
+;
+; Abstract:
+;
+; CpuFlushTlb function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; CpuFlushTlb (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(CpuFlushTlb)
+ASM_PFX(CpuFlushTlb):
+ mov eax, cr3
+ mov cr3, eax ; moving to CR3 flushes TLB
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlbGcc.c b/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlbGcc.c new file mode 100644 index 000000000..15d414992 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuFlushTlbGcc.c @@ -0,0 +1,26 @@ +/** @file
+ CpuFlushTlb function for Ia32/X64 GCC.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/BaseLib.h>
+
+/**
+ Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+
+ Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+
+**/
+VOID
+EFIAPI
+CpuFlushTlb (
+ VOID
+ )
+{
+ AsmWriteCr3 (AsmReadCr3 ());
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuSleep.c b/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuSleep.c new file mode 100644 index 000000000..0fcaf224e --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuSleep.c @@ -0,0 +1,28 @@ +/** @file
+ CpuSleep function.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+/**
+ Places the CPU in a sleep state until an interrupt is received.
+
+ Places the CPU in a sleep state until an interrupt is received. If interrupts
+ are disabled prior to calling this function, then the CPU will be placed in a
+ sleep state indefinitely.
+
+**/
+VOID
+EFIAPI
+CpuSleep (
+ VOID
+ )
+{
+ _asm {
+ hlt
+ }
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuSleep.nasm b/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuSleep.nasm new file mode 100644 index 000000000..5e7f9abe6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuSleep.nasm @@ -0,0 +1,30 @@ +;------------------------------------------------------------------------------ ;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; CpuSleep.Asm
+;
+; Abstract:
+;
+; CpuSleep function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; CpuSleep (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(CpuSleep)
+ASM_PFX(CpuSleep):
+ hlt
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuSleepGcc.c b/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuSleepGcc.c new file mode 100644 index 000000000..ad5b150d6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/Ia32/CpuSleepGcc.c @@ -0,0 +1,27 @@ +/** @file
+ CpuSleep function for Ia32/X64 GCC.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+/**
+ Places the CPU in a sleep state until an interrupt is received.
+
+ Places the CPU in a sleep state until an interrupt is received. If interrupts
+ are disabled prior to calling this function, then the CPU will be placed in a
+ sleep state indefinitely.
+
+**/
+VOID
+EFIAPI
+CpuSleep (
+ VOID
+ )
+{
+ __asm__ __volatile__ ("hlt"::: "memory");
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S b/roms/edk2/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S new file mode 100644 index 000000000..375b91d31 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S @@ -0,0 +1,19 @@ +//------------------------------------------------------------------------------
+//
+// CpuSleep for RISC-V
+//
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+.data
+.align 3
+.section .text
+
+.global ASM_PFX(_CpuSleep)
+
+ASM_PFX(_CpuSleep):
+ wfi
+ ret
+
+
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/X64/CpuFlushTlb.nasm b/roms/edk2/MdePkg/Library/BaseCpuLib/X64/CpuFlushTlb.nasm new file mode 100644 index 000000000..8ddf7a286 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/X64/CpuFlushTlb.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------ ;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; CpuFlushTlb.Asm
+;
+; Abstract:
+;
+; CpuFlushTlb function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; CpuFlushTlb (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(CpuFlushTlb)
+ASM_PFX(CpuFlushTlb):
+ mov rax, cr3
+ mov cr3, rax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/X64/CpuSleep.nasm b/roms/edk2/MdePkg/Library/BaseCpuLib/X64/CpuSleep.nasm new file mode 100644 index 000000000..6a0ddaf2b --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseCpuLib/X64/CpuSleep.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ ;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; CpuSleep.Asm
+;
+; Abstract:
+;
+; CpuSleep function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; CpuSleep (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(CpuSleep)
+ASM_PFX(CpuSleep):
+ hlt
+ ret
+
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