diff options
| author |   Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
|---|---|---|
| committer | Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
| commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
| tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/edk2/MdePkg/Library/BaseLib/AArch64 | |
| parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) | |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/edk2/MdePkg/Library/BaseLib/AArch64')
16 files changed, 714 insertions, 0 deletions
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.S b/roms/edk2/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.S new file mode 100644 index 000000000..7524fb188 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.S @@ -0,0 +1,31 @@ +#------------------------------------------------------------------------------
+#
+# CpuBreakpoint() for AArch64
+#
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(CpuBreakpoint)
+
+#/**
+# Generates a breakpoint on the CPU.
+#
+# Generates a breakpoint on the CPU. The breakpoint must be implemented such
+# that code can resume normal execution after the breakpoint.
+#
+#**/
+#VOID
+#EFIAPI
+#CpuBreakpoint (
+# VOID
+# );
+#
+ASM_PFX(CpuBreakpoint):
+ svc 0xdbdb // Superviser exception. Takes 16bit arg -> Armv7 had 'swi' here.
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm b/roms/edk2/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm new file mode 100644 index 000000000..4a5e05def --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; CpuBreakpoint() for AArch64
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+
+ EXPORT CpuBreakpoint
+ AREA BaseLib_LowLevel, CODE, READONLY
+
+;/**
+; Generates a breakpoint on the CPU.
+;
+; Generates a breakpoint on the CPU. The breakpoint must be implemented such
+; that code can resume normal execution after the breakpoint.
+;
+;**/
+;VOID
+;EFIAPI
+;CpuBreakpoint (
+; VOID
+; );
+;
+CpuBreakpoint
+ svc 0xdbdb // Superviser exception. Takes 16bit arg -> Armv7 had 'swi' here.
+ ret
+
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.S b/roms/edk2/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.S new file mode 100644 index 000000000..f0faf16b0 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.S @@ -0,0 +1,30 @@ +#------------------------------------------------------------------------------
+#
+# DisableInterrupts() for AArch64
+#
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(DisableInterrupts)
+
+.set DAIF_WR_IRQ_BIT, (1 << 1)
+
+#/**
+# Disables CPU interrupts.
+#
+#**/
+#VOID
+#EFIAPI
+#DisableInterrupts (
+# VOID
+# );
+#
+ASM_PFX(DisableInterrupts):
+ msr daifset, #DAIF_WR_IRQ_BIT
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm b/roms/edk2/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm new file mode 100644 index 000000000..f7be1ea27 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; DisableInterrupts() for AArch64
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT DisableInterrupts
+ AREA BaseLib_LowLevel, CODE, READONLY
+
+DAIF_WR_IRQ_BIT EQU (1 << 1)
+
+;/**
+; Disables CPU interrupts.
+;
+;**/
+;VOID
+;EFIAPI
+;DisableInterrupts (
+; VOID
+; );
+;
+DisableInterrupts
+ msr daifset, #DAIF_WR_IRQ_BIT
+ ret
+
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.S b/roms/edk2/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.S new file mode 100644 index 000000000..97eeb13fb --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.S @@ -0,0 +1,30 @@ +#------------------------------------------------------------------------------
+#
+# EnableInterrupts() for AArch64
+#
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(EnableInterrupts)
+
+.set DAIF_WR_IRQ_BIT, (1 << 1)
+
+#/**
+# Enables CPU interrupts.
+#
+#**/
+#VOID
+#EFIAPI
+#EnableInterrupts (
+# VOID
+# );
+#
+ASM_PFX(EnableInterrupts):
+ msr daifclr, #DAIF_WR_IRQ_BIT
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm b/roms/edk2/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm new file mode 100644 index 000000000..0c3a3103e --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------
+;
+; EnableInterrupts() for AArch64
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT EnableInterrupts
+ AREA BaseLib_LowLevel, CODE, READONLY
+
+DAIF_WR_IRQ_BIT EQU (1 << 1)
+
+;/**
+; Enables CPU interrupts.
+;
+;**/
+;VOID
+;EFIAPI
+;EnableInterrupts (
+; VOID
+; );
+;
+EnableInterrupts
+ msr daifclr, #DAIF_WR_IRQ_BIT
+ ret
+
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.S b/roms/edk2/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.S new file mode 100644 index 000000000..bf8b829bb --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.S @@ -0,0 +1,39 @@ +#------------------------------------------------------------------------------
+#
+# GetInterruptState() function for AArch64
+#
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(GetInterruptState)
+
+.set DAIF_RD_IRQ_BIT, (1 << 7)
+
+#/**
+# Retrieves the current CPU interrupt state.
+#
+# Returns TRUE is interrupts are currently enabled. Otherwise
+# returns FALSE.
+#
+# @retval TRUE CPU interrupts are enabled.
+# @retval FALSE CPU interrupts are disabled.
+#
+#**/
+#
+#BOOLEAN
+#EFIAPI
+#GetInterruptState (
+# VOID
+# );
+#
+ASM_PFX(GetInterruptState):
+ mrs x0, daif
+ tst x0, #DAIF_RD_IRQ_BIT // Check IRQ mask; set Z=1 if clear/unmasked
+ cset w0, eq // if Z=1 (eq) return 1, else 0
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm b/roms/edk2/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm new file mode 100644 index 000000000..b169db45d --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm @@ -0,0 +1,43 @@ +;------------------------------------------------------------------------------
+;
+; GetInterruptState() function for AArch64
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT GetInterruptState
+ AREA BaseLib_LowLevel, CODE, READONLY
+
+DAIF_RD_IRQ_BIT EQU (1 << 7)
+
+;/**
+; Retrieves the current CPU interrupt state.
+;
+; Returns TRUE is interrupts are currently enabled. Otherwise
+; returns FALSE.
+;
+; @retval TRUE CPU interrupts are enabled.
+; @retval FALSE CPU interrupts are disabled.
+;
+;**/
+;
+;BOOLEAN
+;EFIAPI
+;GetInterruptState (
+; VOID
+; );
+;
+GetInterruptState
+ mrs x0, daif
+ mov w0, wzr
+ tst x0, #DAIF_RD_IRQ_BIT // Check IRQ mask; set Z=1 if clear/unmasked
+ bne exit // if Z=1 (eq) return 1, else 0
+ mov w0, #1
+exit
+ ret
+
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/MemoryFence.S b/roms/edk2/MdePkg/Library/BaseLib/AArch64/MemoryFence.S new file mode 100644 index 000000000..e553bd2dc --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/MemoryFence.S @@ -0,0 +1,33 @@ +##------------------------------------------------------------------------------
+#
+# MemoryFence() for AArch64
+#
+# Copyright (c) 2013, ARM Ltd. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##------------------------------------------------------------------------------
+
+.text
+.p2align 2
+
+GCC_ASM_EXPORT(MemoryFence)
+
+
+#/**
+# Used to serialize load and store operations.
+#
+# All loads and stores that proceed calls to this function are guaranteed to be
+# globally visible when this function returns.
+#
+#**/
+#VOID
+#EFIAPI
+#MemoryFence (
+# VOID
+# );
+#
+ASM_PFX(MemoryFence):
+ // System wide Data Memory Barrier.
+ dmb sy
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/MemoryFence.asm b/roms/edk2/MdePkg/Library/BaseLib/AArch64/MemoryFence.asm new file mode 100644 index 000000000..85bc6c0f9 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/MemoryFence.asm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; MemoryFence() for AArch64
+;
+; Copyright (c) 2013, ARM Ltd. All rights reserved.
+;
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT MemoryFence
+ AREA BaseLib_LowLevel, CODE, READONLY
+
+;/**
+; Used to serialize load and store operations.
+;
+; All loads and stores that proceed calls to this function are guaranteed to be
+; globally visible when this function returns.
+;
+;**/
+;VOID
+;EFIAPI
+;MemoryFence (
+; VOID
+; );
+;
+MemoryFence
+ // System wide Data Memory Barrier.
+ dmb sy
+ ret
+
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.S b/roms/edk2/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.S new file mode 100644 index 000000000..72cea259e --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.S @@ -0,0 +1,91 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2009-2013, ARM Ltd. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+.text
+.p2align 3
+
+GCC_ASM_EXPORT(SetJump)
+GCC_ASM_EXPORT(InternalLongJump)
+
+#define GPR_LAYOUT \
+ REG_PAIR (x19, x20, 0); \
+ REG_PAIR (x21, x22, 16); \
+ REG_PAIR (x23, x24, 32); \
+ REG_PAIR (x25, x26, 48); \
+ REG_PAIR (x27, x28, 64); \
+ REG_PAIR (x29, x30, 80);/*FP, LR*/ \
+ REG_ONE (x16, 96) /*IP0*/
+
+#define FPR_LAYOUT \
+ REG_PAIR ( d8, d9, 112); \
+ REG_PAIR (d10, d11, 128); \
+ REG_PAIR (d12, d13, 144); \
+ REG_PAIR (d14, d15, 160);
+
+#/**
+# Saves the current CPU context that can be restored with a call to LongJump() and returns 0.#
+#
+# Saves the current CPU context in the buffer specified by JumpBuffer and returns 0. The initial
+# call to SetJump() must always return 0. Subsequent calls to LongJump() cause a non-zero
+# value to be returned by SetJump().
+#
+# If JumpBuffer is NULL, then ASSERT().
+# For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
+#
+# @param JumpBuffer A pointer to CPU context buffer.
+#
+#**/
+#
+#UINTN
+#EFIAPI
+#SetJump (
+# IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer // X0
+# );
+#
+ASM_PFX(SetJump):
+ mov x16, sp // use IP0 so save SP
+#define REG_PAIR(REG1, REG2, OFFS) stp REG1, REG2, [x0, OFFS]
+#define REG_ONE(REG1, OFFS) str REG1, [x0, OFFS]
+ GPR_LAYOUT
+ FPR_LAYOUT
+#undef REG_PAIR
+#undef REG_ONE
+ mov w0, #0
+ ret
+
+#/**
+# Restores the CPU context that was saved with SetJump().#
+#
+# Restores the CPU context from the buffer specified by JumpBuffer.
+# This function never returns to the caller.
+# Instead is resumes execution based on the state of JumpBuffer.
+#
+# @param JumpBuffer A pointer to CPU context buffer.
+# @param Value The value to return when the SetJump() context is restored.
+#
+#**/
+#VOID
+#EFIAPI
+#InternalLongJump (
+# IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, // X0
+# IN UINTN Value // X1
+# );
+#
+ASM_PFX(InternalLongJump):
+#define REG_PAIR(REG1, REG2, OFFS) ldp REG1, REG2, [x0, OFFS]
+#define REG_ONE(REG1, OFFS) ldr REG1, [x0, OFFS]
+ GPR_LAYOUT
+ FPR_LAYOUT
+#undef REG_PAIR
+#undef REG_ONE
+ mov sp, x16
+ cmp w1, #0
+ mov w0, #1
+ csel w0, w1, w0, ne
+ // use br not ret, as ret is guaranteed to mispredict
+ br x30
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm b/roms/edk2/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm new file mode 100644 index 000000000..20dd0f1b8 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm @@ -0,0 +1,95 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2009-2013, ARM Ltd. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT SetJump
+ EXPORT InternalLongJump
+ AREA BaseLib_LowLevel, CODE, READONLY
+
+#define GPR_LAYOUT \
+ REG_PAIR (x19, x20, #0); \
+ REG_PAIR (x21, x22, #16); \
+ REG_PAIR (x23, x24, #32); \
+ REG_PAIR (x25, x26, #48); \
+ REG_PAIR (x27, x28, #64); \
+ REG_PAIR (x29, x30, #80);/*FP, LR*/ \
+ REG_ONE (x16, #96) /*IP0*/
+
+#define FPR_LAYOUT \
+ REG_PAIR ( d8, d9, #112); \
+ REG_PAIR (d10, d11, #128); \
+ REG_PAIR (d12, d13, #144); \
+ REG_PAIR (d14, d15, #160);
+
+;/**
+; Saves the current CPU context that can be restored with a call to LongJump() and returns 0.#
+;
+; Saves the current CPU context in the buffer specified by JumpBuffer and returns 0. The initial
+; call to SetJump() must always return 0. Subsequent calls to LongJump() cause a non-zero
+; value to be returned by SetJump().
+;
+; If JumpBuffer is NULL, then ASSERT().
+; For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
+;
+; @param JumpBuffer A pointer to CPU context buffer.
+;
+;**/
+;
+;UINTN
+;EFIAPI
+;SetJump (
+; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer // X0
+; );
+;
+SetJump
+ mov x16, sp // use IP0 so save SP
+#define REG_PAIR(REG1, REG2, OFFS) stp REG1, REG2, [x0, OFFS]
+#define REG_ONE(REG1, OFFS) str REG1, [x0, OFFS]
+ GPR_LAYOUT
+ FPR_LAYOUT
+#undef REG_PAIR
+#undef REG_ONE
+ mov w0, #0
+ ret
+
+;/**
+; Restores the CPU context that was saved with SetJump().#
+;
+; Restores the CPU context from the buffer specified by JumpBuffer.
+; This function never returns to the caller.
+; Instead is resumes execution based on the state of JumpBuffer.
+;
+; @param JumpBuffer A pointer to CPU context buffer.
+; @param Value The value to return when the SetJump() context is restored.
+;
+;**/
+;VOID
+;EFIAPI
+;InternalLongJump (
+; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, // X0
+; IN UINTN Value // X1
+; );
+;
+InternalLongJump
+#define REG_PAIR(REG1, REG2, OFFS) ldp REG1, REG2, [x0, OFFS]
+#define REG_ONE(REG1, OFFS) ldr REG1, [x0, OFFS]
+ GPR_LAYOUT
+ FPR_LAYOUT
+#undef REG_PAIR
+#undef REG_ONE
+ mov sp, x16
+ cmp w1, #0
+ mov w0, #1
+ beq exit
+ mov w0, w1
+exit
+ // use br not ret, as ret is guaranteed to mispredict
+ br x30
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
+
+ END
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/SpeculationBarrier.S b/roms/edk2/MdePkg/Library/BaseLib/AArch64/SpeculationBarrier.S new file mode 100644 index 000000000..a20d6aed0 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/SpeculationBarrier.S @@ -0,0 +1,33 @@ +##------------------------------------------------------------------------------
+#
+# SpeculationBarrier() for AArch64
+#
+# Copyright (c) 2019, Linaro Ltd. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##------------------------------------------------------------------------------
+
+.text
+.p2align 2
+
+GCC_ASM_EXPORT(SpeculationBarrier)
+
+
+#/**
+# Uses as a barrier to stop speculative execution.
+#
+# Ensures that no later instruction will execute speculatively, until all prior
+# instructions have completed.
+#
+#**/
+#VOID
+#EFIAPI
+#SpeculationBarrier (
+# VOID
+# );
+#
+ASM_PFX(SpeculationBarrier):
+ dsb sy
+ isb
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/SpeculationBarrier.asm b/roms/edk2/MdePkg/Library/BaseLib/AArch64/SpeculationBarrier.asm new file mode 100644 index 000000000..cafbe2bf2 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/SpeculationBarrier.asm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; SpeculationBarrier() for AArch64
+;
+; Copyright (c) 2019, Linaro Ltd. All rights reserved.
+;
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT SpeculationBarrier
+ AREA BaseLib_LowLevel, CODE, READONLY
+
+;/**
+; Uses as a barrier to stop speculative execution.
+;
+; Ensures that no later instruction will execute speculatively, until all prior
+; instructions have completed.
+;
+;**/
+;VOID
+;EFIAPI
+;SpeculationBarrier (
+; VOID
+; );
+;
+SpeculationBarrier
+ dsb sy
+ isb
+ ret
+
+ END
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/SwitchStack.S b/roms/edk2/MdePkg/Library/BaseLib/AArch64/SwitchStack.S new file mode 100644 index 000000000..f3bce6a09 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/SwitchStack.S @@ -0,0 +1,65 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2013, ARM Limited. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.align 5
+
+GCC_ASM_EXPORT(InternalSwitchStackAsm)
+GCC_ASM_EXPORT(CpuPause)
+
+#/**
+#
+# This allows the caller to switch the stack and goes to the new entry point
+#
+# @param EntryPoint The pointer to the location to enter
+# @param Context Parameter to pass in
+# @param Context2 Parameter2 to pass in
+# @param NewStack New Location of the stack
+#
+# @return Nothing. Goes to the Entry Point passing in the new parameters
+#
+#**/
+#VOID
+#EFIAPI
+#InternalSwitchStackAsm (
+# SWITCH_STACK_ENTRY_POINT EntryPoint,
+# VOID *Context,
+# VOID *Context2,
+# VOID *NewStack
+# );
+#
+ASM_PFX(InternalSwitchStackAsm):
+ mov x29, #0
+ mov x30, x0
+ mov sp, x3
+ mov x0, x1
+ mov x1, x2
+ ret
+
+#/**
+#
+# Requests CPU to pause for a short period of time.
+#
+# Requests CPU to pause for a short period of time. Typically used in MP
+# systems to prevent memory starvation while waiting for a spin lock.
+#
+#**/
+#VOID
+#EFIAPI
+#CpuPause (
+# VOID
+# )
+#
+ASM_PFX(CpuPause):
+ nop
+ nop
+ nop
+ nop
+ nop
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseLib/AArch64/SwitchStack.asm b/roms/edk2/MdePkg/Library/BaseLib/AArch64/SwitchStack.asm new file mode 100644 index 000000000..56dce5cbe --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/AArch64/SwitchStack.asm @@ -0,0 +1,65 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Limited. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT InternalSwitchStackAsm
+ EXPORT CpuPause
+ AREA BaseLib_LowLevel, CODE, READONLY
+
+;/**
+;
+; This allows the caller to switch the stack and goes to the new entry point
+;
+; @param EntryPoint The pointer to the location to enter
+; @param Context Parameter to pass in
+; @param Context2 Parameter2 to pass in
+; @param NewStack New Location of the stack
+;
+; @return Nothing. Goes to the Entry Point passing in the new parameters
+;
+;**/
+;VOID
+;EFIAPI
+;InternalSwitchStackAsm (
+; SWITCH_STACK_ENTRY_POINT EntryPoint,
+; VOID *Context,
+; VOID *Context2,
+; VOID *NewStack
+; );
+;
+InternalSwitchStackAsm
+ mov x29, #0
+ mov x30, x0
+ mov sp, x3
+ mov x0, x1
+ mov x1, x2
+ ret
+
+;/**
+;
+; Requests CPU to pause for a short period of time.
+;
+; Requests CPU to pause for a short period of time. Typically used in MP
+; systems to prevent memory starvation while waiting for a spin lock.
+;
+;**/
+;VOID
+;EFIAPI
+;CpuPause (
+; VOID
+; )
+;
+CpuPause
+ nop
+ nop
+ nop
+ nop
+ nop
+ ret
+
+ END
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