diff options
| author |   Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
|---|---|---|
| committer | Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
| commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
| tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/edk2/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c | |
| parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) | |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/edk2/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c')
| -rw-r--r-- | roms/edk2/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/roms/edk2/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c b/roms/edk2/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c new file mode 100644 index 000000000..21c80e432 --- /dev/null +++ b/roms/edk2/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c @@ -0,0 +1,51 @@ +/** @file
+ Base Reset System Library Shutdown API implementation for OVMF.
+
+ Copyright (C) 2020, Red Hat, Inc.
+ Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h> // BIT13
+
+#include <Library/BaseLib.h> // CpuDeadLoop()
+#include <Library/DebugLib.h> // ASSERT()
+#include <Library/IoLib.h> // IoOr16()
+#include <Library/PciLib.h> // PciRead16()
+#include <Library/ResetSystemLib.h> // ResetShutdown()
+#include <OvmfPlatforms.h> // OVMF_HOSTBRIDGE_DID
+
+/**
+ Calling this function causes the system to enter a power state equivalent
+ to the ACPI G2/S5 or G3 states.
+
+ System shutdown should not return, if it returns, it means the system does
+ not support shut down reset.
+**/
+VOID
+EFIAPI
+ResetShutdown (
+ VOID
+ )
+{
+ UINT16 AcpiPmBaseAddress;
+ UINT16 HostBridgeDevId;
+
+ AcpiPmBaseAddress = 0;
+ HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
+ switch (HostBridgeDevId) {
+ case INTEL_82441_DEVICE_ID:
+ AcpiPmBaseAddress = PIIX4_PMBA_VALUE;
+ break;
+ case INTEL_Q35_MCH_DEVICE_ID:
+ AcpiPmBaseAddress = ICH9_PMBASE_VALUE;
+ break;
+ default:
+ ASSERT (FALSE);
+ CpuDeadLoop ();
+ }
+
+ IoBitFieldWrite16 (AcpiPmBaseAddress + 4, 10, 13, 0);
+ IoOr16 (AcpiPmBaseAddress + 4, BIT13);
+ CpuDeadLoop ();
+}
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