Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

4 files changed, 388 insertions, 0 deletions

diff --git a/roms/edk2/OvmfPkg/XenResetVector/Ia32/Flat32ToFlat64.asm b/roms/edk2/OvmfPkg/XenResetVector/Ia32/Flat32ToFlat64.asm
new file mode 100644
index 000000000..661a8e702
--- /dev/null
+++ b/roms/edk2/OvmfPkg/XenResetVector/Ia32/Flat32ToFlat64.asm
@@ -0,0 +1,68 @@
+;------------------------------------------------------------------------------

+; @file

+; Transition from 32 bit flat protected mode into 64 bit flat protected mode

+;

+; Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2019, Citrix Systems, Inc.

+;

+; SPDX-License-Identifier: BSD-2-Clause-Patent

+;

+;------------------------------------------------------------------------------

+

+BITS    32

+

+;

+; Modified:  EAX, EBX, ECX, EDX, ESP

+;

+Transition32FlatTo64Flat:

+

+    OneTimeCall SetCr3ForPageTables64

+

+    mov     eax, cr4

+    bts     eax, 5                      ; enable PAE

+    mov     cr4, eax

+

+    mov     ecx, 0xc0000080

+    rdmsr

+    bts     eax, 8                      ; set LME

+    wrmsr

+

+    mov     eax, cr0

+    bts     eax, 31                     ; set PG

+    mov     cr0, eax                    ; enable paging

+

+    ;

+    ; backup ESP

+    ;

+    mov     ebx, esp

+

+    ;

+    ; recalculate delta

+    ;

+    mov     esp, PVH_SPACE(16)

+    call    .delta

+.delta:

+    pop     edx

+    sub     edx, ADDR_OF(.delta)

+

+    ;

+    ; push return addr and seg to the stack, then return far

+    ;

+    push    dword LINEAR_CODE64_SEL

+    mov     eax, ADDR_OF(jumpTo64BitAndLandHere)

+    add     eax, edx                             ; add delta

+    push    eax

+    retf

+

+BITS    64

+jumpTo64BitAndLandHere:

+

+    ;

+    ; restore ESP

+    ;

+    mov     esp, ebx

+

+    debugShowPostCode POSTCODE_64BIT_MODE

+

+    OneTimeCallRet Transition32FlatTo64Flat

+

diff --git a/roms/edk2/OvmfPkg/XenResetVector/Ia32/PageTables64.asm b/roms/edk2/OvmfPkg/XenResetVector/Ia32/PageTables64.asm
new file mode 100644
index 000000000..9f1c0e225
--- /dev/null
+++ b/roms/edk2/OvmfPkg/XenResetVector/Ia32/PageTables64.asm
@@ -0,0 +1,149 @@
+;------------------------------------------------------------------------------

+; @file

+; Sets the CR3 register for 64-bit paging

+;

+; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2019, Citrix Systems, Inc.

+; SPDX-License-Identifier: BSD-2-Clause-Patent

+;

+;------------------------------------------------------------------------------

+

+BITS    32

+

+%define PAGE_PRESENT            0x01

+%define PAGE_READ_WRITE         0x02

+%define PAGE_USER_SUPERVISOR    0x04

+%define PAGE_WRITE_THROUGH      0x08

+%define PAGE_CACHE_DISABLE     0x010

+%define PAGE_ACCESSED          0x020

+%define PAGE_DIRTY             0x040

+%define PAGE_PAT               0x080

+%define PAGE_GLOBAL           0x0100

+%define PAGE_2M_MBO            0x080

+%define PAGE_2M_PAT          0x01000

+

+%define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \

+                          PAGE_ACCESSED + \

+                          PAGE_DIRTY + \

+                          PAGE_READ_WRITE + \

+                          PAGE_PRESENT)

+

+%define PAGE_PDP_ATTR (PAGE_ACCESSED + \

+                       PAGE_READ_WRITE + \

+                       PAGE_PRESENT)

+

+; Check if Secure Encrypted Virtualization (SEV) feature is enabled

+;

+; If SEV is enabled then EAX will be at least 32

+; If SEV is disabled then EAX will be zero.

+;

+CheckSevFeature:

+    ; Check if we have a valid (0x8000_001F) CPUID leaf

+    mov       eax, 0x80000000

+    cpuid

+

+    ; This check should fail on Intel or Non SEV AMD CPUs. In future if

+    ; Intel CPUs supports this CPUID leaf then we are guranteed to have exact

+    ; same bit definition.

+    cmp       eax, 0x8000001f

+    jl        NoSev

+

+    ; Check for memory encryption feature:

+    ;  CPUID  Fn8000_001F[EAX] - Bit 1

+    ;

+    mov       eax,  0x8000001f

+    cpuid

+    bt        eax, 1

+    jnc       NoSev

+

+    ; Check if memory encryption is enabled

+    ;  MSR_0xC0010131 - Bit 0 (SEV enabled)

+    mov       ecx, 0xc0010131

+    rdmsr

+    bt        eax, 0

+    jnc       NoSev

+

+    ; Get pte bit position to enable memory encryption

+    ; CPUID Fn8000_001F[EBX] - Bits 5:0

+    ;

+    mov       eax, ebx

+    and       eax, 0x3f

+    jmp       SevExit

+

+NoSev:

+    xor       eax, eax

+

+SevExit:

+    OneTimeCallRet CheckSevFeature

+

+;

+; Modified:  EAX, EBX, ECX, EDX

+;

+SetCr3ForPageTables64:

+

+    OneTimeCall   CheckSevFeature

+    xor     edx, edx

+    test    eax, eax

+    jz      SevNotActive

+

+    ; If SEV is enabled, C-bit is always above 31

+    sub     eax, 32

+    bts     edx, eax

+

+SevNotActive:

+

+    ;

+    ; For OVMF, build some initial page tables at

+    ; PcdOvmfSecPageTablesBase - (PcdOvmfSecPageTablesBase + 0x6000).

+    ;

+    ; This range should match with PcdOvmfSecPageTablesSize which is

+    ; declared in the FDF files.

+    ;

+    ; At the end of PEI, the pages tables will be rebuilt into a

+    ; more permanent location by DxeIpl.

+    ;

+

+    mov     ecx, 6 * 0x1000 / 4

+    xor     eax, eax

+clearPageTablesMemoryLoop:

+    mov     dword[ecx * 4 + PT_ADDR (0) - 4], eax

+    loop    clearPageTablesMemoryLoop

+

+    ;

+    ; Top level Page Directory Pointers (1 * 512GB entry)

+    ;

+    mov     dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDP_ATTR

+    mov     dword[PT_ADDR (4)], edx

+

+    ;

+    ; Next level Page Directory Pointers (4 * 1GB entries => 4GB)

+    ;

+    mov     dword[PT_ADDR (0x1000)], PT_ADDR (0x2000) + PAGE_PDP_ATTR

+    mov     dword[PT_ADDR (0x1004)], edx

+    mov     dword[PT_ADDR (0x1008)], PT_ADDR (0x3000) + PAGE_PDP_ATTR

+    mov     dword[PT_ADDR (0x100C)], edx

+    mov     dword[PT_ADDR (0x1010)], PT_ADDR (0x4000) + PAGE_PDP_ATTR

+    mov     dword[PT_ADDR (0x1014)], edx

+    mov     dword[PT_ADDR (0x1018)], PT_ADDR (0x5000) + PAGE_PDP_ATTR

+    mov     dword[PT_ADDR (0x101C)], edx

+

+    ;

+    ; Page Table Entries (2048 * 2MB entries => 4GB)

+    ;

+    mov     ecx, 0x800

+pageTableEntriesLoop:

+    mov     eax, ecx

+    dec     eax

+    shl     eax, 21

+    add     eax, PAGE_2M_PDE_ATTR

+    mov     [ecx * 8 + PT_ADDR (0x2000 - 8)], eax

+    mov     [(ecx * 8 + PT_ADDR (0x2000 - 8)) + 4], edx

+    loop    pageTableEntriesLoop

+

+    ;

+    ; Set CR3 now that the paging structures are available

+    ;

+    mov     eax, PT_ADDR (0)

+    mov     cr3, eax

+

+    OneTimeCallRet SetCr3ForPageTables64

diff --git a/roms/edk2/OvmfPkg/XenResetVector/Ia32/SearchForBfvBase.asm b/roms/edk2/OvmfPkg/XenResetVector/Ia32/SearchForBfvBase.asm
new file mode 100644
index 000000000..190389c46
--- /dev/null
+++ b/roms/edk2/OvmfPkg/XenResetVector/Ia32/SearchForBfvBase.asm
@@ -0,0 +1,87 @@
+;------------------------------------------------------------------------------

+; @file

+; Search for the Boot Firmware Volume (BFV) base address

+;

+; Copyright (c) 2008 - 2009, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2019, Citrix Systems, Inc.

+;

+; SPDX-License-Identifier: BSD-2-Clause-Patent

+;

+;------------------------------------------------------------------------------

+

+;#define EFI_FIRMWARE_FILE_SYSTEM2_GUID \

+;  { 0x8c8ce578, 0x8a3d, 0x4f1c, { 0x99, 0x35, 0x89, 0x61, 0x85, 0xc3, 0x2d, 0xd3 } }

+%define FFS_GUID_DWORD0 0x8c8ce578

+%define FFS_GUID_DWORD1 0x4f1c8a3d

+%define FFS_GUID_DWORD2 0x61893599

+%define FFS_GUID_DWORD3 0xd32dc385

+

+BITS    32

+

+;

+; Modified:  EAX, EBX, ECX

+; Preserved: EDI, ESP

+;

+; @param[in]   EAX  Start search from here

+; @param[out]  EBP  Address of Boot Firmware Volume (BFV)

+;

+Flat32SearchForBfvBase:

+

+    mov     ecx, eax

+searchingForBfvHeaderLoop:

+    ;

+    ; We check for a firmware volume at every 4KB address in the 16MB

+    ; just below where we started, ECX.

+    ;

+    sub     eax, 0x1000

+    mov     ebx, ecx

+    sub     ebx, eax

+    cmp     ebx, 0x01000000

+    ; if ECX-EAX > 16MB; jump notfound

+    ja      searchedForBfvHeaderButNotFound

+

+    ;

+    ; Check FFS GUID

+    ;

+    cmp     dword [eax + 0x10], FFS_GUID_DWORD0

+    jne     searchingForBfvHeaderLoop

+    cmp     dword [eax + 0x14], FFS_GUID_DWORD1

+    jne     searchingForBfvHeaderLoop

+    cmp     dword [eax + 0x18], FFS_GUID_DWORD2

+    jne     searchingForBfvHeaderLoop

+    cmp     dword [eax + 0x1c], FFS_GUID_DWORD3

+    jne     searchingForBfvHeaderLoop

+

+    ;

+    ; Check FV Length

+    ;

+    cmp     dword [eax + 0x24], 0

+    jne     searchingForBfvHeaderLoop

+    mov     ebx, eax

+    add     ebx, dword [eax + 0x20]

+    cmp     ebx, ecx

+    jnz     searchingForBfvHeaderLoop

+

+    jmp     searchedForBfvHeaderAndItWasFound

+

+searchedForBfvHeaderButNotFound:

+    ;

+    ; Hang if the SEC entry point was not found

+    ;

+    debugShowPostCode POSTCODE_BFV_NOT_FOUND

+

+    ;

+    ; 0xbfbfbfbf in the EAX & EBP registers helps signal what failed

+    ; for debugging purposes.

+    ;

+    mov     eax, 0xBFBFBFBF

+    mov     ebp, eax

+    jmp     $

+

+searchedForBfvHeaderAndItWasFound:

+    mov     ebp, eax

+

+    debugShowPostCode POSTCODE_BFV_FOUND

+

+    OneTimeCallRet Flat32SearchForBfvBase

+

diff --git a/roms/edk2/OvmfPkg/XenResetVector/Ia32/XenPVHMain.asm b/roms/edk2/OvmfPkg/XenResetVector/Ia32/XenPVHMain.asm
new file mode 100644
index 000000000..2df0f12e1
--- /dev/null
+++ b/roms/edk2/OvmfPkg/XenResetVector/Ia32/XenPVHMain.asm
@@ -0,0 +1,84 @@
+;------------------------------------------------------------------------------

+; @file

+; An entry point use by Xen when a guest is started in PVH mode.

+;

+; Copyright (c) 2019, Citrix Systems, Inc.

+;

+; SPDX-License-Identifier: BSD-2-Clause-Patent

+;

+;------------------------------------------------------------------------------

+

+BITS    32

+

+xenPVHMain:

+    ;

+    ; 'BP' to indicate boot-strap processor

+    ;

+    mov     di, 'BP'

+

+    ;

+    ; Store "Start of day" struct pointer for later use

+    ;

+    mov     dword[PVH_SPACE (0)], ebx

+    mov     dword[PVH_SPACE (4)], 'XPVH'

+

+    ;

+    ; calculate delta between build-addr and run position

+    ;

+    mov     esp, PVH_SPACE(16)          ; create a temporary stack

+    call    .delta

+.delta:

+    pop     edx                         ; get addr of .delta

+    sub     edx, ADDR_OF(.delta)        ; calculate delta

+

+    ;

+    ; Find address of GDT and gdtr and fix the later

+    ;

+    mov     ebx, ADDR_OF(gdtr)

+    add     ebx, edx                    ; add delta gdtr

+    mov     eax, ADDR_OF(GDT_BASE)

+    add     eax, edx                    ; add delta to GDT_BASE

+    mov     dword[ebx + 2], eax         ; fix GDT_BASE addr in gdtr

+    lgdt    [ebx]

+

+    mov     eax, SEC_DEFAULT_CR0

+    mov     cr0, eax

+

+    ;

+    ; push return addr to the stack, then return far

+    ;

+    push    dword LINEAR_CODE_SEL          ; segment to select

+    mov     eax, ADDR_OF(.jmpToNewCodeSeg) ; return addr

+    add     eax, edx                       ; add delta to return addr

+    push    eax

+    retf

+.jmpToNewCodeSeg:

+

+    mov     eax, SEC_DEFAULT_CR4

+    mov     cr4, eax

+

+    mov     ax, LINEAR_SEL

+    mov     ds, ax

+    mov     es, ax

+    mov     fs, ax

+    mov     gs, ax

+    mov     ss, ax

+

+    ;

+    ; ESP will be used as initial value of the EAX register

+    ; in Main.asm

+    ;

+    xor     esp, esp

+

+    ;

+    ; parameter for Flat32SearchForBfvBase

+    ;

+    mov     eax, ADDR_OF(fourGigabytes)

+    add     eax, edx ; add delta

+

+    ;

+    ; Jump to the main routine of the pre-SEC code

+    ; skiping the 16-bit part of the routine and

+    ; into the 32-bit flat mode part

+    ;

+    OneTimeCallRet TransitionFromReal16To32BitFlat