diff options
| author |   Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
|---|---|---|
| committer | Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
| commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
| tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib | |
| parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) | |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib')
17 files changed, 3501 insertions, 0 deletions
diff --git a/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c new file mode 100644 index 000000000..4a56eec1b --- /dev/null +++ b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c @@ -0,0 +1,119 @@ +/** @file
+ AESNI feature.
+
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "CpuCommonFeatures.h"
+
+/**
+ Prepares for the data used by CPU feature detection and initialization.
+
+ @param[in] NumberOfProcessors The number of CPUs in the platform.
+
+ @return Pointer to a buffer of CPU related configuration data.
+
+ @note This service could be called by BSP only.
+**/
+VOID *
+EFIAPI
+AesniGetConfigData (
+ IN UINTN NumberOfProcessors
+ )
+{
+ UINT64 *ConfigData;
+
+ ConfigData = AllocateZeroPool (sizeof (UINT64) * NumberOfProcessors);
+ ASSERT (ConfigData != NULL);
+ return ConfigData;
+}
+
+/**
+ Detects if AESNI feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE AESNI feature is supported.
+ @retval FALSE AESNI feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+AesniSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ )
+{
+ MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig;
+
+ if (CpuInfo->CpuIdVersionInfoEcx.Bits.AESNI == 1) {
+ MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *) ConfigData;
+ ASSERT (MsrFeatureConfig != NULL);
+ MsrFeatureConfig[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);
+ return TRUE;
+ }
+ return FALSE;
+}
+
+/**
+ Initializes AESNI feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the AESNI feature must be enabled.
+ If FALSE, then the AESNI feature must be disabled.
+
+ @retval RETURN_SUCCESS AESNI feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+AesniInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ )
+{
+ MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig;
+
+ //
+ // SANDY_BRIDGE, SILVERMONT, XEON_5600, XEON_7, and XEON_PHI have the same MSR index,
+ // Simply use MSR_SANDY_BRIDGE_FEATURE_CONFIG here
+ //
+ // The scope of the MSR_SANDY_BRIDGE_FEATURE_CONFIG is Core, only program MSR_FEATURE_CONFIG for thread 0
+ // of each core. Otherwise, once a thread in the core disabled AES, the other thread will cause GP when
+ // programming it.
+ //
+ if (CpuInfo->ProcessorInfo.Location.Thread == 0) {
+ MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *) ConfigData;
+ ASSERT (MsrFeatureConfig != NULL);
+ if ((MsrFeatureConfig[ProcessorNumber].Bits.AESConfiguration & BIT0) == 0) {
+ CPU_REGISTER_TABLE_WRITE_FIELD (
+ ProcessorNumber,
+ Msr,
+ MSR_SANDY_BRIDGE_FEATURE_CONFIG,
+ MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER,
+ Bits.AESConfiguration,
+ BIT0 | ((State) ? 0 : BIT1)
+ );
+ }
+ }
+ return RETURN_SUCCESS;
+}
diff --git a/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c new file mode 100644 index 000000000..e6e5db759 --- /dev/null +++ b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c @@ -0,0 +1,81 @@ +/** @file
+ C1E feature.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "CpuCommonFeatures.h"
+
+/**
+ Detects if C1E feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE C1E feature is supported.
+ @retval FALSE C1E feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+C1eSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ )
+{
+ return IS_NEHALEM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel);
+}
+
+/**
+ Initializes C1E feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the C1E feature must be enabled.
+ If FALSE, then the C1E feature must be disabled.
+
+ @retval RETURN_SUCCESS C1E feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+C1eInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ )
+{
+ //
+ // The scope of C1EEnable bit in the MSR_NEHALEM_POWER_CTL is Package, only program
+ // MSR_FEATURE_CONFIG for thread 0 core 0 in each package.
+ //
+ if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo->ProcessorInfo.Location.Core != 0)) {
+ return RETURN_SUCCESS;
+ }
+
+ CPU_REGISTER_TABLE_WRITE_FIELD (
+ ProcessorNumber,
+ Msr,
+ MSR_NEHALEM_POWER_CTL,
+ MSR_NEHALEM_POWER_CTL_REGISTER,
+ Bits.C1EEnable,
+ (State) ? 1 : 0
+ );
+ return RETURN_SUCCESS;
+}
diff --git a/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c new file mode 100644 index 000000000..b1c6bf614 --- /dev/null +++ b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c @@ -0,0 +1,131 @@ +/** @file
+ Clock Modulation feature.
+
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "CpuCommonFeatures.h"
+
+typedef struct {
+ CPUID_THERMAL_POWER_MANAGEMENT_EAX ThermalPowerManagementEax;
+ MSR_IA32_CLOCK_MODULATION_REGISTER ClockModulation;
+} CLOCK_MODULATION_CONFIG_DATA;
+
+/**
+ Prepares for the data used by CPU feature detection and initialization.
+
+ @param[in] NumberOfProcessors The number of CPUs in the platform.
+
+ @return Pointer to a buffer of CPU related configuration data.
+
+ @note This service could be called by BSP only.
+**/
+VOID *
+EFIAPI
+ClockModulationGetConfigData (
+ IN UINTN NumberOfProcessors
+ )
+{
+ UINT32 *ConfigData;
+
+ ConfigData = AllocateZeroPool (sizeof (CLOCK_MODULATION_CONFIG_DATA) * NumberOfProcessors);
+ ASSERT (ConfigData != NULL);
+ return ConfigData;
+}
+
+/**
+ Detects if Clock Modulation feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE Clock Modulation feature is supported.
+ @retval FALSE Clock Modulation feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+ClockModulationSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ )
+{
+ CLOCK_MODULATION_CONFIG_DATA *CmConfigData;
+
+ if (CpuInfo->CpuIdVersionInfoEdx.Bits.ACPI == 1) {
+ CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *) ConfigData;
+ ASSERT (CmConfigData != NULL);
+ AsmCpuid (
+ CPUID_THERMAL_POWER_MANAGEMENT,
+ &CmConfigData[ProcessorNumber].ThermalPowerManagementEax.Uint32,
+ NULL,
+ NULL,
+ NULL
+ );
+ CmConfigData[ProcessorNumber].ClockModulation.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);
+ return TRUE;
+ }
+ return FALSE;
+}
+
+/**
+ Initializes Clock Modulation feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the Clock Modulation feature must be enabled.
+ If FALSE, then the Clock Modulation feature must be disabled.
+
+ @retval RETURN_SUCCESS Clock Modulation feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+ClockModulationInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ )
+{
+ CLOCK_MODULATION_CONFIG_DATA *CmConfigData;
+ MSR_IA32_CLOCK_MODULATION_REGISTER *ClockModulation;
+
+ CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *) ConfigData;
+ ASSERT (CmConfigData != NULL);
+ ClockModulation = &CmConfigData[ProcessorNumber].ClockModulation;
+
+ if (State) {
+ ClockModulation->Bits.OnDemandClockModulationEnable = 1;
+ ClockModulation->Bits.OnDemandClockModulationDutyCycle = PcdGet8 (PcdCpuClockModulationDutyCycle) >> 1;
+ if (CmConfigData[ProcessorNumber].ThermalPowerManagementEax.Bits.ECMD == 1) {
+ ClockModulation->Bits.ExtendedOnDemandClockModulationDutyCycle = PcdGet8 (PcdCpuClockModulationDutyCycle) & BIT0;
+ }
+ } else {
+ ClockModulation->Bits.OnDemandClockModulationEnable = 0;
+ }
+
+ CPU_REGISTER_TABLE_WRITE64 (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_CLOCK_MODULATION,
+ ClockModulation->Uint64
+ );
+
+ return RETURN_SUCCESS;
+}
diff --git a/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h new file mode 100644 index 000000000..b2390e6c3 --- /dev/null +++ b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h @@ -0,0 +1,1039 @@ +/** @file
+ CPU Common features library header file.
+
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _CPU_COMMON_FEATURES_H_
+#define _CPU_COMMON_FEATURES_H_
+
+#include <PiDxe.h>
+
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/RegisterCpuFeaturesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/LocalApicLib.h>
+
+#include <Register/Intel/Cpuid.h>
+#include <Register/Intel/Msr.h>
+
+/**
+ Prepares for the data used by CPU feature detection and initialization.
+
+ @param[in] NumberOfProcessors The number of CPUs in the platform.
+
+ @return Pointer to a buffer of CPU related configuration data.
+
+ @note This service could be called by BSP only.
+**/
+VOID *
+EFIAPI
+AesniGetConfigData (
+ IN UINTN NumberOfProcessors
+ );
+
+/**
+ Detects if AESNI feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE AESNI feature is supported.
+ @retval FALSE AESNI feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+AesniSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ );
+
+/**
+ Initializes AESNI feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the AESNI feature must be enabled.
+ If FALSE, then the AESNI feature must be disabled.
+
+ @retval RETURN_SUCCESS AESNI feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+AesniInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ );
+
+/**
+ Prepares for the data used by CPU feature detection and initialization.
+
+ @param[in] NumberOfProcessors The number of CPUs in the platform.
+
+ @return Pointer to a buffer of CPU related configuration data.
+
+ @note This service could be called by BSP only.
+**/
+VOID *
+EFIAPI
+ClockModulationGetConfigData (
+ IN UINTN NumberOfProcessors
+ );
+
+/**
+ Detects if Clock Modulation feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE Clock Modulation feature is supported.
+ @retval FALSE Clock Modulation feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+ClockModulationSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ );
+
+/**
+ Initializes Clock Modulation feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the Clock Modulation feature must be enabled.
+ If FALSE, then the Clock Modulation feature must be disabled.
+
+ @retval RETURN_SUCCESS Clock Modulation feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+ClockModulationInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ );
+
+/**
+ Detects if Enhanced Intel SpeedStep feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE Enhanced Intel SpeedStep feature is supported.
+ @retval FALSE Enhanced Intel SpeedStep feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+EistSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ );
+
+/**
+ Initializes Enhanced Intel SpeedStep feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the Enhanced Intel SpeedStep feature
+ must be enabled.
+ If FALSE, then the Enhanced Intel SpeedStep feature
+ must be disabled.
+
+ @retval RETURN_SUCCESS Enhanced Intel SpeedStep feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+EistInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ );
+
+/**
+ Detects if Execute Disable feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE Execute Disable feature is supported.
+ @retval FALSE Execute Disable feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+ExecuteDisableSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ );
+
+/**
+ Initializes Execute Disable feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the Execute Disable feature must be enabled.
+ If FALSE, then the Execute Disable feature must be disabled.
+
+ @retval RETURN_SUCCESS Execute Disable feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+ExecuteDisableInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ );
+
+/**
+ Initializes Fast-Strings feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the Fast-Strings feature must be enabled.
+ If FALSE, then the Fast-Strings feature must be disabled.
+
+ @retval RETURN_SUCCESS Fast-Strings feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+FastStringsInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ );
+
+/**
+ Detects if MONITOR/MWAIT feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE MONITOR/MWAIT feature is supported.
+ @retval FALSE MONITOR/MWAIT feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+MonitorMwaitSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ );
+
+/**
+ Initializes MONITOR/MWAIT feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the MONITOR/MWAIT feature must be enabled.
+ If FALSE, then the MONITOR/MWAIT feature must be disabled.
+
+ @retval RETURN_SUCCESS MONITOR/MWAIT feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+MonitorMwaitInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ );
+
+/**
+ Detects if VMX feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE VMX feature is supported.
+ @retval FALSE VMX feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+VmxSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ );
+
+/**
+ Initializes VMX feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the VMX feature must be enabled.
+ If FALSE, then the VMX feature must be disabled.
+
+ @retval RETURN_SUCCESS VMX feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+VmxInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ );
+
+/**
+ Detects if Lock Feature Control Register feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE Lock Feature Control Register feature is supported.
+ @retval FALSE Lock Feature Control Register feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+LockFeatureControlRegisterSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ );
+
+/**
+ Initializes Lock Feature Control Register feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the Lock Feature Control Register feature must be enabled.
+ If FALSE, then the Lock Feature Control Register feature must be disabled.
+
+ @retval RETURN_SUCCESS Lock Feature Control Register feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+LockFeatureControlRegisterInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ );
+
+/**
+ Detects if SMX feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE SMX feature is supported.
+ @retval FALSE SMX feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+SmxSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ );
+
+/**
+ Initializes SMX feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then SMX feature must be enabled.
+ If FALSE, then SMX feature must be disabled.
+
+ @retval RETURN_SUCCESS SMX feature is initialized.
+ @retval RETURN_UNSUPPORTED VMX not initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+SmxInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ );
+
+/**
+ Detects if LimitCpuidMaxval feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE LimitCpuidMaxval feature is supported.
+ @retval FALSE LimitCpuidMaxval feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+LimitCpuidMaxvalSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ );
+
+/**
+ Initializes LimitCpuidMaxval feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the LimitCpuidMaxval feature must be enabled.
+ If FALSE, then the LimitCpuidMaxval feature must be disabled.
+
+ @retval RETURN_SUCCESS LimitCpuidMaxval feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+LimitCpuidMaxvalInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ );
+
+/**
+ Detects if Machine Check Exception feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE Machine Check Exception feature is supported.
+ @retval FALSE Machine Check Exception feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+MceSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ );
+
+/**
+ Initializes Machine Check Exception feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the Machine Check Exception feature must be enabled.
+ If FALSE, then the Machine Check Exception feature must be disabled.
+
+ @retval RETURN_SUCCESS Machine Check Exception feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+MceInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ );
+
+/**
+ Detects if Machine Check Architecture feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE Machine Check Architecture feature is supported.
+ @retval FALSE Machine Check Architecture feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+McaSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ );
+
+/**
+ Initializes Machine Check Architecture feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the Machine Check Architecture feature must be enabled.
+ If FALSE, then the Machine Check Architecture feature must be disabled.
+
+ @retval RETURN_SUCCESS Machine Check Architecture feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+McaInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ );
+
+/**
+ Detects if IA32_MCG_CTL feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE IA32_MCG_CTL feature is supported.
+ @retval FALSE IA32_MCG_CTL feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+McgCtlSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ );
+
+/**
+ Initializes IA32_MCG_CTL feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the IA32_MCG_CTL feature must be enabled.
+ If FALSE, then the IA32_MCG_CTL feature must be disabled.
+
+ @retval RETURN_SUCCESS IA32_MCG_CTL feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+McgCtlInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ );
+
+/**
+ Detects if Pending Break feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE Pending Break feature is supported.
+ @retval FALSE Pending Break feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+PendingBreakSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ );
+
+/**
+ Initializes Pending Break feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the Pending Break feature must be enabled.
+ If FALSE, then the Pending Break feature must be disabled.
+
+ @retval RETURN_SUCCESS Pending Break feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+PendingBreakInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ );
+
+/**
+ Detects if C1E feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE C1E feature is supported.
+ @retval FALSE C1E feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+C1eSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ );
+
+/**
+ Initializes C1E feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the C1E feature must be enabled.
+ If FALSE, then the C1E feature must be disabled.
+
+ @retval RETURN_SUCCESS C1E feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+C1eInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ );
+
+/**
+ Prepares for the data used by CPU feature detection and initialization.
+
+ @param[in] NumberOfProcessors The number of CPUs in the platform.
+
+ @return Pointer to a buffer of CPU related configuration data.
+
+ @note This service could be called by BSP only.
+**/
+VOID *
+EFIAPI
+X2ApicGetConfigData (
+ IN UINTN NumberOfProcessors
+ );
+
+/**
+ Detects if X2Apci feature supported on current processor.
+
+ Detect if X2Apci has been already enabled.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE X2Apci feature is supported.
+ @retval FALSE X2Apci feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+X2ApicSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ );
+
+/**
+ Initializes X2Apci feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the X2Apci feature must be enabled.
+ If FALSE, then the X2Apci feature must be disabled.
+
+ @retval RETURN_SUCCESS X2Apci feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+X2ApicInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ );
+
+/**
+ Prepares for the data used by CPU feature detection and initialization.
+
+ @param[in] NumberOfProcessors The number of CPUs in the platform.
+
+ @return Pointer to a buffer of CPU related configuration data.
+
+ @note This service could be called by BSP only.
+**/
+VOID *
+EFIAPI
+PpinGetConfigData (
+ IN UINTN NumberOfProcessors
+ );
+
+/**
+ Detects if Protected Processor Inventory Number feature supported on current
+ processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE Protected Processor Inventory Number feature is supported.
+ @retval FALSE Protected Processor Inventory Number feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+PpinSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ );
+
+/**
+ Initializes Protected Processor Inventory Number feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the Protected Processor Inventory
+ Number feature must be enabled.
+ If FALSE, then the Protected Processor Inventory
+ Number feature must be disabled.
+
+ @retval RETURN_SUCCESS Protected Processor Inventory Number feature is
+ initialized.
+ @retval RETURN_DEVICE_ERROR Device can't change state because it has been
+ locked.
+
+**/
+RETURN_STATUS
+EFIAPI
+PpinInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ );
+
+/**
+ Detects if Local machine check exception feature supported on current
+ processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE Local machine check exception feature is supported.
+ @retval FALSE Local machine check exception feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+LmceSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ );
+
+/**
+ Initializes Local machine check exception feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the Local machine check exception
+ feature must be enabled.
+ If FALSE, then the Local machine check exception
+ feature must be disabled.
+
+ @retval RETURN_SUCCESS Local machine check exception feature is initialized.
+
+**/
+RETURN_STATUS
+EFIAPI
+LmceInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ );
+
+/**
+ Prepares for the data used by CPU feature detection and initialization.
+
+ @param[in] NumberOfProcessors The number of CPUs in the platform.
+
+ @return Pointer to a buffer of CPU related configuration data.
+
+ @note This service could be called by BSP only.
+**/
+VOID *
+EFIAPI
+ProcTraceGetConfigData (
+ IN UINTN NumberOfProcessors
+ );
+
+/**
+ Detects if Intel Processor Trace feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE Processor Trace feature is supported.
+ @retval FALSE Processor Trace feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+ProcTraceSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ );
+
+/**
+ Initializes Intel Processor Trace feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the Processor Trace feature must be
+ enabled.
+ If FALSE, then the Processor Trace feature must be
+ disabled.
+
+ @retval RETURN_SUCCESS Intel Processor Trace feature is initialized.
+
+**/
+RETURN_STATUS
+EFIAPI
+ProcTraceInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ );
+
+#endif
diff --git a/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c new file mode 100644 index 000000000..725ef7bd4 --- /dev/null +++ b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c @@ -0,0 +1,231 @@ +/** @file
+ This library registers CPU features defined in Intel(R) 64 and IA-32
+ Architectures Software Developer's Manual.
+
+ Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "CpuCommonFeatures.h"
+
+/**
+ Register CPU features.
+
+ @retval RETURN_SUCCESS Register successfully
+**/
+RETURN_STATUS
+EFIAPI
+CpuCommonFeaturesLibConstructor (
+ VOID
+ )
+{
+ RETURN_STATUS Status;
+
+ if (IsCpuFeatureSupported (CPU_FEATURE_AESNI)) {
+ Status = RegisterCpuFeature (
+ "AESNI",
+ AesniGetConfigData,
+ AesniSupport,
+ AesniInitialize,
+ CPU_FEATURE_AESNI,
+ CPU_FEATURE_END
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+ if (IsCpuFeatureSupported (CPU_FEATURE_MWAIT)) {
+ Status = RegisterCpuFeature (
+ "MWAIT",
+ NULL,
+ MonitorMwaitSupport,
+ MonitorMwaitInitialize,
+ CPU_FEATURE_MWAIT,
+ CPU_FEATURE_END
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+ if (IsCpuFeatureSupported (CPU_FEATURE_ACPI)) {
+ Status = RegisterCpuFeature (
+ "ACPI",
+ ClockModulationGetConfigData,
+ ClockModulationSupport,
+ ClockModulationInitialize,
+ CPU_FEATURE_ACPI,
+ CPU_FEATURE_END
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+ if (IsCpuFeatureSupported (CPU_FEATURE_EIST)) {
+ Status = RegisterCpuFeature (
+ "EIST",
+ NULL,
+ EistSupport,
+ EistInitialize,
+ CPU_FEATURE_EIST,
+ CPU_FEATURE_END
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+ if (IsCpuFeatureSupported (CPU_FEATURE_FASTSTRINGS)) {
+ Status = RegisterCpuFeature (
+ "FastStrings",
+ NULL,
+ NULL,
+ FastStringsInitialize,
+ CPU_FEATURE_FASTSTRINGS,
+ CPU_FEATURE_END
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+ if (IsCpuFeatureSupported (CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER)) {
+ Status = RegisterCpuFeature (
+ "Lock Feature Control Register",
+ NULL,
+ LockFeatureControlRegisterSupport,
+ LockFeatureControlRegisterInitialize,
+ CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER,
+ CPU_FEATURE_END
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+ if (IsCpuFeatureSupported (CPU_FEATURE_SMX)) {
+ Status = RegisterCpuFeature (
+ "SMX",
+ NULL,
+ SmxSupport,
+ SmxInitialize,
+ CPU_FEATURE_SMX,
+ CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER | CPU_FEATURE_THREAD_BEFORE,
+ CPU_FEATURE_END
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+ if (IsCpuFeatureSupported (CPU_FEATURE_VMX)) {
+ Status = RegisterCpuFeature (
+ "VMX",
+ NULL,
+ VmxSupport,
+ VmxInitialize,
+ CPU_FEATURE_VMX,
+ CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER | CPU_FEATURE_THREAD_BEFORE,
+ CPU_FEATURE_END
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+ if (IsCpuFeatureSupported (CPU_FEATURE_LIMIT_CPUID_MAX_VAL)) {
+ Status = RegisterCpuFeature (
+ "Limit CpuId Maximum Value",
+ NULL,
+ LimitCpuidMaxvalSupport,
+ LimitCpuidMaxvalInitialize,
+ CPU_FEATURE_LIMIT_CPUID_MAX_VAL,
+ CPU_FEATURE_END
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+ if (IsCpuFeatureSupported (CPU_FEATURE_MCE)) {
+ Status = RegisterCpuFeature (
+ "Machine Check Enable",
+ NULL,
+ MceSupport,
+ MceInitialize,
+ CPU_FEATURE_MCE,
+ CPU_FEATURE_END
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+ if (IsCpuFeatureSupported (CPU_FEATURE_MCA)) {
+ Status = RegisterCpuFeature (
+ "Machine Check Architect",
+ NULL,
+ McaSupport,
+ McaInitialize,
+ CPU_FEATURE_MCA,
+ CPU_FEATURE_END
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+ if (IsCpuFeatureSupported (CPU_FEATURE_MCG_CTL)) {
+ Status = RegisterCpuFeature (
+ "MCG_CTL",
+ NULL,
+ McgCtlSupport,
+ McgCtlInitialize,
+ CPU_FEATURE_MCG_CTL,
+ CPU_FEATURE_END
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+ if (IsCpuFeatureSupported (CPU_FEATURE_PENDING_BREAK)) {
+ Status = RegisterCpuFeature (
+ "Pending Break",
+ NULL,
+ PendingBreakSupport,
+ PendingBreakInitialize,
+ CPU_FEATURE_PENDING_BREAK,
+ CPU_FEATURE_END
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+ if (IsCpuFeatureSupported (CPU_FEATURE_C1E)) {
+ Status = RegisterCpuFeature (
+ "C1E",
+ NULL,
+ C1eSupport,
+ C1eInitialize,
+ CPU_FEATURE_C1E,
+ CPU_FEATURE_END
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+ if (IsCpuFeatureSupported (CPU_FEATURE_X2APIC)) {
+ Status = RegisterCpuFeature (
+ "X2Apic",
+ X2ApicGetConfigData,
+ X2ApicSupport,
+ X2ApicInitialize,
+ CPU_FEATURE_X2APIC,
+ CPU_FEATURE_END
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+ if (IsCpuFeatureSupported (CPU_FEATURE_PPIN)) {
+ Status = RegisterCpuFeature (
+ "PPIN",
+ PpinGetConfigData,
+ PpinSupport,
+ PpinInitialize,
+ CPU_FEATURE_PPIN,
+ CPU_FEATURE_END
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+ if (IsCpuFeatureSupported (CPU_FEATURE_LMCE)) {
+ Status = RegisterCpuFeature (
+ "LMCE",
+ NULL,
+ LmceSupport,
+ LmceInitialize,
+ CPU_FEATURE_LMCE,
+ CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER | CPU_FEATURE_THREAD_BEFORE,
+ CPU_FEATURE_END
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+ if (IsCpuFeatureSupported (CPU_FEATURE_PROC_TRACE)) {
+ Status = RegisterCpuFeature (
+ "Proc Trace",
+ ProcTraceGetConfigData,
+ ProcTraceSupport,
+ ProcTraceInitialize,
+ CPU_FEATURE_PROC_TRACE,
+ CPU_FEATURE_END
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+
+ return RETURN_SUCCESS;
+}
+
+
+
diff --git a/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf new file mode 100644 index 000000000..7fbcd8da0 --- /dev/null +++ b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf @@ -0,0 +1,64 @@ +## @file
+# NULL instance to register CPU features.
+#
+# This library registers CPU features defined in Intel(R) 64 and IA-32
+# Architectures Software Developer's Manual.
+#
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = CpuCommonFeaturesLib
+ MODULE_UNI_FILE = CpuCommonFeaturesLib.uni
+ FILE_GUID = 6D69F79F-9535-4893-9DD7-93929898252C
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NULL
+
+ CONSTRUCTOR = CpuCommonFeaturesLibConstructor
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources]
+ CpuCommonFeaturesLib.c
+ CpuCommonFeatures.h
+ Aesni.c
+ C1e.c
+ ClockModulation.c
+ Eist.c
+ FastStrings.c
+ FeatureControl.c
+ LimitCpuIdMaxval.c
+ MachineCheck.c
+ MonitorMwait.c
+ PendingBreak.c
+ X2Apic.c
+ Ppin.c
+ ProcTrace.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ DebugLib
+ RegisterCpuFeaturesLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ LocalApicLib
+
+[Pcd]
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle ## SOMETIMES_CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset ## SOMETIMES_CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme ## SOMETIMES_CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize ## SOMETIMES_CONSUMES
diff --git a/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.uni b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.uni new file mode 100644 index 000000000..7f799e895 --- /dev/null +++ b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.uni @@ -0,0 +1,20 @@ +// /** @file
+// Dxe Crc32 Guided Section Extract library.
+//
+// This library doesn't produce any library class. The constructor function uses
+// ExtractGuidedSectionLib service to register CRC32 guided section handler
+// that parses CRC32 encapsulation section and extracts raw data.
+//
+// It uses UEFI boot service CalculateCrc32 to authenticate 32 bit CRC value.
+//
+// Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Dxe Crc32 Guided Section Extract library."
+
+#string STR_MODULE_DESCRIPTION #language en-US "This library doesn't produce any library class. The constructor function uses ExtractGuidedSectionLib service to register CRC32 guided section handler that parses CRC32 encapsulation section and extracts raw data. It uses UEFI boot service CalculateCrc32 to authenticate 32 bit CRC value."
+
diff --git a/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c new file mode 100644 index 000000000..e60220d3c --- /dev/null +++ b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c @@ -0,0 +1,87 @@ +/** @file
+ Enhanced Intel SpeedStep feature.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "CpuCommonFeatures.h"
+
+/**
+ Detects if Enhanced Intel SpeedStep feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE Enhanced Intel SpeedStep feature is supported.
+ @retval FALSE Enhanced Intel SpeedStep feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+EistSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ )
+{
+ return (CpuInfo->CpuIdVersionInfoEcx.Bits.EIST == 1);
+}
+
+/**
+ Initializes Enhanced Intel SpeedStep feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the Enhanced Intel SpeedStep feature
+ must be enabled.
+ If FALSE, then the Enhanced Intel SpeedStep feature
+ must be disabled.
+
+ @retval RETURN_SUCCESS Enhanced Intel SpeedStep feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+EistInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ )
+{
+ //
+ // The scope of the MSR_IA32_MISC_ENABLE is core for below processor type, only program
+ // MSR_IA32_MISC_ENABLE for thread 0 in each core.
+ //
+ if (IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+ if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
+ return RETURN_SUCCESS;
+ }
+ }
+
+ CPU_REGISTER_TABLE_WRITE_FIELD (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_MISC_ENABLE,
+ MSR_IA32_MISC_ENABLE_REGISTER,
+ Bits.EIST,
+ (State) ? 1 : 0
+ );
+ return RETURN_SUCCESS;
+}
diff --git a/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c new file mode 100644 index 000000000..2b678f3bf --- /dev/null +++ b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c @@ -0,0 +1,58 @@ +/** @file
+ Fast-Strings feature.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "CpuCommonFeatures.h"
+
+/**
+ Initializes Fast-Strings feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the Fast-Strings feature must be enabled.
+ If FALSE, then the Fast-Strings feature must be disabled.
+
+ @retval RETURN_SUCCESS Fast-Strings feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+FastStringsInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ )
+{
+ //
+ // The scope of FastStrings bit in the MSR_IA32_MISC_ENABLE is core for below processor type, only program
+ // MSR_IA32_MISC_ENABLE for thread 0 in each core.
+ //
+ if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+ if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
+ return RETURN_SUCCESS;
+ }
+ }
+
+ CPU_REGISTER_TABLE_WRITE_FIELD (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_MISC_ENABLE,
+ MSR_IA32_MISC_ENABLE_REGISTER,
+ Bits.FastStrings,
+ (State) ? 1 : 0
+ );
+ return RETURN_SUCCESS;
+}
diff --git a/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c new file mode 100644 index 000000000..b4474d2fa --- /dev/null +++ b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c @@ -0,0 +1,280 @@ +/** @file
+ Features in MSR_IA32_FEATURE_CONTROL register.
+
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "CpuCommonFeatures.h"
+
+/**
+ Detects if VMX feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE VMX feature is supported.
+ @retval FALSE VMX feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+VmxSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ )
+{
+ return (CpuInfo->CpuIdVersionInfoEcx.Bits.VMX == 1);
+}
+
+/**
+ Initializes VMX feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the VMX feature must be enabled.
+ If FALSE, then the VMX feature must be disabled.
+
+ @retval RETURN_SUCCESS VMX feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+VmxInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ )
+{
+ //
+ // The scope of EnableVmxOutsideSmx bit in the MSR_IA32_FEATURE_CONTROL is core for
+ // below processor type, only program MSR_IA32_FEATURE_CONTROL for thread 0 in each
+ // core.
+ //
+ if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+ if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
+ return RETURN_SUCCESS;
+ }
+ }
+
+ CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_FEATURE_CONTROL,
+ MSR_IA32_FEATURE_CONTROL_REGISTER,
+ Bits.EnableVmxOutsideSmx,
+ (State) ? 1 : 0
+ );
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Detects if Lock Feature Control Register feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE Lock Feature Control Register feature is supported.
+ @retval FALSE Lock Feature Control Register feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+LockFeatureControlRegisterSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ )
+{
+ return TRUE;
+}
+
+/**
+ Initializes Lock Feature Control Register feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the Lock Feature Control Register feature must be enabled.
+ If FALSE, then the Lock Feature Control Register feature must be disabled.
+
+ @retval RETURN_SUCCESS Lock Feature Control Register feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+LockFeatureControlRegisterInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ )
+{
+ //
+ // The scope of Lock bit in the MSR_IA32_FEATURE_CONTROL is core for
+ // below processor type, only program MSR_IA32_FEATURE_CONTROL for thread 0 in each
+ // core.
+ //
+ if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+ if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
+ return RETURN_SUCCESS;
+ }
+ }
+
+ CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_FEATURE_CONTROL,
+ MSR_IA32_FEATURE_CONTROL_REGISTER,
+ Bits.Lock,
+ 1
+ );
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Detects if SMX feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE SMX feature is supported.
+ @retval FALSE SMX feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+SmxSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ )
+{
+ return (CpuInfo->CpuIdVersionInfoEcx.Bits.SMX == 1);
+}
+
+/**
+ Initializes SMX feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then SMX feature must be enabled.
+ If FALSE, then SMX feature must be disabled.
+
+ @retval RETURN_SUCCESS SMX feature is initialized.
+ @retval RETURN_UNSUPPORTED VMX not initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+SmxInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ )
+{
+ RETURN_STATUS Status;
+
+ //
+ // The scope of Lock bit in the MSR_IA32_FEATURE_CONTROL is core for
+ // below processor type, only program MSR_IA32_FEATURE_CONTROL for thread 0 in each
+ // core.
+ //
+ if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+ if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
+ return RETURN_SUCCESS;
+ }
+ }
+
+ Status = RETURN_SUCCESS;
+
+ if (State && (!IsCpuFeatureInSetting (CPU_FEATURE_VMX))) {
+ DEBUG ((DEBUG_WARN, "Warning :: Can't enable SMX feature when VMX feature not enabled, disable it.\n"));
+ State = FALSE;
+ Status = RETURN_UNSUPPORTED;
+ }
+
+ CPU_REGISTER_TABLE_WRITE_FIELD (
+ ProcessorNumber,
+ ControlRegister,
+ 4,
+ IA32_CR4,
+ Bits.SMXE,
+ (State) ? 1 : 0
+ )
+
+ CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_FEATURE_CONTROL,
+ MSR_IA32_FEATURE_CONTROL_REGISTER,
+ Bits.SenterLocalFunctionEnables,
+ (State) ? 0x7F : 0
+ );
+
+ CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_FEATURE_CONTROL,
+ MSR_IA32_FEATURE_CONTROL_REGISTER,
+ Bits.SenterGlobalEnable,
+ (State) ? 1 : 0
+ );
+
+ CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_FEATURE_CONTROL,
+ MSR_IA32_FEATURE_CONTROL_REGISTER,
+ Bits.EnableVmxInsideSmx,
+ (State) ? 1 : 0
+ );
+
+ return Status;
+}
diff --git a/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c new file mode 100644 index 000000000..906ed6540 --- /dev/null +++ b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c @@ -0,0 +1,90 @@ +/** @file
+ LimitCpuidMaxval Feature.
+
+ Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "CpuCommonFeatures.h"
+
+/**
+ Detects if LimitCpuidMaxval feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE LimitCpuidMaxval feature is supported.
+ @retval FALSE LimitCpuidMaxval feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+LimitCpuidMaxvalSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ )
+{
+ UINT32 Eax;
+
+ AsmCpuid (CPUID_SIGNATURE, &Eax, NULL, NULL, NULL);
+ return (Eax > 2);
+}
+
+/**
+ Initializes LimitCpuidMaxval feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the LimitCpuidMaxval feature must be enabled.
+ If FALSE, then the LimitCpuidMaxval feature must be disabled.
+
+ @retval RETURN_SUCCESS LimitCpuidMaxval feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+LimitCpuidMaxvalInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ )
+{
+ //
+ // The scope of LimitCpuidMaxval bit in the MSR_IA32_MISC_ENABLE is core for below
+ // processor type, only program MSR_IA32_MISC_ENABLE for thread 0 in each core.
+ //
+ if (IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+ if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
+ return RETURN_SUCCESS;
+ }
+ }
+
+ CPU_REGISTER_TABLE_WRITE_FIELD (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_MISC_ENABLE,
+ MSR_IA32_MISC_ENABLE_REGISTER,
+ Bits.LimitCpuidMaxval,
+ (State) ? 1 : 0
+ );
+ return RETURN_SUCCESS;
+}
diff --git a/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c new file mode 100644 index 000000000..bb5d983d1 --- /dev/null +++ b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c @@ -0,0 +1,344 @@ +/** @file
+ Machine Check features.
+
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "CpuCommonFeatures.h"
+
+/**
+ Detects if Machine Check Exception feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE Machine Check Exception feature is supported.
+ @retval FALSE Machine Check Exception feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+MceSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ )
+{
+ return (CpuInfo->CpuIdVersionInfoEdx.Bits.MCE == 1);
+}
+
+/**
+ Initializes Machine Check Exception feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the Machine Check Exception feature must be enabled.
+ If FALSE, then the Machine Check Exception feature must be disabled.
+
+ @retval RETURN_SUCCESS Machine Check Exception feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+MceInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ )
+{
+ //
+ // Set MCE bit in CR4
+ //
+ CPU_REGISTER_TABLE_WRITE_FIELD (
+ ProcessorNumber,
+ ControlRegister,
+ 4,
+ IA32_CR4,
+ Bits.MCE,
+ (State) ? 1 : 0
+ );
+ return RETURN_SUCCESS;
+}
+
+/**
+ Detects if Machine Check Architecture feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE Machine Check Architecture feature is supported.
+ @retval FALSE Machine Check Architecture feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+McaSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ )
+{
+ if (!MceSupport (ProcessorNumber, CpuInfo, ConfigData)) {
+ return FALSE;
+ }
+ return (CpuInfo->CpuIdVersionInfoEdx.Bits.MCA == 1);
+}
+
+/**
+ Initializes Machine Check Architecture feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the Machine Check Architecture feature must be enabled.
+ If FALSE, then the Machine Check Architecture feature must be disabled.
+
+ @retval RETURN_SUCCESS Machine Check Architecture feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+McaInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ )
+{
+ MSR_IA32_MCG_CAP_REGISTER McgCap;
+ UINT32 BankIndex;
+
+ //
+ // The scope of MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS is core for below processor type, only program
+ // MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS for thread 0 in each core.
+ //
+ if (IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_SANDY_BRIDGE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_SKYLAKE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_XEON_PHI_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+ if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
+ return RETURN_SUCCESS;
+ }
+ }
+
+ //
+ // The scope of MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS is package for below processor type, only program
+ // MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS for thread 0 core 0 in each package.
+ //
+ if (IS_NEHALEM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+ if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo->ProcessorInfo.Location.Core != 0)) {
+ return RETURN_SUCCESS;
+ }
+ }
+
+ if (State) {
+ McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
+ for (BankIndex = 0; BankIndex < (UINT32) McgCap.Bits.Count; BankIndex++) {
+ CPU_REGISTER_TABLE_WRITE64 (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_MC0_CTL + BankIndex * 4,
+ MAX_UINT64
+ );
+ }
+
+ if (PcdGetBool (PcdIsPowerOnReset)) {
+ for (BankIndex = 0; BankIndex < (UINTN) McgCap.Bits.Count; BankIndex++) {
+ CPU_REGISTER_TABLE_WRITE64 (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_MC0_STATUS + BankIndex * 4,
+ 0
+ );
+ }
+ }
+ }
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Detects if IA32_MCG_CTL feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE IA32_MCG_CTL feature is supported.
+ @retval FALSE IA32_MCG_CTL feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+McgCtlSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ )
+{
+ MSR_IA32_MCG_CAP_REGISTER McgCap;
+
+ if (!McaSupport (ProcessorNumber, CpuInfo, ConfigData)) {
+ return FALSE;
+ }
+ McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
+ return (McgCap.Bits.MCG_CTL_P == 1);
+}
+
+/**
+ Initializes IA32_MCG_CTL feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the IA32_MCG_CTL feature must be enabled.
+ If FALSE, then the IA32_MCG_CTL feature must be disabled.
+
+ @retval RETURN_SUCCESS IA32_MCG_CTL feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+McgCtlInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ )
+{
+ CPU_REGISTER_TABLE_WRITE64 (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_MCG_CTL,
+ (State)? MAX_UINT64 : 0
+ );
+ return RETURN_SUCCESS;
+}
+
+/**
+ Detects if Local machine check exception feature supported on current
+ processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE Local machine check exception feature is supported.
+ @retval FALSE Local machine check exception feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+LmceSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ )
+{
+ MSR_IA32_MCG_CAP_REGISTER McgCap;
+
+ if (!McaSupport (ProcessorNumber, CpuInfo, ConfigData)) {
+ return FALSE;
+ }
+
+ McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
+ if (ProcessorNumber == 0) {
+ DEBUG ((DEBUG_INFO, "LMCE enable = %x\n", (BOOLEAN) (McgCap.Bits.MCG_LMCE_P != 0)));
+ }
+ return (BOOLEAN) (McgCap.Bits.MCG_LMCE_P != 0);
+}
+
+/**
+ Initializes Local machine check exception feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the Local machine check exception
+ feature must be enabled.
+ If FALSE, then the Local machine check exception
+ feature must be disabled.
+
+ @retval RETURN_SUCCESS Local machine check exception feature is initialized.
+
+**/
+RETURN_STATUS
+EFIAPI
+LmceInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ )
+{
+ //
+ // The scope of LcmeOn bit in the MSR_IA32_MISC_ENABLE is core for below processor type, only program
+ // MSR_IA32_MISC_ENABLE for thread 0 in each core.
+ //
+ if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+ if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
+ return RETURN_SUCCESS;
+ }
+ }
+
+ CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_FEATURE_CONTROL,
+ MSR_IA32_FEATURE_CONTROL_REGISTER,
+ Bits.LmceOn,
+ (State) ? 1 : 0
+ );
+
+ return RETURN_SUCCESS;
+}
diff --git a/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c new file mode 100644 index 000000000..08dbb670a --- /dev/null +++ b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c @@ -0,0 +1,88 @@ +/** @file
+ MonitorMwait feature.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "CpuCommonFeatures.h"
+
+/**
+ Detects if MONITOR/MWAIT feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE MONITOR/MWAIT feature is supported.
+ @retval FALSE MONITOR/MWAIT feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+MonitorMwaitSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ )
+{
+ return (CpuInfo->CpuIdVersionInfoEcx.Bits.MONITOR == 1);
+}
+
+/**
+ Initializes MONITOR/MWAIT feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the MONITOR/MWAIT feature must be enabled.
+ If FALSE, then the MONITOR/MWAIT feature must be disabled.
+
+ @retval RETURN_SUCCESS MONITOR/MWAIT feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+MonitorMwaitInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ )
+{
+ //
+ // The scope of the MSR_IA32_MISC_ENABLE is core for below processor type, only program
+ // MSR_IA32_MISC_ENABLE for thread 0 in each core.
+ //
+ if (IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+ if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
+ return RETURN_SUCCESS;
+ }
+ }
+
+ CPU_REGISTER_TABLE_WRITE_FIELD (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_MISC_ENABLE,
+ MSR_IA32_MISC_ENABLE_REGISTER,
+ Bits.MONITOR,
+ (State) ? 1 : 0
+ );
+ return RETURN_SUCCESS;
+}
diff --git a/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c new file mode 100644 index 000000000..9c20a60ef --- /dev/null +++ b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c @@ -0,0 +1,95 @@ +/** @file
+ Pending Break feature.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "CpuCommonFeatures.h"
+
+/**
+ Detects if Pending Break feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE Pending Break feature is supported.
+ @retval FALSE Pending Break feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+PendingBreakSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ )
+{
+ if (IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_PENTIUM_M_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+ return (CpuInfo->CpuIdVersionInfoEdx.Bits.PBE == 1);
+ }
+ return FALSE;
+}
+
+/**
+ Initializes Pending Break feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the Pending Break feature must be enabled.
+ If FALSE, then the Pending Break feature must be disabled.
+
+ @retval RETURN_SUCCESS Pending Break feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+PendingBreakInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ )
+{
+ //
+ // The scope of the MSR_ATOM_IA32_MISC_ENABLE is core for below processor type, only program
+ // MSR_ATOM_IA32_MISC_ENABLE for thread 0 in each core.
+ //
+ // Support function has check the processer type for this feature, no need to check again
+ // here.
+ //
+ if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
+ return RETURN_SUCCESS;
+ }
+
+ //
+ // ATOM, CORE2, CORE, PENTIUM_4 and IS_PENTIUM_M_PROCESSOR have the same MSR index,
+ // Simply use MSR_ATOM_IA32_MISC_ENABLE here
+ //
+ CPU_REGISTER_TABLE_WRITE_FIELD (
+ ProcessorNumber,
+ Msr,
+ MSR_ATOM_IA32_MISC_ENABLE,
+ MSR_ATOM_IA32_MISC_ENABLE_REGISTER,
+ Bits.FERR,
+ (State) ? 1 : 0
+ );
+ return RETURN_SUCCESS;
+}
diff --git a/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c new file mode 100644 index 000000000..8450c7ea3 --- /dev/null +++ b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c @@ -0,0 +1,164 @@ +/** @file
+ Protected Processor Inventory Number(PPIN) feature.
+
+ Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "CpuCommonFeatures.h"
+
+/**
+ Prepares for the data used by CPU feature detection and initialization.
+
+ @param[in] NumberOfProcessors The number of CPUs in the platform.
+
+ @return Pointer to a buffer of CPU related configuration data.
+
+ @note This service could be called by BSP only.
+**/
+VOID *
+EFIAPI
+PpinGetConfigData (
+ IN UINTN NumberOfProcessors
+ )
+{
+ VOID *ConfigData;
+
+ ConfigData = AllocateZeroPool (sizeof (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER) * NumberOfProcessors);
+ ASSERT (ConfigData != NULL);
+ return ConfigData;
+}
+
+/**
+ Detects if Protected Processor Inventory Number feature supported on current
+ processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE Protected Processor Inventory Number feature is supported.
+ @retval FALSE Protected Processor Inventory Number feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+PpinSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ )
+{
+ MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER PlatformInfo;
+ MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl;
+
+ if ((CpuInfo->DisplayFamily == 0x06) &&
+ ((CpuInfo->DisplayModel == 0x3E) || // Xeon E5 V2
+ (CpuInfo->DisplayModel == 0x56) || // Xeon Processor D Product
+ (CpuInfo->DisplayModel == 0x4F) || // Xeon E5 v4, E7 v4
+ (CpuInfo->DisplayModel == 0x55) || // Xeon Processor Scalable
+ (CpuInfo->DisplayModel == 0x57) || // Xeon Phi processor 3200, 5200, 7200 series.
+ (CpuInfo->DisplayModel == 0x85) // Future Xeon phi processor
+ )) {
+ //
+ // Check whether platform support this feature.
+ //
+ PlatformInfo.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);
+ if (PlatformInfo.Bits.PPIN_CAP != 0) {
+ MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *) ConfigData;
+ ASSERT (MsrPpinCtrl != NULL);
+ MsrPpinCtrl[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);
+ return TRUE;
+ }
+ }
+
+ return FALSE;
+}
+
+/**
+ Initializes Protected Processor Inventory Number feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the Protected Processor Inventory
+ Number feature must be enabled.
+ If FALSE, then the Protected Processor Inventory
+ Number feature must be disabled.
+
+ @retval RETURN_SUCCESS Protected Processor Inventory Number feature is
+ initialized.
+ @retval RETURN_DEVICE_ERROR Device can't change state because it has been
+ locked.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+PpinInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ )
+{
+ MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl;
+
+ MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *) ConfigData;
+ ASSERT (MsrPpinCtrl != NULL);
+
+ //
+ // Check whether processor already lock this register.
+ // If already locked, just based on the request state and
+ // the current state to return the status.
+ //
+ if (MsrPpinCtrl[ProcessorNumber].Bits.LockOut != 0) {
+ return MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN == State ? RETURN_SUCCESS : RETURN_DEVICE_ERROR;
+ }
+
+ //
+ // Support function already check the processor which support PPIN feature, so this function not need
+ // to check the processor again.
+ //
+ // The scope of the MSR_IVY_BRIDGE_PPIN_CTL is package level, only program MSR_IVY_BRIDGE_PPIN_CTL for
+ // thread 0 core 0 in each package.
+ //
+ if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo->ProcessorInfo.Location.Core != 0)) {
+ return RETURN_SUCCESS;
+ }
+
+ if (State) {
+ //
+ // Enable and Unlock.
+ // According to SDM, once Enable_PPIN is set, attempt to write 1 to LockOut will cause #GP.
+ //
+ MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 1;
+ MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 0;
+ } else {
+ //
+ // Disable and Lock.
+ // According to SDM, writing 1 to LockOut is permitted only if Enable_PPIN is clear.
+ //
+ MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 0;
+ MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 1;
+ }
+
+ CPU_REGISTER_TABLE_WRITE64 (
+ ProcessorNumber,
+ Msr,
+ MSR_IVY_BRIDGE_PPIN_CTL,
+ MsrPpinCtrl[ProcessorNumber].Uint64
+ );
+
+ return RETURN_SUCCESS;
+}
diff --git a/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c new file mode 100644 index 000000000..611459105 --- /dev/null +++ b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c @@ -0,0 +1,473 @@ +/** @file
+ Intel Processor Trace feature.
+
+ Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "CpuCommonFeatures.h"
+
+///
+/// This macro define the max entries in the Topa table.
+/// Each entry in the table contains some attribute bits, a pointer to an output region, and the size of the region.
+/// The last entry in the table may hold a pointer to the next table. This pointer can either point to the top of the
+/// current table (for circular array) or to the base of another table.
+/// At least 2 entries are needed because the list of entries must
+/// be terminated by an entry with the END bit set to 1, so 2
+/// entries are required to use a single valid entry.
+///
+#define MAX_TOPA_ENTRY_COUNT 2
+
+
+///
+/// Processor trace output scheme selection.
+///
+typedef enum {
+ RtitOutputSchemeSingleRange = 0,
+ RtitOutputSchemeToPA
+} RTIT_OUTPUT_SCHEME;
+
+typedef struct {
+ BOOLEAN TopaSupported;
+ BOOLEAN SingleRangeSupported;
+ MSR_IA32_RTIT_CTL_REGISTER RtitCtrl;
+ MSR_IA32_RTIT_OUTPUT_BASE_REGISTER RtitOutputBase;
+ MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER RtitOutputMaskPtrs;
+} PROC_TRACE_PROCESSOR_DATA;
+
+typedef struct {
+ UINT32 NumberOfProcessors;
+
+ UINT8 ProcTraceOutputScheme;
+ UINT32 ProcTraceMemSize;
+
+ UINTN *ThreadMemRegionTable;
+ UINTN AllocatedThreads;
+
+ UINTN *TopaMemArray;
+
+ PROC_TRACE_PROCESSOR_DATA *ProcessorData;
+} PROC_TRACE_DATA;
+
+typedef struct {
+ RTIT_TOPA_TABLE_ENTRY TopaEntry[MAX_TOPA_ENTRY_COUNT];
+} PROC_TRACE_TOPA_TABLE;
+
+/**
+ Prepares for the data used by CPU feature detection and initialization.
+
+ @param[in] NumberOfProcessors The number of CPUs in the platform.
+
+ @return Pointer to a buffer of CPU related configuration data.
+
+ @note This service could be called by BSP only.
+**/
+VOID *
+EFIAPI
+ProcTraceGetConfigData (
+ IN UINTN NumberOfProcessors
+ )
+{
+ PROC_TRACE_DATA *ConfigData;
+
+ ConfigData = AllocateZeroPool (sizeof (PROC_TRACE_DATA) + sizeof (PROC_TRACE_PROCESSOR_DATA) * NumberOfProcessors);
+ ASSERT (ConfigData != NULL);
+ ConfigData->ProcessorData = (PROC_TRACE_PROCESSOR_DATA *) ((UINT8*) ConfigData + sizeof (PROC_TRACE_DATA));
+
+ ConfigData->NumberOfProcessors = (UINT32) NumberOfProcessors;
+ ConfigData->ProcTraceMemSize = PcdGet32 (PcdCpuProcTraceMemSize);
+ ConfigData->ProcTraceOutputScheme = PcdGet8 (PcdCpuProcTraceOutputScheme);
+
+ return ConfigData;
+}
+
+/**
+ Detects if Intel Processor Trace feature supported on current
+ processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE Processor Trace feature is supported.
+ @retval FALSE Processor Trace feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+ProcTraceSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ )
+{
+ PROC_TRACE_DATA *ProcTraceData;
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
+ CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;
+
+ //
+ // Check if ProcTraceMemorySize option is enabled (0xFF means disable by user)
+ //
+ ProcTraceData = (PROC_TRACE_DATA *) ConfigData;
+ ASSERT (ProcTraceData != NULL);
+ if ((ProcTraceData->ProcTraceMemSize > RtitTopaMemorySize128M) ||
+ (ProcTraceData->ProcTraceOutputScheme > RtitOutputSchemeToPA)) {
+ return FALSE;
+ }
+
+ //
+ // Check if Processor Trace is supported
+ //
+ AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, NULL, &Ebx.Uint32, NULL, NULL);
+ if (Ebx.Bits.IntelProcessorTrace == 0) {
+ return FALSE;
+ }
+
+ AsmCpuidEx (CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, NULL, NULL, &Ecx.Uint32, NULL);
+ ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported = (BOOLEAN) (Ecx.Bits.RTIT == 1);
+ ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported = (BOOLEAN) (Ecx.Bits.SingleRangeOutput == 1);
+ if ((ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) ||
+ (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange))) {
+ ProcTraceData->ProcessorData[ProcessorNumber].RtitCtrl.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
+ ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);
+ ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+/**
+ Initializes Intel Processor Trace feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the Processor Trace feature must be
+ enabled.
+ If FALSE, then the Processor Trace feature must be
+ disabled.
+
+ @retval RETURN_SUCCESS Intel Processor Trace feature is initialized.
+
+**/
+RETURN_STATUS
+EFIAPI
+ProcTraceInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ )
+{
+ UINT32 MemRegionSize;
+ UINTN Pages;
+ UINTN Alignment;
+ UINTN MemRegionBaseAddr;
+ UINTN *ThreadMemRegionTable;
+ UINTN Index;
+ UINTN TopaTableBaseAddr;
+ UINTN AlignedAddress;
+ UINTN *TopaMemArray;
+ PROC_TRACE_TOPA_TABLE *TopaTable;
+ PROC_TRACE_DATA *ProcTraceData;
+ BOOLEAN FirstIn;
+ MSR_IA32_RTIT_CTL_REGISTER CtrlReg;
+ MSR_IA32_RTIT_STATUS_REGISTER StatusReg;
+ MSR_IA32_RTIT_OUTPUT_BASE_REGISTER OutputBaseReg;
+ MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER OutputMaskPtrsReg;
+ RTIT_TOPA_TABLE_ENTRY *TopaEntryPtr;
+
+ //
+ // The scope of the MSR_IA32_RTIT_* is core for below processor type, only program
+ // MSR_IA32_RTIT_* for thread 0 in each core.
+ //
+ if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+ if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
+ return RETURN_SUCCESS;
+ }
+ }
+
+ ProcTraceData = (PROC_TRACE_DATA *) ConfigData;
+ ASSERT (ProcTraceData != NULL);
+
+ //
+ // Clear MSR_IA32_RTIT_CTL[0] and IA32_RTIT_STS only if MSR_IA32_RTIT_CTL[0]==1b
+ //
+ CtrlReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitCtrl.Uint64;
+ if (CtrlReg.Bits.TraceEn != 0) {
+ ///
+ /// Clear bit 0 in MSR IA32_RTIT_CTL (570)
+ ///
+ CtrlReg.Bits.TraceEn = 0;
+ CPU_REGISTER_TABLE_WRITE64 (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_RTIT_CTL,
+ CtrlReg.Uint64
+ );
+
+ ///
+ /// Clear MSR IA32_RTIT_STS (571h) to all zeros
+ ///
+ StatusReg.Uint64 = 0x0;
+ CPU_REGISTER_TABLE_WRITE64 (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_RTIT_STATUS,
+ StatusReg.Uint64
+ );
+ }
+
+ if (!State) {
+ return RETURN_SUCCESS;
+ }
+
+ MemRegionBaseAddr = 0;
+ FirstIn = FALSE;
+
+ if (ProcTraceData->ThreadMemRegionTable == NULL) {
+ FirstIn = TRUE;
+ DEBUG ((DEBUG_INFO, "Initialize Processor Trace\n"));
+ }
+
+ ///
+ /// Refer to PROC_TRACE_MEM_SIZE Table for Size Encoding
+ ///
+ MemRegionSize = (UINT32) (1 << (ProcTraceData->ProcTraceMemSize + 12));
+ if (FirstIn) {
+ DEBUG ((DEBUG_INFO, "ProcTrace: MemSize requested: 0x%X \n", MemRegionSize));
+ }
+
+ if (FirstIn) {
+ //
+ // Let BSP allocate and create the necessary memory region (Aligned to the size of
+ // the memory region from setup option(ProcTraceMemSize) which is an integral multiple of 4kB)
+ // for all the enabled threads to store Processor Trace debug data. Then Configure the trace
+ // address base in MSR, IA32_RTIT_OUTPUT_BASE (560h) bits 47:12. Note that all regions must be
+ // aligned based on their size, not just 4K. Thus a 2M region must have bits 20:12 cleared.
+ //
+ ThreadMemRegionTable = (UINTN *) AllocatePool (ProcTraceData->NumberOfProcessors * sizeof (UINTN *));
+ if (ThreadMemRegionTable == NULL) {
+ DEBUG ((DEBUG_ERROR, "Allocate ProcTrace ThreadMemRegionTable Failed\n"));
+ return RETURN_OUT_OF_RESOURCES;
+ }
+ ProcTraceData->ThreadMemRegionTable = ThreadMemRegionTable;
+
+ for (Index = 0; Index < ProcTraceData->NumberOfProcessors; Index++, ProcTraceData->AllocatedThreads++) {
+ Pages = EFI_SIZE_TO_PAGES (MemRegionSize);
+ Alignment = MemRegionSize;
+ AlignedAddress = (UINTN) AllocateAlignedReservedPages (Pages, Alignment);
+ if (AlignedAddress == 0) {
+ DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocated only for %d threads\n", ProcTraceData->AllocatedThreads));
+ if (Index == 0) {
+ //
+ // Could not allocate for BSP even
+ //
+ FreePool ((VOID *) ThreadMemRegionTable);
+ ThreadMemRegionTable = NULL;
+ return RETURN_OUT_OF_RESOURCES;
+ }
+ break;
+ }
+
+ ThreadMemRegionTable[Index] = AlignedAddress;
+ DEBUG ((DEBUG_INFO, "ProcTrace: PT MemRegionBaseAddr(aligned) for thread %d: 0x%llX \n", Index, (UINT64) ThreadMemRegionTable[Index]));
+ }
+
+ DEBUG ((DEBUG_INFO, "ProcTrace: Allocated PT mem for %d thread \n", ProcTraceData->AllocatedThreads));
+ }
+
+ if (ProcessorNumber < ProcTraceData->AllocatedThreads) {
+ MemRegionBaseAddr = ProcTraceData->ThreadMemRegionTable[ProcessorNumber];
+ } else {
+ return RETURN_SUCCESS;
+ }
+
+ ///
+ /// Check Processor Trace output scheme: Single Range output or ToPA table
+ ///
+
+ //
+ // Single Range output scheme
+ //
+ if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported &&
+ (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)) {
+ if (FirstIn) {
+ DEBUG ((DEBUG_INFO, "ProcTrace: Enabling Single Range Output scheme \n"));
+ }
+
+ //
+ // Clear MSR IA32_RTIT_CTL (0x570) ToPA (Bit 8)
+ //
+ CtrlReg.Bits.ToPA = 0;
+ CPU_REGISTER_TABLE_WRITE64 (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_RTIT_CTL,
+ CtrlReg.Uint64
+ );
+
+ //
+ // Program MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with the allocated Memory Region
+ //
+ OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64;
+ OutputBaseReg.Bits.Base = (MemRegionBaseAddr >> 7) & 0x01FFFFFF;
+ OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64) MemRegionBaseAddr, 32) & 0xFFFFFFFF;
+ CPU_REGISTER_TABLE_WRITE64 (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_RTIT_OUTPUT_BASE,
+ OutputBaseReg.Uint64
+ );
+
+ //
+ // Program the Mask bits for the Memory Region to MSR IA32_RTIT_OUTPUT_MASK_PTRS (561h)
+ //
+ OutputMaskPtrsReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64;
+ OutputMaskPtrsReg.Bits.MaskOrTableOffset = ((MemRegionSize - 1) >> 7) & 0x01FFFFFF;
+ OutputMaskPtrsReg.Bits.OutputOffset = RShiftU64 (MemRegionSize - 1, 32) & 0xFFFFFFFF;
+ CPU_REGISTER_TABLE_WRITE64 (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_RTIT_OUTPUT_MASK_PTRS,
+ OutputMaskPtrsReg.Uint64
+ );
+ }
+
+ //
+ // ToPA(Table of physical address) scheme
+ //
+ if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported &&
+ (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) {
+ //
+ // Create ToPA structure aligned at 4KB for each logical thread
+ // with at least 2 entries by 8 bytes size each. The first entry
+ // should have the trace output base address in bits 47:12, 6:9
+ // for Size, bits 4,2 and 0 must be cleared. The second entry
+ // should have the base address of the table location in bits
+ // 47:12, bits 4 and 2 must be cleared and bit 0 must be set.
+ //
+ if (FirstIn) {
+ DEBUG ((DEBUG_INFO, "ProcTrace: Enabling ToPA scheme \n"));
+ //
+ // Let BSP allocate ToPA table mem for all threads
+ //
+ TopaMemArray = (UINTN *) AllocatePool (ProcTraceData->AllocatedThreads * sizeof (UINTN *));
+ if (TopaMemArray == NULL) {
+ DEBUG ((DEBUG_ERROR, "ProcTrace: Allocate mem for ToPA Failed\n"));
+ return RETURN_OUT_OF_RESOURCES;
+ }
+ ProcTraceData->TopaMemArray = TopaMemArray;
+
+ for (Index = 0; Index < ProcTraceData->AllocatedThreads; Index++) {
+ Pages = EFI_SIZE_TO_PAGES (sizeof (PROC_TRACE_TOPA_TABLE));
+ Alignment = 0x1000;
+ AlignedAddress = (UINTN) AllocateAlignedReservedPages (Pages, Alignment);
+ if (AlignedAddress == 0) {
+ if (Index < ProcTraceData->AllocatedThreads) {
+ ProcTraceData->AllocatedThreads = Index;
+ }
+ DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocated ToPA mem only for %d threads\n", ProcTraceData->AllocatedThreads));
+ if (Index == 0) {
+ //
+ // Could not allocate for BSP even
+ //
+ FreePool ((VOID *) TopaMemArray);
+ TopaMemArray = NULL;
+ return RETURN_OUT_OF_RESOURCES;
+ }
+ break;
+ }
+
+ TopaMemArray[Index] = AlignedAddress;
+ DEBUG ((DEBUG_INFO, "ProcTrace: Topa table address(aligned) for thread %d is 0x%llX \n", Index, (UINT64) TopaMemArray[Index]));
+ }
+
+ DEBUG ((DEBUG_INFO, "ProcTrace: Allocated ToPA mem for %d thread \n", ProcTraceData->AllocatedThreads));
+ }
+
+ if (ProcessorNumber < ProcTraceData->AllocatedThreads) {
+ TopaTableBaseAddr = ProcTraceData->TopaMemArray[ProcessorNumber];
+ } else {
+ return RETURN_SUCCESS;
+ }
+
+ TopaTable = (PROC_TRACE_TOPA_TABLE *) TopaTableBaseAddr;
+ TopaEntryPtr = &TopaTable->TopaEntry[0];
+ TopaEntryPtr->Uint64 = 0;
+ TopaEntryPtr->Bits.Base = (MemRegionBaseAddr >> 12) & 0x000FFFFF;
+ TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64) MemRegionBaseAddr, 32) & 0xFFFFFFFF;
+ TopaEntryPtr->Bits.Size = ProcTraceData->ProcTraceMemSize;
+ TopaEntryPtr->Bits.END = 0;
+
+ TopaEntryPtr = &TopaTable->TopaEntry[1];
+ TopaEntryPtr->Uint64 = 0;
+ TopaEntryPtr->Bits.Base = (TopaTableBaseAddr >> 12) & 0x000FFFFF;
+ TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64) TopaTableBaseAddr, 32) & 0xFFFFFFFF;
+ TopaEntryPtr->Bits.END = 1;
+
+ //
+ // Program the MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with ToPA base
+ //
+ OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64;
+ OutputBaseReg.Bits.Base = (TopaTableBaseAddr >> 7) & 0x01FFFFFF;
+ OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64) TopaTableBaseAddr, 32) & 0xFFFFFFFF;
+ CPU_REGISTER_TABLE_WRITE64 (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_RTIT_OUTPUT_BASE,
+ OutputBaseReg.Uint64
+ );
+
+ //
+ // Set the MSR IA32_RTIT_OUTPUT_MASK (0x561) bits[63:7] to 0
+ //
+ OutputMaskPtrsReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64;
+ OutputMaskPtrsReg.Bits.MaskOrTableOffset = 0;
+ OutputMaskPtrsReg.Bits.OutputOffset = 0;
+ CPU_REGISTER_TABLE_WRITE64 (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_RTIT_OUTPUT_MASK_PTRS,
+ OutputMaskPtrsReg.Uint64
+ );
+ //
+ // Enable ToPA output scheme by enabling MSR IA32_RTIT_CTL (0x570) ToPA (Bit 8)
+ //
+ CtrlReg.Bits.ToPA = 1;
+ CPU_REGISTER_TABLE_WRITE64 (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_RTIT_CTL,
+ CtrlReg.Uint64
+ );
+ }
+
+ ///
+ /// Enable the Processor Trace feature from MSR IA32_RTIT_CTL (570h)
+ ///
+ CtrlReg.Bits.OS = 1;
+ CtrlReg.Bits.User = 1;
+ CtrlReg.Bits.BranchEn = 1;
+ CtrlReg.Bits.TraceEn = 1;
+ CPU_REGISTER_TABLE_WRITE64 (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_RTIT_CTL,
+ CtrlReg.Uint64
+ );
+
+ return RETURN_SUCCESS;
+}
diff --git a/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c new file mode 100644 index 000000000..44b07749f --- /dev/null +++ b/roms/edk2/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c @@ -0,0 +1,137 @@ +/** @file
+ X2Apic feature.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "CpuCommonFeatures.h"
+
+/**
+ Prepares for the data used by CPU feature detection and initialization.
+
+ @param[in] NumberOfProcessors The number of CPUs in the platform.
+
+ @return Pointer to a buffer of CPU related configuration data.
+
+ @note This service could be called by BSP only.
+**/
+VOID *
+EFIAPI
+X2ApicGetConfigData (
+ IN UINTN NumberOfProcessors
+ )
+{
+ BOOLEAN *ConfigData;
+
+ ConfigData = AllocateZeroPool (sizeof (BOOLEAN) * NumberOfProcessors);
+ ASSERT (ConfigData != NULL);
+ return ConfigData;
+}
+
+/**
+ Detects if X2Apci feature supported on current processor.
+
+ Detect if X2Apci has been already enabled.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE X2Apci feature is supported.
+ @retval FALSE X2Apci feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+X2ApicSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ )
+{
+ BOOLEAN *X2ApicEnabled;
+
+ ASSERT (ConfigData != NULL);
+ X2ApicEnabled = (BOOLEAN *) ConfigData;
+ //
+ // *ConfigData indicates if X2APIC enabled on current processor
+ //
+ X2ApicEnabled[ProcessorNumber] = (GetApicMode () == LOCAL_APIC_MODE_X2APIC) ? TRUE : FALSE;
+
+ return (CpuInfo->CpuIdVersionInfoEcx.Bits.x2APIC == 1);
+}
+
+/**
+ Initializes X2Apci feature to specific state.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+ @param[in] State If TRUE, then the X2Apci feature must be enabled.
+ If FALSE, then the X2Apci feature must be disabled.
+
+ @retval RETURN_SUCCESS X2Apci feature is initialized.
+
+ @note This service could be called by BSP only.
+**/
+RETURN_STATUS
+EFIAPI
+X2ApicInitialize (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData, OPTIONAL
+ IN BOOLEAN State
+ )
+{
+ BOOLEAN *X2ApicEnabled;
+
+ //
+ // The scope of the MSR_IA32_APIC_BASE is core for below processor type, only program
+ // MSR_IA32_APIC_BASE for thread 0 in each core.
+ //
+ if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+ if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
+ return RETURN_SUCCESS;
+ }
+ }
+
+ ASSERT (ConfigData != NULL);
+ X2ApicEnabled = (BOOLEAN *) ConfigData;
+ if (X2ApicEnabled[ProcessorNumber]) {
+ PRE_SMM_CPU_REGISTER_TABLE_WRITE_FIELD (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_APIC_BASE,
+ MSR_IA32_APIC_BASE_REGISTER,
+ Bits.EXTD,
+ 1
+ );
+ } else {
+ //
+ // Enable X2APIC mode only if X2APIC is not enabled,
+ // Needn't to disabe X2APIC mode again if X2APIC is not enabled
+ //
+ if (State) {
+ CPU_REGISTER_TABLE_WRITE_FIELD (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_APIC_BASE,
+ MSR_IA32_APIC_BASE_REGISTER,
+ Bits.EXTD,
+ 1
+ );
+ }
+ }
+ return RETURN_SUCCESS;
+}
|