diff options
| author |   Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
|---|---|---|
| committer | Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
| commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
| tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32 | |
| parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) | |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32')
4 files changed, 337 insertions, 0 deletions
diff --git a/roms/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm b/roms/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm new file mode 100644 index 000000000..6891397c2 --- /dev/null +++ b/roms/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm @@ -0,0 +1,39 @@ +;------------------------------------------------------------------------------
+; @file
+; Transition from 32 bit flat protected mode into 64 bit flat protected mode
+;
+; Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+BITS 32
+
+;
+; Modified: EAX
+;
+Transition32FlatTo64Flat:
+
+ OneTimeCall SetCr3ForPageTables64
+
+ mov eax, cr4
+ bts eax, 5 ; enable PAE
+ mov cr4, eax
+
+ mov ecx, 0xc0000080
+ rdmsr
+ bts eax, 8 ; set LME
+ wrmsr
+
+ mov eax, cr0
+ bts eax, 31 ; set PG
+ mov cr0, eax ; enable paging
+
+ jmp LINEAR_CODE64_SEL:ADDR_OF(jumpTo64BitAndLandHere)
+BITS 64
+jumpTo64BitAndLandHere:
+
+ debugShowPostCode POSTCODE_64BIT_MODE
+
+ OneTimeCallRet Transition32FlatTo64Flat
+
diff --git a/roms/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm b/roms/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm new file mode 100644 index 000000000..87a4125d4 --- /dev/null +++ b/roms/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm @@ -0,0 +1,24 @@ +;------------------------------------------------------------------------------
+; @file
+; Sets the CR3 register for 64-bit paging
+;
+; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+BITS 32
+
+;
+; Modified: EAX
+;
+SetCr3ForPageTables64:
+
+ ;
+ ; These pages are built into the ROM image in X64/PageTables.asm
+ ;
+ mov eax, ADDR_OF(TopLevelPageDirectory)
+ mov cr3, eax
+
+ OneTimeCallRet SetCr3ForPageTables64
+
diff --git a/roms/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32/SearchForBfvBase.asm b/roms/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32/SearchForBfvBase.asm new file mode 100644 index 000000000..10f8e3e8b --- /dev/null +++ b/roms/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32/SearchForBfvBase.asm @@ -0,0 +1,80 @@ +;------------------------------------------------------------------------------
+; @file
+; Search for the Boot Firmware Volume (BFV) base address
+;
+; Copyright (c) 2008 - 2009, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+;#define EFI_FIRMWARE_FILE_SYSTEM2_GUID \
+; { 0x8c8ce578, 0x8a3d, 0x4f1c, { 0x99, 0x35, 0x89, 0x61, 0x85, 0xc3, 0x2d, 0xd3 } }
+%define FFS_GUID_DWORD0 0x8c8ce578
+%define FFS_GUID_DWORD1 0x4f1c8a3d
+%define FFS_GUID_DWORD2 0x61893599
+%define FFS_GUID_DWORD3 0xd32dc385
+
+BITS 32
+
+;
+; Modified: EAX, EBX
+; Preserved: EDI, ESP
+;
+; @param[out] EBP Address of Boot Firmware Volume (BFV)
+;
+Flat32SearchForBfvBase:
+
+ xor eax, eax
+searchingForBfvHeaderLoop:
+ ;
+ ; We check for a firmware volume at every 4KB address in the top 16MB
+ ; just below 4GB. (Addresses at 0xffHHH000 where H is any hex digit.)
+ ;
+ sub eax, 0x1000
+ cmp eax, 0xff000000
+ jb searchedForBfvHeaderButNotFound
+
+ ;
+ ; Check FFS GUID
+ ;
+ cmp dword [eax + 0x10], FFS_GUID_DWORD0
+ jne searchingForBfvHeaderLoop
+ cmp dword [eax + 0x14], FFS_GUID_DWORD1
+ jne searchingForBfvHeaderLoop
+ cmp dword [eax + 0x18], FFS_GUID_DWORD2
+ jne searchingForBfvHeaderLoop
+ cmp dword [eax + 0x1c], FFS_GUID_DWORD3
+ jne searchingForBfvHeaderLoop
+
+ ;
+ ; Check FV Length
+ ;
+ cmp dword [eax + 0x24], 0
+ jne searchingForBfvHeaderLoop
+ mov ebx, eax
+ add ebx, dword [eax + 0x20]
+ jnz searchingForBfvHeaderLoop
+
+ jmp searchedForBfvHeaderAndItWasFound
+
+searchedForBfvHeaderButNotFound:
+ ;
+ ; Hang if the SEC entry point was not found
+ ;
+ debugShowPostCode POSTCODE_BFV_NOT_FOUND
+
+ ;
+ ; 0xbfbfbfbf in the EAX & EBP registers helps signal what failed
+ ; for debugging purposes.
+ ;
+ mov eax, 0xBFBFBFBF
+ mov ebp, eax
+ jmp $
+
+searchedForBfvHeaderAndItWasFound:
+ mov ebp, eax
+
+ debugShowPostCode POSTCODE_BFV_FOUND
+
+ OneTimeCallRet Flat32SearchForBfvBase
+
diff --git a/roms/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32/SearchForSecEntry.asm b/roms/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32/SearchForSecEntry.asm new file mode 100644 index 000000000..904c22df2 --- /dev/null +++ b/roms/edk2/UefiCpuPkg/ResetVector/Vtf0/Ia32/SearchForSecEntry.asm @@ -0,0 +1,194 @@ +;------------------------------------------------------------------------------
+; @file
+; Search for the SEC Core entry point
+;
+; Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+BITS 32
+
+%define EFI_FV_FILETYPE_SECURITY_CORE 0x03
+
+;
+; Modified: EAX, EBX, ECX, EDX
+; Preserved: EDI, EBP, ESP
+;
+; @param[in] EBP Address of Boot Firmware Volume (BFV)
+; @param[out] ESI SEC Core Entry Point Address
+;
+Flat32SearchForSecEntryPoint:
+
+ ;
+ ; Initialize EBP and ESI to 0
+ ;
+ xor ebx, ebx
+ mov esi, ebx
+
+ ;
+ ; Pass over the BFV header
+ ;
+ mov eax, ebp
+ mov bx, [ebp + 0x30]
+ add eax, ebx
+ jc secEntryPointWasNotFound
+
+ jmp searchingForFfsFileHeaderLoop
+
+moveForwardWhileSearchingForFfsFileHeaderLoop:
+ ;
+ ; Make forward progress in the search
+ ;
+ inc eax
+ jc secEntryPointWasNotFound
+
+searchingForFfsFileHeaderLoop:
+ test eax, eax
+ jz secEntryPointWasNotFound
+
+ ;
+ ; Ensure 8 byte alignment
+ ;
+ add eax, 7
+ jc secEntryPointWasNotFound
+ and al, 0xf8
+
+ ;
+ ; Look to see if there is an FFS file at eax
+ ;
+ mov bl, [eax + 0x17]
+ test bl, 0x20
+ jz moveForwardWhileSearchingForFfsFileHeaderLoop
+ mov ecx, [eax + 0x14]
+ and ecx, 0x00ffffff
+ or ecx, ecx
+ jz moveForwardWhileSearchingForFfsFileHeaderLoop
+ add ecx, eax
+ jz jumpSinceWeFoundTheLastFfsFile
+ jc moveForwardWhileSearchingForFfsFileHeaderLoop
+jumpSinceWeFoundTheLastFfsFile:
+
+ ;
+ ; There seems to be a valid file at eax
+ ;
+ cmp byte [eax + 0x12], EFI_FV_FILETYPE_SECURITY_CORE ; Check File Type
+ jne readyToTryFfsFileAtEcx
+
+fileTypeIsSecCore:
+ OneTimeCall GetEntryPointOfFfsFile
+ test eax, eax
+ jnz doneSeachingForSecEntryPoint
+
+readyToTryFfsFileAtEcx:
+ ;
+ ; Try the next FFS file at ECX
+ ;
+ mov eax, ecx
+ jmp searchingForFfsFileHeaderLoop
+
+secEntryPointWasNotFound:
+ xor eax, eax
+
+doneSeachingForSecEntryPoint:
+ mov esi, eax
+
+ test esi, esi
+ jnz secCoreEntryPointWasFound
+
+secCoreEntryPointWasNotFound:
+ ;
+ ; Hang if the SEC entry point was not found
+ ;
+ debugShowPostCode POSTCODE_SEC_NOT_FOUND
+ jz $
+
+secCoreEntryPointWasFound:
+ debugShowPostCode POSTCODE_SEC_FOUND
+
+ OneTimeCallRet Flat32SearchForSecEntryPoint
+
+%define EFI_SECTION_PE32 0x10
+%define EFI_SECTION_TE 0x12
+
+;
+; Input:
+; EAX - Start of FFS file
+; ECX - End of FFS file
+;
+; Output:
+; EAX - Entry point of PE32 (or 0 if not found)
+;
+; Modified:
+; EBX
+;
+GetEntryPointOfFfsFile:
+ test eax, eax
+ jz getEntryPointOfFfsFileErrorReturn
+ add eax, 0x18 ; EAX = Start of section
+
+getEntryPointOfFfsFileLoopForSections:
+ cmp eax, ecx
+ jae getEntryPointOfFfsFileErrorReturn
+
+ cmp byte [eax + 3], EFI_SECTION_PE32
+ je getEntryPointOfFfsFileFoundPe32Section
+
+ cmp byte [eax + 3], EFI_SECTION_TE
+ je getEntryPointOfFfsFileFoundTeSection
+
+ ;
+ ; The section type was not PE32 or TE, so move to next section
+ ;
+ mov ebx, dword [eax]
+ and ebx, 0x00ffffff
+ add eax, ebx
+ jc getEntryPointOfFfsFileErrorReturn
+
+ ;
+ ; Ensure that FFS section is 32-bit aligned
+ ;
+ add eax, 3
+ jc getEntryPointOfFfsFileErrorReturn
+ and al, 0xfc
+ jmp getEntryPointOfFfsFileLoopForSections
+
+getEntryPointOfFfsFileFoundPe32Section:
+ add eax, 4 ; EAX = Start of PE32 image
+
+ cmp word [eax], 'MZ'
+ jne getEntryPointOfFfsFileErrorReturn
+ movzx ebx, word [eax + 0x3c]
+ add ebx, eax
+
+ ; if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE)
+ cmp dword [ebx], `PE\x00\x00`
+ jne getEntryPointOfFfsFileErrorReturn
+
+ ; *EntryPoint = (VOID *)((UINTN)Pe32Data +
+ ; (UINTN)(Hdr.Pe32->OptionalHeader.AddressOfEntryPoint & 0x0ffffffff));
+ add eax, [ebx + 0x4 + 0x14 + 0x10]
+ jmp getEntryPointOfFfsFileReturn
+
+getEntryPointOfFfsFileFoundTeSection:
+ add eax, 4 ; EAX = Start of TE image
+ mov ebx, eax
+
+ ; if (Hdr.Te->Signature == EFI_TE_IMAGE_HEADER_SIGNATURE)
+ cmp word [ebx], 'VZ'
+ jne getEntryPointOfFfsFileErrorReturn
+ ; *EntryPoint = (VOID *)((UINTN)Pe32Data +
+ ; (UINTN)(Hdr.Te->AddressOfEntryPoint & 0x0ffffffff) +
+ ; sizeof(EFI_TE_IMAGE_HEADER) - Hdr.Te->StrippedSize);
+ add eax, [ebx + 0x8]
+ add eax, 0x28
+ movzx ebx, word [ebx + 0x6]
+ sub eax, ebx
+ jmp getEntryPointOfFfsFileReturn
+
+getEntryPointOfFfsFileErrorReturn:
+ mov eax, 0
+
+getEntryPointOfFfsFileReturn:
+ OneTimeCallRet GetEntryPointOfFfsFile
+
|