Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

4 files changed, 306 insertions, 0 deletions

diff --git a/roms/opensbi/lib/utils/irqchip/fdt_irqchip.c b/roms/opensbi/lib/utils/irqchip/fdt_irqchip.c
new file mode 100644
index 000000000..3630be657
--- /dev/null
+++ b/roms/opensbi/lib/utils/irqchip/fdt_irqchip.c
@@ -0,0 +1,74 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#include <sbi/sbi_scratch.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/irqchip/fdt_irqchip.h>
+
+extern struct fdt_irqchip fdt_irqchip_plic;
+
+static struct fdt_irqchip *irqchip_drivers[] = {
+	&fdt_irqchip_plic
+};
+
+static struct fdt_irqchip *current_driver = NULL;
+
+void fdt_irqchip_exit(void)
+{
+	if (current_driver && current_driver->exit)
+		current_driver->exit();
+}
+
+static int fdt_irqchip_warm_init(void)
+{
+	if (current_driver && current_driver->warm_init)
+		return current_driver->warm_init();
+	return 0;
+}
+
+static int fdt_irqchip_cold_init(void)
+{
+	int pos, noff, rc;
+	struct fdt_irqchip *drv;
+	const struct fdt_match *match;
+	void *fdt = sbi_scratch_thishart_arg1_ptr();
+
+	for (pos = 0; pos < array_size(irqchip_drivers); pos++) {
+		drv = irqchip_drivers[pos];
+
+		noff = -1;
+		while ((noff = fdt_find_match(fdt, noff,
+					drv->match_table, &match)) >= 0) {
+			if (drv->cold_init) {
+				rc = drv->cold_init(fdt, noff, match);
+				if (rc)
+					return rc;
+			}
+			current_driver = drv;
+		}
+
+		if (current_driver)
+			break;
+	}
+
+	return 0;
+}
+
+int fdt_irqchip_init(bool cold_boot)
+{
+	int rc;
+
+	if (cold_boot) {
+		rc = fdt_irqchip_cold_init();
+		if (rc)
+			return rc;
+	}
+
+	return fdt_irqchip_warm_init();
+}
diff --git a/roms/opensbi/lib/utils/irqchip/fdt_irqchip_plic.c b/roms/opensbi/lib/utils/irqchip/fdt_irqchip_plic.c
new file mode 100644
index 000000000..18d2797c9
--- /dev/null
+++ b/roms/opensbi/lib/utils/irqchip/fdt_irqchip_plic.c
@@ -0,0 +1,120 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#include <libfdt.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_hartmask.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/irqchip/fdt_irqchip.h>
+#include <sbi_utils/irqchip/plic.h>
+
+#define PLIC_MAX_NR			16
+
+static unsigned long plic_count = 0;
+static struct plic_data plic[PLIC_MAX_NR];
+
+static struct plic_data *plic_hartid2data[SBI_HARTMASK_MAX_BITS];
+static int plic_hartid2context[SBI_HARTMASK_MAX_BITS][2];
+
+static int irqchip_plic_warm_init(void)
+{
+	u32 hartid = current_hartid();
+
+	return plic_warm_irqchip_init(plic_hartid2data[hartid],
+				      plic_hartid2context[hartid][0],
+				      plic_hartid2context[hartid][1]);
+}
+
+static int irqchip_plic_update_hartid_table(void *fdt, int nodeoff,
+					    struct plic_data *pd)
+{
+	const fdt32_t *val;
+	u32 phandle, hwirq, hartid;
+	int i, err, count, cpu_offset, cpu_intc_offset;
+
+	val = fdt_getprop(fdt, nodeoff, "interrupts-extended", &count);
+	if (!val || count < sizeof(fdt32_t))
+		return SBI_EINVAL;
+	count = count / sizeof(fdt32_t);
+
+	for (i = 0; i < count; i += 2) {
+		phandle = fdt32_to_cpu(val[i]);
+		hwirq = fdt32_to_cpu(val[i + 1]);
+
+		cpu_intc_offset = fdt_node_offset_by_phandle(fdt, phandle);
+		if (cpu_intc_offset < 0)
+			continue;
+
+		cpu_offset = fdt_parent_offset(fdt, cpu_intc_offset);
+		if (cpu_intc_offset < 0)
+			continue;
+
+		err = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
+		if (err)
+			continue;
+
+		if (SBI_HARTMASK_MAX_BITS <= hartid)
+			continue;
+
+		plic_hartid2data[hartid] = pd;
+		switch (hwirq) {
+		case IRQ_M_EXT:
+			plic_hartid2context[hartid][0] = i / 2;
+			break;
+		case IRQ_S_EXT:
+			plic_hartid2context[hartid][1] = i / 2;
+			break;
+		}
+	}
+
+	return 0;
+}
+
+static int irqchip_plic_cold_init(void *fdt, int nodeoff,
+				  const struct fdt_match *match)
+{
+	int i, rc;
+	struct plic_data *pd;
+
+	if (PLIC_MAX_NR <= plic_count)
+		return SBI_ENOSPC;
+	pd = &plic[plic_count++];
+
+	rc = fdt_parse_plic_node(fdt, nodeoff, pd);
+	if (rc)
+		return rc;
+
+	rc = plic_cold_irqchip_init(pd);
+	if (rc)
+		return rc;
+
+	if (plic_count == 1) {
+		for (i = 0; i < SBI_HARTMASK_MAX_BITS; i++) {
+			plic_hartid2data[i] = NULL;
+			plic_hartid2context[i][0] = -1;
+			plic_hartid2context[i][1] = -1;
+		}
+	}
+
+	return irqchip_plic_update_hartid_table(fdt, nodeoff, pd);
+}
+
+static const struct fdt_match irqchip_plic_match[] = {
+	{ .compatible = "riscv,plic0" },
+	{ .compatible = "sifive,plic-1.0.0" },
+	{ },
+};
+
+struct fdt_irqchip fdt_irqchip_plic = {
+	.match_table = irqchip_plic_match,
+	.cold_init = irqchip_plic_cold_init,
+	.warm_init = irqchip_plic_warm_init,
+	.exit = NULL,
+};
diff --git a/roms/opensbi/lib/utils/irqchip/objects.mk b/roms/opensbi/lib/utils/irqchip/objects.mk
new file mode 100644
index 000000000..934f706b6
--- /dev/null
+++ b/roms/opensbi/lib/utils/irqchip/objects.mk
@@ -0,0 +1,12 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+# Copyright (c) 2019 Western Digital Corporation or its affiliates.
+#
+# Authors:
+#   Anup Patel <anup.patel@wdc.com>
+#
+
+libsbiutils-objs-y += irqchip/fdt_irqchip.o
+libsbiutils-objs-y += irqchip/fdt_irqchip_plic.o
+libsbiutils-objs-y += irqchip/plic.o
diff --git a/roms/opensbi/lib/utils/irqchip/plic.c b/roms/opensbi/lib/utils/irqchip/plic.c
new file mode 100644
index 000000000..7665c62ee
--- /dev/null
+++ b/roms/opensbi/lib/utils/irqchip/plic.c
@@ -0,0 +1,100 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#include <sbi/riscv_io.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_console.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_string.h>
+#include <sbi_utils/irqchip/plic.h>
+
+#define PLIC_PRIORITY_BASE 0x0
+#define PLIC_PENDING_BASE 0x1000
+#define PLIC_ENABLE_BASE 0x2000
+#define PLIC_ENABLE_STRIDE 0x80
+#define PLIC_CONTEXT_BASE 0x200000
+#define PLIC_CONTEXT_STRIDE 0x1000
+
+static void plic_set_priority(struct plic_data *plic, u32 source, u32 val)
+{
+	volatile void *plic_priority = (void *)plic->addr +
+			PLIC_PRIORITY_BASE + 4 * source;
+	writel(val, plic_priority);
+}
+
+void plic_set_thresh(struct plic_data *plic, u32 cntxid, u32 val)
+{
+	volatile void *plic_thresh;
+
+	if (!plic)
+		return;
+
+	plic_thresh = (void *)plic->addr +
+		      PLIC_CONTEXT_BASE + PLIC_CONTEXT_STRIDE * cntxid;
+	writel(val, plic_thresh);
+}
+
+void plic_set_ie(struct plic_data *plic, u32 cntxid, u32 word_index, u32 val)
+{
+	volatile void *plic_ie;
+
+	if (!plic)
+		return;
+
+	plic_ie = (void *)plic->addr +
+		   PLIC_ENABLE_BASE + PLIC_ENABLE_STRIDE * cntxid;
+	writel(val, plic_ie + word_index * 4);
+}
+
+int plic_warm_irqchip_init(struct plic_data *plic,
+			   int m_cntx_id, int s_cntx_id)
+{
+	size_t i, ie_words;
+
+	if (!plic)
+		return SBI_EINVAL;
+
+	ie_words = plic->num_src / 32 + 1;
+
+	/* By default, disable all IRQs for M-mode of target HART */
+	if (m_cntx_id > -1) {
+		for (i = 0; i < ie_words; i++)
+			plic_set_ie(plic, m_cntx_id, i, 0);
+	}
+
+	/* By default, disable all IRQs for S-mode of target HART */
+	if (s_cntx_id > -1) {
+		for (i = 0; i < ie_words; i++)
+			plic_set_ie(plic, s_cntx_id, i, 0);
+	}
+
+	/* By default, disable M-mode threshold */
+	if (m_cntx_id > -1)
+		plic_set_thresh(plic, m_cntx_id, 0x7);
+
+	/* By default, disable S-mode threshold */
+	if (s_cntx_id > -1)
+		plic_set_thresh(plic, s_cntx_id, 0x7);
+
+	return 0;
+}
+
+int plic_cold_irqchip_init(struct plic_data *plic)
+{
+	int i;
+
+	if (!plic)
+		return SBI_EINVAL;
+
+	/* Configure default priorities of all IRQs */
+	for (i = 1; i <= plic->num_src; i++)
+		plic_set_priority(plic, i, 0);
+
+	return 0;
+}