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author | 2023-10-10 14:33:42 +0000 | |
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committer | 2023-10-10 14:33:42 +0000 | |
commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi | |
parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/u-boot/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi')
-rw-r--r-- | roms/u-boot/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi b/roms/u-boot/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi new file mode 100644 index 000000000..23816da8e --- /dev/null +++ b/roms/u-boot/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1028A-QDS device tree fragment for RCW 1xxx + * + * Copyright 2019-2021 NXP Semiconductors + */ + +/* + * This setup is using a SCH-30842 card with AQR112 PHY in slot 1 for ENETC + * port 0 USXGMII. + */ +&slot1 { + #include "fsl-sch-30842.dtsi" +}; + +&enetc0 { + status = "okay"; + phy-mode = "usxgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; +}; |