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| author |   Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
|---|---|---|
| committer | Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
| commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
| tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/arch/arm/include/asm/armv8/cpu.h | |
| parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) | |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/u-boot/arch/arm/include/asm/armv8/cpu.h')
| -rw-r--r-- | roms/u-boot/arch/arm/include/asm/armv8/cpu.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arm/include/asm/armv8/cpu.h b/roms/u-boot/arch/arm/include/asm/armv8/cpu.h new file mode 100644 index 000000000..40d54dc85 --- /dev/null +++ b/roms/u-boot/arch/arm/include/asm/armv8/cpu.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#define MIDR_PARTNUM_CORTEX_A35 0xD04 +#define MIDR_PARTNUM_CORTEX_A53 0xD03 +#define MIDR_PARTNUM_CORTEX_A72 0xD08 +#define MIDR_PARTNUM_SHIFT 0x4 +#define MIDR_PARTNUM_MASK (0xFFF << 0x4) + +static inline unsigned int read_midr(void) +{ + unsigned long val; + + asm volatile("mrs %0, midr_el1" : "=r" (val)); + + return val; +} + +#define is_cortex_a35() (((read_midr() & MIDR_PARTNUM_MASK) >> \ + MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A35) +#define is_cortex_a53() (((read_midr() & MIDR_PARTNUM_MASK) >> \ + MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A53) +#define is_cortex_a72() (((read_midr() & MIDR_PARTNUM_MASK) >>\ + MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A72) |