Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

3 files changed, 235 insertions, 0 deletions

diff --git a/roms/u-boot/arch/arm/mach-mediatek/mt7629/Makefile b/roms/u-boot/arch/arm/mach-mediatek/mt7629/Makefile
new file mode 100644
index 000000000..007eb4a36
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-mediatek/mt7629/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier:	GPL-2.0
+
+obj-y += init.o
+obj-y += lowlevel_init.o
diff --git a/roms/u-boot/arch/arm/mach-mediatek/mt7629/init.c b/roms/u-boot/arch/arm/mach-mediatek/mt7629/init.c
new file mode 100644
index 000000000..0130554ff
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-mediatek/mt7629/init.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <log.h>
+#include <ram.h>
+#include <asm/arch/misc.h>
+#include <asm/global_data.h>
+#include <asm/sections.h>
+#include <dm/uclass.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+
+#include <dt-bindings/clock/mt7629-clk.h>
+
+#define L2_CFG_BASE		0x10200000
+#define L2_CFG_SIZE		0x1000
+#define L2_SHARE_CFG_MP0	0x7f0
+#define L2_SHARE_MODE_OFF	BIT(8)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mtk_pll_early_init(void)
+{
+	unsigned long pll_rates[] = {
+		[CLK_APMIXED_ARMPLL] = 1250000000,
+		[CLK_APMIXED_MAINPLL] = 1120000000,
+		[CLK_APMIXED_UNIV2PLL] = 1200000000,
+		[CLK_APMIXED_ETH1PLL] = 500000000,
+		[CLK_APMIXED_ETH2PLL] = 700000000,
+		[CLK_APMIXED_SGMIPLL] = 650000000,
+	};
+	struct udevice *dev;
+	int ret, i;
+
+	ret = uclass_get_device_by_driver(UCLASS_CLK,
+			DM_DRIVER_GET(mtk_clk_apmixedsys), &dev);
+	if (ret)
+		return ret;
+
+	/* configure default rate then enable apmixedsys */
+	for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
+		struct clk clk = { .id = i, .dev = dev };
+
+		ret = clk_set_rate(&clk, pll_rates[i]);
+		if (ret)
+			return ret;
+
+		ret = clk_enable(&clk);
+		if (ret)
+			return ret;
+	}
+
+	/* setup mcu bus */
+	ret = uclass_get_device_by_driver(UCLASS_SYSCON,
+			DM_DRIVER_GET(mtk_mcucfg), &dev);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+int mtk_soc_early_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	/* initialize early clocks */
+	ret = mtk_pll_early_init();
+	if (ret)
+		return ret;
+
+	ret = uclass_first_device_err(UCLASS_RAM, &dev);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+int mach_cpu_init(void)
+{
+	void __iomem *base;
+
+	base = ioremap(L2_CFG_BASE, L2_CFG_SIZE);
+
+	/* disable L2C shared mode */
+	writel(L2_SHARE_MODE_OFF, base + L2_SHARE_CFG_MP0);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	struct ram_info ram;
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_first_device_err(UCLASS_RAM, &dev);
+	if (ret)
+		return ret;
+
+	ret = ram_get_info(dev, &ram);
+	if (ret)
+		return ret;
+
+	debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
+
+	gd->ram_size = ram.size;
+
+	return 0;
+}
+
+int print_cpuinfo(void)
+{
+	void __iomem *chipid;
+	u32 hwcode, swver;
+
+	chipid = ioremap(VER_BASE, VER_SIZE);
+	hwcode = readl(chipid + APHW_CODE);
+	swver = readl(chipid + APSW_VER);
+
+	printf("CPU:   MediaTek MT%04x E%d\n", hwcode, (swver & 0xf) + 1);
+
+	return 0;
+}
diff --git a/roms/u-boot/arch/arm/mach-mediatek/mt7629/lowlevel_init.S b/roms/u-boot/arch/arm/mach-mediatek/mt7629/lowlevel_init.S
new file mode 100644
index 000000000..0a0672cbe
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-mediatek/mt7629/lowlevel_init.S
@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#include <linux/linkage.h>
+#include <asm/proc-armv/ptrace.h>
+
+#define WAIT_CODE_SRAM_BASE	0x0010ff00
+
+#define SLAVE_JUMP_REG		0x10202034
+#define SLAVE1_MAGIC_REG	0x10202038
+#define SLAVE1_MAGIC_NUM	0x534c4131
+
+#define GIC_CPU_BASE		0x10320000
+
+ENTRY(lowlevel_init)
+
+#ifndef CONFIG_SPL_BUILD
+	/* Return to U-Boot via saved link register */
+	mov	pc, lr
+#else
+	/*
+	 * Arch timer :
+	 * set CNTFRQ = 20Mhz, set CNTVOFF = 0
+	 */
+	movw	r0, #0x2d00
+	movt	r0, #0x131
+	mcr	p15, 0, r0, c14, c0, 0
+
+	cps	#MON_MODE
+	mrc	p15, 0, r1, c1, c1, 0	@ Get Secure Config
+	orr	r0, r1, #1
+	mcr	p15, 0, r0, c1, c1, 0	@ Set Non Secure bit
+	isb
+	mov	r0, #0
+	mcrr	p15, 4, r0, r0, c14	@ CNTVOFF = 0
+	isb
+	mcr	p15, 0, r1, c1, c1, 0	@ Set Secure bit
+	isb
+	cps	#SVC_MODE
+
+	/* enable SMP bit */
+	mrc	p15, 0, r0, c1, c0, 1
+	orr	r0, r0, #0x40
+	mcr	p15, 0, r0, c1, c0, 1
+
+	/* if MP core, handle secondary cores */
+	mrc	p15, 0, r0, c0, c0, 5
+	ands	r1, r0, #0x40000000
+	bne	go			@ Go if UP
+	/* read slave CPU number */
+	ands	r0, r0, #0x0f
+	beq	go			@ Go if core0 on primary core tile
+	b	secondary
+
+go:
+	/* master CPU */
+	mov	pc, lr
+
+secondary:
+	/* enable GIC as cores will be waken up by IPI */
+	ldr	r2, =GIC_CPU_BASE
+	mov	r1, #0xf0
+	str	r1, [r2, #4]
+	mov	r1, #1
+	str	r1, [r2, #0]
+
+	ldr	r1, [r2]
+	orr	r1, #1
+	str	r1, [r2]
+
+	/* copy wait code into SRAM */
+	ldr	r0, =slave_cpu_wait
+	ldm	r0, {r1 - r8}		@ slave_cpu_wait has eight insns
+	ldr	r0, =WAIT_CODE_SRAM_BASE
+	stm	r0, {r1 - r8}
+
+	/* pass args to slave_cpu_wait */
+	ldr	r0, =SLAVE1_MAGIC_REG
+	ldr	r1, =SLAVE1_MAGIC_NUM
+
+	/* jump to wait code in SRAM */
+	ldr	pc, =WAIT_CODE_SRAM_BASE
+
+#endif
+ENDPROC(lowlevel_init)
+
+/* This function will be copied into SRAM */
+ENTRY(slave_cpu_wait)
+	wfi
+	ldr	r2, [r0]
+	cmp	r2, r1
+	bne	slave_cpu_wait
+	movw	r0, #:lower16:SLAVE_JUMP_REG
+	movt	r0, #:upper16:SLAVE_JUMP_REG
+	ldr	r1, [r0]
+	mov	pc, r1
+ENDPROC(slave_cpu_wait)