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authorAngelos Mouzakitis <a.mouzakitis@virtualopensystems.com>2023-10-10 14:33:42 +0000
committerAngelos Mouzakitis <a.mouzakitis@virtualopensystems.com>2023-10-10 14:33:42 +0000
commitaf1a266670d040d2f4083ff309d732d648afba2a (patch)
tree2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/arch/arm/mach-octeontx
parente02cda008591317b1625707ff8e115a4841aa889 (diff)
Add submodule dependency filesHEADmaster
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/u-boot/arch/arm/mach-octeontx')
-rw-r--r--roms/u-boot/arch/arm/mach-octeontx/Kconfig23
-rw-r--r--roms/u-boot/arch/arm/mach-octeontx/Makefile9
-rw-r--r--roms/u-boot/arch/arm/mach-octeontx/clock.c35
-rw-r--r--roms/u-boot/arch/arm/mach-octeontx/cpu.c77
-rw-r--r--roms/u-boot/arch/arm/mach-octeontx/lowlevel_init.S33
5 files changed, 177 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arm/mach-octeontx/Kconfig b/roms/u-boot/arch/arm/mach-octeontx/Kconfig
new file mode 100644
index 000000000..28ecf9821
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-octeontx/Kconfig
@@ -0,0 +1,23 @@
+if ARCH_OCTEONTX
+
+choice
+ prompt "OcteonTX board select"
+ optional
+
+config TARGET_OCTEONTX_81XX
+ bool "Marvell OcteonTX CN81XX"
+
+config TARGET_OCTEONTX_83XX
+ bool "Marvell OcteonTX CN83XX"
+
+endchoice
+
+config SYS_SOC
+ string
+ default "octeontx"
+
+config SYS_PCI_64BIT
+ bool
+ default y
+
+endif
diff --git a/roms/u-boot/arch/arm/mach-octeontx/Makefile b/roms/u-boot/arch/arm/mach-octeontx/Makefile
new file mode 100644
index 000000000..20cb48ad9
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-octeontx/Makefile
@@ -0,0 +1,9 @@
+#/* SPDX-License-Identifier: GPL-2.0
+# *
+# * Copyright (C) 2018 Marvell International Ltd.
+# *
+# * https://spdx.org/licenses
+# */
+
+obj-y += lowlevel_init.o clock.o cpu.o
+
diff --git a/roms/u-boot/arch/arm/mach-octeontx/clock.c b/roms/u-boot/arch/arm/mach-octeontx/clock.c
new file mode 100644
index 000000000..9da21077e
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-octeontx/clock.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/board.h>
+#include <asm/arch/clock.h>
+
+/**
+ * Returns the I/O clock speed in Hz
+ */
+u64 octeontx_get_io_clock(void)
+{
+ union rst_boot rst_boot;
+
+ rst_boot.u = readq(RST_BOOT);
+
+ return rst_boot.s.pnr_mul * PLL_REF_CLK;
+}
+
+/**
+ * Returns the core clock speed in Hz
+ */
+u64 octeontx_get_core_clock(void)
+{
+ union rst_boot rst_boot;
+
+ rst_boot.u = readq(RST_BOOT);
+
+ return rst_boot.s.c_mul * PLL_REF_CLK;
+}
diff --git a/roms/u-boot/arch/arm/mach-octeontx/cpu.c b/roms/u-boot/arch/arm/mach-octeontx/cpu.c
new file mode 100644
index 000000000..7bd74fe4f
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-octeontx/cpu.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/board.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define OTX_MEM_MAP_USED 3
+
+/* 1 for 83xx, +1 is end of list which needs to be empty */
+#define OTX_MEM_MAP_MAX (OTX_MEM_MAP_USED + 1 + CONFIG_NR_DRAM_BANKS + 1)
+
+static struct mm_region otx_mem_map[OTX_MEM_MAP_MAX] = {
+ {
+ .virt = 0x800000000000UL,
+ .phys = 0x800000000000UL,
+ .size = 0x40000000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE
+ }, {
+ .virt = 0x840000000000UL,
+ .phys = 0x840000000000UL,
+ .size = 0x40000000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE
+ }, {
+ .virt = 0x880000000000UL,
+ .phys = 0x880000000000UL,
+ .size = 0x40000000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE
+ }
+
+};
+
+struct mm_region *mem_map = otx_mem_map;
+
+void mem_map_fill(void)
+{
+ int banks = OTX_MEM_MAP_USED;
+ u32 dram_start = CONFIG_SYS_TEXT_BASE;
+
+ if (otx_is_soc(CN83XX)) {
+ otx_mem_map[banks].virt = 0x8c0000000000UL;
+ otx_mem_map[banks].phys = 0x8c0000000000UL;
+ otx_mem_map[banks].size = 0x40000000000UL;
+ otx_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE;
+ banks = banks + 1;
+ }
+
+ for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ otx_mem_map[banks].virt = dram_start;
+ otx_mem_map[banks].phys = dram_start;
+ otx_mem_map[banks].size = gd->ram_size;
+ otx_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_NON_SHARE;
+ banks = banks + 1;
+ }
+}
+
+u64 get_page_table_size(void)
+{
+ return 0x80000;
+}
+
+void reset_cpu(void)
+{
+}
diff --git a/roms/u-boot/arch/arm/mach-octeontx/lowlevel_init.S b/roms/u-boot/arch/arm/mach-octeontx/lowlevel_init.S
new file mode 100644
index 000000000..41a9f08ae
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-octeontx/lowlevel_init.S
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+.align 8
+.global fdt_base_addr
+fdt_base_addr:
+ .dword 0x0
+
+.global save_boot_params
+save_boot_params:
+ /* Read FDT base from x1 register passed by ATF */
+ adr x21, fdt_base_addr
+ str x1, [x21]
+
+ /* Returns */
+ b save_boot_params_ret
+
+ENTRY(lowlevel_init)
+ mov x29, lr /* Save LR */
+
+ /* any lowlevel init should go here */
+
+ mov lr, x29 /* Restore LR */
+ ret
+ENDPROC(lowlevel_init)