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authorAngelos Mouzakitis <a.mouzakitis@virtualopensystems.com>2023-10-10 14:33:42 +0000
committerAngelos Mouzakitis <a.mouzakitis@virtualopensystems.com>2023-10-10 14:33:42 +0000
commitaf1a266670d040d2f4083ff309d732d648afba2a (patch)
tree2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/arch/arm/mach-sunxi/pinmux.c
parente02cda008591317b1625707ff8e115a4841aa889 (diff)
Add submodule dependency filesHEADmaster
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/u-boot/arch/arm/mach-sunxi/pinmux.c')
-rw-r--r--roms/u-boot/arch/arm/mach-sunxi/pinmux.c70
1 files changed, 70 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arm/mach-sunxi/pinmux.c b/roms/u-boot/arch/arm/mach-sunxi/pinmux.c
new file mode 100644
index 000000000..642483f06
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-sunxi/pinmux.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+
+void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
+{
+ u32 index = GPIO_CFG_INDEX(bank_offset);
+ u32 offset = GPIO_CFG_OFFSET(bank_offset);
+
+ clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset);
+}
+
+void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
+{
+ u32 bank = GPIO_BANK(pin);
+ struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+ sunxi_gpio_set_cfgbank(pio, pin, val);
+}
+
+int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
+{
+ u32 index = GPIO_CFG_INDEX(bank_offset);
+ u32 offset = GPIO_CFG_OFFSET(bank_offset);
+ u32 cfg;
+
+ cfg = readl(&pio->cfg[0] + index);
+ cfg >>= offset;
+
+ return cfg & 0xf;
+}
+
+int sunxi_gpio_get_cfgpin(u32 pin)
+{
+ u32 bank = GPIO_BANK(pin);
+ struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+ return sunxi_gpio_get_cfgbank(pio, pin);
+}
+
+int sunxi_gpio_set_drv(u32 pin, u32 val)
+{
+ u32 bank = GPIO_BANK(pin);
+ u32 index = GPIO_DRV_INDEX(pin);
+ u32 offset = GPIO_DRV_OFFSET(pin);
+ struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+ clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val << offset);
+
+ return 0;
+}
+
+int sunxi_gpio_set_pull(u32 pin, u32 val)
+{
+ u32 bank = GPIO_BANK(pin);
+ u32 index = GPIO_PULL_INDEX(pin);
+ u32 offset = GPIO_PULL_OFFSET(pin);
+ struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+ clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset);
+
+ return 0;
+}