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| author |   Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
|---|---|---|
| committer | Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
| commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
| tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/arch/microblaze/include/asm/cache.h | |
| parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) | |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/u-boot/arch/microblaze/include/asm/cache.h')
| -rw-r--r-- | roms/u-boot/arch/microblaze/include/asm/cache.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/roms/u-boot/arch/microblaze/include/asm/cache.h b/roms/u-boot/arch/microblaze/include/asm/cache.h new file mode 100644 index 000000000..baee01a0e --- /dev/null +++ b/roms/u-boot/arch/microblaze/include/asm/cache.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011 The Chromium OS Authors. + */ + +#ifndef __MICROBLAZE_CACHE_H__ +#define __MICROBLAZE_CACHE_H__ + +/* + * The microblaze can have either a 4 or 16 byte cacheline depending on whether + * you are using OPB(4) or CacheLink(16). If the board config has not specified + * a cacheline size we assume the larger value of 16 bytes for DMA buffer + * alignment. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 16 +#endif + +#endif /* __MICROBLAZE_CACHE_H__ */ |