Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

8 files changed, 680 insertions, 0 deletions

diff --git a/roms/u-boot/arch/mips/cpu/Makefile b/roms/u-boot/arch/mips/cpu/Makefile
new file mode 100644
index 000000000..6df7bb4e4
--- /dev/null
+++ b/roms/u-boot/arch/mips/cpu/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+extra-y	= start.o
+
+obj-y += time.o
+obj-y += interrupts.o
+obj-y += cpu.o
+
+obj-$(CONFIG_MIPS_CM)	+= cm_init.o
diff --git a/roms/u-boot/arch/mips/cpu/cm_init.S b/roms/u-boot/arch/mips/cpu/cm_init.S
new file mode 100644
index 000000000..e0d76ce79
--- /dev/null
+++ b/roms/u-boot/arch/mips/cpu/cm_init.S
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MIPS Coherence Manager (CM) Initialisation
+ *
+ * Copyright (c) 2016 Imagination Technologies Ltd.
+ */
+
+#include <asm/addrspace.h>
+#include <asm/asm.h>
+#include <asm/cm.h>
+#include <asm/mipsregs.h>
+#include <asm/regdef.h>
+
+LEAF(mips_cm_map)
+	/* Config3 must exist for a CM to be present */
+	mfc0		t0, CP0_CONFIG, 1
+	bgez		t0, 2f
+	mfc0		t0, CP0_CONFIG, 2
+	bgez		t0, 2f
+
+	/* Check Config3.CMGCR to determine CM presence */
+	mfc0		t0, CP0_CONFIG, 3
+	and		t0, t0, MIPS_CONF3_CMGCR
+	beqz		t0, 2f
+
+	/* Find the current physical GCR base address */
+1:	MFC0		t0, CP0_CMGCRBASE
+	PTR_SLL		t0, t0, 4
+
+	/* If the GCRs are where we want, we're done */
+	PTR_LI		t1, CONFIG_MIPS_CM_BASE
+	beq		t0, t1, 2f
+
+	/* Move the GCRs to our configured base address */
+	PTR_LI		t2, CKSEG1
+	PTR_ADDU	t0, t0, t2
+	sw		zero, GCR_BASE_UPPER(t0)
+	sw		t1, GCR_BASE(t0)
+
+	/* Re-check the GCR base */
+	b		1b
+
+2:	jr		ra
+	END(mips_cm_map)
diff --git a/roms/u-boot/arch/mips/cpu/cpu.c b/roms/u-boot/arch/mips/cpu/cpu.c
new file mode 100644
index 000000000..b304026a6
--- /dev/null
+++ b/roms/u-boot/arch/mips/cpu/cpu.c
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <init.h>
+#include <linux/compiler.h>
+#include <asm/cache.h>
+#include <asm/mipsregs.h>
+#include <asm/reboot.h>
+
+#if !CONFIG_IS_ENABLED(SYSRESET)
+void __weak _machine_restart(void)
+{
+	fprintf(stderr, "*** reset failed ***\n");
+
+	while (1)
+		/* NOP */;
+}
+
+int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	_machine_restart();
+
+	return 0;
+}
+#endif
+
+int arch_cpu_init(void)
+{
+	mips_cache_probe();
+	return 0;
+}
diff --git a/roms/u-boot/arch/mips/cpu/interrupts.c b/roms/u-boot/arch/mips/cpu/interrupts.c
new file mode 100644
index 000000000..b3ba9aaea
--- /dev/null
+++ b/roms/u-boot/arch/mips/cpu/interrupts.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ */
+
+#include <common.h>
+#include <irq_func.h>
+
+int interrupt_init(void)
+{
+	return 0;
+}
+
+void enable_interrupts(void)
+{
+}
+
+int disable_interrupts(void)
+{
+	return 0;
+}
diff --git a/roms/u-boot/arch/mips/cpu/start.S b/roms/u-boot/arch/mips/cpu/start.S
new file mode 100644
index 000000000..335aafa6a
--- /dev/null
+++ b/roms/u-boot/arch/mips/cpu/start.S
@@ -0,0 +1,284 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Startup Code for MIPS32 CPU-core
+ *
+ *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+
+#ifndef CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + \
+				CONFIG_SYS_INIT_SP_OFFSET)
+#endif
+
+#ifdef CONFIG_32BIT
+# define STATUS_SET	0
+#endif
+
+#ifdef CONFIG_64BIT
+# define STATUS_SET	ST0_KX
+#endif
+
+	.set noreorder
+
+	.macro init_wr sel
+	MTC0	zero, CP0_WATCHLO,\sel
+	mtc0	t1, CP0_WATCHHI,\sel
+	mfc0	t0, CP0_WATCHHI,\sel
+	bgez	t0, wr_done
+	 nop
+	.endm
+
+	.macro uhi_mips_exception
+	move	k0, t9		# preserve t9 in k0
+	move	k1, a0		# preserve a0 in k1
+	li	t9, 15		# UHI exception operation
+	li	a0, 0		# Use hard register context
+	sdbbp	1		# Invoke UHI operation
+	.endm
+
+	.macro setup_stack_gd
+	li	t0, -16
+	PTR_LI	t1, CONFIG_SYS_INIT_SP_ADDR
+	and	sp, t1, t0		# force 16 byte alignment
+	PTR_SUBU \
+		sp, sp, GD_SIZE		# reserve space for gd
+	and	sp, sp, t0		# force 16 byte alignment
+	move	k0, sp			# save gd pointer
+#if CONFIG_VAL(SYS_MALLOC_F_LEN) && \
+    !CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F)
+	li	t2, CONFIG_VAL(SYS_MALLOC_F_LEN)
+	PTR_SUBU \
+		sp, sp, t2		# reserve space for early malloc
+	and	sp, sp, t0		# force 16 byte alignment
+#endif
+	move	fp, sp
+
+	/* Clear gd */
+	move	t0, k0
+1:
+	PTR_S	zero, 0(t0)
+	PTR_ADDIU t0, PTRSIZE
+	blt	t0, t1, 1b
+	 nop
+
+#if CONFIG_VAL(SYS_MALLOC_F_LEN) && \
+    !CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F)
+	PTR_S	sp, GD_MALLOC_BASE(k0)	# gd->malloc_base offset
+#endif
+	.endm
+
+ENTRY(_start)
+	/*
+	 * U-Boot entry point.
+	 * Do not add instructions to the branch delay slot! Some SoC's
+	 * like Octeon might patch the final U-Boot binary at this location
+	 * with additional boot headers.
+	 */
+	b	reset
+	 nop
+
+#if defined(CONFIG_MIPS_INSERT_BOOT_CONFIG)
+	/*
+	 * Store some board-specific boot configuration. This is used by some
+	 * MIPS systems like Malta.
+	 */
+	.org 0x10
+	.word CONFIG_MIPS_BOOT_CONFIG_WORD0
+	.word CONFIG_MIPS_BOOT_CONFIG_WORD1
+#endif
+
+#if defined(CONFIG_ROM_EXCEPTION_VECTORS)
+	/*
+	 * Exception vector entry points. When running from ROM, an exception
+	 * cannot be handled. Halt execution and transfer control to debugger,
+	 * if one is attached.
+	 */
+	.org 0x200
+	/* TLB refill, 32 bit task */
+	uhi_mips_exception
+
+	.org 0x280
+	/* XTLB refill, 64 bit task */
+	uhi_mips_exception
+
+	.org 0x300
+	/* Cache error exception */
+	uhi_mips_exception
+
+	.org 0x380
+	/* General exception */
+	uhi_mips_exception
+
+	.org 0x400
+	/* Catch interrupt exceptions */
+	uhi_mips_exception
+
+	.org 0x480
+	/* EJTAG debug exception */
+1:	b	1b
+	 nop
+
+	.org 0x500
+#endif
+
+reset:
+	mtc0	zero, CP0_COUNT	# clear cp0 count for most accurate boot timing
+#if __mips_isa_rev >= 6
+	mfc0	t0, CP0_CONFIG, 5
+	and	t0, t0, MIPS_CONF5_VP
+	beqz	t0, 1f
+	 nop
+
+	b	2f
+	 mfc0	t0, CP0_GLOBALNUMBER
+#endif
+
+#ifdef CONFIG_ARCH_BMIPS
+1:	mfc0	t0, CP0_DIAGNOSTIC, 3
+	and	t0, t0, (1 << 31)
+#else
+1:	mfc0	t0, CP0_EBASE
+	and	t0, t0, MIPS_EBASE_CPUNUM
+#endif
+
+	/* Hang if this isn't the first CPU in the system */
+2:	beqz	t0, 4f
+	 nop
+3:	wait
+	b	3b
+	 nop
+
+	/* Init CP0 Status */
+4:	mfc0	t0, CP0_STATUS
+	and	t0, ST0_IMPL
+	or	t0, ST0_BEV | ST0_ERL | STATUS_SET
+	mtc0	t0, CP0_STATUS
+
+	/*
+	 * Check whether CP0 Config1 is implemented. If not continue
+	 * with legacy Watch register initialization.
+	 */
+	mfc0	t0, CP0_CONFIG
+	bgez	t0, wr_legacy
+	 nop
+
+	/*
+	 * Check WR bit in CP0 Config1 to determine if Watch registers
+	 * are implemented.
+	 */
+	mfc0	t0, CP0_CONFIG, 1
+	andi	t0, (1 << 3)
+	beqz	t0, wr_done
+	 nop
+
+	/* Clear Watch Status bits and disable watch exceptions */
+	li	t1, 0x7		# Clear I, R and W conditions
+	init_wr	0
+	init_wr	1
+	init_wr	2
+	init_wr	3
+	init_wr	4
+	init_wr	5
+	init_wr	6
+	init_wr	7
+	b	wr_done
+	 nop
+
+wr_legacy:
+	MTC0	zero, CP0_WATCHLO
+	mtc0	zero, CP0_WATCHHI
+
+wr_done:
+	/* Clear WP, IV and SW interrupts */
+	mtc0	zero, CP0_CAUSE
+
+	/* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */
+	mtc0	zero, CP0_COMPARE
+
+#ifdef CONFIG_MIPS_CACHE_DISABLE
+	/* Disable caches */
+	PTR_LA	t9, mips_cache_disable
+	jalr	t9
+	 nop
+#endif
+
+#ifdef CONFIG_MIPS_CM
+	PTR_LA	t9, mips_cm_map
+	jalr	t9
+	 nop
+#endif
+
+#ifdef CONFIG_MIPS_INIT_STACK_IN_SRAM
+#ifdef CONFIG_MIPS_SRAM_INIT
+	/* Initialize the SRAM first */
+	PTR_LA	t9, mips_sram_init
+	jalr	t9
+	 nop
+#endif
+
+	/* Set up initial stack and global data */
+	setup_stack_gd
+
+# ifdef CONFIG_DEBUG_UART
+	/* Earliest point to set up debug uart */
+	PTR_LA	t9, debug_uart_init
+	jalr	t9
+	 nop
+# endif
+#endif
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+# ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
+	/* Initialize any external memory */
+	PTR_LA	t9, lowlevel_init
+	jalr	t9
+	 nop
+# endif
+#endif
+
+#ifdef CONFIG_MIPS_MACH_EARLY_INIT
+	bal	mips_mach_early_init
+	 nop
+#endif
+
+#ifdef CONFIG_MIPS_CACHE_SETUP
+	/* Initialize caches... */
+	PTR_LA	t9, mips_cache_reset
+	jalr	t9
+	 nop
+#endif
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
+	/* Initialize any external memory */
+	PTR_LA	t9, lowlevel_init
+	jalr	t9
+	 nop
+# endif
+#endif
+
+#ifndef CONFIG_MIPS_INIT_STACK_IN_SRAM
+	/* Set up initial stack and global data */
+	setup_stack_gd
+
+# ifdef CONFIG_DEBUG_UART
+	/* Earliest point to set up debug uart */
+	PTR_LA	t9, debug_uart_init
+	jalr	t9
+	 nop
+# endif
+#endif
+
+	move	a0, zero		# a0 <-- boot_flags = 0
+	PTR_LA	t9, board_init_f
+
+	jr	t9
+	 move	ra, zero
+
+	END(_start)
diff --git a/roms/u-boot/arch/mips/cpu/time.c b/roms/u-boot/arch/mips/cpu/time.c
new file mode 100644
index 000000000..5e7a7144d
--- /dev/null
+++ b/roms/u-boot/arch/mips/cpu/time.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <time.h>
+#include <asm/mipsregs.h>
+
+unsigned long notrace timer_read_counter(void)
+{
+	return read_c0_count();
+}
+
+#if defined(CONFIG_SYS_MIPS_TIMER_FREQ)
+ulong notrace __weak get_tbclk(void)
+{
+	return CONFIG_SYS_MIPS_TIMER_FREQ;
+}
+#endif
diff --git a/roms/u-boot/arch/mips/cpu/u-boot-spl.lds b/roms/u-boot/arch/mips/cpu/u-boot-spl.lds
new file mode 100644
index 000000000..28ea4f2a4
--- /dev/null
+++ b/roms/u-boot/arch/mips/cpu/u-boot-spl.lds
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+MEMORY { .spl_mem : ORIGIN = IMAGE_TEXT_BASE, \
+		LENGTH = IMAGE_MAX_SIZE }
+MEMORY { .bss_mem : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text : {
+		*(.text*)
+	} > .spl_mem
+
+	. = ALIGN(4);
+	.rodata : {
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	} > .spl_mem
+
+	. = ALIGN(4);
+	.data : {
+		*(SORT_BY_ALIGNMENT(.data*))
+		*(SORT_BY_ALIGNMENT(.sdata*))
+	} > .spl_mem
+
+#if defined(CONFIG_SPL_DM) || defined(CONFIG_SPL_LOADER_SUPPORT)
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	} > .spl_mem
+#endif
+
+	. = ALIGN(4);
+	__image_copy_end = .;
+
+	_image_binary_end = .;
+
+	.bss (NOLOAD) : {
+		__bss_start = .;
+		*(.bss*)
+		*(.sbss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end = .;
+	} > .bss_mem
+
+	/* These mark the ABI of U-Boot for debuggers. */
+	.mdebug.abi32 : {
+		KEEP(*(.mdebug.abi32))
+	}
+	.mdebug.abi64 : {
+		KEEP(*(.mdebug.abi64))
+	}
+
+	/* This is the MIPS specific mdebug section. */
+	.mdebug : { *(.mdebug) }
+
+	/* Stabs debugging sections.  */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+
+	/*
+	 * DWARF debug sections.
+	 * Symbols in the DWARF debugging sections are relative to
+	 * the beginning of the section so we begin them at 0.
+	 */
+	/* DWARF 1 */
+	.debug 0 : { *(.debug) }
+	.line 0 : { *(.line) }
+	/* GNU DWARF 1 extensions */
+	.debug_srcinfo 0 : { *(.debug_srcinfo) }
+	.debug_sfnames 0 : { *(.debug_sfnames) }
+	/* DWARF 1.1 and DWARF 2 */
+	.debug_aranges 0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	/* DWARF 2 */
+	.debug_info 0 : {
+		*(.debug_info
+		.gnu.linkonce.wi.*)
+	}
+	.debug_abbrev 0 : { *(.debug_abbrev) }
+	.debug_line 0 : { *(.debug_line) }
+	.debug_frame 0 : { *(.debug_frame) }
+	.debug_str 0 : { *(.debug_str) }
+	.debug_loc 0 : { *(.debug_loc) }
+	.debug_macinfo 0 : { *(.debug_macinfo) }
+	.debug_pubtypes 0 : { *(.debug_pubtypes) }
+	/* DWARF 3 */
+	.debug_ranges 0 : { *(.debug_ranges) }
+	/* SGI/MIPS DWARF 2 extensions */
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames 0 : { *(.debug_varnames) }
+	/* GNU DWARF 2 extensions */
+	.debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) }
+	.debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) }
+	/* DWARF 4 */
+	.debug_types 0 : { *(.debug_types) }
+	/* DWARF 5 */
+	.debug_macro 0 : { *(.debug_macro) }
+	.debug_addr 0 : { *(.debug_addr) }
+
+	/DISCARD/ : {
+		/* ABI crap starts here */
+		*(.MIPS.abiflags)
+		*(.MIPS.options)
+		*(.options)
+		*(.pdr)
+		*(.reginfo)
+		*(.eh_frame)
+	}
+}
diff --git a/roms/u-boot/arch/mips/cpu/u-boot.lds b/roms/u-boot/arch/mips/cpu/u-boot.lds
new file mode 100644
index 000000000..86496737d
--- /dev/null
+++ b/roms/u-boot/arch/mips/cpu/u-boot.lds
@@ -0,0 +1,142 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ */
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text : {
+		__text_start = .;
+		*(.text*)
+		__text_end = .;
+	}
+
+	. = ALIGN(4);
+	.rodata : {
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+	.sdata : {
+		*(.sdata*)
+	}
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+	__image_copy_end = .;
+	__init_end = .;
+
+	.data.reloc : {
+		__rel_start = .;
+		/*
+		 * Space for relocation table
+		 * This needs to be filled so that the
+		 * mips-reloc tool can overwrite the content.
+		 * An invalid value is left at the start of the
+		 * section to abort relocation if the table
+		 * has not been filled in.
+		 */
+		LONG(0xFFFFFFFF);
+		FILL(0);
+		. += CONFIG_MIPS_RELOCATION_TABLE_SIZE - 4;
+	}
+
+	. = ALIGN(4);
+	_end = .;
+
+	.bss __rel_start (OVERLAY) : {
+		__bss_start = .;
+		*(.sbss.*)
+		*(.bss.*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end = .;
+	}
+
+	/* These mark the ABI of U-Boot for debuggers. */
+	.mdebug.abi32 : {
+		KEEP(*(.mdebug.abi32))
+	}
+	.mdebug.abi64 : {
+		KEEP(*(.mdebug.abi64))
+	}
+
+	/* This is the MIPS specific mdebug section. */
+	.mdebug : { *(.mdebug) }
+
+	/* Stabs debugging sections.  */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+
+	/*
+	 * DWARF debug sections.
+	 * Symbols in the DWARF debugging sections are relative to
+	 * the beginning of the section so we begin them at 0.
+	 */
+	/* DWARF 1 */
+	.debug 0 : { *(.debug) }
+	.line 0 : { *(.line) }
+	/* GNU DWARF 1 extensions */
+	.debug_srcinfo 0 : { *(.debug_srcinfo) }
+	.debug_sfnames 0 : { *(.debug_sfnames) }
+	/* DWARF 1.1 and DWARF 2 */
+	.debug_aranges 0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	/* DWARF 2 */
+	.debug_info 0 : {
+		*(.debug_info
+		.gnu.linkonce.wi.*)
+	}
+	.debug_abbrev 0 : { *(.debug_abbrev) }
+	.debug_line 0 : { *(.debug_line) }
+	.debug_frame 0 : { *(.debug_frame) }
+	.debug_str 0 : { *(.debug_str) }
+	.debug_loc 0 : { *(.debug_loc) }
+	.debug_macinfo 0 : { *(.debug_macinfo) }
+	.debug_pubtypes 0 : { *(.debug_pubtypes) }
+	/* DWARF 3 */
+	.debug_ranges 0 : { *(.debug_ranges) }
+	/* SGI/MIPS DWARF 2 extensions */
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames 0 : { *(.debug_varnames) }
+	/* GNU DWARF 2 extensions */
+	.debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) }
+	.debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) }
+	/* DWARF 4 */
+	.debug_types 0 : { *(.debug_types) }
+	/* DWARF 5 */
+	.debug_macro 0 : { *(.debug_macro) }
+	.debug_addr 0 : { *(.debug_addr) }
+
+	/DISCARD/ : {
+		/* ABI crap starts here */
+		*(.MIPS.abiflags)
+		*(.MIPS.options)
+		*(.options)
+		*(.pdr)
+		*(.reginfo)
+		*(.eh_frame)
+	}
+}