Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

44 files changed, 14110 insertions, 0 deletions

diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/Kconfig b/roms/u-boot/arch/powerpc/cpu/mpc83xx/Kconfig
new file mode 100644
index 000000000..ff85834c4
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -0,0 +1,320 @@
+menu "mpc83xx CPU"
+	depends on MPC83xx
+
+config SYS_CPU
+	default "mpc83xx"
+
+choice
+	prompt "Target select"
+	optional
+
+config TARGET_MPC8308_P1M
+	bool "Support mpc8308_p1m"
+	select ARCH_MPC8308
+
+config TARGET_SBC8349
+	bool "Support sbc8349"
+	select ARCH_MPC8349
+
+config TARGET_VE8313
+	bool "Support ve8313"
+	select ARCH_MPC8313
+
+config TARGET_VME8349
+	bool "Support vme8349"
+	select ARCH_MPC8349
+
+config TARGET_CADDY2
+	bool "Support caddy2"
+	select ARCH_MPC8349
+
+config TARGET_MPC8313ERDB_NOR
+	bool "Support MPC8313ERDB_NOR"
+	select ARCH_MPC8313
+	select BOARD_EARLY_INIT_F
+	select SUPPORT_SPL
+
+config TARGET_MPC8313ERDB_NAND
+	bool "Support MPC8313ERDB_NAND"
+	select ARCH_MPC8313
+	select BOARD_EARLY_INIT_F
+	select SUPPORT_SPL
+
+config TARGET_MPC8315ERDB
+	bool "Support MPC8315ERDB"
+	select ARCH_MPC8315
+	select BOARD_EARLY_INIT_F
+
+config TARGET_MPC8323ERDB
+	bool "Support MPC8323ERDB"
+	select ARCH_MPC832X
+
+config TARGET_MPC832XEMDS
+	bool "Support MPC832XEMDS"
+	select ARCH_MPC832X
+	select BOARD_EARLY_INIT_F
+
+config TARGET_MPC8349EMDS
+	bool "Support MPC8349EMDS"
+	select ARCH_MPC8349
+	select BOARD_EARLY_INIT_F
+	select SYS_FSL_DDR
+	select SYS_FSL_DDR_BE
+	select SYS_FSL_HAS_DDR2
+
+config TARGET_MPC8349EMDS_SDRAM
+	bool "Support MPC8349EMDS_SDRAM"
+	select ARCH_MPC8349
+	select BOARD_EARLY_INIT_F
+	select SYS_FSL_DDR
+	select SYS_FSL_DDR_BE
+	select SYS_FSL_HAS_DDR2
+
+config TARGET_MPC837XERDB
+	bool "Support MPC837XERDB"
+	select ARCH_MPC837X
+	select BOARD_EARLY_INIT_F
+
+config TARGET_IDS8313
+	bool "Support ids8313"
+	select ARCH_MPC8313
+	select DM
+	imply CMD_DM
+
+config TARGET_KMETER1
+	bool "Support kmeter1"
+	select VENDOR_KM
+	select KM_ENABLE_FULL_DM_DTS_SUPPORT
+
+config TARGET_KMCOGE5NE
+	bool "Support kmcoge5ne"
+	select VENDOR_KM
+	select KM_ENABLE_FULL_DM_DTS_SUPPORT
+
+config TARGET_KMTEGR1
+	bool "Support kmtegr1"
+	select VENDOR_KM
+	select KM_ENABLE_FULL_DM_DTS_SUPPORT
+
+config TARGET_TUXX1
+	bool "Support tuxx1"
+	select VENDOR_KM
+	select KM_ENABLE_FULL_DM_DTS_SUPPORT
+
+config TARGET_KMSUPX5
+	bool "Support kmsupx5"
+	select VENDOR_KM
+	select KM_ENABLE_FULL_DM_DTS_SUPPORT
+
+config TARGET_TUGE1
+	bool "Support tuge1"
+	select VENDOR_KM
+	select KM_ENABLE_FULL_DM_DTS_SUPPORT
+
+config TARGET_KMOPTI2
+	bool "Support kmopti2"
+	select VENDOR_KM
+	select KM_ENABLE_FULL_DM_DTS_SUPPORT
+
+config TARGET_KMTEPR2
+	bool "Support kmtepr2"
+	select VENDOR_KM
+	select KM_ENABLE_FULL_DM_DTS_SUPPORT
+
+config TARGET_TQM834X
+	bool "Support TQM834x"
+	select ARCH_MPC8349
+
+
+config TARGET_GAZERBEAM
+	bool "Support gazerbeam"
+	select ARCH_MPC8308
+	select SYS_FSL_ERRATUM_ESDHC111
+	imply ENV_IS_IN_FLASH
+	help
+	  The "Gazerbeam" is a modular system by Guntermann & Drunck GmbH
+	  Systementwicklung based on the NXP MPC8308 SoC for usage in KVM
+	  appliances.
+
+	  Features include:
+	  * Two gigabit ethernet ports
+	  * Multiple USB ports (depending on variant)
+	  * Several gigabit ethernet or optical fiber ports (depending on
+	    variant)
+	  * Several display port inputs and outputs, and supporting redrivers
+	    (depending on variant)
+	  * Several FPGAs with custom logic (depending on variant)
+
+endchoice
+
+config MPC83XX_QUICC_ENGINE
+	bool
+
+# TODO: Imply MPC83xx PCI driver
+config MPC83XX_PCI_SUPPORT
+	bool
+
+# TODO: Imply TSEC driver
+config MPC83XX_TSEC1_SUPPORT
+	bool
+
+config MPC83XX_TSEC2_SUPPORT
+	bool
+
+config MPC83XX_PCIE1_SUPPORT
+	bool
+
+config MPC83XX_PCIE2_SUPPORT
+	bool
+
+config MPC83XX_SDHC_SUPPORT
+	bool
+
+config MPC83XX_SATA_SUPPORT
+	bool
+
+config MPC83XX_SECOND_I2C_SUPPORT
+	bool
+
+config MPC83XX_LDP_PIN
+	bool
+
+config ARCH_MPC830X
+	bool
+	select MPC83XX_SDHC_SUPPORT
+
+config ARCH_MPC8308
+	bool
+	select ARCH_MPC830X
+	select MPC83XX_TSEC1_SUPPORT
+	select MPC83XX_TSEC2_SUPPORT
+	select MPC83XX_PCIE1_SUPPORT
+	select MPC83XX_SECOND_I2C_SUPPORT
+
+config ARCH_MPC8309
+	bool
+	select ARCH_MPC830X
+	select MPC83XX_QUICC_ENGINE
+	select MPC83XX_PCI_SUPPORT
+	select MPC83XX_SECOND_I2C_SUPPORT
+	select SYS_FSL_ERRATUM_ESDHC111
+	select FSL_ELBC
+
+config ARCH_MPC831X
+	bool
+	select MPC83XX_PCI_SUPPORT
+	select MPC83XX_TSEC1_SUPPORT
+	select MPC83XX_TSEC2_SUPPORT
+
+config ARCH_MPC8313
+	bool
+	select ARCH_MPC831X
+	select MPC83XX_SECOND_I2C_SUPPORT
+	select FSL_ELBC
+
+config ARCH_MPC8315
+	bool
+	select ARCH_MPC831X
+	select MPC83XX_PCIE1_SUPPORT
+	select MPC83XX_PCIE2_SUPPORT
+	select MPC83XX_SATA_SUPPORT
+	select FSL_ELBC
+
+config ARCH_MPC832X
+	bool
+	select MPC83XX_QUICC_ENGINE
+	select MPC83XX_PCI_SUPPORT
+
+config ARCH_MPC834X
+	bool
+
+config ARCH_MPC8349
+	bool
+	select ARCH_MPC834X
+	select MPC83XX_PCI_SUPPORT
+	select MPC83XX_TSEC1_SUPPORT
+	select MPC83XX_TSEC2_SUPPORT
+	select MPC83XX_LDP_PIN
+	select MPC83XX_SECOND_I2C_SUPPORT
+
+config ARCH_MPC8360
+	bool
+	select MPC83XX_QUICC_ENGINE
+	select MPC83XX_PCI_SUPPORT
+	select MPC83XX_LDP_PIN
+	select MPC83XX_SECOND_I2C_SUPPORT
+
+config ARCH_MPC837X
+	bool
+	select MPC83XX_PCI_SUPPORT
+	select MPC83XX_TSEC1_SUPPORT
+	select MPC83XX_TSEC2_SUPPORT
+	select MPC83XX_PCIE1_SUPPORT
+	select MPC83XX_PCIE2_SUPPORT
+	select MPC83XX_SDHC_SUPPORT
+	select MPC83XX_SATA_SUPPORT
+	select MPC83XX_LDP_PIN
+	select MPC83XX_SECOND_I2C_SUPPORT
+	select FSL_ELBC
+
+config SYS_IMMR
+	hex "Value for IMMR"
+	default 0xE0000000
+	help
+	  Address for the Internal Memory-Mapped Registers (IMMR) window used
+	  to configure the features of the SoC.
+
+source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/bats/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/hid/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/arbiter/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig"
+
+menu "Legacy options"
+
+if ARCH_MPC8349
+
+#TODO(mario.six@gdsys.cc): Remove when mpc83xx PCI has been converted to DM/DT
+choice
+	prompt "PMC slot configuration"
+
+config PCI_ALL_PCI1
+	bool "All PMC slots on PCI1"
+
+config PCI_ONE_PCI1
+	bool "First PMC1 on PCI1"
+
+config PCI_TWO_PCI1
+	bool "First two PMC1 on PCI1"
+
+endchoice
+
+config PCI_64BIT
+	bool "PMC2 is 64bit"
+
+endif
+
+endmenu
+
+config FSL_ELBC
+	bool
+
+source "board/esd/vme8349/Kconfig"
+source "board/freescale/mpc8313erdb/Kconfig"
+source "board/freescale/mpc8315erdb/Kconfig"
+source "board/freescale/mpc8323erdb/Kconfig"
+source "board/freescale/mpc832xemds/Kconfig"
+source "board/freescale/mpc8349emds/Kconfig"
+source "board/freescale/mpc837xerdb/Kconfig"
+source "board/ids/ids8313/Kconfig"
+source "board/keymile/Kconfig"
+source "board/mpc8308_p1m/Kconfig"
+source "board/sbc8349/Kconfig"
+source "board/tqc/tqm834x/Kconfig"
+source "board/ve8313/Kconfig"
+source "board/gdsys/mpc8308/Kconfig"
+
+endmenu
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/Makefile b/roms/u-boot/arch/powerpc/cpu/mpc83xx/Makefile
new file mode 100644
index 000000000..aeb42b109
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/Makefile
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright 2004 Freescale Semiconductor, Inc.
+
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+extra-y	= start.o
+
+ifdef MINIMAL
+
+obj-y	+= spl_minimal.o
+
+else
+
+obj-y += traps.o
+obj-y += cpu.o
+obj-y += cpu_init.o
+obj-y += speed.o
+obj-y += interrupts.o
+obj-y += ecc.o
+ifndef CONFIG_PINCTRL
+obj-$(CONFIG_QE) += qe_io.o
+endif
+obj-$(CONFIG_FSL_SERDES) += serdes.o
+ifndef CONFIG_ARCH_MPC8308
+obj-$(CONFIG_PCI) += pci.o
+endif
+obj-$(CONFIG_PCIE) += pcie.o
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
+
+ifndef CONFIG_SYS_FSL_DDRC_GEN2
+obj-y += spd_sdram.o
+endif
+obj-$(CONFIG_SYS_FSL_DDR2) += law.o
+
+endif # not minimal
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/arbiter/Kconfig b/roms/u-boot/arch/powerpc/cpu/mpc83xx/arbiter/Kconfig
new file mode 100644
index 000000000..f562476da
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/arbiter/Kconfig
@@ -0,0 +1,139 @@
+menu "Arbiter"
+
+choice
+	prompt "Pipeline depth"
+
+config ACR_PIPE_DEP_UNSET
+	bool "Don't set value"
+
+config ACR_PIPE_DEP_1
+	bool "1"
+
+config ACR_PIPE_DEP_2
+	bool "2"
+
+config ACR_PIPE_DEP_3
+	bool "3"
+
+config ACR_PIPE_DEP_4
+	bool "4"
+
+endchoice
+
+choice
+	prompt "Repeat count"
+
+config ACR_RPTCNT_UNSET
+	bool "Don't set value"
+
+config ACR_RPTCNT_1
+	bool "1"
+
+config ACR_RPTCNT_2
+	bool "2"
+
+config ACR_RPTCNT_3
+	bool "3"
+
+config ACR_RPTCNT_4
+	bool "4"
+
+config ACR_RPTCNT_5
+	bool "5"
+
+config ACR_RPTCNT_6
+	bool "6"
+
+config ACR_RPTCNT_7
+	bool "7"
+
+config ACR_RPTCNT_8
+	bool "8"
+
+endchoice
+
+choice
+	prompt "Address parking"
+
+config ACR_APARK_UNSET
+	bool "Don't set value"
+
+config ACR_APARK_MASTER
+	bool "Park to master"
+
+config ACR_APARK_LAST
+	bool "Park to last owner"
+
+config ACR_APARK_DISABLE
+	bool "Disabled"
+
+endchoice
+
+choice
+	prompt "Parking master"
+
+config ACR_PARKM_UNSET
+	bool "Don't set value"
+
+config ACR_PARKM_E300
+	bool "e300 core"
+
+config ACR_PARKM_TSEC_1_2
+	bool "TSEC1, TSEC2"
+
+config ACR_PARKM_USB_I2C1_BOOT
+	bool "USB/I2C1_BOOT"
+
+config ACR_PARKM_DMA_ESDHC_USB
+	bool "DMA, ESDHC, USB"
+
+config ACR_PARKM_PEX
+	bool "PCI Express"
+
+if MPC83XX_QUICC_ENGINE
+
+config ACR_PARKM_ENC_CORE
+	bool "Encryption core"
+
+endif
+
+endchoice
+
+config ACR_PIPE_DEP
+	hex
+	default 0x0 if ACR_PIPE_DEP_UNSET
+	default 0x0 if ACR_PIPE_DEP_1
+	default 0x10000 if ACR_PIPE_DEP_2
+	default 0x20000 if ACR_PIPE_DEP_3
+	default 0x30000 if ACR_PIPE_DEP_4
+
+config ACR_RPTCNT
+	hex
+	default 0x0 if ACR_RPTCNT_UNSET
+	default 0x0 if ACR_RPTCNT_1
+	default 0x100 if ACR_RPTCNT_2
+	default 0x200 if ACR_RPTCNT_3
+	default 0x300 if ACR_RPTCNT_4
+	default 0x400 if ACR_RPTCNT_5
+	default 0x500 if ACR_RPTCNT_6
+	default 0x600 if ACR_RPTCNT_7
+	default 0x700 if ACR_RPTCNT_8
+
+config ACR_APARK
+	hex
+	default 0x0 if ACR_APARK_UNSET
+	default 0x0 if ACR_APARK_MASTER
+	default 0x10 if ACR_APARK_LAST
+	default 0x20 if ACR_APARK_DISABLE
+
+config ACR_PARKM
+	hex
+	default 0x0 if ACR_PARKM_UNSET
+	default 0x0 if ACR_PARKM_E300
+	default 0x2 if ACR_PARKM_TSEC_1_2
+	default 0x3 if ACR_PARKM_USB_I2C1_BOOT
+	default 0x4 if ACR_PARKM_DMA_ESDHC_USB
+	default 0x5 if ACR_PARKM_PEX
+	default 0x5 if ACR_PARKM_ENC_CORE
+
+endmenu
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/arbiter/arbiter.h b/roms/u-boot/arch/powerpc/cpu/mpc83xx/arbiter/arbiter.h
new file mode 100644
index 000000000..10a47e498
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/arbiter/arbiter.h
@@ -0,0 +1,28 @@
+	const __be32 acr_mask =
+#ifndef CONFIG_ACR_PIPE_DEP_UNSET
+		ACR_PIPE_DEP |
+#endif
+#ifndef CONFIG_ACR_RPTCNT_UNSET
+		ACR_RPTCNT |
+#endif
+#ifndef CONFIG_ACR_APARK_UNSET
+		ACR_APARK |
+#endif
+#ifndef CONFIG_ACR_PARKM_UNSET
+		ACR_PARKM |
+#endif
+		0;
+	const __be32 acr_val =
+#ifndef CONFIG_ACR_PIPE_DEP_UNSET
+		CONFIG_ACR_PIPE_DEP |
+#endif
+#ifndef CONFIG_ACR_RPTCNT_UNSET
+		CONFIG_ACR_RPTCNT |
+#endif
+#ifndef CONFIG_ACR_APARK_UNSET
+		CONFIG_ACR_APARK |
+#endif
+#ifndef CONFIG_ACR_PARKM_UNSET
+		CONFIG_ACR_PARKM |
+#endif
+		0;
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/bats/Kconfig b/roms/u-boot/arch/powerpc/cpu/mpc83xx/bats/Kconfig
new file mode 100644
index 000000000..218920cfc
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/bats/Kconfig
@@ -0,0 +1,1311 @@
+menu "BATS setup"
+
+menuconfig BAT0
+	bool "BAT0"
+
+if BAT0
+
+config BAT0_NAME
+	string "Identifier"
+
+config BAT0_BASE
+	hex "Base"
+
+choice
+	prompt "Block length"
+
+config BAT0_LENGTH_128_KBYTES
+	bool "128 kb"
+
+config BAT0_LENGTH_256_KBYTES
+	bool "256 kb"
+
+config BAT0_LENGTH_512_KBYTES
+	bool "512 kb"
+
+config BAT0_LENGTH_1_MBYTES
+	bool "1 mb"
+
+config BAT0_LENGTH_2_MBYTES
+	bool "2 mb"
+
+config BAT0_LENGTH_4_MBYTES
+	bool "4 mb"
+
+config BAT0_LENGTH_8_MBYTES
+	bool "8 mb"
+
+config BAT0_LENGTH_16_MBYTES
+	bool "16 mb"
+
+config BAT0_LENGTH_32_MBYTES
+	bool "32 mb"
+
+config BAT0_LENGTH_64_MBYTES
+	bool "64 mb"
+
+config BAT0_LENGTH_128_MBYTES
+	bool "128 mb"
+
+config BAT0_LENGTH_256_MBYTES
+	bool "256 mb"
+endchoice
+
+choice
+	prompt "Protection mode"
+
+config BAT0_ACCESS_NONE
+	bool "No access"
+
+config BAT0_ACCESS_RO
+	bool "Read-only"
+
+config BAT0_ACCESS_RW
+	bool "Read-write"
+
+endchoice
+
+config BAT0_ICACHE_WRITETHROUGH
+	bool "I-cache Write-through"
+
+config BAT0_ICACHE_INHIBITED
+	bool "I-cache Inhibited"
+
+config BAT0_ICACHE_MEMORYCOHERENCE
+	bool "I-cache Memory coherence"
+
+config BAT0_ICACHE_GUARDED
+	bool "I-cache Guarded"
+
+config BAT0_DCACHE_WRITETHROUGH
+	bool "D-cache Write-through"
+
+config BAT0_DCACHE_INHIBITED
+	bool "D-cache Inhibited"
+
+config BAT0_DCACHE_MEMORYCOHERENCE
+	bool "D-cache Memory coherence"
+
+config BAT0_DCACHE_GUARDED
+	bool "D-cache Guarded"
+
+config BAT0_USER_MODE_VALID
+	bool "User mode valid"
+
+config BAT0_SUPERVISOR_MODE_VALID
+	bool "Supervisor mode valid"
+
+endif
+
+config BAT0_LENGTH
+	hex
+	default 0x00000000 if BAT0_LENGTH_128_KBYTES
+	default 0x00000004 if BAT0_LENGTH_256_KBYTES
+	default 0x0000000c if BAT0_LENGTH_512_KBYTES
+	default 0x0000001c if BAT0_LENGTH_1_MBYTES
+	default 0x0000003c if BAT0_LENGTH_2_MBYTES
+	default 0x0000007c if BAT0_LENGTH_4_MBYTES
+	default 0x000000fc if BAT0_LENGTH_8_MBYTES
+	default 0x000001fc if BAT0_LENGTH_16_MBYTES
+	default 0x000003fc if BAT0_LENGTH_32_MBYTES
+	default 0x000007fc if BAT0_LENGTH_64_MBYTES
+	default 0x00000ffc if BAT0_LENGTH_128_MBYTES
+	default 0x00001ffc if BAT0_LENGTH_256_MBYTES
+
+config BAT0_PAGE_PROTECTION
+	hex
+	default 0x0 if BAT0_ACCESS_NONE
+	default 0x1 if BAT0_ACCESS_RO
+	default 0x2 if BAT0_ACCESS_RW
+
+config BAT0_WIMG_ICACHE
+	hex
+	default 0x0 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
+	default 0x8 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+	default 0x10 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
+	default 0x18 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+	default 0x20 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
+	default 0x28 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+	default 0x30 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
+	default 0x38 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+	default 0x40 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
+	default 0x48 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+	default 0x50 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
+	default 0x58 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+	default 0x60 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
+	default 0x68 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+	default 0x70 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
+	default 0x78 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+
+config BAT0_WIMG_DCACHE
+	hex
+	default 0x0 if !BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED
+	default 0x8 if !BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED
+	default 0x10 if !BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED
+	default 0x18 if !BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED
+	default 0x20 if !BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED
+	default 0x28 if !BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED
+	default 0x30 if !BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED
+	default 0x38 if !BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED
+	default 0x40 if BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED
+	default 0x48 if BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED
+	default 0x50 if BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED
+	default 0x58 if BAT0_DCACHE_WRITETHROUGH && !BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED
+	default 0x60 if BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED
+	default 0x68 if BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && !BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED
+	default 0x70 if BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && !BAT0_DCACHE_GUARDED
+	default 0x78 if BAT0_DCACHE_WRITETHROUGH && BAT0_DCACHE_INHIBITED && BAT0_DCACHE_MEMORYCOHERENCE && BAT0_DCACHE_GUARDED
+
+config BAT0_VALID_BITS
+	hex
+	default 0x0 if !BAT0_SUPERVISOR_MODE_VALID && !BAT0_USER_MODE_VALID
+	default 0x1 if !BAT0_SUPERVISOR_MODE_VALID && BAT0_USER_MODE_VALID
+	default 0x2 if BAT0_SUPERVISOR_MODE_VALID && !BAT0_USER_MODE_VALID
+	default 0x3 if BAT0_SUPERVISOR_MODE_VALID && BAT0_USER_MODE_VALID
+
+menuconfig BAT1
+	bool "BAT1"
+
+if BAT1
+
+config BAT1_NAME
+	string "Identifier"
+
+config BAT1_BASE
+	hex "Base"
+
+choice
+	prompt "Block length"
+
+config BAT1_LENGTH_128_KBYTES
+	bool "128 kb"
+
+config BAT1_LENGTH_256_KBYTES
+	bool "256 kb"
+
+config BAT1_LENGTH_512_KBYTES
+	bool "512 kb"
+
+config BAT1_LENGTH_1_MBYTES
+	bool "1 mb"
+
+config BAT1_LENGTH_2_MBYTES
+	bool "2 mb"
+
+config BAT1_LENGTH_4_MBYTES
+	bool "4 mb"
+
+config BAT1_LENGTH_8_MBYTES
+	bool "8 mb"
+
+config BAT1_LENGTH_16_MBYTES
+	bool "16 mb"
+
+config BAT1_LENGTH_32_MBYTES
+	bool "32 mb"
+
+config BAT1_LENGTH_64_MBYTES
+	bool "64 mb"
+
+config BAT1_LENGTH_128_MBYTES
+	bool "128 mb"
+
+config BAT1_LENGTH_256_MBYTES
+	bool "256 mb"
+endchoice
+
+choice
+	prompt "Protection mode"
+
+config BAT1_ACCESS_NONE
+	bool "No access"
+
+config BAT1_ACCESS_RO
+	bool "Read-only"
+
+config BAT1_ACCESS_RW
+	bool "Read-write"
+
+endchoice
+
+config BAT1_ICACHE_WRITETHROUGH
+	bool "I-cache Write-through"
+
+config BAT1_ICACHE_INHIBITED
+	bool "I-cache Inhibited"
+
+config BAT1_ICACHE_MEMORYCOHERENCE
+	bool "I-cache Memory coherence"
+
+config BAT1_ICACHE_GUARDED
+	bool "I-cache Guarded"
+
+config BAT1_DCACHE_WRITETHROUGH
+	bool "D-cache Write-through"
+
+config BAT1_DCACHE_INHIBITED
+	bool "D-cache Inhibited"
+
+config BAT1_DCACHE_MEMORYCOHERENCE
+	bool "D-cache Memory coherence"
+
+config BAT1_DCACHE_GUARDED
+	bool "D-cache Guarded"
+
+config BAT1_USER_MODE_VALID
+	bool "User mode valid"
+
+config BAT1_SUPERVISOR_MODE_VALID
+	bool "Supervisor mode valid"
+
+endif
+
+config BAT1_LENGTH
+	hex
+	default 0x00000000 if BAT1_LENGTH_128_KBYTES
+	default 0x00000004 if BAT1_LENGTH_256_KBYTES
+	default 0x0000000c if BAT1_LENGTH_512_KBYTES
+	default 0x0000001c if BAT1_LENGTH_1_MBYTES
+	default 0x0000003c if BAT1_LENGTH_2_MBYTES
+	default 0x0000007c if BAT1_LENGTH_4_MBYTES
+	default 0x000000fc if BAT1_LENGTH_8_MBYTES
+	default 0x000001fc if BAT1_LENGTH_16_MBYTES
+	default 0x000003fc if BAT1_LENGTH_32_MBYTES
+	default 0x000007fc if BAT1_LENGTH_64_MBYTES
+	default 0x00000ffc if BAT1_LENGTH_128_MBYTES
+	default 0x00001ffc if BAT1_LENGTH_256_MBYTES
+
+config BAT1_PAGE_PROTECTION
+	hex
+	default 0x0 if BAT1_ACCESS_NONE
+	default 0x1 if BAT1_ACCESS_RO
+	default 0x2 if BAT1_ACCESS_RW
+
+config BAT1_WIMG_ICACHE
+	hex
+	default 0x0 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
+	default 0x8 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+	default 0x10 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
+	default 0x18 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+	default 0x20 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
+	default 0x28 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+	default 0x30 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
+	default 0x38 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+	default 0x40 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
+	default 0x48 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+	default 0x50 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
+	default 0x58 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+	default 0x60 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
+	default 0x68 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+	default 0x70 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
+	default 0x78 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+
+config BAT1_WIMG_DCACHE
+	hex
+	default 0x0 if !BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED
+	default 0x8 if !BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED
+	default 0x10 if !BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED
+	default 0x18 if !BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED
+	default 0x20 if !BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED
+	default 0x28 if !BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED
+	default 0x30 if !BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED
+	default 0x38 if !BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED
+	default 0x40 if BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED
+	default 0x48 if BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED
+	default 0x50 if BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED
+	default 0x58 if BAT1_DCACHE_WRITETHROUGH && !BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED
+	default 0x60 if BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED
+	default 0x68 if BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && !BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED
+	default 0x70 if BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && !BAT1_DCACHE_GUARDED
+	default 0x78 if BAT1_DCACHE_WRITETHROUGH && BAT1_DCACHE_INHIBITED && BAT1_DCACHE_MEMORYCOHERENCE && BAT1_DCACHE_GUARDED
+
+config BAT1_VALID_BITS
+	hex
+	default 0x0 if !BAT1_SUPERVISOR_MODE_VALID && !BAT1_USER_MODE_VALID
+	default 0x1 if !BAT1_SUPERVISOR_MODE_VALID && BAT1_USER_MODE_VALID
+	default 0x2 if BAT1_SUPERVISOR_MODE_VALID && !BAT1_USER_MODE_VALID
+	default 0x3 if BAT1_SUPERVISOR_MODE_VALID && BAT1_USER_MODE_VALID
+
+menuconfig BAT2
+	bool "BAT2"
+
+if BAT2
+
+config BAT2_NAME
+	string "Identifier"
+
+config BAT2_BASE
+	hex "Base"
+
+choice
+	prompt "Block length"
+
+config BAT2_LENGTH_128_KBYTES
+	bool "128 kb"
+
+config BAT2_LENGTH_256_KBYTES
+	bool "256 kb"
+
+config BAT2_LENGTH_512_KBYTES
+	bool "512 kb"
+
+config BAT2_LENGTH_1_MBYTES
+	bool "1 mb"
+
+config BAT2_LENGTH_2_MBYTES
+	bool "2 mb"
+
+config BAT2_LENGTH_4_MBYTES
+	bool "4 mb"
+
+config BAT2_LENGTH_8_MBYTES
+	bool "8 mb"
+
+config BAT2_LENGTH_16_MBYTES
+	bool "16 mb"
+
+config BAT2_LENGTH_32_MBYTES
+	bool "32 mb"
+
+config BAT2_LENGTH_64_MBYTES
+	bool "64 mb"
+
+config BAT2_LENGTH_128_MBYTES
+	bool "128 mb"
+
+config BAT2_LENGTH_256_MBYTES
+	bool "256 mb"
+endchoice
+
+choice
+	prompt "Protection mode"
+
+config BAT2_ACCESS_NONE
+	bool "No access"
+
+config BAT2_ACCESS_RO
+	bool "Read-only"
+
+config BAT2_ACCESS_RW
+	bool "Read-write"
+
+endchoice
+
+config BAT2_ICACHE_WRITETHROUGH
+	bool "I-cache Write-through"
+
+config BAT2_ICACHE_INHIBITED
+	bool "I-cache Inhibited"
+
+config BAT2_ICACHE_MEMORYCOHERENCE
+	bool "I-cache Memory coherence"
+
+config BAT2_ICACHE_GUARDED
+	bool "I-cache Guarded"
+
+config BAT2_DCACHE_WRITETHROUGH
+	bool "D-cache Write-through"
+
+config BAT2_DCACHE_INHIBITED
+	bool "D-cache Inhibited"
+
+config BAT2_DCACHE_MEMORYCOHERENCE
+	bool "D-cache Memory coherence"
+
+config BAT2_DCACHE_GUARDED
+	bool "D-cache Guarded"
+
+config BAT2_USER_MODE_VALID
+	bool "User mode valid"
+
+config BAT2_SUPERVISOR_MODE_VALID
+	bool "Supervisor mode valid"
+
+endif
+
+config BAT2_LENGTH
+	hex
+	default 0x00000000 if BAT2_LENGTH_128_KBYTES
+	default 0x00000004 if BAT2_LENGTH_256_KBYTES
+	default 0x0000000c if BAT2_LENGTH_512_KBYTES
+	default 0x0000001c if BAT2_LENGTH_1_MBYTES
+	default 0x0000003c if BAT2_LENGTH_2_MBYTES
+	default 0x0000007c if BAT2_LENGTH_4_MBYTES
+	default 0x000000fc if BAT2_LENGTH_8_MBYTES
+	default 0x000001fc if BAT2_LENGTH_16_MBYTES
+	default 0x000003fc if BAT2_LENGTH_32_MBYTES
+	default 0x000007fc if BAT2_LENGTH_64_MBYTES
+	default 0x00000ffc if BAT2_LENGTH_128_MBYTES
+	default 0x00001ffc if BAT2_LENGTH_256_MBYTES
+
+config BAT2_PAGE_PROTECTION
+	hex
+	default 0x0 if BAT2_ACCESS_NONE
+	default 0x1 if BAT2_ACCESS_RO
+	default 0x2 if BAT2_ACCESS_RW
+
+config BAT2_WIMG_ICACHE
+	hex
+	default 0x0 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
+	default 0x8 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+	default 0x10 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
+	default 0x18 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+	default 0x20 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
+	default 0x28 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+	default 0x30 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
+	default 0x38 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+	default 0x40 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
+	default 0x48 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+	default 0x50 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
+	default 0x58 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+	default 0x60 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
+	default 0x68 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+	default 0x70 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
+	default 0x78 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+
+config BAT2_WIMG_DCACHE
+	hex
+	default 0x0 if !BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED
+	default 0x8 if !BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED
+	default 0x10 if !BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED
+	default 0x18 if !BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED
+	default 0x20 if !BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED
+	default 0x28 if !BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED
+	default 0x30 if !BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED
+	default 0x38 if !BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED
+	default 0x40 if BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED
+	default 0x48 if BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED
+	default 0x50 if BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED
+	default 0x58 if BAT2_DCACHE_WRITETHROUGH && !BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED
+	default 0x60 if BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED
+	default 0x68 if BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && !BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED
+	default 0x70 if BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && !BAT2_DCACHE_GUARDED
+	default 0x78 if BAT2_DCACHE_WRITETHROUGH && BAT2_DCACHE_INHIBITED && BAT2_DCACHE_MEMORYCOHERENCE && BAT2_DCACHE_GUARDED
+
+config BAT2_VALID_BITS
+	hex
+	default 0x0 if !BAT2_SUPERVISOR_MODE_VALID && !BAT2_USER_MODE_VALID
+	default 0x1 if !BAT2_SUPERVISOR_MODE_VALID && BAT2_USER_MODE_VALID
+	default 0x2 if BAT2_SUPERVISOR_MODE_VALID && !BAT2_USER_MODE_VALID
+	default 0x3 if BAT2_SUPERVISOR_MODE_VALID && BAT2_USER_MODE_VALID
+
+menuconfig BAT3
+	bool "BAT3"
+
+if BAT3
+
+config BAT3_NAME
+	string "Identifier"
+
+config BAT3_BASE
+	hex "Base"
+
+choice
+	prompt "Block length"
+
+config BAT3_LENGTH_128_KBYTES
+	bool "128 kb"
+
+config BAT3_LENGTH_256_KBYTES
+	bool "256 kb"
+
+config BAT3_LENGTH_512_KBYTES
+	bool "512 kb"
+
+config BAT3_LENGTH_1_MBYTES
+	bool "1 mb"
+
+config BAT3_LENGTH_2_MBYTES
+	bool "2 mb"
+
+config BAT3_LENGTH_4_MBYTES
+	bool "4 mb"
+
+config BAT3_LENGTH_8_MBYTES
+	bool "8 mb"
+
+config BAT3_LENGTH_16_MBYTES
+	bool "16 mb"
+
+config BAT3_LENGTH_32_MBYTES
+	bool "32 mb"
+
+config BAT3_LENGTH_64_MBYTES
+	bool "64 mb"
+
+config BAT3_LENGTH_128_MBYTES
+	bool "128 mb"
+
+config BAT3_LENGTH_256_MBYTES
+	bool "256 mb"
+endchoice
+
+choice
+	prompt "Protection mode"
+
+config BAT3_ACCESS_NONE
+	bool "No access"
+
+config BAT3_ACCESS_RO
+	bool "Read-only"
+
+config BAT3_ACCESS_RW
+	bool "Read-write"
+
+endchoice
+
+config BAT3_ICACHE_WRITETHROUGH
+	bool "I-cache Write-through"
+
+config BAT3_ICACHE_INHIBITED
+	bool "I-cache Inhibited"
+
+config BAT3_ICACHE_MEMORYCOHERENCE
+	bool "I-cache Memory coherence"
+
+config BAT3_ICACHE_GUARDED
+	bool "I-cache Guarded"
+
+config BAT3_DCACHE_WRITETHROUGH
+	bool "D-cache Write-through"
+
+config BAT3_DCACHE_INHIBITED
+	bool "D-cache Inhibited"
+
+config BAT3_DCACHE_MEMORYCOHERENCE
+	bool "D-cache Memory coherence"
+
+config BAT3_DCACHE_GUARDED
+	bool "D-cache Guarded"
+
+config BAT3_USER_MODE_VALID
+	bool "User mode valid"
+
+config BAT3_SUPERVISOR_MODE_VALID
+	bool "Supervisor mode valid"
+
+endif
+
+config BAT3_LENGTH
+	hex
+	default 0x00000000 if BAT3_LENGTH_128_KBYTES
+	default 0x00000004 if BAT3_LENGTH_256_KBYTES
+	default 0x0000000c if BAT3_LENGTH_512_KBYTES
+	default 0x0000001c if BAT3_LENGTH_1_MBYTES
+	default 0x0000003c if BAT3_LENGTH_2_MBYTES
+	default 0x0000007c if BAT3_LENGTH_4_MBYTES
+	default 0x000000fc if BAT3_LENGTH_8_MBYTES
+	default 0x000001fc if BAT3_LENGTH_16_MBYTES
+	default 0x000003fc if BAT3_LENGTH_32_MBYTES
+	default 0x000007fc if BAT3_LENGTH_64_MBYTES
+	default 0x00000ffc if BAT3_LENGTH_128_MBYTES
+	default 0x00001ffc if BAT3_LENGTH_256_MBYTES
+
+config BAT3_PAGE_PROTECTION
+	hex
+	default 0x0 if BAT3_ACCESS_NONE
+	default 0x1 if BAT3_ACCESS_RO
+	default 0x2 if BAT3_ACCESS_RW
+
+config BAT3_WIMG_ICACHE
+	hex
+	default 0x0 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
+	default 0x8 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+	default 0x10 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
+	default 0x18 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+	default 0x20 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
+	default 0x28 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+	default 0x30 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
+	default 0x38 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+	default 0x40 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
+	default 0x48 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+	default 0x50 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
+	default 0x58 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+	default 0x60 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
+	default 0x68 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+	default 0x70 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
+	default 0x78 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+
+config BAT3_WIMG_DCACHE
+	hex
+	default 0x0 if !BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED
+	default 0x8 if !BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED
+	default 0x10 if !BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED
+	default 0x18 if !BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED
+	default 0x20 if !BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED
+	default 0x28 if !BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED
+	default 0x30 if !BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED
+	default 0x38 if !BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED
+	default 0x40 if BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED
+	default 0x48 if BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED
+	default 0x50 if BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED
+	default 0x58 if BAT3_DCACHE_WRITETHROUGH && !BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED
+	default 0x60 if BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED
+	default 0x68 if BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && !BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED
+	default 0x70 if BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && !BAT3_DCACHE_GUARDED
+	default 0x78 if BAT3_DCACHE_WRITETHROUGH && BAT3_DCACHE_INHIBITED && BAT3_DCACHE_MEMORYCOHERENCE && BAT3_DCACHE_GUARDED
+
+config BAT3_VALID_BITS
+	hex
+	default 0x0 if !BAT3_SUPERVISOR_MODE_VALID && !BAT3_USER_MODE_VALID
+	default 0x1 if !BAT3_SUPERVISOR_MODE_VALID && BAT3_USER_MODE_VALID
+	default 0x2 if BAT3_SUPERVISOR_MODE_VALID && !BAT3_USER_MODE_VALID
+	default 0x3 if BAT3_SUPERVISOR_MODE_VALID && BAT3_USER_MODE_VALID
+
+if HIGH_BATS
+
+menuconfig BAT4
+	bool "BAT4"
+
+if BAT4
+
+config BAT4_NAME
+	string "Identifier"
+
+config BAT4_BASE
+	hex "Base"
+
+choice
+	prompt "Block length"
+
+config BAT4_LENGTH_128_KBYTES
+	bool "128 kb"
+
+config BAT4_LENGTH_256_KBYTES
+	bool "256 kb"
+
+config BAT4_LENGTH_512_KBYTES
+	bool "512 kb"
+
+config BAT4_LENGTH_1_MBYTES
+	bool "1 mb"
+
+config BAT4_LENGTH_2_MBYTES
+	bool "2 mb"
+
+config BAT4_LENGTH_4_MBYTES
+	bool "4 mb"
+
+config BAT4_LENGTH_8_MBYTES
+	bool "8 mb"
+
+config BAT4_LENGTH_16_MBYTES
+	bool "16 mb"
+
+config BAT4_LENGTH_32_MBYTES
+	bool "32 mb"
+
+config BAT4_LENGTH_64_MBYTES
+	bool "64 mb"
+
+config BAT4_LENGTH_128_MBYTES
+	bool "128 mb"
+
+config BAT4_LENGTH_256_MBYTES
+	bool "256 mb"
+endchoice
+
+choice
+	prompt "Protection mode"
+
+config BAT4_ACCESS_NONE
+	bool "No access"
+
+config BAT4_ACCESS_RO
+	bool "Read-only"
+
+config BAT4_ACCESS_RW
+	bool "Read-write"
+
+endchoice
+
+config BAT4_ICACHE_WRITETHROUGH
+	bool "I-cache Write-through"
+
+config BAT4_ICACHE_INHIBITED
+	bool "I-cache Inhibited"
+
+config BAT4_ICACHE_MEMORYCOHERENCE
+	bool "I-cache Memory coherence"
+
+config BAT4_ICACHE_GUARDED
+	bool "I-cache Guarded"
+
+config BAT4_DCACHE_WRITETHROUGH
+	bool "D-cache Write-through"
+
+config BAT4_DCACHE_INHIBITED
+	bool "D-cache Inhibited"
+
+config BAT4_DCACHE_MEMORYCOHERENCE
+	bool "D-cache Memory coherence"
+
+config BAT4_DCACHE_GUARDED
+	bool "D-cache Guarded"
+
+config BAT4_USER_MODE_VALID
+	bool "User mode valid"
+
+config BAT4_SUPERVISOR_MODE_VALID
+	bool "Supervisor mode valid"
+
+endif
+
+config BAT4_LENGTH
+	hex
+	default 0x00000000 if BAT4_LENGTH_128_KBYTES
+	default 0x00000004 if BAT4_LENGTH_256_KBYTES
+	default 0x0000000c if BAT4_LENGTH_512_KBYTES
+	default 0x0000001c if BAT4_LENGTH_1_MBYTES
+	default 0x0000003c if BAT4_LENGTH_2_MBYTES
+	default 0x0000007c if BAT4_LENGTH_4_MBYTES
+	default 0x000000fc if BAT4_LENGTH_8_MBYTES
+	default 0x000001fc if BAT4_LENGTH_16_MBYTES
+	default 0x000003fc if BAT4_LENGTH_32_MBYTES
+	default 0x000007fc if BAT4_LENGTH_64_MBYTES
+	default 0x00000ffc if BAT4_LENGTH_128_MBYTES
+	default 0x00001ffc if BAT4_LENGTH_256_MBYTES
+
+config BAT4_PAGE_PROTECTION
+	hex
+	default 0x0 if BAT4_ACCESS_NONE
+	default 0x1 if BAT4_ACCESS_RO
+	default 0x2 if BAT4_ACCESS_RW
+
+config BAT4_WIMG_ICACHE
+	hex
+	default 0x0 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
+	default 0x8 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+	default 0x10 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
+	default 0x18 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+	default 0x20 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
+	default 0x28 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+	default 0x30 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
+	default 0x38 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+	default 0x40 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
+	default 0x48 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+	default 0x50 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
+	default 0x58 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+	default 0x60 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
+	default 0x68 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+	default 0x70 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
+	default 0x78 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+
+config BAT4_WIMG_DCACHE
+	hex
+	default 0x0 if !BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED
+	default 0x8 if !BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED
+	default 0x10 if !BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED
+	default 0x18 if !BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED
+	default 0x20 if !BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED
+	default 0x28 if !BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED
+	default 0x30 if !BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED
+	default 0x38 if !BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED
+	default 0x40 if BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED
+	default 0x48 if BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED
+	default 0x50 if BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED
+	default 0x58 if BAT4_DCACHE_WRITETHROUGH && !BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED
+	default 0x60 if BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED
+	default 0x68 if BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && !BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED
+	default 0x70 if BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && !BAT4_DCACHE_GUARDED
+	default 0x78 if BAT4_DCACHE_WRITETHROUGH && BAT4_DCACHE_INHIBITED && BAT4_DCACHE_MEMORYCOHERENCE && BAT4_DCACHE_GUARDED
+
+config BAT4_VALID_BITS
+	hex
+	default 0x0 if !BAT4_SUPERVISOR_MODE_VALID && !BAT4_USER_MODE_VALID
+	default 0x1 if !BAT4_SUPERVISOR_MODE_VALID && BAT4_USER_MODE_VALID
+	default 0x2 if BAT4_SUPERVISOR_MODE_VALID && !BAT4_USER_MODE_VALID
+	default 0x3 if BAT4_SUPERVISOR_MODE_VALID && BAT4_USER_MODE_VALID
+
+menuconfig BAT5
+	bool "BAT5"
+
+if BAT5
+
+config BAT5_NAME
+	string "Identifier"
+
+config BAT5_BASE
+	hex "Base"
+
+choice
+	prompt "Block length"
+
+config BAT5_LENGTH_128_KBYTES
+	bool "128 kb"
+
+config BAT5_LENGTH_256_KBYTES
+	bool "256 kb"
+
+config BAT5_LENGTH_512_KBYTES
+	bool "512 kb"
+
+config BAT5_LENGTH_1_MBYTES
+	bool "1 mb"
+
+config BAT5_LENGTH_2_MBYTES
+	bool "2 mb"
+
+config BAT5_LENGTH_4_MBYTES
+	bool "4 mb"
+
+config BAT5_LENGTH_8_MBYTES
+	bool "8 mb"
+
+config BAT5_LENGTH_16_MBYTES
+	bool "16 mb"
+
+config BAT5_LENGTH_32_MBYTES
+	bool "32 mb"
+
+config BAT5_LENGTH_64_MBYTES
+	bool "64 mb"
+
+config BAT5_LENGTH_128_MBYTES
+	bool "128 mb"
+
+config BAT5_LENGTH_256_MBYTES
+	bool "256 mb"
+endchoice
+
+choice
+	prompt "Protection mode"
+
+config BAT5_ACCESS_NONE
+	bool "No access"
+
+config BAT5_ACCESS_RO
+	bool "Read-only"
+
+config BAT5_ACCESS_RW
+	bool "Read-write"
+
+endchoice
+
+config BAT5_ICACHE_WRITETHROUGH
+	bool "I-cache Write-through"
+
+config BAT5_ICACHE_INHIBITED
+	bool "I-cache Inhibited"
+
+config BAT5_ICACHE_MEMORYCOHERENCE
+	bool "I-cache Memory coherence"
+
+config BAT5_ICACHE_GUARDED
+	bool "I-cache Guarded"
+
+config BAT5_DCACHE_WRITETHROUGH
+	bool "D-cache Write-through"
+
+config BAT5_DCACHE_INHIBITED
+	bool "D-cache Inhibited"
+
+config BAT5_DCACHE_MEMORYCOHERENCE
+	bool "D-cache Memory coherence"
+
+config BAT5_DCACHE_GUARDED
+	bool "D-cache Guarded"
+
+config BAT5_USER_MODE_VALID
+	bool "User mode valid"
+
+config BAT5_SUPERVISOR_MODE_VALID
+	bool "Supervisor mode valid"
+
+endif
+
+config BAT5_LENGTH
+	hex
+	default 0x00000000 if BAT5_LENGTH_128_KBYTES
+	default 0x00000004 if BAT5_LENGTH_256_KBYTES
+	default 0x0000000c if BAT5_LENGTH_512_KBYTES
+	default 0x0000001c if BAT5_LENGTH_1_MBYTES
+	default 0x0000003c if BAT5_LENGTH_2_MBYTES
+	default 0x0000007c if BAT5_LENGTH_4_MBYTES
+	default 0x000000fc if BAT5_LENGTH_8_MBYTES
+	default 0x000001fc if BAT5_LENGTH_16_MBYTES
+	default 0x000003fc if BAT5_LENGTH_32_MBYTES
+	default 0x000007fc if BAT5_LENGTH_64_MBYTES
+	default 0x00000ffc if BAT5_LENGTH_128_MBYTES
+	default 0x00001ffc if BAT5_LENGTH_256_MBYTES
+
+config BAT5_PAGE_PROTECTION
+	hex
+	default 0x0 if BAT5_ACCESS_NONE
+	default 0x1 if BAT5_ACCESS_RO
+	default 0x2 if BAT5_ACCESS_RW
+
+config BAT5_WIMG_ICACHE
+	hex
+	default 0x0 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
+	default 0x8 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+	default 0x10 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
+	default 0x18 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+	default 0x20 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
+	default 0x28 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+	default 0x30 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
+	default 0x38 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+	default 0x40 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
+	default 0x48 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+	default 0x50 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
+	default 0x58 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+	default 0x60 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
+	default 0x68 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+	default 0x70 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
+	default 0x78 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+
+config BAT5_WIMG_DCACHE
+	hex
+	default 0x0 if !BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED
+	default 0x8 if !BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED
+	default 0x10 if !BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED
+	default 0x18 if !BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED
+	default 0x20 if !BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED
+	default 0x28 if !BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED
+	default 0x30 if !BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED
+	default 0x38 if !BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED
+	default 0x40 if BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED
+	default 0x48 if BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED
+	default 0x50 if BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED
+	default 0x58 if BAT5_DCACHE_WRITETHROUGH && !BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED
+	default 0x60 if BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED
+	default 0x68 if BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && !BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED
+	default 0x70 if BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && !BAT5_DCACHE_GUARDED
+	default 0x78 if BAT5_DCACHE_WRITETHROUGH && BAT5_DCACHE_INHIBITED && BAT5_DCACHE_MEMORYCOHERENCE && BAT5_DCACHE_GUARDED
+
+config BAT5_VALID_BITS
+	hex
+	default 0x0 if !BAT5_SUPERVISOR_MODE_VALID && !BAT5_USER_MODE_VALID
+	default 0x1 if !BAT5_SUPERVISOR_MODE_VALID && BAT5_USER_MODE_VALID
+	default 0x2 if BAT5_SUPERVISOR_MODE_VALID && !BAT5_USER_MODE_VALID
+	default 0x3 if BAT5_SUPERVISOR_MODE_VALID && BAT5_USER_MODE_VALID
+
+menuconfig BAT6
+	bool "BAT6"
+
+if BAT6
+
+config BAT6_NAME
+	string "Identifier"
+
+config BAT6_BASE
+	hex "Base"
+
+choice
+	prompt "Block length"
+
+config BAT6_LENGTH_128_KBYTES
+	bool "128 kb"
+
+config BAT6_LENGTH_256_KBYTES
+	bool "256 kb"
+
+config BAT6_LENGTH_512_KBYTES
+	bool "512 kb"
+
+config BAT6_LENGTH_1_MBYTES
+	bool "1 mb"
+
+config BAT6_LENGTH_2_MBYTES
+	bool "2 mb"
+
+config BAT6_LENGTH_4_MBYTES
+	bool "4 mb"
+
+config BAT6_LENGTH_8_MBYTES
+	bool "8 mb"
+
+config BAT6_LENGTH_16_MBYTES
+	bool "16 mb"
+
+config BAT6_LENGTH_32_MBYTES
+	bool "32 mb"
+
+config BAT6_LENGTH_64_MBYTES
+	bool "64 mb"
+
+config BAT6_LENGTH_128_MBYTES
+	bool "128 mb"
+
+config BAT6_LENGTH_256_MBYTES
+	bool "256 mb"
+endchoice
+
+choice
+	prompt "Protection mode"
+
+config BAT6_ACCESS_NONE
+	bool "No access"
+
+config BAT6_ACCESS_RO
+	bool "Read-only"
+
+config BAT6_ACCESS_RW
+	bool "Read-write"
+
+endchoice
+
+config BAT6_ICACHE_WRITETHROUGH
+	bool "I-cache Write-through"
+
+config BAT6_ICACHE_INHIBITED
+	bool "I-cache Inhibited"
+
+config BAT6_ICACHE_MEMORYCOHERENCE
+	bool "I-cache Memory coherence"
+
+config BAT6_ICACHE_GUARDED
+	bool "I-cache Guarded"
+
+config BAT6_DCACHE_WRITETHROUGH
+	bool "D-cache Write-through"
+
+config BAT6_DCACHE_INHIBITED
+	bool "D-cache Inhibited"
+
+config BAT6_DCACHE_MEMORYCOHERENCE
+	bool "D-cache Memory coherence"
+
+config BAT6_DCACHE_GUARDED
+	bool "D-cache Guarded"
+
+config BAT6_USER_MODE_VALID
+	bool "User mode valid"
+
+config BAT6_SUPERVISOR_MODE_VALID
+	bool "Supervisor mode valid"
+
+endif
+
+config BAT6_LENGTH
+	hex
+	default 0x00000000 if BAT6_LENGTH_128_KBYTES
+	default 0x00000004 if BAT6_LENGTH_256_KBYTES
+	default 0x0000000c if BAT6_LENGTH_512_KBYTES
+	default 0x0000001c if BAT6_LENGTH_1_MBYTES
+	default 0x0000003c if BAT6_LENGTH_2_MBYTES
+	default 0x0000007c if BAT6_LENGTH_4_MBYTES
+	default 0x000000fc if BAT6_LENGTH_8_MBYTES
+	default 0x000001fc if BAT6_LENGTH_16_MBYTES
+	default 0x000003fc if BAT6_LENGTH_32_MBYTES
+	default 0x000007fc if BAT6_LENGTH_64_MBYTES
+	default 0x00000ffc if BAT6_LENGTH_128_MBYTES
+	default 0x00001ffc if BAT6_LENGTH_256_MBYTES
+
+config BAT6_PAGE_PROTECTION
+	hex
+	default 0x0 if BAT6_ACCESS_NONE
+	default 0x1 if BAT6_ACCESS_RO
+	default 0x2 if BAT6_ACCESS_RW
+
+config BAT6_WIMG_ICACHE
+	hex
+	default 0x0 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
+	default 0x8 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+	default 0x10 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
+	default 0x18 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+	default 0x20 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
+	default 0x28 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+	default 0x30 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
+	default 0x38 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+	default 0x40 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
+	default 0x48 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+	default 0x50 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
+	default 0x58 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+	default 0x60 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
+	default 0x68 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+	default 0x70 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
+	default 0x78 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+
+config BAT6_WIMG_DCACHE
+	hex
+	default 0x0 if !BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED
+	default 0x8 if !BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED
+	default 0x10 if !BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED
+	default 0x18 if !BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED
+	default 0x20 if !BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED
+	default 0x28 if !BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED
+	default 0x30 if !BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED
+	default 0x38 if !BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED
+	default 0x40 if BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED
+	default 0x48 if BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED
+	default 0x50 if BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED
+	default 0x58 if BAT6_DCACHE_WRITETHROUGH && !BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED
+	default 0x60 if BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED
+	default 0x68 if BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && !BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED
+	default 0x70 if BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && !BAT6_DCACHE_GUARDED
+	default 0x78 if BAT6_DCACHE_WRITETHROUGH && BAT6_DCACHE_INHIBITED && BAT6_DCACHE_MEMORYCOHERENCE && BAT6_DCACHE_GUARDED
+
+config BAT6_VALID_BITS
+	hex
+	default 0x0 if !BAT6_SUPERVISOR_MODE_VALID && !BAT6_USER_MODE_VALID
+	default 0x1 if !BAT6_SUPERVISOR_MODE_VALID && BAT6_USER_MODE_VALID
+	default 0x2 if BAT6_SUPERVISOR_MODE_VALID && !BAT6_USER_MODE_VALID
+	default 0x3 if BAT6_SUPERVISOR_MODE_VALID && BAT6_USER_MODE_VALID
+
+menuconfig BAT7
+	bool "BAT7"
+
+if BAT7
+
+config BAT7_NAME
+	string "Identifier"
+
+config BAT7_BASE
+	hex "Base"
+
+choice
+	prompt "Block length"
+
+config BAT7_LENGTH_128_KBYTES
+	bool "128 kb"
+
+config BAT7_LENGTH_256_KBYTES
+	bool "256 kb"
+
+config BAT7_LENGTH_512_KBYTES
+	bool "512 kb"
+
+config BAT7_LENGTH_1_MBYTES
+	bool "1 mb"
+
+config BAT7_LENGTH_2_MBYTES
+	bool "2 mb"
+
+config BAT7_LENGTH_4_MBYTES
+	bool "4 mb"
+
+config BAT7_LENGTH_8_MBYTES
+	bool "8 mb"
+
+config BAT7_LENGTH_16_MBYTES
+	bool "16 mb"
+
+config BAT7_LENGTH_32_MBYTES
+	bool "32 mb"
+
+config BAT7_LENGTH_64_MBYTES
+	bool "64 mb"
+
+config BAT7_LENGTH_128_MBYTES
+	bool "128 mb"
+
+config BAT7_LENGTH_256_MBYTES
+	bool "256 mb"
+endchoice
+
+choice
+	prompt "Protection mode"
+
+config BAT7_ACCESS_NONE
+	bool "No access"
+
+config BAT7_ACCESS_RO
+	bool "Read-only"
+
+config BAT7_ACCESS_RW
+	bool "Read-write"
+
+endchoice
+
+config BAT7_ICACHE_WRITETHROUGH
+	bool "I-cache Write-through"
+
+config BAT7_ICACHE_INHIBITED
+	bool "I-cache Inhibited"
+
+config BAT7_ICACHE_MEMORYCOHERENCE
+	bool "I-cache Memory coherence"
+
+config BAT7_ICACHE_GUARDED
+	bool "I-cache Guarded"
+
+config BAT7_DCACHE_WRITETHROUGH
+	bool "D-cache Write-through"
+
+config BAT7_DCACHE_INHIBITED
+	bool "D-cache Inhibited"
+
+config BAT7_DCACHE_MEMORYCOHERENCE
+	bool "D-cache Memory coherence"
+
+config BAT7_DCACHE_GUARDED
+	bool "D-cache Guarded"
+
+config BAT7_USER_MODE_VALID
+	bool "User mode valid"
+
+config BAT7_SUPERVISOR_MODE_VALID
+	bool "Supervisor mode valid"
+
+endif
+
+config BAT7_LENGTH
+	hex
+	default 0x00000000 if BAT7_LENGTH_128_KBYTES
+	default 0x00000004 if BAT7_LENGTH_256_KBYTES
+	default 0x0000000c if BAT7_LENGTH_512_KBYTES
+	default 0x0000001c if BAT7_LENGTH_1_MBYTES
+	default 0x0000003c if BAT7_LENGTH_2_MBYTES
+	default 0x0000007c if BAT7_LENGTH_4_MBYTES
+	default 0x000000fc if BAT7_LENGTH_8_MBYTES
+	default 0x000001fc if BAT7_LENGTH_16_MBYTES
+	default 0x000003fc if BAT7_LENGTH_32_MBYTES
+	default 0x000007fc if BAT7_LENGTH_64_MBYTES
+	default 0x00000ffc if BAT7_LENGTH_128_MBYTES
+	default 0x00001ffc if BAT7_LENGTH_256_MBYTES
+
+config BAT7_PAGE_PROTECTION
+	hex
+	default 0x0 if BAT7_ACCESS_NONE
+	default 0x1 if BAT7_ACCESS_RO
+	default 0x2 if BAT7_ACCESS_RW
+
+config BAT7_WIMG_ICACHE
+	hex
+	default 0x0 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
+	default 0x8 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+	default 0x10 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
+	default 0x18 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+	default 0x20 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
+	default 0x28 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+	default 0x30 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
+	default 0x38 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+	default 0x40 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
+	default 0x48 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+	default 0x50 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
+	default 0x58 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+	default 0x60 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
+	default 0x68 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+	default 0x70 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
+	default 0x78 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+
+config BAT7_WIMG_DCACHE
+	hex
+	default 0x0 if !BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED
+	default 0x8 if !BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED
+	default 0x10 if !BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED
+	default 0x18 if !BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED
+	default 0x20 if !BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED
+	default 0x28 if !BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED
+	default 0x30 if !BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED
+	default 0x38 if !BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED
+	default 0x40 if BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED
+	default 0x48 if BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED
+	default 0x50 if BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED
+	default 0x58 if BAT7_DCACHE_WRITETHROUGH && !BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED
+	default 0x60 if BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED
+	default 0x68 if BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && !BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED
+	default 0x70 if BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && !BAT7_DCACHE_GUARDED
+	default 0x78 if BAT7_DCACHE_WRITETHROUGH && BAT7_DCACHE_INHIBITED && BAT7_DCACHE_MEMORYCOHERENCE && BAT7_DCACHE_GUARDED
+
+config BAT7_VALID_BITS
+	hex
+	default 0x0 if !BAT7_SUPERVISOR_MODE_VALID && !BAT7_USER_MODE_VALID
+	default 0x1 if !BAT7_SUPERVISOR_MODE_VALID && BAT7_USER_MODE_VALID
+	default 0x2 if BAT7_SUPERVISOR_MODE_VALID && !BAT7_USER_MODE_VALID
+	default 0x3 if BAT7_SUPERVISOR_MODE_VALID && BAT7_USER_MODE_VALID
+
+endif
+
+endmenu
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/bats/bats.h b/roms/u-boot/arch/powerpc/cpu/mpc83xx/bats/bats.h
new file mode 100644
index 000000000..f0754c235
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/bats/bats.h
@@ -0,0 +1,223 @@
+#ifdef CONFIG_BAT0
+#define CONFIG_SYS_IBAT0L (\
+		(CONFIG_BAT0_BASE) |\
+		(CONFIG_BAT0_PAGE_PROTECTION) |\
+		(CONFIG_BAT0_WIMG_ICACHE) \
+		)
+#define CONFIG_SYS_IBAT0U (\
+		(CONFIG_BAT0_BASE) |\
+		(CONFIG_BAT0_LENGTH) |\
+		(CONFIG_BAT0_VALID_BITS) \
+		)
+#define CONFIG_SYS_DBAT0L (\
+		(CONFIG_BAT0_BASE) |\
+		(CONFIG_BAT0_PAGE_PROTECTION) |\
+		(CONFIG_BAT0_WIMG_DCACHE) \
+		)
+#define CONFIG_SYS_DBAT0U (\
+		(CONFIG_BAT0_BASE) |\
+		(CONFIG_BAT0_LENGTH) |\
+		(CONFIG_BAT0_VALID_BITS) \
+		)
+#else
+#define CONFIG_SYS_IBAT0L (0)
+#define CONFIG_SYS_IBAT0U (0)
+#define CONFIG_SYS_DBAT0L (0)
+#define CONFIG_SYS_DBAT0U (0)
+#endif /* CONFIG_BAT0 */
+
+#ifdef CONFIG_BAT1
+#define CONFIG_SYS_IBAT1L (\
+		(CONFIG_BAT1_BASE) |\
+		(CONFIG_BAT1_PAGE_PROTECTION) |\
+		(CONFIG_BAT1_WIMG_ICACHE) \
+		)
+#define CONFIG_SYS_IBAT1U (\
+		(CONFIG_BAT1_BASE) |\
+		(CONFIG_BAT1_LENGTH) |\
+		(CONFIG_BAT1_VALID_BITS) \
+		)
+#define CONFIG_SYS_DBAT1L (\
+		(CONFIG_BAT1_BASE) |\
+		(CONFIG_BAT1_PAGE_PROTECTION) |\
+		(CONFIG_BAT1_WIMG_DCACHE) \
+		)
+#define CONFIG_SYS_DBAT1U (\
+		(CONFIG_BAT1_BASE) |\
+		(CONFIG_BAT1_LENGTH) |\
+		(CONFIG_BAT1_VALID_BITS) \
+		)
+#else
+#define CONFIG_SYS_IBAT1L (0)
+#define CONFIG_SYS_IBAT1U (0)
+#define CONFIG_SYS_DBAT1L (0)
+#define CONFIG_SYS_DBAT1U (0)
+#endif /* CONFIG_BAT1 */
+
+#ifdef CONFIG_BAT2
+#define CONFIG_SYS_IBAT2L (\
+		(CONFIG_BAT2_BASE) |\
+		(CONFIG_BAT2_PAGE_PROTECTION) |\
+		(CONFIG_BAT2_WIMG_ICACHE) \
+		)
+#define CONFIG_SYS_IBAT2U (\
+		(CONFIG_BAT2_BASE) |\
+		(CONFIG_BAT2_LENGTH) |\
+		(CONFIG_BAT2_VALID_BITS) \
+		)
+#define CONFIG_SYS_DBAT2L (\
+		(CONFIG_BAT2_BASE) |\
+		(CONFIG_BAT2_PAGE_PROTECTION) |\
+		(CONFIG_BAT2_WIMG_DCACHE) \
+		)
+#define CONFIG_SYS_DBAT2U (\
+		(CONFIG_BAT2_BASE) |\
+		(CONFIG_BAT2_LENGTH) |\
+		(CONFIG_BAT2_VALID_BITS) \
+		)
+#else
+#define CONFIG_SYS_IBAT2L (0)
+#define CONFIG_SYS_IBAT2U (0)
+#define CONFIG_SYS_DBAT2L (0)
+#define CONFIG_SYS_DBAT2U (0)
+#endif /* CONFIG_BAT2 */
+
+#ifdef CONFIG_BAT3
+#define CONFIG_SYS_IBAT3L (\
+		(CONFIG_BAT3_BASE) |\
+		(CONFIG_BAT3_PAGE_PROTECTION) |\
+		(CONFIG_BAT3_WIMG_ICACHE) \
+		)
+#define CONFIG_SYS_IBAT3U (\
+		(CONFIG_BAT3_BASE) |\
+		(CONFIG_BAT3_LENGTH) |\
+		(CONFIG_BAT3_VALID_BITS) \
+		)
+#define CONFIG_SYS_DBAT3L (\
+		(CONFIG_BAT3_BASE) |\
+		(CONFIG_BAT3_PAGE_PROTECTION) |\
+		(CONFIG_BAT3_WIMG_DCACHE) \
+		)
+#define CONFIG_SYS_DBAT3U (\
+		(CONFIG_BAT3_BASE) |\
+		(CONFIG_BAT3_LENGTH) |\
+		(CONFIG_BAT3_VALID_BITS) \
+		)
+#else
+#define CONFIG_SYS_IBAT3L (0)
+#define CONFIG_SYS_IBAT3U (0)
+#define CONFIG_SYS_DBAT3L (0)
+#define CONFIG_SYS_DBAT3U (0)
+#endif /* CONFIG_BAT3 */
+
+#ifdef CONFIG_BAT4
+#define CONFIG_SYS_IBAT4L (\
+		(CONFIG_BAT4_BASE) |\
+		(CONFIG_BAT4_PAGE_PROTECTION) |\
+		(CONFIG_BAT4_WIMG_ICACHE) \
+		)
+#define CONFIG_SYS_IBAT4U (\
+		(CONFIG_BAT4_BASE) |\
+		(CONFIG_BAT4_LENGTH) |\
+		(CONFIG_BAT4_VALID_BITS) \
+		)
+#define CONFIG_SYS_DBAT4L (\
+		(CONFIG_BAT4_BASE) |\
+		(CONFIG_BAT4_PAGE_PROTECTION) |\
+		(CONFIG_BAT4_WIMG_DCACHE) \
+		)
+#define CONFIG_SYS_DBAT4U (\
+		(CONFIG_BAT4_BASE) |\
+		(CONFIG_BAT4_LENGTH) |\
+		(CONFIG_BAT4_VALID_BITS) \
+		)
+#else
+#define CONFIG_SYS_IBAT4L (0)
+#define CONFIG_SYS_IBAT4U (0)
+#define CONFIG_SYS_DBAT4L (0)
+#define CONFIG_SYS_DBAT4U (0)
+#endif /* CONFIG_BAT4 */
+
+#ifdef CONFIG_BAT5
+#define CONFIG_SYS_IBAT5L (\
+		(CONFIG_BAT5_BASE) |\
+		(CONFIG_BAT5_PAGE_PROTECTION) |\
+		(CONFIG_BAT5_WIMG_ICACHE) \
+		)
+#define CONFIG_SYS_IBAT5U (\
+		(CONFIG_BAT5_BASE) |\
+		(CONFIG_BAT5_LENGTH) |\
+		(CONFIG_BAT5_VALID_BITS) \
+		)
+#define CONFIG_SYS_DBAT5L (\
+		(CONFIG_BAT5_BASE) |\
+		(CONFIG_BAT5_PAGE_PROTECTION) |\
+		(CONFIG_BAT5_WIMG_DCACHE) \
+		)
+#define CONFIG_SYS_DBAT5U (\
+		(CONFIG_BAT5_BASE) |\
+		(CONFIG_BAT5_LENGTH) |\
+		(CONFIG_BAT5_VALID_BITS) \
+		)
+#else
+#define CONFIG_SYS_IBAT5L (0)
+#define CONFIG_SYS_IBAT5U (0)
+#define CONFIG_SYS_DBAT5L (0)
+#define CONFIG_SYS_DBAT5U (0)
+#endif /* CONFIG_BAT5 */
+
+#ifdef CONFIG_BAT6
+#define CONFIG_SYS_IBAT6L (\
+		(CONFIG_BAT6_BASE) |\
+		(CONFIG_BAT6_PAGE_PROTECTION) |\
+		(CONFIG_BAT6_WIMG_ICACHE) \
+		)
+#define CONFIG_SYS_IBAT6U (\
+		(CONFIG_BAT6_BASE) |\
+		(CONFIG_BAT6_LENGTH) |\
+		(CONFIG_BAT6_VALID_BITS) \
+		)
+#define CONFIG_SYS_DBAT6L (\
+		(CONFIG_BAT6_BASE) |\
+		(CONFIG_BAT6_PAGE_PROTECTION) |\
+		(CONFIG_BAT6_WIMG_DCACHE) \
+		)
+#define CONFIG_SYS_DBAT6U (\
+		(CONFIG_BAT6_BASE) |\
+		(CONFIG_BAT6_LENGTH) |\
+		(CONFIG_BAT6_VALID_BITS) \
+		)
+#else
+#define CONFIG_SYS_IBAT6L (0)
+#define CONFIG_SYS_IBAT6U (0)
+#define CONFIG_SYS_DBAT6L (0)
+#define CONFIG_SYS_DBAT6U (0)
+#endif /* CONFIG_BAT6 */
+
+#ifdef CONFIG_BAT7
+#define CONFIG_SYS_IBAT7L (\
+		(CONFIG_BAT7_BASE) |\
+		(CONFIG_BAT7_PAGE_PROTECTION) |\
+		(CONFIG_BAT7_WIMG_ICACHE) \
+		)
+#define CONFIG_SYS_IBAT7U (\
+		(CONFIG_BAT7_BASE) |\
+		(CONFIG_BAT7_LENGTH) |\
+		(CONFIG_BAT7_VALID_BITS) \
+		)
+#define CONFIG_SYS_DBAT7L (\
+		(CONFIG_BAT7_BASE) |\
+		(CONFIG_BAT7_PAGE_PROTECTION) |\
+		(CONFIG_BAT7_WIMG_DCACHE) \
+		)
+#define CONFIG_SYS_DBAT7U (\
+		(CONFIG_BAT7_BASE) |\
+		(CONFIG_BAT7_LENGTH) |\
+		(CONFIG_BAT7_VALID_BITS) \
+		)
+#else
+#define CONFIG_SYS_IBAT7L (0)
+#define CONFIG_SYS_IBAT7U (0)
+#define CONFIG_SYS_DBAT7L (0)
+#define CONFIG_SYS_DBAT7U (0)
+#endif /* CONFIG_BAT7 */
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/config.mk b/roms/u-boot/arch/powerpc/cpu/mpc83xx/config.mk
new file mode 100644
index 000000000..a07df4d38
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/config.mk
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2004 Freescale Semiconductor, Inc.
+
+PLATFORM_CPPFLAGS += -DCONFIG_E300 -msoft-float
+PLATFORM_RELFLAGS += -msingle-pic-base -fno-jump-tables
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/cpu.c b/roms/u-boot/arch/powerpc/cpu/mpc83xx/cpu.c
new file mode 100644
index 000000000..8d531898b
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * CPU specific code for the MPC83xx family.
+ *
+ * Derived from the MPC8260 and MPC85xx.
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <irq_func.h>
+#include <net.h>
+#include <time.h>
+#include <vsprintf.h>
+#include <watchdog.h>
+#include <command.h>
+#include <mpc83xx.h>
+#include <asm/global_data.h>
+#include <asm/processor.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <tsec.h>
+#include <netdev.h>
+#include <fsl_esdhc.h>
+#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_ARCH_MPC831X)
+#include <linux/immap_qe.h>
+#include <asm/io.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_CPU_MPC83XX
+int checkcpu(void)
+{
+	volatile immap_t *immr;
+	ulong clock = gd->cpu_clk;
+	u32 pvr = get_pvr();
+	u32 spridr;
+	char buf[32];
+	int ret;
+	int i;
+
+	const struct cpu_type {
+		char name[15];
+		u32 partid;
+	} cpu_type_list [] = {
+		CPU_TYPE_ENTRY(8308),
+		CPU_TYPE_ENTRY(8309),
+		CPU_TYPE_ENTRY(8311),
+		CPU_TYPE_ENTRY(8313),
+		CPU_TYPE_ENTRY(8314),
+		CPU_TYPE_ENTRY(8315),
+		CPU_TYPE_ENTRY(8321),
+		CPU_TYPE_ENTRY(8323),
+		CPU_TYPE_ENTRY(8343),
+		CPU_TYPE_ENTRY(8347_TBGA_),
+		CPU_TYPE_ENTRY(8347_PBGA_),
+		CPU_TYPE_ENTRY(8349),
+		CPU_TYPE_ENTRY(8358_TBGA_),
+		CPU_TYPE_ENTRY(8358_PBGA_),
+		CPU_TYPE_ENTRY(8360),
+		CPU_TYPE_ENTRY(8377),
+		CPU_TYPE_ENTRY(8378),
+		CPU_TYPE_ENTRY(8379),
+	};
+
+	immr = (immap_t *)CONFIG_SYS_IMMR;
+
+	ret = prt_83xx_rsr();
+	if (ret)
+		return ret;
+
+	puts("CPU:   ");
+
+	switch (pvr & 0xffff0000) {
+		case PVR_E300C1:
+			printf("e300c1, ");
+			break;
+
+		case PVR_E300C2:
+			printf("e300c2, ");
+			break;
+
+		case PVR_E300C3:
+			printf("e300c3, ");
+			break;
+
+		case PVR_E300C4:
+			printf("e300c4, ");
+			break;
+
+		default:
+			printf("Unknown core, ");
+	}
+
+	spridr = immr->sysconf.spridr;
+
+	for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
+		if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
+			puts("MPC");
+			puts(cpu_type_list[i].name);
+			if (IS_E_PROCESSOR(spridr))
+				puts("E");
+			if ((SPR_FAMILY(spridr) == SPR_834X_FAMILY ||
+			     SPR_FAMILY(spridr) == SPR_836X_FAMILY) &&
+			    REVID_MAJOR(spridr) >= 2)
+				puts("A");
+			printf(", Rev: %d.%d", REVID_MAJOR(spridr),
+			       REVID_MINOR(spridr));
+			break;
+		}
+
+	if (i == ARRAY_SIZE(cpu_type_list))
+		printf("(SPRIDR %08x unknown), ", spridr);
+
+	printf(" at %s MHz, ", strmhz(buf, clock));
+
+	printf("CSB: %s MHz\n", strmhz(buf, gd->arch.csb_clk));
+
+	return 0;
+}
+#endif
+
+#ifndef CONFIG_SYSRESET
+int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	ulong msr;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+	puts("Resetting the board.\n");
+
+	/* Interrupts and MMU off */
+	msr = mfmsr();
+	msr &= ~(MSR_EE | MSR_IR | MSR_DR);
+	mtmsr(msr);
+
+	/* enable Reset Control Reg */
+	immap->reset.rpr = 0x52535445;
+	sync();
+	isync();
+
+	/* confirm Reset Control Reg is enabled */
+	while(!((immap->reset.rcer) & RCER_CRE))
+		;
+
+	udelay(200);
+
+	/* perform reset, only one bit */
+	immap->reset.rcr = RCR_SWHR;
+
+	return 1;
+}
+#endif
+
+/*
+ * Get timebase clock frequency (like cpu_clk in Hz)
+ */
+#ifndef CONFIG_TIMER
+unsigned long get_tbclk(void)
+{
+	return (gd->bus_clk + 3L) / 4L;
+}
+#endif
+
+#if defined(CONFIG_WATCHDOG)
+void watchdog_reset (void)
+{
+	int re_enable = disable_interrupts();
+
+	/* Reset the 83xx watchdog */
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	immr->wdt.swsrr = 0x556c;
+	immr->wdt.swsrr = 0xaa39;
+
+	if (re_enable)
+		enable_interrupts();
+}
+#endif
+
+#ifndef CONFIG_DM_ETH
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int cpu_eth_init(struct bd_info *bis)
+{
+#if defined(CONFIG_UEC_ETH)
+	uec_standard_init(bis);
+#endif
+
+#if defined(CONFIG_TSEC_ENET)
+	tsec_standard_init(bis);
+#endif
+	return 0;
+}
+#endif /* !CONFIG_DM_ETH */
+
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(struct bd_info *bis)
+{
+#ifdef CONFIG_FSL_ESDHC
+	return fsl_esdhc_mmc_init(bis);
+#else
+	return 0;
+#endif
+}
+
+void ppcDWstore(unsigned int *addr, unsigned int *value)
+{
+	asm("lfd 1, 0(%1)\n\t"
+	    "stfd 1, 0(%0)"
+	    :
+	    : "r" (addr), "r" (value)
+	    : "memory");
+}
+
+void ppcDWload(unsigned int *addr, unsigned int *ret)
+{
+	asm("lfd 1, 0(%0)\n\t"
+	    "stfd 1, 0(%1)"
+	    :
+	    : "r" (addr), "r" (ret)
+	    : "memory");
+}
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/cpu_init.c b/roms/u-boot/arch/powerpc/cpu/mpc83xx/cpu_init.c
new file mode 100644
index 000000000..e6dcb8a33
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -0,0 +1,447 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <asm-offsets.h>
+#include <mpc83xx.h>
+#include <ioports.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <fsl_qe.h>
+#ifdef CONFIG_USB_EHCI_FSL
+#include <usb/ehci-ci.h>
+#endif
+#include <linux/delay.h>
+#ifdef CONFIG_QE
+#include <fsl_qe.h>
+#endif
+
+#include "lblaw/lblaw.h"
+#include "elbc/elbc.h"
+#include "sysio/sysio.h"
+#include "arbiter/arbiter.h"
+#include "initreg/initreg.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_QE
+extern qe_iop_conf_t qe_iop_conf_tab[];
+extern void qe_config_iopin(u8 port, u8 pin, int dir,
+			 int open_drain, int assign);
+
+#if !defined(CONFIG_PINCTRL)
+static void config_qe_ioports(void)
+{
+	u8	port, pin;
+	int	dir, open_drain, assign;
+	int	i;
+
+	for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
+		port		= qe_iop_conf_tab[i].port;
+		pin		= qe_iop_conf_tab[i].pin;
+		dir		= qe_iop_conf_tab[i].dir;
+		open_drain	= qe_iop_conf_tab[i].open_drain;
+		assign		= qe_iop_conf_tab[i].assign;
+		qe_config_iopin(port, pin, dir, open_drain, assign);
+	}
+}
+#endif
+#endif
+
+/*
+ * Breathe some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f (volatile immap_t * im)
+{
+	__be32 sccr_mask =
+#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
+		SCCR_ENCCM |
+#endif
+#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
+		SCCR_PCICM |
+#endif
+#ifdef CONFIG_SYS_SCCR_PCIEXP1CM	/* PCIE1 clock mode */
+		SCCR_PCIEXP1CM |
+#endif
+#ifdef CONFIG_SYS_SCCR_PCIEXP2CM	/* PCIE2 clock mode */
+		SCCR_PCIEXP2CM |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
+		SCCR_TSECCM |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
+		SCCR_TSEC1CM |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
+		SCCR_TSEC2CM |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
+		SCCR_TSEC1ON |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
+		SCCR_TSEC2ON |
+#endif
+#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
+		SCCR_USBMPHCM |
+#endif
+#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
+		SCCR_USBDRCM |
+#endif
+#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
+		SCCR_SATACM |
+#endif
+		0;
+	__be32 sccr_val =
+#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
+		(CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
+		(CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_PCIEXP1CM	/* PCIE1 clock mode */
+		(CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_PCIEXP2CM	/* PCIE2 clock mode */
+		(CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
+		(CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
+		(CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
+		(CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
+		(CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
+		(CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
+		(CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
+		(CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
+		(CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
+#endif
+		0;
+
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+
+	/* global data region was cleared in start.S */
+
+	/* system performance tweaking */
+	clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
+
+	clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
+
+	clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
+
+	/* RSR - Reset Status Register - clear all status (4.6.1.3) */
+	gd->arch.reset_status = __raw_readl(&im->reset.rsr);
+	__raw_writel(~(RSR_RES), &im->reset.rsr);
+
+	/* AER - Arbiter Event Register - store status */
+	gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
+	gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
+
+	/*
+	 * RMR - Reset Mode Register
+	 * contains checkstop reset enable (4.6.1.4)
+	 */
+	__raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
+
+	/* LCRR - Clock Ratio Register (10.3.1.16)
+	 * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
+	 */
+	clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
+	__raw_readl(&im->im_lbc.lcrr);
+	isync();
+
+	/* Enable Time Base & Decrementer ( so we will have udelay() )*/
+	setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
+
+	/* System General Purpose Register */
+#ifdef CONFIG_SYS_SICRH
+#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
+	/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
+	__raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
+		     &im->sysconf.sicrh);
+#else
+	__raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
+#endif
+#endif
+#ifdef CONFIG_SYS_SICRL
+	__raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
+#endif
+#ifdef CONFIG_SYS_GPR1
+	__raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
+#endif
+#ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
+	__raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
+#endif
+#ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
+	__raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
+#endif
+
+#if !defined(CONFIG_PINCTRL)
+#ifdef CONFIG_QE
+	/* Config QE ioports */
+	config_qe_ioports();
+#endif
+#endif
+
+	/* Set up preliminary BR/OR regs */
+	init_early_memctl_regs();
+
+	/* Local Access window setup */
+#if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
+	im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
+	im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
+#else
+#error	CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
+#endif
+
+#if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
+	im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
+	im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
+#endif
+#if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
+	im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
+	im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
+#endif
+#if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
+	im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
+	im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
+#endif
+#if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
+	im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
+	im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
+#endif
+#if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
+	im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
+	im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
+#endif
+#if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
+	im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
+	im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
+#endif
+#if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
+	im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
+	im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
+#endif
+#ifdef CONFIG_SYS_GPIO1_PRELIM
+	im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
+	im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
+#endif
+#ifdef CONFIG_SYS_GPIO2_PRELIM
+	im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
+	im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
+#endif
+#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X)
+	uint32_t temp;
+	struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
+
+	/* Configure interface. */
+	setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
+
+	/* Wait for clock to stabilize */
+	do {
+		temp = __raw_readl(&ehci->control);
+		udelay(1000);
+	} while (!(temp & PHY_CLK_VALID));
+#endif
+}
+
+int cpu_init_r (void)
+{
+#ifdef CONFIG_QE
+	uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
+
+	qe_init(qe_base);
+	qe_reset();
+#endif
+	return 0;
+}
+
+/*
+ * Print out the bus arbiter event
+ */
+#if defined(CONFIG_DISPLAY_AER_FULL)
+static int print_83xx_arb_event(int force)
+{
+	static char* event[] = {
+		"Address Time Out",
+		"Data Time Out",
+		"Address Only Transfer Type",
+		"External Control Word Transfer Type",
+		"Reserved Transfer Type",
+		"Transfer Error",
+		"reserved",
+		"reserved"
+	};
+	static char* master[] = {
+		"e300 Core Data Transaction",
+		"reserved",
+		"e300 Core Instruction Fetch",
+		"reserved",
+		"TSEC1",
+		"TSEC2",
+		"USB MPH",
+		"USB DR",
+		"Encryption Core",
+		"I2C Boot Sequencer",
+		"JTAG",
+		"reserved",
+		"eSDHC",
+		"PCI1",
+		"PCI2",
+		"DMA",
+		"QUICC Engine 00",
+		"QUICC Engine 01",
+		"QUICC Engine 10",
+		"QUICC Engine 11",
+		"reserved",
+		"reserved",
+		"reserved",
+		"reserved",
+		"SATA1",
+		"SATA2",
+		"SATA3",
+		"SATA4",
+		"reserved",
+		"PCI Express 1",
+		"PCI Express 2",
+		"TDM-DMAC"
+	};
+	static char *transfer[] = {
+		"Address-only, Clean Block",
+		"Address-only, lwarx reservation set",
+		"Single-beat or Burst write",
+		"reserved",
+		"Address-only, Flush Block",
+		"reserved",
+		"Burst write",
+		"reserved",
+		"Address-only, sync",
+		"Address-only, tlbsync",
+		"Single-beat or Burst read",
+		"Single-beat or Burst read",
+		"Address-only, Kill Block",
+		"Address-only, icbi",
+		"Burst read",
+		"reserved",
+		"Address-only, eieio",
+		"reserved",
+		"Single-beat write",
+		"reserved",
+		"ecowx - Illegal single-beat write",
+		"reserved",
+		"reserved",
+		"reserved",
+		"Address-only, TLB Invalidate",
+		"reserved",
+		"Single-beat or Burst read",
+		"reserved",
+		"eciwx - Illegal single-beat read",
+		"reserved",
+		"Burst read",
+		"reserved"
+	};
+
+	int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
+		    >> AEATR_EVENT_SHIFT;
+	int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
+		      >> AEATR_MSTR_ID_SHIFT;
+	int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
+		   >> AEATR_TBST_SHIFT;
+	int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
+		    >> AEATR_TSIZE_SHIFT;
+	int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
+		    >> AEATR_TTYPE_SHIFT;
+
+	if (!force && !gd->arch.arbiter_event_address)
+		return 0;
+
+	puts("Arbiter Event Status:\n");
+	printf("       Event Address: 0x%08lX\n",
+	       gd->arch.arbiter_event_address);
+	printf("       Event Type:    0x%1x  = %s\n", etype, event[etype]);
+	printf("       Master ID:     0x%02x = %s\n", mstr_id, master[mstr_id]);
+	printf("       Transfer Size: 0x%1x  = %d bytes\n", (tbst<<3) | tsize,
+				tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
+	printf("       Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
+
+	return gd->arch.arbiter_event_address;
+}
+
+#elif defined(CONFIG_DISPLAY_AER_BRIEF)
+
+static int print_83xx_arb_event(int force)
+{
+	if (!force && !gd->arch.arbiter_event_address)
+		return 0;
+
+	printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
+		gd->arch.arbiter_event_attributes,
+		gd->arch.arbiter_event_address);
+
+	return gd->arch.arbiter_event_address;
+}
+#endif /* CONFIG_DISPLAY_AER_xxxx */
+
+#ifndef CONFIG_CPU_MPC83XX
+/*
+ * Figure out the cause of the reset
+ */
+int prt_83xx_rsr(void)
+{
+	static struct {
+		ulong mask;
+		char *desc;
+	} bits[] = {
+		{
+		RSR_SWSR, "Software Soft"}, {
+		RSR_SWHR, "Software Hard"}, {
+		RSR_JSRS, "JTAG Soft"}, {
+		RSR_CSHR, "Check Stop"}, {
+		RSR_SWRS, "Software Watchdog"}, {
+		RSR_BMRS, "Bus Monitor"}, {
+		RSR_SRS,  "External/Internal Soft"}, {
+		RSR_HRS,  "External/Internal Hard"}
+	};
+	static int n = ARRAY_SIZE(bits);
+	ulong rsr = gd->arch.reset_status;
+	int i;
+	char *sep;
+
+	puts("Reset Status:");
+
+	sep = " ";
+	for (i = 0; i < n; i++)
+		if (rsr & bits[i].mask) {
+			printf("%s%s", sep, bits[i].desc);
+			sep = ", ";
+		}
+	puts("\n");
+
+#if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
+	print_83xx_arb_event(rsr & RSR_BMRS);
+#endif
+	puts("\n");
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/ecc.c b/roms/u-boot/arch/powerpc/cpu/mpc83xx/ecc.c
new file mode 100644
index 000000000..1343dd3d3
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/ecc.c
@@ -0,0 +1,389 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ * based on the contribution of Marian Balakowicz <m8@semihalf.com>
+ */
+
+#include <common.h>
+#include <irq_func.h>
+#include <mpc83xx.h>
+#include <command.h>
+
+#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
+void ecc_print_status(void)
+{
+	immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+#ifdef CONFIG_SYS_FSL_DDR2
+	struct ccsr_ddr __iomem *ddr = &immap->ddr;
+#else
+	ddr83xx_t *ddr = &immap->ddr;
+#endif
+
+	printf("\nECC mode: %s\n\n",
+	       (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
+
+	/* Interrupts */
+	printf("Memory Error Interrupt Enable:\n");
+	printf("  Multiple-Bit Error Interrupt Enable: %d\n",
+	       (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
+	printf("  Single-Bit Error Interrupt Enable: %d\n",
+	       (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
+	printf("  Memory Select Error Interrupt Enable: %d\n\n",
+	       (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
+
+	/* Error disable */
+	printf("Memory Error Disable:\n");
+	printf("  Multiple-Bit Error Disable: %d\n",
+	       (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
+	printf("  Single-Bit Error Disable: %d\n",
+	       (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
+	printf("  Memory Select Error Disable: %d\n\n",
+	       (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
+
+	/* Error injection */
+	printf("Memory Data Path Error Injection Mask High/Low: %08x %08x\n",
+	       ddr->data_err_inject_hi, ddr->data_err_inject_lo);
+
+	printf("Memory Data Path Error Injection Mask ECC:\n");
+	printf("  ECC Mirror Byte: %d\n",
+	       (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
+	printf("  ECC Injection Enable: %d\n",
+	       (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
+	printf("  ECC Error Injection Mask: 0x%02x\n\n",
+	       ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
+
+	/* SBE counter/threshold */
+	printf("Memory Single-Bit Error Management (0..255):\n");
+	printf("  Single-Bit Error Threshold: %d\n",
+	       (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
+	printf("  Single-Bit Error Counter: %d\n\n",
+	       (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
+
+	/* Error detect */
+	printf("Memory Error Detect:\n");
+	printf("  Multiple Memory Errors: %d\n",
+	       (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
+	printf("  Multiple-Bit Error: %d\n",
+	       (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
+	printf("  Single-Bit Error: %d\n",
+	       (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
+	printf("  Memory Select Error: %d\n\n",
+	       (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
+
+	/* Capture data */
+	printf("Memory Error Address Capture: 0x%08x\n", ddr->capture_address);
+	printf("Memory Data Path Read Capture High/Low: %08x %08x\n",
+	       ddr->capture_data_hi, ddr->capture_data_lo);
+	printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
+	       ddr->capture_ecc & CAPTURE_ECC_ECE);
+
+	printf("Memory Error Attributes Capture:\n");
+	printf(" Data Beat Number: %d\n",
+	       (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >>
+	       ECC_CAPT_ATTR_BNUM_SHIFT);
+	printf("  Transaction Size: %d\n",
+	       (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >>
+	       ECC_CAPT_ATTR_TSIZ_SHIFT);
+	printf("  Transaction Source: %d\n",
+	       (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >>
+	       ECC_CAPT_ATTR_TSRC_SHIFT);
+	printf("  Transaction Type: %d\n",
+	       (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >>
+	       ECC_CAPT_ATTR_TTYP_SHIFT);
+	printf("  Error Information Valid: %d\n\n",
+	       ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
+}
+
+int do_ecc(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+#ifdef CONFIG_SYS_FSL_DDR2
+	struct ccsr_ddr __iomem *ddr = &immap->ddr;
+#else
+	ddr83xx_t *ddr = &immap->ddr;
+#endif
+	volatile u32 val;
+	u64 *addr;
+	u32 count;
+	register u64 *i;
+	u32 ret[2];
+	u32 pattern[2];
+	u32 writeback[2];
+
+	/* The pattern is written into memory to generate error */
+	pattern[0] = 0xfedcba98UL;
+	pattern[1] = 0x76543210UL;
+
+	/* After injecting error, re-initialize the memory with the value */
+	writeback[0] = 0x01234567UL;
+	writeback[1] = 0x89abcdefUL;
+
+	if (argc > 4)
+		return cmd_usage(cmdtp);
+
+	if (argc == 2) {
+		if (strcmp(argv[1], "status") == 0) {
+			ecc_print_status();
+			return 0;
+		} else if (strcmp(argv[1], "captureclear") == 0) {
+			ddr->capture_address = 0;
+			ddr->capture_data_hi = 0;
+			ddr->capture_data_lo = 0;
+			ddr->capture_ecc = 0;
+			ddr->capture_attributes = 0;
+			return 0;
+		}
+	}
+	if (argc == 3) {
+		if (strcmp(argv[1], "sbecnt") == 0) {
+			val = simple_strtoul(argv[2], NULL, 10);
+			if (val > 255) {
+				printf("Incorrect Counter value, "
+				       "should be 0..255\n");
+				return 1;
+			}
+
+			val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
+			val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
+
+			ddr->err_sbe = val;
+			return 0;
+		} else if (strcmp(argv[1], "sbethr") == 0) {
+			val = simple_strtoul(argv[2], NULL, 10);
+			if (val > 255) {
+				printf("Incorrect Counter value, "
+				       "should be 0..255\n");
+				return 1;
+			}
+
+			val = (val << ECC_ERROR_MAN_SBET_SHIFT);
+			val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
+
+			ddr->err_sbe = val;
+			return 0;
+		} else if (strcmp(argv[1], "errdisable") == 0) {
+			val = ddr->err_disable;
+
+			if (strcmp(argv[2], "+sbe") == 0) {
+				val |= ECC_ERROR_DISABLE_SBED;
+			} else if (strcmp(argv[2], "+mbe") == 0) {
+				val |= ECC_ERROR_DISABLE_MBED;
+			} else if (strcmp(argv[2], "+mse") == 0) {
+				val |= ECC_ERROR_DISABLE_MSED;
+			} else if (strcmp(argv[2], "+all") == 0) {
+				val |= (ECC_ERROR_DISABLE_SBED |
+					ECC_ERROR_DISABLE_MBED |
+					ECC_ERROR_DISABLE_MSED);
+			} else if (strcmp(argv[2], "-sbe") == 0) {
+				val &= ~ECC_ERROR_DISABLE_SBED;
+			} else if (strcmp(argv[2], "-mbe") == 0) {
+				val &= ~ECC_ERROR_DISABLE_MBED;
+			} else if (strcmp(argv[2], "-mse") == 0) {
+				val &= ~ECC_ERROR_DISABLE_MSED;
+			} else if (strcmp(argv[2], "-all") == 0) {
+				val &= ~(ECC_ERROR_DISABLE_SBED |
+					 ECC_ERROR_DISABLE_MBED |
+					 ECC_ERROR_DISABLE_MSED);
+			} else {
+				printf("Incorrect err_disable field\n");
+				return 1;
+			}
+
+			ddr->err_disable = val;
+			sync();
+			isync();
+			return 0;
+		} else if (strcmp(argv[1], "errdetectclr") == 0) {
+			val = ddr->err_detect;
+
+			if (strcmp(argv[2], "mme") == 0) {
+				val |= ECC_ERROR_DETECT_MME;
+			} else if (strcmp(argv[2], "sbe") == 0) {
+				val |= ECC_ERROR_DETECT_SBE;
+			} else if (strcmp(argv[2], "mbe") == 0) {
+				val |= ECC_ERROR_DETECT_MBE;
+			} else if (strcmp(argv[2], "mse") == 0) {
+				val |= ECC_ERROR_DETECT_MSE;
+			} else if (strcmp(argv[2], "all") == 0) {
+				val |= (ECC_ERROR_DETECT_MME |
+					ECC_ERROR_DETECT_MBE |
+					ECC_ERROR_DETECT_SBE |
+					ECC_ERROR_DETECT_MSE);
+			} else {
+				printf("Incorrect err_detect field\n");
+				return 1;
+			}
+
+			ddr->err_detect = val;
+			return 0;
+		} else if (strcmp(argv[1], "injectdatahi") == 0) {
+			val = simple_strtoul(argv[2], NULL, 16);
+
+			ddr->data_err_inject_hi = val;
+			return 0;
+		} else if (strcmp(argv[1], "injectdatalo") == 0) {
+			val = simple_strtoul(argv[2], NULL, 16);
+
+			ddr->data_err_inject_lo = val;
+			return 0;
+		} else if (strcmp(argv[1], "injectecc") == 0) {
+			val = simple_strtoul(argv[2], NULL, 16);
+			if (val > 0xff) {
+				printf("Incorrect ECC inject mask, "
+				       "should be 0x00..0xff\n");
+				return 1;
+			}
+			val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
+
+			ddr->ecc_err_inject = val;
+			return 0;
+		} else if (strcmp(argv[1], "inject") == 0) {
+			val = ddr->ecc_err_inject;
+
+			if (strcmp(argv[2], "en") == 0)
+				val |= ECC_ERR_INJECT_EIEN;
+			else if (strcmp(argv[2], "dis") == 0)
+				val &= ~ECC_ERR_INJECT_EIEN;
+			else
+				printf("Incorrect command\n");
+
+			ddr->ecc_err_inject = val;
+			sync();
+			isync();
+			return 0;
+		} else if (strcmp(argv[1], "mirror") == 0) {
+			val = ddr->ecc_err_inject;
+
+			if (strcmp(argv[2], "en") == 0)
+				val |= ECC_ERR_INJECT_EMB;
+			else if (strcmp(argv[2], "dis") == 0)
+				val &= ~ECC_ERR_INJECT_EMB;
+			else
+				printf("Incorrect command\n");
+
+			ddr->ecc_err_inject = val;
+			return 0;
+		}
+	}
+	if (argc == 4) {
+		if (strcmp(argv[1], "testdw") == 0) {
+			addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
+			count = simple_strtoul(argv[3], NULL, 16);
+
+			if ((u32) addr % 8) {
+				printf("Address not aligned on "
+				       "double word boundary\n");
+				return 1;
+			}
+			disable_interrupts();
+
+			for (i = addr; i < addr + count; i++) {
+
+				/* enable injects */
+				ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
+				sync();
+				isync();
+
+				/* write memory location injecting errors */
+				ppcDWstore((u32 *) i, pattern);
+				sync();
+
+				/* disable injects */
+				ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
+				sync();
+				isync();
+
+				/* read data, this generates ECC error */
+				ppcDWload((u32 *) i, ret);
+				sync();
+
+				/* re-initialize memory, double word write the location again,
+				 * generates new ECC code this time */
+				ppcDWstore((u32 *) i, writeback);
+				sync();
+			}
+			enable_interrupts();
+			return 0;
+		}
+		if (strcmp(argv[1], "testword") == 0) {
+			addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
+			count = simple_strtoul(argv[3], NULL, 16);
+
+			if ((u32) addr % 8) {
+				printf("Address not aligned on "
+				       "double word boundary\n");
+				return 1;
+			}
+			disable_interrupts();
+
+			for (i = addr; i < addr + count; i++) {
+
+				/* enable injects */
+				ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
+				sync();
+				isync();
+
+				/* write memory location injecting errors */
+				*(u32 *) i = 0xfedcba98UL;
+				sync();
+
+				/* sub double word write,
+				 * bus will read-modify-write,
+				 * generates ECC error */
+				*((u32 *) i + 1) = 0x76543210UL;
+				sync();
+
+				/* disable injects */
+				ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
+				sync();
+				isync();
+
+				/* re-initialize memory,
+				 * double word write the location again,
+				 * generates new ECC code this time */
+				ppcDWstore((u32 *) i, writeback);
+				sync();
+			}
+			enable_interrupts();
+			return 0;
+		}
+	}
+	return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(ecc, 4, 0, do_ecc,
+	   "support for DDR ECC features",
+	   "status              - print out status info\n"
+	   "ecc captureclear        - clear capture regs data\n"
+	   "ecc sbecnt <val>        - set Single-Bit Error counter\n"
+	   "ecc sbethr <val>        - set Single-Bit Threshold\n"
+	   "ecc errdisable <flag>   - clear/set disable Memory Error Disable, flag:\n"
+	   "  [-|+]sbe - Single-Bit Error\n"
+	   "  [-|+]mbe - Multiple-Bit Error\n"
+	   "  [-|+]mse - Memory Select Error\n"
+	   "  [-|+]all - all errors\n"
+	   "ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
+	   "  mme - Multiple Memory Errors\n"
+	   "  sbe - Single-Bit Error\n"
+	   "  mbe - Multiple-Bit Error\n"
+	   "  mse - Memory Select Error\n"
+	   "  all - all errors\n"
+	   "ecc injectdatahi <hi>  - set Memory Data Path Error Injection Mask High\n"
+	   "ecc injectdatalo <lo>  - set Memory Data Path Error Injection Mask Low\n"
+	   "ecc injectecc <ecc>    - set ECC Error Injection Mask\n"
+	   "ecc inject <en|dis>    - enable/disable error injection\n"
+	   "ecc mirror <en|dis>    - enable/disable mirror byte\n"
+	   "ecc testdw <addr> <cnt>  - test mem region with double word access:\n"
+	   "  - enables injects\n"
+	   "  - writes pattern injecting errors with double word access\n"
+	   "  - disables injects\n"
+	   "  - reads pattern back with double word access, generates error\n"
+	   "  - re-inits memory\n"
+	   "ecc testword <addr> <cnt>  - test mem region with word access:\n"
+	   "  - enables injects\n"
+	   "  - writes pattern injecting errors with word access\n"
+	   "  - writes pattern with word access, generates error\n"
+	   "  - disables injects\n" "  - re-inits memory");
+#endif
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig b/roms/u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig
new file mode 100644
index 000000000..74c4ff3ed
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig
@@ -0,0 +1,32 @@
+menu "ELBC register setup"
+
+choice
+	prompt "OR/BR for NAND SPL"
+
+config ELBC_BR_OR_NAND_PRELIM_NONE
+	bool "None"
+
+config ELBC_BR_OR_NAND_PRELIM_0
+	bool "0"
+
+config ELBC_BR_OR_NAND_PRELIM_1
+	bool "1"
+
+config ELBC_BR_OR_NAND_PRELIM_2
+	bool "2"
+
+config ELBC_BR_OR_NAND_PRELIM_3
+	bool "3"
+
+config ELBC_BR_OR_NAND_PRELIM_4
+	bool "4"
+
+endchoice
+
+source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0"
+source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1"
+source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2"
+source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3"
+source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4"
+
+endmenu
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 b/roms/u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0
new file mode 100644
index 000000000..23e81ab0b
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0
@@ -0,0 +1,733 @@
+menuconfig ELBC_BR0_OR0
+	bool "ELBC BR0/OR0"
+
+if ELBC_BR0_OR0
+
+config BR0_OR0_NAME
+	string "Identifier"
+
+config BR0_OR0_BASE
+	hex "Port base"
+
+choice
+	prompt "Port size"
+
+config BR0_PORTSIZE_8BIT
+	bool "8-bit"
+
+config BR0_PORTSIZE_16BIT
+	depends on !BR0_MACHINE_FCM
+	bool "16-bit"
+
+
+config BR0_PORTSIZE_32BIT
+	depends on !BR0_MACHINE_FCM
+	depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+	bool "32-bit"
+
+endchoice
+
+if BR0_MACHINE_FCM
+
+choice
+	prompt "Data Error Checking"
+
+config BR0_ERRORCHECKING_DISABLED
+	bool "Disabled"
+
+config BR0_ERRORCHECKING_ECC_CHECKING
+	bool "ECC checking / No ECC generation"
+
+config BR0_ERRORCHECKING_BOTH
+	bool "ECC checking and generation"
+
+endchoice
+
+endif
+
+config BR0_WRITE_PROTECT
+	bool "Write-protect"
+
+config BR0_MACHINE_UPM
+	bool
+
+choice
+	prompt "Machine select"
+
+config BR0_MACHINE_GPCM
+	bool "GPCM"
+
+config BR0_MACHINE_FCM
+	depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+	bool "FCM"
+
+config BR0_MACHINE_SDRAM
+	depends on ARCH_MPC8349 || ARCH_MPC8360
+	bool "SDRAM"
+
+config BR0_MACHINE_UPMA
+	select BR0_MACHINE_UPM
+	bool "UPM (A)"
+
+config BR0_MACHINE_UPMB
+	select BR0_MACHINE_UPM
+	bool "UPM (B)"
+
+config BR0_MACHINE_UPMC
+	select BR0_MACHINE_UPM
+	bool "UPM (C)"
+
+endchoice
+
+if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
+
+choice
+	prompt "Atomic operations"
+
+config BR0_ATOMIC_NONE
+	bool "No atomic operations"
+
+config BR0_ATOMIC_RAWA
+	bool "Read-after-write-atomic"
+
+config BR0_ATOMIC_WARA
+	bool "Write-after-read-atomic"
+
+endchoice
+
+endif
+
+if BR0_MACHINE_GPCM || BR0_MACHINE_FCM || BR0_MACHINE_UPM || BR0_MACHINE_SDRAM
+
+choice
+	prompt "Address mask"
+
+config OR0_AM_32_KBYTES
+	depends on !BR0_MACHINE_SDRAM
+	bool "32 kb"
+
+config OR0_AM_64_KBYTES
+	bool "64 kb"
+
+config OR0_AM_128_KBYTES
+	bool "128 kb"
+
+config OR0_AM_256_KBYTES
+	bool "256 kb"
+
+config OR0_AM_512_KBYTES
+	bool "512 kb"
+
+config OR0_AM_1_MBYTES
+	bool "1 mb"
+
+config OR0_AM_2_MBYTES
+	bool "2 mb"
+
+config OR0_AM_4_MBYTES
+	bool "4 mb"
+
+config OR0_AM_8_MBYTES
+	bool "8 mb"
+
+config OR0_AM_16_MBYTES
+	bool "16 mb"
+
+config OR0_AM_32_MBYTES
+	bool "32 mb"
+
+config OR0_AM_64_MBYTES
+	bool "64 mb"
+
+# XXX: Some boards define 128MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR0_AM_128_MBYTES
+	bool "128 mb"
+
+# XXX: Some boards define 256MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR0_AM_256_MBYTES
+	bool "256 mb"
+
+config OR0_AM_512_MBYTES
+	depends on BR0_MACHINE_FCM
+	bool "512 mb"
+
+# XXX: Some boards define 1GB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR0_AM_1_GBYTES
+	bool "1 gb"
+
+config OR0_AM_2_GBYTES
+	depends on BR0_MACHINE_FCM
+	bool "2 gb"
+
+config OR0_AM_4_GBYTES
+	depends on BR0_MACHINE_FCM
+	bool "4 gb"
+
+endchoice
+
+config OR0_XAM_SET
+	bool "Set unused bytes after address mask"
+choice
+	prompt "Buffer control disable"
+
+config OR0_BCTLD_ASSERTED
+	bool "Asserted"
+
+config OR0_BCTLD_NOT_ASSERTED
+	bool "Not asserted"
+
+endchoice
+
+endif
+
+if BR0_MACHINE_GPCM || BR0_MACHINE_FCM
+
+choice
+	prompt "Cycle length in bus clocks"
+
+config OR0_SCY_0
+	bool "No wait states"
+
+config OR0_SCY_1
+	bool "1 wait state"
+
+config OR0_SCY_2
+	bool "2 wait states"
+
+config OR0_SCY_3
+	bool "3 wait states"
+
+config OR0_SCY_4
+	bool "4 wait states"
+
+config OR0_SCY_5
+	bool "5 wait states"
+
+config OR0_SCY_6
+	bool "6 wait states"
+
+config OR0_SCY_7
+	bool "7 wait states"
+
+config OR0_SCY_8
+	depends on BR0_MACHINE_GPCM
+	bool "8 wait states"
+
+config OR0_SCY_9
+	depends on BR0_MACHINE_GPCM
+	bool "9 wait states"
+
+config OR0_SCY_10
+	depends on BR0_MACHINE_GPCM
+	bool "10 wait states"
+
+config OR0_SCY_11
+	depends on BR0_MACHINE_GPCM
+	bool "11 wait states"
+
+config OR0_SCY_12
+	depends on BR0_MACHINE_GPCM
+	bool "12 wait states"
+
+config OR0_SCY_13
+	depends on BR0_MACHINE_GPCM
+	bool "13 wait states"
+
+config OR0_SCY_14
+	depends on BR0_MACHINE_GPCM
+	bool "14 wait states"
+
+config OR0_SCY_15
+	depends on BR0_MACHINE_GPCM
+	bool "15 wait states"
+
+endchoice
+
+endif # BR0_MACHINE_GPCM || BR0_MACHINE_FCM
+
+if BR0_MACHINE_GPCM
+
+choice
+	prompt "Chip select negotiation time"
+
+config OR0_CSNT_NORMAL
+	bool "Normal"
+
+config OR0_CSNT_EARLIER
+	bool "Earlier"
+
+endchoice
+
+choice
+	prompt "Address to chip-select setup"
+
+config OR0_ACS_SAME_TIME
+	bool "At the same time"
+
+config OR0_ACS_HALF_CYCLE_EARLIER
+	bool "Half of a bus clock cycle earlier"
+
+config OR0_ACS_QUARTER_CYCLE_EARLIER
+	bool "Half/Quarter of a bus clock cycle earlier"
+
+endchoice
+
+choice
+	prompt "Extra address to check-select setup"
+
+config OR0_XACS_NORMAL
+	bool "Normal"
+
+config OR0_XACS_EXTENDED
+	bool "Extended"
+
+endchoice
+
+choice
+	prompt "External address termination"
+
+config OR0_SETA_INTERNAL
+	bool "Access is terminated internally"
+
+config OR0_SETA_EXTERNAL
+	bool "Access is terminated externally"
+
+endchoice
+
+endif # BR0_MACHINE_GPCM
+
+if BR0_MACHINE_FCM
+
+choice
+	prompt "NAND Flash EEPROM page size"
+
+config OR0_PGS_SMALL
+	bool "Small page device"
+
+config OR0_PGS_LARGE
+	bool "Large page device"
+
+endchoice
+
+choice
+	prompt "Chip select to command time"
+
+config OR0_CSCT_1_CYCLE
+	depends on OR0_TRLX_NORMAL
+	bool "1 cycle"
+
+config OR0_CSCT_2_CYCLE
+	depends on OR0_TRLX_RELAXED
+	bool "2 cycles"
+
+config OR0_CSCT_4_CYCLE
+	depends on OR0_TRLX_NORMAL
+	bool "4 cycles"
+
+config OR0_CSCT_8_CYCLE
+	depends on OR0_TRLX_RELAXED
+	bool "8 cycles"
+
+endchoice
+
+choice
+	prompt "Command setup time"
+
+config OR0_CST_COINCIDENT
+	depends on OR0_TRLX_NORMAL
+	bool "Coincident with any command"
+
+config OR0_CST_QUARTER_CLOCK
+	depends on OR0_TRLX_NORMAL
+	bool "0.25 clocks after"
+
+config OR0_CST_HALF_CLOCK
+	depends on OR0_TRLX_RELAXED
+	bool "0.5 clocks after"
+
+config OR0_CST_ONE_CLOCK
+	depends on OR0_TRLX_RELAXED
+	bool "1 clock after"
+
+endchoice
+
+choice
+	prompt "Command hold time"
+
+config OR0_CHT_HALF_CLOCK
+	depends on OR0_TRLX_NORMAL
+	bool "0.5 clocks before"
+
+config OR0_CHT_ONE_CLOCK
+	depends on OR0_TRLX_NORMAL
+	bool "1 clock before"
+
+config OR0_CHT_ONE_HALF_CLOCK
+	depends on OR0_TRLX_RELAXED
+	bool "1.5 clocks before"
+
+config OR0_CHT_TWO_CLOCK
+	depends on OR0_TRLX_RELAXED
+	bool "2 clocks before"
+
+endchoice
+
+choice
+	prompt "Reset setup time"
+
+config OR0_RST_THREE_QUARTER_CLOCK
+	depends on OR0_TRLX_NORMAL
+	bool "0.75 clocks prior"
+
+config OR0_RST_ONE_HALF_CLOCK
+	depends on OR0_TRLX_RELAXED
+	bool "0.5 clocks prior"
+
+config OR0_RST_ONE_CLOCK
+	bool "1 clock prior"
+
+endchoice
+
+endif # BR0_MACHINE_FCM
+
+if BR0_MACHINE_UPM
+
+choice
+	prompt "Burst inhibit"
+
+config OR0_BI_BURSTSUPPORT
+	bool "Support burst access"
+
+config OR0_BI_BURSTINHIBIT
+	bool "Inhibit burst access"
+
+endchoice
+
+endif # BR0_MACHINE_UPM
+
+if BR0_MACHINE_SDRAM
+
+choice
+	prompt "Number of column address lines"
+
+config OR0_COLS_7
+	bool "7"
+
+config OR0_COLS_8
+	bool "8"
+
+config OR0_COLS_9
+	bool "9"
+
+config OR0_COLS_10
+	bool "10"
+
+config OR0_COLS_11
+	bool "11"
+
+config OR0_COLS_12
+	bool "12"
+
+config OR0_COLS_13
+	bool "13"
+
+config OR0_COLS_14
+	bool "14"
+
+endchoice
+
+choice
+	prompt "Number of rows address lines"
+
+config OR0_ROWS_9
+	bool "9"
+
+config OR0_ROWS_10
+	bool "10"
+
+config OR0_ROWS_11
+	bool "11"
+
+config OR0_ROWS_12
+	bool "12"
+
+config OR0_ROWS_13
+	bool "13"
+
+config OR0_ROWS_14
+	bool "14"
+
+config OR0_ROWS_15
+	bool "15"
+
+endchoice
+
+choice
+	prompt "Page mode select"
+
+config OR0_PMSEL_BTB
+	bool "Back-to-back"
+
+config OR0_PMSEL_KEPT_OPEN
+	bool "Page kept open until page miss or refresh"
+
+endchoice
+
+endif # BR0_MACHINE_SDRAM
+
+choice
+	prompt "Relaxed timing"
+
+config OR0_TRLX_NORMAL
+	bool "Normal"
+
+config OR0_TRLX_RELAXED
+	bool "Relaxed"
+
+endchoice
+
+choice
+	prompt "Extended hold time"
+
+config OR0_EHTR_NORMAL
+	depends on OR0_TRLX_NORMAL
+	bool "Normal"
+
+config OR0_EHTR_1_CYCLE
+	depends on OR0_TRLX_NORMAL
+	bool "1 idle clock cycle inserted"
+
+config OR0_EHTR_4_CYCLE
+	depends on OR0_TRLX_RELAXED
+	bool "4 idle clock cycles inserted"
+
+config OR0_EHTR_8_CYCLE
+	depends on OR0_TRLX_RELAXED
+	bool "8 idle clock cycles inserted"
+
+endchoice
+
+if !ARCH_MPC8308
+
+choice
+	prompt "External address latch delay"
+
+config OR0_EAD_NONE
+	bool "None"
+
+config OR0_EAD_EXTRA
+	bool "Extra"
+
+endchoice
+
+endif # !ARCH_MPC8308
+
+endif # ELBC_BR0_OR0
+
+config BR0_PORTSIZE
+	hex
+	default 0x800 if BR0_PORTSIZE_8BIT
+	default 0x1000 if BR0_PORTSIZE_16BIT
+	default 0x1800 if BR0_PORTSIZE_32BIT
+
+config BR0_ERRORCHECKING
+	hex
+	default 0x0 if !BR0_MACHINE_FCM
+	default 0x0 if BR0_ERRORCHECKING_DISABLED
+	default 0x200 if BR0_ERRORCHECKING_ECC_CHECKING
+	default 0x400 if BR0_ERRORCHECKING_BOTH
+
+config BR0_WRITE_PROTECT_BIT
+	hex
+	default 0x0 if !BR0_WRITE_PROTECT
+	default 0x100 if BR0_WRITE_PROTECT
+
+config BR0_MACHINE
+	hex
+	default 0x0 if BR0_MACHINE_GPCM
+	default 0x20 if BR0_MACHINE_FCM
+	default 0x60 if BR0_MACHINE_SDRAM
+	default 0x80 if BR0_MACHINE_UPMA
+	default 0xa0 if BR0_MACHINE_UPMB
+	default 0xc0 if BR0_MACHINE_UPMC
+
+config BR0_ATOMIC
+	hex
+	default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
+	default 0x0 if BR0_ATOMIC_NONE
+	default 0x4 if BR0_ATOMIC_RAWA
+	default 0x8 if BR0_ATOMIC_WARA
+
+config BR0_VALID_BIT
+	hex
+	default 0x0 if !ELBC_BR0_OR0
+	default 0x1 if ELBC_BR0_OR0
+
+config OR0_AM
+	hex
+	default 0xffff8000 if OR0_AM_32_KBYTES && !BR0_MACHINE_SDRAM
+	default 0xffff0000 if OR0_AM_64_KBYTES
+	default 0xfffe0000 if OR0_AM_128_KBYTES
+	default 0xfffc0000 if OR0_AM_256_KBYTES
+	default 0xfff80000 if OR0_AM_512_KBYTES
+	default 0xfff00000 if OR0_AM_1_MBYTES
+	default 0xffe00000 if OR0_AM_2_MBYTES
+	default 0xffc00000 if OR0_AM_4_MBYTES
+	default 0xff800000 if OR0_AM_8_MBYTES
+	default 0xff000000 if OR0_AM_16_MBYTES
+	default 0xfe000000 if OR0_AM_32_MBYTES
+	default 0xfc000000 if OR0_AM_64_MBYTES
+	default 0xf8000000 if OR0_AM_128_MBYTES
+	default 0xf0000000 if OR0_AM_256_MBYTES
+	default 0xe0000000 if OR0_AM_512_MBYTES
+	default 0xc0000000 if OR0_AM_1_GBYTES
+	default 0x80000000 if OR0_AM_2_GBYTES
+	default 0x00000000 if OR0_AM_4_GBYTES
+
+config OR0_XAM
+	hex
+	default 0x0 if !OR0_XAM_SET
+	default 0x6000 if OR0_XAM_SET
+
+config OR0_BCTLD
+	hex
+	default 0x0 if OR0_BCTLD_ASSERTED
+	default 0x1000 if OR0_BCTLD_NOT_ASSERTED
+
+config OR0_BI
+	hex
+	default 0x0 if !BR0_MACHINE_UPM
+	default 0x0 if OR0_BI_BURSTSUPPORT
+	default 0x100 if OR0_BI_BURSTINHIBIT
+
+config OR0_COLS
+	hex
+	default 0x0 if !BR0_MACHINE_SDRAM
+	default 0x0 if OR0_COLS_7
+	default 0x400 if OR0_COLS_8
+	default 0x800 if OR0_COLS_9
+	default 0xc00 if OR0_COLS_10
+	default 0x1000 if OR0_COLS_11
+	default 0x1400 if OR0_COLS_12
+	default 0x1800 if OR0_COLS_13
+	default 0x1c00 if OR0_COLS_14
+
+config OR0_ROWS
+	hex
+	default 0x0 if !BR0_MACHINE_SDRAM
+	default 0x0 if OR0_ROWS_9
+	default 0x40 if OR0_ROWS_10
+	default 0x80 if OR0_ROWS_11
+	default 0xc0 if OR0_ROWS_12
+	default 0x100 if OR0_ROWS_13
+	default 0x140 if OR0_ROWS_14
+	default 0x180 if OR0_ROWS_15
+
+config OR0_PMSEL
+	hex
+	default 0x0 if !BR0_MACHINE_SDRAM
+	default 0x0 if OR0_PMSEL_BTB
+	default 0x20 if OR0_PMSEL_KEPT_OPEN
+
+config OR0_SCY
+	hex
+	default 0x0 if !BR0_MACHINE_GPCM && !BR0_MACHINE_FCM
+	default 0x0 if OR0_SCY_0
+	default 0x10 if OR0_SCY_1
+	default 0x20 if OR0_SCY_2
+	default 0x30 if OR0_SCY_3
+	default 0x40 if OR0_SCY_4
+	default 0x50 if OR0_SCY_5
+	default 0x60 if OR0_SCY_6
+	default 0x70 if OR0_SCY_7
+	default 0x80 if OR0_SCY_8
+	default 0x90 if OR0_SCY_9
+	default 0xa0 if OR0_SCY_10
+	default 0xb0 if OR0_SCY_11
+	default 0xc0 if OR0_SCY_12
+	default 0xd0 if OR0_SCY_13
+	default 0xe0 if OR0_SCY_14
+	default 0xf0 if OR0_SCY_15
+
+config OR0_PGS
+	hex
+	default 0x0 if !BR0_MACHINE_FCM
+	default 0x0 if OR0_PGS_SMALL
+	default 0x400 if OR0_PGS_LARGE
+
+config OR0_CSCT
+	hex
+	default 0x0 if !BR0_MACHINE_FCM
+	default 0x0 if OR0_CSCT_1_CYCLE
+	default 0x0 if OR0_CSCT_2_CYCLE
+	default 0x200 if OR0_CSCT_4_CYCLE
+	default 0x200 if OR0_CSCT_8_CYCLE
+
+config OR0_CST
+	hex
+	default 0x0 if !BR0_MACHINE_FCM
+	default 0x0 if OR0_CST_COINCIDENT
+	default 0x100 if OR0_CST_QUARTER_CLOCK
+	default 0x0 if OR0_CST_HALF_CLOCK
+	default 0x100 if OR0_CST_ONE_CLOCK
+
+config OR0_CHT
+	hex
+	default 0x0 if !BR0_MACHINE_FCM
+	default 0x0 if OR0_CHT_HALF_CLOCK
+	default 0x80 if OR0_CHT_ONE_CLOCK
+	default 0x0 if OR0_CHT_ONE_HALF_CLOCK
+	default 0x80 if OR0_CHT_TWO_CLOCK
+
+config OR0_RST
+	hex
+	default 0x0 if !BR0_MACHINE_FCM
+	default 0x0 if OR0_RST_THREE_QUARTER_CLOCK
+	default 0x8 if OR0_RST_ONE_CLOCK
+	default 0x0 if OR0_RST_ONE_HALF_CLOCK
+
+config OR0_CSNT
+	hex
+	default 0x0 if !BR0_MACHINE_GPCM
+	default 0x0 if OR0_CSNT_NORMAL
+	default 0x800 if OR0_CSNT_EARLIER
+
+config OR0_ACS
+	hex
+	default 0x0 if !BR0_MACHINE_GPCM
+	default 0x0 if OR0_ACS_SAME_TIME
+	default 0x400 if OR0_ACS_QUARTER_CYCLE_EARLIER
+	default 0x600 if OR0_ACS_HALF_CYCLE_EARLIER
+
+config OR0_XACS
+	hex
+	default 0x0 if !BR0_MACHINE_GPCM
+	default 0x0 if OR0_XACS_NORMAL
+	default 0x100 if OR0_XACS_EXTENDED
+
+config OR0_SETA
+	hex
+	default 0x0 if !BR0_MACHINE_GPCM
+	default 0x0 if OR0_SETA_INTERNAL
+	default 0x8 if OR0_SETA_EXTERNAL
+
+config OR0_TRLX
+	hex
+	default 0x0 if OR0_TRLX_NORMAL
+	default 0x4 if OR0_TRLX_RELAXED
+
+config OR0_EHTR
+	hex
+	default 0x0 if OR0_EHTR_NORMAL
+	default 0x2 if OR0_EHTR_1_CYCLE
+	default 0x0 if OR0_EHTR_4_CYCLE
+	default 0x2 if OR0_EHTR_8_CYCLE
+
+config OR0_EAD
+	hex
+	default 0x0 if ARCH_MPC8308
+	default 0x0 if OR0_EAD_NONE
+	default 0x1 if OR0_EAD_EXTRA
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 b/roms/u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1
new file mode 100644
index 000000000..08dcc7dd2
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1
@@ -0,0 +1,733 @@
+menuconfig ELBC_BR1_OR1
+	bool "ELBC BR1/OR1"
+
+if ELBC_BR1_OR1
+
+config BR1_OR1_NAME
+	string "Identifier"
+
+config BR1_OR1_BASE
+	hex "Port base"
+
+choice
+	prompt "Port size"
+
+config BR1_PORTSIZE_8BIT
+	bool "8-bit"
+
+config BR1_PORTSIZE_16BIT
+	depends on !BR1_MACHINE_FCM
+	bool "16-bit"
+
+
+config BR1_PORTSIZE_32BIT
+	depends on !BR1_MACHINE_FCM
+	depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+	bool "32-bit"
+
+endchoice
+
+if BR1_MACHINE_FCM
+
+choice
+	prompt "Data Error Checking"
+
+config BR1_ERRORCHECKING_DISABLED
+	bool "Disabled"
+
+config BR1_ERRORCHECKING_ECC_CHECKING
+	bool "ECC checking / No ECC generation"
+
+config BR1_ERRORCHECKING_BOTH
+	bool "ECC checking and generation"
+
+endchoice
+
+endif
+
+config BR1_WRITE_PROTECT
+	bool "Write-protect"
+
+config BR1_MACHINE_UPM
+	bool
+
+choice
+	prompt "Machine select"
+
+config BR1_MACHINE_GPCM
+	bool "GPCM"
+
+config BR1_MACHINE_FCM
+	depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+	bool "FCM"
+
+config BR1_MACHINE_SDRAM
+	depends on ARCH_MPC8349 || ARCH_MPC8360
+	bool "SDRAM"
+
+config BR1_MACHINE_UPMA
+	select BR1_MACHINE_UPM
+	bool "UPM (A)"
+
+config BR1_MACHINE_UPMB
+	select BR1_MACHINE_UPM
+	bool "UPM (B)"
+
+config BR1_MACHINE_UPMC
+	select BR1_MACHINE_UPM
+	bool "UPM (C)"
+
+endchoice
+
+if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
+
+choice
+	prompt "Atomic operations"
+
+config BR1_ATOMIC_NONE
+	bool "No atomic operations"
+
+config BR1_ATOMIC_RAWA
+	bool "Read-after-write-atomic"
+
+config BR1_ATOMIC_WARA
+	bool "Write-after-read-atomic"
+
+endchoice
+
+endif
+
+if BR1_MACHINE_GPCM || BR1_MACHINE_FCM || BR1_MACHINE_UPM || BR1_MACHINE_SDRAM
+
+choice
+	prompt "Address mask"
+
+config OR1_AM_32_KBYTES
+	depends on !BR1_MACHINE_SDRAM
+	bool "32 kb"
+
+config OR1_AM_64_KBYTES
+	bool "64 kb"
+
+config OR1_AM_128_KBYTES
+	bool "128 kb"
+
+config OR1_AM_256_KBYTES
+	bool "256 kb"
+
+config OR1_AM_512_KBYTES
+	bool "512 kb"
+
+config OR1_AM_1_MBYTES
+	bool "1 mb"
+
+config OR1_AM_2_MBYTES
+	bool "2 mb"
+
+config OR1_AM_4_MBYTES
+	bool "4 mb"
+
+config OR1_AM_8_MBYTES
+	bool "8 mb"
+
+config OR1_AM_16_MBYTES
+	bool "16 mb"
+
+config OR1_AM_32_MBYTES
+	bool "32 mb"
+
+config OR1_AM_64_MBYTES
+	bool "64 mb"
+
+# XXX: Some boards define 128MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR1_AM_128_MBYTES
+	bool "128 mb"
+
+# XXX: Some boards define 256MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR1_AM_256_MBYTES
+	bool "256 mb"
+
+config OR1_AM_512_MBYTES
+	depends on BR1_MACHINE_FCM
+	bool "512 mb"
+
+# XXX: Some boards define 1GB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR1_AM_1_GBYTES
+	bool "1 gb"
+
+config OR1_AM_2_GBYTES
+	depends on BR1_MACHINE_FCM
+	bool "2 gb"
+
+config OR1_AM_4_GBYTES
+	depends on BR1_MACHINE_FCM
+	bool "4 gb"
+
+endchoice
+
+config OR1_XAM_SET
+	bool "Set unused bytes after address mask"
+choice
+	prompt "Buffer control disable"
+
+config OR1_BCTLD_ASSERTED
+	bool "Asserted"
+
+config OR1_BCTLD_NOT_ASSERTED
+	bool "Not asserted"
+
+endchoice
+
+endif
+
+if BR1_MACHINE_GPCM || BR1_MACHINE_FCM
+
+choice
+	prompt "Cycle length in bus clocks"
+
+config OR1_SCY_0
+	bool "No wait states"
+
+config OR1_SCY_1
+	bool "1 wait state"
+
+config OR1_SCY_2
+	bool "2 wait states"
+
+config OR1_SCY_3
+	bool "3 wait states"
+
+config OR1_SCY_4
+	bool "4 wait states"
+
+config OR1_SCY_5
+	bool "5 wait states"
+
+config OR1_SCY_6
+	bool "6 wait states"
+
+config OR1_SCY_7
+	bool "7 wait states"
+
+config OR1_SCY_8
+	depends on BR1_MACHINE_GPCM
+	bool "8 wait states"
+
+config OR1_SCY_9
+	depends on BR1_MACHINE_GPCM
+	bool "9 wait states"
+
+config OR1_SCY_10
+	depends on BR1_MACHINE_GPCM
+	bool "10 wait states"
+
+config OR1_SCY_11
+	depends on BR1_MACHINE_GPCM
+	bool "11 wait states"
+
+config OR1_SCY_12
+	depends on BR1_MACHINE_GPCM
+	bool "12 wait states"
+
+config OR1_SCY_13
+	depends on BR1_MACHINE_GPCM
+	bool "13 wait states"
+
+config OR1_SCY_14
+	depends on BR1_MACHINE_GPCM
+	bool "14 wait states"
+
+config OR1_SCY_15
+	depends on BR1_MACHINE_GPCM
+	bool "15 wait states"
+
+endchoice
+
+endif # BR1_MACHINE_GPCM || BR1_MACHINE_FCM
+
+if BR1_MACHINE_GPCM
+
+choice
+	prompt "Chip select negotiation time"
+
+config OR1_CSNT_NORMAL
+	bool "Normal"
+
+config OR1_CSNT_EARLIER
+	bool "Earlier"
+
+endchoice
+
+choice
+	prompt "Address to chip-select setup"
+
+config OR1_ACS_SAME_TIME
+	bool "At the same time"
+
+config OR1_ACS_HALF_CYCLE_EARLIER
+	bool "Half of a bus clock cycle earlier"
+
+config OR1_ACS_QUARTER_CYCLE_EARLIER
+	bool "Half/Quarter of a bus clock cycle earlier"
+
+endchoice
+
+choice
+	prompt "Extra address to check-select setup"
+
+config OR1_XACS_NORMAL
+	bool "Normal"
+
+config OR1_XACS_EXTENDED
+	bool "Extended"
+
+endchoice
+
+choice
+	prompt "External address termination"
+
+config OR1_SETA_INTERNAL
+	bool "Access is terminated internally"
+
+config OR1_SETA_EXTERNAL
+	bool "Access is terminated externally"
+
+endchoice
+
+endif # BR1_MACHINE_GPCM
+
+if BR1_MACHINE_FCM
+
+choice
+	prompt "NAND Flash EEPROM page size"
+
+config OR1_PGS_SMALL
+	bool "Small page device"
+
+config OR1_PGS_LARGE
+	bool "Large page device"
+
+endchoice
+
+choice
+	prompt "Chip select to command time"
+
+config OR1_CSCT_1_CYCLE
+	depends on OR1_TRLX_NORMAL
+	bool "1 cycle"
+
+config OR1_CSCT_2_CYCLE
+	depends on OR1_TRLX_RELAXED
+	bool "2 cycles"
+
+config OR1_CSCT_4_CYCLE
+	depends on OR1_TRLX_NORMAL
+	bool "4 cycles"
+
+config OR1_CSCT_8_CYCLE
+	depends on OR1_TRLX_RELAXED
+	bool "8 cycles"
+
+endchoice
+
+choice
+	prompt "Command setup time"
+
+config OR1_CST_COINCIDENT
+	depends on OR1_TRLX_NORMAL
+	bool "Coincident with any command"
+
+config OR1_CST_QUARTER_CLOCK
+	depends on OR1_TRLX_NORMAL
+	bool "0.25 clocks after"
+
+config OR1_CST_HALF_CLOCK
+	depends on OR1_TRLX_RELAXED
+	bool "0.5 clocks after"
+
+config OR1_CST_ONE_CLOCK
+	depends on OR1_TRLX_RELAXED
+	bool "1 clock after"
+
+endchoice
+
+choice
+	prompt "Command hold time"
+
+config OR1_CHT_HALF_CLOCK
+	depends on OR1_TRLX_NORMAL
+	bool "0.5 clocks before"
+
+config OR1_CHT_ONE_CLOCK
+	depends on OR1_TRLX_NORMAL
+	bool "1 clock before"
+
+config OR1_CHT_ONE_HALF_CLOCK
+	depends on OR1_TRLX_RELAXED
+	bool "1.5 clocks before"
+
+config OR1_CHT_TWO_CLOCK
+	depends on OR1_TRLX_RELAXED
+	bool "2 clocks before"
+
+endchoice
+
+choice
+	prompt "Reset setup time"
+
+config OR1_RST_THREE_QUARTER_CLOCK
+	depends on OR1_TRLX_NORMAL
+	bool "0.75 clocks prior"
+
+config OR1_RST_ONE_HALF_CLOCK
+	depends on OR1_TRLX_RELAXED
+	bool "0.5 clocks prior"
+
+config OR1_RST_ONE_CLOCK
+	bool "1 clock prior"
+
+endchoice
+
+endif # BR1_MACHINE_FCM
+
+if BR1_MACHINE_UPM
+
+choice
+	prompt "Burst inhibit"
+
+config OR1_BI_BURSTSUPPORT
+	bool "Support burst access"
+
+config OR1_BI_BURSTINHIBIT
+	bool "Inhibit burst access"
+
+endchoice
+
+endif # BR1_MACHINE_UPM
+
+if BR1_MACHINE_SDRAM
+
+choice
+	prompt "Number of column address lines"
+
+config OR1_COLS_7
+	bool "7"
+
+config OR1_COLS_8
+	bool "8"
+
+config OR1_COLS_9
+	bool "9"
+
+config OR1_COLS_10
+	bool "10"
+
+config OR1_COLS_11
+	bool "11"
+
+config OR1_COLS_12
+	bool "12"
+
+config OR1_COLS_13
+	bool "13"
+
+config OR1_COLS_14
+	bool "14"
+
+endchoice
+
+choice
+	prompt "Number of rows address lines"
+
+config OR1_ROWS_9
+	bool "9"
+
+config OR1_ROWS_10
+	bool "10"
+
+config OR1_ROWS_11
+	bool "11"
+
+config OR1_ROWS_12
+	bool "12"
+
+config OR1_ROWS_13
+	bool "13"
+
+config OR1_ROWS_14
+	bool "14"
+
+config OR1_ROWS_15
+	bool "15"
+
+endchoice
+
+choice
+	prompt "Page mode select"
+
+config OR1_PMSEL_BTB
+	bool "Back-to-back"
+
+config OR1_PMSEL_KEPT_OPEN
+	bool "Page kept open until page miss or refresh"
+
+endchoice
+
+endif # BR1_MACHINE_SDRAM
+
+choice
+	prompt "Relaxed timing"
+
+config OR1_TRLX_NORMAL
+	bool "Normal"
+
+config OR1_TRLX_RELAXED
+	bool "Relaxed"
+
+endchoice
+
+choice
+	prompt "Extended hold time"
+
+config OR1_EHTR_NORMAL
+	depends on OR1_TRLX_NORMAL
+	bool "Normal"
+
+config OR1_EHTR_1_CYCLE
+	depends on OR1_TRLX_NORMAL
+	bool "1 idle clock cycle inserted"
+
+config OR1_EHTR_4_CYCLE
+	depends on OR1_TRLX_RELAXED
+	bool "4 idle clock cycles inserted"
+
+config OR1_EHTR_8_CYCLE
+	depends on OR1_TRLX_RELAXED
+	bool "8 idle clock cycles inserted"
+
+endchoice
+
+if !ARCH_MPC8308
+
+choice
+	prompt "External address latch delay"
+
+config OR1_EAD_NONE
+	bool "None"
+
+config OR1_EAD_EXTRA
+	bool "Extra"
+
+endchoice
+
+endif # !ARCH_MPC8308
+
+endif # ELBC_BR1_OR1
+
+config BR1_PORTSIZE
+	hex
+	default 0x800 if BR1_PORTSIZE_8BIT
+	default 0x1000 if BR1_PORTSIZE_16BIT
+	default 0x1800 if BR1_PORTSIZE_32BIT
+
+config BR1_ERRORCHECKING
+	hex
+	default 0x0 if !BR1_MACHINE_FCM
+	default 0x0 if BR1_ERRORCHECKING_DISABLED
+	default 0x200 if BR1_ERRORCHECKING_ECC_CHECKING
+	default 0x400 if BR1_ERRORCHECKING_BOTH
+
+config BR1_WRITE_PROTECT_BIT
+	hex
+	default 0x0 if !BR1_WRITE_PROTECT
+	default 0x100 if BR1_WRITE_PROTECT
+
+config BR1_MACHINE
+	hex
+	default 0x0 if BR1_MACHINE_GPCM
+	default 0x20 if BR1_MACHINE_FCM
+	default 0x60 if BR1_MACHINE_SDRAM
+	default 0x80 if BR1_MACHINE_UPMA
+	default 0xa0 if BR1_MACHINE_UPMB
+	default 0xc0 if BR1_MACHINE_UPMC
+
+config BR1_ATOMIC
+	hex
+	default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
+	default 0x0 if BR1_ATOMIC_NONE
+	default 0x4 if BR1_ATOMIC_RAWA
+	default 0x8 if BR1_ATOMIC_WARA
+
+config BR1_VALID_BIT
+	hex
+	default 0x0 if !ELBC_BR1_OR1
+	default 0x1 if ELBC_BR1_OR1
+
+config OR1_AM
+	hex
+	default 0xffff8000 if OR1_AM_32_KBYTES && !BR1_MACHINE_SDRAM
+	default 0xffff0000 if OR1_AM_64_KBYTES
+	default 0xfffe0000 if OR1_AM_128_KBYTES
+	default 0xfffc0000 if OR1_AM_256_KBYTES
+	default 0xfff80000 if OR1_AM_512_KBYTES
+	default 0xfff00000 if OR1_AM_1_MBYTES
+	default 0xffe00000 if OR1_AM_2_MBYTES
+	default 0xffc00000 if OR1_AM_4_MBYTES
+	default 0xff800000 if OR1_AM_8_MBYTES
+	default 0xff000000 if OR1_AM_16_MBYTES
+	default 0xfe000000 if OR1_AM_32_MBYTES
+	default 0xfc000000 if OR1_AM_64_MBYTES
+	default 0xf8000000 if OR1_AM_128_MBYTES
+	default 0xf0000000 if OR1_AM_256_MBYTES
+	default 0xe0000000 if OR1_AM_512_MBYTES
+	default 0xc0000000 if OR1_AM_1_GBYTES
+	default 0x80000000 if OR1_AM_2_GBYTES
+	default 0x00000000 if OR1_AM_4_GBYTES
+
+config OR1_XAM
+	hex
+	default 0x0 if !OR1_XAM_SET
+	default 0x6000 if OR1_XAM_SET
+
+config OR1_BCTLD
+	hex
+	default 0x0 if OR1_BCTLD_ASSERTED
+	default 0x1000 if OR1_BCTLD_NOT_ASSERTED
+
+config OR1_BI
+	hex
+	default 0x0 if !BR1_MACHINE_UPM
+	default 0x0 if OR1_BI_BURSTSUPPORT
+	default 0x100 if OR1_BI_BURSTINHIBIT
+
+config OR1_COLS
+	hex
+	default 0x0 if !BR1_MACHINE_SDRAM
+	default 0x0 if OR1_COLS_7
+	default 0x400 if OR1_COLS_8
+	default 0x800 if OR1_COLS_9
+	default 0xc00 if OR1_COLS_10
+	default 0x1000 if OR1_COLS_11
+	default 0x1400 if OR1_COLS_12
+	default 0x1800 if OR1_COLS_13
+	default 0x1c00 if OR1_COLS_14
+
+config OR1_ROWS
+	hex
+	default 0x0 if !BR1_MACHINE_SDRAM
+	default 0x0 if OR1_ROWS_9
+	default 0x40 if OR1_ROWS_10
+	default 0x80 if OR1_ROWS_11
+	default 0xc0 if OR1_ROWS_12
+	default 0x100 if OR1_ROWS_13
+	default 0x140 if OR1_ROWS_14
+	default 0x180 if OR1_ROWS_15
+
+config OR1_PMSEL
+	hex
+	default 0x0 if !BR1_MACHINE_SDRAM
+	default 0x0 if OR1_PMSEL_BTB
+	default 0x20 if OR1_PMSEL_KEPT_OPEN
+
+config OR1_SCY
+	hex
+	default 0x0 if !BR1_MACHINE_GPCM && !BR1_MACHINE_FCM
+	default 0x0 if OR1_SCY_0
+	default 0x10 if OR1_SCY_1
+	default 0x20 if OR1_SCY_2
+	default 0x30 if OR1_SCY_3
+	default 0x40 if OR1_SCY_4
+	default 0x50 if OR1_SCY_5
+	default 0x60 if OR1_SCY_6
+	default 0x70 if OR1_SCY_7
+	default 0x80 if OR1_SCY_8
+	default 0x90 if OR1_SCY_9
+	default 0xa0 if OR1_SCY_10
+	default 0xb0 if OR1_SCY_11
+	default 0xc0 if OR1_SCY_12
+	default 0xd0 if OR1_SCY_13
+	default 0xe0 if OR1_SCY_14
+	default 0xf0 if OR1_SCY_15
+
+config OR1_PGS
+	hex
+	default 0x0 if !BR1_MACHINE_FCM
+	default 0x0 if OR1_PGS_SMALL
+	default 0x400 if OR1_PGS_LARGE
+
+config OR1_CSCT
+	hex
+	default 0x0 if !BR1_MACHINE_FCM
+	default 0x0 if OR1_CSCT_1_CYCLE
+	default 0x0 if OR1_CSCT_2_CYCLE
+	default 0x200 if OR1_CSCT_4_CYCLE
+	default 0x200 if OR1_CSCT_8_CYCLE
+
+config OR1_CST
+	hex
+	default 0x0 if !BR1_MACHINE_FCM
+	default 0x0 if OR1_CST_COINCIDENT
+	default 0x100 if OR1_CST_QUARTER_CLOCK
+	default 0x0 if OR1_CST_HALF_CLOCK
+	default 0x100 if OR1_CST_ONE_CLOCK
+
+config OR1_CHT
+	hex
+	default 0x0 if !BR1_MACHINE_FCM
+	default 0x0 if OR1_CHT_HALF_CLOCK
+	default 0x80 if OR1_CHT_ONE_CLOCK
+	default 0x0 if OR1_CHT_ONE_HALF_CLOCK
+	default 0x80 if OR1_CHT_TWO_CLOCK
+
+config OR1_RST
+	hex
+	default 0x0 if !BR1_MACHINE_FCM
+	default 0x0 if OR1_RST_THREE_QUARTER_CLOCK
+	default 0x8 if OR1_RST_ONE_CLOCK
+	default 0x0 if OR1_RST_ONE_HALF_CLOCK
+
+config OR1_CSNT
+	hex
+	default 0x0 if !BR1_MACHINE_GPCM
+	default 0x0 if OR1_CSNT_NORMAL
+	default 0x800 if OR1_CSNT_EARLIER
+
+config OR1_ACS
+	hex
+	default 0x0 if !BR1_MACHINE_GPCM
+	default 0x0 if OR1_ACS_SAME_TIME
+	default 0x400 if OR1_ACS_QUARTER_CYCLE_EARLIER
+	default 0x600 if OR1_ACS_HALF_CYCLE_EARLIER
+
+config OR1_XACS
+	hex
+	default 0x0 if !BR1_MACHINE_GPCM
+	default 0x0 if OR1_XACS_NORMAL
+	default 0x100 if OR1_XACS_EXTENDED
+
+config OR1_SETA
+	hex
+	default 0x0 if !BR1_MACHINE_GPCM
+	default 0x0 if OR1_SETA_INTERNAL
+	default 0x8 if OR1_SETA_EXTERNAL
+
+config OR1_TRLX
+	hex
+	default 0x0 if OR1_TRLX_NORMAL
+	default 0x4 if OR1_TRLX_RELAXED
+
+config OR1_EHTR
+	hex
+	default 0x0 if OR1_EHTR_NORMAL
+	default 0x2 if OR1_EHTR_1_CYCLE
+	default 0x0 if OR1_EHTR_4_CYCLE
+	default 0x2 if OR1_EHTR_8_CYCLE
+
+config OR1_EAD
+	hex
+	default 0x0 if ARCH_MPC8308
+	default 0x0 if OR1_EAD_NONE
+	default 0x1 if OR1_EAD_EXTRA
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 b/roms/u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2
new file mode 100644
index 000000000..298d87f5e
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2
@@ -0,0 +1,733 @@
+menuconfig ELBC_BR2_OR2
+	bool "ELBC BR2/OR2"
+
+if ELBC_BR2_OR2
+
+config BR2_OR2_NAME
+	string "Identifier"
+
+config BR2_OR2_BASE
+	hex "Port base"
+
+choice
+	prompt "Port size"
+
+config BR2_PORTSIZE_8BIT
+	bool "8-bit"
+
+config BR2_PORTSIZE_16BIT
+	depends on !BR2_MACHINE_FCM
+	bool "16-bit"
+
+
+config BR2_PORTSIZE_32BIT
+	depends on !BR2_MACHINE_FCM
+	depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+	bool "32-bit"
+
+endchoice
+
+if BR2_MACHINE_FCM
+
+choice
+	prompt "Data Error Checking"
+
+config BR2_ERRORCHECKING_DISABLED
+	bool "Disabled"
+
+config BR2_ERRORCHECKING_ECC_CHECKING
+	bool "ECC checking / No ECC generation"
+
+config BR2_ERRORCHECKING_BOTH
+	bool "ECC checking and generation"
+
+endchoice
+
+endif
+
+config BR2_WRITE_PROTECT
+	bool "Write-protect"
+
+config BR2_MACHINE_UPM
+	bool
+
+choice
+	prompt "Machine select"
+
+config BR2_MACHINE_GPCM
+	bool "GPCM"
+
+config BR2_MACHINE_FCM
+	depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+	bool "FCM"
+
+config BR2_MACHINE_SDRAM
+	depends on ARCH_MPC8349 || ARCH_MPC8360
+	bool "SDRAM"
+
+config BR2_MACHINE_UPMA
+	select BR2_MACHINE_UPM
+	bool "UPM (A)"
+
+config BR2_MACHINE_UPMB
+	select BR2_MACHINE_UPM
+	bool "UPM (B)"
+
+config BR2_MACHINE_UPMC
+	select BR2_MACHINE_UPM
+	bool "UPM (C)"
+
+endchoice
+
+if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
+
+choice
+	prompt "Atomic operations"
+
+config BR2_ATOMIC_NONE
+	bool "No atomic operations"
+
+config BR2_ATOMIC_RAWA
+	bool "Read-after-write-atomic"
+
+config BR2_ATOMIC_WARA
+	bool "Write-after-read-atomic"
+
+endchoice
+
+endif
+
+if BR2_MACHINE_GPCM || BR2_MACHINE_FCM || BR2_MACHINE_UPM || BR2_MACHINE_SDRAM
+
+choice
+	prompt "Address mask"
+
+config OR2_AM_32_KBYTES
+	depends on !BR2_MACHINE_SDRAM
+	bool "32 kb"
+
+config OR2_AM_64_KBYTES
+	bool "64 kb"
+
+config OR2_AM_128_KBYTES
+	bool "128 kb"
+
+config OR2_AM_256_KBYTES
+	bool "256 kb"
+
+config OR2_AM_512_KBYTES
+	bool "512 kb"
+
+config OR2_AM_1_MBYTES
+	bool "1 mb"
+
+config OR2_AM_2_MBYTES
+	bool "2 mb"
+
+config OR2_AM_4_MBYTES
+	bool "4 mb"
+
+config OR2_AM_8_MBYTES
+	bool "8 mb"
+
+config OR2_AM_16_MBYTES
+	bool "16 mb"
+
+config OR2_AM_32_MBYTES
+	bool "32 mb"
+
+config OR2_AM_64_MBYTES
+	bool "64 mb"
+
+# XXX: Some boards define 128MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR2_AM_128_MBYTES
+	bool "128 mb"
+
+# XXX: Some boards define 256MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR2_AM_256_MBYTES
+	bool "256 mb"
+
+config OR2_AM_512_MBYTES
+	depends on BR2_MACHINE_FCM
+	bool "512 mb"
+
+# XXX: Some boards define 1GB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR2_AM_1_GBYTES
+	bool "1 gb"
+
+config OR2_AM_2_GBYTES
+	depends on BR2_MACHINE_FCM
+	bool "2 gb"
+
+config OR2_AM_4_GBYTES
+	depends on BR2_MACHINE_FCM
+	bool "4 gb"
+
+endchoice
+
+config OR2_XAM_SET
+	bool "Set unused bytes after address mask"
+choice
+	prompt "Buffer control disable"
+
+config OR2_BCTLD_ASSERTED
+	bool "Asserted"
+
+config OR2_BCTLD_NOT_ASSERTED
+	bool "Not asserted"
+
+endchoice
+
+endif
+
+if BR2_MACHINE_GPCM || BR2_MACHINE_FCM
+
+choice
+	prompt "Cycle length in bus clocks"
+
+config OR2_SCY_0
+	bool "No wait states"
+
+config OR2_SCY_1
+	bool "1 wait state"
+
+config OR2_SCY_2
+	bool "2 wait states"
+
+config OR2_SCY_3
+	bool "3 wait states"
+
+config OR2_SCY_4
+	bool "4 wait states"
+
+config OR2_SCY_5
+	bool "5 wait states"
+
+config OR2_SCY_6
+	bool "6 wait states"
+
+config OR2_SCY_7
+	bool "7 wait states"
+
+config OR2_SCY_8
+	depends on BR2_MACHINE_GPCM
+	bool "8 wait states"
+
+config OR2_SCY_9
+	depends on BR2_MACHINE_GPCM
+	bool "9 wait states"
+
+config OR2_SCY_10
+	depends on BR2_MACHINE_GPCM
+	bool "10 wait states"
+
+config OR2_SCY_11
+	depends on BR2_MACHINE_GPCM
+	bool "11 wait states"
+
+config OR2_SCY_12
+	depends on BR2_MACHINE_GPCM
+	bool "12 wait states"
+
+config OR2_SCY_13
+	depends on BR2_MACHINE_GPCM
+	bool "13 wait states"
+
+config OR2_SCY_14
+	depends on BR2_MACHINE_GPCM
+	bool "14 wait states"
+
+config OR2_SCY_15
+	depends on BR2_MACHINE_GPCM
+	bool "15 wait states"
+
+endchoice
+
+endif # BR2_MACHINE_GPCM || BR2_MACHINE_FCM
+
+if BR2_MACHINE_GPCM
+
+choice
+	prompt "Chip select negotiation time"
+
+config OR2_CSNT_NORMAL
+	bool "Normal"
+
+config OR2_CSNT_EARLIER
+	bool "Earlier"
+
+endchoice
+
+choice
+	prompt "Address to chip-select setup"
+
+config OR2_ACS_SAME_TIME
+	bool "At the same time"
+
+config OR2_ACS_HALF_CYCLE_EARLIER
+	bool "Half of a bus clock cycle earlier"
+
+config OR2_ACS_QUARTER_CYCLE_EARLIER
+	bool "Half/Quarter of a bus clock cycle earlier"
+
+endchoice
+
+choice
+	prompt "Extra address to check-select setup"
+
+config OR2_XACS_NORMAL
+	bool "Normal"
+
+config OR2_XACS_EXTENDED
+	bool "Extended"
+
+endchoice
+
+choice
+	prompt "External address termination"
+
+config OR2_SETA_INTERNAL
+	bool "Access is terminated internally"
+
+config OR2_SETA_EXTERNAL
+	bool "Access is terminated externally"
+
+endchoice
+
+endif # BR2_MACHINE_GPCM
+
+if BR2_MACHINE_FCM
+
+choice
+	prompt "NAND Flash EEPROM page size"
+
+config OR2_PGS_SMALL
+	bool "Small page device"
+
+config OR2_PGS_LARGE
+	bool "Large page device"
+
+endchoice
+
+choice
+	prompt "Chip select to command time"
+
+config OR2_CSCT_1_CYCLE
+	depends on OR2_TRLX_NORMAL
+	bool "1 cycle"
+
+config OR2_CSCT_2_CYCLE
+	depends on OR2_TRLX_RELAXED
+	bool "2 cycles"
+
+config OR2_CSCT_4_CYCLE
+	depends on OR2_TRLX_NORMAL
+	bool "4 cycles"
+
+config OR2_CSCT_8_CYCLE
+	depends on OR2_TRLX_RELAXED
+	bool "8 cycles"
+
+endchoice
+
+choice
+	prompt "Command setup time"
+
+config OR2_CST_COINCIDENT
+	depends on OR2_TRLX_NORMAL
+	bool "Coincident with any command"
+
+config OR2_CST_QUARTER_CLOCK
+	depends on OR2_TRLX_NORMAL
+	bool "0.25 clocks after"
+
+config OR2_CST_HALF_CLOCK
+	depends on OR2_TRLX_RELAXED
+	bool "0.5 clocks after"
+
+config OR2_CST_ONE_CLOCK
+	depends on OR2_TRLX_RELAXED
+	bool "1 clock after"
+
+endchoice
+
+choice
+	prompt "Command hold time"
+
+config OR2_CHT_HALF_CLOCK
+	depends on OR2_TRLX_NORMAL
+	bool "0.5 clocks before"
+
+config OR2_CHT_ONE_CLOCK
+	depends on OR2_TRLX_NORMAL
+	bool "1 clock before"
+
+config OR2_CHT_ONE_HALF_CLOCK
+	depends on OR2_TRLX_RELAXED
+	bool "1.5 clocks before"
+
+config OR2_CHT_TWO_CLOCK
+	depends on OR2_TRLX_RELAXED
+	bool "2 clocks before"
+
+endchoice
+
+choice
+	prompt "Reset setup time"
+
+config OR2_RST_THREE_QUARTER_CLOCK
+	depends on OR2_TRLX_NORMAL
+	bool "0.75 clocks prior"
+
+config OR2_RST_ONE_HALF_CLOCK
+	depends on OR2_TRLX_RELAXED
+	bool "0.5 clocks prior"
+
+config OR2_RST_ONE_CLOCK
+	bool "1 clock prior"
+
+endchoice
+
+endif # BR2_MACHINE_FCM
+
+if BR2_MACHINE_UPM
+
+choice
+	prompt "Burst inhibit"
+
+config OR2_BI_BURSTSUPPORT
+	bool "Support burst access"
+
+config OR2_BI_BURSTINHIBIT
+	bool "Inhibit burst access"
+
+endchoice
+
+endif # BR2_MACHINE_UPM
+
+if BR2_MACHINE_SDRAM
+
+choice
+	prompt "Number of column address lines"
+
+config OR2_COLS_7
+	bool "7"
+
+config OR2_COLS_8
+	bool "8"
+
+config OR2_COLS_9
+	bool "9"
+
+config OR2_COLS_10
+	bool "10"
+
+config OR2_COLS_11
+	bool "11"
+
+config OR2_COLS_12
+	bool "12"
+
+config OR2_COLS_13
+	bool "13"
+
+config OR2_COLS_14
+	bool "14"
+
+endchoice
+
+choice
+	prompt "Number of rows address lines"
+
+config OR2_ROWS_9
+	bool "9"
+
+config OR2_ROWS_10
+	bool "10"
+
+config OR2_ROWS_11
+	bool "11"
+
+config OR2_ROWS_12
+	bool "12"
+
+config OR2_ROWS_13
+	bool "13"
+
+config OR2_ROWS_14
+	bool "14"
+
+config OR2_ROWS_15
+	bool "15"
+
+endchoice
+
+choice
+	prompt "Page mode select"
+
+config OR2_PMSEL_BTB
+	bool "Back-to-back"
+
+config OR2_PMSEL_KEPT_OPEN
+	bool "Page kept open until page miss or refresh"
+
+endchoice
+
+endif # BR2_MACHINE_SDRAM
+
+choice
+	prompt "Relaxed timing"
+
+config OR2_TRLX_NORMAL
+	bool "Normal"
+
+config OR2_TRLX_RELAXED
+	bool "Relaxed"
+
+endchoice
+
+choice
+	prompt "Extended hold time"
+
+config OR2_EHTR_NORMAL
+	depends on OR2_TRLX_NORMAL
+	bool "Normal"
+
+config OR2_EHTR_1_CYCLE
+	depends on OR2_TRLX_NORMAL
+	bool "1 idle clock cycle inserted"
+
+config OR2_EHTR_4_CYCLE
+	depends on OR2_TRLX_RELAXED
+	bool "4 idle clock cycles inserted"
+
+config OR2_EHTR_8_CYCLE
+	depends on OR2_TRLX_RELAXED
+	bool "8 idle clock cycles inserted"
+
+endchoice
+
+if !ARCH_MPC8308
+
+choice
+	prompt "External address latch delay"
+
+config OR2_EAD_NONE
+	bool "None"
+
+config OR2_EAD_EXTRA
+	bool "Extra"
+
+endchoice
+
+endif # !ARCH_MPC8308
+
+endif # ELBC_BR2_OR2
+
+config BR2_PORTSIZE
+	hex
+	default 0x800 if BR2_PORTSIZE_8BIT
+	default 0x1000 if BR2_PORTSIZE_16BIT
+	default 0x1800 if BR2_PORTSIZE_32BIT
+
+config BR2_ERRORCHECKING
+	hex
+	default 0x0 if !BR2_MACHINE_FCM
+	default 0x0 if BR2_ERRORCHECKING_DISABLED
+	default 0x200 if BR2_ERRORCHECKING_ECC_CHECKING
+	default 0x400 if BR2_ERRORCHECKING_BOTH
+
+config BR2_WRITE_PROTECT_BIT
+	hex
+	default 0x0 if !BR2_WRITE_PROTECT
+	default 0x100 if BR2_WRITE_PROTECT
+
+config BR2_MACHINE
+	hex
+	default 0x0 if BR2_MACHINE_GPCM
+	default 0x20 if BR2_MACHINE_FCM
+	default 0x60 if BR2_MACHINE_SDRAM
+	default 0x80 if BR2_MACHINE_UPMA
+	default 0xa0 if BR2_MACHINE_UPMB
+	default 0xc0 if BR2_MACHINE_UPMC
+
+config BR2_ATOMIC
+	hex
+	default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
+	default 0x0 if BR2_ATOMIC_NONE
+	default 0x4 if BR2_ATOMIC_RAWA
+	default 0x8 if BR2_ATOMIC_WARA
+
+config BR2_VALID_BIT
+	hex
+	default 0x0 if !ELBC_BR2_OR2
+	default 0x1 if ELBC_BR2_OR2
+
+config OR2_AM
+	hex
+	default 0xffff8000 if OR2_AM_32_KBYTES && !BR2_MACHINE_SDRAM
+	default 0xffff0000 if OR2_AM_64_KBYTES
+	default 0xfffe0000 if OR2_AM_128_KBYTES
+	default 0xfffc0000 if OR2_AM_256_KBYTES
+	default 0xfff80000 if OR2_AM_512_KBYTES
+	default 0xfff00000 if OR2_AM_1_MBYTES
+	default 0xffe00000 if OR2_AM_2_MBYTES
+	default 0xffc00000 if OR2_AM_4_MBYTES
+	default 0xff800000 if OR2_AM_8_MBYTES
+	default 0xff000000 if OR2_AM_16_MBYTES
+	default 0xfe000000 if OR2_AM_32_MBYTES
+	default 0xfc000000 if OR2_AM_64_MBYTES
+	default 0xf8000000 if OR2_AM_128_MBYTES
+	default 0xf0000000 if OR2_AM_256_MBYTES
+	default 0xe0000000 if OR2_AM_512_MBYTES
+	default 0xc0000000 if OR2_AM_1_GBYTES
+	default 0x80000000 if OR2_AM_2_GBYTES
+	default 0x00000000 if OR2_AM_4_GBYTES
+
+config OR2_XAM
+	hex
+	default 0x0 if !OR2_XAM_SET
+	default 0x6000 if OR2_XAM_SET
+
+config OR2_BCTLD
+	hex
+	default 0x0 if OR2_BCTLD_ASSERTED
+	default 0x1000 if OR2_BCTLD_NOT_ASSERTED
+
+config OR2_BI
+	hex
+	default 0x0 if !BR2_MACHINE_UPM
+	default 0x0 if OR2_BI_BURSTSUPPORT
+	default 0x100 if OR2_BI_BURSTINHIBIT
+
+config OR2_COLS
+	hex
+	default 0x0 if !BR2_MACHINE_SDRAM
+	default 0x0 if OR2_COLS_7
+	default 0x400 if OR2_COLS_8
+	default 0x800 if OR2_COLS_9
+	default 0xc00 if OR2_COLS_10
+	default 0x1000 if OR2_COLS_11
+	default 0x1400 if OR2_COLS_12
+	default 0x1800 if OR2_COLS_13
+	default 0x1c00 if OR2_COLS_14
+
+config OR2_ROWS
+	hex
+	default 0x0 if !BR2_MACHINE_SDRAM
+	default 0x0 if OR2_ROWS_9
+	default 0x40 if OR2_ROWS_10
+	default 0x80 if OR2_ROWS_11
+	default 0xc0 if OR2_ROWS_12
+	default 0x100 if OR2_ROWS_13
+	default 0x140 if OR2_ROWS_14
+	default 0x180 if OR2_ROWS_15
+
+config OR2_PMSEL
+	hex
+	default 0x0 if !BR2_MACHINE_SDRAM
+	default 0x0 if OR2_PMSEL_BTB
+	default 0x20 if OR2_PMSEL_KEPT_OPEN
+
+config OR2_SCY
+	hex
+	default 0x0 if !BR2_MACHINE_GPCM && !BR2_MACHINE_FCM
+	default 0x0 if OR2_SCY_0
+	default 0x10 if OR2_SCY_1
+	default 0x20 if OR2_SCY_2
+	default 0x30 if OR2_SCY_3
+	default 0x40 if OR2_SCY_4
+	default 0x50 if OR2_SCY_5
+	default 0x60 if OR2_SCY_6
+	default 0x70 if OR2_SCY_7
+	default 0x80 if OR2_SCY_8
+	default 0x90 if OR2_SCY_9
+	default 0xa0 if OR2_SCY_10
+	default 0xb0 if OR2_SCY_11
+	default 0xc0 if OR2_SCY_12
+	default 0xd0 if OR2_SCY_13
+	default 0xe0 if OR2_SCY_14
+	default 0xf0 if OR2_SCY_15
+
+config OR2_PGS
+	hex
+	default 0x0 if !BR2_MACHINE_FCM
+	default 0x0 if OR2_PGS_SMALL
+	default 0x400 if OR2_PGS_LARGE
+
+config OR2_CSCT
+	hex
+	default 0x0 if !BR2_MACHINE_FCM
+	default 0x0 if OR2_CSCT_1_CYCLE
+	default 0x0 if OR2_CSCT_2_CYCLE
+	default 0x200 if OR2_CSCT_4_CYCLE
+	default 0x200 if OR2_CSCT_8_CYCLE
+
+config OR2_CST
+	hex
+	default 0x0 if !BR2_MACHINE_FCM
+	default 0x0 if OR2_CST_COINCIDENT
+	default 0x100 if OR2_CST_QUARTER_CLOCK
+	default 0x0 if OR2_CST_HALF_CLOCK
+	default 0x100 if OR2_CST_ONE_CLOCK
+
+config OR2_CHT
+	hex
+	default 0x0 if !BR2_MACHINE_FCM
+	default 0x0 if OR2_CHT_HALF_CLOCK
+	default 0x80 if OR2_CHT_ONE_CLOCK
+	default 0x0 if OR2_CHT_ONE_HALF_CLOCK
+	default 0x80 if OR2_CHT_TWO_CLOCK
+
+config OR2_RST
+	hex
+	default 0x0 if !BR2_MACHINE_FCM
+	default 0x0 if OR2_RST_THREE_QUARTER_CLOCK
+	default 0x8 if OR2_RST_ONE_CLOCK
+	default 0x0 if OR2_RST_ONE_HALF_CLOCK
+
+config OR2_CSNT
+	hex
+	default 0x0 if !BR2_MACHINE_GPCM
+	default 0x0 if OR2_CSNT_NORMAL
+	default 0x800 if OR2_CSNT_EARLIER
+
+config OR2_ACS
+	hex
+	default 0x0 if !BR2_MACHINE_GPCM
+	default 0x0 if OR2_ACS_SAME_TIME
+	default 0x400 if OR2_ACS_QUARTER_CYCLE_EARLIER
+	default 0x600 if OR2_ACS_HALF_CYCLE_EARLIER
+
+config OR2_XACS
+	hex
+	default 0x0 if !BR2_MACHINE_GPCM
+	default 0x0 if OR2_XACS_NORMAL
+	default 0x100 if OR2_XACS_EXTENDED
+
+config OR2_SETA
+	hex
+	default 0x0 if !BR2_MACHINE_GPCM
+	default 0x0 if OR2_SETA_INTERNAL
+	default 0x8 if OR2_SETA_EXTERNAL
+
+config OR2_TRLX
+	hex
+	default 0x0 if OR2_TRLX_NORMAL
+	default 0x4 if OR2_TRLX_RELAXED
+
+config OR2_EHTR
+	hex
+	default 0x0 if OR2_EHTR_NORMAL
+	default 0x2 if OR2_EHTR_1_CYCLE
+	default 0x0 if OR2_EHTR_4_CYCLE
+	default 0x2 if OR2_EHTR_8_CYCLE
+
+config OR2_EAD
+	hex
+	default 0x0 if ARCH_MPC8308
+	default 0x0 if OR2_EAD_NONE
+	default 0x1 if OR2_EAD_EXTRA
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 b/roms/u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3
new file mode 100644
index 000000000..963831bfc
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3
@@ -0,0 +1,733 @@
+menuconfig ELBC_BR3_OR3
+	bool "ELBC BR3/OR3"
+
+if ELBC_BR3_OR3
+
+config BR3_OR3_NAME
+	string "Identifier"
+
+config BR3_OR3_BASE
+	hex "Port base"
+
+choice
+	prompt "Port size"
+
+config BR3_PORTSIZE_8BIT
+	bool "8-bit"
+
+config BR3_PORTSIZE_16BIT
+	depends on !BR3_MACHINE_FCM
+	bool "16-bit"
+
+
+config BR3_PORTSIZE_32BIT
+	depends on !BR3_MACHINE_FCM
+	depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+	bool "32-bit"
+
+endchoice
+
+if BR3_MACHINE_FCM
+
+choice
+	prompt "Data Error Checking"
+
+config BR3_ERRORCHECKING_DISABLED
+	bool "Disabled"
+
+config BR3_ERRORCHECKING_ECC_CHECKING
+	bool "ECC checking / No ECC generation"
+
+config BR3_ERRORCHECKING_BOTH
+	bool "ECC checking and generation"
+
+endchoice
+
+endif
+
+config BR3_WRITE_PROTECT
+	bool "Write-protect"
+
+config BR3_MACHINE_UPM
+	bool
+
+choice
+	prompt "Machine select"
+
+config BR3_MACHINE_GPCM
+	bool "GPCM"
+
+config BR3_MACHINE_FCM
+	depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+	bool "FCM"
+
+config BR3_MACHINE_SDRAM
+	depends on ARCH_MPC8349 || ARCH_MPC8360
+	bool "SDRAM"
+
+config BR3_MACHINE_UPMA
+	select BR3_MACHINE_UPM
+	bool "UPM (A)"
+
+config BR3_MACHINE_UPMB
+	select BR3_MACHINE_UPM
+	bool "UPM (B)"
+
+config BR3_MACHINE_UPMC
+	select BR3_MACHINE_UPM
+	bool "UPM (C)"
+
+endchoice
+
+if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
+
+choice
+	prompt "Atomic operations"
+
+config BR3_ATOMIC_NONE
+	bool "No atomic operations"
+
+config BR3_ATOMIC_RAWA
+	bool "Read-after-write-atomic"
+
+config BR3_ATOMIC_WARA
+	bool "Write-after-read-atomic"
+
+endchoice
+
+endif
+
+if BR3_MACHINE_GPCM || BR3_MACHINE_FCM || BR3_MACHINE_UPM || BR3_MACHINE_SDRAM
+
+choice
+	prompt "Address mask"
+
+config OR3_AM_32_KBYTES
+	depends on !BR3_MACHINE_SDRAM
+	bool "32 kb"
+
+config OR3_AM_64_KBYTES
+	bool "64 kb"
+
+config OR3_AM_128_KBYTES
+	bool "128 kb"
+
+config OR3_AM_256_KBYTES
+	bool "256 kb"
+
+config OR3_AM_512_KBYTES
+	bool "512 kb"
+
+config OR3_AM_1_MBYTES
+	bool "1 mb"
+
+config OR3_AM_2_MBYTES
+	bool "2 mb"
+
+config OR3_AM_4_MBYTES
+	bool "4 mb"
+
+config OR3_AM_8_MBYTES
+	bool "8 mb"
+
+config OR3_AM_16_MBYTES
+	bool "16 mb"
+
+config OR3_AM_32_MBYTES
+	bool "32 mb"
+
+config OR3_AM_64_MBYTES
+	bool "64 mb"
+
+# XXX: Some boards define 128MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR3_AM_128_MBYTES
+	bool "128 mb"
+
+# XXX: Some boards define 256MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR3_AM_256_MBYTES
+	bool "256 mb"
+
+config OR3_AM_512_MBYTES
+	depends on BR3_MACHINE_FCM
+	bool "512 mb"
+
+# XXX: Some boards define 1GB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR3_AM_1_GBYTES
+	bool "1 gb"
+
+config OR3_AM_2_GBYTES
+	depends on BR3_MACHINE_FCM
+	bool "2 gb"
+
+config OR3_AM_4_GBYTES
+	depends on BR3_MACHINE_FCM
+	bool "4 gb"
+
+endchoice
+
+config OR3_XAM_SET
+	bool "Set unused bytes after address mask"
+choice
+	prompt "Buffer control disable"
+
+config OR3_BCTLD_ASSERTED
+	bool "Asserted"
+
+config OR3_BCTLD_NOT_ASSERTED
+	bool "Not asserted"
+
+endchoice
+
+endif
+
+if BR3_MACHINE_GPCM || BR3_MACHINE_FCM
+
+choice
+	prompt "Cycle length in bus clocks"
+
+config OR3_SCY_0
+	bool "No wait states"
+
+config OR3_SCY_1
+	bool "1 wait state"
+
+config OR3_SCY_2
+	bool "2 wait states"
+
+config OR3_SCY_3
+	bool "3 wait states"
+
+config OR3_SCY_4
+	bool "4 wait states"
+
+config OR3_SCY_5
+	bool "5 wait states"
+
+config OR3_SCY_6
+	bool "6 wait states"
+
+config OR3_SCY_7
+	bool "7 wait states"
+
+config OR3_SCY_8
+	depends on BR3_MACHINE_GPCM
+	bool "8 wait states"
+
+config OR3_SCY_9
+	depends on BR3_MACHINE_GPCM
+	bool "9 wait states"
+
+config OR3_SCY_10
+	depends on BR3_MACHINE_GPCM
+	bool "10 wait states"
+
+config OR3_SCY_11
+	depends on BR3_MACHINE_GPCM
+	bool "11 wait states"
+
+config OR3_SCY_12
+	depends on BR3_MACHINE_GPCM
+	bool "12 wait states"
+
+config OR3_SCY_13
+	depends on BR3_MACHINE_GPCM
+	bool "13 wait states"
+
+config OR3_SCY_14
+	depends on BR3_MACHINE_GPCM
+	bool "14 wait states"
+
+config OR3_SCY_15
+	depends on BR3_MACHINE_GPCM
+	bool "15 wait states"
+
+endchoice
+
+endif # BR3_MACHINE_GPCM || BR3_MACHINE_FCM
+
+if BR3_MACHINE_GPCM
+
+choice
+	prompt "Chip select negotiation time"
+
+config OR3_CSNT_NORMAL
+	bool "Normal"
+
+config OR3_CSNT_EARLIER
+	bool "Earlier"
+
+endchoice
+
+choice
+	prompt "Address to chip-select setup"
+
+config OR3_ACS_SAME_TIME
+	bool "At the same time"
+
+config OR3_ACS_HALF_CYCLE_EARLIER
+	bool "Half of a bus clock cycle earlier"
+
+config OR3_ACS_QUARTER_CYCLE_EARLIER
+	bool "Half/Quarter of a bus clock cycle earlier"
+
+endchoice
+
+choice
+	prompt "Extra address to check-select setup"
+
+config OR3_XACS_NORMAL
+	bool "Normal"
+
+config OR3_XACS_EXTENDED
+	bool "Extended"
+
+endchoice
+
+choice
+	prompt "External address termination"
+
+config OR3_SETA_INTERNAL
+	bool "Access is terminated internally"
+
+config OR3_SETA_EXTERNAL
+	bool "Access is terminated externally"
+
+endchoice
+
+endif # BR3_MACHINE_GPCM
+
+if BR3_MACHINE_FCM
+
+choice
+	prompt "NAND Flash EEPROM page size"
+
+config OR3_PGS_SMALL
+	bool "Small page device"
+
+config OR3_PGS_LARGE
+	bool "Large page device"
+
+endchoice
+
+choice
+	prompt "Chip select to command time"
+
+config OR3_CSCT_1_CYCLE
+	depends on OR3_TRLX_NORMAL
+	bool "1 cycle"
+
+config OR3_CSCT_2_CYCLE
+	depends on OR3_TRLX_RELAXED
+	bool "2 cycles"
+
+config OR3_CSCT_4_CYCLE
+	depends on OR3_TRLX_NORMAL
+	bool "4 cycles"
+
+config OR3_CSCT_8_CYCLE
+	depends on OR3_TRLX_RELAXED
+	bool "8 cycles"
+
+endchoice
+
+choice
+	prompt "Command setup time"
+
+config OR3_CST_COINCIDENT
+	depends on OR3_TRLX_NORMAL
+	bool "Coincident with any command"
+
+config OR3_CST_QUARTER_CLOCK
+	depends on OR3_TRLX_NORMAL
+	bool "0.25 clocks after"
+
+config OR3_CST_HALF_CLOCK
+	depends on OR3_TRLX_RELAXED
+	bool "0.5 clocks after"
+
+config OR3_CST_ONE_CLOCK
+	depends on OR3_TRLX_RELAXED
+	bool "1 clock after"
+
+endchoice
+
+choice
+	prompt "Command hold time"
+
+config OR3_CHT_HALF_CLOCK
+	depends on OR3_TRLX_NORMAL
+	bool "0.5 clocks before"
+
+config OR3_CHT_ONE_CLOCK
+	depends on OR3_TRLX_NORMAL
+	bool "1 clock before"
+
+config OR3_CHT_ONE_HALF_CLOCK
+	depends on OR3_TRLX_RELAXED
+	bool "1.5 clocks before"
+
+config OR3_CHT_TWO_CLOCK
+	depends on OR3_TRLX_RELAXED
+	bool "2 clocks before"
+
+endchoice
+
+choice
+	prompt "Reset setup time"
+
+config OR3_RST_THREE_QUARTER_CLOCK
+	depends on OR3_TRLX_NORMAL
+	bool "0.75 clocks prior"
+
+config OR3_RST_ONE_HALF_CLOCK
+	depends on OR3_TRLX_RELAXED
+	bool "0.5 clocks prior"
+
+config OR3_RST_ONE_CLOCK
+	bool "1 clock prior"
+
+endchoice
+
+endif # BR3_MACHINE_FCM
+
+if BR3_MACHINE_UPM
+
+choice
+	prompt "Burst inhibit"
+
+config OR3_BI_BURSTSUPPORT
+	bool "Support burst access"
+
+config OR3_BI_BURSTINHIBIT
+	bool "Inhibit burst access"
+
+endchoice
+
+endif # BR3_MACHINE_UPM
+
+if BR3_MACHINE_SDRAM
+
+choice
+	prompt "Number of column address lines"
+
+config OR3_COLS_7
+	bool "7"
+
+config OR3_COLS_8
+	bool "8"
+
+config OR3_COLS_9
+	bool "9"
+
+config OR3_COLS_10
+	bool "10"
+
+config OR3_COLS_11
+	bool "11"
+
+config OR3_COLS_12
+	bool "12"
+
+config OR3_COLS_13
+	bool "13"
+
+config OR3_COLS_14
+	bool "14"
+
+endchoice
+
+choice
+	prompt "Number of rows address lines"
+
+config OR3_ROWS_9
+	bool "9"
+
+config OR3_ROWS_10
+	bool "10"
+
+config OR3_ROWS_11
+	bool "11"
+
+config OR3_ROWS_12
+	bool "12"
+
+config OR3_ROWS_13
+	bool "13"
+
+config OR3_ROWS_14
+	bool "14"
+
+config OR3_ROWS_15
+	bool "15"
+
+endchoice
+
+choice
+	prompt "Page mode select"
+
+config OR3_PMSEL_BTB
+	bool "Back-to-back"
+
+config OR3_PMSEL_KEPT_OPEN
+	bool "Page kept open until page miss or refresh"
+
+endchoice
+
+endif # BR3_MACHINE_SDRAM
+
+choice
+	prompt "Relaxed timing"
+
+config OR3_TRLX_NORMAL
+	bool "Normal"
+
+config OR3_TRLX_RELAXED
+	bool "Relaxed"
+
+endchoice
+
+choice
+	prompt "Extended hold time"
+
+config OR3_EHTR_NORMAL
+	depends on OR3_TRLX_NORMAL
+	bool "Normal"
+
+config OR3_EHTR_1_CYCLE
+	depends on OR3_TRLX_NORMAL
+	bool "1 idle clock cycle inserted"
+
+config OR3_EHTR_4_CYCLE
+	depends on OR3_TRLX_RELAXED
+	bool "4 idle clock cycles inserted"
+
+config OR3_EHTR_8_CYCLE
+	depends on OR3_TRLX_RELAXED
+	bool "8 idle clock cycles inserted"
+
+endchoice
+
+if !ARCH_MPC8308
+
+choice
+	prompt "External address latch delay"
+
+config OR3_EAD_NONE
+	bool "None"
+
+config OR3_EAD_EXTRA
+	bool "Extra"
+
+endchoice
+
+endif # !ARCH_MPC8308
+
+endif # ELBC_BR3_OR3
+
+config BR3_PORTSIZE
+	hex
+	default 0x800 if BR3_PORTSIZE_8BIT
+	default 0x1000 if BR3_PORTSIZE_16BIT
+	default 0x1800 if BR3_PORTSIZE_32BIT
+
+config BR3_ERRORCHECKING
+	hex
+	default 0x0 if !BR3_MACHINE_FCM
+	default 0x0 if BR3_ERRORCHECKING_DISABLED
+	default 0x200 if BR3_ERRORCHECKING_ECC_CHECKING
+	default 0x400 if BR3_ERRORCHECKING_BOTH
+
+config BR3_WRITE_PROTECT_BIT
+	hex
+	default 0x0 if !BR3_WRITE_PROTECT
+	default 0x100 if BR3_WRITE_PROTECT
+
+config BR3_MACHINE
+	hex
+	default 0x0 if BR3_MACHINE_GPCM
+	default 0x20 if BR3_MACHINE_FCM
+	default 0x60 if BR3_MACHINE_SDRAM
+	default 0x80 if BR3_MACHINE_UPMA
+	default 0xa0 if BR3_MACHINE_UPMB
+	default 0xc0 if BR3_MACHINE_UPMC
+
+config BR3_ATOMIC
+	hex
+	default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
+	default 0x0 if BR3_ATOMIC_NONE
+	default 0x4 if BR3_ATOMIC_RAWA
+	default 0x8 if BR3_ATOMIC_WARA
+
+config BR3_VALID_BIT
+	hex
+	default 0x0 if !ELBC_BR3_OR3
+	default 0x1 if ELBC_BR3_OR3
+
+config OR3_AM
+	hex
+	default 0xffff8000 if OR3_AM_32_KBYTES && !BR3_MACHINE_SDRAM
+	default 0xffff0000 if OR3_AM_64_KBYTES
+	default 0xfffe0000 if OR3_AM_128_KBYTES
+	default 0xfffc0000 if OR3_AM_256_KBYTES
+	default 0xfff80000 if OR3_AM_512_KBYTES
+	default 0xfff00000 if OR3_AM_1_MBYTES
+	default 0xffe00000 if OR3_AM_2_MBYTES
+	default 0xffc00000 if OR3_AM_4_MBYTES
+	default 0xff800000 if OR3_AM_8_MBYTES
+	default 0xff000000 if OR3_AM_16_MBYTES
+	default 0xfe000000 if OR3_AM_32_MBYTES
+	default 0xfc000000 if OR3_AM_64_MBYTES
+	default 0xf8000000 if OR3_AM_128_MBYTES
+	default 0xf0000000 if OR3_AM_256_MBYTES
+	default 0xe0000000 if OR3_AM_512_MBYTES
+	default 0xc0000000 if OR3_AM_1_GBYTES
+	default 0x80000000 if OR3_AM_2_GBYTES
+	default 0x00000000 if OR3_AM_4_GBYTES
+
+config OR3_XAM
+	hex
+	default 0x0 if !OR3_XAM_SET
+	default 0x6000 if OR3_XAM_SET
+
+config OR3_BCTLD
+	hex
+	default 0x0 if OR3_BCTLD_ASSERTED
+	default 0x1000 if OR3_BCTLD_NOT_ASSERTED
+
+config OR3_BI
+	hex
+	default 0x0 if !BR3_MACHINE_UPM
+	default 0x0 if OR3_BI_BURSTSUPPORT
+	default 0x100 if OR3_BI_BURSTINHIBIT
+
+config OR3_COLS
+	hex
+	default 0x0 if !BR3_MACHINE_SDRAM
+	default 0x0 if OR3_COLS_7
+	default 0x400 if OR3_COLS_8
+	default 0x800 if OR3_COLS_9
+	default 0xc00 if OR3_COLS_10
+	default 0x1000 if OR3_COLS_11
+	default 0x1400 if OR3_COLS_12
+	default 0x1800 if OR3_COLS_13
+	default 0x1c00 if OR3_COLS_14
+
+config OR3_ROWS
+	hex
+	default 0x0 if !BR3_MACHINE_SDRAM
+	default 0x0 if OR3_ROWS_9
+	default 0x40 if OR3_ROWS_10
+	default 0x80 if OR3_ROWS_11
+	default 0xc0 if OR3_ROWS_12
+	default 0x100 if OR3_ROWS_13
+	default 0x140 if OR3_ROWS_14
+	default 0x180 if OR3_ROWS_15
+
+config OR3_PMSEL
+	hex
+	default 0x0 if !BR3_MACHINE_SDRAM
+	default 0x0 if OR3_PMSEL_BTB
+	default 0x20 if OR3_PMSEL_KEPT_OPEN
+
+config OR3_SCY
+	hex
+	default 0x0 if !BR3_MACHINE_GPCM && !BR3_MACHINE_FCM
+	default 0x0 if OR3_SCY_0
+	default 0x10 if OR3_SCY_1
+	default 0x20 if OR3_SCY_2
+	default 0x30 if OR3_SCY_3
+	default 0x40 if OR3_SCY_4
+	default 0x50 if OR3_SCY_5
+	default 0x60 if OR3_SCY_6
+	default 0x70 if OR3_SCY_7
+	default 0x80 if OR3_SCY_8
+	default 0x90 if OR3_SCY_9
+	default 0xa0 if OR3_SCY_10
+	default 0xb0 if OR3_SCY_11
+	default 0xc0 if OR3_SCY_12
+	default 0xd0 if OR3_SCY_13
+	default 0xe0 if OR3_SCY_14
+	default 0xf0 if OR3_SCY_15
+
+config OR3_PGS
+	hex
+	default 0x0 if !BR3_MACHINE_FCM
+	default 0x0 if OR3_PGS_SMALL
+	default 0x400 if OR3_PGS_LARGE
+
+config OR3_CSCT
+	hex
+	default 0x0 if !BR3_MACHINE_FCM
+	default 0x0 if OR3_CSCT_1_CYCLE
+	default 0x0 if OR3_CSCT_2_CYCLE
+	default 0x200 if OR3_CSCT_4_CYCLE
+	default 0x200 if OR3_CSCT_8_CYCLE
+
+config OR3_CST
+	hex
+	default 0x0 if !BR3_MACHINE_FCM
+	default 0x0 if OR3_CST_COINCIDENT
+	default 0x100 if OR3_CST_QUARTER_CLOCK
+	default 0x0 if OR3_CST_HALF_CLOCK
+	default 0x100 if OR3_CST_ONE_CLOCK
+
+config OR3_CHT
+	hex
+	default 0x0 if !BR3_MACHINE_FCM
+	default 0x0 if OR3_CHT_HALF_CLOCK
+	default 0x80 if OR3_CHT_ONE_CLOCK
+	default 0x0 if OR3_CHT_ONE_HALF_CLOCK
+	default 0x80 if OR3_CHT_TWO_CLOCK
+
+config OR3_RST
+	hex
+	default 0x0 if !BR3_MACHINE_FCM
+	default 0x0 if OR3_RST_THREE_QUARTER_CLOCK
+	default 0x8 if OR3_RST_ONE_CLOCK
+	default 0x0 if OR3_RST_ONE_HALF_CLOCK
+
+config OR3_CSNT
+	hex
+	default 0x0 if !BR3_MACHINE_GPCM
+	default 0x0 if OR3_CSNT_NORMAL
+	default 0x800 if OR3_CSNT_EARLIER
+
+config OR3_ACS
+	hex
+	default 0x0 if !BR3_MACHINE_GPCM
+	default 0x0 if OR3_ACS_SAME_TIME
+	default 0x400 if OR3_ACS_QUARTER_CYCLE_EARLIER
+	default 0x600 if OR3_ACS_HALF_CYCLE_EARLIER
+
+config OR3_XACS
+	hex
+	default 0x0 if !BR3_MACHINE_GPCM
+	default 0x0 if OR3_XACS_NORMAL
+	default 0x100 if OR3_XACS_EXTENDED
+
+config OR3_SETA
+	hex
+	default 0x0 if !BR3_MACHINE_GPCM
+	default 0x0 if OR3_SETA_INTERNAL
+	default 0x8 if OR3_SETA_EXTERNAL
+
+config OR3_TRLX
+	hex
+	default 0x0 if OR3_TRLX_NORMAL
+	default 0x4 if OR3_TRLX_RELAXED
+
+config OR3_EHTR
+	hex
+	default 0x0 if OR3_EHTR_NORMAL
+	default 0x2 if OR3_EHTR_1_CYCLE
+	default 0x0 if OR3_EHTR_4_CYCLE
+	default 0x2 if OR3_EHTR_8_CYCLE
+
+config OR3_EAD
+	hex
+	default 0x0 if ARCH_MPC8308
+	default 0x0 if OR3_EAD_NONE
+	default 0x1 if OR3_EAD_EXTRA
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 b/roms/u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4
new file mode 100644
index 000000000..0063dab96
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4
@@ -0,0 +1,733 @@
+menuconfig ELBC_BR4_OR4
+	bool "ELBC BR4/OR4"
+
+if ELBC_BR4_OR4
+
+config BR4_OR4_NAME
+	string "Identifier"
+
+config BR4_OR4_BASE
+	hex "Port base"
+
+choice
+	prompt "Port size"
+
+config BR4_PORTSIZE_8BIT
+	bool "8-bit"
+
+config BR4_PORTSIZE_16BIT
+	depends on !BR4_MACHINE_FCM
+	bool "16-bit"
+
+
+config BR4_PORTSIZE_32BIT
+	depends on !BR4_MACHINE_FCM
+	depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+	bool "32-bit"
+
+endchoice
+
+if BR4_MACHINE_FCM
+
+choice
+	prompt "Data Error Checking"
+
+config BR4_ERRORCHECKING_DISABLED
+	bool "Disabled"
+
+config BR4_ERRORCHECKING_ECC_CHECKING
+	bool "ECC checking / No ECC generation"
+
+config BR4_ERRORCHECKING_BOTH
+	bool "ECC checking and generation"
+
+endchoice
+
+endif
+
+config BR4_WRITE_PROTECT
+	bool "Write-protect"
+
+config BR4_MACHINE_UPM
+	bool
+
+choice
+	prompt "Machine select"
+
+config BR4_MACHINE_GPCM
+	bool "GPCM"
+
+config BR4_MACHINE_FCM
+	depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+	bool "FCM"
+
+config BR4_MACHINE_SDRAM
+	depends on ARCH_MPC8349 || ARCH_MPC8360
+	bool "SDRAM"
+
+config BR4_MACHINE_UPMA
+	select BR4_MACHINE_UPM
+	bool "UPM (A)"
+
+config BR4_MACHINE_UPMB
+	select BR4_MACHINE_UPM
+	bool "UPM (B)"
+
+config BR4_MACHINE_UPMC
+	select BR4_MACHINE_UPM
+	bool "UPM (C)"
+
+endchoice
+
+if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
+
+choice
+	prompt "Atomic operations"
+
+config BR4_ATOMIC_NONE
+	bool "No atomic operations"
+
+config BR4_ATOMIC_RAWA
+	bool "Read-after-write-atomic"
+
+config BR4_ATOMIC_WARA
+	bool "Write-after-read-atomic"
+
+endchoice
+
+endif
+
+if BR4_MACHINE_GPCM || BR4_MACHINE_FCM || BR4_MACHINE_UPM || BR4_MACHINE_SDRAM
+
+choice
+	prompt "Address mask"
+
+config OR4_AM_32_KBYTES
+	depends on !BR4_MACHINE_SDRAM
+	bool "32 kb"
+
+config OR4_AM_64_KBYTES
+	bool "64 kb"
+
+config OR4_AM_128_KBYTES
+	bool "128 kb"
+
+config OR4_AM_256_KBYTES
+	bool "256 kb"
+
+config OR4_AM_512_KBYTES
+	bool "512 kb"
+
+config OR4_AM_1_MBYTES
+	bool "1 mb"
+
+config OR4_AM_2_MBYTES
+	bool "2 mb"
+
+config OR4_AM_4_MBYTES
+	bool "4 mb"
+
+config OR4_AM_8_MBYTES
+	bool "8 mb"
+
+config OR4_AM_16_MBYTES
+	bool "16 mb"
+
+config OR4_AM_32_MBYTES
+	bool "32 mb"
+
+config OR4_AM_64_MBYTES
+	bool "64 mb"
+
+# XXX: Some boards define 128MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR4_AM_128_MBYTES
+	bool "128 mb"
+
+# XXX: Some boards define 256MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR4_AM_256_MBYTES
+	bool "256 mb"
+
+config OR4_AM_512_MBYTES
+	depends on BR4_MACHINE_FCM
+	bool "512 mb"
+
+# XXX: Some boards define 1GB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR4_AM_1_GBYTES
+	bool "1 gb"
+
+config OR4_AM_2_GBYTES
+	depends on BR4_MACHINE_FCM
+	bool "2 gb"
+
+config OR4_AM_4_GBYTES
+	depends on BR4_MACHINE_FCM
+	bool "4 gb"
+
+endchoice
+
+config OR4_XAM_SET
+	bool "Set unused bytes after address mask"
+choice
+	prompt "Buffer control disable"
+
+config OR4_BCTLD_ASSERTED
+	bool "Asserted"
+
+config OR4_BCTLD_NOT_ASSERTED
+	bool "Not asserted"
+
+endchoice
+
+endif
+
+if BR4_MACHINE_GPCM || BR4_MACHINE_FCM
+
+choice
+	prompt "Cycle length in bus clocks"
+
+config OR4_SCY_0
+	bool "No wait states"
+
+config OR4_SCY_1
+	bool "1 wait state"
+
+config OR4_SCY_2
+	bool "2 wait states"
+
+config OR4_SCY_3
+	bool "3 wait states"
+
+config OR4_SCY_4
+	bool "4 wait states"
+
+config OR4_SCY_5
+	bool "5 wait states"
+
+config OR4_SCY_6
+	bool "6 wait states"
+
+config OR4_SCY_7
+	bool "7 wait states"
+
+config OR4_SCY_8
+	depends on BR4_MACHINE_GPCM
+	bool "8 wait states"
+
+config OR4_SCY_9
+	depends on BR4_MACHINE_GPCM
+	bool "9 wait states"
+
+config OR4_SCY_10
+	depends on BR4_MACHINE_GPCM
+	bool "10 wait states"
+
+config OR4_SCY_11
+	depends on BR4_MACHINE_GPCM
+	bool "11 wait states"
+
+config OR4_SCY_12
+	depends on BR4_MACHINE_GPCM
+	bool "12 wait states"
+
+config OR4_SCY_13
+	depends on BR4_MACHINE_GPCM
+	bool "13 wait states"
+
+config OR4_SCY_14
+	depends on BR4_MACHINE_GPCM
+	bool "14 wait states"
+
+config OR4_SCY_15
+	depends on BR4_MACHINE_GPCM
+	bool "15 wait states"
+
+endchoice
+
+endif # BR4_MACHINE_GPCM || BR4_MACHINE_FCM
+
+if BR4_MACHINE_GPCM
+
+choice
+	prompt "Chip select negotiation time"
+
+config OR4_CSNT_NORMAL
+	bool "Normal"
+
+config OR4_CSNT_EARLIER
+	bool "Earlier"
+
+endchoice
+
+choice
+	prompt "Address to chip-select setup"
+
+config OR4_ACS_SAME_TIME
+	bool "At the same time"
+
+config OR4_ACS_HALF_CYCLE_EARLIER
+	bool "Half of a bus clock cycle earlier"
+
+config OR4_ACS_QUARTER_CYCLE_EARLIER
+	bool "Half/Quarter of a bus clock cycle earlier"
+
+endchoice
+
+choice
+	prompt "Extra address to check-select setup"
+
+config OR4_XACS_NORMAL
+	bool "Normal"
+
+config OR4_XACS_EXTENDED
+	bool "Extended"
+
+endchoice
+
+choice
+	prompt "External address termination"
+
+config OR4_SETA_INTERNAL
+	bool "Access is terminated internally"
+
+config OR4_SETA_EXTERNAL
+	bool "Access is terminated externally"
+
+endchoice
+
+endif # BR4_MACHINE_GPCM
+
+if BR4_MACHINE_FCM
+
+choice
+	prompt "NAND Flash EEPROM page size"
+
+config OR4_PGS_SMALL
+	bool "Small page device"
+
+config OR4_PGS_LARGE
+	bool "Large page device"
+
+endchoice
+
+choice
+	prompt "Chip select to command time"
+
+config OR4_CSCT_1_CYCLE
+	depends on OR4_TRLX_NORMAL
+	bool "1 cycle"
+
+config OR4_CSCT_2_CYCLE
+	depends on OR4_TRLX_RELAXED
+	bool "2 cycles"
+
+config OR4_CSCT_4_CYCLE
+	depends on OR4_TRLX_NORMAL
+	bool "4 cycles"
+
+config OR4_CSCT_8_CYCLE
+	depends on OR4_TRLX_RELAXED
+	bool "8 cycles"
+
+endchoice
+
+choice
+	prompt "Command setup time"
+
+config OR4_CST_COINCIDENT
+	depends on OR4_TRLX_NORMAL
+	bool "Coincident with any command"
+
+config OR4_CST_QUARTER_CLOCK
+	depends on OR4_TRLX_NORMAL
+	bool "0.25 clocks after"
+
+config OR4_CST_HALF_CLOCK
+	depends on OR4_TRLX_RELAXED
+	bool "0.5 clocks after"
+
+config OR4_CST_ONE_CLOCK
+	depends on OR4_TRLX_RELAXED
+	bool "1 clock after"
+
+endchoice
+
+choice
+	prompt "Command hold time"
+
+config OR4_CHT_HALF_CLOCK
+	depends on OR4_TRLX_NORMAL
+	bool "0.5 clocks before"
+
+config OR4_CHT_ONE_CLOCK
+	depends on OR4_TRLX_NORMAL
+	bool "1 clock before"
+
+config OR4_CHT_ONE_HALF_CLOCK
+	depends on OR4_TRLX_RELAXED
+	bool "1.5 clocks before"
+
+config OR4_CHT_TWO_CLOCK
+	depends on OR4_TRLX_RELAXED
+	bool "2 clocks before"
+
+endchoice
+
+choice
+	prompt "Reset setup time"
+
+config OR4_RST_THREE_QUARTER_CLOCK
+	depends on OR4_TRLX_NORMAL
+	bool "0.75 clocks prior"
+
+config OR4_RST_ONE_HALF_CLOCK
+	depends on OR4_TRLX_RELAXED
+	bool "0.5 clocks prior"
+
+config OR4_RST_ONE_CLOCK
+	bool "1 clock prior"
+
+endchoice
+
+endif # BR4_MACHINE_FCM
+
+if BR4_MACHINE_UPM
+
+choice
+	prompt "Burst inhibit"
+
+config OR4_BI_BURSTSUPPORT
+	bool "Support burst access"
+
+config OR4_BI_BURSTINHIBIT
+	bool "Inhibit burst access"
+
+endchoice
+
+endif # BR4_MACHINE_UPM
+
+if BR4_MACHINE_SDRAM
+
+choice
+	prompt "Number of column address lines"
+
+config OR4_COLS_7
+	bool "7"
+
+config OR4_COLS_8
+	bool "8"
+
+config OR4_COLS_9
+	bool "9"
+
+config OR4_COLS_10
+	bool "10"
+
+config OR4_COLS_11
+	bool "11"
+
+config OR4_COLS_12
+	bool "12"
+
+config OR4_COLS_13
+	bool "13"
+
+config OR4_COLS_14
+	bool "14"
+
+endchoice
+
+choice
+	prompt "Number of rows address lines"
+
+config OR4_ROWS_9
+	bool "9"
+
+config OR4_ROWS_10
+	bool "10"
+
+config OR4_ROWS_11
+	bool "11"
+
+config OR4_ROWS_12
+	bool "12"
+
+config OR4_ROWS_13
+	bool "13"
+
+config OR4_ROWS_14
+	bool "14"
+
+config OR4_ROWS_15
+	bool "15"
+
+endchoice
+
+choice
+	prompt "Page mode select"
+
+config OR4_PMSEL_BTB
+	bool "Back-to-back"
+
+config OR4_PMSEL_KEPT_OPEN
+	bool "Page kept open until page miss or refresh"
+
+endchoice
+
+endif # BR4_MACHINE_SDRAM
+
+choice
+	prompt "Relaxed timing"
+
+config OR4_TRLX_NORMAL
+	bool "Normal"
+
+config OR4_TRLX_RELAXED
+	bool "Relaxed"
+
+endchoice
+
+choice
+	prompt "Extended hold time"
+
+config OR4_EHTR_NORMAL
+	depends on OR4_TRLX_NORMAL
+	bool "Normal"
+
+config OR4_EHTR_1_CYCLE
+	depends on OR4_TRLX_NORMAL
+	bool "1 idle clock cycle inserted"
+
+config OR4_EHTR_4_CYCLE
+	depends on OR4_TRLX_RELAXED
+	bool "4 idle clock cycles inserted"
+
+config OR4_EHTR_8_CYCLE
+	depends on OR4_TRLX_RELAXED
+	bool "8 idle clock cycles inserted"
+
+endchoice
+
+if !ARCH_MPC8308
+
+choice
+	prompt "External address latch delay"
+
+config OR4_EAD_NONE
+	bool "None"
+
+config OR4_EAD_EXTRA
+	bool "Extra"
+
+endchoice
+
+endif # !ARCH_MPC8308
+
+endif # ELBC_BR4_OR4
+
+config BR4_PORTSIZE
+	hex
+	default 0x800 if BR4_PORTSIZE_8BIT
+	default 0x1000 if BR4_PORTSIZE_16BIT
+	default 0x1800 if BR4_PORTSIZE_32BIT
+
+config BR4_ERRORCHECKING
+	hex
+	default 0x0 if !BR4_MACHINE_FCM
+	default 0x0 if BR4_ERRORCHECKING_DISABLED
+	default 0x200 if BR4_ERRORCHECKING_ECC_CHECKING
+	default 0x400 if BR4_ERRORCHECKING_BOTH
+
+config BR4_WRITE_PROTECT_BIT
+	hex
+	default 0x0 if !BR4_WRITE_PROTECT
+	default 0x100 if BR4_WRITE_PROTECT
+
+config BR4_MACHINE
+	hex
+	default 0x0 if BR4_MACHINE_GPCM
+	default 0x20 if BR4_MACHINE_FCM
+	default 0x60 if BR4_MACHINE_SDRAM
+	default 0x80 if BR4_MACHINE_UPMA
+	default 0xa0 if BR4_MACHINE_UPMB
+	default 0xc0 if BR4_MACHINE_UPMC
+
+config BR4_ATOMIC
+	hex
+	default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
+	default 0x0 if BR4_ATOMIC_NONE
+	default 0x4 if BR4_ATOMIC_RAWA
+	default 0x8 if BR4_ATOMIC_WARA
+
+config BR4_VALID_BIT
+	hex
+	default 0x0 if !ELBC_BR4_OR4
+	default 0x1 if ELBC_BR4_OR4
+
+config OR4_AM
+	hex
+	default 0xffff8000 if OR4_AM_32_KBYTES && !BR4_MACHINE_SDRAM
+	default 0xffff0000 if OR4_AM_64_KBYTES
+	default 0xfffe0000 if OR4_AM_128_KBYTES
+	default 0xfffc0000 if OR4_AM_256_KBYTES
+	default 0xfff80000 if OR4_AM_512_KBYTES
+	default 0xfff00000 if OR4_AM_1_MBYTES
+	default 0xffe00000 if OR4_AM_2_MBYTES
+	default 0xffc00000 if OR4_AM_4_MBYTES
+	default 0xff800000 if OR4_AM_8_MBYTES
+	default 0xff000000 if OR4_AM_16_MBYTES
+	default 0xfe000000 if OR4_AM_32_MBYTES
+	default 0xfc000000 if OR4_AM_64_MBYTES
+	default 0xf8000000 if OR4_AM_128_MBYTES
+	default 0xf0000000 if OR4_AM_256_MBYTES
+	default 0xe0000000 if OR4_AM_512_MBYTES
+	default 0xc0000000 if OR4_AM_1_GBYTES
+	default 0x80000000 if OR4_AM_2_GBYTES
+	default 0x00000000 if OR4_AM_4_GBYTES
+
+config OR4_XAM
+	hex
+	default 0x0 if !OR4_XAM_SET
+	default 0x6000 if OR4_XAM_SET
+
+config OR4_BCTLD
+	hex
+	default 0x0 if OR4_BCTLD_ASSERTED
+	default 0x1000 if OR4_BCTLD_NOT_ASSERTED
+
+config OR4_BI
+	hex
+	default 0x0 if !BR4_MACHINE_UPM
+	default 0x0 if OR4_BI_BURSTSUPPORT
+	default 0x100 if OR4_BI_BURSTINHIBIT
+
+config OR4_COLS
+	hex
+	default 0x0 if !BR4_MACHINE_SDRAM
+	default 0x0 if OR4_COLS_7
+	default 0x400 if OR4_COLS_8
+	default 0x800 if OR4_COLS_9
+	default 0xc00 if OR4_COLS_10
+	default 0x1000 if OR4_COLS_11
+	default 0x1400 if OR4_COLS_12
+	default 0x1800 if OR4_COLS_13
+	default 0x1c00 if OR4_COLS_14
+
+config OR4_ROWS
+	hex
+	default 0x0 if !BR4_MACHINE_SDRAM
+	default 0x0 if OR4_ROWS_9
+	default 0x40 if OR4_ROWS_10
+	default 0x80 if OR4_ROWS_11
+	default 0xc0 if OR4_ROWS_12
+	default 0x100 if OR4_ROWS_13
+	default 0x140 if OR4_ROWS_14
+	default 0x180 if OR4_ROWS_15
+
+config OR4_PMSEL
+	hex
+	default 0x0 if !BR4_MACHINE_SDRAM
+	default 0x0 if OR4_PMSEL_BTB
+	default 0x20 if OR4_PMSEL_KEPT_OPEN
+
+config OR4_SCY
+	hex
+	default 0x0 if !BR4_MACHINE_GPCM && !BR4_MACHINE_FCM
+	default 0x0 if OR4_SCY_0
+	default 0x10 if OR4_SCY_1
+	default 0x20 if OR4_SCY_2
+	default 0x30 if OR4_SCY_3
+	default 0x40 if OR4_SCY_4
+	default 0x50 if OR4_SCY_5
+	default 0x60 if OR4_SCY_6
+	default 0x70 if OR4_SCY_7
+	default 0x80 if OR4_SCY_8
+	default 0x90 if OR4_SCY_9
+	default 0xa0 if OR4_SCY_10
+	default 0xb0 if OR4_SCY_11
+	default 0xc0 if OR4_SCY_12
+	default 0xd0 if OR4_SCY_13
+	default 0xe0 if OR4_SCY_14
+	default 0xf0 if OR4_SCY_15
+
+config OR4_PGS
+	hex
+	default 0x0 if !BR4_MACHINE_FCM
+	default 0x0 if OR4_PGS_SMALL
+	default 0x400 if OR4_PGS_LARGE
+
+config OR4_CSCT
+	hex
+	default 0x0 if !BR4_MACHINE_FCM
+	default 0x0 if OR4_CSCT_1_CYCLE
+	default 0x0 if OR4_CSCT_2_CYCLE
+	default 0x200 if OR4_CSCT_4_CYCLE
+	default 0x200 if OR4_CSCT_8_CYCLE
+
+config OR4_CST
+	hex
+	default 0x0 if !BR4_MACHINE_FCM
+	default 0x0 if OR4_CST_COINCIDENT
+	default 0x100 if OR4_CST_QUARTER_CLOCK
+	default 0x0 if OR4_CST_HALF_CLOCK
+	default 0x100 if OR4_CST_ONE_CLOCK
+
+config OR4_CHT
+	hex
+	default 0x0 if !BR4_MACHINE_FCM
+	default 0x0 if OR4_CHT_HALF_CLOCK
+	default 0x80 if OR4_CHT_ONE_CLOCK
+	default 0x0 if OR4_CHT_ONE_HALF_CLOCK
+	default 0x80 if OR4_CHT_TWO_CLOCK
+
+config OR4_RST
+	hex
+	default 0x0 if !BR4_MACHINE_FCM
+	default 0x0 if OR4_RST_THREE_QUARTER_CLOCK
+	default 0x8 if OR4_RST_ONE_CLOCK
+	default 0x0 if OR4_RST_ONE_HALF_CLOCK
+
+config OR4_CSNT
+	hex
+	default 0x0 if !BR4_MACHINE_GPCM
+	default 0x0 if OR4_CSNT_NORMAL
+	default 0x800 if OR4_CSNT_EARLIER
+
+config OR4_ACS
+	hex
+	default 0x0 if !BR4_MACHINE_GPCM
+	default 0x0 if OR4_ACS_SAME_TIME
+	default 0x400 if OR4_ACS_QUARTER_CYCLE_EARLIER
+	default 0x600 if OR4_ACS_HALF_CYCLE_EARLIER
+
+config OR4_XACS
+	hex
+	default 0x0 if !BR4_MACHINE_GPCM
+	default 0x0 if OR4_XACS_NORMAL
+	default 0x100 if OR4_XACS_EXTENDED
+
+config OR4_SETA
+	hex
+	default 0x0 if !BR4_MACHINE_GPCM
+	default 0x0 if OR4_SETA_INTERNAL
+	default 0x8 if OR4_SETA_EXTERNAL
+
+config OR4_TRLX
+	hex
+	default 0x0 if OR4_TRLX_NORMAL
+	default 0x4 if OR4_TRLX_RELAXED
+
+config OR4_EHTR
+	hex
+	default 0x0 if OR4_EHTR_NORMAL
+	default 0x2 if OR4_EHTR_1_CYCLE
+	default 0x0 if OR4_EHTR_4_CYCLE
+	default 0x2 if OR4_EHTR_8_CYCLE
+
+config OR4_EAD
+	hex
+	default 0x0 if ARCH_MPC8308
+	default 0x0 if OR4_EAD_NONE
+	default 0x1 if OR4_EAD_EXTRA
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/elbc/elbc.h b/roms/u-boot/arch/powerpc/cpu/mpc83xx/elbc/elbc.h
new file mode 100644
index 000000000..245fe7c6f
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/elbc/elbc.h
@@ -0,0 +1,186 @@
+#ifdef CONFIG_ELBC_BR0_OR0
+#define CONFIG_SYS_BR0_PRELIM (\
+	CONFIG_BR0_OR0_BASE |\
+	CONFIG_BR0_PORTSIZE |\
+	CONFIG_BR0_ERRORCHECKING |\
+	CONFIG_BR0_WRITE_PROTECT_BIT |\
+	CONFIG_BR0_MACHINE |\
+	CONFIG_BR0_ATOMIC |\
+	CONFIG_BR0_VALID_BIT \
+)
+#define CONFIG_SYS_OR0_PRELIM (\
+	CONFIG_OR0_AM |\
+	CONFIG_OR0_XAM |\
+	CONFIG_OR0_BCTLD |\
+	CONFIG_OR0_BI |\
+	CONFIG_OR0_COLS |\
+	CONFIG_OR0_ROWS |\
+	CONFIG_OR0_PMSEL |\
+	CONFIG_OR0_SCY |\
+	CONFIG_OR0_PGS |\
+	CONFIG_OR0_CSCT |\
+	CONFIG_OR0_CST |\
+	CONFIG_OR0_CHT |\
+	CONFIG_OR0_RST |\
+	CONFIG_OR0_CSNT |\
+	CONFIG_OR0_ACS |\
+	CONFIG_OR0_XACS |\
+	CONFIG_OR0_SETA |\
+	CONFIG_OR0_TRLX |\
+	CONFIG_OR0_EHTR |\
+	CONFIG_OR0_EAD \
+)
+#endif /* CONFIG_ELBC_BR0_OR0 */
+
+#ifdef CONFIG_ELBC_BR1_OR1
+#define CONFIG_SYS_BR1_PRELIM (\
+	CONFIG_BR1_OR1_BASE |\
+	CONFIG_BR1_PORTSIZE |\
+	CONFIG_BR1_ERRORCHECKING |\
+	CONFIG_BR1_WRITE_PROTECT_BIT |\
+	CONFIG_BR1_MACHINE |\
+	CONFIG_BR1_ATOMIC |\
+	CONFIG_BR1_VALID_BIT \
+)
+#define CONFIG_SYS_OR1_PRELIM (\
+	CONFIG_OR1_AM |\
+	CONFIG_OR1_XAM |\
+	CONFIG_OR1_BCTLD |\
+	CONFIG_OR1_BI |\
+	CONFIG_OR1_COLS |\
+	CONFIG_OR1_ROWS |\
+	CONFIG_OR1_PMSEL |\
+	CONFIG_OR1_SCY |\
+	CONFIG_OR1_PGS |\
+	CONFIG_OR1_CSCT |\
+	CONFIG_OR1_CST |\
+	CONFIG_OR1_CHT |\
+	CONFIG_OR1_RST |\
+	CONFIG_OR1_CSNT |\
+	CONFIG_OR1_ACS |\
+	CONFIG_OR1_XACS |\
+	CONFIG_OR1_SETA |\
+	CONFIG_OR1_TRLX |\
+	CONFIG_OR1_EHTR |\
+	CONFIG_OR1_EAD \
+)
+#endif /* CONFIG_ELBC_BR1_OR1 */
+
+#ifdef CONFIG_ELBC_BR2_OR2
+#define CONFIG_SYS_BR2_PRELIM (\
+	CONFIG_BR2_OR2_BASE |\
+	CONFIG_BR2_PORTSIZE |\
+	CONFIG_BR2_ERRORCHECKING |\
+	CONFIG_BR2_WRITE_PROTECT_BIT |\
+	CONFIG_BR2_MACHINE |\
+	CONFIG_BR2_ATOMIC |\
+	CONFIG_BR2_VALID_BIT \
+)
+#define CONFIG_SYS_OR2_PRELIM (\
+	CONFIG_OR2_AM |\
+	CONFIG_OR2_XAM |\
+	CONFIG_OR2_BCTLD |\
+	CONFIG_OR2_BI |\
+	CONFIG_OR2_COLS |\
+	CONFIG_OR2_ROWS |\
+	CONFIG_OR2_PMSEL |\
+	CONFIG_OR2_SCY |\
+	CONFIG_OR2_PGS |\
+	CONFIG_OR2_CSCT |\
+	CONFIG_OR2_CST |\
+	CONFIG_OR2_CHT |\
+	CONFIG_OR2_RST |\
+	CONFIG_OR2_CSNT |\
+	CONFIG_OR2_ACS |\
+	CONFIG_OR2_XACS |\
+	CONFIG_OR2_SETA |\
+	CONFIG_OR2_TRLX |\
+	CONFIG_OR2_EHTR |\
+	CONFIG_OR2_EAD \
+)
+#endif /* CONFIG_ELBC_BR2_OR2 */
+
+#ifdef CONFIG_ELBC_BR3_OR3
+#define CONFIG_SYS_BR3_PRELIM (\
+	CONFIG_BR3_OR3_BASE |\
+	CONFIG_BR3_PORTSIZE |\
+	CONFIG_BR3_ERRORCHECKING |\
+	CONFIG_BR3_WRITE_PROTECT_BIT |\
+	CONFIG_BR3_MACHINE |\
+	CONFIG_BR3_ATOMIC |\
+	CONFIG_BR3_VALID_BIT \
+)
+#define CONFIG_SYS_OR3_PRELIM (\
+	CONFIG_OR3_AM |\
+	CONFIG_OR3_XAM |\
+	CONFIG_OR3_BCTLD |\
+	CONFIG_OR3_BI |\
+	CONFIG_OR3_COLS |\
+	CONFIG_OR3_ROWS |\
+	CONFIG_OR3_PMSEL |\
+	CONFIG_OR3_SCY |\
+	CONFIG_OR3_PGS |\
+	CONFIG_OR3_CSCT |\
+	CONFIG_OR3_CST |\
+	CONFIG_OR3_CHT |\
+	CONFIG_OR3_RST |\
+	CONFIG_OR3_CSNT |\
+	CONFIG_OR3_ACS |\
+	CONFIG_OR3_XACS |\
+	CONFIG_OR3_SETA |\
+	CONFIG_OR3_TRLX |\
+	CONFIG_OR3_EHTR |\
+	CONFIG_OR3_EAD \
+)
+#endif /* CONFIG_ELBC_BR3_OR3 */
+
+#ifdef CONFIG_ELBC_BR4_OR4
+#define CONFIG_SYS_BR4_PRELIM (\
+	CONFIG_BR4_OR4_BASE |\
+	CONFIG_BR4_PORTSIZE |\
+	CONFIG_BR4_ERRORCHECKING |\
+	CONFIG_BR4_WRITE_PROTECT_BIT |\
+	CONFIG_BR4_MACHINE |\
+	CONFIG_BR4_ATOMIC |\
+	CONFIG_BR4_VALID_BIT \
+)
+#define CONFIG_SYS_OR4_PRELIM (\
+	CONFIG_OR4_AM |\
+	CONFIG_OR4_XAM |\
+	CONFIG_OR4_BCTLD |\
+	CONFIG_OR4_BI |\
+	CONFIG_OR4_COLS |\
+	CONFIG_OR4_ROWS |\
+	CONFIG_OR4_PMSEL |\
+	CONFIG_OR4_SCY |\
+	CONFIG_OR4_PGS |\
+	CONFIG_OR4_CSCT |\
+	CONFIG_OR4_CST |\
+	CONFIG_OR4_CHT |\
+	CONFIG_OR4_RST |\
+	CONFIG_OR4_CSNT |\
+	CONFIG_OR4_ACS |\
+	CONFIG_OR4_XACS |\
+	CONFIG_OR4_SETA |\
+	CONFIG_OR4_TRLX |\
+	CONFIG_OR4_EHTR |\
+	CONFIG_OR4_EAD \
+)
+#endif /* CONFIG_ELBC_BR4_OR4 */
+
+#if defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_0)
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
+#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_1)
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
+#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_2)
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR2_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR2_PRELIM
+#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_3)
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR3_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR3_PRELIM
+#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_4)
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR4_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR4_PRELIM
+#endif
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/fdt.c b/roms/u-boot/arch/powerpc/cpu/mpc83xx/fdt.c
new file mode 100644
index 000000000..3393ad562
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/fdt.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <asm/global_data.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <asm/processor.h>
+
+extern void ft_qe_setup(void *blob);
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
+	(defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X))
+#include <linux/immap_qe.h>
+
+void fdt_fixup_muram (void *blob)
+{
+	ulong data[2];
+
+	data[0] = 0;
+	data[1] = QE_MURAM_SIZE - 2 * sizeof(unsigned long);
+	do_fixup_by_compat(blob, "fsl,qe-muram-data", "reg",
+			data, sizeof (data), 0);
+}
+#endif
+
+void ft_cpu_setup(void *blob, struct bd_info *bd)
+{
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	int spridr = immr->sysconf.spridr;
+
+	/*
+	 * delete crypto node if not on an E-processor
+	 * initial revisions of the MPC834xE/6xE have the original SEC 2.0.
+	 * EA revisions got the SEC uprevved to 2.4 but since the default device
+	 * tree contains SEC 2.0 properties we uprev them here.
+	 */
+	if (!IS_E_PROCESSOR(spridr))
+		fdt_fixup_crypto_node(blob, 0);
+	else if (IS_E_PROCESSOR(spridr) &&
+		 (SPR_FAMILY(spridr) == SPR_834X_FAMILY ||
+		  SPR_FAMILY(spridr) == SPR_836X_FAMILY) &&
+		 REVID_MAJOR(spridr) >= 2)
+		fdt_fixup_crypto_node(blob, 0x0204);
+
+#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
+    defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\
+    defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5)
+#ifdef CONFIG_ARCH_MPC8313
+	/*
+	* mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1
+	* h/w (see AN3545).  The base device tree in use has rev. 1 ID numbers,
+	* so if on Rev. 2 (and higher) h/w, we fix them up here
+	*/
+	if (REVID_MAJOR(immr->sysconf.spridr) >= 2) {
+		int nodeoffset, path;
+		const char *prop;
+
+		nodeoffset = fdt_path_offset(blob, "/aliases");
+		if (nodeoffset >= 0) {
+#if defined(CONFIG_HAS_ETH0)
+			prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
+			if (prop) {
+				u32 tmp[] = { 32, 0x8, 33, 0x8, 34, 0x8 };
+
+				path = fdt_path_offset(blob, prop);
+				prop = fdt_getprop(blob, path, "interrupts",
+						   NULL);
+				if (prop)
+					fdt_setprop(blob, path, "interrupts",
+						    &tmp, sizeof(tmp));
+			}
+#endif
+#if defined(CONFIG_HAS_ETH1)
+			prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
+			if (prop) {
+				u32 tmp[] = { 35, 0x8, 36, 0x8, 37, 0x8 };
+
+				path = fdt_path_offset(blob, prop);
+				prop = fdt_getprop(blob, path, "interrupts",
+						   NULL);
+				if (prop)
+					fdt_setprop(blob, path, "interrupts",
+						    &tmp, sizeof(tmp));
+			}
+#endif
+		}
+	}
+#endif
+#endif
+
+	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+		"timebase-frequency", (bd->bi_busfreq / 4), 1);
+	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+		"bus-frequency", bd->bi_busfreq, 1);
+	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+		"clock-frequency", gd->arch.core_clk, 1);
+	do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
+		"bus-frequency", bd->bi_busfreq, 1);
+	do_fixup_by_compat_u32(blob, "fsl,soc",
+		"bus-frequency", bd->bi_busfreq, 1);
+	do_fixup_by_compat_u32(blob, "fsl,soc",
+		"clock-frequency", bd->bi_busfreq, 1);
+	do_fixup_by_compat_u32(blob, "fsl,immr",
+		"bus-frequency", bd->bi_busfreq, 1);
+	do_fixup_by_compat_u32(blob, "fsl,immr",
+		"clock-frequency", bd->bi_busfreq, 1);
+#ifdef CONFIG_QE
+	ft_qe_setup(blob);
+#endif
+
+#ifdef CONFIG_SYS_NS16550
+        do_fixup_by_compat_u32(blob, "ns16550",
+                "clock-frequency", get_serial_clock(), 1);
+#endif
+
+	fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
+
+#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
+	(defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X))
+	fdt_fixup_muram (blob);
+#endif
+}
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/hid/Kconfig b/roms/u-boot/arch/powerpc/cpu/mpc83xx/hid/Kconfig
new file mode 100644
index 000000000..c367ad2ce
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/hid/Kconfig
@@ -0,0 +1,565 @@
+menu "HID setup"
+
+menu "HID0 initial"
+
+config HID0_INIT_EMCP
+	bool "Enable machine check int on mcp"
+
+config HID0_INIT_ECPE
+	bool "Enable cache parity errors"
+
+config HID0_INIT_EBA
+	bool "Enable address parity checking"
+
+config HID0_INIT_EBD
+	bool "Enable data parity checking"
+
+choice
+	prompt "HID0 clock configuration"
+
+config HID0_INIT_CLKOUT_OFF
+	bool "Clock output off"
+
+config HID0_INIT_CLKOUT_CORE_HALF
+	bool "Core clock / 2"
+
+config HID0_INIT_CLKOUT_CORE
+	bool "Core clock"
+
+config HID0_INIT_CLKOUT_BUS
+	bool "Bus clock"
+
+endchoice
+
+config HID0_INIT_PAR
+	bool "Disable precharge of artry_out"
+
+config HID0_INIT_DOZE
+	bool "Enable doze mode"
+
+config HID0_INIT_NAP
+	bool "Enable nap mode"
+
+config HID0_INIT_SLEEP
+	bool "Enable sleep mode"
+
+config HID0_INIT_DPM
+	bool "Enable dynamic power management"
+
+config HID0_INIT_ICE
+	bool "Enable instruction cache"
+
+config HID0_INIT_DCE
+	bool "Enable data cache"
+
+config HID0_INIT_ILOCK
+	bool "Lock instruction cache"
+
+config HID0_INIT_DLOCK
+	bool "Lock data cache"
+
+config HID0_INIT_ICFI
+	bool "Flash invalidate instruction cache"
+
+config HID0_INIT_DCFI
+	bool "Flash invalidate data cache"
+
+config HID0_INIT_IFEM
+	bool "Enable m bit on bus for instruction fetches"
+
+config HID0_INIT_DECAREN
+	bool "Decrementer auto reload"
+
+config HID0_INIT_FBIOB
+	bool "Force indirect branch on the bus"
+
+config HID0_INIT_ABE
+	bool "Enable address broadcast"
+
+config HID0_INIT_NOOPTI
+	bool "No-op data cache touch intructions"
+
+endmenu
+
+menu "HID0 final"
+
+config HID0_FINAL_EMCP
+	bool "Enable machine check int on mcp"
+
+config HID0_FINAL_ECPE
+	bool "Enable cache parity errors"
+
+config HID0_FINAL_EBA
+	bool "Enable address parity checking"
+
+config HID0_FINAL_EBD
+	bool "Enable data parity checking"
+
+choice
+	prompt "HID0 clock configuration"
+
+config HID0_FINAL_CLKOUT_OFF
+	bool "Clock output off"
+
+config HID0_FINAL_CLKOUT_CORE_HALF
+	bool "Core clock / 2"
+
+config HID0_FINAL_CLKOUT_CORE
+	bool "Core clock"
+
+config HID0_FINAL_CLKOUT_BUS
+	bool "Bus clock"
+
+endchoice
+
+config HID0_FINAL_PAR
+	bool "Disable precharge of artry_out"
+
+config HID0_FINAL_DOZE
+	bool "Enable doze mode"
+
+config HID0_FINAL_NAP
+	bool "Enable nap mode"
+
+config HID0_FINAL_SLEEP
+	bool "Enable sleep mode"
+
+config HID0_FINAL_DPM
+	bool "Enable dynamic power management"
+
+config HID0_FINAL_ICE
+	bool "Enable instruction cache"
+
+config HID0_FINAL_DCE
+	bool "Enable data cache"
+
+config HID0_FINAL_ILOCK
+	bool "Lock instruction cache"
+
+config HID0_FINAL_DLOCK
+	bool "Lock data cache"
+
+config HID0_FINAL_ICFI
+	bool "Flash invalidate instruction cache"
+
+config HID0_FINAL_DCFI
+	bool "Flash invalidate data cache"
+
+config HID0_FINAL_IFEM
+	bool "Enable m bit on bus for instruction fetches"
+
+config HID0_FINAL_DECAREN
+	bool "Decrementer auto reload"
+
+config HID0_FINAL_FBIOB
+	bool "Force indirect branch on the bus"
+
+config HID0_FINAL_ABE
+	bool "Enable address broadcast"
+
+config HID0_FINAL_NOOPTI
+	bool "No-op data cache touch intructions"
+
+endmenu
+
+config HID0_INIT_EMCP_BIT
+	hex
+	default 0x0 if !HID0_INIT_EMCP
+	default 0x80000000 if HID0_INIT_EMCP
+
+config HID0_INIT_ECPE_BIT
+	hex
+	default 0x0 if !HID0_INIT_ECPE
+	default 0x40000000 if HID0_INIT_ECPE
+
+config HID0_INIT_EBA_BIT
+	hex
+	default 0x0 if !HID0_INIT_EBA
+	default 0x20000000 if HID0_INIT_EBA
+
+config HID0_INIT_EBD_BIT
+	hex
+	default 0x0 if !HID0_INIT_EBD
+	default 0x10000000 if HID0_INIT_EBD
+
+config HID0_INIT_CLKOUT
+	hex
+	default 0x0 if HID0_INIT_CLKOUT_OFF
+	default 0x8000000 if HID0_INIT_CLKOUT_CORE_HALF
+	default 0x2000000 if HID0_INIT_CLKOUT_CORE
+	default 0xa000000 if HID0_INIT_CLKOUT_BUS
+
+config HID0_INIT_PAR_BIT
+	hex
+	default 0x0 if !HID0_INIT_PAR
+	default 0x1000000 if HID0_INIT_PAR
+
+config HID0_INIT_DOZE_BIT
+	hex
+	default 0x0 if !HID0_INIT_DOZE
+	default 0x800000 if HID0_INIT_DOZE
+
+config HID0_INIT_NAP_BIT
+	hex
+	default 0x0 if !HID0_INIT_NAP
+	default 0x400000 if HID0_INIT_NAP
+
+config HID0_INIT_SLEEP_BIT
+	hex
+	default 0x0 if !HID0_INIT_SLEEP
+	default 0x200000 if HID0_INIT_SLEEP
+
+config HID0_INIT_DPM_BIT
+	hex
+	default 0x0 if !HID0_INIT_DPM
+	default 0x100000 if HID0_INIT_DPM
+
+config HID0_INIT_ICE_BIT
+	hex
+	default 0x0 if !HID0_INIT_ICE
+	default 0x8000 if HID0_INIT_ICE
+
+config HID0_INIT_DCE_BIT
+	hex
+	default 0x0 if !HID0_INIT_DCE
+	default 0x4000 if HID0_INIT_DCE
+
+config HID0_INIT_ILOCK_BIT
+	hex
+	default 0x0 if !HID0_INIT_ILOCK
+	default 0x2000 if HID0_INIT_ILOCK
+
+config HID0_INIT_DLOCK_BIT
+	hex
+	default 0x0 if !HID0_INIT_DLOCK
+	default 0x1000 if HID0_INIT_DLOCK
+
+config HID0_INIT_ICFI_BIT
+	hex
+	default 0x0 if !HID0_INIT_ICFI
+	default 0x800 if HID0_INIT_ICFI
+
+config HID0_INIT_DCFI_BIT
+	hex
+	default 0x0 if !HID0_INIT_DCFI
+	default 0x400 if HID0_INIT_DCFI
+
+config HID0_INIT_IFEM_BIT
+	hex
+	default 0x0 if !HID0_INIT_IFEM
+	default 0x80 if HID0_INIT_IFEM
+
+config HID0_INIT_DECAREN_BIT
+	hex
+	default 0x0 if !HID0_INIT_DECAREN
+	default 0x40 if HID0_INIT_DECAREN
+
+config HID0_INIT_FBIOB_BIT
+	hex
+	default 0x0 if !HID0_INIT_FBIOB
+	default 0x10 if HID0_INIT_FBIOB
+
+config HID0_INIT_ABE_BIT
+	hex
+	default 0x0 if !HID0_INIT_ABE
+	default 0x8 if HID0_INIT_ABE
+
+config HID0_INIT_NOOPTI_BIT
+	hex
+	default 0x0 if !HID0_INIT_NOOPTI
+	default 0x1 if HID0_INIT_NOOPTI
+
+config HID0_FINAL_EMCP_BIT
+	hex
+	default 0x0 if !HID0_FINAL_EMCP
+	default 0x80000000 if HID0_FINAL_EMCP
+
+config HID0_FINAL_ECPE_BIT
+	hex
+	default 0x0 if !HID0_FINAL_ECPE
+	default 0x40000000 if HID0_FINAL_ECPE
+
+config HID0_FINAL_EBA_BIT
+	hex
+	default 0x0 if !HID0_FINAL_EBA
+	default 0x20000000 if HID0_FINAL_EBA
+
+config HID0_FINAL_EBD_BIT
+	hex
+	default 0x0 if !HID0_FINAL_EBD
+	default 0x10000000 if HID0_FINAL_EBD
+
+config HID0_FINAL_CLKOUT
+	hex
+	default 0x0 if HID0_FINAL_CLKOUT_OFF
+	default 0x8000000 if HID0_FINAL_CLKOUT_CORE_HALF
+	default 0x2000000 if HID0_FINAL_CLKOUT_CORE
+	default 0xa000000 if HID0_FINAL_CLKOUT_BUS
+
+config HID0_FINAL_SBCLK_BIT
+	hex
+	default 0x0 if !HID0_FINAL_SBCLK
+	default 0x8000000 if HID0_FINAL_SBCLK
+
+config HID0_FINAL_ECLK_BIT
+	hex
+	default 0x0 if !HID0_FINAL_ECLK
+	default 0x2000000 if HID0_FINAL_ECLK
+
+config HID0_FINAL_PAR_BIT
+	hex
+	default 0x0 if !HID0_FINAL_PAR
+	default 0x1000000 if HID0_FINAL_PAR
+
+config HID0_FINAL_DOZE_BIT
+	hex
+	default 0x0 if !HID0_FINAL_DOZE
+	default 0x800000 if HID0_FINAL_DOZE
+
+config HID0_FINAL_NAP_BIT
+	hex
+	default 0x0 if !HID0_FINAL_NAP
+	default 0x400000 if HID0_FINAL_NAP
+
+config HID0_FINAL_SLEEP_BIT
+	hex
+	default 0x0 if !HID0_FINAL_SLEEP
+	default 0x200000 if HID0_FINAL_SLEEP
+
+config HID0_FINAL_DPM_BIT
+	hex
+	default 0x0 if !HID0_FINAL_DPM
+	default 0x100000 if HID0_FINAL_DPM
+
+config HID0_FINAL_ICE_BIT
+	hex
+	default 0x0 if !HID0_FINAL_ICE
+	default 0x8000 if HID0_FINAL_ICE
+
+config HID0_FINAL_DCE_BIT
+	hex
+	default 0x0 if !HID0_FINAL_DCE
+	default 0x4000 if HID0_FINAL_DCE
+
+config HID0_FINAL_ILOCK_BIT
+	hex
+	default 0x0 if !HID0_FINAL_ILOCK
+	default 0x2000 if HID0_FINAL_ILOCK
+
+config HID0_FINAL_DLOCK_BIT
+	hex
+	default 0x0 if !HID0_FINAL_DLOCK
+	default 0x1000 if HID0_FINAL_DLOCK
+
+config HID0_FINAL_ICFI_BIT
+	hex
+	default 0x0 if !HID0_FINAL_ICFI
+	default 0x800 if HID0_FINAL_ICFI
+
+config HID0_FINAL_DCFI_BIT
+	hex
+	default 0x0 if !HID0_FINAL_DCFI
+	default 0x400 if HID0_FINAL_DCFI
+
+config HID0_FINAL_IFEM_BIT
+	hex
+	default 0x0 if !HID0_FINAL_IFEM
+	default 0x80 if HID0_FINAL_IFEM
+
+config HID0_FINAL_DECAREN_BIT
+	hex
+	default 0x0 if !HID0_FINAL_DECAREN
+	default 0x40 if HID0_FINAL_DECAREN
+
+config HID0_FINAL_FBIOB_BIT
+	hex
+	default 0x0 if !HID0_FINAL_FBIOB
+	default 0x10 if HID0_FINAL_FBIOB
+
+config HID0_FINAL_ABE_BIT
+	hex
+	default 0x0 if !HID0_FINAL_ABE
+	default 0x8 if HID0_FINAL_ABE
+
+config HID0_FINAL_NOOPTI_BIT
+	hex
+	default 0x0 if !HID0_FINAL_NOOPTI
+	default 0x1 if HID0_FINAL_NOOPTI
+
+menu "HID2"
+
+config HID2_LET
+	bool "True little-endian mode"
+
+config HID2_IFEB
+	bool "Instruction fetch burst extension"
+
+config HID2_MESISTATE
+	bool "MESI state enable"
+
+config HID2_IFEC
+	bool "Instruction fetch cancel extension"
+
+config HID2_EBQS
+	bool "BIU queue sharing"
+
+config HID2_EBPX
+	bool "BIU pipeline extension"
+
+if !ARCH_MPC8360
+
+config HID2_ELRW
+	bool "Weighted LRU"
+
+config HID2_NOKS
+	bool "No kill for snoop"
+
+endif
+
+config HID2_HBE
+	bool "High bat enable"
+
+choice
+	prompt "Instruction cache way-lock"
+
+config HID2_IWLCK_NONE
+	bool "No ways locked"
+
+config HID2_IWLCK_0
+	bool "Way 0 locked"
+
+config HID2_IWLCK_1
+	bool "Way 0 through 1 locked"
+
+config HID2_IWLCK_2
+	bool "Way 0 through 2 locked"
+
+if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+
+config HID2_IWLCK_3
+	bool "Way 0 through 3 locked"
+
+config HID2_IWLCK_4
+	bool "Way 0 through 4 locked"
+
+config HID2_IWLCK_5
+	bool "Way 0 through 5 locked"
+
+config HID2_IWLCK_6
+	bool "Way 0 through 6 locked"
+
+endif
+
+endchoice
+
+config HID2_ICWP
+	bool "Instruction cache way protection"
+
+choice
+	prompt "Data cache way-lock"
+
+config HID2_DWLCK_NONE
+	bool "No ways locked"
+
+config HID2_DWLCK_0
+	bool "Way 0 locked"
+
+config HID2_DWLCK_1
+	bool "Way 0 through 1 locked"
+
+config HID2_DWLCK_2
+	bool "Way 0 through 2 locked"
+
+if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+
+config HID2_DWLCK_3
+	bool "Way 0 through 3 locked"
+
+config HID2_DWLCK_4
+	bool "Way 0 through 4 locked"
+
+config HID2_DWLCK_5
+	bool "Way 0 through 5 locked"
+
+config HID2_DWLCK_6
+	bool "Way 0 through 6 locked"
+
+endif
+
+endchoice
+
+config HID2_LET_BIT
+	hex
+	default 0x0 if !HID2_LET
+	default 0x8000000 if HID2_LET
+
+config HID2_IFEB_BIT
+	hex
+	default 0x0 if !HID2_IFEB
+	default 0x4000000 if HID2_IFEB
+
+config HID2_MESISTATE_BIT
+	hex
+	default 0x0 if !HID2_MESISTATE
+	default 0x1000000 if HID2_MESISTATE
+
+config HID2_IFEC_BIT
+	hex
+	default 0x0 if !HID2_IFEC
+	default 0x800000 if HID2_IFEC
+
+config HID2_EBQS_BIT
+	hex
+	default 0x0 if !HID2_EBQS
+	default 0x400000 if HID2_EBQS
+
+config HID2_EBPX_BIT
+	hex
+	default 0x0 if !HID2_EBPX
+	default 0x200000 if HID2_EBPX
+
+config HID2_ELRW_BIT
+	hex
+	default 0x0 if !HID2_ELRW
+	default 0x100000 if HID2_ELRW
+
+config HID2_NOKS_BIT
+	hex
+	default 0x0 if !HID2_NOKS
+	default 0x80000 if HID2_NOKS
+
+config HID2_HBE_BIT
+	hex
+	default 0x0 if !HID2_HBE
+	default 0x40000 if HID2_HBE
+
+config HID2_IWLCK
+	hex
+	default 0x0 if HID2_IWLCK_NONE
+	default 0x2000 if HID2_IWLCK_0
+	default 0x4000 if HID2_IWLCK_1
+	default 0x6000 if HID2_IWLCK_2
+	default 0x8000 if HID2_IWLCK_3
+	default 0xA000 if HID2_IWLCK_4
+	default 0xC000 if HID2_IWLCK_5
+	default 0xE000 if HID2_IWLCK_6
+
+config HID2_ICWP_BIT
+	hex
+	default 0x0 if !HID2_ICWP
+	default 0x1000 if HID2_ICWP
+
+config HID2_DWLCK
+	hex
+	default 0x0 if HID2_DWLCK_NONE
+	default 0x20 if HID2_DWLCK_0
+	default 0x40 if HID2_DWLCK_1
+	default 0x60 if HID2_DWLCK_2
+	default 0x80 if HID2_DWLCK_3
+	default 0xA0 if HID2_DWLCK_4
+	default 0xC0 if HID2_DWLCK_5
+	default 0xE0 if HID2_DWLCK_6
+
+endmenu
+
+endmenu
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/hid/hid.h b/roms/u-boot/arch/powerpc/cpu/mpc83xx/hid/hid.h
new file mode 100644
index 000000000..9f5260c01
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/hid/hid.h
@@ -0,0 +1,72 @@
+#define CONFIG_SYS_HID0_FINAL ( \
+	CONFIG_HID0_FINAL_ABE_BIT |\
+	CONFIG_HID0_FINAL_CLKOUT |\
+	CONFIG_HID0_FINAL_DCE_BIT |\
+	CONFIG_HID0_FINAL_DCFI_BIT |\
+	CONFIG_HID0_FINAL_DECAREN_BIT |\
+	CONFIG_HID0_FINAL_DLOCK_BIT |\
+	CONFIG_HID0_FINAL_DOZE_BIT |\
+	CONFIG_HID0_FINAL_DPM_BIT |\
+	CONFIG_HID0_FINAL_EBA_BIT |\
+	CONFIG_HID0_FINAL_EBD_BIT |\
+	CONFIG_HID0_FINAL_ECLK_BIT |\
+	CONFIG_HID0_FINAL_ECPE_BIT |\
+	CONFIG_HID0_FINAL_EMCP_BIT |\
+	CONFIG_HID0_FINAL_FBIOB_BIT |\
+	CONFIG_HID0_FINAL_ICE_BIT |\
+	CONFIG_HID0_FINAL_ICFI_BIT |\
+	CONFIG_HID0_FINAL_IFEM_BIT |\
+	CONFIG_HID0_FINAL_ILOCK_BIT |\
+	CONFIG_HID0_FINAL_NAP_BIT |\
+	CONFIG_HID0_FINAL_NOOPTI_BIT |\
+	CONFIG_HID0_FINAL_PAR_BIT |\
+	CONFIG_HID0_FINAL_SBCLK_BIT |\
+	CONFIG_HID0_FINAL_SLEEP_BIT \
+)
+
+#define CONFIG_SYS_HID0_INIT ( \
+	CONFIG_HID0_INIT_ABE_BIT |\
+	CONFIG_HID0_INIT_CLKOUT |\
+	CONFIG_HID0_INIT_DCE_BIT |\
+	CONFIG_HID0_INIT_DCFI_BIT |\
+	CONFIG_HID0_INIT_DECAREN_BIT |\
+	CONFIG_HID0_INIT_DLOCK_BIT |\
+	CONFIG_HID0_INIT_DOZE_BIT |\
+	CONFIG_HID0_INIT_DPM_BIT |\
+	CONFIG_HID0_INIT_EBA_BIT |\
+	CONFIG_HID0_INIT_EBD_BIT |\
+	CONFIG_HID0_INIT_ECPE_BIT |\
+	CONFIG_HID0_INIT_EMCP_BIT |\
+	CONFIG_HID0_INIT_FBIOB_BIT |\
+	CONFIG_HID0_INIT_ICE_BIT |\
+	CONFIG_HID0_INIT_ICFI_BIT |\
+	CONFIG_HID0_INIT_IFEM_BIT |\
+	CONFIG_HID0_INIT_ILOCK_BIT |\
+	CONFIG_HID0_INIT_NAP_BIT |\
+	CONFIG_HID0_INIT_NOOPTI_BIT |\
+	CONFIG_HID0_INIT_PAR_BIT |\
+	CONFIG_HID0_INIT_SLEEP_BIT \
+)
+
+#ifdef CONFIG_TARGET_IDS8313
+/* IDS8313 defines a reserved bit; keep to not break compatibility */
+#define CONFIG_HID2_SPECIAL 0x00020000
+#else
+#define CONFIG_HID2_SPECIAL 0x0
+#endif
+
+#define CONFIG_SYS_HID2 ( \
+	CONFIG_HID2_LET_BIT |\
+	CONFIG_HID2_IFEB_BIT |\
+	CONFIG_HID2_MESISTATE_BIT |\
+	CONFIG_HID2_IFEC_BIT |\
+	CONFIG_HID2_EBQS_BIT |\
+	CONFIG_HID2_EBPX_BIT |\
+	CONFIG_HID2_ELRW_BIT |\
+	CONFIG_HID2_NOKS_BIT |\
+	CONFIG_HID2_HBE_BIT |\
+	CONFIG_HID2_IWLCK |\
+	CONFIG_HID2_ICWP_BIT |\
+	CONFIG_HID2_DWLCK |\
+	CONFIG_HID2_SPECIAL \
+)
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig b/roms/u-boot/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
new file mode 100644
index 000000000..c657a47b1
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
@@ -0,0 +1,816 @@
+menu "Reset Configuration Word"
+
+choice
+	prompt "Local bus memory controller clock mode"
+
+config LBMC_CLOCK_MODE_1_1
+	bool "1 : 1"
+
+config LBMC_CLOCK_MODE_1_2
+	depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
+	bool "1 : 2"
+
+endchoice
+
+choice
+	prompt "DDR SDRAM memory controller clock mode"
+
+config DDR_MC_CLOCK_MODE_1_2
+	bool "1 : 2"
+
+config DDR_MC_CLOCK_MODE_1_1
+	depends on ARCH_MPC8315 || ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
+	bool "1 : 1"
+
+endchoice
+
+if !ARCH_MPC8313 && !ARCH_MPC832X && !ARCH_MPC8349
+
+choice
+	prompt "System PLL VCO division"
+
+config SYSTEM_PLL_VCO_DIV_1
+	depends on !ARCH_MPC837X
+	bool "1"
+
+config SYSTEM_PLL_VCO_DIV_2
+	bool "2"
+
+config SYSTEM_PLL_VCO_DIV_4
+	depends on !ARCH_MPC831X
+	bool "4"
+
+config SYSTEM_PLL_VCO_DIV_8
+	depends on !ARCH_MPC831X
+	bool "8"
+
+endchoice
+
+endif
+
+choice
+	prompt "System PLL multiplication factor"
+
+config SYSTEM_PLL_FACTOR_2_1
+	bool "2 : 1"
+
+config SYSTEM_PLL_FACTOR_3_1
+	bool "3 : 1"
+
+config SYSTEM_PLL_FACTOR_4_1
+	bool "4 : 1"
+
+config SYSTEM_PLL_FACTOR_5_1
+	bool "5 : 1"
+
+config SYSTEM_PLL_FACTOR_6_1
+	bool "6 : 1"
+
+config SYSTEM_PLL_FACTOR_7_1
+	depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+	bool "7 : 1"
+
+config SYSTEM_PLL_FACTOR_8_1
+	depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+	bool "8 : 1"
+
+config SYSTEM_PLL_FACTOR_9_1
+	depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+	bool "9 : 1"
+
+config SYSTEM_PLL_FACTOR_10_1
+	depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+	bool "10 : 1"
+
+config SYSTEM_PLL_FACTOR_11_1
+	depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+	bool "11 : 1"
+
+config SYSTEM_PLL_FACTOR_12_1
+	depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+	bool "12 : 1"
+
+config SYSTEM_PLL_FACTOR_13_1
+	depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+	bool "13 : 1"
+
+config SYSTEM_PLL_FACTOR_14_1
+	depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+	bool "14 : 1"
+
+config SYSTEM_PLL_FACTOR_15_1
+	depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
+	bool "15 : 1"
+
+config SYSTEM_PLL_FACTOR_16_1
+	depends on ARCH_MPC8349 || ARCH_MPV8360
+	bool "16 : 1"
+
+endchoice
+
+config CORE_PLL_BYPASS
+	bool "Core PLL bypassed"
+
+if !CORE_PLL_BYPASS
+
+choice
+	prompt "Core PLL Ratio"
+
+config CORE_PLL_RATIO_1_1
+	bool "1 : 1"
+
+config CORE_PLL_RATIO_15_1
+	bool "1.5 : 1"
+
+config CORE_PLL_RATIO_2_1
+	bool "2 : 1"
+
+config CORE_PLL_RATIO_25_1
+	bool "2.5 : 1"
+
+config CORE_PLL_RATIO_3_1
+	bool "3 : 1"
+
+endchoice
+
+choice
+	prompt "Core PLL VCO Divider"
+
+config CORE_PLL_VCO_DIVIDER_2
+	bool "2"
+
+config CORE_PLL_VCO_DIVIDER_4
+	bool "4"
+
+config CORE_PLL_VCO_DIVIDER_8
+	depends on !ARCH_MPC8315
+	bool "8"
+
+endchoice
+
+endif
+
+if MPC83XX_QUICC_ENGINE
+
+choice
+	prompt "QUICC Engine PLL VCO Divider"
+
+config QUICC_VCO_DIVIDER_2
+	bool "2"
+
+config QUICC_VCO_DIVIDER_4
+	bool "4"
+
+config QUICC_VCO_DIVIDER_8
+	depends on ARCH_MPC8309
+	bool "8"
+
+endchoice
+
+choice
+	prompt "QUICC Engine PLL division factor"
+
+config QUICC_DIV_FACTOR_1
+	bool "1"
+
+config QUICC_DIV_FACTOR_2
+	bool "2"
+
+endchoice
+
+choice
+	prompt "QUICC Engine PLL multiplication factor"
+
+config QUICC_MULT_FACTOR_2
+	bool "2"
+
+config QUICC_MULT_FACTOR_3
+	bool "3"
+
+config QUICC_MULT_FACTOR_4
+	bool "4"
+
+config QUICC_MULT_FACTOR_5
+	bool "5"
+
+config QUICC_MULT_FACTOR_6
+	bool "6"
+
+config QUICC_MULT_FACTOR_7
+	bool "7"
+
+config QUICC_MULT_FACTOR_8
+	bool "8"
+
+config QUICC_MULT_FACTOR_9
+	depends on ARCH_MPC8360
+	bool "9"
+
+config QUICC_MULT_FACTOR_10
+	depends on ARCH_MPC8360
+	bool "10"
+
+config QUICC_MULT_FACTOR_11
+	depends on ARCH_MPC8360
+	bool "11"
+
+config QUICC_MULT_FACTOR_12
+	depends on ARCH_MPC8360
+	bool "12"
+
+config QUICC_MULT_FACTOR_13
+	depends on ARCH_MPC8360
+	bool "13"
+
+config QUICC_MULT_FACTOR_14
+	depends on ARCH_MPC8360
+	bool "14"
+
+config QUICC_MULT_FACTOR_15
+	depends on ARCH_MPC8360
+	bool "15"
+
+config QUICC_MULT_FACTOR_16
+	depends on ARCH_MPC8360
+	bool "16"
+
+config QUICC_MULT_FACTOR_17
+	depends on ARCH_MPC8360
+	bool "17"
+
+config QUICC_MULT_FACTOR_18
+	depends on ARCH_MPC8360
+	bool "18"
+
+config QUICC_MULT_FACTOR_19
+	depends on ARCH_MPC8360
+	bool "19"
+
+config QUICC_MULT_FACTOR_20
+	depends on ARCH_MPC8360
+	bool "20"
+
+config QUICC_MULT_FACTOR_21
+	depends on ARCH_MPC8360
+	bool "21"
+
+config QUICC_MULT_FACTOR_22
+	depends on ARCH_MPC8360
+	bool "22"
+
+config QUICC_MULT_FACTOR_23
+	depends on ARCH_MPC8360
+	bool "23"
+
+config QUICC_MULT_FACTOR_24
+	depends on ARCH_MPC8360
+	bool "24"
+
+config QUICC_MULT_FACTOR_25
+	depends on ARCH_MPC8360
+	bool "25"
+
+config QUICC_MULT_FACTOR_26
+	depends on ARCH_MPC8360
+	bool "26"
+
+config QUICC_MULT_FACTOR_27
+	depends on ARCH_MPC8360
+	bool "27"
+
+config QUICC_MULT_FACTOR_28
+	depends on ARCH_MPC8360
+	bool "28"
+
+config QUICC_MULT_FACTOR_29
+	depends on ARCH_MPC8360
+	bool "29"
+
+config QUICC_MULT_FACTOR_30
+	depends on ARCH_MPC8360
+	bool "30"
+
+config QUICC_MULT_FACTOR_31
+	depends on ARCH_MPC8360
+	bool "31"
+
+endchoice
+
+endif
+
+if MPC83XX_PCI_SUPPORT
+
+choice
+	prompt "PCI host mode"
+
+config PCI_HOST_MODE_DISABLE
+	bool "Disabled"
+
+config PCI_HOST_MODE_ENABLE
+	bool "Enabled"
+
+endchoice
+
+if ARCH_MPC8349
+
+choice
+	prompt "PCI 64-bit mode"
+
+config PCI_64BIT_MODE_DISABLE
+	bool "Disabled"
+
+config PCI_64BIT_MODE_ENABLE
+	bool "Enabled"
+
+endchoice
+
+endif
+
+choice
+	prompt "PCI internal arbiter 1 mode"
+
+config PCI_INT_ARBITER1_DISABLE
+	bool "Disabled"
+
+config PCI_INT_ARBITER1_ENABLE
+	bool "Enabled"
+
+endchoice
+
+if ARCH_MPC8349
+
+choice
+	prompt "PCI internal arbiter 2 mode"
+
+config PCI_INT_ARBITER2_DISABLE
+	bool "Disabled"
+
+config PCI_INT_ARBITER2_ENABLE
+	bool "Enabled"
+
+endchoice
+
+endif
+
+if ARCH_MPC8360
+
+choice
+	prompt "PCI clock output drive"
+
+config PCI_CLOCK_OUTPUT_DRIVE_DISABLE
+	bool "Disabled"
+
+config PCI_CLOCK_OUTPUT_DRIVE_ENABLE
+	bool "Enabled"
+
+endchoice
+
+endif
+
+endif
+
+choice
+	prompt "Core disable mode"
+
+config CORE_DISABLE_MODE_OFF
+	bool "Off"
+
+config CORE_DISABLE_MODE_ON
+	bool "On"
+
+endchoice
+
+choice
+	prompt "Boot Memory Space"
+
+config BOOT_MEMORY_SPACE_HIGH
+	bool "High"
+
+config BOOT_MEMORY_SPACE_LOW
+	bool "Low"
+
+endchoice
+
+choice
+	prompt "Boot Sequencer Configuration"
+
+config BOOT_SEQUENCER_DISABLED
+	bool "Disabled"
+
+config BOOT_SEQUENCER_NORMAL_I2C
+	bool "Normal I2C"
+
+config BOOT_SEQUENCER_EXTENDED_I2C
+	bool "Extended I2C"
+
+endchoice
+
+choice
+	prompt "Software Watchdog"
+
+config SOFTWARE_WATCHDOG_DISABLED
+	bool "Disabled"
+
+config SOFTWARE_WATCHDOG_ENABLED
+	bool "Enabled"
+
+endchoice
+
+choice
+	prompt "Boot ROM interface location"
+
+config BOOT_ROM_INTERFACE_DDR_SDRAM
+	bool "DDR_SDRAM"
+
+config BOOT_ROM_INTERFACE_PCI1
+	depends on MPC83XX_PCI_SUPPORT
+	bool "PCI1"
+
+config BOOT_ROM_INTERFACE_PCI2
+	depends on MPC83XX_PCI_SUPPORT && ARCH_MPC8349
+	bool "PCI2"
+
+config BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
+	depends on ARCH_MPC837X
+	bool "PCI2"
+
+config BOOT_ROM_INTERFACE_ESDHC
+	depends on ARCH_MPC8309
+	bool "eSDHC"
+
+config BOOT_ROM_INTERFACE_SPI
+	depends on ARCH_MPC8309
+	bool "SPI"
+
+config BOOT_ROM_INTERFACE_GPCM_8BIT
+	bool "Local bus GPCM - 8-bit ROM"
+
+config BOOT_ROM_INTERFACE_GPCM_16BIT
+	bool "Local bus GPCM - 16-bit ROM"
+
+config BOOT_ROM_INTERFACE_GPCM_32BIT
+	depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
+	bool "Local bus GPCM - 32-bit ROM"
+
+config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL
+	depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+	bool "Local bus NAND Flash- 8-bit small page ROM"
+
+config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE
+	depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+	bool "Local bus NAND Flash- 8-bit large page ROM"
+
+endchoice
+
+if MPC83XX_TSEC1_SUPPORT
+
+choice
+	prompt "TSEC1 mode"
+
+config TSEC1_MODE_MII
+	depends on !ARCH_MPC8349
+	bool "MII"
+
+config TSEC1_MODE_RMII
+	depends on ARCH_MPC831X && !ARCH_MPC8349
+	bool "RMII"
+
+config TSEC1_MODE_RGMII
+	bool "RGMII"
+
+config TSEC1_MODE_RTBI
+	depends on ARCH_MPC831X || ARCH_MPC837X
+	bool "RTBI"
+
+config TSEC1_MODE_GMII
+	depends on ARCH_MPC8349
+	bool "GMII"
+
+config TSEC1_MODE_TBI
+	depends on ARCH_MPC8349
+	bool "TBI"
+
+config TSEC1_MODE_SGMII
+	depends on ARCH_MPC831X || ARCH_MPC837X
+	bool "SGMII"
+
+endchoice
+
+endif
+
+if MPC83XX_TSEC2_SUPPORT
+
+choice
+	prompt "TSEC2 mode"
+
+config TSEC2_MODE_MII
+	depends on !ARCH_MPC8349
+	bool "MII"
+
+config TSEC2_MODE_RMII
+	depends on ARCH_MPC831X && !ARCH_MPC8349
+	bool "RMII"
+
+config TSEC2_MODE_RGMII
+	bool "RGMII"
+
+config TSEC2_MODE_RTBI
+	depends on ARCH_MPC831X || ARCH_MPC837X
+	bool "RTBI"
+
+config TSEC2_MODE_GMII
+	depends on ARCH_MPC8349
+	bool "GMII"
+
+config TSEC2_MODE_TBI
+	depends on ARCH_MPC8349
+	bool "TBI"
+
+config TSEC2_MODE_SGMII
+	depends on ARCH_MPC831X || ARCH_MPC837X
+	bool "SGMII"
+
+endchoice
+
+endif
+
+choice
+	prompt "True litle-endian mode"
+
+config TRUE_LITTLE_ENDIAN_BIG_ENDIAN
+	bool "Big-endian"
+
+config TRUE_LITTLE_ENDIAN_LITTLE_ENDIAN
+	bool "Little-endian"
+
+endchoice
+
+if ARCH_MPC8360
+
+choice
+	prompt "Secondary DDR IO"
+
+config SECONDARY_DDR_IO_DISABLE
+	bool "Disable"
+
+config SECONDARY_DDR_IO_ENABLE
+	bool "Enable"
+
+endchoice
+
+endif
+
+if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8349 || ARCH_MPC8360
+
+choice
+	prompt "LALE timing"
+
+config LALE_TIMING_NORMAL
+	bool "Normal"
+
+config LALE_TIMING_EARLIER
+	bool "Earlier"
+
+endchoice
+
+endif
+
+if MPC83XX_LDP_PIN
+
+choice
+	prompt "LDP pin mux state"
+
+config LDP_PIN_MUX_STATE_1
+	bool "Inital value 1"
+
+config LDP_PIN_MUX_STATE_0
+	bool "Inital value 0"
+
+endchoice
+
+endif
+
+endmenu
+
+config LBMC_CLOCK_MODE
+	int
+	default 0 if LBMC_CLOCK_MODE_1_1
+	default 1 if LBMC_CLOCK_MODE_1_2
+
+config DDR_MC_CLOCK_MODE
+	int
+	default 1 if DDR_MC_CLOCK_MODE_1_2
+	default 0 if DDR_MC_CLOCK_MODE_1_1
+
+config SYSTEM_PLL_VCO_DIV
+	int
+	default 0 if ARCH_MPC8349 || ARCH_MPC832X
+	default 2 if ARCH_MPC8313
+	default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X
+	default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X
+	default 2 if SYSTEM_PLL_VCO_DIV_8 && !ARCH_MPC8360 && !ARCH_MPC837X
+	default 0 if SYSTEM_PLL_VCO_DIV_4 && (ARCH_MPC8360 || ARCH_MPC837X)
+	default 1 if SYSTEM_PLL_VCO_DIV_8 && (ARCH_MPC8360 || ARCH_MPC837X)
+	default 2 if SYSTEM_PLL_VCO_DIV_2 && (ARCH_MPC8360 || ARCH_MPC837X)
+	default 3 if SYSTEM_PLL_VCO_DIV_1
+
+config SYSTEM_PLL_FACTOR
+	int
+	default 2 if SYSTEM_PLL_FACTOR_2_1
+	default 3 if SYSTEM_PLL_FACTOR_3_1
+	default 4 if SYSTEM_PLL_FACTOR_4_1
+	default 5 if SYSTEM_PLL_FACTOR_5_1
+	default 6 if SYSTEM_PLL_FACTOR_6_1
+	default 7 if SYSTEM_PLL_FACTOR_7_1
+	default 8 if SYSTEM_PLL_FACTOR_8_1
+	default 9 if SYSTEM_PLL_FACTOR_9_1
+	default 10 if SYSTEM_PLL_FACTOR_10_1
+	default 11 if SYSTEM_PLL_FACTOR_11_1
+	default 12 if SYSTEM_PLL_FACTOR_12_1
+	default 13 if SYSTEM_PLL_FACTOR_13_1
+	default 14 if SYSTEM_PLL_FACTOR_14_1
+	default 15 if SYSTEM_PLL_FACTOR_15_1
+	default 0 if SYSTEM_PLL_FACTOR_16_1
+
+config CORE_PLL_RATIO
+	hex
+	default 0x0 if CORE_PLL_BYPASS
+	default 0x02 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_2
+	default 0x22 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_4
+	default 0x42 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_8
+	default 0x03 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_2
+	default 0x23 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_4
+	default 0x43 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_8
+	default 0x04 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_2
+	default 0x24 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_4
+	default 0x44 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_8
+	default 0x05 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_2
+	default 0x25 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_4
+	default 0x45 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_8
+	default 0x06 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_2
+	default 0x26 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_4
+	default 0x46 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_8
+
+config CORE_DISABLE_MODE
+	int
+	default 0 if CORE_DISABLE_MODE_OFF
+	default 1 if CORE_DISABLE_MODE_ON
+
+config BOOT_MEMORY_SPACE
+	int
+	default 0 if BOOT_MEMORY_SPACE_LOW
+	default 1 if BOOT_MEMORY_SPACE_HIGH
+
+config BOOT_SEQUENCER
+	int
+	default 0 if BOOT_SEQUENCER_DISABLED
+	default 1 if BOOT_SEQUENCER_NORMAL_I2C
+	default 2 if BOOT_SEQUENCER_EXTENDED_I2C
+
+config SOFTWARE_WATCHDOG
+	int
+	default 0 if SOFTWARE_WATCHDOG_DISABLED
+	default 1 if SOFTWARE_WATCHDOG_ENABLED
+
+config BOOT_ROM_INTERFACE
+	hex
+	default 0x0 if BOOT_ROM_INTERFACE_DDR_SDRAM
+	default 0x4 if BOOT_ROM_INTERFACE_PCI1
+	default 0x8 if BOOT_ROM_INTERFACE_PCI2
+	default 0x8 if BOOT_ROM_INTERFACE_ESDHC
+	default 0xc if BOOT_ROM_INTERFACE_SPI
+	default 0xc if BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
+	default 0x14 if BOOT_ROM_INTERFACE_GPCM_8BIT
+	default 0x18 if BOOT_ROM_INTERFACE_GPCM_16BIT
+	default 0x1c if BOOT_ROM_INTERFACE_GPCM_32BIT
+	default 0x5 if BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL
+	default 0x15 if BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE
+
+config TSEC1_MODE
+	hex
+	default 0x0 if !MPC83XX_TSEC1_SUPPORT
+	default 0x0 if TSEC1_MODE_MII
+	default 0x1 if TSEC1_MODE_RMII
+	default 0x3 if TSEC1_MODE_RGMII && !ARCH_MPC8349
+	default 0x5 if TSEC1_MODE_RTBI && !ARCH_MPC8349
+	default 0x6 if TSEC1_MODE_SGMII
+	default 0x0 if TSEC1_MODE_RGMII && ARCH_MPC8349
+	default 0x1 if TSEC1_MODE_RTBI && ARCH_MPC8349
+	default 0x2 if TSEC1_MODE_GMII
+	default 0x3 if TSEC1_MODE_TBI
+
+config TSEC2_MODE
+	hex
+	default 0x0 if !MPC83XX_TSEC2_SUPPORT
+	default 0x0 if TSEC2_MODE_MII
+	default 0x1 if TSEC2_MODE_RMII
+	default 0x3 if TSEC2_MODE_RGMII && !ARCH_MPC8349
+	default 0x5 if TSEC2_MODE_RTBI && !ARCH_MPC8349
+	default 0x6 if TSEC2_MODE_SGMII
+	default 0x0 if TSEC2_MODE_RGMII && ARCH_MPC8349
+	default 0x1 if TSEC2_MODE_RTBI && ARCH_MPC8349
+	default 0x2 if TSEC2_MODE_GMII
+	default 0x3 if TSEC2_MODE_TBI
+
+config SECONDARY_DDR_IO
+	int
+	default 0 if !ARCH_MPC8360
+	default 0 if SECONDARY_DDR_IO_DISABLE
+	default 1 if SECONDARY_DDR_IO_ENABLE
+
+config TRUE_LITTLE_ENDIAN
+	int
+	default 0 if TRUE_LITTLE_ENDIAN_BIG_ENDIAN
+	default 1 if TRUE_LITTLE_ENDIAN_LITTLE_ENDIAN
+
+config LALE_TIMING
+	int
+	default 0 if ARCH_MPC830X || ARCH_MPC837X
+	default 0 if LALE_TIMING_NORMAL
+	default 1 if LALE_TIMING_EARLIER
+
+config LDP_PIN_MUX_STATE
+	int
+	default 0 if !MPC83XX_LDP_PIN
+	default 0 if LDP_PIN_MUX_STATE_1
+	default 1 if LDP_PIN_MUX_STATE_0
+
+config QUICC_VCO_DIVIDER
+	int
+	default 0 if !MPC83XX_QUICC_ENGINE
+	default 0 if QUICC_VCO_DIVIDER_2 && ARCH_MPC8309
+	default 1 if QUICC_VCO_DIVIDER_4 && ARCH_MPC8309
+	default 2 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8309
+	default 2 if QUICC_VCO_DIVIDER_2 && (ARCH_MPC832X || ARCH_MPC8360)
+	default 0 if QUICC_VCO_DIVIDER_4 && (ARCH_MPC832X || ARCH_MPC8360)
+	default 1 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8360
+
+config QUICC_DIV_FACTOR
+	int
+	default 0 if !MPC83XX_QUICC_ENGINE
+	default 0 if QUICC_DIV_FACTOR_1
+	default 1 if QUICC_DIV_FACTOR_2
+
+config QUICC_MULT_FACTOR
+	int
+	default 0 if !MPC83XX_QUICC_ENGINE
+	default 2 if QUICC_MULT_FACTOR_2
+	default 3 if QUICC_MULT_FACTOR_3
+	default 4 if QUICC_MULT_FACTOR_4
+	default 5 if QUICC_MULT_FACTOR_5
+	default 6 if QUICC_MULT_FACTOR_6
+	default 7 if QUICC_MULT_FACTOR_7
+	default 8 if QUICC_MULT_FACTOR_8
+	default 9 if QUICC_MULT_FACTOR_9
+	default 10 if QUICC_MULT_FACTOR_10
+	default 11 if QUICC_MULT_FACTOR_11
+	default 12 if QUICC_MULT_FACTOR_12
+	default 13 if QUICC_MULT_FACTOR_13
+	default 14 if QUICC_MULT_FACTOR_14
+	default 15 if QUICC_MULT_FACTOR_15
+	default 16 if QUICC_MULT_FACTOR_16
+	default 17 if QUICC_MULT_FACTOR_17
+	default 18 if QUICC_MULT_FACTOR_18
+	default 19 if QUICC_MULT_FACTOR_19
+	default 20 if QUICC_MULT_FACTOR_20
+	default 21 if QUICC_MULT_FACTOR_21
+	default 22 if QUICC_MULT_FACTOR_22
+	default 23 if QUICC_MULT_FACTOR_23
+	default 24 if QUICC_MULT_FACTOR_24
+	default 25 if QUICC_MULT_FACTOR_25
+	default 26 if QUICC_MULT_FACTOR_26
+	default 27 if QUICC_MULT_FACTOR_27
+	default 28 if QUICC_MULT_FACTOR_28
+	default 29 if QUICC_MULT_FACTOR_29
+	default 30 if QUICC_MULT_FACTOR_30
+	default 31 if QUICC_MULT_FACTOR_31
+
+config PCI_HOST_MODE
+	int
+	default 0 if !MPC83XX_PCI_SUPPORT && !ARCH_MPC8308
+	default 0 if PCI_HOST_MODE_DISABLE
+	default 1 if PCI_HOST_MODE_ENABLE || ARCH_MPC8308 # MPC8308 needs this bit set regardless
+
+config PCI_64BIT_MODE
+	int
+	default 0 if !ARCH_MPC8349
+	default 0 if PCI_64BIT_MODE_DISABLE
+	default 1 if PCI_64BIT_MODE_ENABLE
+
+config PCI_INT_ARBITER1
+	int
+	default 0 if !MPC83XX_PCI_SUPPORT && !ARCH_MPC8308
+	default 0 if PCI_INT_ARBITER1_DISABLE
+	default 1 if PCI_INT_ARBITER1_ENABLE || ARCH_MPC8308 # MPC8308 needs this bit set regardless
+
+config PCI_INT_ARBITER2
+	int
+	default 0 if !ARCH_MPC8349
+	default 0 if PCI_INT_ARBITER2_DISABLE
+	default 1 if PCI_INT_ARBITER2_ENABLE
+
+config PCI_CLOCK_OUTPUT_DRIVE
+	int
+	default 0 if !ARCH_MPC8360
+	default 0 if PCI_CLOCK_OUTPUT_DRIVE_DISABLE
+	default 1 if PCI_CLOCK_OUTPUT_DRIVE_ENABLE
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h b/roms/u-boot/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h
new file mode 100644
index 000000000..7d66ba726
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h
@@ -0,0 +1,37 @@
+#ifdef CONFIG_ARCH_MPC8349
+#define TSEC1_MODE_SHIFT 17
+#define TSEC2_MODE_SHIFT 19
+#else
+#define TSEC1_MODE_SHIFT 18
+#define TSEC2_MODE_SHIFT 21
+#endif
+
+#define CONFIG_SYS_HRCW_LOW (\
+	(CONFIG_LBMC_CLOCK_MODE << (31 - 0)) |\
+	(CONFIG_DDR_MC_CLOCK_MODE << (31 - 1)) |\
+	(CONFIG_SYSTEM_PLL_VCO_DIV << (31 - 3)) |\
+	(CONFIG_SYSTEM_PLL_FACTOR << (31 - 7)) |\
+	(CONFIG_CORE_PLL_RATIO << (31 - 15)) |\
+	(CONFIG_QUICC_VCO_DIVIDER << (31 - 25)) |\
+	(CONFIG_QUICC_DIV_FACTOR << (31 - 26)) |\
+	(CONFIG_QUICC_MULT_FACTOR << (31 - 31)) \
+	)
+
+#define CONFIG_SYS_HRCW_HIGH (\
+	(CONFIG_PCI_HOST_MODE << (31 - 0)) |\
+	(CONFIG_PCI_64BIT_MODE << (31 - 1)) |\
+	(CONFIG_PCI_INT_ARBITER1 << (31 - 2)) |\
+	(CONFIG_PCI_INT_ARBITER2 << (31 - 3)) |\
+	(CONFIG_PCI_CLOCK_OUTPUT_DRIVE << (31 - 3)) |\
+	(CONFIG_CORE_DISABLE_MODE << (31 - 4)) |\
+	(CONFIG_BOOT_MEMORY_SPACE << (31 - 5)) |\
+	(CONFIG_BOOT_SEQUENCER << (31 - 7)) |\
+	(CONFIG_SOFTWARE_WATCHDOG << (31 - 8)) |\
+	(CONFIG_BOOT_ROM_INTERFACE << (31 - 13)) |\
+	(CONFIG_TSEC1_MODE << (31 - TSEC1_MODE_SHIFT)) |\
+	(CONFIG_TSEC2_MODE << (31 - TSEC2_MODE_SHIFT)) |\
+	(CONFIG_SECONDARY_DDR_IO << (31 - 27)) |\
+	(CONFIG_TRUE_LITTLE_ENDIAN << (31 - 28)) |\
+	(CONFIG_LALE_TIMING << (31 - 29)) |\
+	(CONFIG_LDP_PIN_MUX_STATE << (31 - 30)) \
+	)
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/initreg/Kconfig b/roms/u-boot/arch/powerpc/cpu/mpc83xx/initreg/Kconfig
new file mode 100644
index 000000000..a6b42a29a
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/initreg/Kconfig
@@ -0,0 +1,6 @@
+menu "Initial register configuration"
+
+source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr"
+source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr"
+
+endmenu
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr b/roms/u-boot/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr
new file mode 100644
index 000000000..e6b6130de
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr
@@ -0,0 +1,139 @@
+menu "LCRR - Clock Ratio Register register"
+
+if !ARCH_MPC8309 && !ARCH_MPC831X && !ARCH_MPC832X
+
+choice
+	prompt "DLL bypass"
+
+config LCRR_DBYP_UNSET
+	bool "Don't set value"
+
+config LCRR_DBYP_PLL_ENABLED
+	bool "PLL enabled"
+
+config LCRR_DBYP_PLL_BYPASSED
+	bool "PLL bypassed"
+
+endchoice
+
+endif
+
+if ARCH_MPC834X || ARCH_MPC8360
+
+choice
+	prompt "Additional delay cycles for SDRAM control signals"
+
+config LCRR_BUFCMDC_UNSET
+	bool "Don't set value"
+
+config LCRR_BUFCMDC_4
+	bool "4"
+
+config LCRR_BUFCMDC_1
+	bool "1"
+
+config LCRR_BUFCMDC_2
+	bool "2"
+
+config LCRR_BUFCMDC_3
+	bool "3"
+
+endchoice
+
+choice
+	prompt "Extended CAS latency"
+
+config LCRR_ECL_UNSET
+	bool "Don't set value"
+
+config LCRR_ECL_4
+	bool "4"
+
+config LCRR_ECL_5
+	bool "5"
+
+config LCRR_ECL_6
+	bool "6"
+
+config LCRR_ECL_7
+	bool "7"
+
+endchoice
+
+endif # ARCH_MPC834X || ARCH_MPC8360
+
+if !ARCH_MPC8308
+
+choice
+	prompt "External address delay cycles"
+
+config LCRR_EADC_UNSET
+	bool "Don't set value"
+
+config LCRR_EADC_4
+	bool "4"
+
+config LCRR_EADC_1
+	bool "1"
+
+config LCRR_EADC_2
+	bool "2"
+
+config LCRR_EADC_3
+	bool "3"
+
+endchoice
+
+endif # !ARCH_MPC8308
+
+choice
+	prompt "System clock divider"
+
+config LCRR_CLKDIV_UNSET
+	bool "Don't set value"
+
+config LCRR_CLKDIV_2
+	bool "2"
+
+config LCRR_CLKDIV_4
+	bool "4"
+
+config LCRR_CLKDIV_8
+	bool "8"
+
+endchoice
+
+config LCRR_DBYP
+	hex
+	default 0x0 if LCRR_DBYP_UNSET || LCRR_DBYP_PLL_ENABLED
+	default 0x80000000 if LCRR_DBYP_PLL_BYPASSED
+
+config LCRR_BUFCMDC
+	hex
+	default 0x0 if LCRR_BUFCMDC_4 || LCRR_BUFCMDC_UNSET
+	default 0x10000000 if LCRR_BUFCMDC_1
+	default 0x20000000 if LCRR_BUFCMDC_2
+	default 0x30000000 if LCRR_BUFCMDC_3
+
+config LCRR_ECL
+	hex
+	default 0x0 if LCRR_ECL_4 || LCRR_ECL_UNSET
+	default 0x1000000 if LCRR_ECL_5
+	default 0x2000000 if LCRR_ECL_6
+	default 0x3000000 if LCRR_ECL_7
+
+config LCRR_EADC
+	hex
+	default 0x0 if LCRR_EADC_4 || LCRR_EADC_UNSET
+	default 0x10000 if LCRR_EADC_1
+	default 0x20000 if LCRR_EADC_2
+	default 0x30000 if LCRR_EADC_3
+
+config LCRR_CLKDIV
+	hex
+	default 0x0 if LCRR_CLKDIV_UNSET
+	default 0x2 if LCRR_CLKDIV_2
+	default 0x4 if LCRR_CLKDIV_4
+	default 0x8 if LCRR_CLKDIV_8
+
+endmenu
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr b/roms/u-boot/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr
new file mode 100644
index 000000000..f32309e6c
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr
@@ -0,0 +1,115 @@
+menu "SPCR - System priority and configuration register"
+
+choice
+	prompt "Optimize"
+
+config SPCR_OPT_UNSET
+	bool "Don't set value"
+
+config SPCR_OPT_NONE
+	bool "No performance enhancement"
+
+config SPCR_OPT_SPEC_READ
+	bool "Performance enhancement by speculative read"
+
+endchoice
+
+if ARCH_MPC8308 || ARCH_MPC831X || ARCH_MPC837X
+
+choice
+	prompt "TSEC emergency priority"
+
+config SPCR_TSECEP_UNSET
+	bool "Don't set value"
+
+config SPCR_TSECEP_0
+	bool "Level 0 (lowest priority)"
+
+config SPCR_TSECEP_1
+	bool "Level 1"
+
+config SPCR_TSECEP_2
+	bool "Level 2"
+
+config SPCR_TSECEP_3
+	bool "Level 3 (highest priority)"
+
+endchoice
+
+endif
+
+if ARCH_MPC8349
+
+choice
+	prompt "TSEC1 emergency priority"
+
+config SPCR_TSEC1EP_UNSET
+	bool "Don't set value"
+
+config SPCR_TSEC1EP_0
+	bool "Level 0 (lowest priority)"
+
+config SPCR_TSEC1EP_1
+	bool "Level 1"
+
+config SPCR_TSEC1EP_2
+	bool "Level 2"
+
+config SPCR_TSEC1EP_3
+	bool "Level 3 (highest priority)"
+
+endchoice
+
+choice
+	prompt "TSEC2 emergency priority"
+
+config SPCR_TSEC2EP_UNSET
+	bool "Don't set value"
+
+config SPCR_TSEC2EP_0
+	bool "Level 0 (lowest priority)"
+
+config SPCR_TSEC2EP_1
+	bool "Level 1"
+
+config SPCR_TSEC2EP_2
+	bool "Level 2"
+
+config SPCR_TSEC2EP_3
+	bool "Level 3 (highest priority)"
+
+endchoice
+
+endif
+
+config SPCR_OPT
+	hex
+	default 0x0 if SPCR_OPT_UNSET
+	default 0x0 if SPCR_OPT_NONE
+	default 0x800000 if SPCR_OPT_SPEC_READ
+
+config SPCR_TSECEP
+	hex
+	default 0x0 if SPCR_TSECEP_UNSET
+	default 0x0 if SPCR_TSECEP_0
+	default 0x100 if SPCR_TSECEP_1
+	default 0x200 if SPCR_TSECEP_2
+	default 0x300 if SPCR_TSECEP_3
+
+config SPCR_TSEC1EP
+	hex
+	default 0x0 if SPCR_TSEC1EP_UNSET
+	default 0x0 if SPCR_TSEC1EP_0
+	default 0x100 if SPCR_TSEC1EP_1
+	default 0x200 if SPCR_TSEC1EP_2
+	default 0x300 if SPCR_TSEC1EP_3
+
+config SPCR_TSEC2EP
+	hex
+	default 0x0 if SPCR_TSEC2EP_UNSET
+	default 0x0 if SPCR_TSEC2EP_0
+	default 0x1 if SPCR_TSEC2EP_1
+	default 0x2 if SPCR_TSEC2EP_2
+	default 0x3 if SPCR_TSEC2EP_3
+
+endmenu
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/initreg/initreg.h b/roms/u-boot/arch/powerpc/cpu/mpc83xx/initreg/initreg.h
new file mode 100644
index 000000000..63aa5c946
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/initreg/initreg.h
@@ -0,0 +1,79 @@
+#define SPCR_PCIHPE_MASK	0x10000000
+#define SPCR_PCIPR_MASK		0x03000000
+#define SPCR_OPT_MASK		0x00800000
+#define SPCR_TBEN_MASK		0x00400000
+#define SPCR_COREPR_MASK	0x00300000
+#define SPCR_TSEC1DP_MASK	0x00003000
+#define SPCR_TSEC1BDP_MASK	0x00000C00
+#define SPCR_TSEC1EP_MASK	0x00000300
+#define SPCR_TSEC2DP_MASK	0x00000030
+#define SPCR_TSEC2BDP_MASK	0x0000000C
+#define SPCR_TSEC2EP_MASK	0x00000003
+#define SPCR_TSECDP_MASK	0x00003000
+#define SPCR_TSECBDP_MASK	0x00000C00
+#define SPCR_TSECEP_MASK	0x00000300
+
+	const __be32 spcr_mask =
+#if defined(CONFIG_SPCR_OPT) && !defined(CONFIG_SPCR_OPT_UNSET)
+		SPCR_OPT_MASK |
+#endif
+#if defined(CONFIG_SPCR_TSECEP) && !defined(CONFIG_SPCR_TSECEP_UNSET)
+		SPCR_TSECEP_MASK |
+#endif
+#if defined(CONFIG_SPCR_TSEC1EP) && !defined(CONFIG_SPCR_TSEC1EP_UNSET)
+		SPCR_TSEC1EP_MASK |
+#endif
+#if defined(CONFIG_SPCR_TSEC2EP) && !defined(CONFIG_SPCR_TSEC2EP_UNSET)
+		SPCR_TSEC2EP_MASK |
+#endif
+		0;
+	const __be32 spcr_val =
+#if defined(CONFIG_SPCR_OPT) && !defined(CONFIG_SPCR_OPT_UNSET)
+		CONFIG_SPCR_OPT |
+#endif
+#if defined(CONFIG_SPCR_TSECEP) && !defined(CONFIG_SPCR_TSECEP_UNSET)
+		CONFIG_SPCR_TSECEP |
+#endif
+#if defined(CONFIG_SPCR_TSEC1EP) && !defined(CONFIG_SPCR_TSEC1EP_UNSET)
+		CONFIG_SPCR_TSEC1EP |
+#endif
+#if defined(CONFIG_SPCR_TSEC2EP) && !defined(CONFIG_SPCR_TSEC2EP_UNSET)
+		CONFIG_SPCR_TSEC2EP |
+#endif
+		0;
+
+	const __be32 lcrr_mask =
+#if defined(CONFIG_LCRR_DBYP) && !defined(CONFIG_LCRR_DBYP_UNSET)
+		LCRR_DBYP |
+#endif
+#if defined(CONFIG_LCRR_BUFCMDC) && !defined(CONFIG_LCRR_BUFCMDC_UNSET)
+		LCRR_BUFCMDC |
+#endif
+#if defined(CONFIG_LCRR_ECL) && !defined(CONFIG_LCRR_ECL_UNSET)
+		LCRR_ECL |
+#endif
+#if defined(CONFIG_LCRR_EADC) && !defined(CONFIG_LCRR_EADC_UNSET)
+		LCRR_EADC |
+#endif
+#if defined(CONFIG_LCRR_CLKDIV) && !defined(CONFIG_LCRR_CLKDIV_UNSET)
+		LCRR_CLKDIV |
+#endif
+		0;
+
+	const __be32 lcrr_val =
+#if defined(CONFIG_LCRR_DBYP) && !defined(CONFIG_LCRR_DBYP_UNSET)
+		CONFIG_LCRR_DBYP |
+#endif
+#if defined(CONFIG_LCRR_BUFCMDC) && !defined(CONFIG_LCRR_BUFCMDC_UNSET)
+		CONFIG_LCRR_BUFCMDC |
+#endif
+#if defined(CONFIG_LCRR_ECL) && !defined(CONFIG_LCRR_ECL_UNSET)
+		CONFIG_LCRR_ECL |
+#endif
+#if defined(CONFIG_LCRR_EADC) && !defined(CONFIG_LCRR_EADC_UNSET)
+		CONFIG_LCRR_EADC |
+#endif
+#if defined(CONFIG_LCRR_CLKDIV) && !defined(CONFIG_LCRR_CLKDIV_UNSET)
+		CONFIG_LCRR_CLKDIV |
+#endif
+		0;
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/interrupts.c b/roms/u-boot/arch/powerpc/cpu/mpc83xx/interrupts.c
new file mode 100644
index 000000000..f9486678a
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/interrupts.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <irq_func.h>
+#include <mpc83xx.h>
+#include <asm/global_data.h>
+#include <asm/processor.h>
+#include <asm/ptrace.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct irq_action {
+	interrupt_handler_t *handler;
+	void *arg;
+	ulong count;
+};
+
+void interrupt_init_cpu (unsigned *decrementer_count)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+
+	*decrementer_count = (gd->bus_clk / 4) / CONFIG_SYS_HZ;
+
+	/* Enable e300 time base */
+
+	immr->sysconf.spcr |= 0x00400000;
+}
+
+
+/*
+ * Handle external interrupts
+ */
+
+void external_interrupt(struct pt_regs *regs)
+{
+}
+
+
+/*
+ * Install and free an interrupt handler.
+ */
+
+void
+irq_install_handler(int irq, interrupt_handler_t * handler, void *arg)
+{
+}
+
+
+void irq_free_handler(int irq)
+{
+}
+
+
+void timer_interrupt_cpu (struct pt_regs *regs)
+{
+	/* nothing to do here */
+	return;
+}
+
+
+#if defined(CONFIG_CMD_IRQ)
+
+/* ripped this out of ppc4xx/interrupts.c */
+
+/*
+ * irqinfo - print information about PCI devices
+ */
+
+void do_irqinfo(struct cmd_tbl *cmdtp, struct bd_info *bd, int flag, int argc,
+		char *const argv[])
+{
+}
+
+#endif
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/law.c b/roms/u-boot/arch/powerpc/cpu/mpc83xx/law.c
new file mode 100644
index 000000000..5e02f4094
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/law.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <log.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+#include <linux/log2.h>
+
+int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
+{
+	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
+	u64 start_align, law_sz;
+	int law_sz_enc;
+
+	if (start == 0)
+		start_align = 1ull << (LAW_SIZE_2G + 1);
+	else
+		start_align = 1ull << (__ffs64(start));
+	law_sz = min(start_align, sz);
+	law_sz_enc = __ilog2_u64(law_sz) - 1;
+
+	/*
+	 * Set up LAWBAR for all of DDR.
+	 */
+	ecm->bar = start & 0xfffff000;
+	ecm->ar  = (LAWAR_EN | (id << 20) | (LAWAR_SIZE & law_sz_enc));
+	debug("DDR:bar=0x%08x\n", ecm->bar);
+	debug("DDR:ar=0x%08x\n", ecm->ar);
+
+	/* recalculate size based on what was actually covered by the law */
+	law_sz = 1ull << __ilog2_u64(law_sz);
+
+	/* do we still have anything to map */
+	sz = sz - law_sz;
+	if (sz) {
+		start += law_sz;
+
+		start_align = 1ull << (__ffs64(start));
+		law_sz = min(start_align, sz);
+		law_sz_enc = __ilog2_u64(law_sz) - 1;
+		ecm = &immap->sysconf.ddrlaw[1];
+		ecm->bar = start & 0xfffff000;
+		ecm->ar  = (LAWAR_EN | (id << 20) | (LAWAR_SIZE & law_sz_enc));
+		debug("DDR:bar=0x%08x\n", ecm->bar);
+		debug("DDR:ar=0x%08x\n", ecm->ar);
+	} else {
+		return 0;
+	}
+
+	/* do we still have anything to map */
+	sz = sz - law_sz;
+	if (sz)
+		return 1;
+
+	return 0;
+}
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/lblaw/Kconfig b/roms/u-boot/arch/powerpc/cpu/mpc83xx/lblaw/Kconfig
new file mode 100644
index 000000000..b20f68b77
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/lblaw/Kconfig
@@ -0,0 +1,519 @@
+menu "LBLAW setup"
+
+choice
+	prompt "NAND LAWBAR for NAND SPL"
+
+config NAND_LBLAWBAR_PRELIM_NONE
+	bool "None"
+
+config NAND_LBLAWBAR_PRELIM_0
+	bool "0"
+	depends on LBLAW0
+
+config NAND_LBLAWBAR_PRELIM_1
+	bool "1"
+	depends on LBLAW1
+
+config NAND_LBLAWBAR_PRELIM_2
+	bool "2"
+	depends on LBLAW2
+
+config NAND_LBLAWBAR_PRELIM_3
+	bool "3"
+	depends on LBLAW3
+
+endchoice
+
+menuconfig LBLAW0
+	bool "LBLAW0"
+
+if LBLAW0
+
+config LBLAW0_ENABLE
+	bool "Window enable"
+	default "y"
+
+if !LBLAW0_ENABLE
+
+config LBLAW0_BASE
+	hex
+	default 0x0
+
+endif
+
+if LBLAW0_ENABLE
+
+config LBLAW0_NAME
+	string "Identifier"
+
+config LBLAW0_BASE
+	hex "Window base"
+
+choice
+	prompt "Window size"
+
+config LBLAW0_LENGTH_4_KBYTES
+	bool "4 kb"
+
+config LBLAW0_LENGTH_8_KBYTES
+	bool "8 kb"
+
+config LBLAW0_LENGTH_16_KBYTES
+	bool "16 kb"
+
+config LBLAW0_LENGTH_32_KBYTES
+	bool "32 kb"
+
+config LBLAW0_LENGTH_64_KBYTES
+	bool "64 kb"
+
+config LBLAW0_LENGTH_128_KBYTES
+	bool "128 kb"
+
+config LBLAW0_LENGTH_256_KBYTES
+	bool "256 kb"
+
+config LBLAW0_LENGTH_512_KBYTES
+	bool "512 kb"
+
+config LBLAW0_LENGTH_1_MBYTES
+	bool "1 mb"
+
+config LBLAW0_LENGTH_2_MBYTES
+	bool "2 mb"
+
+config LBLAW0_LENGTH_4_MBYTES
+	bool "4 mb"
+
+config LBLAW0_LENGTH_8_MBYTES
+	bool "8 mb"
+
+config LBLAW0_LENGTH_16_MBYTES
+	bool "16 mb"
+
+config LBLAW0_LENGTH_32_MBYTES
+	bool "32 mb"
+
+config LBLAW0_LENGTH_64_MBYTES
+	bool "64 mb"
+
+config LBLAW0_LENGTH_128_MBYTES
+	bool "128 mb"
+
+config LBLAW0_LENGTH_256_MBYTES
+	bool "256 mb"
+
+config LBLAW0_LENGTH_512_MBYTES
+	bool "512 mb"
+
+config LBLAW0_LENGTH_1_GBYTES
+	bool "1 gb"
+
+config LBLAW0_LENGTH_2_GBYTES
+	bool "2 gb"
+
+endchoice
+
+endif # LBLAW0_ENABLE
+
+endif # LBLAW0
+
+config LBLAW0_ENABLE_BIT
+	hex
+	default 0x0 if !LBLAW0_ENABLE
+	default 0x80000000 if LBLAW0_ENABLE
+
+config LBLAW0_LENGTH
+	hex
+	default 0x0 if !LBLAW0_ENABLE
+	default 0x0000000B if LBLAW0_LENGTH_4_KBYTES
+	default 0x0000000C if LBLAW0_LENGTH_8_KBYTES
+	default 0x0000000D if LBLAW0_LENGTH_16_KBYTES
+	default 0x0000000E if LBLAW0_LENGTH_32_KBYTES
+	default 0x0000000F if LBLAW0_LENGTH_64_KBYTES
+	default 0x00000010 if LBLAW0_LENGTH_128_KBYTES
+	default 0x00000011 if LBLAW0_LENGTH_256_KBYTES
+	default 0x00000012 if LBLAW0_LENGTH_512_KBYTES
+	default 0x00000013 if LBLAW0_LENGTH_1_MBYTES
+	default 0x00000014 if LBLAW0_LENGTH_2_MBYTES
+	default 0x00000015 if LBLAW0_LENGTH_4_MBYTES
+	default 0x00000016 if LBLAW0_LENGTH_8_MBYTES
+	default 0x00000017 if LBLAW0_LENGTH_16_MBYTES
+	default 0x00000018 if LBLAW0_LENGTH_32_MBYTES
+	default 0x00000019 if LBLAW0_LENGTH_64_MBYTES
+	default 0x0000001A if LBLAW0_LENGTH_128_MBYTES
+	default 0x0000001B if LBLAW0_LENGTH_256_MBYTES
+	default 0x0000001C if LBLAW0_LENGTH_512_MBYTES
+	default 0x0000001D if LBLAW0_LENGTH_1_GBYTES
+	default 0x0000001E if LBLAW0_LENGTH_2_GBYTES
+
+menuconfig LBLAW1
+	bool "LBLAW1"
+
+if LBLAW1
+
+config LBLAW1_ENABLE
+	bool "Window enable"
+	default "y"
+
+if !LBLAW1_ENABLE
+
+config LBLAW1_BASE
+	hex
+	default 0x0
+
+endif
+
+if LBLAW1_ENABLE
+
+config LBLAW1_NAME
+	string "Identifier"
+
+config LBLAW1_BASE
+	hex "Window base"
+
+choice
+	prompt "Window size"
+
+config LBLAW1_LENGTH_4_KBYTES
+	bool "4 kb"
+
+config LBLAW1_LENGTH_8_KBYTES
+	bool "8 kb"
+
+config LBLAW1_LENGTH_16_KBYTES
+	bool "16 kb"
+
+config LBLAW1_LENGTH_32_KBYTES
+	bool "32 kb"
+
+config LBLAW1_LENGTH_64_KBYTES
+	bool "64 kb"
+
+config LBLAW1_LENGTH_128_KBYTES
+	bool "128 kb"
+
+config LBLAW1_LENGTH_256_KBYTES
+	bool "256 kb"
+
+config LBLAW1_LENGTH_512_KBYTES
+	bool "512 kb"
+
+config LBLAW1_LENGTH_1_MBYTES
+	bool "1 mb"
+
+config LBLAW1_LENGTH_2_MBYTES
+	bool "2 mb"
+
+config LBLAW1_LENGTH_4_MBYTES
+	bool "4 mb"
+
+config LBLAW1_LENGTH_8_MBYTES
+	bool "8 mb"
+
+config LBLAW1_LENGTH_16_MBYTES
+	bool "16 mb"
+
+config LBLAW1_LENGTH_32_MBYTES
+	bool "32 mb"
+
+config LBLAW1_LENGTH_64_MBYTES
+	bool "64 mb"
+
+config LBLAW1_LENGTH_128_MBYTES
+	bool "128 mb"
+
+config LBLAW1_LENGTH_256_MBYTES
+	bool "256 mb"
+
+config LBLAW1_LENGTH_512_MBYTES
+	bool "512 mb"
+
+config LBLAW1_LENGTH_1_GBYTES
+	bool "1 gb"
+
+config LBLAW1_LENGTH_2_GBYTES
+	bool "2 gb"
+
+endchoice
+
+endif # LBLAW1_ENABLE
+
+endif # LBLAW1
+
+config LBLAW1_ENABLE_BIT
+	hex
+	default 0x0 if !LBLAW1_ENABLE
+	default 0x80000000 if LBLAW1_ENABLE
+
+config LBLAW1_LENGTH
+	hex
+	default 0x0 if !LBLAW1_ENABLE
+	default 0x0000000B if LBLAW1_LENGTH_4_KBYTES
+	default 0x0000000C if LBLAW1_LENGTH_8_KBYTES
+	default 0x0000000D if LBLAW1_LENGTH_16_KBYTES
+	default 0x0000000E if LBLAW1_LENGTH_32_KBYTES
+	default 0x0000000F if LBLAW1_LENGTH_64_KBYTES
+	default 0x00000010 if LBLAW1_LENGTH_128_KBYTES
+	default 0x00000011 if LBLAW1_LENGTH_256_KBYTES
+	default 0x00000012 if LBLAW1_LENGTH_512_KBYTES
+	default 0x00000013 if LBLAW1_LENGTH_1_MBYTES
+	default 0x00000014 if LBLAW1_LENGTH_2_MBYTES
+	default 0x00000015 if LBLAW1_LENGTH_4_MBYTES
+	default 0x00000016 if LBLAW1_LENGTH_8_MBYTES
+	default 0x00000017 if LBLAW1_LENGTH_16_MBYTES
+	default 0x00000018 if LBLAW1_LENGTH_32_MBYTES
+	default 0x00000019 if LBLAW1_LENGTH_64_MBYTES
+	default 0x0000001A if LBLAW1_LENGTH_128_MBYTES
+	default 0x0000001B if LBLAW1_LENGTH_256_MBYTES
+	default 0x0000001C if LBLAW1_LENGTH_512_MBYTES
+	default 0x0000001D if LBLAW1_LENGTH_1_GBYTES
+	default 0x0000001E if LBLAW1_LENGTH_2_GBYTES
+
+menuconfig LBLAW2
+	bool "LBLAW2"
+
+if LBLAW2
+
+config LBLAW2_ENABLE
+	bool "Window enable"
+	default "y"
+
+if !LBLAW2_ENABLE
+
+config LBLAW2_BASE
+	hex
+	default 0x0
+
+endif
+
+if LBLAW2_ENABLE
+
+config LBLAW2_NAME
+	string "Identifier"
+
+config LBLAW2_BASE
+	hex "Window base"
+
+choice
+	prompt "Window size"
+
+config LBLAW2_LENGTH_4_KBYTES
+	bool "4 kb"
+
+config LBLAW2_LENGTH_8_KBYTES
+	bool "8 kb"
+
+config LBLAW2_LENGTH_16_KBYTES
+	bool "16 kb"
+
+config LBLAW2_LENGTH_32_KBYTES
+	bool "32 kb"
+
+config LBLAW2_LENGTH_64_KBYTES
+	bool "64 kb"
+
+config LBLAW2_LENGTH_128_KBYTES
+	bool "128 kb"
+
+config LBLAW2_LENGTH_256_KBYTES
+	bool "256 kb"
+
+config LBLAW2_LENGTH_512_KBYTES
+	bool "512 kb"
+
+config LBLAW2_LENGTH_1_MBYTES
+	bool "1 mb"
+
+config LBLAW2_LENGTH_2_MBYTES
+	bool "2 mb"
+
+config LBLAW2_LENGTH_4_MBYTES
+	bool "4 mb"
+
+config LBLAW2_LENGTH_8_MBYTES
+	bool "8 mb"
+
+config LBLAW2_LENGTH_16_MBYTES
+	bool "16 mb"
+
+config LBLAW2_LENGTH_32_MBYTES
+	bool "32 mb"
+
+config LBLAW2_LENGTH_64_MBYTES
+	bool "64 mb"
+
+config LBLAW2_LENGTH_128_MBYTES
+	bool "128 mb"
+
+config LBLAW2_LENGTH_256_MBYTES
+	bool "256 mb"
+
+config LBLAW2_LENGTH_512_MBYTES
+	bool "512 mb"
+
+config LBLAW2_LENGTH_1_GBYTES
+	bool "1 gb"
+
+config LBLAW2_LENGTH_2_GBYTES
+	bool "2 gb"
+
+endchoice
+
+endif # LBLAW2_ENABLE
+
+endif # LBLAW2
+
+config LBLAW2_ENABLE_BIT
+	hex
+	default 0x0 if !LBLAW2_ENABLE
+	default 0x80000000 if LBLAW2_ENABLE
+
+config LBLAW2_LENGTH
+	hex
+	default 0x0 if !LBLAW2_ENABLE
+	default 0x0000000B if LBLAW2_LENGTH_4_KBYTES
+	default 0x0000000C if LBLAW2_LENGTH_8_KBYTES
+	default 0x0000000D if LBLAW2_LENGTH_16_KBYTES
+	default 0x0000000E if LBLAW2_LENGTH_32_KBYTES
+	default 0x0000000F if LBLAW2_LENGTH_64_KBYTES
+	default 0x00000010 if LBLAW2_LENGTH_128_KBYTES
+	default 0x00000011 if LBLAW2_LENGTH_256_KBYTES
+	default 0x00000012 if LBLAW2_LENGTH_512_KBYTES
+	default 0x00000013 if LBLAW2_LENGTH_1_MBYTES
+	default 0x00000014 if LBLAW2_LENGTH_2_MBYTES
+	default 0x00000015 if LBLAW2_LENGTH_4_MBYTES
+	default 0x00000016 if LBLAW2_LENGTH_8_MBYTES
+	default 0x00000017 if LBLAW2_LENGTH_16_MBYTES
+	default 0x00000018 if LBLAW2_LENGTH_32_MBYTES
+	default 0x00000019 if LBLAW2_LENGTH_64_MBYTES
+	default 0x0000001A if LBLAW2_LENGTH_128_MBYTES
+	default 0x0000001B if LBLAW2_LENGTH_256_MBYTES
+	default 0x0000001C if LBLAW2_LENGTH_512_MBYTES
+	default 0x0000001D if LBLAW2_LENGTH_1_GBYTES
+	default 0x0000001E if LBLAW2_LENGTH_2_GBYTES
+
+menuconfig LBLAW3
+	bool "LBLAW3"
+
+if LBLAW3
+
+config LBLAW3_ENABLE
+	bool "Window enable"
+	default "y"
+
+if !LBLAW3_ENABLE
+
+config LBLAW3_BASE
+	hex
+	default 0x0
+
+endif
+
+if LBLAW3_ENABLE
+
+config LBLAW3_NAME
+	string "Identifier"
+
+config LBLAW3_BASE
+	hex "Window base"
+
+choice
+	prompt "Window size"
+
+config LBLAW3_LENGTH_4_KBYTES
+	bool "4 kb"
+
+config LBLAW3_LENGTH_8_KBYTES
+	bool "8 kb"
+
+config LBLAW3_LENGTH_16_KBYTES
+	bool "16 kb"
+
+config LBLAW3_LENGTH_32_KBYTES
+	bool "32 kb"
+
+config LBLAW3_LENGTH_64_KBYTES
+	bool "64 kb"
+
+config LBLAW3_LENGTH_128_KBYTES
+	bool "128 kb"
+
+config LBLAW3_LENGTH_256_KBYTES
+	bool "256 kb"
+
+config LBLAW3_LENGTH_512_KBYTES
+	bool "512 kb"
+
+config LBLAW3_LENGTH_1_MBYTES
+	bool "1 mb"
+
+config LBLAW3_LENGTH_2_MBYTES
+	bool "2 mb"
+
+config LBLAW3_LENGTH_4_MBYTES
+	bool "4 mb"
+
+config LBLAW3_LENGTH_8_MBYTES
+	bool "8 mb"
+
+config LBLAW3_LENGTH_16_MBYTES
+	bool "16 mb"
+
+config LBLAW3_LENGTH_32_MBYTES
+	bool "32 mb"
+
+config LBLAW3_LENGTH_64_MBYTES
+	bool "64 mb"
+
+config LBLAW3_LENGTH_128_MBYTES
+	bool "128 mb"
+
+config LBLAW3_LENGTH_256_MBYTES
+	bool "256 mb"
+
+config LBLAW3_LENGTH_512_MBYTES
+	bool "512 mb"
+
+config LBLAW3_LENGTH_1_GBYTES
+	bool "1 gb"
+
+config LBLAW3_LENGTH_2_GBYTES
+	bool "2 gb"
+
+endchoice
+
+endif # LBLAW3_ENABLE
+
+endif # LBLAW3
+
+config LBLAW3_ENABLE_BIT
+	hex
+	default 0x0 if !LBLAW3_ENABLE
+	default 0x80000000 if LBLAW3_ENABLE
+
+config LBLAW3_LENGTH
+	hex
+	default 0x0 if !LBLAW3_ENABLE
+	default 0x0000000B if LBLAW3_LENGTH_4_KBYTES
+	default 0x0000000C if LBLAW3_LENGTH_8_KBYTES
+	default 0x0000000D if LBLAW3_LENGTH_16_KBYTES
+	default 0x0000000E if LBLAW3_LENGTH_32_KBYTES
+	default 0x0000000F if LBLAW3_LENGTH_64_KBYTES
+	default 0x00000010 if LBLAW3_LENGTH_128_KBYTES
+	default 0x00000011 if LBLAW3_LENGTH_256_KBYTES
+	default 0x00000012 if LBLAW3_LENGTH_512_KBYTES
+	default 0x00000013 if LBLAW3_LENGTH_1_MBYTES
+	default 0x00000014 if LBLAW3_LENGTH_2_MBYTES
+	default 0x00000015 if LBLAW3_LENGTH_4_MBYTES
+	default 0x00000016 if LBLAW3_LENGTH_8_MBYTES
+	default 0x00000017 if LBLAW3_LENGTH_16_MBYTES
+	default 0x00000018 if LBLAW3_LENGTH_32_MBYTES
+	default 0x00000019 if LBLAW3_LENGTH_64_MBYTES
+	default 0x0000001A if LBLAW3_LENGTH_128_MBYTES
+	default 0x0000001B if LBLAW3_LENGTH_256_MBYTES
+	default 0x0000001C if LBLAW3_LENGTH_512_MBYTES
+	default 0x0000001D if LBLAW3_LENGTH_1_GBYTES
+	default 0x0000001E if LBLAW3_LENGTH_2_GBYTES
+
+endmenu
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h b/roms/u-boot/arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h
new file mode 100644
index 000000000..6972afcc2
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h
@@ -0,0 +1,55 @@
+#if defined(CONFIG_LBLAW0)
+#define CONFIG_SYS_LBLAWBAR0_PRELIM \
+	CONFIG_LBLAW0_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM (\
+	CONFIG_LBLAW0_ENABLE_BIT |\
+	CONFIG_LBLAW0_LENGTH \
+)
+#endif
+
+#if defined(CONFIG_LBLAW1)
+#define CONFIG_SYS_LBLAWBAR1_PRELIM \
+	CONFIG_LBLAW1_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM (\
+	CONFIG_LBLAW1_ENABLE_BIT |\
+	CONFIG_LBLAW1_LENGTH \
+)
+#endif
+
+#if defined(CONFIG_LBLAW2)
+#define CONFIG_SYS_LBLAWBAR2_PRELIM \
+	CONFIG_LBLAW2_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM (\
+	CONFIG_LBLAW2_ENABLE_BIT |\
+	CONFIG_LBLAW2_LENGTH \
+)
+#endif
+
+#if defined(CONFIG_LBLAW3)
+#define CONFIG_SYS_LBLAWBAR3_PRELIM \
+	CONFIG_LBLAW3_BASE
+#define CONFIG_SYS_LBLAWAR3_PRELIM (\
+	CONFIG_LBLAW3_ENABLE_BIT |\
+	CONFIG_LBLAW3_LENGTH \
+)
+#endif
+
+#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_0
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM
+#endif
+
+#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_1
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
+#endif
+
+#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_2
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR2_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR2_PRELIM
+#endif
+
+#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_3
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR3_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR3_PRELIM
+#endif
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/pci.c b/roms/u-boot/arch/powerpc/cpu/mpc83xx/pci.c
new file mode 100644
index 000000000..5c289d002
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/pci.c
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2007
+ *
+ * Author: Scott Wood <scottwood@freescale.com>,
+ * with some bits from older board-specific PCI initialization.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <pci.h>
+#include <asm/bitops.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+
+#if defined(CONFIG_OF_LIBFDT)
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#endif
+
+#include <asm/mpc8349_pci.h>
+
+#define MAX_BUSES 2
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pci_controller pci_hose[MAX_BUSES];
+static int pci_num_buses;
+
+static void pci_init_bus(int bus, struct pci_region *reg)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile pot83xx_t *pot = immr->ios.pot;
+	volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus];
+	struct pci_controller *hose = &pci_hose[bus];
+	u32 dev;
+	u16 reg16;
+	int i;
+
+	if (bus == 1)
+		pot += 3;
+
+	/* Setup outbound translation windows */
+	for (i = 0; i < 3; i++, reg++, pot++) {
+		if (reg->size == 0)
+			break;
+
+		hose->regions[i] = *reg;
+		hose->region_count++;
+
+		pot->potar = reg->bus_start >> 12;
+		pot->pobar = reg->phys_start >> 12;
+		pot->pocmr = ~(reg->size - 1) >> 12;
+
+		if (reg->flags & PCI_REGION_IO)
+			pot->pocmr |= POCMR_IO;
+#ifdef CONFIG_83XX_PCI_STREAMING
+		else if (reg->flags & PCI_REGION_PREFETCH)
+			pot->pocmr |= POCMR_SE;
+#endif
+
+		if (bus == 1)
+			pot->pocmr |= POCMR_DST;
+
+		pot->pocmr |= POCMR_EN;
+	}
+
+	/* Point inbound translation at RAM */
+	pci_ctrl->pitar1 = 0;
+	pci_ctrl->pibar1 = 0;
+	pci_ctrl->piebar1 = 0;
+	pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
+			   PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size - 1));
+
+	i = hose->region_count++;
+	hose->regions[i].bus_start = 0;
+	hose->regions[i].phys_start = 0;
+	hose->regions[i].size = gd->ram_size;
+	hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
+
+	hose->first_busno = pci_last_busno() + 1;
+	hose->last_busno = 0xff;
+
+	pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80,
+				 CONFIG_SYS_IMMR + 0x8304 + bus * 0x80);
+
+	pci_register_hose(hose);
+
+	/*
+	 * Write to Command register
+	 */
+	reg16 = 0xff;
+	dev = PCI_BDF(hose->first_busno, 0, 0);
+	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
+	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+
+	/*
+	 * Clear non-reserved bits in status register.
+	 */
+	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+	printf("PCI:   Bus Dev VenId DevId Class Int\n");
+#endif
+#ifndef CONFIG_PCISLAVE
+	/*
+	 * Hose scan.
+	 */
+	hose->last_busno = pci_hose_scan(hose);
+#endif
+}
+
+/*
+ * The caller must have already set OCCR, and the PCI_LAW BARs
+ * must have been set to cover all of the requested regions.
+ *
+ * If fewer than three regions are requested, then the region
+ * list is terminated with a region of size 0.
+ */
+void mpc83xx_pci_init(int num_buses, struct pci_region **reg)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	int i;
+
+	if (num_buses > MAX_BUSES) {
+		printf("%d PCI buses requested, %d supported\n",
+		       num_buses, MAX_BUSES);
+
+		num_buses = MAX_BUSES;
+	}
+
+	pci_num_buses = num_buses;
+
+	/*
+	 * Release PCI RST Output signal.
+	 * Power on to RST high must be at least 100 ms as per PCI spec.
+	 * On warm boots only 1 ms is required, but we play it safe.
+	 */
+	udelay(100000);
+
+	for (i = 0; i < num_buses; i++)
+		immr->pci_ctrl[i].gcr = 1;
+
+	/*
+	 * RST high to first config access must be at least 2^25 cycles
+	 * as per PCI spec.  This could be cut in half if we know we're
+	 * running at 66MHz.  This could be insufficiently long if we're
+	 * running the PCI bus at significantly less than 33MHz.
+	 */
+	udelay(1020000);
+
+	for (i = 0; i < num_buses; i++)
+		pci_init_bus(i, reg[i]);
+}
+
+#ifdef CONFIG_PCISLAVE
+
+#define PCI_FUNCTION_CONFIG	0x44
+#define PCI_FUNCTION_CFG_LOCK	0x20
+
+/*
+ * Unlock the configuration bit so that the host system can begin booting
+ *
+ * This should be used after you have:
+ * 1) Called mpc83xx_pci_init()
+ * 2) Set up your inbound translation windows to the appropriate size
+ */
+void mpc83xx_pcislave_unlock(int bus)
+{
+	struct pci_controller *hose = &pci_hose[bus];
+	u32 dev;
+	u16 reg16;
+
+	/* Unlock configuration lock in PCI function configuration register */
+	dev = PCI_BDF(hose->first_busno, 0, 0);
+	pci_hose_read_config_word (hose, dev, PCI_FUNCTION_CONFIG, &reg16);
+	reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
+	pci_hose_write_config_word (hose, dev, PCI_FUNCTION_CONFIG, reg16);
+
+	/* The configuration bit is now unlocked, so we can scan the bus */
+	hose->last_busno = pci_hose_scan(hose);
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT)
+void ft_pci_setup(void *blob, struct bd_info *bd)
+{
+	int nodeoffset;
+	int tmp[2];
+	const char *path;
+
+	if (pci_num_buses < 1)
+		return;
+
+	nodeoffset = fdt_path_offset(blob, "/aliases");
+	if (nodeoffset >= 0) {
+		path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
+		if (path) {
+			tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
+			tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
+			do_fixup_by_path(blob, path, "bus-range",
+				&tmp, sizeof(tmp), 1);
+
+			tmp[0] = cpu_to_be32(gd->pci_clk);
+			do_fixup_by_path(blob, path, "clock-frequency",
+				&tmp, sizeof(tmp[0]), 1);
+		}
+
+		if (pci_num_buses < 2)
+			return;
+
+		path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
+		if (path) {
+			tmp[0] = cpu_to_be32(pci_hose[1].first_busno);
+			tmp[1] = cpu_to_be32(pci_hose[1].last_busno);
+			do_fixup_by_path(blob, path, "bus-range",
+				&tmp, sizeof(tmp), 1);
+
+			tmp[0] = cpu_to_be32(gd->pci_clk);
+			do_fixup_by_path(blob, path, "clock-frequency",
+				&tmp, sizeof(tmp[0]), 1);
+		}
+	}
+}
+#endif /* CONFIG_OF_LIBFDT */
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/pcie.c b/roms/u-boot/arch/powerpc/cpu/mpc83xx/pcie.c
new file mode 100644
index 000000000..84797c871
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/pcie.c
@@ -0,0 +1,369 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2007-2009  Freescale Semiconductor, Inc.
+ * Copyright (C) 2008-2009  MontaVista Software, Inc.
+ *
+ * Authors: Tony Li <tony.li@freescale.com>
+ *          Anton Vorontsov <avorontsov@ru.mvista.com>
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PCIE_MAX_BUSES 2
+
+static struct {
+	u32 base;
+	u32 size;
+} mpc83xx_pcie_cfg_space[] = {
+	{
+		.base = CONFIG_SYS_PCIE1_CFG_BASE,
+		.size = CONFIG_SYS_PCIE1_CFG_SIZE,
+	},
+#if defined(CONFIG_SYS_PCIE2_CFG_BASE) && defined(CONFIG_SYS_PCIE2_CFG_SIZE)
+	{
+		.base = CONFIG_SYS_PCIE2_CFG_BASE,
+		.size = CONFIG_SYS_PCIE2_CFG_SIZE,
+	},
+#endif
+};
+
+#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
+
+/* private structure for mpc83xx pcie hose */
+static struct mpc83xx_pcie_priv {
+	u8 index;
+} pcie_priv[PCIE_MAX_BUSES] = {
+	{
+		/* pcie controller 1 */
+		.index = 0,
+	},
+	{
+		/* pcie controller 2 */
+		.index = 1,
+	},
+};
+
+static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
+{
+	int bus = PCI_BUS(dev) - hose->first_busno;
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	struct mpc83xx_pcie_priv *pcie_priv = hose->priv_data;
+	pex83xx_t *pex = &immr->pciexp[pcie_priv->index];
+	struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0];
+	u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev);
+	u32 dev_base = bus << 24 | devfn << 16;
+
+	if (hose->indirect_type == INDIRECT_TYPE_NO_PCIE_LINK)
+		return -1;
+	/*
+	 * Workaround for the HW bug: for Type 0 configure transactions the
+	 * PCI-E controller does not check the device number bits and just
+	 * assumes that the device number bits are 0.
+	 */
+	if (devfn & 0xf8)
+		return -1;
+
+	out_le32(&out_win->tarl, dev_base);
+	return 0;
+}
+
+#define cfg_read(val, addr, type, op) \
+	do { *val = op((type)(addr)); } while (0)
+#define cfg_write(val, addr, type, op) \
+	do { op((type *)(addr), (val)); } while (0)
+
+#define cfg_read_err(val) do { *val = -1; } while (0)
+#define cfg_write_err(val) do { } while (0)
+
+#define PCIE_OP(rw, size, type, op)					\
+static int pcie_##rw##_config_##size(struct pci_controller *hose,	\
+				     pci_dev_t dev, int offset,		\
+				     type val)				\
+{									\
+	int ret;							\
+									\
+	ret = mpc83xx_pcie_remap_cfg(hose, dev);			\
+	if (ret) {							\
+		cfg_##rw##_err(val); 					\
+		return ret; 						\
+	}								\
+	cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op);	\
+	return 0;							\
+}
+
+PCIE_OP(read, byte, u8 *, in_8)
+PCIE_OP(read, word, u16 *, in_le16)
+PCIE_OP(read, dword, u32 *, in_le32)
+PCIE_OP(write, byte, u8, out_8)
+PCIE_OP(write, word, u16, out_le16)
+PCIE_OP(write, dword, u32, out_le32)
+
+static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
+				       u8 link)
+{
+	extern void disable_addr_trans(void); /* start.S */
+	static struct pci_controller pcie_hose[PCIE_MAX_BUSES];
+	struct pci_controller *hose = &pcie_hose[bus];
+	int i;
+
+	/*
+	 * There are no spare BATs to remap all PCI-E windows for U-Boot, so
+	 * disable translations. In general, this is not great solution, and
+	 * that's why we don't register PCI-E hoses by default.
+	 */
+	disable_addr_trans();
+
+	for (i = 0; i < 2; i++, reg++) {
+		if (reg->size == 0)
+			break;
+
+		hose->regions[i] = *reg;
+		hose->region_count++;
+	}
+
+	i = hose->region_count++;
+	hose->regions[i].bus_start = 0;
+	hose->regions[i].phys_start = 0;
+	hose->regions[i].size = gd->ram_size;
+	hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
+
+	i = hose->region_count++;
+	hose->regions[i].bus_start = CONFIG_SYS_IMMR;
+	hose->regions[i].phys_start = CONFIG_SYS_IMMR;
+	hose->regions[i].size = 0x100000;
+	hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
+
+	hose->first_busno = pci_last_busno() + 1;
+	hose->last_busno = 0xff;
+
+	hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base;
+
+	hose->priv_data = &pcie_priv[bus];
+
+	pci_set_ops(hose,
+			pcie_read_config_byte,
+			pcie_read_config_word,
+			pcie_read_config_dword,
+			pcie_write_config_byte,
+			pcie_write_config_word,
+			pcie_write_config_dword);
+
+	if (!link)
+		hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK;
+
+	pci_register_hose(hose);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+	printf("PCI:   Bus Dev VenId DevId Class Int\n");
+#endif
+	/*
+	 * Hose scan.
+	 */
+	hose->last_busno = pci_hose_scan(hose);
+}
+
+#else
+
+static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
+				       u8 link) {}
+
+#endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */
+
+int get_pcie_clk(int index)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 pci_sync_in;
+	u8 spmf;
+	u8 clkin_div;
+	u32 sccr;
+	u32 csb_clk;
+	u32 testval;
+
+	clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
+	sccr = im->clk.sccr;
+	pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
+	spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
+	csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
+
+	if (index)
+		testval = (sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT;
+	else
+		testval = (sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT;
+
+	switch (testval) {
+	case 0:
+		return 0;
+	case 1:
+		return csb_clk;
+	case 2:
+		return csb_clk / 2;
+	case 3:
+		return csb_clk / 3;
+	}
+
+	return 0;
+}
+
+static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
+{
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	pex83xx_t *pex = &immr->pciexp[bus];
+	struct pex_outbound_window *out_win;
+	struct pex_inbound_window *in_win;
+	void *hose_cfg_base;
+	unsigned int ram_sz;
+	unsigned int barl;
+	unsigned int tar;
+	u16 reg16;
+	int i;
+
+	/* Enable pex csb bridge inbound & outbound transactions */
+	out_le32(&pex->bridge.pex_csb_ctrl,
+		in_le32(&pex->bridge.pex_csb_ctrl) | PEX_CSB_CTRL_OBPIOE |
+		PEX_CSB_CTRL_IBPIOE);
+
+	/* Enable bridge outbound */
+	out_le32(&pex->bridge.pex_csb_obctrl, PEX_CSB_OBCTRL_PIOE |
+		PEX_CSB_OBCTRL_MEMWE | PEX_CSB_OBCTRL_IOWE |
+		PEX_CSB_OBCTRL_CFGWE);
+
+	out_win = &pex->bridge.pex_outbound_win[0];
+	out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
+			mpc83xx_pcie_cfg_space[bus].size);
+	out_le32(&out_win->bar, mpc83xx_pcie_cfg_space[bus].base);
+	out_le32(&out_win->tarl, 0);
+	out_le32(&out_win->tarh, 0);
+
+	for (i = 0; i < 2; i++) {
+		u32 ar;
+
+		if (reg[i].size == 0)
+			break;
+
+		out_win = &pex->bridge.pex_outbound_win[i + 1];
+		out_le32(&out_win->bar, reg[i].phys_start);
+		out_le32(&out_win->tarl, reg[i].bus_start);
+		out_le32(&out_win->tarh, 0);
+		ar = PEX_OWAR_EN | (reg[i].size & PEX_OWAR_SIZE);
+		if (reg[i].flags & PCI_REGION_IO)
+			ar |= PEX_OWAR_TYPE_IO;
+		else
+			ar |= PEX_OWAR_TYPE_MEM;
+		out_le32(&out_win->ar, ar);
+	}
+
+	out_le32(&pex->bridge.pex_csb_ibctrl, PEX_CSB_IBCTRL_PIOE);
+
+	ram_sz = gd->ram_size;
+	barl = 0;
+	tar = 0;
+	i = 0;
+	while (ram_sz > 0) {
+		in_win = &pex->bridge.pex_inbound_win[i];
+		out_le32(&in_win->barl, barl);
+		out_le32(&in_win->barh, 0x0);
+		out_le32(&in_win->tar, tar);
+		if (ram_sz >= 0x10000000) {
+			/* The maxium windows size is 256M */
+			out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
+				PEX_IWAR_TYPE_PF | 0x0FFFF000);
+			barl += 0x10000000;
+			tar += 0x10000000;
+			ram_sz -= 0x10000000;
+		} else {
+			/* The UM  is not clear here.
+			 * So, round up to even Mb boundary */
+
+			ram_sz = ram_sz >> (20 +
+					((ram_sz & 0xFFFFF) ? 1 : 0));
+			if (!(ram_sz % 2))
+				ram_sz -= 1;
+			out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
+				PEX_IWAR_TYPE_PF | (ram_sz << 20) | 0xFF000);
+			ram_sz = 0;
+		}
+		i++;
+	}
+
+	in_win = &pex->bridge.pex_inbound_win[i];
+	out_le32(&in_win->barl, CONFIG_SYS_IMMR);
+	out_le32(&in_win->barh, 0);
+	out_le32(&in_win->tar, CONFIG_SYS_IMMR);
+	out_le32(&in_win->ar, PEX_IWAR_EN |
+		PEX_IWAR_TYPE_NO_PF | PEX_IWAR_SIZE_1M);
+
+	/* Enable the host virtual INTX interrupts */
+	out_le32(&pex->bridge.pex_int_axi_misc_enb,
+		in_le32(&pex->bridge.pex_int_axi_misc_enb) | 0x1E0);
+
+	/* Hose configure header is memory-mapped */
+	hose_cfg_base = (void *)pex;
+
+	/* Configure the PCIE controller core clock ratio */
+	out_le32(hose_cfg_base + PEX_GCLK_RATIO,
+		((get_pcie_clk(bus) / 1000000) * 16) / 333);
+	udelay(1000000);
+
+	/* Do Type 1 bridge configuration */
+	out_8(hose_cfg_base + PCI_PRIMARY_BUS, 0);
+	out_8(hose_cfg_base + PCI_SECONDARY_BUS, 1);
+	out_8(hose_cfg_base + PCI_SUBORDINATE_BUS, 255);
+
+	/*
+	 * Write to Command register
+	 */
+	reg16 = in_le16(hose_cfg_base + PCI_COMMAND);
+	reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO |
+			PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
+	out_le16(hose_cfg_base + PCI_COMMAND, reg16);
+
+	/*
+	 * Clear non-reserved bits in status register.
+	 */
+	out_le16(hose_cfg_base + PCI_STATUS, 0xffff);
+	out_8(hose_cfg_base + PCI_LATENCY_TIMER, 0x80);
+	out_8(hose_cfg_base + PCI_CACHE_LINE_SIZE, 0x08);
+
+	printf("PCIE%d: ", bus);
+
+#define PCI_LTSSM	0x404 /* PCIe Link Training, Status State Machine */
+#define PCI_LTSSM_L0	0x16 /* L0 state */
+	reg16 = in_le16(hose_cfg_base + PCI_LTSSM);
+	if (reg16 >= PCI_LTSSM_L0)
+		printf("link\n");
+	else
+		printf("No link\n");
+
+	mpc83xx_pcie_register_hose(bus, reg, reg16 >= PCI_LTSSM_L0);
+}
+
+/*
+ * The caller must have already set SCCR, SERDES and the PCIE_LAW BARs
+ * must have been set to cover all of the requested regions.
+ */
+void mpc83xx_pcie_init(int num_buses, struct pci_region **reg)
+{
+	int i;
+
+	/*
+	 * Release PCI RST Output signal.
+	 * Power on to RST high must be at least 100 ms as per PCI spec.
+	 * On warm boots only 1 ms is required, but we play it safe.
+	 */
+	udelay(100000);
+
+	if (num_buses > ARRAY_SIZE(mpc83xx_pcie_cfg_space)) {
+		printf("Second PCIE host contoller not configured!\n");
+		num_buses = ARRAY_SIZE(mpc83xx_pcie_cfg_space);
+	}
+
+	for (i = 0; i < num_buses; i++)
+		mpc83xx_pcie_init_bus(i, reg[i]);
+}
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/qe_io.c b/roms/u-boot/arch/powerpc/cpu/mpc83xx/qe_io.c
new file mode 100644
index 000000000..52360703a
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/qe_io.c
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ * based on source code of Shlomi Gridish
+ */
+
+#include <common.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+#include <asm/immap_83xx.h>
+
+#define	NUM_OF_PINS	32
+
+/** qe_cfg_iopin configure one io pin setting
+ *
+ * @par_io:	pointer to parallel I/O base
+ * @port:	io pin port
+ * @pin:	io pin number which get configured
+ * @dir:	direction of io pin 2 bits valid
+ *		00 = pin disabled
+ *		01 = output
+ *		10 = input
+ *		11 = pin is I/O
+ * @open_drain:	is pin open drain
+ * @assign:	pin assignment registers select the function of the pin
+ */
+static void qe_cfg_iopin(qepio83xx_t *par_io, u8 port, u8 pin, int dir,
+			 int open_drain, int assign)
+{
+	u32	dbit_mask;
+	u32	dbit_dir;
+	u32	dbit_asgn;
+	u32	bit_mask;
+	u32	tmp_val;
+	int	offset;
+
+	offset = (NUM_OF_PINS - (pin % (NUM_OF_PINS / 2) + 1) * 2);
+
+	/* Calculate pin location and 2bit mask and dir */
+	dbit_mask = (u32)(0x3 << offset);
+	dbit_dir = (u32)(dir << offset);
+
+	/* Setup the direction */
+	tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
+		in_be32(&par_io->ioport[port].dir2) :
+		in_be32(&par_io->ioport[port].dir1);
+
+	if (pin > (NUM_OF_PINS / 2) - 1) {
+		out_be32(&par_io->ioport[port].dir2, ~dbit_mask & tmp_val);
+		out_be32(&par_io->ioport[port].dir2, dbit_dir | tmp_val);
+	} else {
+		out_be32(&par_io->ioport[port].dir1, ~dbit_mask & tmp_val);
+		out_be32(&par_io->ioport[port].dir1, dbit_dir | tmp_val);
+	}
+
+	/* Calculate pin location for 1bit mask */
+	bit_mask = (u32)(1 << (NUM_OF_PINS - (pin + 1)));
+
+	/* Setup the open drain */
+	tmp_val = in_be32(&par_io->ioport[port].podr);
+	if (open_drain)
+		out_be32(&par_io->ioport[port].podr, bit_mask | tmp_val);
+	else
+		out_be32(&par_io->ioport[port].podr, ~bit_mask & tmp_val);
+
+	/* Setup the assignment */
+	tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
+		in_be32(&par_io->ioport[port].ppar2) :
+		in_be32(&par_io->ioport[port].ppar1);
+	dbit_asgn = (u32)(assign << offset);
+
+	/* Clear and set 2 bits mask */
+	if (pin > (NUM_OF_PINS / 2) - 1) {
+		out_be32(&par_io->ioport[port].ppar2, ~dbit_mask & tmp_val);
+		out_be32(&par_io->ioport[port].ppar2, dbit_asgn | tmp_val);
+	} else {
+		out_be32(&par_io->ioport[port].ppar1, ~dbit_mask & tmp_val);
+		out_be32(&par_io->ioport[port].ppar1, dbit_asgn | tmp_val);
+	}
+}
+
+#if !defined(CONFIG_PINCTRL)
+/** qe_config_iopin configure one io pin setting
+ *
+ * @port:	io pin port
+ * @pin:	io pin number which get configured
+ * @dir:	direction of io pin 2 bits valid
+ *		00 = pin disabled
+ *		01 = output
+ *		10 = input
+ *		11 = pin is I/O
+ * @open_drain:	is pin open drain
+ * @assign:	pin assignment registers select the function of the pin
+ */
+void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
+{
+	immap_t        *im = (immap_t *)CONFIG_SYS_IMMR;
+	qepio83xx_t    *par_io = (qepio83xx_t *)&im->qepio;
+
+	qe_cfg_iopin(par_io, port, pin, dir, open_drain, assign);
+}
+#endif
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/serdes.c b/roms/u-boot/arch/powerpc/cpu/mpc83xx/serdes.c
new file mode 100644
index 000000000..bb963ee5e
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/serdes.c
@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Freescale SerDes initialization routine
+ *
+ * Copyright 2007,2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 MontaVista Software, Inc.
+ *
+ * Author: Li Yang <leoli@freescale.com>
+ */
+
+#ifndef CONFIG_MPC83XX_SERDES
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+#include <linux/delay.h>
+
+/* SerDes registers */
+#define FSL_SRDSCR0_OFFS		0x0
+#define FSL_SRDSCR0_DPP_1V2		0x00008800
+#define FSL_SRDSCR0_TXEQA_MASK		0x00007000
+#define FSL_SRDSCR0_TXEQA_SATA		0x00001000
+#define FSL_SRDSCR0_TXEQE_MASK		0x00000700
+#define FSL_SRDSCR0_TXEQE_SATA		0x00000100
+#define FSL_SRDSCR1_OFFS		0x4
+#define FSL_SRDSCR1_PLLBW		0x00000040
+#define FSL_SRDSCR2_OFFS		0x8
+#define FSL_SRDSCR2_VDD_1V2		0x00800000
+#define FSL_SRDSCR2_SEIC_MASK		0x00001c1c
+#define FSL_SRDSCR2_SEIC_SATA		0x00001414
+#define FSL_SRDSCR2_SEIC_PEX		0x00001010
+#define FSL_SRDSCR2_SEIC_SGMII		0x00000101
+#define FSL_SRDSCR3_OFFS		0xc
+#define FSL_SRDSCR3_KFR_SATA		0x10100000
+#define FSL_SRDSCR3_KPH_SATA		0x04040000
+#define FSL_SRDSCR3_SDFM_SATA_PEX	0x01010000
+#define FSL_SRDSCR3_SDTXL_SATA		0x00000505
+#define FSL_SRDSCR4_OFFS		0x10
+#define FSL_SRDSCR4_PROT_SATA		0x00000808
+#define FSL_SRDSCR4_PROT_PEX		0x00000101
+#define FSL_SRDSCR4_PROT_SGMII		0x00000505
+#define FSL_SRDSCR4_PLANE_X2		0x01000000
+#define FSL_SRDSRSTCTL_OFFS		0x20
+#define FSL_SRDSRSTCTL_RST		0x80000000
+#define FSL_SRDSRSTCTL_SATA_RESET	0xf
+
+void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd)
+{
+	void *regs = (void *)CONFIG_SYS_IMMR + offset;
+	u32 tmp;
+
+	/* 1.0V corevdd */
+	if (vdd) {
+		/* DPPE/DPPA = 0 */
+		tmp = in_be32(regs + FSL_SRDSCR0_OFFS);
+		tmp &= ~FSL_SRDSCR0_DPP_1V2;
+		out_be32(regs + FSL_SRDSCR0_OFFS, tmp);
+
+		/* VDD = 0 */
+		tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
+		tmp &= ~FSL_SRDSCR2_VDD_1V2;
+		out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
+	}
+
+	/* protocol specific configuration */
+	switch (proto) {
+	case FSL_SERDES_PROTO_SATA:
+		/* Set and clear reset bits */
+		tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS);
+		tmp |= FSL_SRDSRSTCTL_SATA_RESET;
+		out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
+		udelay(1000);
+		tmp &= ~FSL_SRDSRSTCTL_SATA_RESET;
+		out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
+
+		/* Configure SRDSCR0 */
+		clrsetbits_be32(regs + FSL_SRDSCR0_OFFS,
+			FSL_SRDSCR0_TXEQA_MASK | FSL_SRDSCR0_TXEQE_MASK,
+			FSL_SRDSCR0_TXEQA_SATA | FSL_SRDSCR0_TXEQE_SATA);
+
+		/* Configure SRDSCR1 */
+		tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
+		tmp &= ~FSL_SRDSCR1_PLLBW;
+		out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
+
+		/* Configure SRDSCR2 */
+		tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
+		tmp &= ~FSL_SRDSCR2_SEIC_MASK;
+		tmp |= FSL_SRDSCR2_SEIC_SATA;
+		out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
+
+		/* Configure SRDSCR3 */
+		tmp = FSL_SRDSCR3_KFR_SATA | FSL_SRDSCR3_KPH_SATA |
+			FSL_SRDSCR3_SDFM_SATA_PEX |
+			FSL_SRDSCR3_SDTXL_SATA;
+		out_be32(regs + FSL_SRDSCR3_OFFS, tmp);
+
+		/* Configure SRDSCR4 */
+		tmp = rfcks | FSL_SRDSCR4_PROT_SATA;
+		out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
+		break;
+	case FSL_SERDES_PROTO_PEX:
+	case FSL_SERDES_PROTO_PEX_X2:
+		/* Configure SRDSCR1 */
+		tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
+		tmp |= FSL_SRDSCR1_PLLBW;
+		out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
+
+		/* Configure SRDSCR2 */
+		tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
+		tmp &= ~FSL_SRDSCR2_SEIC_MASK;
+		tmp |= FSL_SRDSCR2_SEIC_PEX;
+		out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
+
+		/* Configure SRDSCR3 */
+		tmp = FSL_SRDSCR3_SDFM_SATA_PEX;
+		out_be32(regs + FSL_SRDSCR3_OFFS, tmp);
+
+		/* Configure SRDSCR4 */
+		tmp = rfcks | FSL_SRDSCR4_PROT_PEX;
+		if (proto == FSL_SERDES_PROTO_PEX_X2)
+			tmp |= FSL_SRDSCR4_PLANE_X2;
+		out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
+		break;
+	case FSL_SERDES_PROTO_SGMII:
+		/* Configure SRDSCR1 */
+		tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
+		tmp &= ~FSL_SRDSCR1_PLLBW;
+		out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
+
+		/* Configure SRDSCR2 */
+		tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
+		tmp &= ~FSL_SRDSCR2_SEIC_MASK;
+		tmp |= FSL_SRDSCR2_SEIC_SGMII;
+		out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
+
+		/* Configure SRDSCR3 */
+		out_be32(regs + FSL_SRDSCR3_OFFS, 0);
+
+		/* Configure SRDSCR4 */
+		tmp = rfcks | FSL_SRDSCR4_PROT_SGMII;
+		out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
+		break;
+	default:
+		return;
+	}
+
+	/* Do a software reset */
+	tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS);
+	tmp |= FSL_SRDSRSTCTL_RST;
+	out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
+}
+
+#endif /* !CONFIG_MPC83XX_SERDES */
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/roms/u-boot/arch/powerpc/cpu/mpc83xx/spd_sdram.c
new file mode 100644
index 000000000..a861e8dd2
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/spd_sdram.c
@@ -0,0 +1,955 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
+ * (C) Copyright 2003 Motorola Inc.
+ * Xianghua Xiao (X.Xiao@motorola.com)
+ */
+
+#ifndef CONFIG_MPC83XX_SDRAM
+
+#include <common.h>
+#include <cpu_func.h>
+#include <log.h>
+#include <time.h>
+#include <vsprintf.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include <spd.h>
+#include <asm/mmu.h>
+#include <spd_sdram.h>
+#include <asm/bitops.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_add_ram_info(int use_default)
+{
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	volatile ddr83xx_t *ddr = &immap->ddr;
+	char buf[32];
+
+	printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
+			   >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
+
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
+	if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16)
+		puts(", 16-bit");
+	else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32)
+		puts(", 32-bit");
+	else
+		puts(", unknown width");
+#else
+	if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
+		puts(", 32-bit");
+	else
+		puts(", 64-bit");
+#endif
+
+	if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
+		puts(", ECC on");
+	else
+		puts(", ECC off");
+
+	printf(", %s MHz)", strmhz(buf, gd->mem_clk));
+
+#if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE)
+	puts("\nSDRAM: ");
+	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
+#endif
+}
+
+#ifdef CONFIG_SPD_EEPROM
+#ifndef	CONFIG_SYS_READ_SPD
+#define CONFIG_SYS_READ_SPD	i2c_read
+#endif
+#ifndef SPD_EEPROM_OFFSET
+#define SPD_EEPROM_OFFSET	0
+#endif
+#ifndef SPD_EEPROM_ADDR_LEN
+#define SPD_EEPROM_ADDR_LEN     1
+#endif
+
+/*
+ * Convert picoseconds into clock cycles (rounding up if needed).
+ */
+int
+picos_to_clk(int picos)
+{
+	unsigned int mem_bus_clk;
+	int clks;
+
+	mem_bus_clk = gd->mem_clk >> 1;
+	clks = picos / (1000000000 / (mem_bus_clk / 1000));
+	if (picos % (1000000000 / (mem_bus_clk / 1000)) != 0)
+		clks++;
+
+	return clks;
+}
+
+unsigned int banksize(unsigned char row_dens)
+{
+	return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
+}
+
+int read_spd(uint addr)
+{
+	return ((int) addr);
+}
+
+#undef SPD_DEBUG
+#ifdef SPD_DEBUG
+static void spd_debug(spd_eeprom_t *spd)
+{
+	printf ("\nDIMM type:       %-18.18s\n", spd->mpart);
+	printf ("SPD size:        %d\n", spd->info_size);
+	printf ("EEPROM size:     %d\n", 1 << spd->chip_size);
+	printf ("Memory type:     %d\n", spd->mem_type);
+	printf ("Row addr:        %d\n", spd->nrow_addr);
+	printf ("Column addr:     %d\n", spd->ncol_addr);
+	printf ("# of rows:       %d\n", spd->nrows);
+	printf ("Row density:     %d\n", spd->row_dens);
+	printf ("# of banks:      %d\n", spd->nbanks);
+	printf ("Data width:      %d\n",
+			256 * spd->dataw_msb + spd->dataw_lsb);
+	printf ("Chip width:      %d\n", spd->primw);
+	printf ("Refresh rate:    %02X\n", spd->refresh);
+	printf ("CAS latencies:   %02X\n", spd->cas_lat);
+	printf ("Write latencies: %02X\n", spd->write_lat);
+	printf ("tRP:             %d\n", spd->trp);
+	printf ("tRCD:            %d\n", spd->trcd);
+	printf ("\n");
+}
+#endif /* SPD_DEBUG */
+
+long int spd_sdram()
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile ddr83xx_t *ddr = &immap->ddr;
+	volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
+	spd_eeprom_t spd;
+	unsigned int n_ranks;
+	unsigned int odt_rd_cfg, odt_wr_cfg;
+	unsigned char twr_clk, twtr_clk;
+	unsigned int sdram_type;
+	unsigned int memsize;
+	unsigned int law_size;
+	unsigned char caslat, caslat_ctrl;
+	unsigned int trfc, trfc_clk, trfc_low;
+	unsigned int trcd_clk, trtp_clk;
+	unsigned char cke_min_clk;
+	unsigned char add_lat, wr_lat;
+	unsigned char wr_data_delay;
+	unsigned char four_act;
+	unsigned char cpo;
+	unsigned char burstlen;
+	unsigned char odt_cfg, mode_odt_enable;
+	unsigned int max_bus_clk;
+	unsigned int max_data_rate, effective_data_rate;
+	unsigned int ddrc_clk;
+	unsigned int refresh_clk;
+	unsigned int sdram_cfg;
+	unsigned int ddrc_ecc_enable;
+	unsigned int pvr = get_pvr();
+
+	/*
+	 * First disable the memory controller (could be enabled
+	 * by the debugger)
+	 */
+	clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0);
+	sync();
+	isync();
+
+	/* Read SPD parameters with I2C */
+	CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, SPD_EEPROM_OFFSET,
+		SPD_EEPROM_ADDR_LEN, (uchar *) &spd, sizeof(spd));
+#ifdef SPD_DEBUG
+	spd_debug(&spd);
+#endif
+	/* Check the memory type */
+	if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) {
+		debug("DDR: Module mem type is %02X\n", spd.mem_type);
+		return 0;
+	}
+
+	/* Check the number of physical bank */
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		n_ranks = spd.nrows;
+	} else {
+		n_ranks = (spd.nrows & 0x7) + 1;
+	}
+
+	if (n_ranks > 2) {
+		printf("DDR: The number of physical bank is %02X\n", n_ranks);
+		return 0;
+	}
+
+	/* Check if the number of row of the module is in the range of DDRC */
+	if (spd.nrow_addr < 12 || spd.nrow_addr > 15) {
+		printf("DDR: Row number is out of range of DDRC, row=%02X\n",
+							 spd.nrow_addr);
+		return 0;
+	}
+
+	/* Check if the number of col of the module is in the range of DDRC */
+	if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
+		printf("DDR: Col number is out of range of DDRC, col=%02X\n",
+							 spd.ncol_addr);
+		return 0;
+	}
+
+#ifdef CONFIG_SYS_DDRCDR_VALUE
+	/*
+	 * Adjust DDR II IO voltage biasing.  It just makes it work.
+	 */
+	if(spd.mem_type == SPD_MEMTYPE_DDR2) {
+		immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
+	}
+	udelay(50000);
+#endif
+
+	/*
+	 * ODT configuration recommendation from DDR Controller Chapter.
+	 */
+	odt_rd_cfg = 0;			/* Never assert ODT */
+	odt_wr_cfg = 0;			/* Never assert ODT */
+	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+		odt_wr_cfg = 1;		/* Assert ODT on writes to CSn */
+	}
+
+	/* Setup DDR chip select register */
+#ifdef CONFIG_SYS_83XX_DDR_USES_CS0
+	ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
+	ddr->cs_config[0] = ( 1 << 31
+			    | (odt_rd_cfg << 20)
+			    | (odt_wr_cfg << 16)
+			    | ((spd.nbanks == 8 ? 1 : 0) << 14)
+			    | ((spd.nrow_addr - 12) << 8)
+			    | (spd.ncol_addr - 8) );
+	debug("\n");
+	debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
+	debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
+
+	if (n_ranks == 2) {
+		ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
+				  | ((banksize(spd.row_dens) >> 23) - 1) );
+		ddr->cs_config[1] = ( 1<<31
+				    | (odt_rd_cfg << 20)
+				    | (odt_wr_cfg << 16)
+				    | ((spd.nbanks == 8 ? 1 : 0) << 14)
+				    | ((spd.nrow_addr - 12) << 8)
+				    | (spd.ncol_addr - 8) );
+		debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
+		debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
+	}
+
+#else
+	ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
+	ddr->cs_config[2] = ( 1 << 31
+			    | (odt_rd_cfg << 20)
+			    | (odt_wr_cfg << 16)
+			    | ((spd.nbanks == 8 ? 1 : 0) << 14)
+			    | ((spd.nrow_addr - 12) << 8)
+			    | (spd.ncol_addr - 8) );
+	debug("\n");
+	debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
+	debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
+
+	if (n_ranks == 2) {
+		ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
+				  | ((banksize(spd.row_dens) >> 23) - 1) );
+		ddr->cs_config[3] = ( 1<<31
+				    | (odt_rd_cfg << 20)
+				    | (odt_wr_cfg << 16)
+				    | ((spd.nbanks == 8 ? 1 : 0) << 14)
+				    | ((spd.nrow_addr - 12) << 8)
+				    | (spd.ncol_addr - 8) );
+		debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
+		debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
+	}
+#endif
+
+	/*
+	 * Figure out memory size in Megabytes.
+	 */
+	memsize = n_ranks * banksize(spd.row_dens) / 0x100000;
+
+	/*
+	 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
+	 */
+	law_size = 19 + __ilog2(memsize);
+
+	/*
+	 * Set up LAWBAR for all of DDR.
+	 */
+	ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
+	ecm->ar  = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
+	debug("DDR:bar=0x%08x\n", ecm->bar);
+	debug("DDR:ar=0x%08x\n", ecm->ar);
+
+	/*
+	 * Find the largest CAS by locating the highest 1 bit
+	 * in the spd.cas_lat field.  Translate it to a DDR
+	 * controller field value:
+	 *
+	 *	CAS Lat	DDR I	DDR II	Ctrl
+	 *	Clocks	SPD Bit	SPD Bit	Value
+	 *	-------	-------	-------	-----
+	 *	1.0	0		0001
+	 *	1.5	1		0010
+	 *	2.0	2	2	0011
+	 *	2.5	3		0100
+	 *	3.0	4	3	0101
+	 *	3.5	5		0110
+	 *	4.0	6	4	0111
+	 *	4.5			1000
+	 *	5.0		5	1001
+	 */
+	caslat = __ilog2(spd.cas_lat);
+	if ((spd.mem_type == SPD_MEMTYPE_DDR)
+	    && (caslat > 6)) {
+		printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
+		return 0;
+	} else if (spd.mem_type == SPD_MEMTYPE_DDR2
+		   && (caslat < 2 || caslat > 5)) {
+		printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
+		       spd.cas_lat);
+		return 0;
+	}
+	debug("DDR: caslat SPD bit is %d\n", caslat);
+
+	max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
+			+ (spd.clk_cycle & 0x0f));
+	max_data_rate = max_bus_clk * 2;
+
+	debug("DDR:Module maximum data rate is: %d MHz\n", max_data_rate);
+
+	ddrc_clk = gd->mem_clk / 1000000;
+	effective_data_rate = 0;
+
+	if (max_data_rate >= 460) { /* it is DDR2-800, 667, 533 */
+		if (spd.cas_lat & 0x08)
+			caslat = 3;
+		else
+			caslat = 4;
+		if (ddrc_clk <= 460 && ddrc_clk > 350)
+			effective_data_rate = 400;
+		else if (ddrc_clk <=350 && ddrc_clk > 280)
+			effective_data_rate = 333;
+		else if (ddrc_clk <= 280 && ddrc_clk > 230)
+			effective_data_rate = 266;
+		else
+			effective_data_rate = 200;
+	} else if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
+		if (ddrc_clk <= 460 && ddrc_clk > 350) {
+			/* DDR controller clk at 350~460 */
+			effective_data_rate = 400; /* 5ns */
+			caslat = caslat;
+		} else if (ddrc_clk <= 350 && ddrc_clk > 280) {
+			/* DDR controller clk at 280~350 */
+			effective_data_rate = 333; /* 6ns */
+			if (spd.clk_cycle2 == 0x60)
+				caslat = caslat - 1;
+			else
+				caslat = caslat;
+		} else if (ddrc_clk <= 280 && ddrc_clk > 230) {
+			/* DDR controller clk at 230~280 */
+			effective_data_rate = 266; /* 7.5ns */
+			if (spd.clk_cycle3 == 0x75)
+				caslat = caslat - 2;
+			else if (spd.clk_cycle2 == 0x75)
+				caslat = caslat - 1;
+			else
+				caslat = caslat;
+		} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
+			/* DDR controller clk at 90~230 */
+			effective_data_rate = 200; /* 10ns */
+			if (spd.clk_cycle3 == 0xa0)
+				caslat = caslat - 2;
+			else if (spd.clk_cycle2 == 0xa0)
+				caslat = caslat - 1;
+			else
+				caslat = caslat;
+		}
+	} else if (max_data_rate >= 323) { /* it is DDR 333 */
+		if (ddrc_clk <= 350 && ddrc_clk > 280) {
+			/* DDR controller clk at 280~350 */
+			effective_data_rate = 333; /* 6ns */
+			caslat = caslat;
+		} else if (ddrc_clk <= 280 && ddrc_clk > 230) {
+			/* DDR controller clk at 230~280 */
+			effective_data_rate = 266; /* 7.5ns */
+			if (spd.clk_cycle2 == 0x75)
+				caslat = caslat - 1;
+			else
+				caslat = caslat;
+		} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
+			/* DDR controller clk at 90~230 */
+			effective_data_rate = 200; /* 10ns */
+			if (spd.clk_cycle3 == 0xa0)
+				caslat = caslat - 2;
+			else if (spd.clk_cycle2 == 0xa0)
+				caslat = caslat - 1;
+			else
+				caslat = caslat;
+		}
+	} else if (max_data_rate >= 256) { /* it is DDR 266 */
+		if (ddrc_clk <= 350 && ddrc_clk > 280) {
+			/* DDR controller clk at 280~350 */
+			printf("DDR: DDR controller freq is more than "
+				"max data rate of the module\n");
+			return 0;
+		} else if (ddrc_clk <= 280 && ddrc_clk > 230) {
+			/* DDR controller clk at 230~280 */
+			effective_data_rate = 266; /* 7.5ns */
+			caslat = caslat;
+		} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
+			/* DDR controller clk at 90~230 */
+			effective_data_rate = 200; /* 10ns */
+			if (spd.clk_cycle2 == 0xa0)
+				caslat = caslat - 1;
+		}
+	} else if (max_data_rate >= 190) { /* it is DDR 200 */
+		if (ddrc_clk <= 350 && ddrc_clk > 230) {
+			/* DDR controller clk at 230~350 */
+			printf("DDR: DDR controller freq is more than "
+				"max data rate of the module\n");
+			return 0;
+		} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
+			/* DDR controller clk at 90~230 */
+			effective_data_rate = 200; /* 10ns */
+			caslat = caslat;
+		}
+	}
+
+	debug("DDR:Effective data rate is: %dMHz\n", effective_data_rate);
+	debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
+
+	/*
+	 * Errata DDR6 work around: input enable 2 cycles earlier.
+	 * including MPC834X Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
+	 */
+	if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
+		if (caslat == 2)
+			ddr->debug_reg = 0x201c0000; /* CL=2 */
+		else if (caslat == 3)
+			ddr->debug_reg = 0x202c0000; /* CL=2.5 */
+		else if (caslat == 4)
+			ddr->debug_reg = 0x202c0000; /* CL=3.0 */
+
+		sync();
+
+		debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
+	}
+
+	/*
+	 * Convert caslat clocks to DDR controller value.
+	 * Force caslat_ctrl to be DDR Controller field-sized.
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		caslat_ctrl = (caslat + 1) & 0x07;
+	} else {
+		caslat_ctrl =  (2 * caslat - 1) & 0x0f;
+	}
+
+	debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
+	debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
+	      caslat, caslat_ctrl);
+
+	/*
+	 * Timing Config 0.
+	 * Avoid writing for DDR I.
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+		unsigned char taxpd_clk = 8;		/* By the book. */
+		unsigned char tmrd_clk = 2;		/* By the book. */
+		unsigned char act_pd_exit = 2;		/* Empirical? */
+		unsigned char pre_pd_exit = 6;		/* Empirical? */
+
+		ddr->timing_cfg_0 = (0
+			| ((act_pd_exit & 0x7) << 20)	/* ACT_PD_EXIT */
+			| ((pre_pd_exit & 0x7) << 16)	/* PRE_PD_EXIT */
+			| ((taxpd_clk & 0xf) << 8)	/* ODT_PD_EXIT */
+			| ((tmrd_clk & 0xf) << 0)	/* MRS_CYC */
+			);
+		debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
+	}
+
+	/*
+	 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
+	 * use conservative value.
+	 * For DDR II, they are bytes 36 and 37, in quarter nanos.
+	 */
+
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		twr_clk = 3;	/* Clocks */
+		twtr_clk = 1;	/* Clocks */
+	} else {
+		twr_clk = picos_to_clk(spd.twr * 250);
+		twtr_clk = picos_to_clk(spd.twtr * 250);
+		if (twtr_clk < 2)
+			twtr_clk = 2;
+	}
+
+	/*
+	 * Calculate Trfc, in picos.
+	 * DDR I:  Byte 42 straight up in ns.
+	 * DDR II: Byte 40 and 42 swizzled some, in ns.
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		trfc = spd.trfc * 1000;		/* up to ps */
+	} else {
+		unsigned int byte40_table_ps[8] = {
+			0,
+			250,
+			330,
+			500,
+			660,
+			750,
+			0,
+			0
+		};
+
+		trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
+			+ byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
+	}
+	trfc_clk = picos_to_clk(trfc);
+
+	/*
+	 * Trcd, Byte 29, from quarter nanos to ps and clocks.
+	 */
+	trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
+
+	/*
+	 * Convert trfc_clk to DDR controller fields.  DDR I should
+	 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
+	 * 83xx controller has an extended REFREC field of three bits.
+	 * The controller automatically adds 8 clocks to this value,
+	 * so preadjust it down 8 first before splitting it up.
+	 */
+	trfc_low = (trfc_clk - 8) & 0xf;
+
+	ddr->timing_cfg_1 =
+	    (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |	/* PRETOACT */
+	     ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
+	     (trcd_clk << 20 ) |				/* ACTTORW */
+	     (caslat_ctrl << 16 ) |				/* CASLAT */
+	     (trfc_low << 12 ) |				/* REFEC */
+	     ((twr_clk & 0x07) << 8) |				/* WRRREC */
+	     ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) |	/* ACTTOACT */
+	     ((twtr_clk & 0x07) << 0)				/* WRTORD */
+	    );
+
+	/*
+	 * Additive Latency
+	 * For DDR I, 0.
+	 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
+	 * which comes from Trcd, and also note that:
+	 *	add_lat + caslat must be >= 4
+	 */
+	add_lat = 0;
+	if (spd.mem_type == SPD_MEMTYPE_DDR2
+	    && (odt_wr_cfg || odt_rd_cfg)
+	    && (caslat < 4)) {
+		add_lat = 4 - caslat;
+		if ((add_lat + caslat) < 4) {
+			add_lat = 0;
+		}
+	}
+
+	/*
+	 * Write Data Delay
+	 * Historically 0x2 == 4/8 clock delay.
+	 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
+	 */
+	wr_data_delay = 2;
+#ifdef CONFIG_SYS_DDR_WRITE_DATA_DELAY
+	wr_data_delay = CONFIG_SYS_DDR_WRITE_DATA_DELAY;
+#endif
+
+	/*
+	 * Write Latency
+	 * Read to Precharge
+	 * Minimum CKE Pulse Width.
+	 * Four Activate Window
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		/*
+		 * This is a lie.  It should really be 1, but if it is
+		 * set to 1, bits overlap into the old controller's
+		 * otherwise unused ACSM field.  If we leave it 0, then
+		 * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
+		 */
+		wr_lat = 0;
+
+		trtp_clk = 2;		/* By the book. */
+		cke_min_clk = 1;	/* By the book. */
+		four_act = 1;		/* By the book. */
+
+	} else {
+		wr_lat = caslat - 1;
+
+		/* Convert SPD value from quarter nanos to picos. */
+		trtp_clk = picos_to_clk(spd.trtp * 250);
+		if (trtp_clk < 2)
+			trtp_clk = 2;
+		trtp_clk += add_lat;
+
+		cke_min_clk = 3;	/* By the book. */
+		four_act = picos_to_clk(37500);	/* By the book. 1k pages? */
+	}
+
+	/*
+	 * Empirically set ~MCAS-to-preamble override for DDR 2.
+	 * Your mileage will vary.
+	 */
+	cpo = 0;
+	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+#ifdef CONFIG_SYS_DDR_CPO
+		cpo = CONFIG_SYS_DDR_CPO;
+#else
+		if (effective_data_rate == 266) {
+			cpo = 0x4;		/* READ_LAT + 1/2 */
+		} else if (effective_data_rate == 333) {
+			cpo = 0x6;		/* READ_LAT + 1 */
+		} else if (effective_data_rate == 400) {
+			cpo = 0x7;		/* READ_LAT + 5/4 */
+		} else {
+			/* Automatic calibration */
+			cpo = 0x1f;
+		}
+#endif
+	}
+
+	ddr->timing_cfg_2 = (0
+		| ((add_lat & 0x7) << 28)		/* ADD_LAT */
+		| ((cpo & 0x1f) << 23)			/* CPO */
+		| ((wr_lat & 0x7) << 19)		/* WR_LAT */
+		| ((trtp_clk & 0x7) << 13)		/* RD_TO_PRE */
+		| ((wr_data_delay & 0x7) << 10)		/* WR_DATA_DELAY */
+		| ((cke_min_clk & 0x7) << 6)		/* CKE_PLS */
+		| ((four_act & 0x1f) << 0)		/* FOUR_ACT */
+		);
+
+	debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
+	debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
+
+	/* Check DIMM data bus width */
+	if (spd.dataw_lsb < 64) {
+		if (spd.mem_type == SPD_MEMTYPE_DDR)
+			burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
+		else
+			burstlen = 0x02; /* 32 bit data bus, burst len is 4 */
+		debug("\n   DDR DIMM: data bus width is 32 bit");
+	} else {
+		burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
+		debug("\n   DDR DIMM: data bus width is 64 bit");
+	}
+
+	/* Is this an ECC DDR chip? */
+	if (spd.config == 0x02)
+		debug(" with ECC\n");
+	else
+		debug(" without ECC\n");
+
+	/* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
+	   Burst type is sequential
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		switch (caslat) {
+		case 1:
+			ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
+			break;
+		case 2:
+			ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
+			break;
+		case 3:
+			ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
+			break;
+		case 4:
+			ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
+			break;
+		default:
+			printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
+			return 0;
+		}
+	} else {
+		mode_odt_enable = 0x0;                  /* Default disabled */
+		if (odt_wr_cfg || odt_rd_cfg) {
+			/*
+			 * Bits 6 and 2 in Extended MRS(1)
+			 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
+			 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
+			 */
+			mode_odt_enable = 0x40;         /* 150 Ohm */
+		}
+
+		ddr->sdram_mode =
+			(0
+			 | (1 << (16 + 10))             /* DQS Differential disable */
+#ifdef CONFIG_SYS_DDR_MODE_WEAK
+			 | (1 << (16 + 1))		/* weak driver (~60%) */
+#endif
+			 | (add_lat << (16 + 3))        /* Additive Latency in EMRS1 */
+			 | (mode_odt_enable << 16)      /* ODT Enable in EMRS1 */
+			 | ((twr_clk - 1) << 9)         /* Write Recovery Autopre */
+			 | (caslat << 4)                /* caslat */
+			 | (burstlen << 0)              /* Burst length */
+			);
+	}
+	debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
+
+	/*
+	 * Clear EMRS2 and EMRS3.
+	 */
+	ddr->sdram_mode2 = 0;
+	debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2);
+
+	switch (spd.refresh) {
+		case 0x00:
+		case 0x80:
+			refresh_clk = picos_to_clk(15625000);
+			break;
+		case 0x01:
+		case 0x81:
+			refresh_clk = picos_to_clk(3900000);
+			break;
+		case 0x02:
+		case 0x82:
+			refresh_clk = picos_to_clk(7800000);
+			break;
+		case 0x03:
+		case 0x83:
+			refresh_clk = picos_to_clk(31300000);
+			break;
+		case 0x04:
+		case 0x84:
+			refresh_clk = picos_to_clk(62500000);
+			break;
+		case 0x05:
+		case 0x85:
+			refresh_clk = picos_to_clk(125000000);
+			break;
+		default:
+			refresh_clk = 0x512;
+			break;
+	}
+
+	/*
+	 * Set BSTOPRE to 0x100 for page mode
+	 * If auto-charge is used, set BSTOPRE = 0
+	 */
+	ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
+	debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
+
+	/*
+	 * SDRAM Cfg 2
+	 */
+	odt_cfg = 0;
+#ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU
+	if (odt_rd_cfg | odt_wr_cfg) {
+		odt_cfg = 0x2;		/* ODT to IOs during reads */
+	}
+#endif
+	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+		ddr->sdram_cfg2 = (0
+			    | (0 << 26)	/* True DQS */
+			    | (odt_cfg << 21)	/* ODT only read */
+			    | (1 << 12)	/* 1 refresh at a time */
+			    );
+
+		debug("DDR: sdram_cfg2  = 0x%08x\n", ddr->sdram_cfg2);
+	}
+
+#ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL	/* Optional platform specific value */
+	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
+#endif
+	debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
+
+	sync();
+	isync();
+
+	udelay(600);
+
+	/*
+	 * Figure out the settings for the sdram_cfg register. Build up
+	 * the value in 'sdram_cfg' before writing since the write into
+	 * the register will actually enable the memory controller, and all
+	 * settings must be done before enabling.
+	 *
+	 * sdram_cfg[0]   = 1 (ddr sdram logic enable)
+	 * sdram_cfg[1]   = 1 (self-refresh-enable)
+	 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
+	 *			010 DDR 1 SDRAM
+	 *			011 DDR 2 SDRAM
+	 * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
+	 * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR)
+		sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1;
+	else
+		sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR2;
+
+	sdram_cfg = (0
+		     | SDRAM_CFG_MEM_EN		/* DDR enable */
+		     | SDRAM_CFG_SREN		/* Self refresh */
+		     | sdram_type		/* SDRAM type */
+		     );
+
+	/* sdram_cfg[3] = RD_EN - registered DIMM enable */
+	if (spd.mod_attr & 0x02)
+		sdram_cfg |= SDRAM_CFG_RD_EN;
+
+	/* The DIMM is 32bit width */
+	if (spd.dataw_lsb < 64) {
+		if (spd.mem_type == SPD_MEMTYPE_DDR)
+			sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
+		if (spd.mem_type == SPD_MEMTYPE_DDR2)
+			sdram_cfg |= SDRAM_CFG_32_BE;
+	}
+
+	ddrc_ecc_enable = 0;
+
+#if defined(CONFIG_DDR_ECC)
+	/* Enable ECC with sdram_cfg[2] */
+	if (spd.config == 0x02) {
+		sdram_cfg |= 0x20000000;
+		ddrc_ecc_enable = 1;
+		/* disable error detection */
+		ddr->err_disable = ~ECC_ERROR_ENABLE;
+		/* set single bit error threshold to maximum value,
+		 * reset counter to zero */
+		ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
+				(0 << ECC_ERROR_MAN_SBEC_SHIFT);
+	}
+
+	debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
+	debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
+#endif
+	debug("   DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
+
+#if defined(CONFIG_DDR_2T_TIMING)
+	/*
+	 * Enable 2T timing by setting sdram_cfg[16].
+	 */
+	sdram_cfg |= SDRAM_CFG_2T_EN;
+#endif
+	/* Enable controller, and GO! */
+	ddr->sdram_cfg = sdram_cfg;
+	sync();
+	isync();
+	udelay(500);
+
+	debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
+	return memsize; /*in MBytes*/
+}
+#endif /* CONFIG_SPD_EEPROM */
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+static inline u32 mftbu(void)
+{
+	u32 rval;
+
+	asm volatile("mftbu %0" : "=r" (rval));
+	return rval;
+}
+
+static inline u32 mftb(void)
+{
+	u32 rval;
+
+	asm volatile("mftb %0" : "=r" (rval));
+	return rval;
+}
+
+/*
+ * Use timebase counter, get_timer() is not available
+ * at this point of initialization yet.
+ */
+static __inline__ unsigned long get_tbms (void)
+{
+	unsigned long tbl;
+	unsigned long tbu1, tbu2;
+	unsigned long ms;
+	unsigned long long tmp;
+
+	ulong tbclk = get_tbclk();
+
+	/* get the timebase ticks */
+	do {
+		tbu1 = mftbu();
+		tbl = mftb();
+		tbu2 = mftbu();
+	} while (tbu1 != tbu2);
+
+	/* convert ticks to ms */
+	tmp = (unsigned long long)(tbu1);
+	tmp = (tmp << 32);
+	tmp += (unsigned long long)(tbl);
+	ms = tmp/(tbclk/1000);
+
+	return ms;
+}
+
+/*
+ * Initialize all of memory for ECC, then enable errors.
+ */
+void ddr_enable_ecc(unsigned int dram_size)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile ddr83xx_t *ddr= &immap->ddr;
+	unsigned long t_start, t_end;
+	register u64 *p;
+	register uint size;
+	unsigned int pattern[2];
+
+	icache_enable();
+	t_start = get_tbms();
+	pattern[0] = 0xdeadbeef;
+	pattern[1] = 0xdeadbeef;
+
+#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
+	dma_meminit(pattern[0], dram_size);
+#else
+	debug("ddr init: CPU FP write method\n");
+	size = dram_size;
+	for (p = 0; p < (u64*)(size); p++) {
+		ppcDWstore((u32*)p, pattern);
+	}
+	sync();
+#endif
+
+	t_end = get_tbms();
+	icache_disable();
+
+	debug("\nREADY!!\n");
+	debug("ddr init duration: %ld ms\n", t_end - t_start);
+
+	/* Clear All ECC Errors */
+	if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
+		ddr->err_detect |= ECC_ERROR_DETECT_MME;
+	if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
+		ddr->err_detect |= ECC_ERROR_DETECT_MBE;
+	if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
+		ddr->err_detect |= ECC_ERROR_DETECT_SBE;
+	if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
+		ddr->err_detect |= ECC_ERROR_DETECT_MSE;
+
+	/* Disable ECC-Interrupts */
+	ddr->err_int_en &= ECC_ERR_INT_DISABLE;
+
+	/* Enable errors for ECC */
+	ddr->err_disable &= ECC_ERROR_ENABLE;
+
+	sync();
+	isync();
+}
+#endif	/* CONFIG_DDR_ECC */
+
+#endif /* !CONFIG_MPC83XX_SDRAM */
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/speed.c b/roms/u-boot/arch/powerpc/cpu/mpc83xx/speed.c
new file mode 100644
index 000000000..58e197f12
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/speed.c
@@ -0,0 +1,605 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ */
+
+#ifndef CONFIG_CLK_MPC83XX
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <mpc83xx.h>
+#include <command.h>
+#include <vsprintf.h>
+#include <asm/global_data.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ----------------------------------------------------------------- */
+
+typedef enum {
+	_unk,
+	_off,
+	_byp,
+	_x8,
+	_x4,
+	_x2,
+	_x1,
+	_1x,
+	_1_5x,
+	_2x,
+	_2_5x,
+	_3x
+} mult_t;
+
+typedef struct {
+	mult_t core_csb_ratio;
+	mult_t vco_divider;
+} corecnf_t;
+
+static corecnf_t corecnf_tab[] = {
+	{_byp, _byp},		/* 0x00 */
+	{_byp, _byp},		/* 0x01 */
+	{_byp, _byp},		/* 0x02 */
+	{_byp, _byp},		/* 0x03 */
+	{_byp, _byp},		/* 0x04 */
+	{_byp, _byp},		/* 0x05 */
+	{_byp, _byp},		/* 0x06 */
+	{_byp, _byp},		/* 0x07 */
+	{_1x, _x2},		/* 0x08 */
+	{_1x, _x4},		/* 0x09 */
+	{_1x, _x8},		/* 0x0A */
+	{_1x, _x8},		/* 0x0B */
+	{_1_5x, _x2},		/* 0x0C */
+	{_1_5x, _x4},		/* 0x0D */
+	{_1_5x, _x8},		/* 0x0E */
+	{_1_5x, _x8},		/* 0x0F */
+	{_2x, _x2},		/* 0x10 */
+	{_2x, _x4},		/* 0x11 */
+	{_2x, _x8},		/* 0x12 */
+	{_2x, _x8},		/* 0x13 */
+	{_2_5x, _x2},		/* 0x14 */
+	{_2_5x, _x4},		/* 0x15 */
+	{_2_5x, _x8},		/* 0x16 */
+	{_2_5x, _x8},		/* 0x17 */
+	{_3x, _x2},		/* 0x18 */
+	{_3x, _x4},		/* 0x19 */
+	{_3x, _x8},		/* 0x1A */
+	{_3x, _x8},		/* 0x1B */
+};
+
+/* ----------------------------------------------------------------- */
+
+/*
+ *
+ */
+int get_clocks(void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 pci_sync_in;
+	u8 spmf;
+	u8 clkin_div;
+	u32 sccr;
+	u32 corecnf_tab_index;
+	u8 corepll;
+	u32 lcrr;
+
+	u32 csb_clk;
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+	defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
+	u32 tsec1_clk;
+	u32 tsec2_clk;
+	u32 usbdr_clk;
+#elif defined(CONFIG_ARCH_MPC8309)
+	u32 usbdr_clk;
+#endif
+#ifdef CONFIG_ARCH_MPC834X
+	u32 usbmph_clk;
+#endif
+	u32 core_clk;
+	u32 i2c1_clk;
+#if !defined(CONFIG_ARCH_MPC832X)
+	u32 i2c2_clk;
+#endif
+#if defined(CONFIG_ARCH_MPC8315)
+	u32 tdm_clk;
+#endif
+#if defined(CONFIG_FSL_ESDHC)
+	u32 sdhc_clk;
+#endif
+#if !defined(CONFIG_ARCH_MPC8309)
+	u32 enc_clk;
+#endif
+	u32 lbiu_clk;
+	u32 lclk_clk;
+	u32 mem_clk;
+#if defined(CONFIG_ARCH_MPC8360)
+	u32 mem_sec_clk;
+#endif
+#if defined(CONFIG_QE)
+	u32 qepmf;
+	u32 qepdf;
+	u32 qe_clk;
+	u32 brg_clk;
+#endif
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+	defined(CONFIG_ARCH_MPC837X)
+	u32 pciexp1_clk;
+	u32 pciexp2_clk;
+#endif
+#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
+	u32 sata_clk;
+#endif
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+		return -1;
+
+	clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
+
+	if (im->reset.rcwh & HRCWH_PCI_HOST) {
+#if defined(CONFIG_SYS_CLK_FREQ)
+		pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
+#else
+		pci_sync_in = 0xDEADBEEF;
+#endif
+	} else {
+#if defined(CONFIG_83XX_PCICLK)
+		pci_sync_in = CONFIG_83XX_PCICLK;
+#else
+		pci_sync_in = 0xDEADBEEF;
+#endif
+	}
+
+	spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
+	csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
+
+	sccr = im->clk.sccr;
+
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+	defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
+	switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
+	case 0:
+		tsec1_clk = 0;
+		break;
+	case 1:
+		tsec1_clk = csb_clk;
+		break;
+	case 2:
+		tsec1_clk = csb_clk / 2;
+		break;
+	case 3:
+		tsec1_clk = csb_clk / 3;
+		break;
+	default:
+		/* unknown SCCR_TSEC1CM value */
+		return -2;
+	}
+#endif
+
+#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \
+	defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
+	switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
+	case 0:
+		usbdr_clk = 0;
+		break;
+	case 1:
+		usbdr_clk = csb_clk;
+		break;
+	case 2:
+		usbdr_clk = csb_clk / 2;
+		break;
+	case 3:
+		usbdr_clk = csb_clk / 3;
+		break;
+	default:
+		/* unknown SCCR_USBDRCM value */
+		return -3;
+	}
+#endif
+
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \
+	defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
+	switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
+	case 0:
+		tsec2_clk = 0;
+		break;
+	case 1:
+		tsec2_clk = csb_clk;
+		break;
+	case 2:
+		tsec2_clk = csb_clk / 2;
+		break;
+	case 3:
+		tsec2_clk = csb_clk / 3;
+		break;
+	default:
+		/* unknown SCCR_TSEC2CM value */
+		return -4;
+	}
+#elif defined(CONFIG_ARCH_MPC8313)
+	tsec2_clk = tsec1_clk;
+
+	if (!(sccr & SCCR_TSEC1ON))
+		tsec1_clk = 0;
+	if (!(sccr & SCCR_TSEC2ON))
+		tsec2_clk = 0;
+#endif
+
+#if defined(CONFIG_ARCH_MPC834X)
+	switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
+	case 0:
+		usbmph_clk = 0;
+		break;
+	case 1:
+		usbmph_clk = csb_clk;
+		break;
+	case 2:
+		usbmph_clk = csb_clk / 2;
+		break;
+	case 3:
+		usbmph_clk = csb_clk / 3;
+		break;
+	default:
+		/* unknown SCCR_USBMPHCM value */
+		return -5;
+	}
+
+	if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
+		/* if USB MPH clock is not disabled and
+		 * USB DR clock is not disabled then
+		 * USB MPH & USB DR must have the same rate
+		 */
+		return -6;
+	}
+#endif
+#if !defined(CONFIG_ARCH_MPC8309)
+	switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
+	case 0:
+		enc_clk = 0;
+		break;
+	case 1:
+		enc_clk = csb_clk;
+		break;
+	case 2:
+		enc_clk = csb_clk / 2;
+		break;
+	case 3:
+		enc_clk = csb_clk / 3;
+		break;
+	default:
+		/* unknown SCCR_ENCCM value */
+		return -7;
+	}
+#endif
+
+#if defined(CONFIG_FSL_ESDHC)
+	switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
+	case 0:
+		sdhc_clk = 0;
+		break;
+	case 1:
+		sdhc_clk = csb_clk;
+		break;
+	case 2:
+		sdhc_clk = csb_clk / 2;
+		break;
+	case 3:
+		sdhc_clk = csb_clk / 3;
+		break;
+	default:
+		/* unknown SCCR_SDHCCM value */
+		return -8;
+	}
+#endif
+#if defined(CONFIG_ARCH_MPC8315)
+	switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
+	case 0:
+		tdm_clk = 0;
+		break;
+	case 1:
+		tdm_clk = csb_clk;
+		break;
+	case 2:
+		tdm_clk = csb_clk / 2;
+		break;
+	case 3:
+		tdm_clk = csb_clk / 3;
+		break;
+	default:
+		/* unknown SCCR_TDMCM value */
+		return -8;
+	}
+#endif
+
+#if defined(CONFIG_ARCH_MPC834X)
+	i2c1_clk = tsec2_clk;
+#elif defined(CONFIG_ARCH_MPC8360)
+	i2c1_clk = csb_clk;
+#elif defined(CONFIG_ARCH_MPC832X)
+	i2c1_clk = enc_clk;
+#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
+	i2c1_clk = enc_clk;
+#elif defined(CONFIG_FSL_ESDHC)
+	i2c1_clk = sdhc_clk;
+#elif defined(CONFIG_ARCH_MPC837X)
+	i2c1_clk = enc_clk;
+#elif defined(CONFIG_ARCH_MPC8309)
+	i2c1_clk = csb_clk;
+#endif
+#if !defined(CONFIG_ARCH_MPC832X)
+	i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
+#endif
+
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+	defined(CONFIG_ARCH_MPC837X)
+	switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
+	case 0:
+		pciexp1_clk = 0;
+		break;
+	case 1:
+		pciexp1_clk = csb_clk;
+		break;
+	case 2:
+		pciexp1_clk = csb_clk / 2;
+		break;
+	case 3:
+		pciexp1_clk = csb_clk / 3;
+		break;
+	default:
+		/* unknown SCCR_PCIEXP1CM value */
+		return -9;
+	}
+
+	switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
+	case 0:
+		pciexp2_clk = 0;
+		break;
+	case 1:
+		pciexp2_clk = csb_clk;
+		break;
+	case 2:
+		pciexp2_clk = csb_clk / 2;
+		break;
+	case 3:
+		pciexp2_clk = csb_clk / 3;
+		break;
+	default:
+		/* unknown SCCR_PCIEXP2CM value */
+		return -10;
+	}
+#endif
+
+#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
+	switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
+	case 0:
+		sata_clk = 0;
+		break;
+	case 1:
+		sata_clk = csb_clk;
+		break;
+	case 2:
+		sata_clk = csb_clk / 2;
+		break;
+	case 3:
+		sata_clk = csb_clk / 3;
+		break;
+	default:
+		/* unknown SCCR_SATA1CM value */
+		return -11;
+	}
+#endif
+
+	lbiu_clk = csb_clk *
+		   (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
+	lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
+	switch (lcrr) {
+	case 2:
+	case 4:
+	case 8:
+		lclk_clk = lbiu_clk / lcrr;
+		break;
+	default:
+		/* unknown lcrr */
+		return -12;
+	}
+
+	mem_clk = csb_clk *
+		  (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
+	corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
+
+#if defined(CONFIG_ARCH_MPC8360)
+	mem_sec_clk = csb_clk * (1 +
+		       ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
+#endif
+
+	corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
+	if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) {
+		/* corecnf_tab_index is too high, possibly wrong value */
+		return -11;
+	}
+	switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
+	case _byp:
+	case _x1:
+	case _1x:
+		core_clk = csb_clk;
+		break;
+	case _1_5x:
+		core_clk = (3 * csb_clk) / 2;
+		break;
+	case _2x:
+		core_clk = 2 * csb_clk;
+		break;
+	case _2_5x:
+		core_clk = (5 * csb_clk) / 2;
+		break;
+	case _3x:
+		core_clk = 3 * csb_clk;
+		break;
+	default:
+		/* unknown core to csb ratio */
+		return -13;
+	}
+
+#if defined(CONFIG_QE)
+	qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
+	qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
+	qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
+	brg_clk = qe_clk / 2;
+#endif
+
+	gd->arch.csb_clk = csb_clk;
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+	defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
+	gd->arch.tsec1_clk = tsec1_clk;
+	gd->arch.tsec2_clk = tsec2_clk;
+	gd->arch.usbdr_clk = usbdr_clk;
+#elif defined(CONFIG_ARCH_MPC8309)
+	gd->arch.usbdr_clk = usbdr_clk;
+#endif
+#if defined(CONFIG_ARCH_MPC834X)
+	gd->arch.usbmph_clk = usbmph_clk;
+#endif
+#if defined(CONFIG_ARCH_MPC8315)
+	gd->arch.tdm_clk = tdm_clk;
+#endif
+#if defined(CONFIG_FSL_ESDHC)
+	gd->arch.sdhc_clk = sdhc_clk;
+#endif
+	gd->arch.core_clk = core_clk;
+	gd->arch.i2c1_clk = i2c1_clk;
+#if !defined(CONFIG_ARCH_MPC832X)
+	gd->arch.i2c2_clk = i2c2_clk;
+#endif
+#if !defined(CONFIG_ARCH_MPC8309)
+	gd->arch.enc_clk = enc_clk;
+#endif
+	gd->arch.lbiu_clk = lbiu_clk;
+	gd->arch.lclk_clk = lclk_clk;
+	gd->mem_clk = mem_clk;
+#if defined(CONFIG_ARCH_MPC8360)
+	gd->arch.mem_sec_clk = mem_sec_clk;
+#endif
+#if defined(CONFIG_QE)
+	gd->arch.qe_clk = qe_clk;
+	gd->arch.brg_clk = brg_clk;
+#endif
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+	defined(CONFIG_ARCH_MPC837X)
+	gd->arch.pciexp1_clk = pciexp1_clk;
+	gd->arch.pciexp2_clk = pciexp2_clk;
+#endif
+#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
+	gd->arch.sata_clk = sata_clk;
+#endif
+	gd->pci_clk = pci_sync_in;
+	gd->cpu_clk = gd->arch.core_clk;
+	gd->bus_clk = gd->arch.csb_clk;
+	return 0;
+
+}
+
+/********************************************
+ * get_bus_freq
+ * return system bus freq in Hz
+ *********************************************/
+ulong get_bus_freq(ulong dummy)
+{
+	return gd->arch.csb_clk;
+}
+
+/********************************************
+ * get_ddr_freq
+ * return ddr bus freq in Hz
+ *********************************************/
+ulong get_ddr_freq(ulong dummy)
+{
+	return gd->mem_clk;
+}
+
+int get_serial_clock(void)
+{
+	return get_bus_freq(0);
+}
+
+static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc,
+		     char *const argv[])
+{
+	char buf[32];
+
+	printf("Clock configuration:\n");
+	printf("  Core:                %-4s MHz\n",
+	       strmhz(buf, gd->arch.core_clk));
+	printf("  Coherent System Bus: %-4s MHz\n",
+	       strmhz(buf, gd->arch.csb_clk));
+#if defined(CONFIG_QE)
+	printf("  QE:                  %-4s MHz\n",
+	       strmhz(buf, gd->arch.qe_clk));
+	printf("  BRG:                 %-4s MHz\n",
+	       strmhz(buf, gd->arch.brg_clk));
+#endif
+	printf("  Local Bus Controller:%-4s MHz\n",
+	       strmhz(buf, gd->arch.lbiu_clk));
+	printf("  Local Bus:           %-4s MHz\n",
+	       strmhz(buf, gd->arch.lclk_clk));
+	printf("  DDR:                 %-4s MHz\n", strmhz(buf, gd->mem_clk));
+#if defined(CONFIG_ARCH_MPC8360)
+	printf("  DDR Secondary:       %-4s MHz\n",
+	       strmhz(buf, gd->arch.mem_sec_clk));
+#endif
+#if !defined(CONFIG_ARCH_MPC8309)
+	printf("  SEC:                 %-4s MHz\n",
+	       strmhz(buf, gd->arch.enc_clk));
+#endif
+	printf("  I2C1:                %-4s MHz\n",
+	       strmhz(buf, gd->arch.i2c1_clk));
+#if !defined(CONFIG_ARCH_MPC832X)
+	printf("  I2C2:                %-4s MHz\n",
+	       strmhz(buf, gd->arch.i2c2_clk));
+#endif
+#if defined(CONFIG_ARCH_MPC8315)
+	printf("  TDM:                 %-4s MHz\n",
+	       strmhz(buf, gd->arch.tdm_clk));
+#endif
+#if defined(CONFIG_FSL_ESDHC)
+	printf("  SDHC:                %-4s MHz\n",
+	       strmhz(buf, gd->arch.sdhc_clk));
+#endif
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+	defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
+	printf("  TSEC1:               %-4s MHz\n",
+	       strmhz(buf, gd->arch.tsec1_clk));
+	printf("  TSEC2:               %-4s MHz\n",
+	       strmhz(buf, gd->arch.tsec2_clk));
+	printf("  USB DR:              %-4s MHz\n",
+	       strmhz(buf, gd->arch.usbdr_clk));
+#elif defined(CONFIG_ARCH_MPC8309)
+	printf("  USB DR:              %-4s MHz\n",
+	       strmhz(buf, gd->arch.usbdr_clk));
+#endif
+#if defined(CONFIG_ARCH_MPC834X)
+	printf("  USB MPH:             %-4s MHz\n",
+	       strmhz(buf, gd->arch.usbmph_clk));
+#endif
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+	defined(CONFIG_ARCH_MPC837X)
+	printf("  PCIEXP1:             %-4s MHz\n",
+	       strmhz(buf, gd->arch.pciexp1_clk));
+	printf("  PCIEXP2:             %-4s MHz\n",
+	       strmhz(buf, gd->arch.pciexp2_clk));
+#endif
+#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
+	printf("  SATA:                %-4s MHz\n",
+	       strmhz(buf, gd->arch.sata_clk));
+#endif
+	return 0;
+}
+
+U_BOOT_CMD(clocks, 1, 0, do_clocks,
+	"print clock configuration",
+	"    clocks"
+);
+
+#endif
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/roms/u-boot/arch/powerpc/cpu/mpc83xx/spl_minimal.c
new file mode 100644
index 000000000..00cb2bd04
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/spl_minimal.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <asm-offsets.h>
+#include <clock_legacy.h>
+#include <mpc83xx.h>
+#include <time.h>
+#include <asm/global_data.h>
+
+#include "lblaw/lblaw.h"
+#include "elbc/elbc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Breathe some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f (volatile immap_t * im)
+{
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+
+	/* global data region was cleared in start.S */
+
+	/* system performance tweaking */
+
+#ifndef CONFIG_ACR_PIPE_DEP_UNSET
+	/* Arbiter pipeline depth */
+	im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
+			  CONFIG_ACR_PIPE_DEP;
+#endif
+
+#ifndef CONFIG_ACR_RPTCNT_UNSET
+	/* Arbiter repeat count */
+	im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
+			  CONFIG_ACR_RPTCNT;
+#endif
+
+#ifdef CONFIG_SYS_SPCR_OPT
+	/* Optimize transactions between CSB and other devices */
+	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
+			   (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
+#endif
+
+	/* Enable Time Base & Decrementer (so we will have udelay()) */
+	im->sysconf.spcr |= SPCR_TBEN;
+
+	/* DDR control driver register */
+#ifdef CONFIG_SYS_DDRCDR
+	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
+#endif
+	/* Output buffer impedance register */
+#ifdef CONFIG_SYS_OBIR
+	im->sysconf.obir = CONFIG_SYS_OBIR;
+#endif
+
+	/*
+	 * Memory Controller:
+	 */
+
+	/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
+	 * addresses - these have to be modified later when FLASH size
+	 * has been determined
+	 */
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM)  \
+	&& defined(CONFIG_SYS_NAND_OR_PRELIM) \
+	&& defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
+	&& defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
+	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+	im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
+	im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
+#else
+#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
+#endif
+}
+
+/*
+ * Get timebase clock frequency (like cpu_clk in Hz)
+ */
+unsigned long get_tbclk(void)
+{
+	return (gd->bus_clk + 3L) / 4L;
+}
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}
+
+ulong get_bus_freq(ulong dummy)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u8 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
+
+	return CONFIG_SYS_CLK_FREQ * spmf;
+}
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/start.S b/roms/u-boot/arch/powerpc/cpu/mpc83xx/start.S
new file mode 100644
index 000000000..9da22ce48
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/start.S
@@ -0,0 +1,1196 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
+ * Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
+ * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
+ * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008.
+ */
+
+/*
+ *  U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <mpc83xx.h>
+#include <version.h>
+
+#define CONFIG_83XX	1		/* needed for Linux kernel header files*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <asm/u-boot.h>
+
+#include "hrcw/hrcw.h"
+#include "bats/bats.h"
+#include "hid/hid.h"
+
+/* We don't want the  MMU yet.
+ */
+#undef	MSR_KERNEL
+
+/*
+ * Floating Point enable, Machine Check and Recoverable Interr.
+ */
+#ifdef DEBUG
+#define MSR_KERNEL (MSR_FP|MSR_RI)
+#else
+#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
+#endif
+
+#if defined(CONFIG_NAND_SPL) || \
+	(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
+#define MINIMAL_SPL
+#endif
+
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \
+	!defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_SYS_FLASHBOOT
+#endif
+
+/*
+ * Set up GOT: Global Offset Table
+ *
+ * Use r12 to access the GOT
+ */
+	START_GOT
+	GOT_ENTRY(_GOT2_TABLE_)
+	GOT_ENTRY(__bss_start)
+	GOT_ENTRY(__bss_end)
+
+#ifndef MINIMAL_SPL
+	GOT_ENTRY(_FIXUP_TABLE_)
+	GOT_ENTRY(_start)
+	GOT_ENTRY(_start_of_vectors)
+	GOT_ENTRY(_end_of_vectors)
+	GOT_ENTRY(transfer_to_handler)
+#endif
+	END_GOT
+
+/*
+ * The Hard Reset Configuration Word (HRCW) table is in the first 64
+ * (0x40) bytes of flash.  It has 8 bytes, but each byte is repeated 8
+ * times so the processor can fetch it out of flash whether the flash
+ * is 8, 16, 32, or 64 bits wide (hardware trickery).
+ */
+	.text
+#define _HRCW_TABLE_ENTRY(w)		\
+	.fill	8,1,(((w)>>24)&0xff);	\
+	.fill	8,1,(((w)>>16)&0xff);	\
+	.fill	8,1,(((w)>> 8)&0xff);	\
+	.fill	8,1,(((w)    )&0xff)
+
+	_HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW)
+	_HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH)
+
+/*
+ * Magic number and version string - put it after the HRCW since it
+ * cannot be first in flash like it is in many other processors.
+ */
+	.long	0x27051956		/* U-Boot Magic Number */
+
+	.globl	version_string
+version_string:
+	.ascii U_BOOT_VERSION_STRING, "\0"
+
+	.align 2
+
+	.globl enable_addr_trans
+enable_addr_trans:
+	/* enable address translation */
+	mfmsr	r5
+	ori	r5, r5, (MSR_IR | MSR_DR)
+	mtmsr	r5
+	isync
+	blr
+
+	.globl disable_addr_trans
+disable_addr_trans:
+	/* disable address translation */
+	mflr	r4
+	mfmsr	r3
+	andi.	r0, r3, (MSR_IR | MSR_DR)
+	beqlr
+	andc	r3, r3, r0
+	mtspr	SRR0, r4
+	mtspr	SRR1, r3
+	rfi
+
+#ifndef CONFIG_DEFAULT_IMMR
+#error CONFIG_DEFAULT_IMMR must be defined
+#endif /* CONFIG_DEFAULT_IMMR */
+#ifndef CONFIG_SYS_IMMR
+#define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR
+#endif /* CONFIG_SYS_IMMR */
+
+/*
+ * After configuration, a system reset exception is executed using the
+ * vector at offset 0x100 relative to the base set by MSR[IP]. If
+ * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the
+ * base address is 0xfff00000. In the case of a Power On Reset or Hard
+ * Reset, the value of MSR[IP] is determined by the CIP field in the
+ * HRCW.
+ *
+ * Other bits in the HRCW set up the Base Address and Port Size in BR0.
+ * This determines the location of the boot ROM (flash or EPROM) in the
+ * processor's address space at boot time. As long as the HRCW is set up
+ * so that we eventually end up executing the code below when the
+ * processor executes the reset exception, the actual values used should
+ * not matter.
+ *
+ * Once we have got here, the address mask in OR0 is cleared so that the
+ * bottom 32K of the boot ROM is effectively repeated all throughout the
+ * processor's address space, after which we can jump to the absolute
+ * address at which the boot ROM was linked at compile time, and proceed
+ * to initialise the memory controller without worrying if the rug will
+ * be pulled out from under us, so to speak (it will be fine as long as
+ * we configure BR0 with the same boot ROM link address).
+ */
+	. = EXC_OFF_SYS_RESET
+
+	.globl	_start
+_start: /* time t 0 */
+	lis	r4, CONFIG_DEFAULT_IMMR@h
+	nop
+
+	mfmsr	r5			/* save msr contents	*/
+
+	/* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */
+	bl	1f
+1:	mflr	r7
+
+	lis	r3, CONFIG_SYS_IMMR@h
+	ori	r3, r3, CONFIG_SYS_IMMR@l
+
+	lwz	r6, IMMRBAR(r4)
+	isync
+
+	stw	r3, IMMRBAR(r4)
+	lwz	r6, 0(r7)		/* Arbitrary external load */
+	isync
+
+	lwz	r6, IMMRBAR(r3)
+	isync
+
+	/* Initialise the E300 processor core		*/
+	/*------------------------------------------*/
+
+#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \
+		defined(CONFIG_NAND_SPL)
+	/* The FCM begins execution after only the first page
+	 * is loaded.  Wait for the rest before branching
+	 * to another flash page.
+	 */
+1:	lwz	r6, 0x50b0(r3)
+	andi.	r6, r6, 1
+	beq	1b
+#endif
+
+	bl	init_e300_core
+
+#ifdef CONFIG_SYS_FLASHBOOT
+
+	/* Inflate flash location so it appears everywhere, calculate */
+	/* the absolute address in final location of the FLASH, jump  */
+	/* there and deflate the flash size back to minimal size      */
+	/*------------------------------------------------------------*/
+	bl map_flash_by_law1
+	lis r4, (CONFIG_SYS_MONITOR_BASE)@h
+	ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
+	addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
+	mtlr r5
+	blr
+in_flash:
+#if 1 /* Remapping flash with LAW0. */
+	bl remap_flash_by_law0
+#endif
+#endif	/* CONFIG_SYS_FLASHBOOT */
+
+	/* setup the bats */
+	bl	setup_bats
+	sync
+
+	/*
+	 * Cache must be enabled here for stack-in-cache trick.
+	 * This means we need to enable the BATS.
+	 * This means:
+	 *   1) for the EVB, original gt regs need to be mapped
+	 *   2) need to have an IBAT for the 0xf region,
+	 *      we are running there!
+	 * Cache should be turned on after BATs, since by default
+	 * everything is write-through.
+	 * The init-mem BAT can be reused after reloc. The old
+	 * gt-regs BAT can be reused after board_init_f calls
+	 * board_early_init_f (EVB only).
+	 */
+	/* enable address translation */
+	bl	enable_addr_trans
+	sync
+
+	/* enable the data cache */
+	bl	dcache_enable
+	sync
+#ifdef CONFIG_SYS_INIT_RAM_LOCK
+	bl	lock_ram_in_cache
+	sync
+#endif
+
+	/* set up the stack pointer in our newly created
+	 * cache-ram; use r3 to keep the new SP for now to
+	 * avoid overiding the SP it uselessly */
+	lis	r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
+	ori	r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
+
+	/* r4 = end of GD area */
+	addi r4, r3, GENERATED_GBL_DATA_SIZE
+
+	/* Zero GD area */
+	li	r0, 0
+1:
+	subi	r4, r4, 1
+	stb	r0, 0(r4)
+	cmplw	r3, r4
+	bne	1b
+
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+
+#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
+#error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
+#endif
+
+	/* r3 = new stack pointer / pre-reloc malloc area */
+	subi    r3, r3, CONFIG_VAL(SYS_MALLOC_F_LEN)
+
+	/* Set pointer to pre-reloc malloc area in GD */
+	stw     r3, GD_MALLOC_BASE(r4)
+#endif
+	li	r0, 0		/* Make room for stack frame header and	*/
+	stwu	r0, -4(r3)	/* clear final stack frame so that	*/
+	stwu	r0, -4(r3)	/* stack backtraces terminate cleanly	*/
+
+	/* Finally, actually set SP */
+	mr	r1, r3
+
+	/* let the C-code set up the rest	                    */
+	/*				                            */
+	/* Be careful to keep code relocatable & stack humble   */
+	/*------------------------------------------------------*/
+
+	GET_GOT			/* initialize GOT access	*/
+	/* Needed for -msingle-pic-base */
+	bl	_GLOBAL_OFFSET_TABLE_@local-4
+	mflr	r30
+
+	/* r3: IMMR */
+	lis	r3, CONFIG_SYS_IMMR@h
+	/* run low-level CPU init code (in Flash)*/
+	bl	cpu_init_f
+
+	/* run 1st part of board init code (in Flash)*/
+	li	r3, 0		/* clear boot_flag for calling board_init_f */
+	bl	board_init_f
+
+	/* NOTREACHED - board_init_f() does not return */
+
+#ifndef MINIMAL_SPL
+/*
+ * Vector Table
+ */
+
+	.globl	_start_of_vectors
+_start_of_vectors:
+
+/* Machine check */
+	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
+
+/* Data Storage exception. */
+	STD_EXCEPTION(0x300, DataStorage, UnknownException)
+
+/* Instruction Storage exception. */
+	STD_EXCEPTION(0x400, InstStorage, UnknownException)
+
+/* External Interrupt exception. */
+#ifndef FIXME
+	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
+#endif
+
+/* Alignment exception. */
+	. = 0x600
+Alignment:
+	EXCEPTION_PROLOG(SRR0, SRR1)
+	mfspr	r4,DAR
+	stw	r4,_DAR(r21)
+	mfspr	r5,DSISR
+	stw	r5,_DSISR(r21)
+	addi	r3,r1,STACK_FRAME_OVERHEAD
+	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
+
+/* Program check exception */
+	. = 0x700
+ProgramCheck:
+	EXCEPTION_PROLOG(SRR0, SRR1)
+	addi	r3,r1,STACK_FRAME_OVERHEAD
+	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
+		MSR_KERNEL, COPY_EE)
+
+	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
+
+	/* I guess we could implement decrementer, and may have
+	 * to someday for timekeeping.
+	 */
+	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
+
+	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
+	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
+	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
+	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
+
+	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
+	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
+
+	STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
+	STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
+	STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
+#ifdef DEBUG
+	. = 0x1300
+	/*
+	 * This exception occurs when the program counter matches the
+	 * Instruction Address Breakpoint Register (IABR).
+	 *
+	 * I want the cpu to halt if this occurs so I can hunt around
+	 * with the debugger and look at things.
+	 *
+	 * When DEBUG is defined, both machine check enable (in the MSR)
+	 * and checkstop reset enable (in the reset mode register) are
+	 * turned off and so a checkstop condition will result in the cpu
+	 * halting.
+	 *
+	 * I force the cpu into a checkstop condition by putting an illegal
+	 * instruction here (at least this is the theory).
+	 *
+	 * well - that didnt work, so just do an infinite loop!
+	 */
+1:	b	1b
+#else
+	STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
+#endif
+	STD_EXCEPTION(0x1400, SMI, UnknownException)
+
+	STD_EXCEPTION(0x1500, Trap_15, UnknownException)
+	STD_EXCEPTION(0x1600, Trap_16, UnknownException)
+	STD_EXCEPTION(0x1700, Trap_17, UnknownException)
+	STD_EXCEPTION(0x1800, Trap_18, UnknownException)
+	STD_EXCEPTION(0x1900, Trap_19, UnknownException)
+	STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
+	STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
+	STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
+	STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
+	STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
+	STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
+	STD_EXCEPTION(0x2000, Trap_20, UnknownException)
+	STD_EXCEPTION(0x2100, Trap_21, UnknownException)
+	STD_EXCEPTION(0x2200, Trap_22, UnknownException)
+	STD_EXCEPTION(0x2300, Trap_23, UnknownException)
+	STD_EXCEPTION(0x2400, Trap_24, UnknownException)
+	STD_EXCEPTION(0x2500, Trap_25, UnknownException)
+	STD_EXCEPTION(0x2600, Trap_26, UnknownException)
+	STD_EXCEPTION(0x2700, Trap_27, UnknownException)
+	STD_EXCEPTION(0x2800, Trap_28, UnknownException)
+	STD_EXCEPTION(0x2900, Trap_29, UnknownException)
+	STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
+	STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
+	STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
+	STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
+	STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
+	STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
+
+
+	.globl	_end_of_vectors
+_end_of_vectors:
+
+	. = 0x3000
+
+/*
+ * This code finishes saving the registers to the exception frame
+ * and jumps to the appropriate handler for the exception.
+ * Register r21 is pointer into trap frame, r1 has new stack pointer.
+ */
+	.globl	transfer_to_handler
+transfer_to_handler:
+	stw	r22,_NIP(r21)
+	lis	r22,MSR_POW@h
+	andc	r23,r23,r22
+	stw	r23,_MSR(r21)
+	SAVE_GPR(7, r21)
+	SAVE_4GPRS(8, r21)
+	SAVE_8GPRS(12, r21)
+	SAVE_8GPRS(24, r21)
+	mflr	r23
+	andi.	r24,r23,0x3f00		/* get vector offset */
+	stw	r24,TRAP(r21)
+	li	r22,0
+	stw	r22,RESULT(r21)
+	lwz	r24,0(r23)		/* virtual address of handler */
+	lwz	r23,4(r23)		/* where to go when done */
+	mtspr	SRR0,r24
+	mtspr	SRR1,r20
+	mtlr	r23
+	SYNC
+	rfi				/* jump to handler, enable MMU */
+
+int_return:
+	mfmsr	r28		/* Disable interrupts */
+	li	r4,0
+	ori	r4,r4,MSR_EE
+	andc	r28,r28,r4
+	SYNC			/* Some chip revs need this... */
+	mtmsr	r28
+	SYNC
+	lwz	r2,_CTR(r1)
+	lwz	r0,_LINK(r1)
+	mtctr	r2
+	mtlr	r0
+	lwz	r2,_XER(r1)
+	lwz	r0,_CCR(r1)
+	mtspr	XER,r2
+	mtcrf	0xFF,r0
+	REST_10GPRS(3, r1)
+	REST_10GPRS(13, r1)
+	REST_8GPRS(23, r1)
+	REST_GPR(31, r1)
+	lwz	r2,_NIP(r1)	/* Restore environment */
+	lwz	r0,_MSR(r1)
+	mtspr	SRR0,r2
+	mtspr	SRR1,r0
+	lwz	r0,GPR0(r1)
+	lwz	r2,GPR2(r1)
+	lwz	r1,GPR1(r1)
+	SYNC
+	rfi
+#endif /* !MINIMAL_SPL */
+
+/*
+ * This code initialises the E300 processor core
+ * (conforms to PowerPC 603e spec)
+ * Note: expects original MSR contents to be in r5.
+ */
+	.globl	init_e300_core
+init_e300_core: /* time t 10 */
+	/* Initialize machine status; enable machine check interrupt */
+	/*-----------------------------------------------------------*/
+
+	li	r3, MSR_KERNEL			/* Set ME and RI flags */
+	rlwimi	r3, r5, 0, 25, 25	/* preserve IP bit set by HRCW */
+#ifdef DEBUG
+	rlwimi	r3, r5, 0, 21, 22   /* debugger might set SE & BE bits */
+#endif
+	SYNC						/* Some chip revs need this... */
+	mtmsr	r3
+	SYNC
+	mtspr	SRR1, r3			/* Make SRR1 match MSR */
+
+
+	lis	r3, CONFIG_SYS_IMMR@h
+#if defined(CONFIG_WATCHDOG)
+	/* Initialise the Watchdog values and reset it (if req) */
+	/*------------------------------------------------------*/
+	lis r4, CONFIG_SYS_WATCHDOG_VALUE
+	ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
+	stw r4, SWCRR(r3)
+
+	/* and reset it */
+
+	li	r4, 0x556C
+	sth	r4, SWSRR@l(r3)
+	li	r4, -0x55C7
+	sth	r4, SWSRR@l(r3)
+#else
+	/* Disable Watchdog  */
+	/*-------------------*/
+	lwz r4, SWCRR(r3)
+	/* Check to see if its enabled for disabling
+	   once disabled by SW you can't re-enable */
+	andi. r4, r4, 0x4
+	beq 1f
+	xor r4, r4, r4
+	stw r4, SWCRR(r3)
+1:
+#endif /* CONFIG_WATCHDOG */
+
+#if defined(CONFIG_MASK_AER_AO)
+	/* Write the Arbiter Event Enable to mask Address Only traps. */
+	/* This prevents the dcbz instruction from being trapped when */
+	/* HID0_ABE Address Broadcast Enable is set and the MEMORY    */
+	/* COHERENCY bit is set in the WIMG bits, which is often      */
+	/* needed for PCI operation.                                  */
+	lwz	r4, 0x0808(r3)
+	rlwinm	r0, r4, 0, ~AER_AO
+	stw	r0, 0x0808(r3)
+#endif /* CONFIG_MASK_AER_AO */
+
+	/* Initialize the Hardware Implementation-dependent Registers */
+	/* HID0 also contains cache control			*/
+	/* - force invalidation of data and instruction caches  */
+	/*------------------------------------------------------*/
+
+	lis	r3, CONFIG_SYS_HID0_INIT@h
+	ori	r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l
+	SYNC
+	mtspr	HID0, r3
+
+	lis	r3, CONFIG_SYS_HID0_FINAL@h
+	ori	r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l
+	SYNC
+	mtspr	HID0, r3
+
+	lis	r3, CONFIG_SYS_HID2@h
+	ori	r3, r3, CONFIG_SYS_HID2@l
+	SYNC
+	mtspr	HID2, r3
+
+	/* Done!						*/
+	/*------------------------------*/
+	blr
+
+	/* setup_bats - set them up to some initial state */
+	.globl	setup_bats
+setup_bats:
+	addis	r0, r0, 0x0000
+
+	/* IBAT 0 */
+	addis	r4, r0, CONFIG_SYS_IBAT0L@h
+	ori	r4, r4, CONFIG_SYS_IBAT0L@l
+	addis	r3, r0, CONFIG_SYS_IBAT0U@h
+	ori	r3, r3, CONFIG_SYS_IBAT0U@l
+	mtspr	IBAT0L, r4
+	mtspr	IBAT0U, r3
+
+	/* DBAT 0 */
+	addis	r4, r0, CONFIG_SYS_DBAT0L@h
+	ori	r4, r4, CONFIG_SYS_DBAT0L@l
+	addis	r3, r0, CONFIG_SYS_DBAT0U@h
+	ori	r3, r3, CONFIG_SYS_DBAT0U@l
+	mtspr	DBAT0L, r4
+	mtspr	DBAT0U, r3
+
+	/* IBAT 1 */
+	addis	r4, r0, CONFIG_SYS_IBAT1L@h
+	ori	r4, r4, CONFIG_SYS_IBAT1L@l
+	addis	r3, r0, CONFIG_SYS_IBAT1U@h
+	ori	r3, r3, CONFIG_SYS_IBAT1U@l
+	mtspr	IBAT1L, r4
+	mtspr	IBAT1U, r3
+
+	/* DBAT 1 */
+	addis	r4, r0, CONFIG_SYS_DBAT1L@h
+	ori	r4, r4, CONFIG_SYS_DBAT1L@l
+	addis	r3, r0, CONFIG_SYS_DBAT1U@h
+	ori	r3, r3, CONFIG_SYS_DBAT1U@l
+	mtspr	DBAT1L, r4
+	mtspr	DBAT1U, r3
+
+	/* IBAT 2 */
+	addis	r4, r0, CONFIG_SYS_IBAT2L@h
+	ori	r4, r4, CONFIG_SYS_IBAT2L@l
+	addis	r3, r0, CONFIG_SYS_IBAT2U@h
+	ori	r3, r3, CONFIG_SYS_IBAT2U@l
+	mtspr	IBAT2L, r4
+	mtspr	IBAT2U, r3
+
+	/* DBAT 2 */
+	addis	r4, r0, CONFIG_SYS_DBAT2L@h
+	ori	r4, r4, CONFIG_SYS_DBAT2L@l
+	addis	r3, r0, CONFIG_SYS_DBAT2U@h
+	ori	r3, r3, CONFIG_SYS_DBAT2U@l
+	mtspr	DBAT2L, r4
+	mtspr	DBAT2U, r3
+
+	/* IBAT 3 */
+	addis	r4, r0, CONFIG_SYS_IBAT3L@h
+	ori	r4, r4, CONFIG_SYS_IBAT3L@l
+	addis	r3, r0, CONFIG_SYS_IBAT3U@h
+	ori	r3, r3, CONFIG_SYS_IBAT3U@l
+	mtspr	IBAT3L, r4
+	mtspr	IBAT3U, r3
+
+	/* DBAT 3 */
+	addis	r4, r0, CONFIG_SYS_DBAT3L@h
+	ori	r4, r4, CONFIG_SYS_DBAT3L@l
+	addis	r3, r0, CONFIG_SYS_DBAT3U@h
+	ori	r3, r3, CONFIG_SYS_DBAT3U@l
+	mtspr	DBAT3L, r4
+	mtspr	DBAT3U, r3
+
+#ifdef CONFIG_HIGH_BATS
+	/* IBAT 4 */
+	addis   r4, r0, CONFIG_SYS_IBAT4L@h
+	ori     r4, r4, CONFIG_SYS_IBAT4L@l
+	addis   r3, r0, CONFIG_SYS_IBAT4U@h
+	ori     r3, r3, CONFIG_SYS_IBAT4U@l
+	mtspr   IBAT4L, r4
+	mtspr   IBAT4U, r3
+
+	/* DBAT 4 */
+	addis   r4, r0, CONFIG_SYS_DBAT4L@h
+	ori     r4, r4, CONFIG_SYS_DBAT4L@l
+	addis   r3, r0, CONFIG_SYS_DBAT4U@h
+	ori     r3, r3, CONFIG_SYS_DBAT4U@l
+	mtspr   DBAT4L, r4
+	mtspr   DBAT4U, r3
+
+	/* IBAT 5 */
+	addis   r4, r0, CONFIG_SYS_IBAT5L@h
+	ori     r4, r4, CONFIG_SYS_IBAT5L@l
+	addis   r3, r0, CONFIG_SYS_IBAT5U@h
+	ori     r3, r3, CONFIG_SYS_IBAT5U@l
+	mtspr   IBAT5L, r4
+	mtspr   IBAT5U, r3
+
+	/* DBAT 5 */
+	addis   r4, r0, CONFIG_SYS_DBAT5L@h
+	ori     r4, r4, CONFIG_SYS_DBAT5L@l
+	addis   r3, r0, CONFIG_SYS_DBAT5U@h
+	ori     r3, r3, CONFIG_SYS_DBAT5U@l
+	mtspr   DBAT5L, r4
+	mtspr   DBAT5U, r3
+
+	/* IBAT 6 */
+	addis   r4, r0, CONFIG_SYS_IBAT6L@h
+	ori     r4, r4, CONFIG_SYS_IBAT6L@l
+	addis   r3, r0, CONFIG_SYS_IBAT6U@h
+	ori     r3, r3, CONFIG_SYS_IBAT6U@l
+	mtspr   IBAT6L, r4
+	mtspr   IBAT6U, r3
+
+	/* DBAT 6 */
+	addis   r4, r0, CONFIG_SYS_DBAT6L@h
+	ori     r4, r4, CONFIG_SYS_DBAT6L@l
+	addis   r3, r0, CONFIG_SYS_DBAT6U@h
+	ori     r3, r3, CONFIG_SYS_DBAT6U@l
+	mtspr   DBAT6L, r4
+	mtspr   DBAT6U, r3
+
+	/* IBAT 7 */
+	addis   r4, r0, CONFIG_SYS_IBAT7L@h
+	ori     r4, r4, CONFIG_SYS_IBAT7L@l
+	addis   r3, r0, CONFIG_SYS_IBAT7U@h
+	ori     r3, r3, CONFIG_SYS_IBAT7U@l
+	mtspr   IBAT7L, r4
+	mtspr   IBAT7U, r3
+
+	/* DBAT 7 */
+	addis   r4, r0, CONFIG_SYS_DBAT7L@h
+	ori     r4, r4, CONFIG_SYS_DBAT7L@l
+	addis   r3, r0, CONFIG_SYS_DBAT7U@h
+	ori     r3, r3, CONFIG_SYS_DBAT7U@l
+	mtspr   DBAT7L, r4
+	mtspr   DBAT7U, r3
+#endif
+
+	isync
+
+	/* invalidate all tlb's
+	 *
+	 * From the 603e User Manual: "The 603e provides the ability to
+	 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie)
+	 * instruction invalidates the TLB entry indexed by the EA, and
+	 * operates on both the instruction and data TLBs simultaneously
+	 * invalidating four TLB entries (both sets in each TLB). The
+	 * index corresponds to bits 15-19 of the EA. To invalidate all
+	 * entries within both TLBs, 32 tlbie instructions should be
+	 * issued, incrementing this field by one each time."
+	 *
+	 * "Note that the tlbia instruction is not implemented on the
+	 * 603e."
+	 *
+	 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000
+	 * incrementing by 0x1000 each time. The code below is sort of
+	 * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S
+	 *
+	 */
+	lis	r3, 0
+	lis	r5, 2
+
+1:
+	tlbie	r3
+	addi	r3, r3, 0x1000
+	cmp	0, 0, r3, r5
+	blt	1b
+
+	blr
+
+/* Cache functions.
+ *
+ * Note: requires that all cache bits in
+ * HID0 are in the low half word.
+ */
+#ifndef MINIMAL_SPL
+	.globl	icache_enable
+icache_enable:
+	mfspr	r3, HID0
+	ori	r3, r3, HID0_ICE
+	li	r4, HID0_ICFI|HID0_ILOCK
+	andc	r3, r3, r4
+	ori	r4, r3, HID0_ICFI
+	isync
+	mtspr	HID0, r4    /* sets enable and invalidate, clears lock */
+	isync
+	mtspr	HID0, r3	/* clears invalidate */
+	blr
+
+	.globl	icache_disable
+icache_disable:
+	mfspr	r3, HID0
+	lis	r4, 0
+	ori	r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK
+	andc	r3, r3, r4
+	isync
+	mtspr	HID0, r3	/* clears invalidate, enable and lock */
+	blr
+
+	.globl	icache_status
+icache_status:
+	mfspr	r3, HID0
+	rlwinm	r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
+	blr
+#endif	/* !MINIMAL_SPL */
+
+	.globl	dcache_enable
+dcache_enable:
+	mfspr	r3, HID0
+	li	r5, HID0_DCFI|HID0_DLOCK
+	andc	r3, r3, r5
+	ori	r3, r3, HID0_DCE
+	sync
+	mtspr	HID0, r3		/* enable, no invalidate */
+	blr
+
+	.globl	dcache_disable
+dcache_disable:
+	mflr	r4
+	bl	flush_dcache		/* uses r3 and r5 */
+	mfspr	r3, HID0
+	li	r5, HID0_DCE|HID0_DLOCK
+	andc	r3, r3, r5
+	ori	r5, r3, HID0_DCFI
+	sync
+	mtspr	HID0, r5	/* sets invalidate, clears enable and lock */
+	sync
+	mtspr	HID0, r3	/* clears invalidate */
+	mtlr	r4
+	blr
+
+	.globl	dcache_status
+dcache_status:
+	mfspr	r3, HID0
+	rlwinm	r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
+	blr
+
+	.globl	flush_dcache
+flush_dcache:
+	lis	r3, 0
+	lis	r5, CONFIG_SYS_CACHELINE_SIZE
+1:	cmp	0, 1, r3, r5
+	bge	2f
+	lwz	r5, 0(r3)
+	lis	r5, CONFIG_SYS_CACHELINE_SIZE
+	addi	r3, r3, 0x4
+	b	1b
+2:	blr
+
+/*-------------------------------------------------------------------*/
+
+/*
+ * void relocate_code(addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+	.globl	relocate_code
+relocate_code:
+	mr	r1,  r3		/* Set new stack pointer	*/
+	mr	r9,  r4		/* Save copy of Global Data pointer */
+	mr	r10, r5		/* Save copy of Destination Address */
+
+	GET_GOT
+	mr	r3,  r5				/* Destination Address */
+	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address */
+	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
+	lwz	r5, GOT(__bss_start)
+	sub	r5, r5, r4
+	li	r6, CONFIG_SYS_CACHELINE_SIZE		/* Cache Line Size */
+
+	/*
+	 * Fix GOT pointer:
+	 *
+	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
+	 *		+ Destination Address
+	 *
+	 * Offset:
+	 */
+	sub	r15, r10, r4
+
+	/* First our own GOT */
+	add	r12, r12, r15
+	/* then the one used by the C code */
+	add	r30, r30, r15
+
+	/*
+	 * Now relocate code
+	 */
+
+	cmplw	cr1,r3,r4
+	addi	r0,r5,3
+	srwi.	r0,r0,2
+	beq	cr1,4f		/* In place copy is not necessary */
+	beq	7f		/* Protect against 0 count	  */
+	mtctr	r0
+	bge	cr1,2f
+	la	r8,-4(r4)
+	la	r7,-4(r3)
+
+	/* copy */
+1:	lwzu	r0,4(r8)
+	stwu	r0,4(r7)
+	bdnz	1b
+
+	addi	r0,r5,3
+	srwi.	r0,r0,2
+	mtctr	r0
+	la	r8,-4(r4)
+	la	r7,-4(r3)
+
+	/* and compare */
+20:	lwzu	r20,4(r8)
+	lwzu	r21,4(r7)
+	xor. r22, r20, r21
+	bne  30f
+	bdnz	20b
+	b 4f
+
+	/* compare failed */
+30:	li r3, 0
+	blr
+
+2:	slwi	r0,r0,2 /* re copy in reverse order ... y do we needed it? */
+	add	r8,r4,r0
+	add	r7,r3,r0
+3:	lwzu	r0,-4(r8)
+	stwu	r0,-4(r7)
+	bdnz	3b
+
+/*
+ * Now flush the cache: note that we must start from a cache aligned
+ * address. Otherwise we might miss one cache line.
+ */
+4:	cmpwi	r6,0
+	add	r5,r3,r5
+	beq	7f		/* Always flush prefetch queue in any case */
+	subi	r0,r6,1
+	andc	r3,r3,r0
+	mr	r4,r3
+5:	dcbst	0,r4
+	add	r4,r4,r6
+	cmplw	r4,r5
+	blt	5b
+	sync			/* Wait for all dcbst to complete on bus */
+	mr	r4,r3
+6:	icbi	0,r4
+	add	r4,r4,r6
+	cmplw	r4,r5
+	blt	6b
+7:	sync			/* Wait for all icbi to complete on bus	*/
+	isync
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
+	mtlr	r0
+	blr
+
+in_ram:
+
+	/*
+	 * Relocation Function, r12 point to got2+0x8000
+	 *
+	 * Adjust got2 pointers, no need to check for 0, this code
+	 * already puts a few entries in the table.
+	 */
+	li	r0,__got2_entries@sectoff@l
+	la	r3,GOT(_GOT2_TABLE_)
+	lwz	r11,GOT(_GOT2_TABLE_)
+	mtctr	r0
+	sub	r11,r3,r11
+	addi	r3,r3,-4
+1:	lwzu	r0,4(r3)
+	cmpwi	r0,0
+	beq-	2f
+	add	r0,r0,r11
+	stw	r0,0(r3)
+2:	bdnz	1b
+
+#ifndef MINIMAL_SPL
+	/*
+	 * Now adjust the fixups and the pointers to the fixups
+	 * in case we need to move ourselves again.
+	 */
+	li	r0,__fixup_entries@sectoff@l
+	lwz	r3,GOT(_FIXUP_TABLE_)
+	cmpwi	r0,0
+	mtctr	r0
+	addi	r3,r3,-4
+	beq	4f
+3:	lwzu	r4,4(r3)
+	lwzux	r0,r4,r11
+	cmpwi	r0,0
+	add	r0,r0,r11
+	stw	r4,0(r3)
+	beq-	5f
+	stw	r0,0(r4)
+5:	bdnz	3b
+4:
+#endif
+
+clear_bss:
+	/*
+	 * Now clear BSS segment
+	 */
+	lwz	r3,GOT(__bss_start)
+	lwz	r4,GOT(__bss_end)
+
+	cmplw	0, r3, r4
+	beq	6f
+
+	li	r0, 0
+5:
+	stw	r0, 0(r3)
+	addi	r3, r3, 4
+	cmplw	0, r3, r4
+	bne	5b
+6:
+
+	mr	r3, r9		/* Global Data pointer		*/
+	mr	r4, r10		/* Destination Address		*/
+	bl	board_init_r
+
+#ifndef MINIMAL_SPL
+	/*
+	 * Copy exception vector code to low memory
+	 *
+	 * r3: dest_addr
+	 * r7: source address, r8: end address, r9: target address
+	 */
+	.globl	trap_init
+trap_init:
+	mflr	r4		/* save link register */
+	GET_GOT
+	lwz	r7, GOT(_start)
+	lwz	r8, GOT(_end_of_vectors)
+
+	li	r9, 0x100	/* reset vector always at 0x100 */
+
+	cmplw	0, r7, r8
+	bgelr			/* return if r7>=r8 - just in case */
+1:
+	lwz	r0, 0(r7)
+	stw	r0, 0(r9)
+	addi	r7, r7, 4
+	addi	r9, r9, 4
+	cmplw	0, r7, r8
+	bne	1b
+
+	/*
+	 * relocate `hdlr' and `int_return' entries
+	 */
+	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
+	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
+2:
+	bl	trap_reloc
+	addi	r7, r7, 0x100		/* next exception vector */
+	cmplw	0, r7, r8
+	blt	2b
+
+	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
+	bl	trap_reloc
+
+	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
+	bl	trap_reloc
+
+	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
+	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
+3:
+	bl	trap_reloc
+	addi	r7, r7, 0x100		/* next exception vector */
+	cmplw	0, r7, r8
+	blt	3b
+
+	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
+	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
+4:
+	bl	trap_reloc
+	addi	r7, r7, 0x100		/* next exception vector */
+	cmplw	0, r7, r8
+	blt	4b
+
+	mfmsr	r3			/* now that the vectors have */
+	lis	r7, MSR_IP@h		/* relocated into low memory */
+	ori	r7, r7, MSR_IP@l	/* MSR[IP] can be turned off */
+	andc	r3, r3, r7		/* (if it was on) */
+	SYNC				/* Some chip revs need this... */
+	mtmsr	r3
+	SYNC
+
+	mtlr	r4			/* restore link register    */
+	blr
+
+#endif /* !MINIMAL_SPL */
+
+#ifdef CONFIG_SYS_INIT_RAM_LOCK
+lock_ram_in_cache:
+	/* Allocate Initial RAM in data cache.
+	 */
+	lis	r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
+	ori	r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
+	li	r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
+		     (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
+	mtctr	r4
+1:
+	dcbz	r0, r3
+	addi	r3, r3, 32
+	bdnz	1b
+
+	/* Lock the data cache */
+	mfspr	r0, HID0
+	ori	r0, r0, HID0_DLOCK
+	sync
+	mtspr	HID0, r0
+	sync
+	blr
+
+#ifndef MINIMAL_SPL
+.globl unlock_ram_in_cache
+unlock_ram_in_cache:
+	/* invalidate the INIT_RAM section */
+	lis	r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
+	ori	r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
+	li	r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
+		     (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
+	mtctr	r4
+1:	icbi	r0, r3
+	dcbi	r0, r3
+	addi	r3, r3, 32
+	bdnz	1b
+	sync			/* Wait for all icbi to complete on bus	*/
+	isync
+
+	/* Unlock the data cache and invalidate it */
+	mfspr   r3, HID0
+	li	r5, HID0_DLOCK|HID0_DCFI
+	andc	r3, r3, r5		/* no invalidate, unlock */
+	ori	r5, r3, HID0_DCFI	/* invalidate, unlock */
+	sync
+	mtspr	HID0, r5		/* invalidate, unlock */
+	sync
+	mtspr	HID0, r3		/* no invalidate, unlock */
+	blr
+#endif /* !MINIMAL_SPL */
+#endif /* CONFIG_SYS_INIT_RAM_LOCK */
+
+#ifdef CONFIG_SYS_FLASHBOOT
+map_flash_by_law1:
+	/* When booting from ROM (Flash or EPROM), clear the  */
+	/* Address Mask in OR0 so ROM appears everywhere      */
+	/*----------------------------------------------------*/
+	lis	r3, (CONFIG_SYS_IMMR)@h  /* r3 <= CONFIG_SYS_IMMR    */
+	lwz	r4, OR0@l(r3)
+	li	r5, 0x7fff        /* r5 <= 0x00007FFFF */
+	and	r4, r4, r5
+	stw	r4, OR0@l(r3)     /* OR0 <= OR0 & 0x00007FFFF */
+
+	/* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,
+	 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR]
+	 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot
+	 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is
+	 * 0xFF800.  From the hard resetting to here, the processor fetched and
+	 * executed the instructions one by one.  There is not absolutely
+	 * jumping happened.  Laterly, the u-boot code has to do an absolutely
+	 * jumping to tell the CPU instruction fetching component what the
+	 * u-boot TEXT base address is.  Because the TEXT base resides in the
+	 * boot ROM memory space, to garantee the code can run smoothly after
+	 * that jumping, we must map in the entire boot ROM by Local Access
+	 * Window.  Sometimes, we desire an non-0x00000 or non-0xFF800 starting
+	 * address for boot ROM, such as 0xFE000000.  In this case, the default
+	 * LBIU Local Access Widow 0 will not cover this memory space.  So, we
+	 * need another window to map in it.
+	 */
+	lis r4, (CONFIG_SYS_FLASH_BASE)@h
+	ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
+	stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */
+
+	/* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */
+	lis r4, (0x80000012)@h
+	ori r4, r4, (0x80000012)@l
+	li r5, CONFIG_SYS_FLASH_SIZE
+1:	srawi. r5, r5, 1	/* r5 = r5 >> 1 */
+	addi r4, r4, 1
+	bne 1b
+
+	stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
+	/* Wait for HW to catch up */
+	lwz r4, LBLAWAR1(r3)
+	twi 0,r4,0
+	isync
+	blr
+
+	/* Though all the LBIU Local Access Windows and LBC Banks will be
+	 * initialized in the C code, we'd better configure boot ROM's
+	 * window 0 and bank 0 correctly at here.
+	 */
+remap_flash_by_law0:
+	/* Initialize the BR0 with the boot ROM starting address. */
+	lwz r4, BR0(r3)
+	li  r5, 0x7FFF
+	and r4, r4, r5
+	lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h
+	ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l
+	or  r5, r5, r4
+	stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
+
+	lwz r4, OR0(r3)
+	lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1)
+	or r4, r4, r5
+	stw r4, OR0(r3)
+
+	lis r4, (CONFIG_SYS_FLASH_BASE)@h
+	ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
+	stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */
+
+	/* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */
+	lis r4, (0x80000012)@h
+	ori r4, r4, (0x80000012)@l
+	li r5, CONFIG_SYS_FLASH_SIZE
+1:	srawi. r5, r5, 1 /* r5 = r5 >> 1 */
+	addi r4, r4, 1
+	bne 1b
+	stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */
+
+
+	xor r4, r4, r4
+	stw r4, LBLAWBAR1(r3)
+	stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
+	/* Wait for HW to catch up */
+	lwz r4, LBLAWAR1(r3)
+	twi 0,r4,0
+	isync
+	blr
+#endif /* CONFIG_SYS_FLASHBOOT */
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/sysio/Kconfig b/roms/u-boot/arch/powerpc/cpu/mpc83xx/sysio/Kconfig
new file mode 100644
index 000000000..9e1f15871
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/sysio/Kconfig
@@ -0,0 +1,7 @@
+menu "System I/O configuration"
+
+if ARCH_MPC8308
+source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig.mpc8308"
+endif
+
+endmenu
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/sysio/Kconfig.mpc8308 b/roms/u-boot/arch/powerpc/cpu/mpc83xx/sysio/Kconfig.mpc8308
new file mode 100644
index 000000000..de62171b3
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/sysio/Kconfig.mpc8308
@@ -0,0 +1,323 @@
+choice
+	prompt "SPI group"
+
+config SICR_SPI_SPI
+	bool "SPI"
+
+config SICR_SPI_MSRCID
+	bool "MSRCID"
+
+config SICR_SPI_LSRCID
+	bool "LSRCID"
+
+endchoice
+
+choice
+	prompt "UART group"
+
+config SICR_UART_SPI
+	bool "UART"
+
+config SICR_UART_MSRCID
+	bool "MSRCID"
+
+config SICR_UART_LSRCID
+	bool "LSRCID"
+
+endchoice
+
+choice
+	prompt "IRQ group"
+
+config SICR_IRQ_SPI
+	bool "IRQ"
+
+config SICR_IRQ_MCP_CKSTOP
+	bool "MCP/CKSTOP"
+
+config SICR_IRQ_INTA
+	bool "INTA"
+
+endchoice
+
+choice
+	prompt "I2C2 group"
+
+config SICR_I2C2_I2C
+	bool "IRQ"
+
+config SICR_I2C2_CKSTOP
+	bool "CKSTOP"
+
+endchoice
+
+choice
+	prompt "ETSEC1 A group"
+
+config SICR_ETSEC1_A_TSEC2
+	bool "TSEC1"
+
+config SICR_ETSEC1_A_TSEC_GTX_CLK125
+	bool "TSEC1 GTX_CLK125"
+
+endchoice
+
+choice
+	prompt "eSDHC A group"
+
+config SICR_ESDHC_A_SD
+	bool "SD"
+
+config SICR_ESDHC_A_GTM
+	bool "GTM"
+
+config SICR_ESDHC_A_GPIO
+	bool "GPIO"
+
+endchoice
+
+choice
+	prompt "eSDHC B group"
+
+config SICR_ESDHC_B_SD
+	bool "SD"
+
+config SICR_ESDHC_B_GTM
+	bool "GTM"
+
+config SICR_ESDHC_B_GPIO
+	bool "GPIO"
+
+endchoice
+
+choice
+	prompt "eSDHC C group"
+
+config SICR_ESDHC_C_SD
+	bool "SD"
+
+config SICR_ESDHC_C_GTM
+	bool "GTM"
+
+config SICR_ESDHC_C_GPIO
+	bool "GPIO"
+
+endchoice
+
+choice
+	prompt "GPIO A group"
+
+config SICR_GPIO_A_GPIO
+	bool "GPIO"
+
+config SICR_GPIO_A_TSEC2
+	bool "TSEC2"
+
+endchoice
+
+choice
+	prompt "GPIO B group"
+
+config SICR_GPIO_B_GPIO
+	bool "GPIO"
+
+config SICR_GPIO_B_TSEC2
+	bool "TSEC2"
+
+config SICR_GPIO_B_TSEC_GTX_CLK125
+	bool "TSEC2 GTX_CLK125"
+
+endchoice
+
+choice
+	prompt "IEEE1588 A group"
+
+config SICR_IEEE1588_A_TSEC
+	bool "TSEC"
+
+config SICR_IEEE1588_A_GPIO
+	bool "GPIO"
+
+endchoice
+
+choice
+	prompt "USB group"
+
+config SICR_USB_TSEC
+	bool "USB"
+
+endchoice
+
+choice
+	prompt "GTM group"
+
+config SICR_GTM_TSEC
+	bool "GTM"
+
+config SICR_GTM_GPIO
+	bool "GPIO"
+
+endchoice
+
+choice
+	prompt "IEEE1588 B group"
+
+config SICR_IEEE1588_B_GPIO
+	bool "GPIO"
+
+endchoice
+
+choice
+	prompt "ETSEC2 group"
+
+config SICR_ETSEC2_TSEC2
+	bool "TSEC2"
+
+config SICR_ETSEC2_GPIO
+	bool "GPIO"
+
+endchoice
+
+choice
+	prompt "GPIO selection"
+
+config SICR_GPIOSEL_GPIO
+	bool "GPIO_A, GPIO_B"
+
+config SICR_GPIOSEL_IEEE1588
+	bool "IEEE1588_A, IEEE1588_B, ETSEC2"
+
+endchoice
+
+choice
+	prompt "IEEE1588 timer output buffer impedance"
+
+config SICR_TMROBI_3_3_V
+	bool "40 Ohm, 3.3V"
+
+config SICR_TMROBI_2_5_V
+	bool "40 Ohm, 2.5V"
+
+endchoice
+
+choice
+	prompt "TSEC1 output buffer impedance"
+
+config SICR_TMSOBI1_3_3_V
+	bool "40 Ohm, 3.3V"
+
+config SICR_TMSOBI1_2_5_V
+	bool "40 Ohm, 2.5V"
+
+endchoice
+
+choice
+	prompt "TSEC2 output buffer impedance"
+
+config SICR_TMSOBI2_3_3_V
+	bool "40 Ohm, 3.3V"
+
+config SICR_TMSOBI2_2_5_V
+	bool "40 Ohm, 2.5V"
+
+endchoice
+
+config SICRL_SPI
+	hex
+	default 0x0 if SICR_SPI_SPI
+	default 0x10000000 if SICR_SPI_MSRCID
+	default 0x30000000 if SICR_SPI_LSRCID
+
+config SICRL_UART
+	hex
+	default 0x0 if SICR_UART_SPI
+	default 0x4000000 if SICR_UART_MSRCID
+	default 0xc000000 if SICR_UART_LSRCID
+
+config SICRL_IRQ
+	hex
+	default 0x0 if SICR_IRQ_SPI
+	default 0x1000000 if SICR_IRQ_MCP_CKSTOP
+	default 0x3000000 if SICR_IRQ_INTA
+
+config SICRL_I2C2
+	hex
+	default 0x0 if SICR_I2C2_I2C
+	default 0x100000 if SICR_I2C2_CKSTOP
+
+config SICRL_ETSEC1_A
+	hex
+	default 0x0 if SICR_ETSEC1_A_TSEC2
+	default 0x40 if SICR_ETSEC1_A_TSEC_GTX_CLK125
+
+config SICRH_ESDHC_A
+	hex
+	default 0x0 if SICR_ESDHC_A_SD
+	default 0x40000000 if SICR_ESDHC_A_GTM
+	default 0xc0000000 if SICR_ESDHC_A_GPIO
+
+config SICRH_ESDHC_B
+	hex
+	default 0x0 if SICR_ESDHC_B_SD
+	default 0x10000000 if SICR_ESDHC_B_GTM
+	default 0x30000000 if SICR_ESDHC_B_GPIO
+
+config SICRH_ESDHC_C
+	hex
+	default 0x0 if SICR_ESDHC_C_SD
+	default 0x4000000 if SICR_ESDHC_C_GTM
+	default 0xc000000 if SICR_ESDHC_C_GPIO
+
+config SICRH_GPIO_A
+	hex
+	default 0x0 if SICR_GPIO_A_GPIO
+	default 0x1000000 if SICR_GPIO_A_TSEC2
+
+config SICRH_GPIO_B
+	hex
+	default 0x0 if SICR_GPIO_B_GPIO
+	default 0x400000 if SICR_GPIO_B_TSEC2
+	default 0x800000 if SICR_GPIO_B_TSEC_GTX_CLK125
+
+config SICRH_IEEE1588_A
+	hex
+	default 0x100000 if SICR_IEEE1588_A_TSEC
+	default 0x300000 if SICR_IEEE1588_A_GPIO
+
+config SICRH_USB
+	hex
+	default 0x40000 if SICR_USB_TSEC
+
+config SICRH_GTM
+	hex
+	default 0x10000 if SICR_GTM_TSEC
+	default 0x30000 if SICR_GTM_GPIO
+
+config SICRH_IEEE1588_B
+	hex
+	default 0xc000 if SICR_IEEE1588_B_GPIO
+
+config SICRH_ETSEC2
+	hex
+	default 0x1000 if SICR_ETSEC2_TSEC2
+	default 0x3000 if SICR_ETSEC2_GPIO
+
+config SICRH_GPIOSEL
+	hex
+	default 0x0 if SICR_GPIOSEL_GPIO
+	default 0x100 if SICR_GPIOSEL_IEEE1588
+
+config SICRH_TMROBI
+	hex
+	default 0x0 if SICR_TMROBI_3_3_V
+	default 0x10 if SICR_TMROBI_2_5_V
+
+config SICRH_TMSOBI1
+	hex
+	default 0x0 if SICR_TMSOBI1_3_3_V
+	default 0x2 if SICR_TMSOBI1_2_5_V
+
+config SICRH_TMSOBI2
+	hex
+	default 0x0 if SICR_TMSOBI2_3_3_V
+	default 0x1 if SICR_TMSOBI2_2_5_V
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/sysio/sysio.h b/roms/u-boot/arch/powerpc/cpu/mpc83xx/sysio/sysio.h
new file mode 100644
index 000000000..f8c2f104c
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/sysio/sysio.h
@@ -0,0 +1,32 @@
+#ifdef CONFIG_ARCH_MPC8308
+
+#ifndef CONFIG_SYS_SICRL
+#define CONFIG_SYS_SICRL (\
+	CONFIG_SICRL_SPI |\
+	CONFIG_SICRL_UART |\
+	CONFIG_SICRL_IRQ |\
+	CONFIG_SICRL_I2C2 |\
+	CONFIG_SICRL_ETSEC1_A \
+)
+#endif
+
+#ifndef CONFIG_SYS_SICRH
+#define CONFIG_SYS_SICRH (\
+	CONFIG_SICRH_ESDHC_A |\
+	CONFIG_SICRH_ESDHC_B |\
+	CONFIG_SICRH_ESDHC_C |\
+	CONFIG_SICRH_GPIO_A |\
+	CONFIG_SICRH_GPIO_B |\
+	CONFIG_SICRH_IEEE1588_A |\
+	CONFIG_SICRH_USB |\
+	CONFIG_SICRH_GTM |\
+	CONFIG_SICRH_IEEE1588_B |\
+	CONFIG_SICRH_ETSEC2 |\
+	CONFIG_SICRH_GPIOSEL |\
+	CONFIG_SICRH_TMROBI |\
+	CONFIG_SICRH_TMSOBI1 |\
+	CONFIG_SICRH_TMSOBI2 \
+)
+#endif
+
+#endif
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/traps.c b/roms/u-boot/arch/powerpc/cpu/mpc83xx/traps.c
new file mode 100644
index 000000000..22e451c58
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/traps.c
@@ -0,0 +1,218 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
+ */
+
+/*
+ * This file handles the architecture-dependent parts of hardware
+ * exceptions
+ */
+
+#include <common.h>
+#include <asm/global_data.h>
+#include <asm/ptrace.h>
+#include <command.h>
+#include <kgdb.h>
+#include <asm/processor.h>
+#include <asm/mpc8349_pci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Returns 0 if exception not found and fixup otherwise.  */
+extern unsigned long search_exception_table(unsigned long);
+
+#define END_OF_MEM	(gd->ram_base + gd->ram_size)
+
+/*
+ * Trap & Exception support
+ */
+
+static void print_backtrace(unsigned long *sp)
+{
+	int cnt = 0;
+	unsigned long i;
+
+	puts ("Call backtrace: ");
+	while (sp) {
+		if ((uint)sp > END_OF_MEM)
+			break;
+
+		i = sp[1];
+		if (cnt++ % 7 == 0)
+			putc ('\n');
+		printf("%08lX ", i);
+		if (cnt > 32) break;
+		sp = (unsigned long *)*sp;
+	}
+	putc ('\n');
+}
+
+void show_regs(struct pt_regs *regs)
+{
+	int i;
+
+	printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
+	       regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
+	printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
+	       regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
+	       regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
+	       regs->msr&MSR_IR ? 1 : 0,
+	       regs->msr&MSR_DR ? 1 : 0);
+
+	putc ('\n');
+	for (i = 0;  i < 32;  i++) {
+		if ((i % 8) == 0) {
+			printf("GPR%02d: ", i);
+		}
+
+		printf("%08lX ", regs->gpr[i]);
+		if ((i % 8) == 7) {
+			putc ('\n');
+		}
+	}
+}
+
+
+static void _exception(int signr, struct pt_regs *regs)
+{
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
+}
+
+#ifdef CONFIG_PCI
+void dump_pci (void)
+{
+/*
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	printf ("PCI: err status %x err mask %x err ctrl %x\n",
+		le32_to_cpu (immap->im_pci.pci_esr),
+		le32_to_cpu (immap->im_pci.pci_emr),
+		le32_to_cpu (immap->im_pci.pci_ecr));
+	printf ("     error address %x error data %x ctrl %x\n",
+		le32_to_cpu (immap->im_pci.pci_eacr),
+		le32_to_cpu (immap->im_pci.pci_edcr),
+		le32_to_cpu (immap->im_pci.pci_eccr));
+*/
+}
+#endif
+
+void MachineCheckException(struct pt_regs *regs)
+{
+	unsigned long fixup;
+
+	/* Probing PCI using config cycles cause this exception
+	 * when a device is not present.  Catch it and return to
+	 * the PCI exception handler.
+	 */
+#ifdef CONFIG_PCI
+#if 0
+	volatile immap_t *immap  = (immap_t *)CONFIG_SYS_IMMR;
+#ifdef DEBUG
+	dump_pci();
+#endif
+	/* clear the error in the error status register */
+	if(immap->im_pci.pci_esr & cpu_to_le32(PCI_ERROR_PCI_NO_RSP)) {
+		immap->im_pci.pci_esr = cpu_to_le32(PCI_ERROR_PCI_NO_RSP);
+		return;
+	}
+#endif
+#endif /* CONFIG_PCI */
+	if ((fixup = search_exception_table(regs->nip)) != 0) {
+		regs->nip = fixup;
+		return;
+	}
+
+#if defined(CONFIG_CMD_KGDB)
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+		return;
+#endif
+
+	puts ("Machine check in kernel mode.\n"
+		"Caused by (from msr): ");
+	printf("regs %p ",regs);
+	switch( regs->msr & 0x000F0000) {
+	case (0x80000000>>12):
+		puts ("Machine check signal - probably due to mm fault\n"
+			"with mmu off\n");
+		break;
+	case (0x80000000>>13):
+		puts ("Transfer error ack signal\n");
+		break;
+	case (0x80000000>>14):
+		puts ("Data parity signal\n");
+		break;
+	case (0x80000000>>15):
+		puts ("Address parity signal\n");
+		break;
+	default:
+		puts ("Unknown values in msr\n");
+	}
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+#ifdef CONFIG_PCI
+	dump_pci();
+#endif
+	panic("machine check");
+}
+
+void AlignmentException(struct pt_regs *regs)
+{
+#if defined(CONFIG_CMD_KGDB)
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+		return;
+#endif
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Alignment Exception");
+}
+
+void ProgramCheckException(struct pt_regs *regs)
+{
+#if defined(CONFIG_CMD_KGDB)
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+		return;
+#endif
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Program Check Exception");
+}
+
+void SoftEmuException(struct pt_regs *regs)
+{
+#if defined(CONFIG_CMD_KGDB)
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+		return;
+#endif
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Software Emulation Exception");
+}
+
+
+void UnknownException(struct pt_regs *regs)
+{
+#if defined(CONFIG_CMD_KGDB)
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+		return;
+#endif
+	printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
+	       regs->nip, regs->msr, regs->trap);
+	_exception(0, regs);
+}
+
+#if defined(CONFIG_CMD_BEDBUG)
+extern void do_bedbug_breakpoint(struct pt_regs *);
+#endif
+
+void DebugException(struct pt_regs *regs)
+{
+	printf("Debugger trap at @ %lx\n", regs->nip );
+	show_regs(regs);
+#if defined(CONFIG_CMD_BEDBUG)
+	do_bedbug_breakpoint( regs );
+#endif
+}
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds b/roms/u-boot/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds
new file mode 100644
index 000000000..856d3b3e1
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+	. = 0xfff00000;
+	.text : {
+		*(.text*)
+		. = ALIGN(16);
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
+
+	. = ALIGN(8);
+	.data : {
+		*(.data*)
+		*(.sdata*)
+		_GOT2_TABLE_ = .;
+		KEEP(*(.got2))
+		KEEP(*(.got))
+	}
+	__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
+
+	. = ALIGN(8);
+	__bss_start = .;
+	.bss (NOLOAD) : {
+		*(.*bss)
+	}
+	__bss_end = .;
+}
+ENTRY(_start)
+ASSERT(__bss_end <= 0xfff01000, "NAND bootstrap too big");
diff --git a/roms/u-boot/arch/powerpc/cpu/mpc83xx/u-boot.lds b/roms/u-boot/arch/powerpc/cpu/mpc83xx/u-boot.lds
new file mode 100644
index 000000000..d10f528da
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/cpu/mpc83xx/u-boot.lds
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2006-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  .text      :
+  {
+    arch/powerpc/cpu/mpc83xx/start.o	(.text*)
+    *(.text*)
+    . = ALIGN(16);
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    KEEP(*(.got))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	KEEP(*(SORT(.u_boot_list*)));
+  }
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  /*
+   * _end - This is end of u-boot.bin image.
+   * dtb will be appended here to make u-boot-dtb.bin
+   */
+  _end = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  __bss_end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)