Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

158 files changed, 12547 insertions, 0 deletions

diff --git a/roms/u-boot/arch/powerpc/dts/.gitignore b/roms/u-boot/arch/powerpc/dts/.gitignore
new file mode 100644
index 000000000..b60ed208c
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/.gitignore
@@ -0,0 +1 @@
+*.dtb
diff --git a/roms/u-boot/arch/powerpc/dts/Makefile b/roms/u-boot/arch/powerpc/dts/Makefile
new file mode 100644
index 000000000..ceaa8ce5c
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/Makefile
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+dtb-$(CONFIG_TARGET_KMCENT2) += kmcent2.dtb
+dtb-$(CONFIG_TARGET_KMCOGE5NE) += kmcoge5ne.dtb
+dtb-$(CONFIG_TARGET_KMETER1) += kmeter1.dtb
+dtb-$(CONFIG_TARGET_KMOPTI2) += kmopti2.dtb
+dtb-$(CONFIG_TARGET_KMSUPX5) += kmsupc5.dtb kmsupm5.dtb
+dtb-$(CONFIG_TARGET_KMTEGR1) += kmtegr1.dtb
+dtb-$(CONFIG_TARGET_KMTEPR2) += kmtepr2.dtb
+dtb-$(CONFIG_TARGET_MPC837XERDB) += mpc8379erdb.dtb
+dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb
+dtb-$(CONFIG_TARGET_P1010RDB_PA) += p1010rdb-pa.dtb p1010rdb-pa_36b.dtb
+dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb
+dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
+dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
+dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb
+dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb
+dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb
+dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb
+dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb
+dtb-$(CONFIG_TARGET_SOCRATES) += socrates.dtb
+dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb
+dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb
+dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
+dtb-$(CONFIG_TARGET_T2080RDB) += t2080rdb.dtb
+dtb-$(CONFIG_TARGET_T4240RDB) += t4240rdb.dtb
+dtb-$(CONFIG_TARGET_TUGE1) += kmtuge1.dtb
+dtb-$(CONFIG_TARGET_TUXX1) += kmtuxa1.dtb
+dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb
+dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb
+
+targets += $(dtb-y)
+
+# Add any required device tree compiler flags here
+DTC_FLAGS +=
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+	@:
+
+clean-files := *.dtb
diff --git a/roms/u-boot/arch/powerpc/dts/e500mc_power_isa.dtsi b/roms/u-boot/arch/powerpc/dts/e500mc_power_isa.dtsi
new file mode 100644
index 000000000..e486ae501
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/e500mc_power_isa.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * e500mc Power ISA Device Tree Source (include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/ {
+	cpus {
+		power-isa-version = "2.06";
+		power-isa-b;		// Base
+		power-isa-e;		// Embedded
+		power-isa-atb;		// Alternate Time Base
+		power-isa-cs;		// Cache Specification
+		power-isa-ds;		// Decorated Storage
+		power-isa-e.ed;		// Embedded.Enhanced Debug
+		power-isa-e.pd;		// Embedded.External PID
+		power-isa-e.hv;		// Embedded.Hypervisor
+		power-isa-e.le;		// Embedded.Little-Endian
+		power-isa-e.pm;		// Embedded.Performance Monitor
+		power-isa-e.pc;		// Embedded.Processor Control
+		power-isa-ecl;		// Embedded Cache Locking
+		power-isa-exp;		// External Proxy
+		power-isa-fp;		// Floating Point
+		power-isa-fp.r;		// Floating Point.Record
+		power-isa-mmc;		// Memory Coherence
+		power-isa-scpm;		// Store Conditional Page Mobility
+		power-isa-wt;		// Wait
+		fsl,eref-deo;		// Data Cache Extended Operations
+		mmu-type = "power-embedded";
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/e500v2_power_isa.dtsi b/roms/u-boot/arch/powerpc/dts/e500v2_power_isa.dtsi
new file mode 100644
index 000000000..010e8e5f3
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/e500v2_power_isa.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * e500v2 Power ISA Device Tree Source (include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/ {
+	cpus {
+		power-isa-version = "2.03";
+		power-isa-b;		// Base
+		power-isa-e;		// Embedded
+		power-isa-atb;		// Alternate Time Base
+		power-isa-cs;		// Cache Specification
+		power-isa-e.le;		// Embedded.Little-Endian
+		power-isa-e.pm;		// Embedded.Performance Monitor
+		power-isa-ecl;		// Embedded Cache Locking
+		power-isa-mmc;		// Memory Coherence
+		power-isa-sp;		// Signal Processing Engine
+		power-isa-sp.fd;	// SPE.Embedded Float Scalar Double
+		power-isa-sp.fs;	// SPE.Embedded Float Scalar Single
+		power-isa-sp.fv;	// SPE.Embedded Float Vector
+		mmu-type = "power-embedded";
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/e5500_power_isa.dtsi b/roms/u-boot/arch/powerpc/dts/e5500_power_isa.dtsi
new file mode 100644
index 000000000..0a0943b0b
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/e5500_power_isa.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * e5500 Power ISA Device Tree Source (include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/ {
+	cpus {
+		power-isa-version = "2.06";
+		power-isa-b;		// Base
+		power-isa-e;		// Embedded
+		power-isa-atb;		// Alternate Time Base
+		power-isa-cs;		// Cache Specification
+		power-isa-ds;		// Decorated Storage
+		power-isa-e.ed;		// Embedded.Enhanced Debug
+		power-isa-e.pd;		// Embedded.External PID
+		power-isa-e.hv;		// Embedded.Hypervisor
+		power-isa-e.le;		// Embedded.Little-Endian
+		power-isa-e.pm;		// Embedded.Performance Monitor
+		power-isa-e.pc;		// Embedded.Processor Control
+		power-isa-ecl;		// Embedded Cache Locking
+		power-isa-exp;		// External Proxy
+		power-isa-fp;		// Floating Point
+		power-isa-fp.r;		// Floating Point.Record
+		power-isa-mmc;		// Memory Coherence
+		power-isa-scpm;		// Store Conditional Page Mobility
+		power-isa-wt;		// Wait
+		power-isa-64;		// 64-bit
+		fsl,eref-deo;		// Data Cache Extended Operations
+		mmu-type = "power-embedded";
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/e6500_power_isa.dtsi b/roms/u-boot/arch/powerpc/dts/e6500_power_isa.dtsi
new file mode 100644
index 000000000..1b06170c7
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/e6500_power_isa.dtsi
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * e6500 Power ISA Device Tree Source (include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2018 NXP
+ */
+
+/ {
+	cpus {
+		power-isa-version = "2.06";
+		power-isa-b;		// Base
+		power-isa-e;		// Embedded
+		power-isa-atb;		// Alternate Time Base
+		power-isa-cs;		// Cache Specification
+		power-isa-ds;		// Decorated Storage
+		power-isa-e.ed;		// Embedded.Enhanced Debug
+		power-isa-e.pd;		// Embedded.External PID
+		power-isa-e.hv;		// Embedded.Hypervisor
+		power-isa-e.le;		// Embedded.Little-Endian
+		power-isa-e.pm;		// Embedded.Performance Monitor
+		power-isa-e.pc;		// Embedded.Processor Control
+		power-isa-ecl;		// Embedded Cache Locking
+		power-isa-exp;		// External Proxy
+		power-isa-fp;		// Floating Point
+		power-isa-fp.r;		// Floating Point.Record
+		power-isa-mmc;		// Memory Coherence
+		power-isa-scpm;		// Store Conditional Page Mobility
+		power-isa-wt;		// Wait
+		power-isa-64;		// 64-bit
+		power-isa-e.pt;		// Embedded.Page Table
+		power-isa-e.hv.lrat;	// Embedded.Hypervisor.LRAT
+		power-isa-e.em;		// Embedded Multi-Threading
+		power-isa-v;		// Vector (AltiVec)
+		fsl,eref-er;		// Enhanced Reservations
+		fsl,eref-deo;		// Data Cache Extended Operations
+		mmu-type = "power-embedded";
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/elo3-dma-0.dtsi b/roms/u-boot/arch/powerpc/dts/elo3-dma-0.dtsi
new file mode 100644
index 000000000..c3f773725
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/elo3-dma-0.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x100000 ]
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ */
+
+dma0: dma@100300 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "fsl,elo3-dma";
+	reg = <0x100300 0x4>,
+	      <0x100600 0x4>;
+	ranges = <0x0 0x100100 0x500>;
+	dma-channel@0 {
+		compatible = "fsl,eloplus-dma-channel";
+		reg = <0x0 0x80>;
+		interrupts = <28 2 0 0>;
+	};
+	dma-channel@80 {
+		compatible = "fsl,eloplus-dma-channel";
+		reg = <0x80 0x80>;
+		interrupts = <29 2 0 0>;
+	};
+	dma-channel@100 {
+		compatible = "fsl,eloplus-dma-channel";
+		reg = <0x100 0x80>;
+		interrupts = <30 2 0 0>;
+	};
+	dma-channel@180 {
+		compatible = "fsl,eloplus-dma-channel";
+		reg = <0x180 0x80>;
+		interrupts = <31 2 0 0>;
+	};
+	dma-channel@300 {
+		compatible = "fsl,eloplus-dma-channel";
+		reg = <0x300 0x80>;
+		interrupts = <76 2 0 0>;
+	};
+	dma-channel@380 {
+		compatible = "fsl,eloplus-dma-channel";
+		reg = <0x380 0x80>;
+		interrupts = <77 2 0 0>;
+	};
+	dma-channel@400 {
+		compatible = "fsl,eloplus-dma-channel";
+		reg = <0x400 0x80>;
+		interrupts = <78 2 0 0>;
+	};
+	dma-channel@480 {
+		compatible = "fsl,eloplus-dma-channel";
+		reg = <0x480 0x80>;
+		interrupts = <79 2 0 0>;
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/elo3-dma-1.dtsi b/roms/u-boot/arch/powerpc/dts/elo3-dma-1.dtsi
new file mode 100644
index 000000000..a61c88649
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/elo3-dma-1.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x101000 ]
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ */
+
+dma1: dma@101300 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "fsl,elo3-dma";
+	reg = <0x101300 0x4>,
+	      <0x101600 0x4>;
+	ranges = <0x0 0x101100 0x500>;
+	dma-channel@0 {
+		compatible = "fsl,eloplus-dma-channel";
+		reg = <0x0 0x80>;
+		interrupts = <32 2 0 0>;
+	};
+	dma-channel@80 {
+		compatible = "fsl,eloplus-dma-channel";
+		reg = <0x80 0x80>;
+		interrupts = <33 2 0 0>;
+	};
+	dma-channel@100 {
+		compatible = "fsl,eloplus-dma-channel";
+		reg = <0x100 0x80>;
+		interrupts = <34 2 0 0>;
+	};
+	dma-channel@180 {
+		compatible = "fsl,eloplus-dma-channel";
+		reg = <0x180 0x80>;
+		interrupts = <35 2 0 0>;
+	};
+	dma-channel@300 {
+		compatible = "fsl,eloplus-dma-channel";
+		reg = <0x300 0x80>;
+		interrupts = <80 2 0 0>;
+	};
+	dma-channel@380 {
+		compatible = "fsl,eloplus-dma-channel";
+		reg = <0x380 0x80>;
+		interrupts = <81 2 0 0>;
+	};
+	dma-channel@400 {
+		compatible = "fsl,eloplus-dma-channel";
+		reg = <0x400 0x80>;
+		interrupts = <82 2 0 0>;
+	};
+	dma-channel@480 {
+		compatible = "fsl,eloplus-dma-channel";
+		reg = <0x480 0x80>;
+		interrupts = <83 2 0 0>;
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/gazerbeam.dts b/roms/u-boot/arch/powerpc/dts/gazerbeam.dts
new file mode 100644
index 000000000..96c03c77a
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/gazerbeam.dts
@@ -0,0 +1,602 @@
+/*
+ * Gazerbeam CON Device Tree Source
+ *
+ * (C) Copyright 2015
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include "gdsys/mpc8308.dtsi"
+
+/include/ "gdsys/gazerbeam-base.dtsi"
+
+/include/ "gdsys/soc/i2c/cirrus-audio-codec.dtsi"
+/include/ "gdsys/soc/i2c/dallas-rtc.dtsi"
+/include/ "gdsys/soc/lbc/gazerbeam.dtsi"
+/include/ "gdsys/soc/nor/flash-80k-partition.dtsi"
+
+&board_lbc {
+	FPGA0:iocon_uart@1,0 {
+		reg = <0x1 0x0 0x100000>;
+		little-endian;
+		interrupts = <48 0x8>;
+		interrupt-parent = <&ipic>;
+	};
+
+	FPGA1:iocon_uart@2,0 {
+		reg = <0x2 0x0 0x100000>;
+		little-endian;
+		interrupts = <17 0x8>;
+		interrupt-parent = <&ipic>;
+	};
+};
+
+&FPGA0 {
+	compatible = "gdsys,iocon_fpga";
+	#gpio-cells = <2>;
+	gpio-controller;
+	bus = <&FPGA0BUS>;
+	unit_id = <0>;
+	fpga-type = <1>;
+	usb_base = <0x0080>;
+	audio_base = <0x0040>;
+	timebase_base = <0x013c>;
+
+	/*
+	 * for every interrupt source there must be a dataset specifying
+	 * 1. type (1: standard)
+	 * 2. status register offset
+	 * 3. mask register offset
+	 * 4. default mask
+	 */
+	fpga_interrupt_sources =
+		<1 0x000a 0x000c 0x4000>, /* 0: TOP_INTERRUPT */
+		<1 0x001c 0x001e 0x0000>; /* 1: EXTENDED_INTERRUPT */
+	/*
+	 * for every interrupt there must be a dataset specifying
+	 * 1. type (1: status, 2: event)
+	 * 2. interrupt source index
+	 * 3. interrupt register bit
+	 * 4. mask register bit
+	 */
+	 #fpga_interrupt_map-cells = <4>;
+	fpga_interrupt_map =
+		<1 0 14 14>, /*  0: EXTENDED_INTERRUPT */
+		<1 0  0  0>, /*  1: VIDEO 0 */
+		<1 0  1  1>, /*  2: VIDEO 1 */
+		<1 0  2  2>, /*  3: VIDEO IC 0 */
+		<1 0  3  3>, /*  4: VIDEO IC 1 */
+		<1 0  4  4>, /*  5: IIC MAIN */
+		<1 0  6  6>, /*  6: IIC VIDEO 0 */
+		<1 0  7  7>, /*  7: IIC VIDEO 1 */
+		<1 1  0  0>, /*  8: OSD 0 */
+		<1 1  1  1>, /*  9: OSD 1 */
+		<1 1  2  2>, /* 10: SPDIF 0 */
+		<1 1  3  3>, /* 11: SPDIF 1 */
+		<1 0 12 12>, /* 12: COMM 0 */
+		<1 0 13 13>, /* 13: COMM 1 */
+		<1 0 10 10>, /* 14: COMM 2 */
+		<1 0 11 11>, /* 15: COMM 3 */
+		<2 0  5  5>, /* 16: MDIO */
+		<1 0  8  8>, /* 17: PHY */
+		<1 1  4  4>, /* 18: RS232 */
+		<1 1  5  5>, /* 19: AUDIO */
+		<1 1  8  8>, /* 20: PROC_AUDIO */
+		<1 1  7  7>, /* 21: USB/ETH-UART INT */
+		<2 1 10 10>, /* 22: AXI Bridge 0 */
+		<2 1 11 11>, /* 23: AXI Bridge 1 */
+		<2 1  9  9>, /* 24: USB/ETH-Secondary IIC */
+		<>;
+};
+
+&FPGA1 {
+	compatible = "gdsys,iocon_fpga";
+	#gpio-cells = <2>;
+	gpio-controller;
+	bus = <&FPGA1BUS>;
+	unit_id = <1>;
+	fpga-type = <1>;
+	usb_base = <0x0070>;
+	audio_base = <0x0040>;
+	timebase_base = <0x013c>;
+
+	/*
+	 * for every interrupt source there must be a dataset specifying
+	 * 1. type (1: standard)
+	 * 2. status register offset
+	 * 3. mask register offset
+	 * 4. default mask
+	 */
+	fpga_interrupt_sources =
+		<1 0x000a 0x000c 0x4000>, /* 0: TOP_INTERRUPT */
+		<1 0x001c 0x001e 0x0000>; /* 1: EXTENDED_INTERRUPT */
+	/*
+	 * for every interrupt there must be a dataset specifying
+	 * 1. type (1: status, 2: event)
+	 * 2. interrupt source index
+	 * 3. interrupt register bit
+	 * 4. mask register bit
+	 */
+	 #fpga_interrupt_map-cells = <4>;
+	fpga_interrupt_map =
+		<1 0 14 14>, /*  0: EXTENDED_INTERRUPT */
+		<1 0  0  0>, /*  1: VIDEO 0 */
+		<1 0  1  1>, /*  2: VIDEO 1 */
+		<1 0  2  2>, /*  3: VIDEO IC 0 */
+		<1 0  3  3>, /*  4: VIDEO IC 1 */
+		<1 0  4  4>, /*  5: IIC MAIN */
+		<1 0  6  6>, /*  6: IIC VIDEO 0 */
+		<1 0  7  7>, /*  7: IIC VIDEO 1 */
+		<1 1  0  0>, /*  8: OSD 0 */
+		<1 1  1  1>, /*  9: OSD 1 */
+		<1 1  2  2>, /* 10: SPDIF 0 */
+		<1 1  3  3>, /* 11: SPDIF 1 */
+		<1 0 12 12>, /* 12: COMM 0 */
+		<1 0 13 13>, /* 13: COMM 1 */
+		<1 0 10 10>, /* 14: COMM 2 */
+		<1 0 11 11>, /* 15: COMM 3 */
+		<2 0  5  5>, /* 16: MDIO */
+		<1 0  8  8>, /* 17: PHY */
+		<1 1  4  4>, /* 18: RS232 */
+		<1 1  5  5>, /* 19: AUDIO */
+		<1 1  8  8>, /* 20: PROC_AUDIO */
+		<1 1  7  7>, /* 21: USB/ETH-UART INT */
+		<2 1 10 10>, /* 22: AXI Bridge 0 */
+		<2 1 11 11>, /* 23: AXI Bridge 1 */
+		<2 1  9  9>, /* 24: USB/ETH-Secondary IIC */
+		<>;
+};
+
+/ {
+	FPGA0BUS: fpga0bus {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0x00002000>;
+
+		compatible = "gdsys,soc";
+
+		fpga0_rs232 {
+			compatible = "gdsys,ihs_trans_rs232";
+			reg = <0x50 0x08>;
+			little-endian;
+		};
+
+		fpga0_uart_usb {
+			compatible = "gdsys,ihs_simple_uart";
+			reg = <0xa0 0x08>;
+			little-endian;
+			fpga_interrupts = <21>;
+			line = <0>;
+		};
+
+		fpga0_iic_main {
+			compatible = "gdsys,ihs_i2cmaster";
+			reg = <0x60 0x10>;
+			little-endian;
+			fpga_interrupts = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			fpga0_dp_video0_redriver: fpga0_dp_video0_redriver {
+				compatible = "ti,sn75dp130";
+				reg = <0x2c>;
+				eq-i2c-enable = <3 2 1 0
+						 3 2 1 0
+						 3 2 1 0
+						 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
+			};
+			fpga0_dp_video1_redriver: fpga0_dp_video1_redriver {
+				compatible = "ti,sn75dp130";
+				reg = <0x2e>;
+				eq-i2c-enable = <3 2 1 0
+						 3 2 1 0
+						 3 2 1 0
+						 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
+			};
+			lm77@48 {
+				compatible = "national,lm77";
+				reg = <0x48>;
+			};
+			ads1015@49 {
+				compatible = "ti,ads1015";
+				reg = <0x49>;
+			};
+			ads1015@4b {
+				compatible = "ti,ads1015";
+				reg = <0x4b>;
+			};
+		};
+
+		fpga0_video0 {
+			compatible = "gdsys,ihs_video_out";
+			reg = <0x100 0x40>;
+			little-endian;
+			fpga_interrupts = <1 8>; /* VIDEO OSD */
+			osd_base = <0x180>;
+			osd_buffer_base = <0x1000>;
+			spdif_audio_base = <0x1e0>;
+			video_index = <0>;
+			video_id = <0>;
+			fpga-force-pos-pol;
+			sync-source;
+			fpga-pb-pixels = <2730>; /* 8192 / 3 */
+			fpga-ra-lines = <2>;
+			video_tx = <&fpga0_dp_video0>;
+			clk_gen = <&fpga0_video0_clkgen>;
+			ddc_ci = <&fpga0_dp_video0>;
+		};
+
+		fpga0_iic_video0  {
+			compatible = "gdsys,ihs_i2cmaster";
+			reg = <0x1c0 0x10>;
+			little-endian;
+			fpga_interrupts = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			fpga0_video0_clkgen: fpga0_video0_clkgen {
+				compatible = "idt,ics8n3qv01";
+				reg = <0x6e>;
+				channel = <0>;
+			};
+		};
+
+		fpga0_axi_video0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "gdsys,ihs_axi";
+			reg = <0x170 0x10>;
+			little-endian;
+			fpga_interrupts = <22>;
+
+			fpga0_dp_video0: fpga0_dp_video0 {
+				compatible = "gdsys,logicore_dp_tx";
+				reg = <0x44a10000 0x1000>;
+				little-endian;
+				redriver = <&fpga0_dp_video0_redriver>;
+				video_id = <0>;
+			};
+		};
+
+		fpga0_video1 {
+			compatible = "gdsys,ihs_video_out";
+			reg = <0x200 0x40>;
+			little-endian;
+			fpga_interrupts = <2 9>; /* VIDEO OSD */
+			osd_base = <0x280>;
+			osd_buffer_base = <0x2000>;
+			spdif_audio_base = <0x2e0>;
+			video_index = <1>;
+			video_id = <1>;
+			fpga-force-pos-pol;
+			sync-source;
+			fpga-pb-pixels = <2730>; /* 8192 / 3 */
+			fpga-ra-lines = <2>;
+			video_tx = <&fpga0_dp_video1>;
+			clk_gen = <&fpga0_video1_clkgen>;
+			ddc_ci = <&fpga0_dp_video1>;
+		};
+
+		fpga0_iic_video1  {
+			compatible = "gdsys,ihs_i2cmaster";
+			reg = <0x2c0 0x10>;
+			little-endian;
+			fpga_interrupts = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			fpga0_video1_clkgen: fpga0_video1_clkgen {
+				compatible = "idt,ics8n3qv01";
+				reg = <0x6e>;
+				channel = <1>;
+			};
+		};
+
+		fpga0_axi_video1 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "gdsys,ihs_axi";
+			reg = <0x270 0x10>;
+			little-endian;
+			fpga_interrupts = <23>;
+
+			fpga0_dp_video1: fpga0_dp_video1 {
+				compatible = "gdsys,logicore_dp_tx";
+				reg = <0x44a10000 0x1000>;
+				little-endian;
+				redriver = <&fpga0_dp_video1_redriver>;
+				video_id = <1>;
+			};
+		};
+
+		fpga0_iic_usb {
+			compatible = "gdsys,ihs_i2cmaster";
+			reg = <0xb0 0x10>;
+			little-endian;
+			fpga_interrupts = <24>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pca9555@20 {
+				compatible = "nxp,pca9555";
+				reg = <0x20>;
+				#gpio-cells = <2>;
+				gpio-controller;
+			};
+		};
+
+		fpga0_ep0 {
+			compatible = "gdsys,io-endpoint";
+			reg = < 0x020 0x10
+				0x320 0x10
+				0x340 0x10
+				0x360 0x10>;
+			little-endian;
+			irq-model-local;
+			fpga_interrupts = <12 13 14 15>;
+			pollcycle = <200>;
+			nprot_channel = <16>;
+			uart_line = <0>;
+			ep_index = <0>;
+			line_protocol = <1>;
+		};
+
+		fpga0_mdio {
+			compatible = "gdsys,ihs_mdiomaster";
+			reg = <0x0058 0x10>;
+			little-endian;
+			fpga_interrupts = <16>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			fpga0_phy0 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				device_type ="ethernet-phy";
+				reg = <0>;
+			};
+			fpga0_phy1 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				device_type ="ethernet-phy";
+				reg = <1>;
+			};
+			fpga0_phy2 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				device_type ="ethernet-phy";
+				reg = <2>;
+			};
+			fpga0_phy3 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				device_type ="ethernet-phy";
+				reg = <3>;
+			};
+		};
+
+	};
+
+
+	FPGA1BUS: fpga1bus {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0x00002000>;
+
+		compatible = "gdsys,soc";
+
+		fpga1_uart_usb {
+			compatible = "gdsys,ihs_simple_uart";
+			reg = <0xa0 0x08>;
+			little-endian;
+			fpga_interrupts = <21>;
+			line = <4>; /* TODO check and FIX */
+		};
+
+		fpga1_iic_main {
+			compatible = "gdsys,ihs_i2cmaster";
+			reg = <0x60 0x10>;
+			little-endian;
+			fpga_interrupts = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			fpga1_dp_video0_redriver: fpga1_dp_video0_redriver {
+				compatible = "ti,sn75dp130";
+				reg = <0x2c>;
+				eq-i2c-enable = <3 2 1 0
+						 3 2 1 0
+						 3 2 1 0
+						 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
+			};
+			fpga1_dp_video1_redriver: fpga1_dp_video1_redriver {
+				compatible = "ti,sn75dp130";
+				reg = <0x2e>;
+				eq-i2c-enable = <3 2 1 0
+						 3 2 1 0
+						 3 2 1 0
+						 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
+			};
+			lm77@48 {
+				compatible = "national,lm77";
+				reg = <0x48>;
+			};
+			ads1015@49 {
+				compatible = "ti,ads1015";
+				reg = <0x49>;
+			};
+			ads1015@4b {
+				compatible = "ti,ads1015";
+				reg = <0x4b>;
+			};
+		};
+
+		fpga1_video0 {
+			compatible = "gdsys,ihs_video_out";
+			reg = <0x100 0x40>;
+			little-endian;
+			fpga_interrupts = <1 8>; /* VIDEO OSD */
+			osd_base = <0x180>;
+			osd_buffer_base = <0x1000>;
+			spdif_audio_base = <0x1e0>;
+			video_index = <0>;
+			video_id = <4>;
+			fpga-force-pos-pol;
+			sync-source;
+			fpga-pb-pixels = <2730>; /* 8192 / 3 */
+			fpga-ra-lines = <2>;
+			video_tx = <&fpga1_dp_video0>;
+			clk_gen = <&fpga1_video0_clkgen>;
+			ddc_ci = <&fpga1_dp_video0>;
+		};
+
+		fpga1_iic_video0  {
+			compatible = "gdsys,ihs_i2cmaster";
+			reg = <0x1c0 0x10>;
+			little-endian;
+			fpga_interrupts = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			fpga1_video0_clkgen: fpga1_video0_clkgen {
+				compatible = "idt,ics8n3qv01";
+				reg = <0x6e>;
+				channel = <4>;
+			};
+		};
+
+		fpga1_axi_video0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "gdsys,ihs_axi";
+			reg = <0x170 0x10>;
+			little-endian;
+			fpga_interrupts = <22>;
+
+			fpga1_dp_video0: fpga1_dp_video0 {
+				compatible = "gdsys,logicore_dp_tx";
+				reg = <0x44a10000 0x1000>;
+				little-endian;
+				redriver = <&fpga1_dp_video0_redriver>;
+				video_id = <4>;
+			};
+		};
+
+		fpga1_video1 {
+			compatible = "gdsys,ihs_video_out";
+			reg = <0x200 0x40>;
+			little-endian;
+			fpga_interrupts = <2 9>; /* VIDEO OSD */
+			osd_base = <0x280>;
+			osd_buffer_base = <0x2000>;
+			spdif_audio_base = <0x2e0>;
+			video_index = <1>;
+			video_id = <5>;
+			fpga-force-pos-pol;
+			sync-source;
+			fpga-pb-pixels = <2730>; /* 8192 / 3 */
+			fpga-ra-lines = <2>;
+			video_tx = <&fpga1_dp_video1>;
+			clk_gen = <&fpga1_video1_clkgen>;
+			ddc_ci = <&fpga1_dp_video1>;
+		};
+
+		fpga1_iic_video1  {
+			compatible = "gdsys,ihs_i2cmaster";
+			reg = <0x2c0 0x10>;
+			little-endian;
+			fpga_interrupts = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			fpga1_video1_clkgen: fpga1_video1_clkgen {
+				compatible = "idt,ics8n3qv01";
+				reg = <0x6e>;
+				channel = <5>;
+			};
+		};
+
+		fpga1_axi_video1 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "gdsys,ihs_axi";
+			reg = <0x270 0x10>;
+			little-endian;
+			fpga_interrupts = <23>;
+
+			fpga1_dp_video1: fpga1_dp_video1 {
+				compatible = "gdsys,logicore_dp_tx";
+				reg = <0x44a10000 0x1000>;
+				little-endian;
+				redriver = <&fpga1_dp_video1_redriver>;
+				video_id = <5>;
+			};
+		};
+
+		fpga1_iic_usb {
+			compatible = "gdsys,ihs_i2cmaster";
+			reg = <0xb0 0x10>;
+			little-endian;
+			fpga_interrupts = <24>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pca9555@20 {
+				compatible = "nxp,pca9555";
+				reg = <0x20>;
+				#gpio-cells = <2>;
+				gpio-controller;
+			};
+		};
+
+		fpga1_ep0 {
+			compatible = "gdsys,io-endpoint";
+			reg = < 0x020 0x10
+				0x320 0x10
+				0x340 0x10
+				0x360 0x10>;
+			little-endian;
+			irq-model-local;
+			fpga_interrupts = <12 13 14 15>;
+			pollcycle = <200>;
+			nprot_channel = <17>;
+			uart_line = <1>;
+			ep_index = <0>;
+			line_protocol = <1>;
+		};
+
+		fpga1_mdio {
+			compatible = "gdsys,ihs_mdiomaster";
+			reg = <0x0058 0x10>;
+			little-endian;
+			fpga_interrupts = <16>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			fpga1_phy0 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				device_type ="ethernet-phy";
+				reg = <0>;
+			};
+			fpga1_phy1 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				device_type ="ethernet-phy";
+				reg = <1>;
+			};
+			fpga1_phy2 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				device_type ="ethernet-phy";
+				reg = <2>;
+			};
+			fpga1_phy3 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				device_type ="ethernet-phy";
+				reg = <3>;
+			};
+		};
+
+	};
+
+};
+
+#include "gdsys/gazerbeam-uboot.dtsi"
diff --git a/roms/u-boot/arch/powerpc/dts/gdsys/gazerbeam-base.dtsi b/roms/u-boot/arch/powerpc/dts/gdsys/gazerbeam-base.dtsi
new file mode 100644
index 000000000..aca05f2cd
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/gdsys/gazerbeam-base.dtsi
@@ -0,0 +1,185 @@
+/*
+ * Gazerbeam Device Tree Source
+ *
+ * (C) Copyright 2015
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/ {
+	model = "gdsys,gazerbeam";
+	compatible = "fsl,mpc8308rdb";
+
+	aliases {
+		ethernet0 = &enet0;
+		ethernet1 = &enet1;
+	};
+
+	memory {
+		device_type = "memory";
+	};
+};
+
+&enet1 {
+	status = "okay";
+};
+
+&IIC {
+	fsl,preserve-clocking;
+
+	at97sc3205t@29 {
+		compatible = "atmel,at97sc3204t";
+		reg = <0x29>;
+	};
+
+	lm77@48 {
+		compatible = "national,lm77";
+		reg = <0x48>;
+	};
+
+	ads1015@49 {
+		compatible = "ti,ads1015";
+		reg = <0x49>;
+	};
+
+	lm77@4a {
+		compatible = "national,lm77";
+		reg = <0x4a>;
+	};
+
+	emc2305@2e {
+		compatible = "smsc,emc2305";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x2e>;
+		fan@0 {
+			reg = <0>;
+		};
+		fan@1 {
+			reg = <1>;
+		};
+		fan@2 {
+			reg = <2>;
+		};
+		fan@3 {
+			reg = <3>;
+		};
+		fan@4 {
+			reg = <4>;
+		};
+	};
+
+	emc2305@4c {
+		compatible = "smsc,emc2305";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x4c>;
+		fan@0 {
+			reg = <0>;
+		};
+		fan@1 {
+			reg = <1>;
+		};
+		fan@2 {
+			reg = <2>;
+		};
+		fan@3 {
+			reg = <3>;
+		};
+		fan@4 {
+			reg = <4>;
+		};
+	};
+
+	at24c512@54 {
+		compatible = "atmel,24c512";
+		reg = <0x54>;
+	};
+
+	/* PPC-Board */
+	pca9698@22 {
+		compatible = "nxp,pca9698";
+		reg = <0x22>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	/* IO-Board */
+	pca9698@20 {
+		compatible = "nxp,pca9698";
+		reg = <0x20>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+};
+
+&IIC2 {
+	fsl,preserve-clocking;
+
+	status = "okay";
+
+	/* MC2/SC-Board */
+	GPIO_VB0: pca9698@20 {
+		compatible = "nxp,pca9698";
+		reg = <0x20>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	/* MC4-Board */
+	GPIO_VB1: pca9698@22 {
+		compatible = "nxp,pca9698";
+		reg = <0x22>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+};
+
+&SPI {
+	gpios = < /*SPI-CSS-FPGA-U-FLASH#*/ &gpio0 8 0
+		  /*SPI-CSS-FPGA-O-FLASH#*/ &gpio0 6 0
+		  /*SPI-CSS-STDP1_U-FLASH#*/ &gpio0 12 0
+		  /*SPI-CSS-STDP2_U-FLASH#*/ &gpio0 11 0
+		  /*SPI-CSS-STDP1_O-FLASH#*/ &gpio0 15 0
+		  /*SPI-CSS-STDP2_O-FLASH#*/ &gpio0 3 0>;
+
+	m25p16@0 {
+		compatible = "st,n25q128a11";
+		reg = <0x0>;
+		spi-max-frequency = <20000000>;
+	};
+
+	m25p16@1 {
+		compatible = "st,n25q128a11";
+		reg = <0x1>;
+		spi-max-frequency = <20000000>;
+	};
+
+	m25p16@2 {
+		compatible = "st,m25p40";
+		reg = <0x2>;
+		spi-max-frequency = <20000000>;
+	};
+
+	m25p16@3 {
+		compatible = "st,m25p40";
+		reg = <0x3>;
+		spi-max-frequency = <20000000>;
+	};
+
+	m25p16@4 {
+		compatible = "st,m25p40";
+		reg = <0x4>;
+		spi-max-frequency = <20000000>;
+	};
+
+	m25p16@5 {
+		compatible = "st,m25p40";
+		reg = <0x5>;
+		spi-max-frequency = <20000000>;
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi b/roms/u-boot/arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi
new file mode 100644
index 000000000..3439737fa
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi
@@ -0,0 +1,250 @@
+#include <dt-bindings/memory/mpc83xx-sdram.h>
+#include <dt-bindings/clk/mpc83xx-clk.h>
+
+/ {
+	aliases {
+		i2c0 = &IIC;
+		i2c1 = &IIC2;
+		i2c2 = "/fpga0bus/fpga0_iic_main";
+		i2c3 = "/fpga0bus/fpga0_iic_video0";
+		i2c4 = "/fpga0bus/fpga0_iic_video1";
+		i2c5 = "/fpga0bus/fpga0_iic_usb";
+		gdsys_soc0 = "/fpga0bus";
+		gdsys_soc1 = "/fpga1bus";
+		ioep0 = "/fpga0bus/fpga0_ep0";
+		ioep1 = "/fpga0bus/fpga1_ep0";
+	};
+
+	chosen {
+		stdout-path = &serial1;
+	};
+
+	cpus {
+		compatible = "cpu_bus";
+		u-boot,dm-pre-reloc;
+
+		PowerPC,8308@0 {
+			compatible = "fsl,mpc8308";
+			clocks = <&socclocks MPC83XX_CLK_CORE
+			          &socclocks MPC83XX_CLK_CSB>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	board {
+		compatible = "gdsys,sysinfo-gazerbeam";
+		csb = <&board_soc>;
+		serdes = <&SERDES>;
+		rxaui0 = <&RXAUI0_0>;
+		rxaui1 = <&RXAUI0_1>;
+		rxaui2 = <&RXAUI0_2>;
+		rxaui3 = <&RXAUI0_3>;
+		rxaui4 = <&RXAUI1_0>;
+		rxaui5 = <&RXAUI1_1>;
+		rxaui6 = <&RXAUI1_2>;
+		rxaui7 = <&RXAUI1_3>;
+		fpga0 = <&FPGA0>;
+		fpga1 = <&FPGA1>;
+		ioep0 = <&IOEP0>;
+		ioep1 = <&IOEP1>;
+
+		ver-gpios = <&PPCPCA 12 0
+			     &PPCPCA 13 0
+			     &PPCPCA 14 0
+			     &PPCPCA 15 0>;
+
+		/* MC2/SC-Board */
+		var-gpios-mc2 = <&GPIO_VB0 0 0    /* VAR-MC_SC */
+				 &GPIO_VB0 11 0>; /* VAR-CON */
+		/* MC4-Board */
+		var-gpios-mc4 = <&GPIO_VB1 0 0    /* VAR-MC_SC */
+				 &GPIO_VB1 11 0>; /* VAR-CON */
+
+		reset-gpios = <&gpio0 1 0 &gpio0 2 1>;
+	};
+
+	socclocks: clocks {
+		compatible = "fsl,mpc8308-clk";
+		#clock-cells = <1>;
+		u-boot,dm-pre-reloc;
+	};
+
+	timer {
+		compatible = "fsl,mpc83xx-timer";
+		clocks = <&socclocks MPC83XX_CLK_CSB>;
+	};
+};
+
+&FPGA0 {
+	reset-gpios = <&PPCPCA 26 0>;
+	done-gpios = <&GPIO_VB0 19 0>;
+};
+
+&FPGA1 {
+	status = "disable";
+};
+
+&FPGA0BUS {
+	ranges = <0x0 0xe0600000 0x00004000>;
+	fpga = <&FPGA0>;
+
+	fpga0_video0 {
+		mode = "640_480_60";
+
+		status = "disabled";
+	};
+
+	RXAUI0_0: fpga0_rxaui@fc0 {
+		compatible = "gdsys,rxaui_ctrl";
+		reg = <0x0fc0 0x10>;
+	};
+
+	fpga0_iic_video0  {
+		status = "disabled";
+	};
+
+	fpga0_axi_video0 {
+		status = "disabled";
+	};
+
+	fpga0_video1 {
+		mode = "640_480_60";
+		status = "disabled";
+	};
+
+	fpga0_iic_video1  {
+		status = "disabled";
+	};
+
+	fpga0_axi_video1 {
+		status = "disabled";
+	};
+
+	IOEP0: fpga0_ep0 {
+	};
+
+	RXAUI0_1: fpga0_rxaui@fd0 {
+		compatible = "gdsys,rxaui_ctrl";
+		reg = <0x0fd0 0x10>;
+	};
+
+	RXAUI0_2: fpga0_rxaui@fe0 {
+		compatible = "gdsys,rxaui_ctrl";
+		reg = <0x0fe0 0x10>;
+	};
+
+	RXAUI0_3: fpga0_rxaui@ff0 {
+		compatible = "gdsys,rxaui_ctrl";
+		reg = <0x0ff0 0x10>;
+	};
+};
+
+&FPGA1BUS {
+	ranges = <0x0 0xe0700000 0x00004000>;
+	fpga = <&FPGA1>;
+
+	status = "disable";
+
+	fpga1_video0 {
+		mode = "640_480_60";
+	};
+
+	RXAUI1_0: fpga0_rxaui@fc0 {
+		compatible = "gdsys,rxaui_ctrl";
+		reg = <0x0fc0 0x10>;
+	};
+
+	fpga1_video1 {
+		mode = "640_480_60";
+	};
+
+	IOEP1: fpga1_ep0 {
+	};
+
+	RXAUI1_1: fpga0_rxaui@fd0 {
+		compatible = "gdsys,rxaui_ctrl";
+		reg = <0x0fd0 0x10>;
+	};
+
+	RXAUI1_2: fpga0_rxaui@fe0 {
+		compatible = "gdsys,rxaui_ctrl";
+		reg = <0x0fe0 0x10>;
+	};
+
+	RXAUI1_3: fpga0_rxaui@ff0 {
+		compatible = "gdsys,rxaui_ctrl";
+		reg = <0x0ff0 0x10>;
+	};
+};
+
+&board_soc {
+	u-boot,dm-pre-reloc;
+	clocks = <&socclocks MPC83XX_CLK_CSB>;
+
+	memory@2000 {
+		u-boot,dm-pre-reloc;
+	};
+
+	sdhc@2e000 {
+		clocks = <&socclocks MPC83XX_CLK_SDHC>;
+		clock-names = "per";
+	};
+
+	SERDES: serdes@e3000 {
+		reg = <0xe3000 0x200>;
+		compatible = "fsl,mpc83xx-serdes";
+		proto = "pex";
+		serdes-clk = <100>;
+		vdd;
+	};
+};
+
+&IIC {
+	clocks = <&socclocks MPC83XX_CLK_I2C1>;
+
+	PPCPCA: pca9698@20 {
+		label = "ppc";
+	};
+
+	IOPCA: pca9698@22 {
+		label = "io";
+	};
+
+	at97sc3205t@29 {
+		u-boot,i2c-offset-len = <0>;
+	};
+};
+
+&IIC2 {
+	clocks = <&socclocks MPC83XX_CLK_I2C2>;
+
+	GPIO_VB0: pca9698@20 {
+		label = "mc2-sc";
+	};
+
+	GPIO_VB1: pca9698@22 {
+		label = "mc4";
+	};
+};
+
+&board_soc {
+	u-boot,dm-pre-reloc;
+};
+
+&GPIO_VB0 {
+	u-boot,dm-pre-reloc;
+};
+
+&serial0 {
+	clocks = <&socclocks MPC83XX_CLK_CSB>;
+	u-boot,dm-pre-reloc;
+};
+
+&serial1 {
+	clocks = <&socclocks MPC83XX_CLK_CSB>;
+	u-boot,dm-pre-reloc;
+};
+
+&pci0 {
+	clocks = <&socclocks MPC83XX_CLK_PCIEXP1>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/gdsys/mpc8308.dtsi b/roms/u-boot/arch/powerpc/dts/gdsys/mpc8308.dtsi
new file mode 100644
index 000000000..1a319e232
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/gdsys/mpc8308.dtsi
@@ -0,0 +1,361 @@
+/*
+ * Basic platform for gdsys mpc8308 based devices
+ *
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * based on mpc8308rdb
+ * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/memory/mpc83xx-sdram.h>
+#include <dt-bindings/clk/mpc83xx-clk.h>
+
+/ {
+	compatible = "fsl,mpc8308rdb";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		serial0 = &serial0;
+		serial1 = &serial1;
+	};
+
+	memory {
+		device_type = "memory";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,8308@0 {
+			device_type = "cpu";
+			reg = <0x0>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <16384>;
+			i-cache-size = <16384>;
+			timebase-frequency = <0>;	// from bootloader
+			bus-frequency = <0>;		// from bootloader
+			clock-frequency = <0>;		// from bootloader
+		};
+	};
+
+	socclocks: clocks {
+		compatible = "fsl,mpc8308-clk";
+		#clock-cells = <1>;
+	};
+
+	board_lbc: localbus@e0005000 {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
+		reg = <0xe0005000 0x1000>;
+		interrupts = <77 0x8>;
+		interrupt-parent = <&ipic>;
+	};
+
+	board_soc: immr@e0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "fsl,mpc8308-immr", "simple-bus";
+		ranges = <0 0xe0000000 0x00100000>;
+		reg = <0xe0000000 0x00000200>;
+		bus-frequency = <0>;
+
+		wdt@200 {
+			device_type = "watchdog";
+			compatible = "mpc83xx_wdt";
+			reg = <0x200 0x100>;
+		};
+
+		memory@2000 {
+			#address-cells = <2>;
+			#size-cells = <1>;
+			compatible = "fsl,mpc83xx-mem-controller";
+			reg = <0x2000 0x1000>;
+			device_type = "memory";
+
+			driver_software_override = <DSO_ENABLE>;
+			p_impedance_override = <DSO_P_IMPEDANCE_NOMINAL>;
+			n_impedance_override = <DSO_N_IMPEDANCE_NOMINAL>;
+			odt_termination_value = <ODT_TERMINATION_150_OHM>;
+			ddr_type = <DDR_TYPE_DDR2_1_8_VOLT>;
+
+			clock_adjust = <CLOCK_ADJUST_05>;
+
+			read_to_write = <0>;
+			write_to_read = <0>;
+			read_to_read = <0>;
+			write_to_write = <0>;
+			active_powerdown_exit = <2>;
+			precharge_powerdown_exit = <6>;
+			odt_powerdown_exit = <8>;
+			mode_reg_set_cycle = <2>;
+
+			precharge_to_activate = <2>;
+			activate_to_precharge = <6>;
+			activate_to_readwrite = <2>;
+			mcas_latency = <CASLAT_40>;
+			refresh_recovery = <17>;
+			last_data_to_precharge = <2>;
+			activate_to_activate = <2>;
+			last_write_data_to_read = <2>;
+
+			additive_latency = <0>;
+			mcas_to_preamble_override = <READ_LAT_PLUS_1_2>;
+			write_latency = <3>;
+			read_to_precharge = <2>;
+			write_cmd_to_write_data = <CLOCK_DELAY_1_2>;
+			minimum_cke_pulse_width = <3>;
+			four_activates_window = <5>;
+
+			self_refresh = <SREN_ENABLE>;
+			sdram_type = <TYPE_DDR2>;
+			databus_width = <DATA_BUS_WIDTH_32>;
+
+			force_self_refresh = <MODE_NORMAL>;
+			dll_reset = <DLL_RESET_ENABLE>;
+			dqs_config = <DQS_TRUE>;
+			odt_config = <ODT_ASSERT_READS>;
+			posted_refreshes = <1>;
+
+			refresh_interval = <2084>;
+			precharge_interval = <256>;
+
+			sdmode = <0x0242>;
+			esdmode = <0x0440>;
+
+			ram@0 {
+				reg = <0x0 0x0 0x8000000>;
+				compatible = "nanya,nt5tu64m16hg";
+
+				odt_rd_cfg = <ODT_RD_NEVER>;
+				odt_wr_cfg = <ODT_WR_ONLY_CURRENT>;
+				bank_bits = <3>;
+				row_bits = <13>;
+				col_bits = <10>;
+			};
+		};
+
+		IIC:i2c@3000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <0>;
+			compatible = "fsl-i2c";
+			reg = <0x3000 0x100>;
+			interrupts = <14 0x8>;
+			interrupt-parent = <&ipic>;
+			dfsrr;
+		};
+
+		IIC2: i2c@3100 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl-i2c";
+			reg = <0x3100 0x100>;
+			interrupts = <15 0x8>;
+			interrupt-parent = <&ipic>;
+			dfsrr;
+			status = "disabled";
+		};
+
+		SPI:spi@7000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <0>;
+			compatible = "fsl,spi";
+			reg = <0x7000 0x1000>;
+			interrupts = <16 0x8>;
+			interrupt-parent = <&ipic>;
+			clocks = <&socclocks MPC83XX_CLK_CSB>;
+			mode = "cpu";
+		};
+
+		sdhc@2e000 {
+			compatible = "fsl,esdhc", "fsl,mpc8308-esdhc";
+			reg = <0x2e000 0x1000>;
+			interrupts = <42 0x8>;
+			interrupt-parent = <&ipic>;
+			sdhci,auto-cmd12;
+			/* Filled in by U-Boot */
+			clock-frequency = <0>;
+		};
+
+		serial0: serial@4500 {
+			cell-index = <0>;
+			device_type = "serial";
+			compatible = "fsl,ns16550", "ns16550";
+			reg = <0x4500 0x100>;
+			clock-frequency = <133333333>;
+			interrupts = <9 0x8>;
+			interrupt-parent = <&ipic>;
+		};
+
+		serial1: serial@4600 {
+			cell-index = <1>;
+			device_type = "serial";
+			compatible = "fsl,ns16550", "ns16550";
+			reg = <0x4600 0x100>;
+			clock-frequency = <133333333>;
+			interrupts = <10 0x8>;
+			interrupt-parent = <&ipic>;
+		};
+
+		gpio0: gpio@c00 {
+			#gpio-cells = <2>;
+			device_type = "gpio";
+			compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
+			reg = <0xc00 0x18>;
+			interrupts = <74 0x8>;
+			interrupt-parent = <&ipic>;
+			gpio-controller;
+		};
+
+		/* IPIC
+		 * interrupts cell = <intr #, sense>
+		 * sense values match linux IORESOURCE_IRQ_* defines:
+		 * sense == 8: Level, low assertion
+		 * sense == 2: Edge, high-to-low change
+		 */
+		ipic: interrupt-controller@700 {
+			compatible = "fsl,ipic";
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			reg = <0x700 0x100>;
+			device_type = "ipic";
+		};
+
+		ipic-msi@7c0 {
+			compatible = "fsl,ipic-msi";
+			reg = <0x7c0 0x40>;
+			msi-available-ranges = <0x0 0x100>;
+			interrupts = < 0x43 0x8
+					0x4  0x8
+					0x51 0x8
+					0x52 0x8
+					0x56 0x8
+					0x57 0x8
+					0x58 0x8
+					0x59 0x8 >;
+			interrupt-parent = < &ipic >;
+		};
+
+		dma@2c000 {
+			compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma";
+			reg = <0x2c000 0x1800>;
+			interrupts = <3 0x8
+					94 0x8>;
+			interrupt-parent = < &ipic >;
+		};
+
+		enet0: ethernet@24000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x24000 0x1000>;
+
+			cell-index = <0>;
+			device_type = "network";
+			model = "eTSEC";
+			compatible = "gianfar", "fsl,tsec";
+			reg = <0x24000 0x1000>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <32 0x8 33 0x8 34 0x8>;
+			interrupt-parent = <&ipic>;
+			tbi-handle = < &tbi0 >;
+			phy-handle = < &phy1 >;
+			fsl,magic-packet;
+
+			mdio@520 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,gianfar-mdio";
+				reg = <0x520 0x20>;
+				phy1: ethernet-phy@1 {
+					reg = <0x1>;
+				};
+				phy2: ethernet-phy@0 {
+					reg = <0x0>;
+					device_type = "ethernet-phy";
+				};
+				tbi0: tbi-phy@11 {
+					reg = <0x11>;
+					device_type = "tbi-phy";
+				};
+			};
+		};
+
+		enet1: ethernet@25000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			cell-index = <1>;
+			device_type = "network";
+			model = "eTSEC";
+			compatible = "gianfar", "fsl,tsec";
+			reg = <0x25000 0x1000>;
+			ranges = <0x0 0x25000 0x1000>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <35 0x8 36 0x8 37 0x8>;
+			interrupt-parent = <&ipic>;
+			phy-handle = < &phy2 >;
+			status = "disabled";
+
+			mdio@520 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,gianfar-tbi";
+				reg = <0x520 0x20>;
+				tbi1: tbi-phy@11 {
+					reg = <0x11>;
+					device_type = "tbi-phy";
+				};
+			};
+		};
+	};
+
+	pci0: pcie@e0009000 {
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		device_type = "pci";
+		compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie";
+		reg = <0xe0009000 0x00001000
+			0xb0000000 0x01000000>;
+		ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
+		          0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
+		bus-range = <0 0>;
+		interrupt-map-mask = <0xf800 0 0 7>;
+		interrupt-map = <0 0 0 1 &ipic 1 8
+				 0 0 0 2 &ipic 1 8
+				 0 0 0 3 &ipic 1 8
+				 0 0 0 4 &ipic 1 8>;
+		interrupts = <0x1 0x8>;
+		interrupt-parent = <&ipic>;
+		clock-frequency = <0>;
+
+		pcie@0 {
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			reg = <0 0 0 0 0>;
+			ranges = <0x02000000 0 0xa0000000
+				  0x02000000 0 0xa0000000
+				  0 0x10000000
+				  0x01000000 0 0x00000000
+				  0x01000000 0 0x00000000
+				  0 0x00800000>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/gdsys/soc/i2c/cirrus-audio-codec.dtsi b/roms/u-boot/arch/powerpc/dts/gdsys/soc/i2c/cirrus-audio-codec.dtsi
new file mode 100644
index 000000000..9787e0964
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/gdsys/soc/i2c/cirrus-audio-codec.dtsi
@@ -0,0 +1,6 @@
+&IIC {
+	cs4265@4f {
+		compatible = "cirrus,cs4265";
+		reg = <0x0000004f>;
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/gdsys/soc/i2c/dallas-rtc.dtsi b/roms/u-boot/arch/powerpc/dts/gdsys/soc/i2c/dallas-rtc.dtsi
new file mode 100644
index 000000000..336bdcaf2
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/gdsys/soc/i2c/dallas-rtc.dtsi
@@ -0,0 +1,6 @@
+&IIC {
+	ds1339@68 {
+		compatible = "dallas,ds1339";
+		reg = <0x68>;
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/gdsys/soc/lbc/gazerbeam.dtsi b/roms/u-boot/arch/powerpc/dts/gdsys/soc/lbc/gazerbeam.dtsi
new file mode 100644
index 000000000..5ff58c28e
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/gdsys/soc/lbc/gazerbeam.dtsi
@@ -0,0 +1,5 @@
+&board_lbc {
+	ranges = <0x0 0x0 0xfe000000 0x00800000
+	          0x1 0x0 0xe0600000 0x00003000
+		  0x2 0x0 0xe0700000 0x00003000>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/gdsys/soc/nor/flash-80k-partition.dtsi b/roms/u-boot/arch/powerpc/dts/gdsys/soc/nor/flash-80k-partition.dtsi
new file mode 100644
index 000000000..c6cc1409e
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/gdsys/soc/nor/flash-80k-partition.dtsi
@@ -0,0 +1,20 @@
+&board_lbc {
+	flash@0,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "cfi-flash";
+		reg = <0x0 0x0 0x100000>;
+		bank-width = <2>;
+		device-width = <1>;
+
+		u-boot@0 {
+			reg = <0x0 0x80000>;
+		};
+		env@80000 {
+			reg = <0x80000 0x10000>;
+		};
+		env1@90000 {
+			reg = <0x90000 0x10000>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/km8309-uboot.dtsi b/roms/u-boot/arch/powerpc/dts/km8309-uboot.dtsi
new file mode 100644
index 000000000..a93bdb2d0
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/km8309-uboot.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Hitachi Power Grids 8309 U-Boot specific Device Tree Source parts
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/ {
+	cpus {
+		u-boot,dm-pre-reloc;
+		PowerPC,8309@0 {
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	chosen {
+		stdout-path = &serial0;
+	};
+};
+
+&qe {
+	compatible = "fsl,qe", "simple-bus";
+};
+
+&soc {
+	u-boot,dm-pre-reloc;
+};
+
+&serial0 {
+	clock-frequency = <132000000>;
+	u-boot,dm-pre-reloc;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/km8321-uboot.dtsi b/roms/u-boot/arch/powerpc/dts/km8321-uboot.dtsi
new file mode 100644
index 000000000..fd11fe63e
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/km8321-uboot.dtsi
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Hitachi Power Grids 8321 U-Boot specific Device Tree Source parts
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/ {
+	cpus {
+		u-boot,dm-pre-reloc;
+		PowerPC,8321@0 {
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	chosen {
+		stdout-path = &serial0;
+	};
+};
+
+&enet_piggy2 {
+	status = "okay";
+};
+
+&qe {
+	compatible = "fsl,qe", "simple-bus";
+};
+
+&serial0 {
+	clock-frequency = <132000000>;
+	u-boot,dm-pre-reloc;
+};
+
+&soc {
+	u-boot,dm-pre-reloc;
+
+	par_io@1400 {
+		compatible = "fsl,mpc8360-par_io";
+		u-boot,dm-pre-reloc;
+
+		serial_pin@0 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@0 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@1 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@3 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@4 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@5 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@6 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@7 {
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/km8321.dtsi b/roms/u-boot/arch/powerpc/dts/km8321.dtsi
new file mode 100644
index 000000000..6c3601756
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/km8321.dtsi
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Hitachi Power Grids km8321 common ports Device Tree Source
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/dts-v1/;
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,8321@0 {
+			device_type = "cpu";
+			reg = <0x0>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <16384>;		// L1, 16K
+			i-cache-size = <16384>;		// L1, 16K
+			timebase-frequency = <66000000>;
+			bus-frequency = <264000000>;
+			clock-frequency = <528000000>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;
+	};
+
+	soc: soc8321@e0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "simple-bus";
+		ranges = <0x0 0xe0000000 0x00100000>;
+		reg = <0xe0000000 0x00000200>;
+		bus-frequency = <264000000>;
+
+		i2c0: i2c@3000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <0>;
+			compatible = "fsl,mpc8313-i2c","fsl-i2c";
+			reg = <0x3000 0x100>;
+			interrupts = <14 0x8>;
+			interrupt-parent = <&ipic>;
+			clock-frequency = <100000>;
+		};
+
+		serial0: serial@4500 {
+			cell-index = <0>;
+			device_type = "serial";
+			compatible = "fsl,ns16550", "ns16550";
+			reg = <0x4500 0x100>;
+			clock-frequency = <264000000>;
+			interrupts = <9 0x8>;
+			interrupt-parent = <&ipic>;
+		};
+
+		dma@82a8 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,mpc8321-dma", "fsl,elo-dma";
+			reg = <0x82a8 4>;
+			ranges = <0 0x8100 0x1a8>;
+			interrupt-parent = <&ipic>;
+			interrupts = <71 8>;
+			cell-index = <0>;
+			dma-channel@0 {
+				compatible = "fsl,mpc8321-dma-channel",
+					     "fsl,elo-dma-channel";
+				reg = <0 0x80>;
+				interrupt-parent = <&ipic>;
+				interrupts = <71 8>;
+			};
+			dma-channel@80 {
+				compatible = "fsl,mpc8321-dma-channel",
+					     "fsl,elo-dma-channel";
+				reg = <0x80 0x80>;
+				interrupt-parent = <&ipic>;
+				interrupts = <71 8>;
+			};
+			dma-channel@100 {
+				compatible = "fsl,mpc8321-dma-channel",
+					     "fsl,elo-dma-channel";
+				reg = <0x100 0x80>;
+				interrupt-parent = <&ipic>;
+				interrupts = <71 8>;
+			};
+			dma-channel@180 {
+				compatible = "fsl,mpc8321-dma-channel",
+					     "fsl,elo-dma-channel";
+				reg = <0x180 0x28>;
+				interrupt-parent = <&ipic>;
+				interrupts = <71 8>;
+			};
+		};
+
+		ipic: pic@700 {
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			compatible = "fsl,pq2pro-pic", "fsl,ipic";
+			interrupt-controller;
+			reg = <0x700 0x100>;
+			device_type = "ipic";
+		};
+
+		par_io: par_io@1400 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x1400 0x100>;
+			ranges;
+			device_type = "par_io";
+			num-ports = <7>;
+
+			qe_pio_d: gpio-controller@48 {
+				#gpio-cells = <2>;
+				compatible = "fsl,mpc8360-qe-pario-bank",
+					     "fsl,mpc8323-qe-pario-bank";
+				reg = <0x1448 0x18>;
+				gpio-controller;
+			};
+		};
+	};
+
+	qe: qe@e0100000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "qe";
+		compatible = "fsl,qe";
+		ranges = <0x0 0xe0100000 0x00100000>;
+		reg = <0xe0100000 0x480>;
+		brg-frequency = <0>;
+		bus-frequency = <396000000>;
+
+		muram@10000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,qe-muram", "fsl,cpm-muram";
+			ranges = <0x0 0x00010000 0x00004000>;
+
+			data-only@0 {
+				compatible = "fsl,qe-muram-data",
+					     "fsl,cpm-muram-data";
+				reg = <0x0 0x4000>;
+			};
+		};
+
+		/* Piggy2 (UCC4, MDIO 0x00, RMII) */
+		enet_piggy2: ucc@3200 {
+			device_type = "network";
+			compatible = "ucc_geth";
+			cell-index = <4>;
+			reg = <0x3200 0x200>;
+			interrupts = <35>;
+			interrupt-parent = <&qeic>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			rx-clock-name = "none";
+			tx-clock-name = "clk17";
+			phy-handle = <&phy_piggy2>;
+			phy-connection-type = "rmii";
+			pio-handle = <&pio_ucc4>;
+		};
+
+		mdio: mdio@3320 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3320 0x18>;
+			compatible = "fsl,ucc-mdio";
+
+			/* Piggy2 (UCC4, MDIO 0x00, RMII) */
+			phy_piggy2: ethernet-phy@00 {
+				reg = <0x0>;
+				device_type = "ethernet-phy";
+			};
+		};
+
+		qeic: interrupt-controller@80 {
+			interrupt-controller;
+			compatible = "fsl,qe-ic";
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			reg = <0x80 0x80>;
+			big-endian;
+			interrupts = <32 8 33 8>;
+			interrupt-parent = <&ipic>;
+		};
+		bootcount@0x13ff8 {
+			device_type = "bootcount";
+			compatible = "u-boot,bootcount";
+			reg = <0x13ff8 0x08>;
+		};
+
+		spi0: spi@4c0 {
+			cell-index = <0>;
+			compatible = "fsl,spi";
+			reg = <0x4c0 0x40>;
+			interrupts = <2>;
+			interrupt-parent = <&qeic>;
+			mode = "qe";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pio-handle = <&pio_spi>;
+		};
+	};
+
+	localbus: localbus@e0005000 {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		compatible = "fsl,mpc8321-localbus", "fsl,pq2pro-localbus",
+			     "simple-bus";
+		reg = <0xe0005000 0xd8>;
+	};
+};
+
+#include "km8321-uboot.dtsi"
diff --git a/roms/u-boot/arch/powerpc/dts/km836x-uboot.dtsi b/roms/u-boot/arch/powerpc/dts/km836x-uboot.dtsi
new file mode 100644
index 000000000..5c78529c4
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/km836x-uboot.dtsi
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Hitachi Power Grids km836x U-Boot specific Device Tree Source parts
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/ {
+	cpus {
+		u-boot,dm-pre-reloc;
+		PowerPC,8360@0 {
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	chosen {
+		stdout-path = &serial0;
+	};
+};
+
+&qe {
+	compatible = "fsl,qe", "simple-bus";
+};
+
+&soc {
+	u-boot,dm-pre-reloc;
+
+	par_io@1400 {
+		u-boot,dm-pre-reloc;
+
+		serial_pin@0 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@0 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@1 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@3 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@4 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@5 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@6 {
+			u-boot,dm-pre-reloc;
+		};
+		ucc_pin@7 {
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
+
+&serial0 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/km836x.dtsi b/roms/u-boot/arch/powerpc/dts/km836x.dtsi
new file mode 100644
index 000000000..94b71cdca
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/km836x.dtsi
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Hitachi Power Grids km836x common ports Device Tree Source
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,8360@0 {
+			device_type = "cpu";
+			reg = <0x0>;
+			d-cache-line-size = <32>;	/* 32 bytes */
+			i-cache-line-size = <32>;	/* 32 bytes */
+			d-cache-size = <32768>;	/* L1, 32K */
+			i-cache-size = <32768>;	/* L1, 32K */
+			timebase-frequency = <0>; /* Filled in by U-Boot */
+			bus-frequency = <0>; /* Filled in by U-Boot */
+			clock-frequency = <0>; /* Filled in by U-Boot */
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0>;		/* Filled in by U-Boot */
+	};
+
+	soc: soc8360@e0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "fsl,mpc8360-immr", "simple-bus";
+		ranges = <0x0 0xe0000000 0x00200000>;
+		reg = <0xe0000000 0x00000200>;
+		bus-frequency = <0>;/* Filled in by U-Boot */
+
+		/* power management control module*/
+		pmc: power@b00 {
+			compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
+			reg = <0xb00 0x100 0xa00 0x100>;
+			interrupts = <80 0x8>;
+			interrupt-parent = <&ipic>;
+		};
+
+		i2c0: i2c@3000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <0>;
+			compatible = "fsl,mpc8313-i2c","fsl-i2c";
+			reg = <0x3000 0x100>;
+			interrupts = <14 0x8>;
+			interrupt-parent = <&ipic>;
+			clock-frequency = <100000>;
+		};
+
+		serial0: serial@4500 {
+			cell-index = <0>;
+			device_type = "serial";
+			compatible = "fsl,ns16550", "ns16550";
+			reg = <0x4500 0x100>;
+			clock-frequency = <264000000>;
+			interrupts = <9 0x8>;
+			interrupt-parent = <&ipic>;
+			status = "disabled";
+		};
+
+		serial1: serial@4600 {
+			cell-index = <1>;
+			device_type = "serial";
+			compatible = "fsl,ns16550", "ns16550";
+			reg = <0x4600 0x100>;
+			clock-frequency = <133333333>;
+			interrupts = <10 0x8>;
+			interrupt-parent = <&ipic>;
+			status = "disabled";
+		};
+
+		ipic: pic@700 {
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			compatible = "fsl,pq2pro-pic", "fsl,ipic";
+			interrupt-controller;
+			reg = <0x700 0x100>;
+		};
+
+		par_io: par_io@1400 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x1400 0x100>;
+			ranges;
+			compatible = "fsl,mpc8360-par_io";
+			device_type = "par_io";
+			num-ports = <7>;
+
+			qe_pio_c: gpio-controller@30 {
+				#gpio-cells = <2>;
+				compatible = "fsl,mpc8360-qe-pario-bank",
+					     "fsl,mpc8323-qe-pario-bank";
+				reg = <0x1430 0x18>;
+				gpio-controller;
+			};
+		};
+
+		qe: qe@100000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,qe";
+			ranges = <0x0 0x100000 0x100000>;
+			reg = <0x100000 0x480>;
+			clock-frequency = <0>;	/* Filled in by U-Boot */
+			brg-frequency = <0>;	/* Filled in by U-Boot */
+			bus-frequency = <0>;	/* Filled in by U-Boot */
+
+			muram@10000 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "fsl,qe-muram", "fsl,cpm-muram";
+				ranges = <0x0 0x00010000 0x0000c000>;
+
+				data-only@0 {
+					compatible = "fsl,qe-muram-data",
+						     "fsl,cpm-muram-data";
+					reg = <0x0 0xc000>;
+				};
+			};
+
+			qeic: interrupt-controller@80 {
+				interrupt-controller;
+				compatible = "fsl,qe-ic";
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+				reg = <0x80 0x80>;
+				big-endian;
+				interrupts = <
+					32 0x8 /* ucc1 */
+					33 0x8 /* ucc2 */
+					34 0x8 /* ucc3 */
+					35 0x8 /* ucc4 */
+					40 0x8 /* ucc1 */
+				>;
+				interrupt-parent = <&ipic>;
+			};
+
+			spi0: spi@4c0 {
+				cell-index = <0>;
+				compatible = "fsl,spi";
+				reg = <0x4c0 0x40>;
+				interrupts = <2>;
+				interrupt-parent = <&qeic>;
+				mode = "qe";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				pio-handle = <&pio_spi>;
+			};
+
+			bootcount@0x1bff8 {
+				device_type = "bootcount";
+				compatible = "u-boot,bootcount";
+				reg = <0x1bff8 0x08>;
+			};
+		};
+	};
+
+	localbus: localbus@e0005000 {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
+			     "simple-bus";
+		reg = <0xe0005000 0xd8>;
+	};
+};
+
+#include "km836x-uboot.dtsi"
diff --git a/roms/u-boot/arch/powerpc/dts/kmcent2-u-boot.dtsi b/roms/u-boot/arch/powerpc/dts/kmcent2-u-boot.dtsi
new file mode 100644
index 000000000..ab76a9f12
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/kmcent2-u-boot.dtsi
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2021  Niel Fourie <lusus@denx.de>
+ */
+
+#include <config.h>
+
+/ {
+
+	aliases {
+		spi0 = "/soc@ffe000000/spi@110000";
+		i2c0 = "/soc@ffe000000/i2c@118000";
+		i2c1 = "/soc@ffe000000/i2c@118000/mux@70/i2c@0";
+		i2c2 = "/soc@ffe000000/i2c@118000/mux@70/i2c@1";
+		i2c3 = "/soc@ffe000000/i2c@118000/mux@70/i2c@7";
+		i2c4 = "/soc@ffe000000/i2c@118100";
+		/delete-property/ pci1;
+		/delete-property/ pci2;
+		/delete-property/ pci3;
+	};
+
+	chosen {
+		stdout-path = "/soc@ffe000000/serial@11c500";
+	};
+
+	soc@ffe000000 {
+		u-boot,dm-pre-reloc;
+		spi@110000 {
+			/* This documents where km_fpgacfg should be appear */
+			fpga@0 {
+				compatible = "keymile,fpga-conf";
+				reg = <0>;
+				spi-max-frequency = <25000000>;
+			};
+		};
+
+		sdhc@114000 {
+			status = "okay";
+		};
+
+		i2c@118000 {
+			u-boot,dm-pre-reloc;
+			mux@70 {
+				i2c@1 { /* IVM bus */
+					reg = <1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+			};
+		};
+
+		serial@11c500 {
+			u-boot,dm-pre-reloc;
+			clock-frequency = <200000000>;
+		};
+
+		fman@400000 {
+			ethernet@e0000 {
+				phy-connection-type = "sgmii";
+			};
+
+			ethernet@e2000 {
+				phy-connection-type = "sgmii";
+			};
+
+			ethernet@e8000 {
+				phy-connection-type = "rgmii-id";
+			};
+		};
+
+	};
+
+	pcie@ffe240000 {
+		compatible = "fsl,pcie-t104x";
+		law_trgt_if = <0>;
+	};
+
+	binman {
+		filename = "u-boot-with-dtb.bin";
+		skip-at-start = <CONFIG_SYS_TEXT_BASE>;
+		sort-by-offset;
+		pad-byte = <0xff>;
+		size = <CONFIG_SYS_MONITOR_LEN>;
+
+		u-boot-with-ucode-ptr {
+			offset = <CONFIG_SYS_TEXT_BASE>;
+			optional-ucode;
+		};
+
+		u-boot-dtb-with-ucode {
+			align = <256>;
+		};
+		powerpc-mpc85xx-bootpg-resetvec {
+			offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/kmcent2.dts b/roms/u-boot/arch/powerpc/dts/kmcent2.dts
new file mode 100644
index 000000000..5d23ecb34
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/kmcent2.dts
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Keymile kmcent2 Device Tree Source, based on T1040RDB DTS
+ *
+ * (C) Copyright 2016
+ * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
+ *
+ * Copyright 2014 - 2015 Freescale Semiconductor Inc.
+ */
+
+/include/ "t104xsi-pre.dtsi"
+
+/ {
+	model = "keymile,kmcent2";
+	compatible = "keymile,kmcent2";
+
+	aliases {
+		front_phy = &front_phy;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		bman_fbpr: bman-fbpr {
+			size = <0 0x1000000>;
+			alignment = <0 0x1000000>;
+		};
+		qman_fqd: qman-fqd {
+			size = <0 0x400000>;
+			alignment = <0 0x400000>;
+		};
+		qman_pfdr: qman-pfdr {
+			size = <0 0x2000000>;
+			alignment = <0 0x2000000>;
+		};
+	};
+
+	ifc: localbus@ffe124000 {
+		reg = <0xf 0xfe124000 0 0x2000>;
+		ranges = <0 0 0xf 0xe8000000 0x04000000
+			  1 0 0xf 0xfa000000 0x00010000
+			  2 0 0xf 0xfb000000 0x00010000
+			  4 0 0xf 0xc0000000 0x08000000
+			  6 0 0xf 0xd0000000 0x08000000
+			  7 0 0xf 0xd8000000 0x08000000>;
+
+		nor@0,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "cfi-flash";
+			reg = <0x0 0x0 0x04000000>;
+			bank-width = <2>;
+			device-width = <2>;
+		};
+
+		nand@1,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,ifc-nand";
+			reg = <0x1 0x0 0x10000>;
+		};
+
+		board-control@2,0 {
+			compatible = "keymile,qriox";
+			reg = <0x2 0x0 0x80>;
+		};
+
+		chassis-mgmt@6,0 {
+			compatible = "keymile,bfticu";
+			reg = <6 0 0x100>;
+			interrupt-controller;
+			interrupt-parent = <&mpic>;
+			interrupts = <11 1 0 0>;
+			#interrupt-cells = <1>;
+		};
+
+	};
+
+	memory {
+		device_type = "memory";
+	};
+
+	dcsr: dcsr@f00000000 {
+		ranges = <0x00000000 0xf 0x00000000 0x01072000>;
+	};
+
+	bportals: bman-portals@ff4000000 {
+		ranges = <0x0 0xf 0xf4000000 0x2000000>;
+	};
+
+	qportals: qman-portals@ff6000000 {
+		ranges = <0x0 0xf 0xf6000000 0x2000000>;
+	};
+
+	soc: soc@ffe000000 {
+		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+		reg = <0xf 0xfe000000 0 0x00001000>;
+
+		spi@110000 {
+			network-clock@1 {
+				compatible = "zarlink,zl30364";
+				reg = <1>;
+				spi-max-frequency = <1000000>;
+			};
+		};
+
+		sdhc@114000 {
+			status = "disabled";
+		};
+
+		i2c@118000 {
+			clock-frequency = <100000>;
+
+			mux@70 {
+				compatible = "nxp,pca9547";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				i2c-mux-idle-disconnect;
+
+				i2c@0 {
+					reg = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					eeprom@54 {
+						compatible = "atmel,24c02";
+						reg = <0x54>;
+						pagesize = <2>;
+						read-only;
+						label = "ddr3-spd";
+					};
+				};
+
+				i2c@7 {
+					reg = <7>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					temp-sensor@48 {
+						compatible = "national,lm75";
+						reg = <0x48>;
+						label = "SENSOR_0";
+					};
+					temp-sensor@4a {
+						compatible = "national,lm75";
+						reg = <0x4a>;
+						label = "SENSOR_2";
+					};
+					temp-sensor@4b {
+						compatible = "national,lm75";
+						reg = <0x4b>;
+						label = "SENSOR_3";
+					};
+				};
+			};
+		};
+
+		i2c@118100 {
+			clock-frequency = <100000>;
+
+			eeprom@50 {
+				compatible = "atmel,24c08";
+				reg = <0x50>;
+				pagesize = <16>;
+			};
+
+			eeprom@54 {
+				compatible = "atmel,24c08";
+				reg = <0x54>;
+				pagesize = <16>;
+			};
+		};
+
+		i2c@119000 {
+			status = "disabled";
+		};
+
+		i2c@119100 {
+			status = "disabled";
+		};
+
+		serial2: serial@11d500 {
+			status = "disabled";
+		};
+
+		serial3: serial@11d600 {
+			status = "disabled";
+		};
+
+		usb0: usb@210000 {
+			status = "disabled";
+		};
+		usb1: usb@211000 {
+			status = "disabled";
+		};
+
+		display@180000 {
+			status = "disabled";
+		};
+
+		sata@220000 {
+			status = "disabled";
+		};
+		sata@221000 {
+			status = "disabled";
+		};
+
+		fman@400000 {
+			ethernet@e0000 {
+				phy-mode = "sgmii";
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+
+			ethernet@e2000 {
+				phy-mode = "sgmii";
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+
+			ethernet@e4000 {
+				status = "disabled";
+			};
+
+			ethernet@e6000 {
+				status = "disabled";
+			};
+
+			ethernet@e8000 {
+				phy-handle = <&front_phy>;
+				phy-mode = "rgmii-id";
+			};
+
+			mdio0: mdio@fc000 {
+				front_phy: ethernet-phy@11 {
+					reg = <0x11>;
+				};
+			};
+		};
+	};
+
+	pci0: pcie@ffe240000 {
+		reg = <0xf 0xfe240000 0 0x10000>;
+		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+		pcie@0 {
+			ranges = <0x02000000 0 0xe0000000
+				  0x02000000 0 0xe0000000
+				  0 0x20000000
+
+				  0x01000000 0 0x00000000
+				  0x01000000 0 0x00000000
+				  0 0x00010000>;
+		};
+	};
+
+	pci1: pcie@ffe250000 {
+		status = "disabled";
+		reg = <0xf 0xfe250000 0 0x10000>;
+		ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000
+			  0x01000000 0 0 0xf 0xf8010000 0 0x00010000>;
+		pcie@0 {
+			ranges = <0x02000000 0 0xe0000000
+				  0x02000000 0 0xe0000000
+				  0 0x10000000
+
+				  0x01000000 0 0x00000000
+				  0x01000000 0 0x00000000
+				  0 0x00010000>;
+		};
+	};
+
+	pci2: pcie@ffe260000 {
+		status = "disabled";
+		reg = <0xf 0xfe260000 0 0x10000>;
+		ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
+			  0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
+		pcie@0 {
+			ranges = <0x02000000 0 0xe0000000
+				  0x02000000 0 0xe0000000
+				  0 0x10000000
+
+				  0x01000000 0 0x00000000
+				  0x01000000 0 0x00000000
+				  0 0x00010000>;
+		};
+	};
+
+	pci3: pcie@ffe270000 {
+		status = "disabled";
+		reg = <0xf 0xfe270000 0 0x10000>;
+		ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
+			  0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
+		pcie@0 {
+			ranges = <0x02000000 0 0xe0000000
+				  0x02000000 0 0xe0000000
+				  0 0x10000000
+
+				  0x01000000 0 0x00000000
+				  0x01000000 0 0x00000000
+				  0 0x00010000>;
+		};
+	};
+
+	qe: qe@ffe140000 {
+		ranges = <0x0 0xf 0xfe140000 0x40000>;
+		reg = <0xf 0xfe140000 0 0x480>;
+		brg-frequency = <0>;
+		bus-frequency = <0>;
+
+		si1: si@700 {
+			compatible = "fsl,t1040-qe-si";
+			reg = <0x700 0x80>;
+		};
+
+		siram1: siram@1000 {
+			compatible = "fsl,t1040-qe-siram";
+			reg = <0x1000 0x800>;
+		};
+
+		ucc_hdlc: ucc@2000 {
+			device_type = "hdlc";
+			compatible = "fsl,ucc-hdlc";
+			rx-clock-name = "clk9";
+			tx-clock-name = "clk9";
+			fsl,hdlc-bus;
+		};
+	};
+};
+
+#include "t1040si-post.dtsi"
diff --git a/roms/u-boot/arch/powerpc/dts/kmcoge5ne-uboot.dtsi b/roms/u-boot/arch/powerpc/dts/kmcoge5ne-uboot.dtsi
new file mode 100644
index 000000000..69392bbab
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/kmcoge5ne-uboot.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Hitachi Power Grids kmcoge5ne U-Boot specific Device Tree Source parts
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/ {
+	aliases {
+		/delete-property/ ethernet1;
+		/delete-property/ ethernet2;
+	};
+};
+
+&enet_switch {
+	status = "disabled";
+};
+
+&enet_mate {
+	status = "disabled";
+};
diff --git a/roms/u-boot/arch/powerpc/dts/kmcoge5ne.dts b/roms/u-boot/arch/powerpc/dts/kmcoge5ne.dts
new file mode 100644
index 000000000..0dad793b6
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/kmcoge5ne.dts
@@ -0,0 +1,320 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Hitachi Power Grids KMCOGE5ne Device Tree Source
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/dts-v1/;
+
+#include "km836x.dtsi"
+
+/ {
+	model = "kmcoge5ne";
+	compatible = "hitachi,kmcoge5ne";
+
+	aliases {
+		ethernet0 = &enet_admin;
+		ethernet1 = &enet_mate;
+		ethernet2 = &enet_switch;
+		serial0 = &serial0;
+	};
+};
+
+&soc {
+	/* brg for hdlc clk */
+	brg@0 {
+		compatible = "fsl,mpc-brg";
+		brg-name = "brg16";
+		brg-frequency = <20000000>; /* 20 MHz */
+		pio-handle =  <&pio_brg>;
+	};
+};
+
+&i2c0 {
+	mux@70 {
+		compatible = "nxp,pca9547";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Inventory EEPROM of the unit itself */
+			ivm@50 {
+				label = "MAIN_CTRL";
+				compatible = "dummy";
+				reg = <0x50>;
+			};
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Inventory EEPROM of the fan unit */
+			fanu-ivm@50 {
+				label = "FANUV";
+				compatible = "dummy";
+				reg = <0x50>;
+			};
+
+			/* fan unit (GPIOs and so on) */
+			fanu@20 {
+				label = "FANUV_CTRL";
+				compatible = "dummy";
+				reg = <0x20>;
+			};
+		};
+
+		i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			backplane@50 {
+				label = "BP_CTRL";
+				compatible = "dummy";
+				reg = <0x50>;
+			};
+		};
+	};
+};
+
+&serial0 {
+	status = "okay";
+};
+
+&par_io {
+	pio_ucc1: ucc_pin@0 { /* RGMII mng-switch */
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			0   1  3  0  2  0	/* MDIO   (PA1,   bi, f2) */
+			0   2  1  0  1  0	/* MDC    (PA2,   in, f1) */
+
+			0   3  1  0  1  0	/* TxD0   (PA3,   in, f1) */
+			0   4  1  0  1  0	/* TxD1   (PA4,   in, f1) */
+			0   5  1  0  1  0	/* TxD2   (PA5,   in, f1) */
+			0   6  1  0  1  0	/* TxD3   (PA6,   in, f1) */
+			0   9  2  0  1  0	/* RxD0   (PA9,  out, f1) */
+			0  10  2  0  1  0	/* RxD1   (PA10, out, f1) */
+			0  11  2  0  1  0	/* RxD2   (PA11, out, f1) */
+			0  12  2  0  1  0	/* RxD3   (PA12, out, f1) */
+			0   7  1  0  1  0	/* TX_EN  (PA7,   in, f1) */
+			0  15  2  0  1  0	/* RX_DV  (PA15, out, f1) */
+			0   0  2  0  1  0	/* RX_CLK (PA0,  out, f1) */
+			2   9  1  0  3  0	/* GTX_CLK        (CLK10) */
+			2   8  2  0  1  0	/* GTX125          (CLK9) */
+		>;
+	};
+
+	pio_ucc4: ucc_pin@3 { /* RMII, admin front port */
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			0   1  3  0  2  0	/* MDIO   (PA1,   bi, f2) */
+			0   2  1  0  1  0	/* MDC    (PA2,   in, f1) */
+
+			1  14  1  0  1  0	/* TxD0   (PB14, out, f1) */
+			1  15  1  0  1  0	/* TxD1   (PB15, out, f1) */
+			1  20  2  0  1  0	/* RxD0   (PB20, in,  f1) */
+			1  21  2  0  1  0	/* RxD1   (PB21, in,  f1) */
+			1  18  1  0  1  0	/* TX_EN  (PB18, out, f1) */
+			1  26  2  0  1  0	/* RX_DV  (PB26, in,  f1) */
+			1  27  2  0  1  0	/* RX_ER  (PB27, in,  f1) */
+
+			2  16  2  0  1  0	/* UCC4_RMII_CLK  (CLK17) */
+		>;
+	};
+
+	pio_ucc5: ucc_pin@4 { /* RMII, mate backplane port */
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			0   1  3  0  2  0	/* MDIO  (PA1,   bi, f2) */
+			0   2  1  0  1  0	/* MDC   (PA2,   in, f1) */
+
+			3   0  1  0  1  0	/* TxD0  (PD0,  out, f1) */
+			3   1  1  0  1  0	/* TxD1  (PD1,  out, f1) */
+			3   6  2  0  1  0	/* RxD0  (PD6,   in, f1) */
+			3   7  2  0  1  0	/* RxD1  (PD7,   in, f1) */
+			3   4  1  0  1  0	/* TX_EN (PD4,  out, f1) */
+			3  12  2  0  1  0	/* RX_DV (PD12,  in, f1) */
+			3  13  2  0  1  0	/* RX_ER (PD13,  in, f1) */
+
+			2  15  2  0  1  0	/* UCCx_RMII_CLK  (CLK16) */
+		>;
+	};
+
+	pio_spi: spi_pin@01 {
+		pio-map = <
+			/* port  pin  dir  open_drain  assignment  has_irq  */
+			4  28  3  0  3  0	/* SPI_MOSI (PE28, out, f3) */
+			4  29  3  0  3  0	/* SPI_MISO (PE29, out, f3) */
+			4  30  3  0  3  0	/* SPI_CLK  (PE30, out, f3) */
+		>;
+	};
+
+	pio_brg: brg_pin@0 {
+		pio-map = <
+			/* port  pin  dir  open_drain  assignment  has_irq  */
+			2  25  1  0  1  0	/* BRG	   (PC25, out, f1) */
+		>;
+	};
+
+	pio_tdm: tdm_pin@00 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			/* TDMa */
+			0  8  3  0  2  0	/* RxD0    (PA8,  bi, f2) */
+			0  13 3  0  2  0	/* TxD0    (PA13, bi, f2) */
+			0  14 2  0  2  0	/* RSync0  (PA14, in, f2) */
+			2  7  2  0  1  0	/* RxClk8  (PC7,  in, f1) */
+			/* TDMb */
+			0  27 3  0  2  0	/* RxD1    (PA27, bi, f2) */
+			0  22 3  0  2  0	/* TxD1    (PA22, bi, f2) */
+			0  28 2  0  2  0	/* RSync1  (PA28, in, f2) */
+			2  1  2  0  1  0	/* RxClk2  (PC1,  in, f1) */
+			/* TDMc */
+			1  5  3  0  2  0	/* RxD2    (PB5,  bi, f2) */
+			1  8  3  0  2  0	/* TxD2    (PB8,  bi, f2) */
+			1  2  2  0  3  0	/* RSync2  (PB2,  in, f3) */
+			2  6  2  0  1  0	/* RxClk7  (PC6,  in, f1) */
+			/* TDMd */
+			1  22 3  0  2  0	/* RxD3    (PB22, bi, f2) */
+			1  19 3  0  1  0	/* TxD3    (PB19, bi, f1) */
+			1  16 2  0  2  0	/* RSync3  (PB16, in, f2) */
+			2  13 2  0  1  0	/* RxClk14 (PC13, in, f1) */
+			/* TDMe */
+			3  8  3  0  2  0	/* RxD4    (PD8,  bi, f2) */
+			3  5  3  0  2  0	/* TxD4    (PD5,  bi, f2) */
+			3  2  2  0  2  0	/* RSync4  (PD2 , in, f2) */
+			2  22 2  0  1  0	/* RxClk23 (PC22, in, f1) */
+			/* TDMf */
+			3  19 3  0  2  0	/* RxD5    (PD19, bi, f2) */
+			3  22 3  0  2  0	/* TxD5    (PD22, bi, f2) */
+			3  16 2  0  1  0	/* RSync5  (PD16, in, f1) */
+			2  17 2  0  1  0	/* RxClk18 (PC17, in, f1) */
+			/* TDMg */
+			4  8  3  0  2  0	/* RxD6    (PE8,  bi, f2) */
+			4  5  3  0  2  0	/* TxD6    (PE5,  bi, f2) */
+			4  2  2  0  1  0	/* RSync6  (PE2,  in, f1) */
+			2  19 2  0  1  0	/* RxClk20 (PC19, in, f1) */
+			/* TDMh */
+			4  19 3  0  2  0	/* RxD7    (PE19, bi, f2) */
+			4  22 3  0  3  0	/* TxD7    (PE22, bi, f3) */
+			4  16 2  0  2  0	/* RSync7  (PE16, in, f2) */
+			2  21 2  0  1  0	/* RxClk22 (PC21, in, f1) */
+			/* RxTxClk0/1 */
+			2  0  2  0  1  0	/* Clk1    (PC0,  in, f1) */
+			2  23 2  0  1  0	/* Clk24   (PC23, in, f1) */
+			/* RxTxSync0/1 */
+			2  10 2  0  1  0	/* Clk11   (PC10, in, f1) */
+			2  20 2  0  1  0>;	/* Clk21   (PC20, in, f1) */
+	};
+};
+
+&qe {
+	/* mng-switch port (UCC1, MDIO 0x10, RGMII) */
+	enet_switch: ethernet@2000 {
+		device_type = "network";
+		compatible = "ucc_geth";
+		cell-index = <1>;
+		reg = <0x2000 0x200>;
+		interrupts = <32>;
+		interrupt-parent = <&qeic>;
+		local-mac-address = [ 00 00 00 00 00 00 ];
+		rx-clock-name = "none";
+		tx-clock-name = "clk9";
+		/*id=0, full-dup, 1G, no-pause, no-asym_p*/
+		fixed-link = <0 1 1000 0 0>;
+		phy-connection-type = "rgmii-id";
+		pio-handle = <&pio_ucc1>;
+	};
+
+	/* admin and debug port (UCC4, MDIO 0x00, RMII) */
+	enet_admin: ucc@3200 {
+		device_type = "network";
+		compatible = "ucc_geth";
+		cell-index = <4>;
+		reg = <0x3200 0x200>;
+		interrupts = <35>;
+		interrupt-parent = <&qeic>;
+		local-mac-address = [ 00 00 00 00 00 00 ];
+		rx-clock-name = "none";
+		tx-clock-name = "clk17";
+		phy-handle = <&phy_admin>;
+		phy-connection-type = "rmii";
+		pio-handle = <&pio_ucc4>;
+	};
+
+	/* mate backplane port (UCC5, MDIO 0x08, RMII) */
+	enet_mate: ucc@2400 {
+		device_type = "network";
+		compatible = "ucc_geth";
+		cell-index = <5>;
+		reg = <0x2400 0x200>;
+		interrupts = <40>;
+		interrupt-parent = <&qeic>;
+		local-mac-address = [ 00 00 00 00 00 00 ];
+		rx-clock-name = "none";
+		tx-clock-name = "clk16";
+		phy-handle = <&phy_mate>;
+		phy-connection-type = "rmii";
+		pio-handle = <&pio_ucc5>;
+	};
+
+	mdio@3320 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x3320 0x18>;
+		compatible = "fsl,ucc-mdio";
+
+		/* admin front port (UCC4, MDIO 0x00, RMII) */
+		phy_admin: ethernet-phy@00 {
+			reg = <0x0>;
+		};
+
+		/* mate bp port (UCC5, MDIO 0x08, RMII) */
+		phy_mate: ethernet-phy@08 {
+			reg = <0x08>;
+		};
+	};
+};
+
+&localbus {
+	ranges = <0 0 0xf0000000 0x04000000
+		   1 0 0xe8000000 0x01000000
+		   3 0 0xa0000000 0x10000000
+		   4 0 0xb0000000 0x10000000>;
+
+	flash@0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0 0x04000000>;
+		nornand = "nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		bank-width = <2>;
+		partition@0 { /* 768KB */
+			label = "u-boot";
+			reg = <0 0xC0000>;
+		};
+		partition@c0000 { /* 128KB */
+			label = "env";
+			reg = <0xC0000 0x20000>;
+		};
+		partition@e0000 { /* 128KB */
+			label = "envred";
+			reg = <0xE0000 0x20000>;
+		};
+		partition@100000 { /* 64512KB */
+			label = "ubi0";
+			reg = <0x100000 0x3F00000>;
+		};
+	};
+};
+
+#include "kmcoge5ne-uboot.dtsi"
diff --git a/roms/u-boot/arch/powerpc/dts/kmeter1-uboot.dtsi b/roms/u-boot/arch/powerpc/dts/kmeter1-uboot.dtsi
new file mode 100644
index 000000000..5f63994aa
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/kmeter1-uboot.dtsi
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Hitachi Power Grids kmeter1 U-Boot specific Device Tree Source parts
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/ {
+	aliases {
+		/delete-property/ ethernet1;
+		/delete-property/ ethernet2;
+		/delete-property/ ethernet3;
+		/delete-property/ ethernet4;
+		/delete-property/ ethernet5;
+		/delete-property/ ethernet6;
+	};
+};
+
+&enet_estar1 {
+	status = "disabled";
+};
+
+&enet_estar2 {
+	status = "disabled";
+};
+
+&enet_eth1 {
+	status = "disabled";
+};
+
+&enet_eth2 {
+	status = "disabled";
+};
+
+&enet_eth3 {
+	status = "disabled";
+};
+
+&enet_eth4 {
+	status = "disabled";
+};
diff --git a/roms/u-boot/arch/powerpc/dts/kmeter1.dts b/roms/u-boot/arch/powerpc/dts/kmeter1.dts
new file mode 100644
index 000000000..a62ee18bb
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/kmeter1.dts
@@ -0,0 +1,480 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Hitachi Power Grids KMETER1 Device Tree Source
+ *
+ * 2008-2011 DENX Software Engineering GmbH
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ */
+
+/dts-v1/;
+
+#include "km836x.dtsi"
+
+/ {
+	model = "KMETER1";
+	compatible = "keymile,KMETER1";
+
+	aliases {
+		ethernet0 = &enet_piggy2;
+		ethernet1 = &enet_estar1;
+		ethernet2 = &enet_estar2;
+		ethernet3 = &enet_eth1;
+		ethernet4 = &enet_eth2;
+		ethernet5 = &enet_eth3;
+		ethernet6 = &enet_eth4;
+		serial0 = &serial0;
+	};
+};
+
+&i2c0 {
+	mux@70 {
+		compatible = "nxp,pca9547";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Inventory EEPROM of the unit itself */
+			ivm@50 {
+				label = "MAIN_CTRL";
+				compatible = "dummy";
+				reg = <0x50>;
+			};
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Temperature sensors */
+			temp@48 {
+				label = "Top";
+				compatible = "national,lm75";
+				reg = <0x48>;
+			};
+
+			temp@49 {
+				label = "Control";
+				compatible = "national,lm75";
+				reg = <0x49>;
+			};
+
+			temp@4a {
+				label = "Power";
+				compatible = "national,lm75";
+				reg = <0x4a>;
+			};
+
+			temp@4b {
+				label = "Front";
+				compatible = "national,lm75";
+				reg = <0x4b>;
+			};
+		};
+	};
+};
+
+&serial0 {
+	status = "okay";
+};
+
+&par_io {
+	pio_ucc1: ucc_pin@0 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			0   1  3  0  2  0	/* MDIO   */
+			0   2  1  0  1  0	/* MDC    */
+
+			0   3  1  0  1  0	/* TxD0   */
+			0   4  1  0  1  0	/* TxD1   */
+			0   5  1  0  1  0	/* TxD2   */
+			0   6  1  0  1  0	/* TxD3   */
+			0   9  2  0  1  0	/* RxD0   */
+			0  10  2  0  1  0	/* RxD1   */
+			0  11  2  0  1  0	/* RxD2   */
+			0  12  2  0  1  0	/* RxD3   */
+			0   7  1  0  1  0	/* TX_EN  */
+			0   8  1  0  1  0	/* TX_ER  */
+			0  15  2  0  1  0	/* RX_DV  */
+			0  16  2  0  1  0	/* RX_ER  */
+			0   0  2  0  1  0	/* RX_CLK */
+			2   9  1  0  3  0	/* GTX_CLK - CLK10 */
+			2   8  2  0  1  0	/* GTX125  - CLK9  */
+		>;
+	};
+
+	pio_ucc2: ucc_pin@1 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			0   1  3  0  2  0	/* MDIO   */
+			0   2  1  0  1  0	/* MDC    */
+
+			0  17  1  0  1  0	/* TxD0   */
+			0  18  1  0  1  0	/* TxD1   */
+			0  19  1  0  1  0	/* TxD2   */
+			0  20  1  0  1  0	/* TxD3   */
+			0  23  2  0  1  0	/* RxD0   */
+			0  24  2  0  1  0	/* RxD1   */
+			0  25  2  0  1  0	/* RxD2   */
+			0  26  2  0  1  0	/* RxD3   */
+			0  21  1  0  1  0	/* TX_EN  */
+			0  22  1  0  1  0	/* TX_ER  */
+			0  29  2  0  1  0	/* RX_DV  */
+			0  30  2  0  1  0	/* RX_ER  */
+			0  31  2  0  1  0	/* RX_CLK */
+			2  2   1  0  2  0	/* GTX_CLK - CLK3  */
+			2  3   2  0  1  0	/* GTX125  - CLK4  */
+		>;
+	};
+
+	pio_ucc4: ucc_pin@3 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			0   1  3  0  2  0	/* MDIO */
+			0   2  1  0  1  0	/* MDC  */
+
+			1  14  1  0  1  0	/* TxD0   (PB14, out, f1) */
+			1  15  1  0  1  0	/* TxD1   (PB15, out, f1) */
+			1  20  2  0  1  0	/* RxD0   (PB20, in,  f1) */
+			1  21  2  0  1  0	/* RxD1   (PB21, in,  f1) */
+			1  18  1  0  1  0	/* TX_EN  (PB18, out, f1) */
+			1  26  2  0  1  0	/* RX_DV  (PB26, in,  f1) */
+			1  27  2  0  1  0	/* RX_ER  (PB27, in,  f1) */
+
+			2  16  2  0  1  0	/* UCC4_RMII_CLK (CLK17) */
+		>;
+	};
+
+	pio_ucc5: ucc_pin@4 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			0   1  3  0  2  0	/* MDIO */
+			0   2  1  0  1  0	/* MDC  */
+
+			3   0  1  0  1  0	/* TxD0  (PD0,  out, f1) */
+			3   1  1  0  1  0	/* TxD1  (PD1,  out, f1) */
+			3   6  2  0  1  0	/* RxD0  (PD6,   in, f1) */
+			3   7  2  0  1  0	/* RxD1  (PD7,   in, f1) */
+			3   4  1  0  1  0	/* TX_EN (PD4,  out, f1) */
+			3  12  2  0  1  0	/* RX_DV (PD12,  in, f1) */
+			3  13  2  0  1  0	/* RX_ER (PD13,  in, f1) */
+		>;
+	};
+
+	pio_ucc6: ucc_pin@5 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			0   1  3  0  2  0	/* MDIO */
+			0   2  1  0  1  0	/* MDC  */
+
+			3  14  1  0  1  0	/* TxD0   (PD14, out, f1) */
+			3  15  1  0  1  0	/* TxD1   (PD15, out, f1) */
+			3  20  2  0  1  0	/* RxD0   (PD20, in,  f1) */
+			3  21  2  0  1  0	/* RxD1   (PD21, in,  f1) */
+			3  18  1  0  1  0	/* TX_EN  (PD18, out, f1) */
+			3  26  2  0  1  0	/* RX_DV  (PD26, in,  f1) */
+			3  27  2  0  1  0	/* RX_ER  (PD27, in,  f1) */
+		>;
+	};
+
+	pio_ucc7: ucc_pin@6 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			0   1  3  0  2  0	/* MDIO */
+			0   2  1  0  1  0	/* MDC  */
+
+			4   0  1  0  1  0	/* TxD0   (PE0,  out, f1) */
+			4   1  1  0  1  0	/* TxD1   (PE1,  out, f1) */
+			4   6  2  0  1  0	/* RxD0   (PE6,   in, f1) */
+			4   7  2  0  1  0	/* RxD1   (PE7,   in, f1) */
+			4   4  1  0  1  0	/* TX_EN  (PE4,  out, f1) */
+			4  12  2  0  1  0	/* RX_DV  (PE12,  in, f1) */
+			4  13  2  0  1  0	/* RX_ER  (PE13,  in, f1) */
+		>;
+	};
+
+	pio_ucc8: ucc_pin@7 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			0   1  3  0  2  0	/* MDIO */
+			0   2  1  0  1  0	/* MDC  */
+
+			4  14  1  0  2  0	/* TxD0   (PE14, out, f2) */
+			4  15  1  0  1  0	/* TxD1   (PE15, out, f1) */
+			4  20  2  0  1  0	/* RxD0   (PE20, in,  f1) */
+			4  21  2  0  1  0	/* RxD1   (PE21, in,  f1) */
+			4  18  1  0  1  0	/* TX_EN  (PE18, out, f1) */
+			4  26  2  0  1  0	/* RX_DV  (PE26, in,  f1) */
+			4  27  2  0  1  0	/* RX_ER  (PE27, in,  f1) */
+
+			2  15  2  0  1  0	/* UCCx_RMII_CLK (CLK16) */
+		>;
+	};
+
+	pio_spi: spi_pin@01 {
+		pio-map = <
+			/* port  pin  dir  open_drain  assignment  has_irq  */
+			4  28  3  0  3  0	/* SPI_MOSI (PE28, out, f3  */
+			4  30  3  0  3  0	/* SPI_CLK  (PE30, out, f3  */
+		>;
+	};
+
+	/* UCC3 as HDLC controller for ICN */
+	pio5: ucc_pin@02 {
+		pio-map = <
+			/* port  pin  dir  open_drain  assignment  has_irq */
+			1   0  1  0  1  0   /* TxD0 */
+			1   6  2  0  1  0   /* RxD0 */
+			1  12  2  0  1  0   /* CTS */
+			2  11  2  0  1  0   /* TX-CLK12 */
+		>;
+	};
+
+	pio_tdm: tdm_pin@00 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			/* TDMa */
+			0  8  3  0  2  0	/* RxD0    (PA8,  bi, f2) */
+			0  13 3  0  2  0	/* TxD0    (PA13, bi, f2) */
+			0  14 2  0  2  0	/* RSync0  (PA14, in, f2) */
+			2  7  2  0  1  0	/* RxClk8  (PC7,  in, f1) */
+			/* TDMb */
+			0  27 3  0  2  0	/* RxD1    (PA27, bi, f2) */
+			0  22 3  0  2  0	/* TxD1    (PA22, bi, f2) */
+			0  28 2  0  2  0	/* RSync1  (PA28, in, f2) */
+			2  1  2  0  1  0	/* RxClk2  (PC1,  in, f1) */
+			/* TDMc */
+			1  5  3  0  2  0	/* RxD2    (PB5,  bi, f2) */
+			1  8  3  0  2  0	/* TxD2    (PB8,  bi, f2) */
+			1  2  2  0  3  0	/* RSync2  (PB2,  in, f3) */
+			2  6  2  0  1  0	/* RxClk7  (PC6,  in, f1) */
+			/* TDMd */
+			1  22 3  0  2  0	/* RxD3    (PB22, bi, f2) */
+			1  19 3  0  1  0	/* TxD3    (PB19, bi, f1) */
+			1  16 2  0  2  0	/* RSync3  (PB16, in, f2) */
+			2  13 2  0  1  0	/* RxClk14 (PC13, in, f1) */
+			/* TDMe */
+			3  8  3  0  2  0	/* RxD4    (PD8,  bi, f2) */
+			3  5  3  0  2  0	/* TxD4    (PD5,  bi, f2) */
+			3  2  2  0  2  0	/* RSync4  (PD2 , in, f2) */
+			2  22 2  0  1  0	/* RxClk23 (PC22, in, f1) */
+			/* TDMf */
+			3  19 3  0  2  0	/* RxD5    (PD19, bi, f2) */
+			3  22 3  0  2  0	/* TxD5    (PD22, bi, f2) */
+			3  16 2  0  1  0	/* RSync5  (PD16, in, f1) */
+			2  17 2  0  1  0	/* RxClk18 (PC17, in, f1) */
+			/* TDMg */
+			4  8  3  0  2  0	/* RxD6    (PE8,  bi, f2) */
+			4  5  3  0  2  0	/* TxD6    (PE5,  bi, f2) */
+			4  2  2  0  1  0	/* RSync6  (PE2,  in, f1) */
+			2  19 2  0  1  0	/* RxClk20 (PC19, in, f1) */
+			/* TDMh */
+			4  19 3  0  2  0	/* RxD7    (PE19, bi, f2) */
+			4  22 3  0  3  0	/* TxD7    (PE22, bi, f3) */
+			4  16 2  0  2  0	/* RSync7  (PE16, in, f2) */
+			2  21 2  0  1  0	/* RxClk22 (PC21, in, f1) */
+			/* RxTxClk0/1 */
+			2  0  2  0  1  0	/* Clk1    (PC0,  in, f1) */
+			2  23 2  0  1  0	/* Clk24   (PC23, in, f1) */
+			/* RxTxSync0/1 */
+			2  10 2  0  1  0	/* Clk11   (PC10, in, f1) */
+			2  20 2  0  1  0>;	/* Clk21   (PC20, in, f1) */
+	};
+};
+
+&qe {
+	/* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
+	enet_estar1: ucc@2000 {
+		device_type = "network";
+		compatible = "ucc_geth";
+		cell-index = <1>;
+		reg = <0x2000 0x200>;
+		interrupts = <32>;
+		interrupt-parent = <&qeic>;
+		local-mac-address = [ 00 00 00 00 00 00 ];
+		rx-clock-name = "none";
+		tx-clock-name = "clk9";
+		phy-handle = <&phy_estar1>;
+		phy-connection-type = "rgmii-id";
+		pio-handle = <&pio_ucc1>;
+	};
+
+	/* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
+	enet_estar2: ucc@3000 {
+		device_type = "network";
+		compatible = "ucc_geth";
+		cell-index = <2>;
+		reg = <0x3000 0x200>;
+		interrupts = <33>;
+		interrupt-parent = <&qeic>;
+		local-mac-address = [ 00 00 00 00 00 00 ];
+		rx-clock-name = "none";
+		tx-clock-name = "clk4";
+		phy-handle = <&phy_estar2>;
+		phy-connection-type = "rgmii-id";
+		pio-handle = <&pio_ucc2>;
+	};
+
+	/* Piggy2 (UCC4, MDIO 0x00, RMII) */
+	enet_piggy2: ucc@3200 {
+		device_type = "network";
+		compatible = "ucc_geth";
+		cell-index = <4>;
+		reg = <0x3200 0x200>;
+		interrupts = <35>;
+		interrupt-parent = <&qeic>;
+		local-mac-address = [ 00 00 00 00 00 00 ];
+		rx-clock-name = "none";
+		tx-clock-name = "clk17";
+		phy-handle = <&phy_piggy2>;
+		phy-connection-type = "rmii";
+		pio-handle = <&pio_ucc4>;
+	};
+
+	/* Eth-1 (UCC5, MDIO 0x08, RMII) */
+	enet_eth1: ucc@2400 {
+		device_type = "network";
+		compatible = "ucc_geth";
+		cell-index = <5>;
+		reg = <0x2400 0x200>;
+		interrupts = <40>;
+		interrupt-parent = <&qeic>;
+		local-mac-address = [ 00 00 00 00 00 00 ];
+		rx-clock-name = "none";
+		tx-clock-name = "clk16";
+		phy-handle = <&phy_eth1>;
+		phy-connection-type = "rmii";
+		pio-handle = <&pio_ucc5>;
+	};
+
+	/* Eth-2 (UCC6, MDIO 0x09, RMII) */
+	enet_eth2: ucc@3400 {
+		device_type = "network";
+		compatible = "ucc_geth";
+		cell-index = <6>;
+		reg = <0x3400 0x200>;
+		interrupts = <41>;
+		interrupt-parent = <&qeic>;
+		local-mac-address = [ 00 00 00 00 00 00 ];
+		rx-clock-name = "none";
+		tx-clock-name = "clk16";
+		phy-handle = <&phy_eth2>;
+		phy-connection-type = "rmii";
+		pio-handle = <&pio_ucc6>;
+	};
+
+	/* Eth-3 (UCC7, MDIO 0x0a, RMII) */
+	enet_eth3: ucc@2600 {
+		device_type = "network";
+		compatible = "ucc_geth";
+		cell-index = <7>;
+		reg = <0x2600 0x200>;
+		interrupts = <42>;
+		interrupt-parent = <&qeic>;
+		local-mac-address = [ 00 00 00 00 00 00 ];
+		rx-clock-name = "none";
+		tx-clock-name = "clk16";
+		phy-handle = <&phy_eth3>;
+		phy-connection-type = "rmii";
+		pio-handle = <&pio_ucc7>;
+	};
+
+	/* Eth-4 (UCC8, MDIO 0x0b, RMII) */
+	enet_eth4: ucc@3600 {
+		device_type = "network";
+		compatible = "ucc_geth";
+		cell-index = <8>;
+		reg = <0x3600 0x200>;
+		interrupts = <43>;
+		interrupt-parent = <&qeic>;
+		local-mac-address = [ 00 00 00 00 00 00 ];
+		rx-clock-name = "none";
+		tx-clock-name = "clk16";
+		phy-handle = <&phy_eth4>;
+		phy-connection-type = "rmii";
+		pio-handle = <&pio_ucc8>;
+	};
+
+	mdio@3320 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x3320 0x18>;
+		compatible = "fsl,ucc-mdio";
+
+		/* Piggy2 (UCC4, MDIO 0x00, RMII) */
+		phy_piggy2: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+
+		/* Eth-1 (UCC5, MDIO 0x08, RMII) */
+		phy_eth1: ethernet-phy@8 {
+			reg = <0x08>;
+		};
+
+		/* Eth-2 (UCC6, MDIO 0x09, RMII) */
+		phy_eth2: ethernet-phy@9 {
+			reg = <0x09>;
+		};
+
+		/* Eth-3 (UCC7, MDIO 0x0a, RMII) */
+		phy_eth3: ethernet-phy@a {
+			reg = <0x0a>;
+		};
+
+		/* Eth-4 (UCC8, MDIO 0x0b, RMII) */
+		phy_eth4: ethernet-phy@b {
+			reg = <0x0b>;
+		};
+
+		/* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
+		phy_estar1: ethernet-phy@10 {
+			interrupt-parent = <&ipic>;
+			interrupts = <17 0x8>;
+			reg = <0x10>;
+		};
+
+		/* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
+		phy_estar2: ethernet-phy@11 {
+			interrupt-parent = <&ipic>;
+			interrupts = <18 0x8>;
+			reg = <0x11>;
+		};
+	};
+};
+
+&localbus {
+	ranges = <0 0 0xf0000000 0x04000000	/* LB 0 */
+		  1 0 0xe8000000 0x01000000	/* LB 1 */
+		  3 0 0xa0000000 0x10000000>;	/* LB 3 */
+
+	flash@0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0 0x04000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		bank-width = <2>;
+		partition@0 { /* 768KB */
+			label = "u-boot";
+			reg = <0 0xC0000>;
+		};
+		partition@c0000 { /* 128KB */
+			label = "env";
+			reg = <0xC0000 0x20000>;
+		};
+		partition@e0000 { /* 128KB */
+			label = "envred";
+			reg = <0xE0000 0x20000>;
+		};
+		partition@100000 { /* 64512KB */
+			label = "ubi0";
+			reg = <0x100000 0x3F00000>;
+		};
+	};
+};
+
+#include "kmeter1-uboot.dtsi"
diff --git a/roms/u-boot/arch/powerpc/dts/kmopti2.dts b/roms/u-boot/arch/powerpc/dts/kmopti2.dts
new file mode 100644
index 000000000..b2d9f0fa7
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/kmopti2.dts
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Hitachi Power Grids OPTI2 Device Tree Source
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/dts-v1/;
+
+#include "km8321.dtsi"
+
+/ {
+	model = "KMOPTI2";
+	compatible = "hitachi,kmpbec8321";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		ethernet0 = &enet_piggy2;
+		serial0 = &serial0;
+	};
+};
+
+&i2c0 {
+	mux@70 {
+		compatible = "nxp,pca9547";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Inventory EEPROM of the unit itself */
+			ivm@50 {
+				label = "MAIN_CTRL";
+				compatible = "dummy";
+				reg = <0x50>;
+			};
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Temperature sensors */
+			temp@49 {
+				label = "board";
+				compatible = "national,lm75";
+				reg = <0x49>;
+			};
+
+			temp@4a {
+				label = "power";
+				compatible = "national,lm75";
+				reg = <0x4a>;
+			};
+		};
+
+		i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+&par_io {
+	/* UCC5 as HDLC controller for ICN */
+	pio_ucc5: ucc_pin@04 {
+		pio-map = <
+			/* port  pin  dir  open_drain  assignment  has_irq */
+			2   0  1  0  2  0 /* TxD0 */
+			2   8  2  0  2  0 /* RxD0 */
+			2  29  2  0  2  0 /* CTS */
+			3  30  2  0  1  0 /* ICN CLK */
+			>;
+	};
+
+	/* UCC4 Piggy Ethernet */
+	pio_ucc4: ucc_pin@03 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			3   4  3  0  2  0 /* MDIO */
+			3   5  1  0  2  0 /* MDC  */
+
+			1 18  1  0  1  0 /* TxD0 */
+			1 19  1  0  1  0 /* TxD1 */
+			1 22  2  0  1  0 /* RxD0 */
+			1 23  2  0  1  0 /* RxD1 */
+			1 26  2  0  1  0 /* RX_ER */
+			1 28  2  0  1  0 /* RX_DV */
+			1 30  1  0  1  0 /* TX_EN */
+			1 31  2  0  1  0 /* CRS */
+			3 10  2  0  3  0 /* UCC4_RMII_CLK (CLK17) */
+		>;
+	};
+
+	pio_spi: spi_pin@01 {
+		pio-map = <
+			/* port  pin  dir  open_drain  assignment  has_irq  */
+			3  0  3  0  1  0 /* SPI_MOSI (PD0, bi, f3)  */
+			3  1  3	 0  1  0 /* SPI_MISO (PD1, bi, f3)  */
+			3  2  3  0  1  0 /* SPI_CLK  (PD2, bi, f3)  */
+		>;
+	};
+};
+
+&localbus {
+	ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
+		1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
+		2 0 0xa0000000 0x10000000 /* LB 2 PAXE */
+		3 0 0xb0000000 0x10000000>; /* LB 3 OPI2 */
+
+	flash@0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0x00000000 0x04000000>;
+		bank-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		use-advanced-sector-protection;
+		partition@0 { /* 768KB */
+			label = "u-boot";
+			reg = <0 0xC0000>;
+		};
+		partition@c0000 { /* 128KB */
+			label = "env";
+			reg = <0xc0000 0x20000>;
+		};
+		partition@e0000 { /* 128KB */
+			label = "envred";
+			reg = <0xe0000 0x20000>;
+		};
+		partition@100000 { /* 64512KB */
+			label = "ubi0";
+			reg = <0x100000 0x3F00000>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/kmsupc5.dts b/roms/u-boot/arch/powerpc/dts/kmsupc5.dts
new file mode 100644
index 000000000..9736c1840
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/kmsupc5.dts
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Hitachi Power Grids SUPC5 Device Tree Source
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/dts-v1/;
+
+#include "km8321.dtsi"
+
+/ {
+	model = "SUPC5";
+	compatible = "hitachi,kmpbec8321";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		ethernet0 = &enet_piggy2;
+		serial0 = &serial0;
+	};
+};
+
+&i2c0 {
+	mux@70 {
+		compatible = "nxp,pca9547";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Inventory EEPROM of the unit itself */
+			ivm@50 {
+				label = "MAIN_CTRL";
+				compatible = "dummy";
+				reg = <0x50>;
+			};
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Temperature sensors */
+			temp@49 {
+				label = "board";
+				compatible = "national,lm75";
+				reg = <0x49>;
+			};
+		};
+	};
+};
+
+&par_io {
+	/* UCC5 as HDLC controller for ICN */
+	pio_ucc5: ucc_pin@04 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			2   0  1  0  2  0	/* TxD0 */
+			2   8  2  0  2  0	/* RxD0 */
+			2  29  2  0  2  0	/* CTS */
+			3  30  2  0  1  0	/* ICN CLK */
+			>;
+	};
+
+	/* UCC4 Piggy Ethernet */
+	pio_ucc4: ucc_pin@03 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			3   4  3  0  2  0	/* MDIO */
+			3   5  1  0  2  0	/* MDC  */
+
+			1 18  1  0  1  0	/* TxD0 */
+			1 19  1  0  1  0	/* TxD1 */
+			1 22  2  0  1  0	/* RxD0 */
+			1 23  2  0  1  0	/* RxD1 */
+			1 26  2  0  1  0	/* RX_ER */
+			1 28  2  0  1  0	/* RX_DV */
+			1 30  1  0  1  0	/* TX_EN */
+			1 31  2  0  1  0	/* CRS */
+			/* UCC4_RMII_CLK (CLK17) */
+			3 10  2  0  3  0
+		>;
+	};
+
+	pio_spi: spi_pin@01 {
+		pio-map = <
+			/*
+			 * port  pin  dir  open_drain  assignment  has_irq
+			 * SPI_MOSI (PD0, bi, f3)
+			 */
+			3  0  3  0  1  0
+			/* SPI_MISO (PD1, bi, f3) */
+			3  1  3  0  1  0
+			/* SPI_CLK  (PD2, bi, f3) */
+			3  2  3  0  1  0
+		>;
+	};
+};
+
+&spi0 {
+	pio-handle = <&pio_spi>;
+};
+
+&localbus {
+	ranges = <0 0 0xf0000000 0x04000000     /* LB 0 Flash (boot) */
+		  1 0 0xe8000000 0x01000000     /* LB 1 PRIO1 and Piggy */
+		  2 0 0xa0000000 0x10000000>;   /* LB 2 LPXF */
+
+	flash@0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0x00000000 0x04000000>;
+		bank-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		partition@0 { /* 768KB */
+			label = "u-boot";
+			reg = <0 0xC0000>;
+		};
+		partition@c0000 { /* 128KB */
+			label = "env";
+			reg = <0xc0000 0x20000>;
+		};
+		partition@e0000 { /* 128KB */
+			label = "envred";
+			reg = <0xe0000 0x20000>;
+		};
+		partition@100000 { /* 64512KB */
+			label = "ubi0";
+			reg = <0x100000 0x3F00000>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/kmsupm5.dts b/roms/u-boot/arch/powerpc/dts/kmsupm5.dts
new file mode 100644
index 000000000..0687b4dea
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/kmsupm5.dts
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Hitachi Power Grids SUPM5 Device Tree Source
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/dts-v1/;
+
+#include "km8321.dtsi"
+
+/ {
+	model = "SUPM5";
+	compatible = "hitachi,kmpbec8321";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		ethernet0 = &enet_piggy2;
+		serial0 = &serial0;
+	};
+};
+
+&i2c0 {
+	mux@70 {
+		compatible = "nxp,pca9547";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Inventory EEPROM of the unit itself */
+			ivm@50 {
+				label = "MAIN_CTRL";
+				compatible = "dummy";
+				reg = <0x50>;
+			};
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Temperature sensors */
+			temp@49 {
+				label = "board";
+				compatible = "national,lm75";
+				reg = <0x49>;
+			};
+		};
+	};
+};
+
+&par_io {
+	/* UCC5 as HDLC controller for ICN */
+	pio_ucc5: ucc_pin@04 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			2   0  1  0  2  0	/* TxD0 */
+			2   8  2  0  2  0	/* RxD0 */
+			2  29  2  0  2  0	/* CTS */
+			3  30  2  0  1  0	/* ICN CLK */
+			>;
+	};
+
+	/* UCC4 Piggy Ethernet */
+	pio_ucc4: ucc_pin@03 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			3   4  3  0  2  0	/* MDIO */
+			3   5  1  0  2  0	/* MDC  */
+
+			1 18  1  0  1  0	/* TxD0 */
+			1 19  1  0  1  0	/* TxD1 */
+			1 22  2  0  1  0	/* RxD0 */
+			1 23  2  0  1  0	/* RxD1 */
+			1 26  2  0  1  0	/* RX_ER */
+			1 28  2  0  1  0	/* RX_DV */
+			1 30  1  0  1  0	/* TX_EN */
+			1 31  2  0  1  0	/* CRS */
+			3 10  2  0  3  0 /* UCC4_RMII_CLK (CLK17) */
+		>;
+	};
+
+	pio_spi: spi_pin@01 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			3  0  3  0  1  0 /* SPI_MOSI (PD0, bi, f3)  */
+			3  1  3  0  1  0 /* SPI_MISO (PD1, bi, f3)  */
+			3  2  3  0  1  0 /* SPI_CLK  (PD2, bi, f3)  */
+		>;
+	};
+};
+
+&localbus {
+	ranges = <0 0 0xf0000000 0x04000000     /* LB 0 Flash (boot) */
+		  1 0 0xe8000000 0x01000000     /* LB 1 PRIO1 and Piggy */
+		  2 0 0xa0000000 0x10000000>;   /* LB 2 LPXF */
+
+	flash@0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0x00000000 0x04000000>;
+		bank-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		partition@0 { /* 768KB */
+			label = "u-boot";
+			reg = <0 0xC0000>;
+		};
+		partition@c0000 { /* 128KB */
+			label = "env";
+			reg = <0xc0000 0x20000>;
+		};
+		partition@e0000 { /* 128KB */
+			label = "envred";
+			reg = <0xe0000 0x20000>;
+		};
+		partition@100000 { /* 64512KB */
+			label = "ubi0";
+			reg = <0x100000 0x3F00000>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/kmtegr1.dts b/roms/u-boot/arch/powerpc/dts/kmtegr1.dts
new file mode 100644
index 000000000..d40d9716e
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/kmtegr1.dts
@@ -0,0 +1,392 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Hitachi Power Grids TEGR1 Device Tree Source
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/dts-v1/;
+
+/ {
+	model = "KMTEGR1";
+	compatible = "hitachi,kmpbec8309";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		ethernet0 = &enet_zynq;
+		ethernet1 = &enet_piggy2;
+		serial0 = &serial0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,8309@0 {
+			device_type = "cpu";
+			reg = <0x0>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <16384>;		// L1, 16K
+			i-cache-size = <16384>;		// L1, 16K
+			timebase-frequency = <66000000>;
+			bus-frequency = <264000000>;
+			clock-frequency = <264000000>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;
+	};
+
+	soc: soc8309@e0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "simple-bus";
+		ranges = <0x0 0xe0000000 0x00100000>;
+		reg = <0xe0000000 0x00000200>;
+		bus-frequency = <264000000>;
+
+		i2c@3000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <0>;
+			compatible = "fsl,mpc8313-i2c","fsl-i2c";
+			reg = <0x3000 0x100>;
+			interrupts = <14 0x8>;
+			interrupt-parent = <&ipic>;
+			clock-frequency = <400000>;
+
+			mux@70 {
+				compatible = "nxp,pca9547";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				i2c@1 {
+					reg = <1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					/*
+					 * Inventory EEPROM of the
+					 * unit itself
+					 */
+					ivm@50 {
+						label = "MAIN_CTRL";
+						compatible = "dummy";
+						reg = <0x50>;
+					};
+				};
+
+				i2c@2 {
+					reg = <2>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					/* Temperature sensors */
+					temp@48 {
+						label = "front";
+						compatible = "national,lm75";
+						reg = <0x48>;
+					};
+
+					temp@49 {
+						label = "board";
+						compatible = "national,lm75";
+						reg = <0x49>;
+					};
+
+					temp@4a {
+						label = "power";
+						compatible = "national,lm75";
+						reg = <0x4a>;
+					};
+
+					temp@4b {
+						label = "bottom";
+						compatible = "national,lm75";
+						reg = <0x4b>;
+					};
+				};
+
+				i2c@6 {
+					reg = <6>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+				};
+
+				i2c@5 {
+					reg = <5>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+				};
+
+				i2c@7 {
+					reg = <7>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+				};
+
+				i2c@3 {
+					reg = <3>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+				};
+			};
+		};
+
+		serial0: serial@4500 {
+			cell-index = <0>;
+			device_type = "serial";
+			compatible = "fsl,ns16550", "ns16550";
+			reg = <0x4500 0x100>;
+			clock-frequency = <264000000>;
+			interrupts = <9 0x8>;
+			interrupt-parent = <&ipic>;
+		};
+
+		dma@82a8 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,mpc8309-dma", "fsl,elo-dma";
+			reg = <0x82a8 4>;
+			ranges = <0 0x8100 0x1a8>;
+			interrupt-parent = <&ipic>;
+			interrupts = <71 8>;
+			cell-index = <0>;
+			dma-channel@0 {
+				compatible = "fsl,mpc8309-dma-channel",
+						"fsl,elo-dma-channel";
+				reg = <0 0x80>;
+				interrupt-parent = <&ipic>;
+				interrupts = <71 8>;
+			};
+			dma-channel@80 {
+				compatible = "fsl,mpc8309-dma-channel",
+						"fsl,elo-dma-channel";
+				reg = <0x80 0x80>;
+				interrupt-parent = <&ipic>;
+				interrupts = <71 8>;
+			};
+			dma-channel@100 {
+				compatible = "fsl,mpc8309-dma-channel",
+						"fsl,elo-dma-channel";
+				reg = <0x100 0x80>;
+				interrupt-parent = <&ipic>;
+				interrupts = <71 8>;
+			};
+			dma-channel@180 {
+				compatible = "fsl,mpc8309-dma-channel",
+						"fsl,elo-dma-channel";
+				reg = <0x180 0x28>;
+				interrupt-parent = <&ipic>;
+				interrupts = <71 8>;
+			};
+		};
+
+		ipic: pic@700 {
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			compatible = "fsl,pq2pro-pic", "fsl,ipic";
+			interrupt-controller;
+			reg = <0x700 0x100>;
+			device_type = "ipic";
+		};
+
+		gpio1: gpio-controller@c00 {
+			#gpio-cells = <2>;
+			compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio";
+			reg = <0xc00 0x100>;
+			interrupts = <75 0x8>;
+			interrupt-parent = <&ipic>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio2: gpio-controller@d00 {
+			#gpio-cells = <2>;
+			compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio";
+			reg = <0xd00 0x100>;
+			interrupts = <75 0x8>;
+			interrupt-parent = <&ipic>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		spi@7000 {
+			cell-index = <0>;
+			compatible = "fsl,spi";
+			reg = <0x7000 0x1000>;
+			interrupts = <16 0x8>;
+			interrupt-parent = <&ipic>;
+			mode = "cpu";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* GPIO_15 chipselect for ZYNQ flash */
+			gpios = <&gpio1 15 0>;
+
+			zynq_flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "spansion,m25p80";
+				reg = <0>;
+				spi-max-frequency = <4000000>;
+				m25p,fast-read;
+				partition@0 {
+					label = "bootloader";
+					reg = <0x0 0x01000000>;
+				};
+			};
+		};
+	};
+
+	qe: qe@e0100000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "qe";
+		compatible = "fsl,qe";
+		ranges = <0x0 0xe0100000 0x00100000>;
+		reg = <0xe0100000 0x480>;
+		brg-frequency = <0>;
+		bus-frequency = <396000000>;
+		fsl,qe-num-snums = <32>;
+
+		muram@10000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,qe-muram", "fsl,cpm-muram";
+			ranges = <0x0 0x00010000 0x00004000>;
+
+			data-only@0 {
+				compatible = "fsl,qe-muram-data",
+					     "fsl,cpm-muram-data";
+				reg = <0x0 0x4000>;
+			};
+		};
+
+		/* ZYNQ (UCC1, MDIO 0x10, MII) */
+		enet_zynq: ethernet@2000 {
+			device_type = "network";
+			compatible = "ucc_geth";
+			cell-index = <1>;
+			reg = <0x2000 0x200>;
+			interrupts = <32>;
+			interrupt-parent = <&qeic>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			/*id=0, full-dup, 100M, no-pause, no-asym_p*/
+			fixed-link = <0 1 100 0 0>;
+			rx-clock-name = "clk9";
+			tx-clock-name = "clk10";
+			phy-connection-type = "mii";
+		};
+
+		/* Piggy2 (UCC3, MDIO 0x00, RMII) */
+		enet_piggy2: ucc@2200 {
+			device_type = "network";
+			compatible = "ucc_geth";
+			cell-index = <3>;
+			reg = <0x2200 0x200>;
+			interrupts = <34>;
+			interrupt-parent = <&qeic>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			rx-clock-name = "none";
+			tx-clock-name = "clk12";
+			phy-handle = <&phy_piggy2>;
+			phy-connection-type = "rmii";
+		};
+
+		mdio@2320 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x2320 0x38>;
+			compatible = "fsl,ucc-mdio";
+
+			/* Piggy2 (UCC3, MDIO 0x00, RMII) */
+			phy_piggy2: ethernet-phy@0 {
+				reg = <0x0>;
+				device_type = "ethernet-phy";
+			};
+
+			/* Explicitly set the tbi-phy to a non-zero address
+			 * so that it does not conflict with phy_piggy2 that
+			 * is unfortunately at address 0
+			 */
+			tbi1: tbi-phy@1 {
+				reg = <0x1>;
+				device_type = "tbi-phy";
+			};
+		};
+
+		qeic: interrupt-controller@80 {
+			interrupt-controller;
+			compatible = "fsl,qe-ic";
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			reg = <0x80 0x80>;
+			big-endian;
+			interrupts = <32 8 33 8>;
+			interrupt-parent = <&ipic>;
+		};
+		bootcount@0x13ff8 {
+			device_type = "bootcount";
+			compatible = "u-boot,bootcount";
+			reg = <0x13ff8 0x08>;
+		};
+
+	};
+	localbus@e0005000 {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		compatible = "fsl,mpc8309-localbus", "fsl,pq2pro-localbus",
+			     "simple-bus";
+		reg = <0xe0005000 0xd8>;
+		ranges = <0 0 0xf0000000 0x04000000
+			1 0 0xe8000000 0x01000000
+			2 0 0xe0000000 0x10000000
+			3 0 0xb0000000 0x10000000>;
+
+		flash@0,0 {
+			compatible = "cfi-flash";
+			reg = <0 0x00000000 0x04000000>;
+			bank-width = <2>;
+			nornand = "nor";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			use-advanced-sector-protection;
+			partition@0 { /* 768KB */
+				label = "u-boot";
+				reg = <0 0xc0000>;
+			};
+			partition@c0000 { /* 256KB */
+				label = "qe-fw";
+				reg = <0xc0000 0x40000>;
+			};
+			partition@100000 { /* 128KB */
+				label = "env";
+				reg = <0x100000 0x20000>;
+			};
+			partition@120000 { /* 128KB */
+				label = "envred";
+				reg = <0x120000 0x20000>;
+			};
+			partition@140000 { /* 64256KB */
+				label = "ubi0";
+				reg = <0x140000 0x3EC0000>;
+			};
+		};
+	};
+};
+
+#include "km8309-uboot.dtsi"
diff --git a/roms/u-boot/arch/powerpc/dts/kmtepr2.dts b/roms/u-boot/arch/powerpc/dts/kmtepr2.dts
new file mode 100644
index 000000000..7cf6aefe5
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/kmtepr2.dts
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Hitachi Power Grids TEPR2 Device Tree Source
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/dts-v1/;
+
+#include "km8321.dtsi"
+
+/ {
+	model = "KMTEPR2";
+	compatible = "hitachi,kmpbec8321";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		ethernet0 = &enet_piggy2;
+		serial0 = &serial0;
+	};
+};
+
+&i2c0 {
+	mux@70 {
+		compatible = "nxp,pca9547";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Inventory EEPROM of the unit itself */
+			ivm@50 {
+				label = "MAIN_CTRL";
+				compatible = "dummy";
+				reg = <0x50>;
+			};
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Temperature sensors */
+			temp@49 {
+				label = "board";
+				compatible = "national,lm75";
+				reg = <0x49>;
+			};
+
+			temp@4a {
+				label = "power";
+				compatible = "national,lm75";
+				reg = <0x4a>;
+			};
+		};
+	};
+};
+
+&par_io {
+	/* UCC5 as HDLC controller for ICN */
+	pio_ucc5: ucc_pin@04 {
+		pio-map = <
+			/* port  pin  dir  open_drain  assignment  has_irq */
+			2   0  1  0  2  0   /* TxD0 */
+			2   8  2  0  2  0   /* RxD0 */
+			2  29  2  0  2  0   /* CTS */
+			3  30  2  0  1  0   /* ICN CLK */
+			>;
+	};
+
+	/* UCC4 Piggy Ethernet */
+	pio_ucc4: ucc_pin@03 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			3   4  3  0  2  0	/* MDIO */
+			3   5  1  0  2  0	/* MDC  */
+
+			1 18  1  0  1  0	/* TxD0 */
+			1 19  1  0  1  0	/* TxD1 */
+			1 22  2  0  1  0	/* RxD0 */
+			1 23  2  0  1  0	/* RxD1 */
+			1 26  2  0  1  0	/* RX_ER */
+			1 28  2  0  1  0	/* RX_DV */
+			1 30  1  0  1  0	/* TX_EN */
+			1 31  2  0  1  0	/* CRS */
+			3 10  2  0  3  0	/* UCC4_RMII_CLK (CLK17) */
+		>;
+	};
+
+	pio_spi: spi_pin@01 {
+		pio-map = <
+			/*
+			 *port pin dir open_drain assignment has_irq
+			 * SPI_MOSI (PD0, bi, f3)
+			 */
+			3  0  3  0  1  0
+			/* SPI_MISO (PD1, bi, f3) */
+			3  1  3  0  1  0
+			/* SPI_CLK  (PD2, bi, f3) */
+			3  2  3  0  1  0
+		>;
+	};
+};
+
+&localbus {
+	ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
+		1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
+		2 0 0xa0000000 0x10000000 /* LB 2 NVSRAM */
+		3 0 0xb0000000 0x10000000>; /* LB 3 TEP2 */
+
+	flash@0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0x00000000 0x04000000>;
+		bank-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		use-advanced-sector-protection;
+		partition@0 { /* 768KB */
+			label = "u-boot";
+			reg = <0 0xC0000>;
+		};
+		partition@c0000 { /* 128KB */
+			label = "env";
+			reg = <0xc0000 0x20000>;
+		};
+		partition@e0000 { /* 128KB */
+			label = "envred";
+			reg = <0xe0000 0x20000>;
+		};
+		partition@100000 { /* 64512KB */
+			label = "ubi0";
+			reg = <0x100000 0x3F00000>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/kmtuge1.dts b/roms/u-boot/arch/powerpc/dts/kmtuge1.dts
new file mode 100644
index 000000000..41bb3623f
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/kmtuge1.dts
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Hitachi Power Grids TUGE1 Device Tree Source
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/dts-v1/;
+
+#include "km8321.dtsi"
+
+/ {
+	model = "TUGE1";
+	compatible = "hitachi,kmpbec8321";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		ethernet0 = &enet_piggy2;
+		serial0 = &serial0;
+	};
+};
+
+&par_io {
+	/* UCC5 as HDLC controller for ICN */
+	pio_ucc5: ucc_pin@04 {
+		pio-map = <
+			/* port  pin  dir  open_drain  assignment  has_irq */
+			2   0  1  0  2  0   /* TxD0 */
+			2   8  2  0  2  0   /* RxD0 */
+			2  29  2  0  2  0   /* CTS */
+			3  30  2  0  1  0   /* ICN CLK */
+			>;
+	};
+
+	/* UCC4 Piggy Ethernet */
+	pio_ucc4: ucc_pin@03 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			3   4  3  0  2  0	/* MDIO */
+			3   5  1  0  2  0	/* MDC  */
+
+			1 18  1  0  1  0	/* TxD0 */
+			1 19  1  0  1  0	/* TxD1 */
+			1 22  2  0  1  0	/* RxD0 */
+			1 23  2  0  1  0	/* RxD1 */
+			1 26  2  0  1  0	/* RX_ER */
+			1 28  2  0  1  0	/* RX_DV */
+			1 30  1  0  1  0	/* TX_EN */
+			1 31  2  0  1  0	/* CRS */
+			3  10  2  0  3  0 /* UCC4_RMII_CLK (CLK17) */
+		>;
+	};
+
+	pio_spi: spi_pin@01 {
+		pio-map = <
+			/*
+			 *port pin dir open_drain assignment has_irq
+			 * SPI_MOSI (PD0, bi, f3)
+			 */
+			3  0  3  0  1  0
+			/* SPI_MISO (PD1, bi, f3) */
+			3  1  3  0  1  0
+			/* SPI_CLK  (PD2, bi, f3) */
+			3  2  3  0  1  0
+		>;
+	};
+};
+
+&localbus {
+	ranges = <0 0 0xf0000000 0x04000000     /* LB 0 Flash (boot) */
+		  1 0 0xe8000000 0x01000000     /* LB 1 PRIO1 and Piggy */
+		  2 0 0xa0000000 0x10000000>;   /* LB 2 PAXI */
+
+	flash@0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0x00000000 0x04000000>;
+		bank-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 { /* 768KB */
+			label = "u-boot";
+			reg = <0 0xC0000>;
+		};
+		partition@c0000 { /* 128KB */
+			label = "env";
+			reg = <0xc0000 0x20000>;
+		};
+		partition@e0000 { /* 128KB */
+			label = "envred";
+			reg = <0xe0000 0x20000>;
+		};
+		partition@100000 { /* 64512KB */
+			label = "ubi0";
+			reg = <0x100000 0x3F00000>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/kmtuxa1.dts b/roms/u-boot/arch/powerpc/dts/kmtuxa1.dts
new file mode 100644
index 000000000..8b06a18f5
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/kmtuxa1.dts
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Hitachi Power Grids TUXA1 Device Tree Source
+ *
+ * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
+ *
+ */
+
+/dts-v1/;
+
+#include "km8321.dtsi"
+
+/ {
+	model = "TUXA1";
+	compatible = "hitachi,kmpbec8321";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		ethernet0 = &enet_piggy2;
+		serial0 = &serial0;
+	};
+};
+
+&par_io {
+	/* UCC5 as HDLC controller for ICN */
+	pio_ucc5: ucc_pin@04 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			2   0  1  0  2  0   /* TxD0 */
+			2   8  2  0  2  0   /* RxD0 */
+			2  29  2  0  2  0   /* CTS */
+			3  30  2  0  1  0   /* ICN CLK */
+		>;
+	};
+
+	/* UCC4 Piggy Ethernet */
+	pio_ucc4: ucc_pin@03 {
+		pio-map = <
+			/* port pin dir open_drain assignment has_irq */
+			3   4  3  0  2  0	/* MDIO */
+			3   5  1  0  2  0	/* MDC  */
+
+			1 18  1  0  1  0	/* TxD0 */
+			1 19  1  0  1  0	/* TxD1 */
+			1 22  2  0  1  0	/* RxD0 */
+			1 23  2  0  1  0	/* RxD1 */
+			1 26  2  0  1  0	/* RX_ER */
+			1 28  2  0  1  0	/* RX_DV */
+			1 30  1  0  1  0	/* TX_EN */
+			1 31  2  0  1  0	/* CRS */
+			3 10  2  0  3  0 /* UCC4_RMII_CLK (CLK17) */
+		>;
+	};
+
+	pio_spi: spi_pin@01 {
+		pio-map = <
+			/*
+			 *port  pin  dir  open_drain  assignment  has_irq
+			 * SPI_MOSI (PD0, bi, f3)
+			 */
+			3  0  3  0  1  0
+			/* SPI_MISO (PD1, bi, f3) */
+			3  1  3  0  1  0
+			/* SPI_CLK  (PD2, bi, f3) */
+			3  2  3  0  1  0
+		>;
+	};
+};
+
+&localbus {
+	ranges = <0 0 0xf0000000 0x04000000     /* LB 0 Flash (boot) */
+		  1 0 0xe8000000 0x01000000     /* LB 1 PRIO1 and Piggy */
+		  2 0 0xa0000000 0x10000000     /* LB 2 LPXF */
+		  3 0 0xb0000000 0x10000000>;	/* LB 3 PINC2 */
+
+	flash@0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0x00000000 0x04000000>;
+		bank-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		partition@0 { /* 768KB */
+			label = "u-boot";
+			reg = <0 0xC0000>;
+		};
+		partition@c0000 { /* 128KB */
+			label = "env";
+			reg = <0xc0000 0x20000>;
+		};
+		partition@e0000 { /* 128KB */
+			label = "envred";
+			reg = <0xe0000 0x20000>;
+		};
+		partition@100000 { /* 64512KB */
+			label = "ubi0";
+			reg = <0x100000 0x3F00000>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/mcr3000.dts b/roms/u-boot/arch/powerpc/dts/mcr3000.dts
new file mode 100644
index 000000000..5abf111dc
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/mcr3000.dts
@@ -0,0 +1,22 @@
+/*
+ * MCR3000 Device Tree Source
+ *
+ * Copyright 2017 CS Systemes d'Information
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+/ {
+	WDT: watchdog@0 {
+		compatible = "fsl,pq1-wdt";
+	};
+	SERIAL: smc@0 {
+		compatible = "fsl,pq1-smc";
+	};
+
+	chosen {
+		stdout-path = &SERIAL;
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/mpc8379erdb.dts b/roms/u-boot/arch/powerpc/dts/mpc8379erdb.dts
new file mode 100644
index 000000000..b1881b161
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/mpc8379erdb.dts
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * MPC8379E RDB Device Tree Source
+ *
+ * Copyright 2020 NXP
+ */
+
+/dts-v1/;
+
+/ {
+	compatible = "fsl,mpc8379erdb";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,8379@0 {
+			device_type = "cpu";
+			reg = <0x0>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <32768>;
+			i-cache-size = <32768>;
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;  // 256MB at 0
+	};
+
+	localbus@e0005000 {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		compatible = "fsl,elbc", "simple-bus";
+		reg = <0xe0005000 0x1000>;
+		interrupts = <77 0x8>;
+		interrupt-parent = <&ipic>;
+	};
+
+	immr@e0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "simple-bus";
+		ranges = <0 0xe0000000 0x00100000>;
+		reg = <0xe0000000 0x00000200>;
+		bus-frequency = <0>;
+
+		sdhc@2e000 {
+			compatible = "fsl,esdhc";
+			reg = <0x2e000 0x1000>;
+			bus-width = <0x4>;
+			clock-frequency = <0>;
+		};
+
+		ipic: interrupt-controller@700 {
+			compatible = "fsl,ipic";
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			reg = <0x700 0x100>;
+			device_type = "ipic";
+		};
+
+	};
+
+};
diff --git a/roms/u-boot/arch/powerpc/dts/mpc8548-post.dtsi b/roms/u-boot/arch/powerpc/dts/mpc8548-post.dtsi
new file mode 100644
index 000000000..2206f2da9
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/mpc8548-post.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * MPC8548 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	device_type = "soc";
+	compatible = "fsl,mpc8548-immr", "simple-bus";
+	bus-frequency = <0x0>;
+
+	mpic: pic@40000 {
+		interrupt-controller;
+		#address-cells = <0>;
+		#interrupt-cells = <4>;
+		reg = <0x40000 0x40000>;
+		compatible = "fsl,mpic";
+		device_type = "open-pic";
+		big-endian;
+		single-cpu-affinity;
+		last-interrupt-source = <255>;
+	};
+};
+
+&pcie {
+	compatible = "fsl,pcie-mpc8548", "fsl,pcie-fsl-qoriq";
+	law_trgt_if = <2>;
+	#address-cells = <3>;
+	#size-cells = <2>;
+	device_type = "pci";
+	bus-range = <0x0 0xff>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/mpc8548.dtsi b/roms/u-boot/arch/powerpc/dts/mpc8548.dtsi
new file mode 100644
index 000000000..b24567dc6
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/mpc8548.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * MPC8548CDS Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,8548@0 {
+			device_type = "cpu";
+			reg = <0>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/mpc8548cds.dts b/roms/u-boot/arch/powerpc/dts/mpc8548cds.dts
new file mode 100644
index 000000000..3b927bd26
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/mpc8548cds.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * MPC8548CDS Device Tree Source
+ *
+ * Copyright 2006 - 2012 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "mpc8548.dtsi"
+
+/ {
+	model = "fsl,MPC8548CDS";
+	compatible = "fsl,MPC8548CDS";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	soc: soc8548@e0000000 {
+		ranges = <0x0 0x0 0xe0000000 0x100000>;
+	};
+
+	pcie: pcie@e000a000 {
+		reg = <0x0 0xe000a000 0x0 0x1000>;	/* registers */
+		ranges = <0x01000000 0x0 0x00000000 0x0 0xe3000000 0x0 0x00100000   /* downstream I/O */
+			  0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+};
+
+/include/ "mpc8548-post.dtsi"
diff --git a/roms/u-boot/arch/powerpc/dts/mpc8548cds_36b.dts b/roms/u-boot/arch/powerpc/dts/mpc8548cds_36b.dts
new file mode 100644
index 000000000..98d7c2410
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/mpc8548cds_36b.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * MPC8548CDS (36-bit address map) Device Tree Source
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "mpc8548.dtsi"
+
+/ {
+	model = "fsl,MPC8548CDS";
+	compatible = "fsl,MPC8548CDS";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	soc: soc8548@fe0000000 {
+		ranges = <0x0 0xf 0xe0000000 0x100000>;
+	};
+
+	pcie: pcie@fe000a000 {
+		reg = <0xf 0xe000a000 0x0 0x1000>;	/* registers */
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xe3000000 0x0 0x00100000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+};
+
+/include/ "mpc8548-post.dtsi"
diff --git a/roms/u-boot/arch/powerpc/dts/p1010rdb-pa.dts b/roms/u-boot/arch/powerpc/dts/p1010rdb-pa.dts
new file mode 100644
index 000000000..360d254d9
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p1010rdb-pa.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1010 RDB Device Tree Source
+ *
+ * Copyright 2020 NXP
+ */
+
+/include/ "p1010si-pre.dtsi"
+
+/ {
+	model = "fsl,P1010RDB";
+	compatible = "fsl,P1010RDB";
+
+	/include/ "p1010rdb_32b.dtsi"
+};
+
+/include/ "p1010si-post.dtsi"
+/include/ "p1010rdb.dtsi"
diff --git a/roms/u-boot/arch/powerpc/dts/p1010rdb-pa_36b.dts b/roms/u-boot/arch/powerpc/dts/p1010rdb-pa_36b.dts
new file mode 100644
index 000000000..062086a8c
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p1010rdb-pa_36b.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1010 RDB Device Tree Source (36-bit address map)
+ *
+ * Copyright 2020 NXP
+ */
+
+/include/ "p1010si-pre.dtsi"
+
+/ {
+	model = "fsl,P1010RDB";
+	compatible = "fsl,P1010RDB";
+
+	/include/ "p1010rdb_36b.dtsi"
+};
+
+/include/ "p1010si-post.dtsi"
+/include/ "p1010rdb.dtsi"
diff --git a/roms/u-boot/arch/powerpc/dts/p1010rdb-pb.dts b/roms/u-boot/arch/powerpc/dts/p1010rdb-pb.dts
new file mode 100644
index 000000000..9ca562534
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p1010rdb-pb.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1010RDB Device Tree Source
+ *
+ * Copyright 2020 NXP
+ */
+
+/include/ "p1010si-pre.dtsi"
+
+/ {
+	model = "fsl,P1010RDB-PB";
+	compatible = "fsl,P1010RDB-PB";
+
+	/include/ "p1010rdb_32b.dtsi"
+};
+
+/include/ "p1010si-post.dtsi"
+/include/ "p1010rdb.dtsi"
diff --git a/roms/u-boot/arch/powerpc/dts/p1010rdb-pb_36b.dts b/roms/u-boot/arch/powerpc/dts/p1010rdb-pb_36b.dts
new file mode 100644
index 000000000..eeff2a870
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p1010rdb-pb_36b.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1010 RDB Device Tree Source (36-bit address map)
+ *
+ * Copyright 2020 NXP
+ */
+
+/include/ "p1010si-pre.dtsi"
+
+/ {
+	model = "fsl,P1010RDB-PB";
+	compatible = "fsl,P1010RDB-PB";
+
+	/include/ "p1010rdb_36b.dtsi"
+};
+
+/include/ "p1010si-post.dtsi"
+/include/ "p1010rdb.dtsi"
diff --git a/roms/u-boot/arch/powerpc/dts/p1010rdb.dtsi b/roms/u-boot/arch/powerpc/dts/p1010rdb.dtsi
new file mode 100644
index 000000000..c2aecde13
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p1010rdb.dtsi
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1010RDB Device Tree Source
+ *
+ * Copyright 2020 NXP
+ */
+/ {
+	aliases {
+		spi0 = &espi0;
+	};
+};
+
+&soc {
+	mdio@24000 {
+		phy0: ethernet-phy@0 {
+			reg = <0x1>;
+		};
+
+		phy1: ethernet-phy@1 {
+			reg = <0x0>;
+		};
+
+		phy2: ethernet-phy@2 {
+			reg = <0x2>;
+		};
+
+		tbi-phy@3 {
+			device_type = "tbi-phy";
+			reg = <0x3>;
+		};
+	};
+
+	mdio@25000 {
+		tbi0: tbi-phy@11 {
+			reg = <0x11>;
+			device_type = "tbi-phy";
+		};
+	};
+
+	mdio@26000 {
+		tbi1: tbi-phy@11 {
+			reg = <0x11>;
+			device_type = "tbi-phy";
+		};
+	};
+
+	enet0: ethernet@b0000 {
+		phy-handle = <&phy0>;
+		phy-connection-type = "rgmii-id";
+	};
+
+	enet1: ethernet@b1000 {
+		phy-handle = <&phy1>;
+		tbi-handle = <&tbi0>;
+		phy-connection-type = "sgmii";
+	};
+
+	enet2: ethernet@b2000 {
+		phy-handle = <&phy2>;
+		tbi-handle = <&tbi1>;
+		phy-connection-type = "sgmii";
+	};
+
+	i2c@3000 {
+		rtc@68 {
+			compatible = "pericom,pt7c4338";
+			reg = <0x68>;
+		};
+	};
+
+	spi@7000 {
+		status = "okay";
+		flash@0 {
+			compatible = "jedec,spi-nor";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0>;
+			spi-max-frequency = <10000000>; /* input clock */
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/p1010rdb_32b.dtsi b/roms/u-boot/arch/powerpc/dts/p1010rdb_32b.dtsi
new file mode 100644
index 000000000..5da790da5
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p1010rdb_32b.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1010RDB Device Tree Source
+ *
+ * Copyright 2020 NXP
+ */
+
+soc: soc@ffe00000 {
+	ranges = <0x0 0x0 0xffe00000 0x100000>;
+};
+
+pci1: pcie@ffe09000 {
+	reg = <0 0xffe09000 0 0x1000>;
+	ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+		  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+};
+
+pci0: pcie@ffe0a000 {
+	reg = <0 0xffe0a000 0 0x1000>;
+	ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+		  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/p1010rdb_36b.dtsi b/roms/u-boot/arch/powerpc/dts/p1010rdb_36b.dtsi
new file mode 100644
index 000000000..54dd16e43
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p1010rdb_36b.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1010RDB Device Tree Source (36-bit address map)
+ *
+ * Copyright 2020 NXP
+ */
+
+soc: soc@fffe00000 {
+	ranges = <0x0 0xf 0xffe00000 0x100000>;
+};
+
+pci1: pcie@fffe09000 {
+	reg = <0xf 0xffe09000 0 0x1000>;
+	ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
+		  0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
+};
+
+pci0: pcie@fffe0a000 {
+	reg = <0xf 0xffe0a000 0 0x1000>;
+	ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
+		  0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/p1010si-post.dtsi b/roms/u-boot/arch/powerpc/dts/p1010si-post.dtsi
new file mode 100644
index 000000000..2e7eb0e2f
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p1010si-post.dtsi
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1010 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2020 NXP
+ */
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	device_type = "soc";
+	compatible = "fsl,p1010-immr", "simple-bus";
+	bus-frequency = <0>;
+
+	mpic: pic@40000 {
+		interrupt-controller;
+		#address-cells = <0>;
+		#interrupt-cells = <4>;
+		reg = <0x40000 0x40000>;
+		compatible = "fsl,mpic";
+		device_type = "open-pic";
+		big-endian;
+		single-cpu-affinity;
+		last-interrupt-source = <255>;
+	};
+
+	espi0: spi@7000 {
+		compatible = "fsl,mpc8536-espi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x7000 0x1000>;
+		fsl,espi-num-chipselects = <1>;
+		status = "disabled";
+	};
+
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+
+/include/ "pq3-etsec2-0.dtsi"
+	enet0: ethernet@b0000 {
+		queue-group@b0000 {
+			fsl,rx-bit-map = <0xff>;
+			fsl,tx-bit-map = <0xff>;
+		};
+	};
+
+/include/ "pq3-etsec2-1.dtsi"
+	enet1: ethernet@b1000 {
+		queue-group@b1000 {
+			fsl,rx-bit-map = <0xff>;
+			fsl,tx-bit-map = <0xff>;
+		};
+	};
+
+/include/ "pq3-etsec2-2.dtsi"
+	enet2: ethernet@b2000 {
+		queue-group@b2000 {
+			fsl,rx-bit-map = <0xff>;
+			fsl,tx-bit-map = <0xff>;
+		};
+
+	};
+};
+
+/* controller at 0x9000 */
+&pci1 {
+	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+	law_trgt_if = <1>;
+	#address-cells = <3>;
+	#size-cells = <2>;
+	device_type = "pci";
+	bus-range = <0x0 0xff>;
+};
+
+/* controller at 0xa000 */
+&pci0 {
+	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+	law_trgt_if = <2>;
+	#address-cells = <3>;
+	#size-cells = <2>;
+	device_type = "pci";
+	bus-range = <0x0 0xff>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/p1010si-pre.dtsi b/roms/u-boot/arch/powerpc/dts/p1010si-pre.dtsi
new file mode 100644
index 000000000..9d7bb6c95
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p1010si-pre.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1010 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2020 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
+/ {
+	compatible = "fsl,P1010";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,P1010@0 {
+			device_type = "cpu";
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/p1020-post.dtsi b/roms/u-boot/arch/powerpc/dts/p1020-post.dtsi
new file mode 100644
index 000000000..03b688699
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p1020-post.dtsi
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	device_type = "soc";
+	compatible = "fsl,p1020-immr", "simple-bus";
+	bus-frequency = <0x0>;
+
+	usb@22000 {
+		compatible = "fsl-usb2-dr";
+		reg = <0x22000 0x1000>;
+		phy_type = "ulpi";
+	};
+
+	usb@23000 {
+		compatible = "fsl-usb2-dr";
+		reg = <0x23000 0x1000>;
+		phy_type = "ulpi";
+	};
+
+	mpic: pic@40000 {
+		interrupt-controller;
+		#address-cells = <0>;
+		#interrupt-cells = <4>;
+		reg = <0x40000 0x40000>;
+		compatible = "fsl,mpic";
+		device_type = "open-pic";
+		big-endian;
+		single-cpu-affinity;
+		last-interrupt-source = <255>;
+	};
+
+	esdhc: esdhc@2e000 {
+		compatible = "fsl,esdhc";
+		reg = <0x2e000 0x1000>;
+		/* Filled in by U-Boot */
+		clock-frequency = <0>;
+	};
+
+	espi0: spi@7000 {
+		compatible = "fsl,mpc8536-espi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x7000 0x1000>;
+		fsl,espi-num-chipselects = <4>;
+		status = "disabled";
+	};
+
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+
+/include/ "pq3-etsec2-0.dtsi"
+	enet0: enet0_grp2: ethernet@b0000 {
+	};
+
+/include/ "pq3-etsec2-1.dtsi"
+	enet1: enet1_grp2: ethernet@b1000 {
+	};
+
+/include/ "pq3-etsec2-2.dtsi"
+	enet2: enet2_grp2: ethernet@b2000 {
+	};
+};
+
+/include/ "pq3-etsec2-grp2-0.dtsi"
+/include/ "pq3-etsec2-grp2-1.dtsi"
+/include/ "pq3-etsec2-grp2-2.dtsi"
+
+/* PCIe controller base address 0x9000 */
+&pci1 {
+	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+	law_trgt_if = <1>;
+	#address-cells = <3>;
+	#size-cells = <2>;
+	device_type = "pci";
+	bus-range = <0x0 0xff>;
+};
+
+/* PCIe controller base address 0xa000 */
+&pci0 {
+	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+	law_trgt_if = <2>;
+	#address-cells = <3>;
+	#size-cells = <2>;
+	device_type = "pci";
+	bus-range = <0x0 0xff>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/p1020.dtsi b/roms/u-boot/arch/powerpc/dts/p1020.dtsi
new file mode 100644
index 000000000..ee2b6f494
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p1020.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: PowerPC,P1020@0 {
+			device_type = "cpu";
+			reg = <0>;
+		};
+		cpu1: PowerPC,P1020@1 {
+			device_type = "cpu";
+			reg = <1>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/p1020rdb-pc.dts b/roms/u-boot/arch/powerpc/dts/p1020rdb-pc.dts
new file mode 100644
index 000000000..ab4232536
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p1020rdb-pc.dts
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020RDB-PC Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p1020.dtsi"
+
+/ {
+	model = "fsl,P1020RDB-PC";
+	compatible = "fsl,P1020RDB-PC";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+	};
+
+	pci1: pcie@ffe09000 {
+		reg = <0x0 0xffe09000 0x0 0x1000>;	/* registers */
+		ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pci0: pcie@ffe0a000 {
+		reg = <0x0 0xffe0a000 0x0 0x1000>;	/* registers */
+		ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	aliases {
+		spi0 = &espi0;
+	};
+};
+
+/include/ "p1020rdb-pc.dtsi"
+/include/ "p1020-post.dtsi"
+
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/p1020rdb-pc.dtsi b/roms/u-boot/arch/powerpc/dts/p1020rdb-pc.dtsi
new file mode 100644
index 000000000..6bf424fd3
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p1020rdb-pc.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+&soc {
+	mdio@24000 {
+		phy0: ethernet-phy@0 {
+			interrupt-parent = <&mpic>;
+			interrupts = <3 1 0 0>;
+			reg = <0x0>;
+		};
+
+		phy1: ethernet-phy@1 {
+			interrupt-parent = <&mpic>;
+			interrupts = <2 1 0 0>;
+			reg = <0x1>;
+		};
+
+		tbi0: tbi-phy@11 {
+			device_type = "tbi-phy";
+			reg = <0x11>;
+		};
+	};
+
+	mdio@25000 {
+		tbi1: tbi-phy@11 {
+			reg = <0x11>;
+			device_type = "tbi-phy";
+		};
+	};
+
+	enet0: ethernet@b0000 {
+		phy-connection-type = "rgmii-id";
+		fixed-link {
+			speed = <1000>;
+			full-duplex;
+		};
+
+	};
+
+	enet1: ethernet@b1000 {
+		phy-handle = <&phy0>;
+		tbi-handle = <&tbi1>;
+		phy-connection-type = "sgmii";
+	};
+
+	enet2: ethernet@b2000 {
+		phy-handle = <&phy1>;
+		phy-connection-type = "rgmii-id";
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/p1020rdb-pc_36b.dts b/roms/u-boot/arch/powerpc/dts/p1020rdb-pc_36b.dts
new file mode 100644
index 000000000..708f9a9db
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p1020rdb-pc_36b.dts
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020RDB-PC (36-bit address map) Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p1020.dtsi"
+
+/ {
+	model = "fsl,P1020RDB-PC";
+	compatible = "fsl,P1020RDB-PC";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	soc: soc@fffe00000 {
+		ranges = <0x0 0xf 0xffe00000 0x100000>;
+	};
+
+	pci1: pcie@fffe09000 {
+		reg = <0xf 0xffe09000 0x0 0x1000>;	/* registers */
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pci0: pcie@fffe0a000 {
+		reg = <0xf 0xffe0a000 0x0 0x1000>;	/* registers */
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	aliases {
+		spi0 = &espi0;
+	};
+};
+
+/include/ "p1020rdb-pc.dtsi"
+/include/ "p1020-post.dtsi"
+
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/p1020rdb-pd.dts b/roms/u-boot/arch/powerpc/dts/p1020rdb-pd.dts
new file mode 100644
index 000000000..b05f3deed
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p1020rdb-pd.dts
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020RDB-PD Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p1020.dtsi"
+
+/ {
+	model = "fsl,P1020RDB-PD";
+	compatible = "fsl,P1020RDB-PD";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+		mdio@24000 {
+			phy0: ethernet-phy@0 {
+				interrupts = <3 1 0 0>;
+				reg = <0x0>;
+			};
+
+			phy1: ethernet-phy@1 {
+				interrupts = <2 1 0 0>;
+				reg = <0x1>;
+			};
+		};
+
+		mdio@25000 {
+			tbi1: tbi-phy@11 {
+				reg = <0x11>;
+				device_type = "tbi-phy";
+			};
+		};
+
+		mdio@26000 {
+			tbi2: tbi-phy@11 {
+				reg = <0x11>;
+				device_type = "tbi-phy";
+			};
+		};
+
+		enet0: ethernet@b0000 {
+			phy-connection-type = "rgmii-id";
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+
+		enet1: ethernet@b1000 {
+			phy-handle = <&phy0>;
+			tbi-handle = <&tbi1>;
+			phy-connection-type = "sgmii";
+		};
+
+		enet2: ethernet@b2000 {
+			phy-handle = <&phy1>;
+			phy-connection-type = "rgmii-id";
+		};
+	};
+
+	pci1: pcie@ffe09000 {
+		reg = <0x0 0xffe09000 0x0 0x1000>;	/* registers */
+		ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pci0: pcie@ffe0a000 {
+		reg = <0x0 0xffe0a000 0x0 0x1000>;	/* registers */
+		ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	aliases {
+		spi0 = &espi0;
+	};
+};
+
+/include/ "p1020-post.dtsi"
+
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/p2020-post.dtsi b/roms/u-boot/arch/powerpc/dts/p2020-post.dtsi
new file mode 100644
index 000000000..6d46f7d8d
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p2020-post.dtsi
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2020 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	device_type = "soc";
+	compatible = "fsl,p2020-immr", "simple-bus";
+	bus-frequency = <0x0>;
+
+	usb@22000 {
+		compatible = "fsl-usb2-dr";
+		reg = <0x22000 0x1000>;
+		phy_type = "ulpi";
+	};
+
+	mpic: pic@40000 {
+		interrupt-controller;
+		#address-cells = <0>;
+		#interrupt-cells = <4>;
+		reg = <0x40000 0x40000>;
+		compatible = "fsl,mpic";
+		device_type = "open-pic";
+		big-endian;
+		single-cpu-affinity;
+		last-interrupt-source = <255>;
+	};
+
+	esdhc: esdhc@2e000 {
+		compatible = "fsl,esdhc";
+		reg = <0x2e000 0x1000>;
+		/* Filled in by U-Boot */
+		clock-frequency = <0>;
+	};
+
+	espi0: spi@7000 {
+		compatible = "fsl,mpc8536-espi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x7000 0x1000>;
+		fsl,espi-num-chipselects = <4>;
+		status = "disabled";
+	};
+
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+
+/include/ "pq3-etsec1-0.dtsi"
+/include/ "pq3-etsec1-1.dtsi"
+/include/ "pq3-etsec1-2.dtsi"
+};
+
+/* PCIe controller base address 0x8000 */
+&pci2 {
+	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+	law_trgt_if = <0>;
+	#address-cells = <3>;
+	#size-cells = <2>;
+	device_type = "pci";
+	bus-range = <0x0 0xff>;
+};
+
+/* PCIe controller base address 0x9000 */
+&pci1 {
+	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+	law_trgt_if = <1>;
+	#address-cells = <3>;
+	#size-cells = <2>;
+	device_type = "pci";
+	bus-range = <0x0 0xff>;
+};
+
+/* PCIe controller base address 0xa000 */
+&pci0 {
+	compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+	law_trgt_if = <2>;
+	#address-cells = <3>;
+	#size-cells = <2>;
+	device_type = "pci";
+	bus-range = <0x0 0xff>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/p2020.dtsi b/roms/u-boot/arch/powerpc/dts/p2020.dtsi
new file mode 100644
index 000000000..7c4c2061d
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p2020.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2020 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500v2_power_isa.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: PowerPC,P2020@0 {
+			device_type = "cpu";
+			reg = <0>;
+		};
+		cpu1: PowerPC,P2020@1 {
+			device_type = "cpu";
+			reg = <1>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/p2020rdb-pc.dts b/roms/u-boot/arch/powerpc/dts/p2020rdb-pc.dts
new file mode 100644
index 000000000..b37931ac4
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p2020rdb-pc.dts
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2020RDB-PC Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p2020.dtsi"
+
+/ {
+	model = "fsl,P2020RDB-PC";
+	compatible = "fsl,P2020RDB-PC";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+	};
+
+	pci2: pcie@ffe08000 {
+		reg = <0x0 0xffe08000 0x0 0x1000>;	/* registers */
+		status = "disabled";
+	};
+
+	pci1: pcie@ffe09000 {
+		reg = <0x0 0xffe09000 0x0 0x1000>;	/* registers */
+		ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pci0: pcie@ffe0a000 {
+		reg = <0x0 0xffe0a000 0x0 0x1000>;	/* registers */
+		ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	aliases {
+		spi0 = &espi0;
+	};
+};
+
+/include/ "p2020rdb-pc.dtsi"
+/include/ "p2020-post.dtsi"
+
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/p2020rdb-pc.dtsi b/roms/u-boot/arch/powerpc/dts/p2020rdb-pc.dtsi
new file mode 100644
index 000000000..0d2acc746
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p2020rdb-pc.dtsi
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+&soc {
+	mdio@24520 {
+		phy0: ethernet-phy@0 {
+			interrupts = <3 1 0 0>;
+			reg = <0x0>;
+			};
+		phy1: ethernet-phy@1 {
+			interrupts = <2 1 0 0>;
+			reg = <0x1>;
+			};
+	};
+
+	mdio@25520 {
+		tbi0: tbi-phy@11 {
+			reg = <0x11>;
+			device_type = "tbi-phy";
+		};
+	};
+
+	mdio@26520 {
+		status = "disabled";
+	};
+
+	enet0: ethernet@24000 {
+		phy-connection-type = "rgmii-id";
+		fixed-link {
+			speed = <1000>;
+			full-duplex;
+		};
+	};
+
+	enet1: ethernet@25000 {
+		tbi-handle = <&tbi0>;
+		phy-handle = <&phy0>;
+		phy-connection-type = "sgmii";
+	};
+
+	enet2: ethernet@26000 {
+		phy-handle = <&phy1>;
+		phy-connection-type = "rgmii-id";
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/p2020rdb-pc_36b.dts b/roms/u-boot/arch/powerpc/dts/p2020rdb-pc_36b.dts
new file mode 100644
index 000000000..ecdc022d9
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p2020rdb-pc_36b.dts
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2020RDB-PC (36-bit address map) Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019 NXP
+ */
+
+/include/ "p2020.dtsi"
+
+/ {
+	model = "fsl,P2020RDB-PC";
+	compatible = "fsl,P2020RDB-PC";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	soc: soc@fffe00000 {
+		ranges = <0x0 0xf 0xffe00000 0x100000>;
+	};
+
+	pci2: pcie@fffe08000 {
+		reg = <0xf 0xffe08000 0x0 0x1000>;	/* registers */
+		status = "disabled";
+	};
+
+	pci1: pcie@fffe09000 {
+		reg = <0xf 0xffe09000 0x0 0x1000>;	/* registers */
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pci0: pcie@fffe0a000 {
+		reg = <0xf 0xffe0a000 0x0 0x1000>;	/* registers */
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	aliases {
+		spi0 = &espi0;
+	};
+};
+
+/include/ "p2020rdb-pc.dtsi"
+/include/ "p2020-post.dtsi"
+
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/p2041.dtsi b/roms/u-boot/arch/powerpc/dts/p2041.dtsi
new file mode 100644
index 000000000..ad09b138f
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p2041.dtsi
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2041 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019-2020 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500mc_power_isa.dtsi"
+
+/ {
+	compatible = "fsl,P2041";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: PowerPC,e500mc@0 {
+			device_type = "cpu";
+			reg = <0>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu1: PowerPC,e500mc@1 {
+			device_type = "cpu";
+			reg = <1>;
+			fsl,portid-mapping = <0x40000000>;
+		};
+		cpu2: PowerPC,e500mc@2 {
+			device_type = "cpu";
+			reg = <2>;
+			fsl,portid-mapping = <0x20000000>;
+		};
+		cpu3: PowerPC,e500mc@3 {
+			device_type = "cpu";
+			reg = <3>;
+			fsl,portid-mapping = <0x10000000>;
+		};
+	};
+
+	soc: soc@ffe000000 {
+		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+		reg = <0xf 0xfe000000 0 0x00001000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "simple-bus";
+
+		mpic: pic@40000 {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <4>;
+			reg = <0x40000 0x40000>;
+			compatible = "fsl,mpic", "chrp,open-pic";
+			device_type = "open-pic";
+			clock-frequency = <0x0>;
+		};
+
+		espi0: spi@110000 {
+			compatible = "fsl,mpc8536-espi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x110000 0x1000>;
+			fsl,espi-num-chipselects = <4>;
+			status = "disabled";
+		};
+
+		usb0: usb@210000 {
+			compatible = "fsl-usb2-mph";
+			reg = <0x210000 0x1000>;
+			phy_type = "utmi";
+		};
+
+		usb1: usb@211000 {
+			compatible = "fsl-usb2-mph";
+			reg = <0x210000 0x1000>;
+			phy_type = "utmi";
+		};
+
+		sata: sata@220000 {
+			compatible = "fsl,pq-sata-v2";
+			reg = <0x220000 0x1000>;
+			interrupts = <68 0x2 0 0>;
+			sata-offset = <0x1000>;
+			sata-number = <2>;
+			sata-fpdma = <0>;
+		};
+
+		esdhc: esdhc@114000 {
+			compatible = "fsl,esdhc";
+			reg = <0x114000 0x1000>;
+			clock-frequency = <0>;
+		};
+
+		/include/ "qoriq-i2c-0.dtsi"
+		/include/ "qoriq-i2c-1.dtsi"
+	};
+
+	pcie@ffe200000 {
+		compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe200000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie@ffe201000 {
+		compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe201000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie@ffe202000 {
+		compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe202000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <2>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/p2041rdb.dts b/roms/u-boot/arch/powerpc/dts/p2041rdb.dts
new file mode 100644
index 000000000..0fa1f0985
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p2041rdb.dts
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2041RDB Device Tree Source
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019-2020 NXP
+ */
+
+/include/ "p2041.dtsi"
+
+/ {
+	model = "fsl,P2041RDB";
+	compatible = "fsl,P2041RDB";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	aliases {
+		phy_rgmii_0 = &phy_rgmii_0;
+		phy_rgmii_1 = &phy_rgmii_1;
+		phy_sgmii_2 = &phy_sgmii_2;
+		phy_sgmii_3 = &phy_sgmii_3;
+		phy_sgmii_4 = &phy_sgmii_4;
+		phy_sgmii_1c = &phy_sgmii_1c;
+		phy_sgmii_1d = &phy_sgmii_1d;
+		phy_sgmii_1e = &phy_sgmii_1e;
+		phy_sgmii_1f = &phy_sgmii_1f;
+		phy_xgmii_2 = &phy_xgmii_2;
+		spi0 = &espi0;
+	};
+
+	soc: soc@ffe000000 {
+		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+		reg = <0xf 0xfe000000 0 0x00001000>;
+
+		fman@400000 {
+			ethernet@e0000 {
+				phy-handle = <&phy_sgmii_2>;
+				phy-connection-type = "sgmii";
+			};
+
+			mdio@e1120 {
+				phy_rgmii_0: ethernet-phy@0 {
+					reg = <0x0>;
+				};
+
+				phy_rgmii_1: ethernet-phy@1 {
+					reg = <0x1>;
+				};
+
+				phy_sgmii_2: ethernet-phy@2 {
+					reg = <0x2>;
+				};
+
+				phy_sgmii_3: ethernet-phy@3 {
+					reg = <0x3>;
+				};
+
+				phy_sgmii_4: ethernet-phy@4 {
+					reg = <0x4>;
+				};
+
+				phy_sgmii_1c: ethernet-phy@1c {
+					reg = <0x1c>;
+				};
+
+				phy_sgmii_1d: ethernet-phy@1d {
+					reg = <0x1d>;
+				};
+
+				phy_sgmii_1e: ethernet-phy@1e {
+					reg = <0x1e>;
+				};
+
+				phy_sgmii_1f: ethernet-phy@1f {
+					reg = <0x1f>;
+				};
+			};
+
+			ethernet@e2000 {
+				phy-handle = <&phy_sgmii_3>;
+				phy-connection-type = "sgmii";
+			};
+
+			ethernet@e4000 {
+				phy-handle = <&phy_sgmii_4>;
+				phy-connection-type = "sgmii";
+			};
+
+			ethernet@e6000 {
+				phy-handle = <&phy_rgmii_1>;
+				phy-connection-type = "rgmii";
+			};
+
+			ethernet@e8000 {
+				phy-handle = <&phy_rgmii_0>;
+				phy-connection-type = "rgmii";
+			};
+
+			ethernet@f0000 {
+				phy-handle = <&phy_xgmii_2>;
+				phy-connection-type = "xgmii";
+			};
+
+			mdio@f1000 {
+				phy_xgmii_2: ethernet-phy@0 {
+					compatible = "ethernet-phy-ieee802.3-c45";
+					reg = <0x0>;
+				};
+			};
+		};
+	};
+};
+
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		/* input clock */
+		spi-max-frequency = <10000000>;
+	};
+};
+
+/include/ "p2041si-post.dtsi"
diff --git a/roms/u-boot/arch/powerpc/dts/p2041si-post.dtsi b/roms/u-boot/arch/powerpc/dts/p2041si-post.dtsi
new file mode 100644
index 000000000..01ab39595
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p2041si-post.dtsi
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * P2041/P2040 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+&soc {
+
+/include/ "qoriq-clockgen1.dtsi"
+/include/ "qoriq-gpio-0.dtsi"
+
+/* include used FMan blocks */
+/include/ "qoriq-fman-0.dtsi"
+/include/ "qoriq-fman-0-1g-0.dtsi"
+/include/ "qoriq-fman-0-1g-1.dtsi"
+/include/ "qoriq-fman-0-1g-2.dtsi"
+/include/ "qoriq-fman-0-1g-3.dtsi"
+/include/ "qoriq-fman-0-1g-4.dtsi"
+/include/ "qoriq-fman-0-10g-0.dtsi"
+	fman@400000 {
+		enet0: ethernet@e0000 {
+		};
+
+		enet1: ethernet@e2000 {
+		};
+
+		enet2: ethernet@e4000 {
+		};
+
+		enet3: ethernet@e6000 {
+		};
+
+		enet4: ethernet@e8000 {
+		};
+
+		enet5: ethernet@f0000 {
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/p3041.dtsi b/roms/u-boot/arch/powerpc/dts/p3041.dtsi
new file mode 100644
index 000000000..e34117b65
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p3041.dtsi
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P3041 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2010 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019-2020 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500mc_power_isa.dtsi"
+
+/ {
+	compatible = "fsl,P3041";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: PowerPC,e500mc@0 {
+			device_type = "cpu";
+			reg = <0>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu1: PowerPC,e500mc@1 {
+			device_type = "cpu";
+			reg = <1>;
+			fsl,portid-mapping = <0x40000000>;
+		};
+		cpu2: PowerPC,e500mc@2 {
+			device_type = "cpu";
+			reg = <2>;
+			fsl,portid-mapping = <0x20000000>;
+		};
+		cpu3: PowerPC,e500mc@3 {
+			device_type = "cpu";
+			reg = <3>;
+			fsl,portid-mapping = <0x10000000>;
+		};
+	};
+
+	soc: soc@ffe000000 {
+		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+		reg = <0xf 0xfe000000 0 0x00001000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "simple-bus";
+
+		mpic: pic@40000 {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <4>;
+			reg = <0x40000 0x40000>;
+			compatible = "fsl,mpic", "chrp,open-pic";
+			device_type = "open-pic";
+			clock-frequency = <0x0>;
+		};
+
+		espi0: spi@110000 {
+			compatible = "fsl,mpc8536-espi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x110000 0x1000>;
+			fsl,espi-num-chipselects = <4>;
+			status = "disabled";
+		};
+
+		usb0: usb@fe210000 {
+			compatible = "fsl-usb2-mph";
+			reg = <0x210000 0x1000>;
+			phy_type = "utmi";
+		};
+
+		usb1: usb@fe211000 {
+			compatible = "fsl-usb2-dr";
+			reg = <0x211000 0x1000>;
+			phy_type = "utmi";
+		};
+
+		sata: sata@220000 {
+			compatible = "fsl,pq-sata-v2";
+			reg = <0x220000 0x1000>;
+			interrupts = <68 0x2 0 0>;
+			sata-offset = <0x1000>;
+			sata-number = <2>;
+			sata-fpdma = <0>;
+		};
+
+		esdhc: esdhc@114000 {
+			compatible = "fsl,esdhc";
+			reg = <0x114000 0x1000>;
+			clock-frequency = <0>;
+		};
+		/include/ "qoriq-i2c-0.dtsi"
+		/include/ "qoriq-i2c-1.dtsi"
+	};
+
+	pcie@ffe200000 {
+		compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe200000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie@ffe201000 {
+		compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe201000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie@ffe202000 {
+		compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe202000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <2>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie@ffe203000 {
+		compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe203000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <3>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/p3041ds.dts b/roms/u-boot/arch/powerpc/dts/p3041ds.dts
new file mode 100644
index 000000000..069dae3b8
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p3041ds.dts
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P3041DS Device Tree Source
+ *
+ * Copyright 2010 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019-2020 NXP
+ */
+
+/include/ "p3041.dtsi"
+
+/ {
+	model = "fsl,P3041DS";
+	compatible = "fsl,P3041DS";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	aliases{
+		phy_rgmii_0 = &phy_rgmii_0;
+		phy_rgmii_1 = &phy_rgmii_1;
+		phy_sgmii_1c = &phy_sgmii_1c;
+		phy_sgmii_1d = &phy_sgmii_1d;
+		phy_sgmii_1e = &phy_sgmii_1e;
+		phy_sgmii_1f = &phy_sgmii_1f;
+		phy_xgmii_1 = &phy_xgmii_1;
+		phy_xgmii_2 = &phy_xgmii_2;
+		emi1_rgmii = &hydra_mdio_rgmii;
+		emi1_sgmii = &hydra_mdio_sgmii;
+		emi2_xgmii = &hydra_mdio_xgmii;
+		spi0 = &espi0;
+	};
+
+	soc: soc@ffe000000 {
+		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+		reg = <0xf 0xfe000000 0 0x00001000>;
+		fman@400000{
+			ethernet@e0000 {
+				phy-handle = <&phy_sgmii_1c>;
+				phy-connection-type = "sgmii";
+			};
+
+			ethernet@e2000 {
+				phy-handle = <&phy_sgmii_1d>;
+				phy-connection-type = "sgmii";
+			};
+
+			ethernet@e4000 {
+				phy-handle = <&phy_sgmii_1e>;
+				phy-connection-type = "sgmii";
+			};
+
+			ethernet@e6000 {
+				phy-handle = <&phy_sgmii_1f>;
+				phy-connection-type = "sgmii";
+			};
+
+			ethernet@e8000 {
+				phy-handle = <&phy_rgmii_1>;
+				phy-connection-type = "rgmii";
+			};
+
+			ethernet@f0000 {
+				phy-handle = <&phy_xgmii_1>;
+				phy-connection-type = "xgmii";
+			};
+
+			hydra_mdio_xgmii: mdio@f1000 {
+				status = "disabled";
+
+				phy_xgmii_1: ethernet-phy@4 {
+					compatible = "ethernet-phy-ieee802.3-c45";
+					reg = <0x4>;
+				};
+
+				phy_xgmii_2: ethernet-phy@0 {
+					compatible = "ethernet-phy-ieee802.3-c45";
+					reg = <0x0>;
+				};
+			};
+		};
+	};
+
+	lbc: localbus@ffe124000 {
+		reg = <0xf 0xfe124000 0 0x1000>;
+		ranges = <0 0 0xf 0xe8000000 0x08000000
+			  2 0 0xf 0xffa00000 0x00040000
+			  3 0 0xf 0xffdf0000 0x00008000>;
+
+		board-control@3,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis";
+			reg = <3 0 0x30>;
+			ranges = <0 3 0 0x30>;
+
+			mdio-mux-emi1 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "mdio-mux-mmioreg", "mdio-mux";
+				mdio-parent-bus = <&mdio0>;
+				reg = <9 1>;
+				mux-mask = <0x78>;
+
+				hydra_mdio_rgmii: rgmii-mdio@8 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <8>;
+					status = "disabled";
+
+					phy_rgmii_0: ethernet-phy@0 {
+						reg = <0x0>;
+					};
+
+					phy_rgmii_1: ethernet-phy@1 {
+						reg = <0x1>;
+					};
+				};
+
+				hydra_mdio_sgmii: sgmii-mdio@28 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x28>;
+					status = "disabled";
+
+					phy_sgmii_1c: ethernet-phy@1c {
+						reg = <0x1c>;
+					};
+
+					phy_sgmii_1d: ethernet-phy@1d {
+						reg = <0x1d>;
+					};
+
+					phy_sgmii_1e: ethernet-phy@1e {
+						reg = <0x1e>;
+					};
+
+					phy_sgmii_1f: ethernet-phy@1f {
+						reg = <0x1f>;
+					};
+				};
+			};
+		};
+	};
+};
+
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		/* input clock */
+		spi-max-frequency = <10000000>;
+	};
+};
+
+/include/ "p3041si-post.dtsi"
diff --git a/roms/u-boot/arch/powerpc/dts/p3041si-post.dtsi b/roms/u-boot/arch/powerpc/dts/p3041si-post.dtsi
new file mode 100644
index 000000000..21f322f06
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p3041si-post.dtsi
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * P3041 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+&soc {
+
+/include/ "qoriq-clockgen1.dtsi"
+/include/ "qoriq-gpio-0.dtsi"
+
+/* include used FMan blocks */
+/include/ "qoriq-fman-0.dtsi"
+/include/ "qoriq-fman-0-1g-0.dtsi"
+/include/ "qoriq-fman-0-1g-1.dtsi"
+/include/ "qoriq-fman-0-1g-2.dtsi"
+/include/ "qoriq-fman-0-1g-3.dtsi"
+/include/ "qoriq-fman-0-1g-4.dtsi"
+/include/ "qoriq-fman-0-10g-0.dtsi"
+	fman@400000 {
+		enet0: ethernet@e0000 {
+		};
+
+		enet1: ethernet@e2000 {
+		};
+
+		enet2: ethernet@e4000 {
+		};
+
+		enet3: ethernet@e6000 {
+		};
+
+		enet4: ethernet@e8000 {
+		};
+
+		enet5: ethernet@f0000 {
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/p4080.dtsi b/roms/u-boot/arch/powerpc/dts/p4080.dtsi
new file mode 100644
index 000000000..8ab5cf541
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p4080.dtsi
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P4080/P4040 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019-2020 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e500mc_power_isa.dtsi"
+
+/ {
+	compatible = "fsl,P4080";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: PowerPC,e500mc@0 {
+			device_type = "cpu";
+			reg = <0>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu1: PowerPC,e500mc@1 {
+			device_type = "cpu";
+			reg = <1>;
+			fsl,portid-mapping = <0x40000000>;
+		};
+		cpu2: PowerPC,e500mc@2 {
+			device_type = "cpu";
+			reg = <2>;
+			fsl,portid-mapping = <0x20000000>;
+		};
+		cpu3: PowerPC,e500mc@3 {
+			device_type = "cpu";
+			reg = <3>;
+			fsl,portid-mapping = <0x10000000>;
+		};
+		cpu4: PowerPC,e500mc@4 {
+			device_type = "cpu";
+			reg = <4>;
+			fsl,portid-mapping = <0x08000000>;
+		};
+		cpu5: PowerPC,e500mc@5 {
+			device_type = "cpu";
+			reg = <5>;
+			fsl,portid-mapping = <0x04000000>;
+		};
+		cpu6: PowerPC,e500mc@6 {
+			device_type = "cpu";
+			reg = <6>;
+			fsl,portid-mapping = <0x02000000>;
+		};
+		cpu7: PowerPC,e500mc@7 {
+			device_type = "cpu";
+			reg = <7>;
+			fsl,portid-mapping = <0x01000000>;
+		};
+	};
+
+	soc: soc@ffe000000 {
+		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+		reg = <0xf 0xfe000000 0 0x00001000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "simple-bus";
+
+		mpic: pic@40000 {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <4>;
+			reg = <0x40000 0x40000>;
+			compatible = "fsl,mpic", "chrp,open-pic";
+			device_type = "open-pic";
+			clock-frequency = <0x0>;
+		};
+
+		espi0: spi@110000 {
+			compatible = "fsl,mpc8536-espi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x110000 0x1000>;
+			fsl,espi-num-chipselects = <4>;
+			status = "disabled";
+		};
+
+		esdhc: esdhc@114000 {
+			compatible = "fsl,esdhc";
+			reg = <0x114000 0x1000>;
+			clock-frequency = <0>;
+		};
+
+		usb0@210000 {
+			compatible = "fsl-usb2-mph";
+			reg = <0x210000 0x1000>;
+			phy_type = "ulpi";
+		};
+
+		usb1@211000 {
+			compatible = "fsl-usb2-dr";
+			reg = <0x211000 0x1000>;
+			phy_type = "ulpi";
+		};
+		/include/ "qoriq-i2c-0.dtsi"
+		/include/ "qoriq-i2c-1.dtsi"
+	};
+
+	pcie@ffe200000 {
+		compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe200000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie@ffe201000 {
+		compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe201000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie@ffe202000 {
+		compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe202000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <2>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/p4080ds.dts b/roms/u-boot/arch/powerpc/dts/p4080ds.dts
new file mode 100644
index 000000000..d5618f1e4
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p4080ds.dts
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P4080DS Device Tree Source
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019-2020 NXP
+ */
+
+/include/ "p4080.dtsi"
+
+/ {
+	model = "fsl,P4080DS";
+	compatible = "fsl,P4080DS";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	aliases {
+		phy_rgmii = &phyrgmii;
+		phy5_slot3 = &phy5slot3;
+		phy6_slot3 = &phy6slot3;
+		phy7_slot3 = &phy7slot3;
+		phy8_slot3 = &phy8slot3;
+		emi1_slot3 = &p4080mdio2;
+		emi1_slot4 = &p4080mdio1;
+		emi1_slot5 = &p4080mdio3;
+		emi1_rgmii = &p4080mdio0;
+		emi2_slot4 = &p4080xmdio1;
+		emi2_slot5 = &p4080xmdio3;
+		spi0 = &espi0;
+	};
+
+	soc: soc@ffe000000 {
+		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+		reg = <0xf 0xfe000000 0 0x00001000>;
+
+		fman@400000 {
+			ethernet@e0000 {
+				phy-handle = <&phy0>;
+				phy-connection-type = "sgmii";
+			};
+
+			ethernet@e2000 {
+				phy-handle = <&phy1>;
+				phy-connection-type = "sgmii";
+			};
+
+			ethernet@e4000 {
+				phy-handle = <&phy2>;
+				phy-connection-type = "sgmii";
+			};
+
+			ethernet@e6000 {
+				phy-handle = <&phy3>;
+				phy-connection-type = "sgmii";
+			};
+
+			ethernet@f0000 {
+				phy-handle = <&phy10>;
+				phy-connection-type = "xgmii";
+			};
+		};
+
+		fman@500000 {
+			ethernet@e0000 {
+				phy-handle = <&phy5>;
+				phy-connection-type = "sgmii";
+			};
+
+			ethernet@e2000 {
+				phy-handle = <&phy6>;
+				phy-connection-type = "sgmii";
+			};
+
+			ethernet@e4000 {
+				phy-handle = <&phy7>;
+				phy-connection-type = "sgmii";
+			};
+
+			ethernet@e6000 {
+				phy-handle = <&phy8>;
+				phy-connection-type = "sgmii";
+			};
+
+			ethernet@f0000 {
+				phy-handle = <&phy11>;
+				phy-connection-type = "xgmii";
+			};
+		};
+	};
+
+	mdio-mux-emi1 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "mdio-mux-gpio", "mdio-mux";
+		mdio-parent-bus = <&mdio0>;
+		gpios = <&gpio0 1 0>, <&gpio0 0 0>;
+
+		p4080mdio0: mdio@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			phyrgmii: ethernet-phy@0 {
+				reg = <0x0>;
+			};
+		};
+
+		p4080mdio1: mdio@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+
+			phy5: ethernet-phy@1c {
+				reg = <0x1c>;
+			};
+
+			phy6: ethernet-phy@1d {
+				reg = <0x1d>;
+			};
+
+			phy7: ethernet-phy@1e {
+				reg = <0x1e>;
+			};
+
+			phy8: ethernet-phy@1f {
+				reg = <0x1f>;
+			};
+		};
+
+		p4080mdio2: mdio@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+			status = "disabled";
+
+			phy5slot3: ethernet-phy@1c {
+				reg = <0x1c>;
+			};
+
+			phy6slot3: ethernet-phy@1d {
+				reg = <0x1d>;
+			};
+
+			phy7slot3: ethernet-phy@1e {
+				reg = <0x1e>;
+			};
+
+			phy8slot3: ethernet-phy@1f {
+				reg = <0x1f>;
+			};
+		};
+
+		p4080mdio3: mdio@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+
+			phy0: ethernet-phy@1c {
+				reg = <0x1c>;
+			};
+
+			phy1: ethernet-phy@1d {
+				reg = <0x1d>;
+			};
+
+			phy2: ethernet-phy@1e {
+				reg = <0x1e>;
+			};
+
+			phy3: ethernet-phy@1f {
+				reg = <0x1f>;
+			};
+		};
+	};
+
+	mdio-mux-emi2 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "mdio-mux-gpio", "mdio-mux";
+		mdio-parent-bus = <&xmdio0>;
+		gpios = <&gpio0 3 0>, <&gpio0 2 0>;
+
+		p4080xmdio1: mdio@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+
+			phy11: ethernet-phy@0 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				reg = <0x0>;
+			};
+		};
+
+		p4080xmdio3: mdio@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+
+			phy10: ethernet-phy@4 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				reg = <0x4>;
+			};
+		};
+	};
+};
+
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		/* input clock */
+		spi-max-frequency = <10000000>;
+	};
+};
+
+/include/ "p4080si-post.dtsi"
diff --git a/roms/u-boot/arch/powerpc/dts/p4080si-post.dtsi b/roms/u-boot/arch/powerpc/dts/p4080si-post.dtsi
new file mode 100644
index 000000000..7c3f2fb92
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p4080si-post.dtsi
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * P4080/P4040 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+&soc {
+
+/include/ "qoriq-clockgen1.dtsi"
+/include/ "qoriq-gpio-0.dtsi"
+
+/* include used FMan blocks */
+/include/ "qoriq-fman-0.dtsi"
+/include/ "qoriq-fman-0-1g-0.dtsi"
+/include/ "qoriq-fman-0-1g-1.dtsi"
+/include/ "qoriq-fman-0-1g-2.dtsi"
+/include/ "qoriq-fman-0-1g-3.dtsi"
+/include/ "qoriq-fman-0-10g-0.dtsi"
+	fman@400000 {
+		enet0: ethernet@e0000 {
+		};
+
+		enet1: ethernet@e2000 {
+		};
+
+		enet2: ethernet@e4000 {
+		};
+
+		enet3: ethernet@e6000 {
+		};
+
+		enet4: ethernet@f0000 {
+		};
+	};
+
+/include/ "qoriq-fman-1.dtsi"
+/include/ "qoriq-fman-1-1g-0.dtsi"
+/include/ "qoriq-fman-1-1g-1.dtsi"
+/include/ "qoriq-fman-1-1g-2.dtsi"
+/include/ "qoriq-fman-1-1g-3.dtsi"
+/include/ "qoriq-fman-1-10g-0.dtsi"
+	fman@500000 {
+		enet5: ethernet@e0000 {
+		};
+
+		enet6: ethernet@e2000 {
+		};
+
+		enet7: ethernet@e4000 {
+		};
+
+		enet8: ethernet@e6000 {
+		};
+
+		enet9: ethernet@f0000 {
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/p5040.dtsi b/roms/u-boot/arch/powerpc/dts/p5040.dtsi
new file mode 100644
index 000000000..10402cf22
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p5040.dtsi
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P5040 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019-2020 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e5500_power_isa.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: PowerPC,e5500@0 {
+			device_type = "cpu";
+			reg = <0>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu1: PowerPC,e5500@1 {
+			device_type = "cpu";
+			reg = <1>;
+			fsl,portid-mapping = <0x40000000>;
+		};
+		cpu2: PowerPC,e5500@2 {
+			device_type = "cpu";
+			reg = <2>;
+			fsl,portid-mapping = <0x20000000>;
+		};
+		cpu3: PowerPC,e5500@3 {
+			device_type = "cpu";
+			reg = <3>;
+			fsl,portid-mapping = <0x10000000>;
+		};
+	};
+
+	soc: soc@ffe000000 {
+		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+		reg = <0xf 0xfe000000 0 0x00001000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "simple-bus";
+
+		mpic: pic@40000 {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <4>;
+			reg = <0x40000 0x40000>;
+			compatible = "fsl,mpic", "chrp,open-pic";
+			device_type = "open-pic";
+			clock-frequency = <0x0>;
+		};
+
+		espi0: spi@110000 {
+			compatible = "fsl,mpc8536-espi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x110000 0x1000>;
+			fsl,espi-num-chipselects = <4>;
+			status = "disabled";
+		};
+
+		usb@210000 {
+			compatible = "fsl-usb2-mph";
+			reg = <0x210000 0x1000>;
+			phy_type = "utmi";
+		};
+
+		usb@211000 {
+			compatible = "fsl-usb2-dr";
+			reg = <0x211000 0x1000>;
+			phy_type = "utmi";
+		};
+
+		sata: sata@220000 {
+			compatible = "fsl,pq-sata-v2";
+			reg = <0x220000 0x1000>;
+			interrupts = <68 0x2 0 0>;
+			sata-offset = <0x1000>;
+			sata-number = <2>;
+			sata-fpdma = <0>;
+		};
+
+		esdhc: esdhc@114000 {
+			compatible = "fsl,esdhc";
+			reg = <0x114000 0x1000>;
+			clock-frequency = <0>;
+		};
+
+		/include/ "qoriq-i2c-0.dtsi"
+		/include/ "qoriq-i2c-1.dtsi"
+	};
+
+	pcie@ffe200000 {
+		compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe200000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie@ffe201000 {
+		compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe201000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie@ffe202000 {
+		compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe202000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <2>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/p5040ds.dts b/roms/u-boot/arch/powerpc/dts/p5040ds.dts
new file mode 100644
index 000000000..c2ec765d3
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p5040ds.dts
@@ -0,0 +1,281 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P5040DS Device Tree Source
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019-2020 NXP
+ */
+
+/include/ "p5040.dtsi"
+
+/ {
+	model = "fsl,P5040DS";
+	compatible = "fsl,P5040DS";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	aliases{
+		phy_sgmii_slot2_1c = &phy_sgmii_slot2_1c;
+		phy_sgmii_slot2_1d = &phy_sgmii_slot2_1d;
+		phy_sgmii_slot2_1e = &phy_sgmii_slot2_1e;
+		phy_sgmii_slot2_1f = &phy_sgmii_slot2_1f;
+		phy_sgmii_slot3_1c = &phy_sgmii_slot3_1c;
+		phy_sgmii_slot3_1d = &phy_sgmii_slot3_1d;
+		phy_sgmii_slot3_1e = &phy_sgmii_slot3_1e;
+		phy_sgmii_slot3_1f = &phy_sgmii_slot3_1f;
+		phy_sgmii_slot5_1c = &phy_sgmii_slot5_1c;
+		phy_sgmii_slot5_1d = &phy_sgmii_slot5_1d;
+		phy_sgmii_slot5_1e = &phy_sgmii_slot5_1e;
+		phy_sgmii_slot5_1f = &phy_sgmii_slot5_1f;
+		phy_sgmii_slot6_1c = &phy_sgmii_slot6_1c;
+		phy_sgmii_slot6_1d = &phy_sgmii_slot6_1d;
+		phy_sgmii_slot6_1e = &phy_sgmii_slot6_1e;
+		phy_sgmii_slot6_1f = &phy_sgmii_slot6_1f;
+		hydra_rg = &hydra_rg;
+		hydra_sg_slot2 = &hydra_sg_slot2;
+		hydra_sg_slot3 = &hydra_sg_slot3;
+		hydra_sg_slot5 = &hydra_sg_slot5;
+		hydra_sg_slot6 = &hydra_sg_slot6;
+		hydra_xg_slot1 = &hydra_xg_slot1;
+		hydra_xg_slot2 = &hydra_xg_slot2;
+		spi0 = &espi0;
+	};
+
+	soc: soc@ffe000000 {
+		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+		reg = <0xf 0xfe000000 0 0x00001000>;
+
+		fman@400000 {
+			ethernet@e0000 {
+				phy-connection-type = "sgmii";
+			};
+
+			ethernet@e2000 {
+				phy-connection-type = "sgmii";
+			};
+
+			ethernet@e4000 {
+				phy-connection-type = "sgmii";
+			};
+
+			ethernet@e6000 {
+				phy-connection-type = "sgmii";
+			};
+
+			ethernet@e8000 {
+				phy-handle = <&phy_rgmii_0>;
+				phy-connection-type = "rgmii";
+			};
+
+			ethernet@f0000 {
+				phy-handle = <&phy_xgmii_slot_2>;
+				phy-connection-type = "xgmii";
+			};
+		};
+
+		fman@500000 {
+			ethernet@e0000 {
+				phy-connection-type = "sgmii";
+			};
+
+			ethernet@e2000 {
+				phy-connection-type = "sgmii";
+			};
+
+			ethernet@e4000 {
+				phy-connection-type = "sgmii";
+			};
+
+			ethernet@e6000 {
+				phy-connection-type = "sgmii";
+			};
+
+			ethernet@e8000 {
+				phy-handle = <&phy_rgmii_1>;
+				phy-connection-type = "rgmii";
+			};
+
+			ethernet@f0000 {
+				phy-handle = <&phy_xgmii_slot_1>;
+				phy-connection-type = "xgmii";
+			};
+		};
+	};
+
+	lbc: localbus@ffe124000 {
+		reg = <0xf 0xfe124000 0 0x1000>;
+		ranges = <0 0 0xf 0xe8000000 0x08000000
+			  2 0 0xf 0xffa00000 0x00040000
+			  3 0 0xf 0xffdf0000 0x00008000>;
+
+		board-control@3,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis";
+			reg = <3 0 0x40>;
+			ranges = <0 3 0 0x40>;
+
+			mdio-mux-emi1 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "mdio-mux-mmioreg", "mdio-mux";
+				mdio-parent-bus = <&mdio0>;
+				reg = <9 1>;
+				mux-mask = <0x78>;
+
+				hydra_rg:rgmii-mdio@8 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <8>;
+					status = "disabled";
+
+					phy_rgmii_0: ethernet-phy@0 {
+						reg = <0x0>;
+					};
+
+					phy_rgmii_1: ethernet-phy@1 {
+						reg = <0x1>;
+					};
+				};
+
+				hydra_sg_slot2: sgmii-mdio@28 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x28>;
+					status = "disabled";
+
+					phy_sgmii_slot2_1c: ethernet-phy@1c {
+						reg = <0x1c>;
+					};
+
+					phy_sgmii_slot2_1d: ethernet-phy@1d {
+						reg = <0x1d>;
+					};
+
+					phy_sgmii_slot2_1e: ethernet-phy@1e {
+						reg = <0x1e>;
+					};
+
+					phy_sgmii_slot2_1f: ethernet-phy@1f {
+						reg = <0x1f>;
+					};
+				};
+
+				hydra_sg_slot3: sgmii-mdio@68 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x68>;
+					status = "disabled";
+
+					phy_sgmii_slot3_1c: ethernet-phy@1c {
+						reg = <0x1c>;
+					};
+
+					phy_sgmii_slot3_1d: ethernet-phy@1d {
+						reg = <0x1d>;
+					};
+
+					phy_sgmii_slot3_1e: ethernet-phy@1e {
+						reg = <0x1e>;
+					};
+
+					phy_sgmii_slot3_1f: ethernet-phy@1f {
+						reg = <0x1f>;
+					};
+				};
+
+				hydra_sg_slot5: sgmii-mdio@38 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x38>;
+					status = "disabled";
+
+					phy_sgmii_slot5_1c: ethernet-phy@1c {
+						reg = <0x1c>;
+					};
+
+					phy_sgmii_slot5_1d: ethernet-phy@1d {
+						reg = <0x1d>;
+					};
+
+					phy_sgmii_slot5_1e: ethernet-phy@1e {
+						reg = <0x1e>;
+					};
+
+					phy_sgmii_slot5_1f: ethernet-phy@1f {
+						reg = <0x1f>;
+					};
+				};
+				hydra_sg_slot6: sgmii-mdio@48 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x48>;
+					status = "disabled";
+
+					phy_sgmii_slot6_1c: ethernet-phy@1c {
+						reg = <0x1c>;
+					};
+
+					phy_sgmii_slot6_1d: ethernet-phy@1d {
+						reg = <0x1d>;
+					};
+
+					phy_sgmii_slot6_1e: ethernet-phy@1e {
+						reg = <0x1e>;
+					};
+
+					phy_sgmii_slot6_1f: ethernet-phy@1f {
+						reg = <0x1f>;
+					};
+				};
+			};
+
+			mdio-mux-emi2 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "mdio-mux-mmioreg", "mdio-mux";
+				mdio-parent-bus = <&xmdio0>;
+				reg = <9 1>;
+				mux-mask = <0x06>;
+
+				hydra_xg_slot1: hydra-xg-slot1@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+					status = "disabled";
+
+					phy_xgmii_slot_1: ethernet-phy@0 {
+						compatible = "ethernet-phy-ieee802.3-c45";
+						reg = <4>;
+					};
+				};
+
+				hydra_xg_slot2: hydra-xg-slot2@2 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <2>;
+
+					phy_xgmii_slot_2: ethernet-phy@4 {
+						compatible = "ethernet-phy-ieee802.3-c45";
+						reg = <0>;
+					};
+				};
+			};
+		};
+	};
+};
+
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		/* input clock */
+		spi-max-frequency = <10000000>;
+	};
+};
+
+/include/ "p5040si-post.dtsi"
diff --git a/roms/u-boot/arch/powerpc/dts/p5040si-post.dtsi b/roms/u-boot/arch/powerpc/dts/p5040si-post.dtsi
new file mode 100644
index 000000000..1efad2d01
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/p5040si-post.dtsi
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * P5040 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+&soc {
+
+/include/ "qoriq-clockgen1.dtsi"
+/include/ "qoriq-gpio-0.dtsi"
+
+/* include used FMan blocks */
+/include/ "qoriq-fman-0.dtsi"
+/include/ "qoriq-fman-0-1g-0.dtsi"
+/include/ "qoriq-fman-0-1g-1.dtsi"
+/include/ "qoriq-fman-0-1g-2.dtsi"
+/include/ "qoriq-fman-0-1g-3.dtsi"
+/include/ "qoriq-fman-0-1g-4.dtsi"
+/include/ "qoriq-fman-0-10g-0.dtsi"
+	fman@400000 {
+		enet0: ethernet@e0000 {
+		};
+
+		enet1: ethernet@e2000 {
+		};
+
+		enet2: ethernet@e4000 {
+		};
+
+		enet3: ethernet@e6000 {
+		};
+
+		enet4: ethernet@e8000 {
+		};
+
+		enet5: ethernet@f0000 {
+		};
+	};
+
+/include/ "qoriq-fman-1.dtsi"
+/include/ "qoriq-fman-1-1g-0.dtsi"
+/include/ "qoriq-fman-1-1g-1.dtsi"
+/include/ "qoriq-fman-1-1g-2.dtsi"
+/include/ "qoriq-fman-1-1g-3.dtsi"
+/include/ "qoriq-fman-1-1g-4.dtsi"
+/include/ "qoriq-fman-1-10g-0.dtsi"
+	fman@500000 {
+		enet6: ethernet@e0000 {
+		};
+
+		enet7: ethernet@e2000 {
+		};
+
+		enet8: ethernet@e4000 {
+		};
+
+		enet9: ethernet@e6000 {
+		};
+
+		enet10: ethernet@e8000 {
+		};
+
+		enet11: ethernet@f0000 {
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/pq3-etsec1-0.dtsi b/roms/u-boot/arch/powerpc/dts/pq3-etsec1-0.dtsi
new file mode 100644
index 000000000..8800243f3
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/pq3-etsec1-0.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x24000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ethernet@24000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	cell-index = <0>;
+	device_type = "network";
+	model = "eTSEC";
+	compatible = "gianfar";
+	reg = <0x24000 0x1000>;
+	ranges = <0x0 0x24000 0x1000>;
+	fsl,magic-packet;
+	local-mac-address = [ 00 00 00 00 00 00 ];
+	interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
+};
+
+mdio@24520 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "fsl,gianfar-mdio";
+	reg = <0x24520 0x20>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/pq3-etsec1-1.dtsi b/roms/u-boot/arch/powerpc/dts/pq3-etsec1-1.dtsi
new file mode 100644
index 000000000..2bc62d1a5
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/pq3-etsec1-1.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x25000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ethernet@25000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	cell-index = <1>;
+	device_type = "network";
+	model = "eTSEC";
+	compatible = "gianfar";
+	reg = <0x25000 0x1000>;
+	ranges = <0x0 0x25000 0x1000>;
+	fsl,magic-packet;
+	local-mac-address = [ 00 00 00 00 00 00 ];
+	interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
+};
+
+mdio@25520 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "fsl,gianfar-tbi";
+	reg = <0x25520 0x20>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/pq3-etsec1-2.dtsi b/roms/u-boot/arch/powerpc/dts/pq3-etsec1-2.dtsi
new file mode 100644
index 000000000..d45865fe0
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/pq3-etsec1-2.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x26000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ethernet@26000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	cell-index = <2>;
+	device_type = "network";
+	model = "eTSEC";
+	compatible = "gianfar";
+	reg = <0x26000 0x1000>;
+	ranges = <0x0 0x26000 0x1000>;
+	fsl,magic-packet;
+	local-mac-address = [ 00 00 00 00 00 00 ];
+	interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
+};
+
+mdio@26520 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "fsl,gianfar-tbi";
+	reg = <0x26520 0x20>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/pq3-etsec1-3.dtsi b/roms/u-boot/arch/powerpc/dts/pq3-etsec1-3.dtsi
new file mode 100644
index 000000000..853a27359
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/pq3-etsec1-3.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x27000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ethernet@27000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	cell-index = <3>;
+	device_type = "network";
+	model = "eTSEC";
+	compatible = "gianfar";
+	reg = <0x27000 0x1000>;
+	ranges = <0x0 0x27000 0x1000>;
+	fsl,magic-packet;
+	local-mac-address = [ 00 00 00 00 00 00 ];
+	interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>;
+};
+
+mdio@27520 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "fsl,gianfar-tbi";
+	reg = <0x27520 0x20>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/pq3-etsec2-0.dtsi b/roms/u-boot/arch/powerpc/dts/pq3-etsec2-0.dtsi
new file mode 100644
index 000000000..f9d3d0465
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/pq3-etsec2-0.dtsi
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC2 device tree stub [ @ offsets 0x24000/0xb0000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+mdio@24000 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "fsl,etsec2-mdio";
+	reg = <0x24000 0x1000 0xb0030 0x4>;
+};
+
+ethernet@b0000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	device_type = "network";
+	model = "eTSEC";
+	compatible = "fsl,etsec2";
+	reg = <0xb0000 0x1000>;
+	fsl,num_rx_queues = <0x8>;
+	fsl,num_tx_queues = <0x8>;
+	fsl,magic-packet;
+	local-mac-address = [ 00 00 00 00 00 00 ];
+	ranges;
+
+	queue-group@b0000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0xb0000 0x1000>;
+		interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/pq3-etsec2-1.dtsi b/roms/u-boot/arch/powerpc/dts/pq3-etsec2-1.dtsi
new file mode 100644
index 000000000..6c0148190
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/pq3-etsec2-1.dtsi
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC2 device tree stub [ @ offsets 0x25000/0xb1000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+mdio@25000 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "fsl,etsec2-tbi";
+	reg = <0x25000 0x1000 0xb1030 0x4>;
+};
+
+ethernet@b1000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	device_type = "network";
+	model = "eTSEC";
+	compatible = "fsl,etsec2";
+	reg = <0xb1000 0x1000>;
+	fsl,num_rx_queues = <0x8>;
+	fsl,num_tx_queues = <0x8>;
+	fsl,magic-packet;
+	local-mac-address = [ 00 00 00 00 00 00 ];
+	ranges;
+
+	queue-group@b1000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0xb1000 0x1000>;
+		interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/pq3-etsec2-2.dtsi b/roms/u-boot/arch/powerpc/dts/pq3-etsec2-2.dtsi
new file mode 100644
index 000000000..2a597c0db
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/pq3-etsec2-2.dtsi
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC2 device tree stub [ @ offsets 0x26000/0xb2000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+mdio@26000 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "fsl,etsec2-tbi";
+	reg = <0x26000 0x1000 0xb1030 0x4>;
+};
+
+ethernet@b2000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	device_type = "network";
+	model = "eTSEC";
+	compatible = "fsl,etsec2";
+	reg = <0xb2000 0x1000>;
+	fsl,num_rx_queues = <0x8>;
+	fsl,num_tx_queues = <0x8>;
+	fsl,magic-packet;
+	local-mac-address = [ 00 00 00 00 00 00 ];
+	ranges;
+
+	queue-group@b2000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0xb2000 0x1000>;
+		interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi b/roms/u-boot/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi
new file mode 100644
index 000000000..16752a7c4
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb4000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+&enet0_grp2 {
+	queue-group@b4000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0xb4000 0x1000>;
+		interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi b/roms/u-boot/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi
new file mode 100644
index 000000000..046493842
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb5000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+&enet1_grp2 {
+	queue-group@b5000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0xb5000 0x1000>;
+		interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi b/roms/u-boot/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi
new file mode 100644
index 000000000..fe8003c44
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb6000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+&enet2_grp2 {
+	queue-group@b6000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0xb6000 0x1000>;
+		interrupts = <25 2 0 0 26 2 0 0 27 2 0 0>;
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/pq3-i2c-0.dtsi b/roms/u-boot/arch/powerpc/dts/pq3-i2c-0.dtsi
new file mode 100644
index 000000000..86a91e633
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/pq3-i2c-0.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 I2C Device Tree stub
+ *
+ * Copyright 2020 NXP
+ */
+i2c@3000 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	cell-index = <0>;
+	compatible = "fsl-i2c";
+	u-boot,dm-pre-reloc;
+	reg = <0x3000 0x100>;
+	interrupts = <43 2 0 0>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/pq3-i2c-1.dtsi b/roms/u-boot/arch/powerpc/dts/pq3-i2c-1.dtsi
new file mode 100644
index 000000000..5d79b1fb4
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/pq3-i2c-1.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 I2C Device Tree stub
+ *
+ * Copyright 2020 NXP
+ */
+i2c@3100 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	cell-index = <1>;
+	compatible = "fsl-i2c";
+	u-boot,dm-pre-reloc;
+	reg = <0x3100 0x100>;
+	interrupts = <43 2 0 0>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-bman1.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-bman1.dtsi
new file mode 100644
index 000000000..d6164bac8
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-bman1.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ BMan device tree stub [ controller @ offset 0x31a000 ]
+ *
+ * Copyright 2011 - 2014 Freescale Semiconductor Inc.
+ */
+
+bman: bman@31a000 {
+	compatible = "fsl,bman";
+	reg = <0x31a000 0x1000>;
+	interrupts = <16 2 1 2>;
+	fsl,bman-portals = <&bportals>;
+	memory-region = <&bman_fbpr>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-clockgen1.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-clockgen1.dtsi
new file mode 100644
index 000000000..dd4253d1d
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-clockgen1.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ clock control device tree stub [ controller @ offset 0xe1000 ]
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+clockgen: global-utilities@e1000 {
+	compatible = "fsl,qoriq-clockgen-1.0";
+	reg = <0xe1000 0x1000>;
+	#clock-cells = <2>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-clockgen2.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-clockgen2.dtsi
new file mode 100644
index 000000000..dec1e363b
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-clockgen2.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ clock control device tree stub [ controller @ offset 0xe1000 ]
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+clockgen: global-utilities@e1000 {
+	compatible = "fsl,qoriq-clockgen-2.0";
+	reg = <0xe1000 0x1000>;
+	#clock-cells = <2>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-duart-0.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-duart-0.dtsi
new file mode 100644
index 000000000..0ac484384
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-duart-0.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ DUART device tree stub [ controller @ offset 0x11c000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+serial0: serial@11c500 {
+	cell-index = <0>;
+	device_type = "serial";
+	compatible = "fsl,ns16550", "ns16550";
+	reg = <0x11c500 0x100>;
+	clock-frequency = <0>;
+	interrupts = <36 2 0 0>;
+};
+
+serial1: serial@11c600 {
+	cell-index = <1>;
+	device_type = "serial";
+	compatible = "fsl,ns16550", "ns16550";
+	reg = <0x11c600 0x100>;
+	clock-frequency = <0>;
+	interrupts = <36 2 0 0>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-duart-1.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-duart-1.dtsi
new file mode 100644
index 000000000..c712146aa
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-duart-1.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ DUART device tree stub [ controller @ offset 0x11d000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+serial2: serial@11d500 {
+	cell-index = <2>;
+	device_type = "serial";
+	compatible = "fsl,ns16550", "ns16550";
+	reg = <0x11d500 0x100>;
+	clock-frequency = <0>;
+	interrupts = <37 2 0 0>;
+};
+
+serial3: serial@11d600 {
+	cell-index = <3>;
+	device_type = "serial";
+	compatible = "fsl,ns16550", "ns16550";
+	reg = <0x11d600 0x100>;
+	clock-frequency = <0>;
+	interrupts = <37 2 0 0>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-esdhc-0.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-esdhc-0.dtsi
new file mode 100644
index 000000000..dd24a4909
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-esdhc-0.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ eSDHC device tree stub [ controller @ offset 0x114000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+sdhc: sdhc@114000 {
+	compatible = "fsl,esdhc";
+	reg = <0x114000 0x1000>;
+	interrupts = <48 2 0 0>;
+	clock-frequency = <0>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-espi-0.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-espi-0.dtsi
new file mode 100644
index 000000000..e87e6dd49
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-espi-0.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ eSPI device tree stub [ controller @ offset 0x110000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+spi@110000 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "fsl,mpc8536-espi";
+	reg = <0x110000 0x1000>;
+	interrupts = <53 0x2 0 0>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman-0-10g-0.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman-0-10g-0.dtsi
new file mode 100644
index 000000000..0b2488441
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman-0-10g-0.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan 10g port #0 device tree stub [ controller @ offset 0x400000 ]
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@400000 {
+	fman0_rx_0x10: port@90000 {
+		cell-index = <0x10>;
+		compatible = "fsl,fman-v2-port-rx";
+		reg = <0x90000 0x1000>;
+	};
+
+	fman0_tx_0x30: port@b0000 {
+		cell-index = <0x30>;
+		compatible = "fsl,fman-v2-port-tx";
+		reg = <0xb0000 0x1000>;
+	};
+
+	ethernet@f0000 {
+		cell-index = <0x8>;
+		compatible = "fsl,fman-xgec";
+		reg = <0xf0000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>;
+	};
+
+	xmdio0: mdio@f1000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-xmdio";
+		reg = <0xf1000 0x1000>;
+		interrupts = <101 2 0 0>;
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman-0-1g-0.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman-0-1g-0.dtsi
new file mode 100644
index 000000000..0acc172bc
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman-0-1g-0.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan 1g port #0 device tree stub [ controller @ offset 0x400000 ]
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@400000 {
+	fman0_rx_0x08: port@88000 {
+		cell-index = <0x8>;
+		compatible = "fsl,fman-v2-port-rx";
+		reg = <0x88000 0x1000>;
+	};
+
+	fman0_tx_0x28: port@a8000 {
+		cell-index = <0x28>;
+		compatible = "fsl,fman-v2-port-tx";
+		reg = <0xa8000 0x1000>;
+	};
+
+	ethernet@e0000 {
+		cell-index = <0>;
+		compatible = "fsl,fman-dtsec";
+		reg = <0xe0000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
+		tbi-handle = <&tbi0>;
+		ptp-timer = <&ptp_timer0>;
+	};
+
+	mdio0: mdio@e1120 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-mdio";
+		reg = <0xe1120 0xee0>;
+		interrupts = <100 2 0 0>;
+
+		tbi0: tbi-phy@8 {
+			reg = <0x8>;
+			device_type = "tbi-phy";
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman-0-1g-1.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman-0-1g-1.dtsi
new file mode 100644
index 000000000..52ea19e5f
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman-0-1g-1.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan 1g port #1 device tree stub [ controller @ offset 0x400000 ]
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@400000 {
+	fman0_rx_0x09: port@89000 {
+		cell-index = <0x9>;
+		compatible = "fsl,fman-v2-port-rx";
+		reg = <0x89000 0x1000>;
+	};
+
+	fman0_tx_0x29: port@a9000 {
+		cell-index = <0x29>;
+		compatible = "fsl,fman-v2-port-tx";
+		reg = <0xa9000 0x1000>;
+	};
+
+	ethernet@e2000 {
+		cell-index = <1>;
+		compatible = "fsl,fman-dtsec";
+		reg = <0xe2000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
+		tbi-handle = <&tbi1>;
+		ptp-timer = <&ptp_timer0>;
+	};
+
+	mdio@e3120 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-mdio";
+		reg = <0xe3120 0xee0>;
+
+		tbi1: tbi-phy@8 {
+			reg = <0x8>;
+			device_type = "tbi-phy";
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman-0-1g-2.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman-0-1g-2.dtsi
new file mode 100644
index 000000000..c6a7aed2b
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman-0-1g-2.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan 1g port #2 device tree stub [ controller @ offset 0x400000 ]
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@400000 {
+	fman0_rx_0x0a: port@8a000 {
+		cell-index = <0xa>;
+		compatible = "fsl,fman-v2-port-rx";
+		reg = <0x8a000 0x1000>;
+	};
+
+	fman0_tx_0x2a: port@aa000 {
+		cell-index = <0x2a>;
+		compatible = "fsl,fman-v2-port-tx";
+		reg = <0xaa000 0x1000>;
+	};
+
+	ethernet@e4000 {
+		cell-index = <2>;
+		compatible = "fsl,fman-dtsec";
+		reg = <0xe4000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
+		tbi-handle = <&tbi2>;
+		ptp-timer = <&ptp_timer0>;
+	};
+
+	mdio@e5120 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-mdio";
+		reg = <0xe5120 0xee0>;
+
+		tbi2: tbi-phy@8 {
+			reg = <0x8>;
+			device_type = "tbi-phy";
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman-0-1g-3.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman-0-1g-3.dtsi
new file mode 100644
index 000000000..39f273458
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman-0-1g-3.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan 1g port #3 device tree stub [ controller @ offset 0x400000 ]
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@400000 {
+	fman0_rx_0x0b: port@8b000 {
+		cell-index = <0xb>;
+		compatible = "fsl,fman-v2-port-rx";
+		reg = <0x8b000 0x1000>;
+	};
+
+	fman0_tx_0x2b: port@ab000 {
+		cell-index = <0x2b>;
+		compatible = "fsl,fman-v2-port-tx";
+		reg = <0xab000 0x1000>;
+	};
+
+	ethernet@e6000 {
+		cell-index = <3>;
+		compatible = "fsl,fman-dtsec";
+		reg = <0xe6000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
+		tbi-handle = <&tbi3>;
+		ptp-timer = <&ptp_timer0>;
+	};
+
+	mdio@e7120 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-mdio";
+		reg = <0xe7120 0xee0>;
+
+		tbi3: tbi-phy@8 {
+			reg = <0x8>;
+			device_type = "tbi-phy";
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman-0-1g-4.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman-0-1g-4.dtsi
new file mode 100644
index 000000000..b73014cc7
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman-0-1g-4.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan 1g port #4 device tree stub [ controller @ offset 0x400000 ]
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@400000 {
+	fman0_rx_0x0c: port@8c000 {
+		cell-index = <0xc>;
+		compatible = "fsl,fman-v2-port-rx";
+		reg = <0x8c000 0x1000>;
+	};
+
+	fman0_tx_0x2c: port@ac000 {
+		cell-index = <0x2c>;
+		compatible = "fsl,fman-v2-port-tx";
+		reg = <0xac000 0x1000>;
+	};
+
+	ethernet@e8000 {
+		cell-index = <4>;
+		compatible = "fsl,fman-dtsec";
+		reg = <0xe8000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
+		tbi-handle = <&tbi4>;
+		ptp-timer = <&ptp_timer0>;
+	};
+
+	mdio@e9120 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-mdio";
+		reg = <0xe9120 0xee0>;
+
+		tbi4: tbi-phy@8 {
+			reg = <0x8>;
+			device_type = "tbi-phy";
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman-0.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman-0.dtsi
new file mode 100644
index 000000000..ed103f2fd
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman-0.dtsi
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan device tree stub [ controller @ offset 0x400000 ]
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman0: fman@400000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	cell-index = <0>;
+	compatible = "fsl,fman";
+	ranges = <0 0x400000 0xfe000>;
+	reg = <0x400000 0xfe000>;
+	interrupts = <96 2 0 0>, <16 2 1 1>;
+	clocks = <&clockgen 3 0>;
+	clock-names = "fmanclk";
+	fsl,qman-channel-range = <0x40 0xc>;
+	ptimer-handle = <&ptp_timer0>;
+
+	muram@0 {
+		compatible = "fsl,fman-muram";
+		reg = <0x0 0x28000>;
+	};
+
+	fman0_oh_0x1: port@81000 {
+		cell-index = <0x1>;
+		compatible = "fsl,fman-v2-port-oh";
+		reg = <0x81000 0x1000>;
+	};
+
+	fman0_oh_0x2: port@82000 {
+		cell-index = <0x2>;
+		compatible = "fsl,fman-v2-port-oh";
+		reg = <0x82000 0x1000>;
+	};
+
+	fman0_oh_0x3: port@83000 {
+		cell-index = <0x3>;
+		compatible = "fsl,fman-v2-port-oh";
+		reg = <0x83000 0x1000>;
+	};
+
+	fman0_oh_0x4: port@84000 {
+		cell-index = <0x4>;
+		compatible = "fsl,fman-v2-port-oh";
+		reg = <0x84000 0x1000>;
+	};
+
+	fman0_oh_0x5: port@85000 {
+		cell-index = <0x5>;
+		compatible = "fsl,fman-v2-port-oh";
+		reg = <0x85000 0x1000>;
+		status = "disabled";
+	};
+
+	fman0_oh_0x6: port@86000 {
+		cell-index = <0x6>;
+		compatible = "fsl,fman-v2-port-oh";
+		reg = <0x86000 0x1000>;
+		status = "disabled";
+	};
+
+	fman0_oh_0x7: port@87000 {
+		cell-index = <0x7>;
+		compatible = "fsl,fman-v2-port-oh";
+		reg = <0x87000 0x1000>;
+		status = "disabled";
+	};
+};
+
+ptp_timer0: ptp-timer@4fe000 {
+	compatible = "fsl,fman-ptp-timer";
+	reg = <0x4fe000 0x1000>;
+	interrupts = <96 2 0 0>;
+	clocks = <&clockgen 3 0>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman-1-10g-0.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman-1-10g-0.dtsi
new file mode 100644
index 000000000..d29399011
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman-1-10g-0.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan 10g port #0 device tree stub [ controller @ offset 0x500000 ]
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@500000 {
+	fman1_rx_0x10: port@90000 {
+		cell-index = <0x10>;
+		compatible = "fsl,fman-v2-port-rx";
+		reg = <0x90000 0x1000>;
+	};
+
+	fman1_tx_0x30: port@b0000 {
+		cell-index = <0x30>;
+		compatible = "fsl,fman-v2-port-tx";
+		reg = <0xb0000 0x1000>;
+	};
+
+	ethernet@f0000 {
+		cell-index = <0x8>;
+		compatible = "fsl,fman-xgec";
+		reg = <0xf0000 0x1000>;
+		fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
+	};
+
+	mdio@f1000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-xmdio";
+		reg = <0xf1000 0x1000>;
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman-1-1g-0.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman-1-1g-0.dtsi
new file mode 100644
index 000000000..1eb6bbf36
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman-1-1g-0.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan 1g port #0 device tree stub [ controller @ offset 0x500000 ]
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@500000 {
+	fman1_rx_0x08: port@88000 {
+		cell-index = <0x8>;
+		compatible = "fsl,fman-v2-port-rx";
+		reg = <0x88000 0x1000>;
+	};
+
+	fman1_tx_0x28: port@a8000 {
+		cell-index = <0x28>;
+		compatible = "fsl,fman-v2-port-tx";
+		reg = <0xa8000 0x1000>;
+	};
+
+	ethernet@e0000 {
+		cell-index = <0>;
+		compatible = "fsl,fman-dtsec";
+		reg = <0xe0000 0x1000>;
+		fsl,fman-ports = <&fman1_rx_0x08 &fman1_tx_0x28>;
+		tbi-handle = <&tbi5>;
+		ptp-timer = <&ptp_timer1>;
+	};
+
+	mdio@e1120 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-mdio";
+		reg = <0xe1120 0xee0>;
+
+		tbi5: tbi-phy@8 {
+			reg = <0x8>;
+			device_type = "tbi-phy";
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman-1-1g-1.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman-1-1g-1.dtsi
new file mode 100644
index 000000000..5ad1b6fb9
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman-1-1g-1.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan 1g port #1 device tree stub [ controller @ offset 0x500000 ]
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@500000 {
+	fman1_rx_0x09: port@89000 {
+		cell-index = <0x9>;
+		compatible = "fsl,fman-v2-port-rx";
+		reg = <0x89000 0x1000>;
+	};
+
+	fman1_tx_0x29: port@a9000 {
+		cell-index = <0x29>;
+		compatible = "fsl,fman-v2-port-tx";
+		reg = <0xa9000 0x1000>;
+	};
+
+	ethernet@e2000 {
+		cell-index = <1>;
+		compatible = "fsl,fman-dtsec";
+		reg = <0xe2000 0x1000>;
+		fsl,fman-ports = <&fman1_rx_0x09 &fman1_tx_0x29>;
+		tbi-handle = <&tbi6>;
+		ptp-timer = <&ptp_timer1>;
+	};
+
+	mdio@e3120 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-mdio";
+		reg = <0xe3120 0xee0>;
+
+		tbi6: tbi-phy@8 {
+			reg = <0x8>;
+			device_type = "tbi-phy";
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman-1-1g-2.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman-1-1g-2.dtsi
new file mode 100644
index 000000000..0d7ee5417
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman-1-1g-2.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan 1g port #2 device tree stub [ controller @ offset 0x500000 ]
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@500000 {
+	fman1_rx_0x0a: port@8a000 {
+		cell-index = <0xa>;
+		compatible = "fsl,fman-v2-port-rx";
+		reg = <0x8a000 0x1000>;
+	};
+
+	fman1_tx_0x2a: port@aa000 {
+		cell-index = <0x2a>;
+		compatible = "fsl,fman-v2-port-tx";
+		reg = <0xaa000 0x1000>;
+	};
+
+	ethernet@e4000 {
+		cell-index = <2>;
+		compatible = "fsl,fman-dtsec";
+		reg = <0xe4000 0x1000>;
+		fsl,fman-ports = <&fman1_rx_0x0a &fman1_tx_0x2a>;
+		tbi-handle = <&tbi7>;
+		ptp-timer = <&ptp_timer1>;
+	};
+
+	mdio@e5120 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-mdio";
+		reg = <0xe5120 0xee0>;
+
+		tbi7: tbi-phy@8 {
+			reg = <0x8>;
+			device_type = "tbi-phy";
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman-1-1g-3.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman-1-1g-3.dtsi
new file mode 100644
index 000000000..06a8c08e1
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman-1-1g-3.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan 1g port #3 device tree stub [ controller @ offset 0x500000 ]
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@500000 {
+	fman1_rx_0x0b: port@8b000 {
+		cell-index = <0xb>;
+		compatible = "fsl,fman-v2-port-rx";
+		reg = <0x8b000 0x1000>;
+	};
+
+	fman1_tx_0x2b: port@ab000 {
+		cell-index = <0x2b>;
+		compatible = "fsl,fman-v2-port-tx";
+		reg = <0xab000 0x1000>;
+	};
+
+	ethernet@e6000 {
+		cell-index = <3>;
+		compatible = "fsl,fman-dtsec";
+		reg = <0xe6000 0x1000>;
+		fsl,fman-ports = <&fman1_rx_0x0b &fman1_tx_0x2b>;
+		tbi-handle = <&tbi8>;
+		ptp-timer = <&ptp_timer1>;
+	};
+
+	mdio@e7120 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-mdio";
+		reg = <0xe7120 0xee0>;
+
+		tbi8: tbi-phy@8 {
+			reg = <0x8>;
+			device_type = "tbi-phy";
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman-1-1g-4.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman-1-1g-4.dtsi
new file mode 100644
index 000000000..f64dc2a3c
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman-1-1g-4.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan 1g port #4 device tree stub [ controller @ offset 0x500000 ]
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@500000 {
+	fman1_rx_0x0c: port@8c000 {
+		cell-index = <0xc>;
+		compatible = "fsl,fman-v2-port-rx";
+		reg = <0x8c000 0x1000>;
+	};
+
+	fman1_tx_0x2c: port@ac000 {
+		cell-index = <0x2c>;
+		compatible = "fsl,fman-v2-port-tx";
+		reg = <0xac000 0x1000>;
+	};
+
+	ethernet@e8000 {
+		cell-index = <4>;
+		compatible = "fsl,fman-dtsec";
+		reg = <0xe8000 0x1000>;
+		fsl,fman-ports = <&fman1_rx_0x0c &fman1_tx_0x2c>;
+		tbi-handle = <&tbi9>;
+		ptp-timer = <&ptp_timer1>;
+	};
+
+	mdio@e9120 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-mdio";
+		reg = <0xe9120 0xee0>;
+
+		tbi9: tbi-phy@8 {
+			reg = <0x8>;
+			device_type = "tbi-phy";
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman-1.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman-1.dtsi
new file mode 100644
index 000000000..1166f3fcd
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman-1.dtsi
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan device tree stub [ controller @ offset 0x500000 ]
+ *
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman1: fman@500000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	cell-index = <1>;
+	compatible = "fsl,fman";
+	ranges = <0 0x500000 0xfe000>;
+	reg = <0x500000 0xfe000>;
+	interrupts = <97 2 0 0>, <16 2 1 0>;
+	clocks = <&clockgen 3 1>;
+	clock-names = "fmanclk";
+	fsl,qman-channel-range = <0x60 0xc>;
+	ptimer-handle = <&ptp_timer1>;
+
+	muram@0 {
+		compatible = "fsl,fman-muram";
+		reg = <0x0 0x28000>;
+	};
+
+	fman1_oh_0x1: port@81000 {
+		cell-index = <0x1>;
+		compatible = "fsl,fman-v2-port-oh";
+		reg = <0x81000 0x1000>;
+	};
+
+	fman1_oh_0x2: port@82000 {
+		cell-index = <0x2>;
+		compatible = "fsl,fman-v2-port-oh";
+		reg = <0x82000 0x1000>;
+	};
+
+	fman1_oh_0x3: port@83000 {
+		cell-index = <0x3>;
+		compatible = "fsl,fman-v2-port-oh";
+		reg = <0x83000 0x1000>;
+	};
+
+	fman1_oh_0x4: port@84000 {
+		cell-index = <0x4>;
+		compatible = "fsl,fman-v2-port-oh";
+		reg = <0x84000 0x1000>;
+	};
+
+	fman1_oh_0x5: port@85000 {
+		cell-index = <0x5>;
+		compatible = "fsl,fman-v2-port-oh";
+		reg = <0x85000 0x1000>;
+		status = "disabled";
+	};
+
+	fman1_oh_0x6: port@86000 {
+		cell-index = <0x6>;
+		compatible = "fsl,fman-v2-port-oh";
+		reg = <0x86000 0x1000>;
+		status = "disabled";
+	};
+
+	fman1_oh_0x7: port@87000 {
+		cell-index = <0x7>;
+		compatible = "fsl,fman-v2-port-oh";
+		reg = <0x87000 0x1000>;
+		status = "disabled";
+	};
+};
+
+ptp_timer1: ptp-timer@5fe000 {
+	compatible = "fsl,fman-ptp-timer";
+	reg = <0x5fe000 0x1000>;
+	interrupts = <97 2 0 0>;
+	clocks = <&clockgen 3 1>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-10g-0-best-effort.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-10g-0-best-effort.dtsi
new file mode 100644
index 000000000..e2c3da0e5
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-10g-0-best-effort.dtsi
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #0 device tree stub [ controller @ offset 0x400000 ]
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@400000 {
+	fman0_rx_0x08: port@88000 {
+		cell-index = <0x8>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x88000 0x1000>;
+		fsl,fman-10g-port;
+		fsl,fman-best-effort-port;
+	};
+
+	fman0_tx_0x28: port@a8000 {
+		cell-index = <0x28>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xa8000 0x1000>;
+		fsl,fman-10g-port;
+		fsl,fman-best-effort-port;
+	};
+
+	ethernet@e0000 {
+		cell-index = <0>;
+		compatible = "fsl,fman-memac";
+		reg = <0xe0000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
+		ptp-timer = <&ptp_timer0>;
+		pcsphy-handle = <&pcsphy0>;
+	};
+
+	mdio@e1000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xe1000 0x1000>;
+		fsl,erratum-a011043; /* must ignore read errors */
+
+		pcsphy0: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-10g-0.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-10g-0.dtsi
new file mode 100644
index 000000000..0ac313342
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-10g-0.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 10g port #0 device tree stub [ controller @ offset 0x400000 ]
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@400000 {
+	fman0_rx_0x10: port@90000 {
+		cell-index = <0x10>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x90000 0x1000>;
+		fsl,fman-10g-port;
+	};
+
+	fman0_tx_0x30: port@b0000 {
+		cell-index = <0x30>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xb0000 0x1000>;
+		fsl,fman-10g-port;
+	};
+
+	ethernet@f0000 {
+		cell-index = <0x8>;
+		compatible = "fsl,fman-memac";
+		reg = <0xf0000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>;
+		pcsphy-handle = <&pcsphy6>;
+	};
+
+	mdio@f1000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xf1000 0x1000>;
+		fsl,erratum-a011043; /* must ignore read errors */
+
+		pcsphy6: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-10g-1-best-effort.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-10g-1-best-effort.dtsi
new file mode 100644
index 000000000..142c696c3
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-10g-1-best-effort.dtsi
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #1 device tree stub [ controller @ offset 0x400000 ]
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@400000 {
+	fman0_rx_0x09: port@89000 {
+		cell-index = <0x9>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x89000 0x1000>;
+		fsl,fman-10g-port;
+		fsl,fman-best-effort-port;
+	};
+
+	fman0_tx_0x29: port@a9000 {
+		cell-index = <0x29>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xa9000 0x1000>;
+		fsl,fman-10g-port;
+		fsl,fman-best-effort-port;
+	};
+
+	ethernet@e2000 {
+		cell-index = <1>;
+		compatible = "fsl,fman-memac";
+		reg = <0xe2000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
+		ptp-timer = <&ptp_timer0>;
+		pcsphy-handle = <&pcsphy1>;
+	};
+
+	mdio@e3000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xe3000 0x1000>;
+		fsl,erratum-a011043; /* must ignore read errors */
+
+		pcsphy1: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-10g-1.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-10g-1.dtsi
new file mode 100644
index 000000000..b04af6437
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-10g-1.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x400000 ]
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@400000 {
+	fman0_rx_0x11: port@91000 {
+		cell-index = <0x11>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x91000 0x1000>;
+		fsl,fman-10g-port;
+	};
+
+	fman0_tx_0x31: port@b1000 {
+		cell-index = <0x31>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xb1000 0x1000>;
+		fsl,fman-10g-port;
+	};
+
+	ethernet@f2000 {
+		cell-index = <0x9>;
+		compatible = "fsl,fman-memac";
+		reg = <0xf2000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>;
+		pcsphy-handle = <&pcsphy7>;
+	};
+
+	mdio@f3000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xf3000 0x1000>;
+		fsl,erratum-a011043; /* must ignore read errors */
+
+		pcsphy7: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-1g-0.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-1g-0.dtsi
new file mode 100644
index 000000000..a9297c4e9
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-1g-0.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #0 device tree stub [ controller @ offset 0x400000 ]
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@400000 {
+	fman0_rx_0x08: port@88000 {
+		cell-index = <0x8>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x88000 0x1000>;
+	};
+
+	fman0_tx_0x28: port@a8000 {
+		cell-index = <0x28>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xa8000 0x1000>;
+	};
+
+	ethernet@e0000 {
+		cell-index = <0>;
+		compatible = "fsl,fman-memac";
+		reg = <0xe0000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
+		ptp-timer = <&ptp_timer0>;
+		pcsphy-handle = <&pcsphy0>;
+	};
+
+	mdio@e1000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xe1000 0x1000>;
+		fsl,erratum-a011043; /* must ignore read errors */
+
+		pcsphy0: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-1g-1.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-1g-1.dtsi
new file mode 100644
index 000000000..9cc210396
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-1g-1.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #1 device tree stub [ controller @ offset 0x400000 ]
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@400000 {
+	fman0_rx_0x09: port@89000 {
+		cell-index = <0x9>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x89000 0x1000>;
+	};
+
+	fman0_tx_0x29: port@a9000 {
+		cell-index = <0x29>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xa9000 0x1000>;
+	};
+
+	ethernet@e2000 {
+		cell-index = <1>;
+		compatible = "fsl,fman-memac";
+		reg = <0xe2000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
+		ptp-timer = <&ptp_timer0>;
+		pcsphy-handle = <&pcsphy1>;
+	};
+
+	mdio@e3000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xe3000 0x1000>;
+		fsl,erratum-a011043; /* must ignore read errors */
+
+		pcsphy1: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-1g-2.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-1g-2.dtsi
new file mode 100644
index 000000000..86f94dde8
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-1g-2.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #2 device tree stub [ controller @ offset 0x400000 ]
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@400000 {
+	fman0_rx_0x0a: port@8a000 {
+		cell-index = <0xa>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x8a000 0x1000>;
+	};
+
+	fman0_tx_0x2a: port@aa000 {
+		cell-index = <0x2a>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xaa000 0x1000>;
+	};
+
+	ethernet@e4000 {
+		cell-index = <2>;
+		compatible = "fsl,fman-memac";
+		reg = <0xe4000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
+		ptp-timer = <&ptp_timer0>;
+		pcsphy-handle = <&pcsphy2>;
+	};
+
+	mdio@e5000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xe5000 0x1000>;
+		fsl,erratum-a011043; /* must ignore read errors */
+
+		pcsphy2: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-1g-3.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-1g-3.dtsi
new file mode 100644
index 000000000..d59e625ad
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-1g-3.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #3 device tree stub [ controller @ offset 0x400000 ]
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@400000 {
+	fman0_rx_0x0b: port@8b000 {
+		cell-index = <0xb>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x8b000 0x1000>;
+	};
+
+	fman0_tx_0x2b: port@ab000 {
+		cell-index = <0x2b>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xab000 0x1000>;
+	};
+
+	ethernet@e6000 {
+		cell-index = <3>;
+		compatible = "fsl,fman-memac";
+		reg = <0xe6000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
+		ptp-timer = <&ptp_timer0>;
+		pcsphy-handle = <&pcsphy3>;
+	};
+
+	mdio@e7000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xe7000 0x1000>;
+		fsl,erratum-a011043; /* must ignore read errors */
+
+		pcsphy3: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-1g-4.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-1g-4.dtsi
new file mode 100644
index 000000000..4878736aa
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-1g-4.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #4 device tree stub [ controller @ offset 0x400000 ]
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@400000 {
+	fman0_rx_0x0c: port@8c000 {
+		cell-index = <0xc>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x8c000 0x1000>;
+	};
+
+	fman0_tx_0x2c: port@ac000 {
+		cell-index = <0x2c>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xac000 0x1000>;
+	};
+
+	ethernet@e8000 {
+		cell-index = <4>;
+		compatible = "fsl,fman-memac";
+		reg = <0xe8000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
+		ptp-timer = <&ptp_timer0>;
+		pcsphy-handle = <&pcsphy4>;
+	};
+
+	mdio@e9000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xe9000 0x1000>;
+		fsl,erratum-a011043; /* must ignore read errors */
+
+		pcsphy4: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-1g-5.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-1g-5.dtsi
new file mode 100644
index 000000000..989328cc3
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0-1g-5.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #5 device tree stub [ controller @ offset 0x400000 ]
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@400000 {
+	fman0_rx_0x0d: port@8d000 {
+		cell-index = <0xd>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x8d000 0x1000>;
+	};
+
+	fman0_tx_0x2d: port@ad000 {
+		cell-index = <0x2d>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xad000 0x1000>;
+	};
+
+	ethernet@ea000 {
+		cell-index = <5>;
+		compatible = "fsl,fman-memac";
+		reg = <0xea000 0x1000>;
+		fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>;
+		ptp-timer = <&ptp_timer0>;
+		pcsphy-handle = <&pcsphy5>;
+	};
+
+	mdio@eb000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xeb000 0x1000>;
+		fsl,erratum-a011043; /* must ignore read errors */
+
+		pcsphy5: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0.dtsi
new file mode 100644
index 000000000..d9098f72a
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-0.dtsi
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 device tree stub [ controller @ offset 0x400000 ]
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman0: fman@400000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	cell-index = <0>;
+	compatible = "fsl,fman";
+	ranges = <0 0x400000 0xfe000>;
+	reg = <0x400000 0xfe000>;
+	interrupts = <96 2 0 0>, <16 2 1 1>;
+	clocks = <&clockgen 3 0>;
+	clock-names = "fmanclk";
+	fsl,qman-channel-range = <0x800 0x10>;
+	ptimer-handle = <&ptp_timer0>;
+
+	muram@0 {
+		compatible = "fsl,fman-muram";
+		reg = <0x0 0x60000>;
+	};
+
+	fman0_oh_0x2: port@82000 {
+		cell-index = <0x2>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x82000 0x1000>;
+	};
+
+	fman0_oh_0x3: port@83000 {
+		cell-index = <0x3>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x83000 0x1000>;
+	};
+
+	fman0_oh_0x4: port@84000 {
+		cell-index = <0x4>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x84000 0x1000>;
+	};
+
+	fman0_oh_0x5: port@85000 {
+		cell-index = <0x5>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x85000 0x1000>;
+	};
+
+	fman0_oh_0x6: port@86000 {
+		cell-index = <0x6>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x86000 0x1000>;
+	};
+
+	fman0_oh_0x7: port@87000 {
+		cell-index = <0x7>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x87000 0x1000>;
+	};
+
+	mdio0: mdio@fc000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xfc000 0x1000>;
+	};
+
+	xmdio0: mdio@fd000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xfd000 0x1000>;
+	};
+};
+
+ptp_timer0: ptp-timer@4fe000 {
+	compatible = "fsl,fman-ptp-timer";
+	reg = <0x4fe000 0x1000>;
+	interrupts = <96 2 0 0>;
+	clocks = <&clockgen 3 0>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1-10g-0.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1-10g-0.dtsi
new file mode 100644
index 000000000..65bb8a4b0
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1-10g-0.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 10g port #0 device tree stub [ controller @ offset 0x500000 ]
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@500000 {
+	fman1_rx_0x10: port@90000 {
+		cell-index = <0x10>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x90000 0x1000>;
+		fsl,fman-10g-port;
+	};
+
+	fman1_tx_0x30: port@b0000 {
+		cell-index = <0x30>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xb0000 0x1000>;
+		fsl,fman-10g-port;
+	};
+
+	ethernet@f0000 {
+		cell-index = <0x8>;
+		compatible = "fsl,fman-memac";
+		reg = <0xf0000 0x1000>;
+		fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
+		pcsphy-handle = <&pcsphy14>;
+	};
+
+	mdio@5f1000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xf1000 0x1000>;
+		fsl,erratum-a011043; /* must ignore read errors */
+
+		pcsphy14: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1-10g-1.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1-10g-1.dtsi
new file mode 100644
index 000000000..eb39d29b3
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1-10g-1.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x500000 ]
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@500000 {
+	fman1_rx_0x11: port@91000 {
+		cell-index = <0x11>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x91000 0x1000>;
+		fsl,fman-10g-port;
+	};
+
+	fman1_tx_0x31: port@b1000 {
+		cell-index = <0x31>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xb1000 0x1000>;
+		fsl,fman-10g-port;
+	};
+
+	ethernet@f2000 {
+		cell-index = <0x9>;
+		compatible = "fsl,fman-memac";
+		reg = <0xf2000 0x1000>;
+		fsl,fman-ports = <&fman1_rx_0x11 &fman1_tx_0x31>;
+		pcsphy-handle = <&pcsphy15>;
+	};
+
+	mdio@5f3000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xf3000 0x1000>;
+		fsl,erratum-a011043; /* must ignore read errors */
+
+		pcsphy15: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1-1g-0.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1-1g-0.dtsi
new file mode 100644
index 000000000..2f2209dbc
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1-1g-0.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #0 device tree stub [ controller @ offset 0x500000 ]
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@500000 {
+	fman1_rx_0x08: port@88000 {
+		cell-index = <0x8>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x88000 0x1000>;
+	};
+
+	fman1_tx_0x28: port@a8000 {
+		cell-index = <0x28>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xa8000 0x1000>;
+	};
+
+	ethernet@e0000 {
+		cell-index = <0>;
+		compatible = "fsl,fman-memac";
+		reg = <0xe0000 0x1000>;
+		fsl,fman-ports = <&fman1_rx_0x08 &fman1_tx_0x28>;
+		ptp-timer = <&ptp_timer1>;
+		pcsphy-handle = <&pcsphy8>;
+	};
+
+	mdio@5e1000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xe1000 0x1000>;
+		fsl,erratum-a011043; /* must ignore read errors */
+
+		pcsphy8: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi
new file mode 100644
index 000000000..11653c58b
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #1 device tree stub [ controller @ offset 0x500000 ]
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@500000 {
+	fman1_rx_0x09: port@89000 {
+		cell-index = <0x9>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x89000 0x1000>;
+	};
+
+	fman1_tx_0x29: port@a9000 {
+		cell-index = <0x29>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xa9000 0x1000>;
+	};
+
+	ethernet@e2000 {
+		cell-index = <1>;
+		compatible = "fsl,fman-memac";
+		reg = <0xe2000 0x1000>;
+		fsl,fman-ports = <&fman1_rx_0x09 &fman1_tx_0x29>;
+		ptp-timer = <&ptp_timer1>;
+		pcsphy-handle = <&pcsphy9>;
+	};
+
+	mdio@5e3000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xe3000 0x1000>;
+		fsl,erratum-a011043; /* must ignore read errors */
+
+		pcsphy9: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1-1g-2.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1-1g-2.dtsi
new file mode 100644
index 000000000..ae27c7bc6
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1-1g-2.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #2 device tree stub [ controller @ offset 0x500000 ]
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@500000 {
+	fman1_rx_0x0a: port@8a000 {
+		cell-index = <0xa>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x8a000 0x1000>;
+	};
+
+	fman1_tx_0x2a: port@aa000 {
+		cell-index = <0x2a>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xaa000 0x1000>;
+	};
+
+	ethernet@e4000 {
+		cell-index = <2>;
+		compatible = "fsl,fman-memac";
+		reg = <0xe4000 0x1000>;
+		fsl,fman-ports = <&fman1_rx_0x0a &fman1_tx_0x2a>;
+		ptp-timer = <&ptp_timer1>;
+		pcsphy-handle = <&pcsphy10>;
+	};
+
+	mdio@5e5000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xe5000 0x1000>;
+		fsl,erratum-a011043; /* must ignore read errors */
+
+		pcsphy10: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1-1g-3.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1-1g-3.dtsi
new file mode 100644
index 000000000..55ae54991
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1-1g-3.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #3 device tree stub [ controller @ offset 0x500000 ]
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@500000 {
+	fman1_rx_0x0b: port@8b000 {
+		cell-index = <0xb>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x8b000 0x1000>;
+	};
+
+	fman1_tx_0x2b: port@ab000 {
+		cell-index = <0x2b>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xab000 0x1000>;
+	};
+
+	ethernet@e6000 {
+		cell-index = <3>;
+		compatible = "fsl,fman-memac";
+		reg = <0xe6000 0x1000>;
+		fsl,fman-ports = <&fman1_rx_0x0b &fman1_tx_0x2b>;
+		ptp-timer = <&ptp_timer1>;
+		pcsphy-handle = <&pcsphy11>;
+	};
+
+	mdio@5e7000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xe7000 0x1000>;
+		fsl,erratum-a011043; /* must ignore read errors */
+
+		pcsphy11: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1-1g-4.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1-1g-4.dtsi
new file mode 100644
index 000000000..833cf3e23
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1-1g-4.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #4 device tree stub [ controller @ offset 0x500000 ]
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@500000 {
+	fman1_rx_0x0c: port@8c000 {
+		cell-index = <0xc>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x8c000 0x1000>;
+	};
+
+	fman1_tx_0x2c: port@ac000 {
+		cell-index = <0x2c>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xac000 0x1000>;
+	};
+
+	ethernet@e8000 {
+		cell-index = <4>;
+		compatible = "fsl,fman-memac";
+		reg = <0xe8000 0x1000>;
+		fsl,fman-ports = <&fman1_rx_0x0c &fman1_tx_0x2c>;
+		ptp-timer = <&ptp_timer1>;
+		pcsphy-handle = <&pcsphy12>;
+	};
+
+	mdio@5e9000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xe9000 0x1000>;
+		fsl,erratum-a011043; /* must ignore read errors */
+
+		pcsphy12: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1-1g-5.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1-1g-5.dtsi
new file mode 100644
index 000000000..81da55dfb
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1-1g-5.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 1g port #5 device tree stub [ controller @ offset 0x500000 ]
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman@500000 {
+	fman1_rx_0x0d: port@8d000 {
+		cell-index = <0xd>;
+		compatible = "fsl,fman-v3-port-rx";
+		reg = <0x8d000 0x1000>;
+	};
+
+	fman1_tx_0x2d: port@ad000 {
+		cell-index = <0x2d>;
+		compatible = "fsl,fman-v3-port-tx";
+		reg = <0xad000 0x1000>;
+	};
+
+	ethernet@ea000 {
+		cell-index = <5>;
+		compatible = "fsl,fman-memac";
+		reg = <0xea000 0x1000>;
+		fsl,fman-ports = <&fman1_rx_0x0d &fman1_tx_0x2d>;
+		ptp-timer = <&ptp_timer1>;
+		pcsphy-handle = <&pcsphy13>;
+	};
+
+	mdio@5eb000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xeb000 0x1000>;
+		fsl,erratum-a011043; /* must ignore read errors */
+
+		pcsphy13: ethernet-phy@0 {
+			reg = <0x0>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1.dtsi
new file mode 100644
index 000000000..9efcf26c4
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman3-1.dtsi
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 device tree stub [ controller @ offset 0x500000 ]
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman1: fman@500000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	cell-index = <1>;
+	compatible = "fsl,fman";
+	ranges = <0 0x500000 0xfe000>;
+	reg = <0x500000 0xfe000>;
+	interrupts = <97 2 0 0>, <16 2 1 0>;
+	clocks = <&clockgen 3 1>;
+	clock-names = "fmanclk";
+	fsl,qman-channel-range = <0x820 0x10>;
+	ptimer-handle = <&ptp_timer1>;
+
+	muram@0 {
+		compatible = "fsl,fman-muram";
+		reg = <0x0 0x60000>;
+	};
+
+	fman1_oh_0x2: port@82000 {
+		cell-index = <0x2>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x82000 0x1000>;
+	};
+
+	fman1_oh_0x3: port@83000 {
+		cell-index = <0x3>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x83000 0x1000>;
+	};
+
+	fman1_oh_0x4: port@84000 {
+		cell-index = <0x4>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x84000 0x1000>;
+	};
+
+	fman1_oh_0x5: port@85000 {
+		cell-index = <0x5>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x85000 0x1000>;
+	};
+
+	fman1_oh_0x6: port@86000 {
+		cell-index = <0x6>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x86000 0x1000>;
+	};
+
+	fman1_oh_0x7: port@87000 {
+		cell-index = <0x7>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x87000 0x1000>;
+	};
+
+	mdio1: mdio@5fc000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xfc000 0x1000>;
+	};
+
+	mdio@5fd000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xfd000 0x1000>;
+	};
+};
+
+ptp_timer1: ptp-timer@5fe000 {
+	compatible = "fsl,fman-ptp-timer";
+	reg = <0x5fe000 0x1000>;
+	interrupts = <97 2 0 0>;
+	clocks = <&clockgen 3 1>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-fman3l-0.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-fman3l-0.dtsi
new file mode 100644
index 000000000..84cc9a1f6
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-fman3l-0.dtsi
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ FMan v3 device tree stub [ controller @ offset 0x400000 ]
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+fman0: fman@400000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	cell-index = <0>;
+	compatible = "fsl,fman";
+	ranges = <0 0x400000 0xfe000>;
+	reg = <0x400000 0xfe000>;
+	interrupts = <96 2 0 0>, <16 2 1 1>;
+	clocks = <&clockgen 3 0>;
+	clock-names = "fmanclk";
+	fsl,qman-channel-range = <0x800 0x10>;
+	ptimer-handle = <&ptp_timer0>;
+
+	muram@0 {
+		compatible = "fsl,fman-muram";
+		reg = <0x0 0x30000>;
+	};
+
+	fman0_oh_0x2: port@82000 {
+		cell-index = <0x2>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x82000 0x1000>;
+	};
+
+	fman0_oh_0x3: port@83000 {
+		cell-index = <0x3>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x83000 0x1000>;
+	};
+
+	fman0_oh_0x4: port@84000 {
+		cell-index = <0x4>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x84000 0x1000>;
+	};
+
+	fman0_oh_0x5: port@85000 {
+		cell-index = <0x5>;
+		compatible = "fsl,fman-v3-port-oh";
+		reg = <0x85000 0x1000>;
+	};
+
+	mdio0: mdio@fc000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xfc000 0x1000>;
+	};
+
+	xmdio0: mdio@fd000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+		reg = <0xfd000 0x1000>;
+	};
+};
+
+ptp_timer0: ptp-timer@4fe000 {
+	compatible = "fsl,fman-ptp-timer";
+	reg = <0x4fe000 0x1000>;
+	interrupts = <96 2 0 0>;
+	clocks = <&clockgen 3 0>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-gpio-0.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-gpio-0.dtsi
new file mode 100644
index 000000000..417fd2bdd
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-gpio-0.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ GPIO device tree stub [ controller @ offset 0x130000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+gpio0: gpio@130000 {
+	compatible = "fsl,qoriq-gpio";
+	reg = <0x130000 0x1000>;
+	interrupts = <55 2 0 0>;
+	#gpio-cells = <2>;
+	gpio-controller;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-gpio-1.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-gpio-1.dtsi
new file mode 100644
index 000000000..237f49e60
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-gpio-1.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ GPIO device tree stub [ controller @ offset 0x131000 ]
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+gpio1: gpio@131000 {
+	compatible = "fsl,qoriq-gpio";
+	reg = <0x131000 0x1000>;
+	interrupts = <54 2 0 0>;
+	#gpio-cells = <2>;
+	gpio-controller;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-gpio-2.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-gpio-2.dtsi
new file mode 100644
index 000000000..d3ee2aed6
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-gpio-2.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ GPIO device tree stub [ controller @ offset 0x132000 ]
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+gpio2: gpio@132000 {
+	compatible = "fsl,qoriq-gpio";
+	reg = <0x132000 0x1000>;
+	interrupts = <86 2 0 0>;
+	#gpio-cells = <2>;
+	gpio-controller;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-gpio-3.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-gpio-3.dtsi
new file mode 100644
index 000000000..3d766f266
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-gpio-3.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * QorIQ GPIO device tree stub [ controller @ offset 0x133000 ]
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ *
+ */
+
+gpio3: gpio@133000 {
+	compatible = "fsl,qoriq-gpio";
+	reg = <0x133000 0x1000>;
+	interrupts = <87 2 0 0>;
+	#gpio-cells = <2>;
+	gpio-controller;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-i2c-0.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-i2c-0.dtsi
new file mode 100644
index 000000000..9d0ab886e
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-i2c-0.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * QorIQ I2C Device Tree stub
+ *
+ * Copyright 2020 NXP
+ */
+i2c0: i2c@118000 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	cell-index = <0>;
+	compatible = "fsl-i2c";
+	u-boot,dm-pre-reloc;
+	reg = <0x118000 0x100>;
+	interrupts = <38 2 0 0>;
+};
+
+i2c1: i2c@118100 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	cell-index = <1>;
+	compatible = "fsl-i2c";
+	u-boot,dm-pre-reloc;
+	reg = <0x118100 0x100>;
+	interrupts = <38 2 0 0>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-i2c-1.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-i2c-1.dtsi
new file mode 100644
index 000000000..de0a22e3e
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-i2c-1.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * QorIQ I2C Device Tree stub
+ *
+ * Copyright 2020 NXP
+ */
+i2c2: i2c@119000 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	cell-index = <2>;
+	compatible = "fsl-i2c";
+	u-boot,dm-pre-reloc;
+	reg = <0x119000 0x100>;
+	interrupts = <39 2 0 0>;
+};
+
+i2c3: i2c@119100 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	cell-index = <3>;
+	compatible = "fsl-i2c";
+	u-boot,dm-pre-reloc;
+	reg = <0x119100 0x100>;
+	interrupts = <39 2 0 0>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-mpic.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-mpic.dtsi
new file mode 100644
index 000000000..bec7c04e6
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-mpic.dtsi
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+mpic: pic@40000 {
+	interrupt-controller;
+	#address-cells = <0>;
+	#interrupt-cells = <4>;
+	reg = <0x40000 0x40000>;
+	compatible = "fsl,mpic", "chrp,open-pic";
+	device_type = "open-pic";
+	clock-frequency = <0x0>;
+};
+
+timer@41100 {
+	compatible = "fsl,mpic-global-timer";
+	reg = <0x41100 0x100 0x41300 4>;
+	interrupts = <0 0 3 0
+		      1 0 3 0
+		      2 0 3 0
+		      3 0 3 0>;
+};
+
+msi0: msi@41600 {
+	compatible = "fsl,mpic-msi";
+	reg = <0x41600 0x200 0x44140 4>;
+	msi-available-ranges = <0 0x100>;
+	interrupts = <
+		0xe0 0 0 0
+		0xe1 0 0 0
+		0xe2 0 0 0
+		0xe3 0 0 0
+		0xe4 0 0 0
+		0xe5 0 0 0
+		0xe6 0 0 0
+		0xe7 0 0 0>;
+};
+
+msi1: msi@41800 {
+	compatible = "fsl,mpic-msi";
+	reg = <0x41800 0x200 0x45140 4>;
+	msi-available-ranges = <0 0x100>;
+	interrupts = <
+		0xe8 0 0 0
+		0xe9 0 0 0
+		0xea 0 0 0
+		0xeb 0 0 0
+		0xec 0 0 0
+		0xed 0 0 0
+		0xee 0 0 0
+		0xef 0 0 0>;
+};
+
+msi2: msi@41a00 {
+	compatible = "fsl,mpic-msi";
+	reg = <0x41a00 0x200 0x46140 4>;
+	msi-available-ranges = <0 0x100>;
+	interrupts = <
+		0xf0 0 0 0
+		0xf1 0 0 0
+		0xf2 0 0 0
+		0xf3 0 0 0
+		0xf4 0 0 0
+		0xf5 0 0 0
+		0xf6 0 0 0
+		0xf7 0 0 0>;
+};
+
+timer@42100 {
+	compatible = "fsl,mpic-global-timer";
+	reg = <0x42100 0x100 0x42300 4>;
+	interrupts = <4 0 3 0
+		      5 0 3 0
+		      6 0 3 0
+		      7 0 3 0>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-qman3.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-qman3.dtsi
new file mode 100644
index 000000000..b1f8a777a
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-qman3.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ QMan rev3 device tree stub [ controller @ offset 0x318000 ]
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ */
+
+qman: qman@318000 {
+	compatible = "fsl,qman";
+	reg = <0x318000 0x2000>;
+	interrupts = <16 2 1 3>;
+	fsl,qman-portals = <&qportals>;
+	memory-region = <&qman_fqd &qman_pfdr>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-sata2-0.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-sata2-0.dtsi
new file mode 100644
index 000000000..385b91784
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-sata2-0.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ SATAv2 device tree stub [ controller @ offset 0x220000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+sata@220000 {
+	compatible = "fsl,pq-sata-v2";
+	reg = <0x220000 0x1000>;
+	interrupts = <68 0x2 0 0>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-sata2-1.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-sata2-1.dtsi
new file mode 100644
index 000000000..d72dd39e0
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-sata2-1.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ SATAv2 device tree stub [ controller @ offset 0x221000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+sata@221000 {
+	compatible = "fsl,pq-sata-v2";
+	reg = <0x221000 0x1000>;
+	interrupts = <69 0x2 0 0>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-sec5.0-0.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-sec5.0-0.dtsi
new file mode 100644
index 000000000..af0bb9dd6
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-sec5.0-0.dtsi
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ Sec/Crypto 5.0 device tree stub [ controller @ offset 0x300000 ]
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ */
+
+crypto: crypto@300000 {
+	compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+	fsl,sec-era = <5>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+	reg		 = <0x300000 0x10000>;
+	ranges		 = <0 0x300000 0x10000>;
+	interrupts	 = <92 2 0 0>;
+
+	sec_jr0: jr@1000 {
+		compatible = "fsl,sec-v5.0-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg = <0x1000 0x1000>;
+		interrupts = <88 2 0 0>;
+	};
+
+	sec_jr1: jr@2000 {
+		compatible = "fsl,sec-v5.0-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg = <0x2000 0x1000>;
+		interrupts = <89 2 0 0>;
+	};
+
+	sec_jr2: jr@3000 {
+		compatible = "fsl,sec-v5.0-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg = <0x3000 0x1000>;
+		interrupts = <90 2 0 0>;
+	};
+
+	sec_jr3: jr@4000 {
+		compatible = "fsl,sec-v5.0-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg = <0x4000 0x1000>;
+		interrupts = <91 2 0 0>;
+	};
+
+	rtic@6000 {
+		compatible = "fsl,sec-v5.0-rtic",
+			     "fsl,sec-v4.0-rtic";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x6000 0x100>;
+		ranges = <0x0 0x6100 0xe00>;
+
+		rtic_a: rtic-a@0 {
+			compatible = "fsl,sec-v5.0-rtic-memory",
+				     "fsl,sec-v4.0-rtic-memory";
+			reg = <0x00 0x20 0x100 0x80>;
+		};
+
+		rtic_b: rtic-b@20 {
+			compatible = "fsl,sec-v5.0-rtic-memory",
+				     "fsl,sec-v4.0-rtic-memory";
+			reg = <0x20 0x20 0x200 0x80>;
+		};
+
+		rtic_c: rtic-c@40 {
+			compatible = "fsl,sec-v5.0-rtic-memory",
+				     "fsl,sec-v4.0-rtic-memory";
+			reg = <0x40 0x20 0x300 0x80>;
+		};
+
+		rtic_d: rtic-d@60 {
+			compatible = "fsl,sec-v5.0-rtic-memory",
+				     "fsl,sec-v4.0-rtic-memory";
+			reg = <0x60 0x20 0x500 0x80>;
+		};
+	};
+};
+
+sec_mon: sec_mon@314000 {
+	compatible = "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon";
+	reg = <0x314000 0x1000>;
+	interrupts = <93 2 0 0>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-usb2-dr-0.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-usb2-dr-0.dtsi
new file mode 100644
index 000000000..ee135c67c
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-usb2-dr-0.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ USB DR device tree stub [ controller @ offset 0x211000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+usb@211000 {
+	compatible = "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
+	reg = <0x211000 0x1000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	interrupts = <45 0x2 0 0>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/qoriq-usb2-mph-0.dtsi b/roms/u-boot/arch/powerpc/dts/qoriq-usb2-mph-0.dtsi
new file mode 100644
index 000000000..8579cc1e0
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/qoriq-usb2-mph-0.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ USB Host device tree stub [ controller @ offset 0x210000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+usb@210000 {
+	compatible = "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
+	reg = <0x210000 0x1000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	interrupts = <44 0x2 0 0>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/socrates-u-boot.dtsi b/roms/u-boot/arch/powerpc/dts/socrates-u-boot.dtsi
new file mode 100644
index 000000000..14a7c245d
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/socrates-u-boot.dtsi
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de
+ */
+/ {
+	binman {
+		filename = "u-boot-socrates.bin";
+		pad-byte = <0xff>;
+		// Place dtb one sector before u-boot-nodtb.bin
+		blob {
+			filename = "dts/dt.dtb";
+		};
+		u-boot-nodtb {
+			filename = "u-boot-nodtb.bin";
+			offset = <0x20000>;
+		};
+	};
+
+	chosen {
+		stdout-path = &serial0;
+	};
+
+	soc8544@e0000000 {
+		i2c@3000 {
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
+
+&pci0 {
+	clock-frequency = <33000000>;
+	ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+		  0x01000000 0x0 0xe2000000 0xe2000000 0x0 0x01000000>;
+};
+
+&serial0 {
+	u-boot,dm-pre-reloc;
+	clock-frequency = <333333330>;
+};
diff --git a/roms/u-boot/arch/powerpc/dts/socrates.dts b/roms/u-boot/arch/powerpc/dts/socrates.dts
new file mode 100644
index 000000000..452cf58b5
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/socrates.dts
@@ -0,0 +1,349 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree Source for the Socrates board (MPC8544).
+ *
+ * Copyright (c) 2008 Emcraft Systems.
+ * Sergei Poselenov, <sposelenov@emcraft.com>
+ *
+ */
+
+/dts-v1/;
+
+/ {
+	model = "abb,socrates";
+	compatible = "abb,socrates";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		ethernet0 = &enet0;
+		ethernet1 = &enet1;
+		serial0 = &serial0;
+		serial1 = &serial1;
+		pci0 = &pci0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,8544@0 {
+			device_type = "cpu";
+			reg = <0>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x8000>;	// L1, 32K
+			i-cache-size = <0x8000>;	// L1, 32K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+			next-level-cache = <&L2>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x00000000>;	// Filled in by U-Boot
+	};
+
+	soc8544@e0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+
+		ranges = <0x00000000 0xe0000000 0x00100000>;
+		bus-frequency = <0>;		// Filled in by U-Boot
+		compatible = "fsl,mpc8544-immr", "simple-bus";
+
+		ecm-law@0 {
+			compatible = "fsl,ecm-law";
+			reg = <0x0 0x1000>;
+			fsl,num-laws = <10>;
+		};
+
+		ecm@1000 {
+			compatible = "fsl,mpc8544-ecm", "fsl,ecm";
+			reg = <0x1000 0x1000>;
+			interrupts = <17 2>;
+			interrupt-parent = <&mpic>;
+		};
+
+		memory-controller@2000 {
+			compatible = "fsl,mpc8544-memory-controller";
+			reg = <0x2000 0x1000>;
+			interrupt-parent = <&mpic>;
+			interrupts = <18 2>;
+		};
+
+		L2: l2-cache-controller@20000 {
+			compatible = "fsl,mpc8544-l2-cache-controller";
+			reg = <0x20000 0x1000>;
+			cache-line-size = <32>;
+			cache-size = <0x40000>;	// L2, 256K
+			interrupt-parent = <&mpic>;
+			interrupts = <16 2>;
+		};
+
+		i2c@3000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <0>;
+			compatible = "fsl,mpc8544-i2c", "fsl-i2c";
+			reg = <0x3000 0x100>;
+			interrupts = <43 2>;
+			interrupt-parent = <&mpic>;
+			fsl,preserve-clocking;
+
+			dtt@28 {
+				compatible = "winbond,w83782d";
+				reg = <0x28>;
+			};
+			rtc@32 {
+				compatible = "epson,rx8025";
+				reg = <0x32>;
+				interrupts = <7 1>;
+				interrupt-parent = <&mpic>;
+			};
+			dtt@4c {
+				compatible = "dallas,ds75";
+				reg = <0x4c>;
+			};
+			ts@4a {
+				compatible = "ti,tsc2003";
+				reg = <0x4a>;
+				interrupt-parent = <&mpic>;
+				interrupts = <8 1>;
+			};
+		};
+
+		i2c@3100 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <1>;
+			compatible = "fsl,mpc8544-i2c", "fsl-i2c";
+			reg = <0x3100 0x100>;
+			interrupts = <43 2>;
+			interrupt-parent = <&mpic>;
+			fsl,preserve-clocking;
+		};
+
+		enet0: ethernet@24000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			cell-index = <0>;
+			device_type = "network";
+			model = "eTSEC";
+			compatible = "gianfar";
+			reg = <0x24000 0x1000>;
+			ranges = <0x0 0x24000 0x1000>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <29 2 30 2 34 2>;
+			interrupt-parent = <&mpic>;
+			phy-handle = <&phy0>;
+			tbi-handle = <&tbi0>;
+			phy-connection-type = "rgmii-id";
+
+			mdio@520 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,gianfar-mdio";
+				reg = <0x520 0x20>;
+
+				phy0: ethernet-phy@0 {
+					interrupt-parent = <&mpic>;
+					interrupts = <0 1>;
+					reg = <0>;
+				};
+				phy1: ethernet-phy@1 {
+					interrupt-parent = <&mpic>;
+					interrupts = <0 1>;
+					reg = <1>;
+				};
+				tbi0: tbi-phy@11 {
+					reg = <0x11>;
+				};
+			};
+		};
+
+		enet1: ethernet@26000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			cell-index = <1>;
+			device_type = "network";
+			model = "eTSEC";
+			compatible = "gianfar";
+			reg = <0x26000 0x1000>;
+			ranges = <0x0 0x26000 0x1000>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <31 2 32 2 33 2>;
+			interrupt-parent = <&mpic>;
+			phy-handle = <&phy1>;
+			tbi-handle = <&tbi1>;
+			phy-connection-type = "rgmii-id";
+
+			mdio@520 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,gianfar-tbi";
+				reg = <0x520 0x20>;
+
+				tbi1: tbi-phy@11 {
+					reg = <0x11>;
+				};
+			};
+		};
+
+		serial0: serial@4500 {
+			cell-index = <0>;
+			device_type = "serial";
+			compatible = "fsl,ns16550", "ns16550";
+			reg = <0x4500 0x100>;
+			clock-frequency = <0>;
+			interrupts = <42 2>;
+			interrupt-parent = <&mpic>;
+		};
+
+		serial1: serial@4600 {
+			cell-index = <1>;
+			device_type = "serial";
+			compatible = "fsl,ns16550", "ns16550";
+			reg = <0x4600 0x100>;
+			clock-frequency = <0>;
+			interrupts = <42 2>;
+			interrupt-parent = <&mpic>;
+		};
+
+		global-utilities@e0000 {	//global utilities block
+			compatible = "fsl,mpc8548-guts";
+			reg = <0xe0000 0x1000>;
+			fsl,has-rstcr;
+		};
+
+		mpic: pic@40000 {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			reg = <0x40000 0x40000>;
+			compatible = "chrp,open-pic";
+			device_type = "open-pic";
+		};
+	};
+
+
+	localbus {
+		compatible = "fsl,mpc8544-localbus",
+		             "fsl,pq3-localbus",
+			     "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		reg = <0xe0005000 0x40>;
+		interrupt-parent = <&mpic>;
+		interrupts = <19 2>;
+
+		ranges = <0 0 0xfc000000 0x04000000
+			  2 0 0xc8000000 0x04000000
+			  3 0 0xc0000000 0x00100000
+			>; /* Overwritten by U-Boot */
+
+		nor_flash@0,0 {
+			compatible = "amd,s29gl256n", "cfi-flash";
+			bank-width = <2>;
+			reg = <0x0 0x000000 0x4000000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			partition@0 {
+				label = "kernel";
+				reg = <0x0 0x1e0000>;
+				read-only;
+			};
+			partition@1e0000 {
+				label = "dtb";
+				reg = <0x1e0000 0x20000>;
+			};
+			partition@200000 {
+				label = "root";
+				reg = <0x200000 0x200000>;
+			};
+			partition@400000 {
+				label = "user";
+				reg = <0x400000 0x3b80000>;
+			};
+			partition@3f80000 {
+				label = "env";
+				reg = <0x3f80000 0x40000>;
+				read-only;
+			};
+			partition@3fc0000 {
+				label = "u-boot";
+				reg = <0x3fc0000 0x40000>;
+				read-only;
+			};
+		};
+
+		display@2,0 {
+			compatible = "fujitsu,lime";
+			reg = <2 0x0 0x4000000>;
+			interrupt-parent = <&mpic>;
+			interrupts = <6 1>;
+		};
+
+		fpga_pic: fpga-pic@3,10 {
+			compatible = "abb,socrates-fpga-pic";
+			reg = <3 0x10 0x10>;
+			interrupt-controller;
+			/* IRQs 2, 10, 11, active low, level-sensitive */
+			interrupts = <2 1 10 1 11 1>;
+			interrupt-parent = <&mpic>;
+			#interrupt-cells = <3>;
+		};
+
+		spi@3,60 {
+			compatible = "abb,socrates-spi";
+			reg = <3 0x60 0x10>;
+			interrupts = <8 4 0>;	// number, type, routing
+			interrupt-parent = <&fpga_pic>;
+		};
+
+		nand@3,70 {
+			compatible = "abb,socrates-nand";
+			reg = <3 0x70 0x04>;
+			bank-width = <1>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			data@0 {
+				label = "data";
+				reg = <0x0 0x40000000>;
+			};
+		};
+
+		can@3,100 {
+			compatible = "philips,sja1000";
+			reg = <3 0x100 0x80>;
+			interrupts = <2 8 1>;	// number, type, routing
+			interrupt-parent = <&fpga_pic>;
+		};
+	};
+
+	pci0: pci@e0008000 {
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		compatible = "fsl,mpc8540-pci";
+		device_type = "pci";
+		reg = <0xe0008000 0x1000>;
+		clock-frequency = <66666666>;
+
+		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+		interrupt-map = <
+				/* IDSEL 0x11 */
+				 0x8800 0x0 0x0 1 &mpic 5 1
+				/* IDSEL 0x12 */
+				 0x9000 0x0 0x0 1 &mpic 4 1>;
+		interrupt-parent = <&mpic>;
+		interrupts = <24 2>;
+		bus-range = <0x0 0x0>;
+		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>;
+	};
+
+};
diff --git a/roms/u-boot/arch/powerpc/dts/t1023si-post.dtsi b/roms/u-boot/arch/powerpc/dts/t1023si-post.dtsi
new file mode 100644
index 000000000..7284eb979
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/t1023si-post.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * T1023 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ * Copyright 2019-2020 NXP
+ *
+ */
+
+&soc {
+
+/include/ "qoriq-clockgen2.dtsi"
+/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-gpio-1.dtsi"
+/include/ "qoriq-gpio-2.dtsi"
+/include/ "qoriq-gpio-3.dtsi"
+
+/* include used FMan blocks */
+/include/ "qoriq-fman3l-0.dtsi"
+/include/ "qoriq-fman3-0-10g-0-best-effort.dtsi"
+/include/ "qoriq-fman3-0-1g-1.dtsi"
+/include/ "qoriq-fman3-0-1g-2.dtsi"
+/include/ "qoriq-fman3-0-1g-3.dtsi"
+	fman@400000 {
+		enet0: ethernet@e0000 {
+		};
+
+		enet1: ethernet@e2000 {
+		};
+
+		enet2: ethernet@e4000 {
+		};
+
+		enet3: ethernet@e6000 {
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/t1024rdb.dts b/roms/u-boot/arch/powerpc/dts/t1024rdb.dts
new file mode 100644
index 000000000..eeba99f84
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/t1024rdb.dts
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T1024RDB Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019-2020 NXP
+ */
+
+/include/ "t102x.dtsi"
+
+/ {
+	model = "fsl,T1024RDB";
+	compatible = "fsl,T1024RDB";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	aliases {
+		sg_2500_aqr105_phy4 = &sg_2500_aqr105_phy4;
+		spi0 = &espi0;
+	};
+
+	soc: soc@ffe000000 {
+		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+		reg = <0xf 0xfe000000 0 0x00001000>;
+
+		fman@400000 {
+			fm1mac1: ethernet@e0000 {
+				phy-handle = <&xg_aqr105_phy3>;
+				phy-connection-type = "xgmii";
+			};
+
+			fm1mac2: ethernet@e2000 {
+			};
+
+			fm1mac3: ethernet@e4000 {
+				phy-handle = <&rgmii_phy2>;
+				phy-connection-type = "rgmii";
+			};
+
+			fm1mac4: ethernet@e6000 {
+				phy-handle = <&rgmii_phy1>;
+				phy-connection-type = "rgmii";
+			};
+
+			mdio0: mdio@fc000 {
+				rgmii_phy1: ethernet-phy@2 {
+					reg = <0x2>;
+				};
+				rgmii_phy2: ethernet-phy@6 {
+					reg = <0x6>;
+				};
+			};
+
+			xmdio0: mdio@fd000 {
+				xg_aqr105_phy3: ethernet-phy@1 {
+					compatible = "ethernet-phy-ieee802.3-c45";
+					reg = <0x1>;
+				};
+				sg_2500_aqr105_phy4: ethernet-phy@2 {
+					compatible = "ethernet-phy-ieee802.3-c45";
+					reg = <0x2>;
+				};
+			};
+		};
+	};
+};
+
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		/* input clock */
+		spi-max-frequency = <10000000>;
+	};
+};
+
+#include "t1024si-post.dtsi"
diff --git a/roms/u-boot/arch/powerpc/dts/t1024si-post.dtsi b/roms/u-boot/arch/powerpc/dts/t1024si-post.dtsi
new file mode 100644
index 000000000..8cdc5088e
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/t1024si-post.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * T1024 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ * Copyright 2019-2020 NXP
+ *
+ */
+
+#include "t1023si-post.dtsi"
diff --git a/roms/u-boot/arch/powerpc/dts/t102x.dtsi b/roms/u-boot/arch/powerpc/dts/t102x.dtsi
new file mode 100644
index 000000000..cf8962abe
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/t102x.dtsi
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T102X Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019-2020 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e5500_power_isa.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: PowerPC,e5500@0 {
+			device_type = "cpu";
+			reg = <0>;
+			#cooling-cells = <2>;
+		};
+		cpu1: PowerPC,e5500@1 {
+			device_type = "cpu";
+			reg = <1>;
+			#cooling-cells = <2>;
+		};
+	};
+
+	soc: soc@ffe000000 {
+		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+		reg = <0xf 0xfe000000 0 0x00001000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "simple-bus";
+
+		mpic: pic@40000 {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <4>;
+			reg = <0x40000 0x40000>;
+			compatible = "fsl,mpic", "chrp,open-pic";
+			device_type = "open-pic";
+			clock-frequency = <0x0>;
+		};
+
+		espi0: spi@110000 {
+			compatible = "fsl,mpc8536-espi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x110000 0x1000>;
+			fsl,espi-num-chipselects = <4>;
+			status = "disabled";
+		};
+
+		usb0@210000 {
+			compatible = "fsl-usb2-mph";
+			reg = <0x210000 0x1000>;
+			phy_type = "utmi";
+		};
+
+		usb1@211000 {
+			compatible = "fsl-usb2-dr";
+			reg = <0x211000 0x1000>;
+			phy_type = "utmi";
+		};
+
+		sata: sata@220000 {
+			compatible = "fsl,pq-sata-v2";
+			reg = <0x220000 0x1000>;
+			interrupts = <68 0x2 0 0>;
+			sata-offset = <0x1000>;
+			sata-number = <2>;
+			sata-fpdma = <0>;
+		};
+
+		esdhc: esdhc@114000 {
+			compatible = "fsl,esdhc";
+			reg = <0x114000 0x1000>;
+			clock-frequency = <0>;
+		};
+		/include/ "qoriq-i2c-0.dtsi"
+		/include/ "qoriq-i2c-1.dtsi"
+	};
+
+	pcie@ffe240000 {
+		compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe240000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */
+	};
+
+	pcie@ffe250000 {
+		compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe250000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */
+	};
+
+	pcie@ffe260000 {
+		compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe260000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <2>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/t1040si-post.dtsi b/roms/u-boot/arch/powerpc/dts/t1040si-post.dtsi
new file mode 100644
index 000000000..c71cf33f8
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/t1040si-post.dtsi
@@ -0,0 +1,727 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * T1040 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 - 2014 Freescale Semiconductor Inc.
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+&bman_fbpr {
+	compatible = "fsl,bman-fbpr";
+	alloc-ranges = <0 0 0x10000 0>;
+};
+
+&qman_fqd {
+	compatible = "fsl,qman-fqd";
+	alloc-ranges = <0 0 0x10000 0>;
+};
+
+&qman_pfdr {
+	compatible = "fsl,qman-pfdr";
+	alloc-ranges = <0 0 0x10000 0>;
+};
+
+&ifc {
+	#address-cells = <2>;
+	#size-cells = <1>;
+	compatible = "fsl,ifc", "simple-bus";
+	interrupts = <25 2 0 0>;
+};
+
+&pci0 {
+	compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
+	device_type = "pci";
+	#size-cells = <2>;
+	#address-cells = <3>;
+	bus-range = <0x0 0xff>;
+	interrupts = <20 2 0 0>;
+	fsl,iommu-parent = <&pamu0>;
+	pcie@0 {
+		reg = <0 0 0 0 0>;
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		device_type = "pci";
+		interrupts = <20 2 0 0>;
+		interrupt-map-mask = <0xf800 0 0 7>;
+		interrupt-map = <
+			/* IDSEL 0x0 */
+			0000 0 0 1 &mpic 40 1 0 0
+			0000 0 0 2 &mpic 1 1 0 0
+			0000 0 0 3 &mpic 2 1 0 0
+			0000 0 0 4 &mpic 3 1 0 0
+			>;
+	};
+};
+
+&pci1 {
+	compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
+	device_type = "pci";
+	#size-cells = <2>;
+	#address-cells = <3>;
+	bus-range = <0 0xff>;
+	interrupts = <21 2 0 0>;
+	fsl,iommu-parent = <&pamu0>;
+	pcie@0 {
+		reg = <0 0 0 0 0>;
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		device_type = "pci";
+		interrupts = <21 2 0 0>;
+		interrupt-map-mask = <0xf800 0 0 7>;
+		interrupt-map = <
+			/* IDSEL 0x0 */
+			0000 0 0 1 &mpic 41 1 0 0
+			0000 0 0 2 &mpic 5 1 0 0
+			0000 0 0 3 &mpic 6 1 0 0
+			0000 0 0 4 &mpic 7 1 0 0
+			>;
+	};
+};
+
+&pci2 {
+	compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
+	device_type = "pci";
+	#size-cells = <2>;
+	#address-cells = <3>;
+	bus-range = <0x0 0xff>;
+	interrupts = <22 2 0 0>;
+	fsl,iommu-parent = <&pamu0>;
+	pcie@0 {
+		reg = <0 0 0 0 0>;
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		device_type = "pci";
+		interrupts = <22 2 0 0>;
+		interrupt-map-mask = <0xf800 0 0 7>;
+		interrupt-map = <
+			/* IDSEL 0x0 */
+			0000 0 0 1 &mpic 42 1 0 0
+			0000 0 0 2 &mpic 9 1 0 0
+			0000 0 0 3 &mpic 10 1 0 0
+			0000 0 0 4 &mpic 11 1 0 0
+			>;
+	};
+};
+
+&pci3 {
+	compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
+	device_type = "pci";
+	#size-cells = <2>;
+	#address-cells = <3>;
+	bus-range = <0x0 0xff>;
+	interrupts = <23 2 0 0>;
+	fsl,iommu-parent = <&pamu0>;
+	pcie@0 {
+		reg = <0 0 0 0 0>;
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		device_type = "pci";
+		interrupts = <23 2 0 0>;
+		interrupt-map-mask = <0xf800 0 0 7>;
+		interrupt-map = <
+			/* IDSEL 0x0 */
+			0000 0 0 1 &mpic 43 1 0 0
+			0000 0 0 2 &mpic 0 1 0 0
+			0000 0 0 3 &mpic 4 1 0 0
+			0000 0 0 4 &mpic 8 1 0 0
+			>;
+	};
+};
+
+&dcsr {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "fsl,dcsr", "simple-bus";
+
+	dcsr-epu@0 {
+		compatible = "fsl,t1040-dcsr-epu", "fsl,dcsr-epu";
+		interrupts = <52 2 0 0
+			      84 2 0 0
+			      85 2 0 0>;
+		reg = <0x0 0x1000>;
+	};
+	dcsr-npc {
+		compatible = "fsl,t1040-dcsr-cnpc", "fsl,dcsr-cnpc";
+		reg = <0x1000 0x1000 0x1002000 0x10000>;
+	};
+	dcsr-nxc@2000 {
+		compatible = "fsl,dcsr-nxc";
+		reg = <0x2000 0x1000>;
+	};
+	dcsr-corenet {
+		compatible = "fsl,dcsr-corenet";
+		reg = <0x8000 0x1000 0x1A000 0x1000>;
+	};
+	dcsr-dpaa@9000 {
+		compatible = "fsl,t1040-dcsr-dpaa", "fsl,dcsr-dpaa";
+		reg = <0x9000 0x1000>;
+	};
+	dcsr-ocn@11000 {
+		compatible = "fsl,t1040-dcsr-ocn", "fsl,dcsr-ocn";
+		reg = <0x11000 0x1000>;
+	};
+	dcsr-ddr@12000 {
+		compatible = "fsl,dcsr-ddr";
+		dev-handle = <&ddr1>;
+		reg = <0x12000 0x1000>;
+	};
+	dcsr-nal@18000 {
+		compatible = "fsl,t1040-dcsr-nal", "fsl,dcsr-nal";
+		reg = <0x18000 0x1000>;
+	};
+	dcsr-rcpm@22000 {
+		compatible = "fsl,t1040-dcsr-rcpm", "fsl,dcsr-rcpm";
+		reg = <0x22000 0x1000>;
+	};
+	dcsr-snpc@30000 {
+		compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc";
+		reg = <0x30000 0x1000 0x1022000 0x10000>;
+	};
+	dcsr-snpc@31000 {
+		compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc";
+		reg = <0x31000 0x1000 0x1042000 0x10000>;
+	};
+	dcsr-cpu-sb-proxy@100000 {
+		compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+		cpu-handle = <&cpu0>;
+		reg = <0x100000 0x1000 0x101000 0x1000>;
+	};
+	dcsr-cpu-sb-proxy@108000 {
+		compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+		cpu-handle = <&cpu1>;
+		reg = <0x108000 0x1000 0x109000 0x1000>;
+	};
+	dcsr-cpu-sb-proxy@110000 {
+		compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+		cpu-handle = <&cpu2>;
+		reg = <0x110000 0x1000 0x111000 0x1000>;
+	};
+	dcsr-cpu-sb-proxy@118000 {
+		compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+		cpu-handle = <&cpu3>;
+		reg = <0x118000 0x1000 0x119000 0x1000>;
+	};
+};
+
+&bportals {
+	#address-cells = <0x1>;
+	#size-cells = <0x1>;
+	compatible = "simple-bus";
+
+	bman-portal@0 {
+		compatible = "fsl,bman-portal";
+		reg = <0x0 0x4000>, <0x1000000 0x1000>;
+		interrupts = <105 2 0 0>;
+	};
+	bman-portal@4000 {
+		compatible = "fsl,bman-portal";
+		reg = <0x4000 0x4000>, <0x1001000 0x1000>;
+		interrupts = <107 2 0 0>;
+	};
+	bman-portal@8000 {
+		compatible = "fsl,bman-portal";
+		reg = <0x8000 0x4000>, <0x1002000 0x1000>;
+		interrupts = <109 2 0 0>;
+	};
+	bman-portal@c000 {
+		compatible = "fsl,bman-portal";
+		reg = <0xc000 0x4000>, <0x1003000 0x1000>;
+		interrupts = <111 2 0 0>;
+	};
+	bman-portal@10000 {
+		compatible = "fsl,bman-portal";
+		reg = <0x10000 0x4000>, <0x1004000 0x1000>;
+		interrupts = <113 2 0 0>;
+	};
+	bman-portal@14000 {
+		compatible = "fsl,bman-portal";
+		reg = <0x14000 0x4000>, <0x1005000 0x1000>;
+		interrupts = <115 2 0 0>;
+	};
+	bman-portal@18000 {
+		compatible = "fsl,bman-portal";
+		reg = <0x18000 0x4000>, <0x1006000 0x1000>;
+		interrupts = <117 2 0 0>;
+	};
+	bman-portal@1c000 {
+		compatible = "fsl,bman-portal";
+		reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
+		interrupts = <119 2 0 0>;
+	};
+	bman-portal@20000 {
+		compatible = "fsl,bman-portal";
+		reg = <0x20000 0x4000>, <0x1008000 0x1000>;
+		interrupts = <121 2 0 0>;
+	};
+	bman-portal@24000 {
+		compatible = "fsl,bman-portal";
+		reg = <0x24000 0x4000>, <0x1009000 0x1000>;
+		interrupts = <123 2 0 0>;
+	};
+};
+
+&qportals {
+	#address-cells = <0x1>;
+	#size-cells = <0x1>;
+	compatible = "simple-bus";
+
+	qportal0: qman-portal@0 {
+		compatible = "fsl,qman-portal";
+		reg = <0x0 0x4000>, <0x1000000 0x1000>;
+		interrupts = <104 0x2 0 0>;
+		cell-index = <0x0>;
+	};
+	qportal1: qman-portal@4000 {
+		compatible = "fsl,qman-portal";
+		reg = <0x4000 0x4000>, <0x1001000 0x1000>;
+		interrupts = <106 0x2 0 0>;
+		cell-index = <0x1>;
+	};
+	qportal2: qman-portal@8000 {
+		compatible = "fsl,qman-portal";
+		reg = <0x8000 0x4000>, <0x1002000 0x1000>;
+		interrupts = <108 0x2 0 0>;
+		cell-index = <0x2>;
+	};
+	qportal3: qman-portal@c000 {
+		compatible = "fsl,qman-portal";
+		reg = <0xc000 0x4000>, <0x1003000 0x1000>;
+		interrupts = <110 0x2 0 0>;
+		cell-index = <0x3>;
+	};
+	qportal4: qman-portal@10000 {
+		compatible = "fsl,qman-portal";
+		reg = <0x10000 0x4000>, <0x1004000 0x1000>;
+		interrupts = <112 0x2 0 0>;
+		cell-index = <0x4>;
+	};
+	qportal5: qman-portal@14000 {
+		compatible = "fsl,qman-portal";
+		reg = <0x14000 0x4000>, <0x1005000 0x1000>;
+		interrupts = <114 0x2 0 0>;
+		cell-index = <0x5>;
+	};
+	qportal6: qman-portal@18000 {
+		compatible = "fsl,qman-portal";
+		reg = <0x18000 0x4000>, <0x1006000 0x1000>;
+		interrupts = <116 0x2 0 0>;
+		cell-index = <0x6>;
+	};
+	qportal7: qman-portal@1c000 {
+		compatible = "fsl,qman-portal";
+		reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
+		interrupts = <118 0x2 0 0>;
+		cell-index = <0x7>;
+	};
+	qportal8: qman-portal@20000 {
+		compatible = "fsl,qman-portal";
+		reg = <0x20000 0x4000>, <0x1008000 0x1000>;
+		interrupts = <120 0x2 0 0>;
+		cell-index = <0x8>;
+	};
+	qportal9: qman-portal@24000 {
+		compatible = "fsl,qman-portal";
+		reg = <0x24000 0x4000>, <0x1009000 0x1000>;
+		interrupts = <122 0x2 0 0>;
+		cell-index = <0x9>;
+	};
+};
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	device_type = "soc";
+	compatible = "simple-bus";
+
+	soc-sram-error {
+		compatible = "fsl,soc-sram-error";
+		interrupts = <16 2 1 29>;
+	};
+
+	corenet-law@0 {
+		compatible = "fsl,corenet-law";
+		reg = <0x0 0x1000>;
+		fsl,num-laws = <16>;
+	};
+
+	ddr1: memory-controller@8000 {
+		compatible = "fsl,qoriq-memory-controller-v5.0",
+				"fsl,qoriq-memory-controller";
+		reg = <0x8000 0x1000>;
+		interrupts = <16 2 1 23>;
+	};
+
+	cpc: l3-cache-controller@10000 {
+		compatible = "fsl,t1040-l3-cache-controller", "cache";
+		reg = <0x10000 0x1000>;
+		interrupts = <16 2 1 27>;
+	};
+
+	corenet-cf@18000 {
+		compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
+		reg = <0x18000 0x1000>;
+		interrupts = <16 2 1 31>;
+		fsl,ccf-num-csdids = <32>;
+		fsl,ccf-num-snoopids = <32>;
+	};
+
+	iommu@20000 {
+		compatible = "fsl,pamu-v1.0", "fsl,pamu";
+		reg = <0x20000 0x1000>;
+		ranges = <0 0x20000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		interrupts = <
+			24 2 0 0
+			16 2 1 30>;
+		pamu0: pamu@0 {
+			reg = <0 0x1000>;
+			fsl,primary-cache-geometry = <128 1>;
+			fsl,secondary-cache-geometry = <16 2>;
+		};
+	};
+
+/include/ "qoriq-mpic.dtsi"
+
+	guts: global-utilities@e0000 {
+		compatible = "fsl,t1040-device-config", "fsl,qoriq-device-config-2.0";
+		reg = <0xe0000 0xe00>;
+		fsl,has-rstcr;
+		fsl,liodn-bits = <12>;
+	};
+
+/include/ "qoriq-clockgen2.dtsi"
+	global-utilities@e1000 {
+		compatible = "fsl,t1040-clockgen", "fsl,qoriq-clockgen-2.0";
+	};
+
+	rcpm: global-utilities@e2000 {
+		compatible = "fsl,t1040-rcpm", "fsl,qoriq-rcpm-2.1";
+		reg = <0xe2000 0x1000>;
+	};
+
+	sfp: sfp@e8000 {
+		compatible = "fsl,t1040-sfp";
+		reg	   = <0xe8000 0x1000>;
+	};
+
+	serdes: serdes@ea000 {
+		compatible = "fsl,t1040-serdes";
+		reg	   = <0xea000 0x4000>;
+	};
+
+	tmu: tmu@f0000 {
+		compatible = "fsl,qoriq-tmu";
+		reg = <0xf0000 0x1000>;
+		interrupts = <18 2 0 0>;
+		fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>;
+		fsl,tmu-calibration = <0x00000000 0x00000025
+				       0x00000001 0x00000028
+				       0x00000002 0x0000002d
+				       0x00000003 0x00000031
+				       0x00000004 0x00000036
+				       0x00000005 0x0000003a
+				       0x00000006 0x00000040
+				       0x00000007 0x00000044
+				       0x00000008 0x0000004a
+				       0x00000009 0x0000004f
+				       0x0000000a 0x00000054
+
+				       0x00010000 0x0000000d
+				       0x00010001 0x00000013
+				       0x00010002 0x00000019
+				       0x00010003 0x0000001f
+				       0x00010004 0x00000025
+				       0x00010005 0x0000002d
+				       0x00010006 0x00000033
+				       0x00010007 0x00000043
+				       0x00010008 0x0000004b
+				       0x00010009 0x00000053
+
+				       0x00020000 0x00000010
+				       0x00020001 0x00000017
+				       0x00020002 0x0000001f
+				       0x00020003 0x00000029
+				       0x00020004 0x00000031
+				       0x00020005 0x0000003c
+				       0x00020006 0x00000042
+				       0x00020007 0x0000004d
+				       0x00020008 0x00000056
+
+				       0x00030000 0x00000012
+				       0x00030001 0x0000001d>;
+		#thermal-sensor-cells = <1>;
+	};
+
+	thermal-zones {
+		cpu_thermal: cpu-thermal {
+			polling-delay-passive = <1000>;
+			polling-delay = <5000>;
+
+			thermal-sensors = <&tmu 2>;
+
+			trips {
+				cpu_alert: cpu-alert {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu_crit: cpu-crit {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert>;
+					cooling-device =
+						<&cpu0 THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+				};
+				map1 {
+					trip = <&cpu_alert>;
+					cooling-device =
+						<&cpu1 THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+				};
+				map2 {
+					trip = <&cpu_alert>;
+					cooling-device =
+						<&cpu2 THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+				};
+				map3 {
+					trip = <&cpu_alert>;
+					cooling-device =
+						<&cpu3 THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+
+	scfg: global-utilities@fc000 {
+		compatible = "fsl,t1040-scfg";
+		reg = <0xfc000 0x1000>;
+	};
+
+/include/ "elo3-dma-0.dtsi"
+/include/ "elo3-dma-1.dtsi"
+/include/ "qoriq-espi-0.dtsi"
+	spi@110000 {
+		fsl,espi-num-chipselects = <4>;
+	};
+
+/include/ "qoriq-esdhc-0.dtsi"
+	sdhc@114000 {
+		compatible = "fsl,t1040-esdhc", "fsl,esdhc";
+		fsl,iommu-parent = <&pamu0>;
+		fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
+		sdhci,auto-cmd12;
+	};
+/include/ "qoriq-i2c-0.dtsi"
+/include/ "qoriq-i2c-1.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
+/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-gpio-1.dtsi"
+/include/ "qoriq-gpio-2.dtsi"
+/include/ "qoriq-gpio-3.dtsi"
+/include/ "qoriq-usb2-mph-0.dtsi"
+		usb0: usb@210000 {
+			compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph";
+			fsl,iommu-parent = <&pamu0>;
+			fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
+			phy_type = "utmi";
+			port0;
+		};
+/include/ "qoriq-usb2-dr-0.dtsi"
+		usb1: usb@211000 {
+			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
+			fsl,iommu-parent = <&pamu0>;
+			fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
+			dr_mode = "host";
+			phy_type = "utmi";
+		};
+
+	display@180000 {
+		compatible = "fsl,t1040-diu", "fsl,diu";
+		reg = <0x180000 1000>;
+		interrupts = <74 2 0 0>;
+	};
+
+/include/ "qoriq-sata2-0.dtsi"
+	sata@220000 {
+		fsl,iommu-parent = <&pamu0>;
+		fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
+	};
+/include/ "qoriq-sata2-1.dtsi"
+	sata@221000 {
+		fsl,iommu-parent = <&pamu0>;
+		fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
+	};
+/include/ "qoriq-sec5.0-0.dtsi"
+/include/ "qoriq-qman3.dtsi"
+/include/ "qoriq-bman1.dtsi"
+
+/include/ "qoriq-fman3l-0.dtsi"
+/include/ "qoriq-fman3-0-1g-0.dtsi"
+/include/ "qoriq-fman3-0-1g-1.dtsi"
+/include/ "qoriq-fman3-0-1g-2.dtsi"
+/include/ "qoriq-fman3-0-1g-3.dtsi"
+/include/ "qoriq-fman3-0-1g-4.dtsi"
+	fman@400000 {
+		enet0: ethernet@e0000 {
+		};
+
+		enet1: ethernet@e2000 {
+		};
+
+		enet2: ethernet@e4000 {
+		};
+
+		enet3: ethernet@e6000 {
+		};
+
+		enet4: ethernet@e8000 {
+		};
+
+		mdio@fc000 {
+			interrupts = <100 1 0 0>;
+		};
+
+		mdio@fd000 {
+			status = "disabled";
+		};
+	};
+
+	seville_switch: ethernet-switch@800000 {
+		compatible = "mscc,vsc9953-switch";
+		reg = <0x800000 0x290000>;
+		interrupts = <26 2 0 0>;
+		interrupt-names = "xtr";
+		little-endian;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			seville_port0: port@0 {
+				reg = <0>;
+				status = "disabled";
+			};
+
+			seville_port1: port@1 {
+				reg = <1>;
+				status = "disabled";
+			};
+
+			seville_port2: port@2 {
+				reg = <2>;
+				status = "disabled";
+			};
+
+			seville_port3: port@3 {
+				reg = <3>;
+				status = "disabled";
+			};
+
+			seville_port4: port@4 {
+				reg = <4>;
+				status = "disabled";
+			};
+
+			seville_port5: port@5 {
+				reg = <5>;
+				status = "disabled";
+			};
+
+			seville_port6: port@6 {
+				reg = <6>;
+				status = "disabled";
+			};
+
+			seville_port7: port@7 {
+				reg = <7>;
+				status = "disabled";
+			};
+
+			seville_port8: port@8 {
+				reg = <8>;
+				phy-mode = "internal";
+				status = "disabled";
+
+				fixed-link {
+					speed = <2500>;
+					full-duplex;
+				};
+			};
+
+			seville_port9: port@9 {
+				reg = <9>;
+				phy-mode = "internal";
+				status = "disabled";
+
+				fixed-link {
+					speed = <2500>;
+					full-duplex;
+				};
+			};
+		};
+	};
+};
+
+&qe {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	device_type = "qe";
+	compatible = "fsl,qe";
+	fsl,qe-num-riscs = <1>;
+	fsl,qe-num-snums = <28>;
+
+	qeic: interrupt-controller@80 {
+		interrupt-controller;
+		compatible = "fsl,qe-ic";
+		#address-cells = <0>;
+		#interrupt-cells = <1>;
+		reg = <0x80 0x80>;
+		interrupts = <95 2 0 0  94 2 0 0>; //high:79 low:78
+	};
+
+	ucc@2000 {
+		cell-index = <1>;
+		reg = <0x2000 0x200>;
+		interrupts = <32>;
+		interrupt-parent = <&qeic>;
+	};
+
+	ucc@2200 {
+		cell-index = <3>;
+		reg = <0x2200 0x200>;
+		interrupts = <34>;
+		interrupt-parent = <&qeic>;
+	};
+
+	muram@10000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,qe-muram", "fsl,cpm-muram";
+		ranges = <0x0 0x10000 0x6000>;
+
+		data-only@0 {
+			compatible = "fsl,qe-muram-data",
+			"fsl,cpm-muram-data";
+			reg = <0x0 0x6000>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/t1042d4rdb.dts b/roms/u-boot/arch/powerpc/dts/t1042d4rdb.dts
new file mode 100644
index 000000000..5e9fab7a1
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/t1042d4rdb.dts
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T1042D4RDB Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019-2021 NXP
+ */
+
+/include/ "t104x.dtsi"
+
+/ {
+	model = "fsl,T1042D4RDB";
+	compatible = "fsl,T1042D4RDB";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	aliases {
+		spi0 = &espi0;
+	};
+};
+
+&soc {
+	fman0: fman@400000 {
+		ethernet@e0000 {
+			phy-handle = <&phy_sgmii_0>;
+			phy-connection-type = "sgmii";
+		};
+
+		ethernet@e2000 {
+			phy-handle = <&phy_sgmii_1>;
+			phy-connection-type = "sgmii";
+		};
+
+		ethernet@e4000 {
+			phy-handle = <&phy_sgmii_2>;
+			phy-connection-type = "sgmii";
+		};
+
+		ethernet@e6000 {
+			phy-handle = <&phy_rgmii_0>;
+			phy-connection-type = "rgmii";
+		};
+
+		ethernet@e8000 {
+			phy-handle = <&phy_rgmii_1>;
+			phy-connection-type = "rgmii";
+		};
+
+		mdio0: mdio@fc000 {
+			phy_sgmii_0: ethernet-phy@2 {
+				reg = <0x02>;
+			};
+
+			phy_sgmii_1: ethernet-phy@3 {
+				reg = <0x03>;
+			};
+
+			phy_sgmii_2: ethernet-phy@1 {
+				reg = <0x01>;
+			};
+
+			phy_rgmii_0: ethernet-phy@4 {
+				reg = <0x04>;
+			};
+
+			phy_rgmii_1: ethernet-phy@5 {
+				reg = <0x05>;
+			};
+		};
+	};
+};
+
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
+};
+
+/include/ "t1042si-post.dtsi"
diff --git a/roms/u-boot/arch/powerpc/dts/t1042si-post.dtsi b/roms/u-boot/arch/powerpc/dts/t1042si-post.dtsi
new file mode 100644
index 000000000..5c60944e6
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/t1042si-post.dtsi
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * T1042 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 - 2014 Freescale Semiconductor Inc.
+ * Copyright 2021 NXP
+ *
+ */
+&soc {
+/include/ "qoriq-clockgen2.dtsi"
+/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-gpio-1.dtsi"
+/include/ "qoriq-gpio-2.dtsi"
+/include/ "qoriq-gpio-3.dtsi"
+
+/include/ "qoriq-fman3l-0.dtsi"
+/include/ "qoriq-fman3-0-1g-0.dtsi"
+/include/ "qoriq-fman3-0-1g-1.dtsi"
+/include/ "qoriq-fman3-0-1g-2.dtsi"
+/include/ "qoriq-fman3-0-1g-3.dtsi"
+/include/ "qoriq-fman3-0-1g-4.dtsi"
+	fman@400000 {
+		enet0: ethernet@e0000 {
+		};
+
+		enet1: ethernet@e2000 {
+		};
+
+		enet2: ethernet@e4000 {
+		};
+
+		enet3: ethernet@e6000 {
+		};
+
+		enet4: ethernet@e8000 {
+		};
+
+		mdio@fc000 {
+			interrupts = <100 1 0 0>;
+		};
+
+		mdio@fd000 {
+			status = "disabled";
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/t104x.dtsi b/roms/u-boot/arch/powerpc/dts/t104x.dtsi
new file mode 100644
index 000000000..2c7e5b471
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/t104x.dtsi
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T104X Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019-2020 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e5500_power_isa.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: PowerPC,e5500@0 {
+			device_type = "cpu";
+			reg = <0>;
+			#cooling-cells = <2>;
+		};
+		cpu1: PowerPC,e5500@1 {
+			device_type = "cpu";
+			reg = <1>;
+			#cooling-cells = <2>;
+		};
+		cpu2: PowerPC,e5500@2 {
+			device_type = "cpu";
+			reg = <2>;
+			#cooling-cells = <2>;
+		};
+		cpu3: PowerPC,e5500@3 {
+			device_type = "cpu";
+			reg = <3>;
+			#cooling-cells = <2>;
+		};
+	};
+
+	soc: soc@ffe000000 {
+		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+		reg = <0xf 0xfe000000 0 0x00001000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "simple-bus";
+
+		mpic: pic@40000 {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <4>;
+			reg = <0x40000 0x40000>;
+			compatible = "fsl,mpic", "chrp,open-pic";
+			device_type = "open-pic";
+			clock-frequency = <0x0>;
+		};
+
+		espi0: spi@110000 {
+			compatible = "fsl,mpc8536-espi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x110000 0x1000>;
+			fsl,espi-num-chipselects = <4>;
+			status = "disabled";
+		};
+
+		usb0@210000 {
+			compatible = "fsl-usb2-mph";
+			reg = <0x210000 0x1000>;
+			phy_type = "utmi";
+		};
+
+		usb1@211000 {
+			compatible = "fsl-usb2-dr";
+			reg = <0x211000 0x1000>;
+			phy_type = "utmi";
+		};
+
+		sata: sata@220000 {
+			compatible = "fsl,pq-sata-v2";
+			reg = <0x220000 0x1000>;
+			interrupts = <68 0x2 0 0>;
+			sata-offset = <0x1000>;
+			sata-number = <2>;
+			sata-fpdma = <0>;
+		};
+
+		esdhc: esdhc@114000 {
+			compatible = "fsl,esdhc";
+			reg = <0x114000 0x1000>;
+			clock-frequency = <0>;
+		};
+		/include/ "qoriq-i2c-0.dtsi"
+		/include/ "qoriq-i2c-1.dtsi"
+	};
+
+	pcie@ffe240000 {
+		compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe240000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */
+	};
+
+	pcie@ffe250000 {
+		compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe250000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */
+	};
+
+	pcie@ffe260000 {
+		compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe260000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <2>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
+	};
+
+	pcie@ffe270000 {
+		compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe270000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <3>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-prefetchable memory */
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/t104xsi-pre.dtsi b/roms/u-boot/arch/powerpc/dts/t104xsi-pre.dtsi
new file mode 100644
index 000000000..025872cfe
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/t104xsi-pre.dtsi
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * T1040/T1042 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013-2014 Freescale Semiconductor Inc.
+ */
+
+/dts-v1/;
+
+/include/ "e5500_power_isa.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	aliases {
+		ccsr = &soc;
+		dcsr = &dcsr;
+
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		serial3 = &serial3;
+		pci0 = &pci0;
+		pci1 = &pci1;
+		pci2 = &pci2;
+		pci3 = &pci3;
+		usb0 = &usb0;
+		usb1 = &usb1;
+		sdhc = &sdhc;
+
+		crypto = &crypto;
+
+		fman0 = &fman0;
+		ethernet0 = &enet0;
+		ethernet1 = &enet1;
+		ethernet2 = &enet2;
+		ethernet3 = &enet3;
+		ethernet4 = &enet4;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: PowerPC,e5500@0 {
+			device_type = "cpu";
+			reg = <0>;
+			clocks = <&clockgen 1 0>;
+			next-level-cache = <&L2_1>;
+			#cooling-cells = <2>;
+			L2_1: l2-cache {
+				next-level-cache = <&cpc>;
+			};
+		};
+		cpu1: PowerPC,e5500@1 {
+			device_type = "cpu";
+			reg = <1>;
+			clocks = <&clockgen 1 1>;
+			next-level-cache = <&L2_2>;
+			#cooling-cells = <2>;
+			L2_2: l2-cache {
+				next-level-cache = <&cpc>;
+			};
+		};
+		cpu2: PowerPC,e5500@2 {
+			device_type = "cpu";
+			reg = <2>;
+			clocks = <&clockgen 1 2>;
+			next-level-cache = <&L2_3>;
+			#cooling-cells = <2>;
+			L2_3: l2-cache {
+				next-level-cache = <&cpc>;
+			};
+		};
+		cpu3: PowerPC,e5500@3 {
+			device_type = "cpu";
+			reg = <3>;
+			clocks = <&clockgen 1 3>;
+			next-level-cache = <&L2_4>;
+			#cooling-cells = <2>;
+			L2_4: l2-cache {
+				next-level-cache = <&cpc>;
+			};
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/t2080.dtsi b/roms/u-boot/arch/powerpc/dts/t2080.dtsi
new file mode 100644
index 000000000..7e446b18d
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/t2080.dtsi
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T2080/T2081 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2018,2020 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e6500_power_isa.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: PowerPC,e6500@0 {
+			device_type = "cpu";
+			reg = <0 1>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu1: PowerPC,e6500@2 {
+			device_type = "cpu";
+			reg = <2 3>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu2: PowerPC,e6500@4 {
+			device_type = "cpu";
+			reg = <4 5>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu3: PowerPC,e6500@6 {
+			device_type = "cpu";
+			reg = <6 7>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+	};
+
+	soc: soc@ffe000000 {
+		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+		reg = <0xf 0xfe000000 0 0x00001000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "simple-bus";
+
+		mpic: pic@40000 {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <4>;
+			reg = <0x40000 0x40000>;
+			compatible = "fsl,mpic";
+			device_type = "open-pic";
+			clock-frequency = <0x0>;
+		};
+
+		esdhc: esdhc@114000 {
+			compatible = "fsl,esdhc";
+			reg = <0x114000 0x1000>;
+			interrupts = <48 2 0 0>;
+			clock-frequency = <0>;
+			sdhci,auto-cmd12;
+			bus-width = <4>;
+			voltage-ranges = <1800 1800 3300 3300>;
+		};
+
+		espi0: spi@110000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,mpc8536-espi";
+			reg = <0x110000 0x1000>;
+			interrupts = <53 0x2 0 0>;
+			fsl,espi-num-chipselects = <4>;
+			status = "disabled";
+		};
+
+		usb0: usb@210000 {
+			compatible = "fsl-usb2-mph";
+			reg = <0x210000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <44 0x2 0 0>;
+			phy_type = "utmi";
+		};
+
+		usb1: usb@211000 {
+			compatible = "fsl-usb2-dr";
+			reg = <0x211000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <45 0x2 0 0>;
+			dr_mode = "host";
+			phy_type = "utmi";
+		};
+
+		sata: sata@220000 {
+			compatible = "fsl,pq-sata-v2";
+			reg = <0x220000 0x1000>;
+			interrupts = <68 0x2 0 0>;
+			sata-offset = <0x1000>;
+			sata-number = <2>;
+			sata-fpdma = <0>;
+		};
+		/include/ "qoriq-i2c-0.dtsi"
+		/include/ "qoriq-i2c-1.dtsi"
+	};
+
+	pcie@ffe240000 {
+		compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe240000 0x0 0x4000>;   /* registers */
+		law_trgt_if = <0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie@ffe250000 {
+		compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe250000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
+	};
+
+	pcie@ffe260000 {
+		compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe260000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <2>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-prefetchable memory */
+	};
+
+	pcie@ffe270000 {
+		compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe270000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <3>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x10000000>; /* non-prefetchable memory */
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/t2080qds.dts b/roms/u-boot/arch/powerpc/dts/t2080qds.dts
new file mode 100644
index 000000000..f9e786b23
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/t2080qds.dts
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T2080QDS Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2018 NXP
+ */
+
+/include/ "t2080.dtsi"
+
+/ {
+	model = "fsl,T2080QDS";
+	compatible = "fsl,T2080QDS";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	aliases {
+		spi0 = &espi0;
+	};
+};
+
+&espi0 {
+
+	status = "okay";
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q128a11", "jedec,spi-nor"; /* 16MB */
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+	};
+
+	flash@1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "sst,sst25wf040", "jedec,spi-nor";
+		reg = <1>;
+		spi-max-frequency = <10000000>;
+	};
+
+	flash@2 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "eon,en25s64", "jedec,spi-nor";
+		reg = <2>;
+		spi-max-frequency = <10000000>;
+	};
+
+};
diff --git a/roms/u-boot/arch/powerpc/dts/t2080rdb.dts b/roms/u-boot/arch/powerpc/dts/t2080rdb.dts
new file mode 100644
index 000000000..4de814ea8
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/t2080rdb.dts
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T2080RDB Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019-2021 NXP
+ */
+
+/include/ "t2080.dtsi"
+
+/ {
+	model = "fsl,T2080RDB";
+	compatible = "fsl,T2080RDB";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	aliases {
+		spi0 = &espi0;
+	};
+};
+
+&soc {
+	fman@400000 {
+		ethernet@e0000 {
+			phy-handle = <&xg_aq1202_phy3>;
+			phy-connection-type = "xgmii";
+		};
+
+		ethernet@e2000 {
+			phy-handle = <&xg_aq1202_phy4>;
+			phy-connection-type = "xgmii";
+		};
+
+		ethernet@e4000 {
+			phy-handle = <&rgmii_phy1>;
+			phy-connection-type = "rgmii";
+		};
+
+		ethernet@e6000 {
+			phy-handle = <&rgmii_phy2>;
+			phy-connection-type = "rgmii";
+		};
+
+		ethernet@f0000 {
+			phy-handle = <&xg_cs4315_phy2>;
+			phy-connection-type = "xgmii";
+		};
+
+		ethernet@f2000 {
+			phy-handle = <&xg_cs4315_phy1>;
+			phy-connection-type = "xgmii";
+		};
+
+		mdio@fc000 {
+			rgmii_phy1: ethernet-phy@1 {
+				reg = <0x1>;
+			};
+			rgmii_phy2: ethernet-phy@2 {
+				reg = <0x2>;
+			};
+		};
+
+		mdio@fd000 {
+			xg_cs4315_phy1: ethernet-phy@c {
+				compatible = "ethernet-phy-id13e5.1002";
+				reg = <0xc>;
+			};
+
+			xg_cs4315_phy2: ethernet-phy@d {
+				compatible = "ethernet-phy-id13e5.1002";
+				reg = <0xd>;
+			};
+
+			xg_aq1202_phy3: ethernet-phy@0 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				reg = <0x0>;
+			};
+
+#ifdef CONFIG_T2080RDB_REV_D
+			xg_aq1202_phy4: ethernet-phy@8 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				reg = <0x8>;
+			};
+#else
+			xg_aq1202_phy4: ethernet-phy@1 {
+				compatible = "ethernet-phy-ieee802.3-c45";
+				reg = <0x1>;
+			};
+#endif
+		};
+	};
+};
+
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor"; /* 16MB */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
+};
+
+&i2c0 {
+	status = "okay";
+	rtc@68 {
+		compatible = "dallas,ds1339";
+		reg = <0x68>;
+	};
+};
+
+/include/ "t2080si-post.dtsi"
diff --git a/roms/u-boot/arch/powerpc/dts/t2080si-post.dtsi b/roms/u-boot/arch/powerpc/dts/t2080si-post.dtsi
new file mode 100644
index 000000000..d8ef579cb
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/t2080si-post.dtsi
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * T2080 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2021 NXP
+ *
+ */
+&soc {
+
+/include/ "qoriq-clockgen2.dtsi"
+/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-gpio-1.dtsi"
+/include/ "qoriq-gpio-2.dtsi"
+/include/ "qoriq-gpio-3.dtsi"
+
+/include/ "qoriq-fman3-0.dtsi"
+/include/ "qoriq-fman3-0-10g-0-best-effort.dtsi"
+/include/ "qoriq-fman3-0-10g-1-best-effort.dtsi"
+/include/ "qoriq-fman3-0-1g-2.dtsi"
+/include/ "qoriq-fman3-0-1g-3.dtsi"
+/include/ "qoriq-fman3-0-10g-0.dtsi"
+/include/ "qoriq-fman3-0-10g-1.dtsi"
+	fman@400000 {
+		enet0: ethernet@e0000 {
+		};
+
+		enet1: ethernet@e2000 {
+		};
+
+		enet2: ethernet@e4000 {
+		};
+
+		enet3: ethernet@e6000 {
+		};
+
+		enet6: ethernet@f0000 {
+		};
+
+		enet7: ethernet@f2000 {
+		};
+
+		mdio@fc000 {
+			interrupts = <100 1 0 0>;
+		};
+
+		mdio@fd000 {
+			interrupts = <101 1 0 0>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/t4240.dtsi b/roms/u-boot/arch/powerpc/dts/t4240.dtsi
new file mode 100644
index 000000000..498da4f79
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/t4240.dtsi
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T4240 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ * Copyright 2019-2020 NXP
+ */
+
+/dts-v1/;
+
+/include/ "e6500_power_isa.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: PowerPC,e6500@0 {
+			device_type = "cpu";
+			reg = <0 1>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu1: PowerPC,e6500@2 {
+			device_type = "cpu";
+			reg = <2 3>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu2: PowerPC,e6500@4 {
+			device_type = "cpu";
+			reg = <4 5>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu3: PowerPC,e6500@6 {
+			device_type = "cpu";
+			reg = <6 7>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu4: PowerPC,e6500@8 {
+			device_type = "cpu";
+			reg = <8 9>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu5: PowerPC,e6500@10 {
+			device_type = "cpu";
+			reg = <10 11>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu6: PowerPC,e6500@12 {
+			device_type = "cpu";
+			reg = <12 13>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu7: PowerPC,e6500@14 {
+			device_type = "cpu";
+			reg = <14 15>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu8: PowerPC,e6500@16 {
+			device_type = "cpu";
+			reg = <16 17>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu9: PowerPC,e6500@18 {
+			device_type = "cpu";
+			reg = <18 19>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu10: PowerPC,e6500@20 {
+			device_type = "cpu";
+			reg = <20 21>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+		cpu11: PowerPC,e6500@22 {
+			device_type = "cpu";
+			reg = <22 23>;
+			fsl,portid-mapping = <0x80000000>;
+		};
+	};
+
+	soc: soc@ffe000000 {
+		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+		reg = <0xf 0xfe000000 0 0x00001000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "simple-bus";
+
+		mpic: pic@40000 {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <4>;
+			reg = <0x40000 0x40000>;
+			compatible = "fsl,mpic";
+			device_type = "open-pic";
+			clock-frequency = <0x0>;
+		};
+
+		espi0: spi@110000 {
+			compatible = "fsl,mpc8536-espi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x110000 0x1000>;
+			fsl,espi-num-chipselects = <4>;
+			status = "disabled";
+		};
+
+		usb@210000 {
+			compatible = "fsl-usb2-mph";
+			reg = <0x210000 0x1000>;
+			phy_type = "utmi";
+		};
+
+		usb@211000 {
+			compatible = "fsl-usb2-dr";
+			reg = <0x211000 0x1000>;
+			phy_type = "utmi";
+		};
+
+		sata: sata@220000 {
+			compatible = "fsl,pq-sata-v2";
+			reg = <0x220000 0x1000>;
+			interrupts = <68 0x2 0 0>;
+			sata-offset = <0x1000>;
+			sata-number = <2>;
+			sata-fpdma = <0>;
+		};
+
+		esdhc: esdhc@114000 {
+			compatible = "fsl,esdhc";
+			reg = <0x114000 0x1000>;
+			clock-frequency = <0>;
+		};
+
+		/include/ "qoriq-i2c-0.dtsi"
+		/include/ "qoriq-i2c-1.dtsi"
+	};
+
+	pcie@ffe240000 {
+		compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe240000 0x0 0x4000>;   /* registers */
+		law_trgt_if = <0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie@ffe250000 {
+		compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe250000 0x0 0x4000>;   /* registers */
+		law_trgt_if = <1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie@ffe260000 {
+		compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe260000 0x0 0x4000>;   /* registers */
+		law_trgt_if = <2>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie@ffe270000 {
+		compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe270000 0x0 0x4000>;   /* registers */
+		law_trgt_if = <3>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/t4240rdb.dts b/roms/u-boot/arch/powerpc/dts/t4240rdb.dts
new file mode 100644
index 000000000..b3251e330
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/t4240rdb.dts
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * T4240RDB Device Tree Source
+ *
+ * Copyright 2013 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2019-2021 NXP
+ */
+
+/include/ "t4240.dtsi"
+
+/ {
+	model = "fsl,T4240RDB";
+	compatible = "fsl,T4240RDB";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	aliases {
+		spi0 = &espi0;
+	};
+};
+
+&soc {
+	fman@400000 {
+		ethernet@e0000 {
+			phy-handle = <&sgmiiphy21>;
+			phy-connection-type = "sgmii";
+		};
+
+		ethernet@e2000 {
+			phy-handle = <&sgmiiphy22>;
+			phy-connection-type = "sgmii";
+		};
+
+		ethernet@e4000 {
+			phy-handle = <&sgmiiphy23>;
+			phy-connection-type = "sgmii";
+		};
+
+		ethernet@e6000 {
+			phy-handle = <&sgmiiphy24>;
+			phy-connection-type = "sgmii";
+		};
+
+		ethernet@e8000 {
+			status = "disabled";
+		};
+
+		ethernet@ea000 {
+			status = "disabled";
+		};
+
+		ethernet@f0000 {
+			phy-handle = <&xfiphy1>;
+			phy-connection-type = "xgmii";
+		};
+
+		ethernet@f2000 {
+			phy-handle = <&xfiphy2>;
+			phy-connection-type = "xgmii";
+		};
+	};
+
+	fman@500000 {
+		ethernet@e0000 {
+			phy-handle = <&sgmiiphy41>;
+			phy-connection-type = "sgmii";
+		};
+
+		ethernet@e2000 {
+			phy-handle = <&sgmiiphy42>;
+			phy-connection-type = "sgmii";
+		};
+
+		ethernet@e4000 {
+			phy-handle = <&sgmiiphy43>;
+			phy-connection-type = "sgmii";
+		};
+
+		ethernet@e6000 {
+			phy-handle = <&sgmiiphy44>;
+			phy-connection-type = "sgmii";
+		};
+
+		ethernet@e8000 {
+			status = "disabled";
+		};
+
+		ethernet@ea000 {
+			status = "disabled";
+		};
+
+		ethernet@f0000 {
+			phy-handle = <&xfiphy3>;
+			phy-connection-type = "xgmii";
+		};
+
+		ethernet@f2000 {
+			phy-handle = <&xfiphy4>;
+			phy-connection-type = "xgmii";
+		};
+
+		mdio@5fc000 {
+			sgmiiphy21: ethernet-phy@0 {
+				reg = <0x0>;
+			};
+
+			sgmiiphy22: ethernet-phy@1 {
+				reg = <0x1>;
+			};
+
+			sgmiiphy23: ethernet-phy@2 {
+				reg = <0x2>;
+			};
+
+			sgmiiphy24: ethernet-phy@3 {
+				reg = <0x3>;
+			};
+
+			sgmiiphy41: ethernet-phy@4 {
+				reg = <0x4>;
+			};
+
+			sgmiiphy42: ethernet-phy@5 {
+				reg = <0x5>;
+			};
+
+			sgmiiphy43: ethernet-phy@6 {
+				reg = <0x6>;
+			};
+
+			sgmiiphy44: ethernet-phy@7 {
+				reg = <0x7>;
+			};
+		};
+
+		mdio@5fd000 {
+			xfiphy1: ethernet-phy@10 {
+				compatible = "ethernet-phy-id13e5.1002";
+				reg = <0x10>;
+			};
+
+			xfiphy2: ethernet-phy@11 {
+				compatible = "ethernet-phy-id13e5.1002";
+				reg = <0x11>;
+			};
+
+			xfiphy3: ethernet-phy@13 {
+				compatible = "ethernet-phy-id13e5.1002";
+				reg = <0x13>;
+			};
+
+			xfiphy4: ethernet-phy@12 {
+				compatible = "ethernet-phy-id13e5.1002";
+				reg = <0x12>;
+			};
+		};
+	};
+};
+
+&espi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <10000000>; /* input clock */
+	};
+};
+
+/include/ "t4240si-post.dtsi"
diff --git a/roms/u-boot/arch/powerpc/dts/t4240si-post.dtsi b/roms/u-boot/arch/powerpc/dts/t4240si-post.dtsi
new file mode 100644
index 000000000..a596f48b5
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/t4240si-post.dtsi
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * T4240 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ * Copyright 2021 NXP
+ *
+ */
+&soc {
+/include/ "qoriq-clockgen2.dtsi"
+/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-gpio-1.dtsi"
+/include/ "qoriq-gpio-2.dtsi"
+/include/ "qoriq-gpio-3.dtsi"
+
+/include/ "qoriq-fman3-0.dtsi"
+/include/ "qoriq-fman3-0-1g-0.dtsi"
+/include/ "qoriq-fman3-0-1g-1.dtsi"
+/include/ "qoriq-fman3-0-1g-2.dtsi"
+/include/ "qoriq-fman3-0-1g-3.dtsi"
+/include/ "qoriq-fman3-0-1g-4.dtsi"
+/include/ "qoriq-fman3-0-1g-5.dtsi"
+/include/ "qoriq-fman3-0-10g-0.dtsi"
+/include/ "qoriq-fman3-0-10g-1.dtsi"
+	fman@400000 {
+		enet0: ethernet@e0000 {
+		};
+
+		enet1: ethernet@e2000 {
+		};
+
+		enet2: ethernet@e4000 {
+		};
+
+		enet3: ethernet@e6000 {
+		};
+
+		enet4: ethernet@e8000 {
+		};
+
+		enet5: ethernet@ea000 {
+		};
+
+		enet6: ethernet@f0000 {
+		};
+
+		enet7: ethernet@f2000 {
+		};
+
+		mdio@fc000 {
+			status = "disabled";
+		};
+
+		mdio@fd000 {
+			status = "disabled";
+		};
+	};
+
+/include/ "qoriq-fman3-1.dtsi"
+/include/ "qoriq-fman3-1-1g-0.dtsi"
+/include/ "qoriq-fman3-1-1g-1.dtsi"
+/include/ "qoriq-fman3-1-1g-2.dtsi"
+/include/ "qoriq-fman3-1-1g-3.dtsi"
+/include/ "qoriq-fman3-1-1g-4.dtsi"
+/include/ "qoriq-fman3-1-1g-5.dtsi"
+/include/ "qoriq-fman3-1-10g-0.dtsi"
+/include/ "qoriq-fman3-1-10g-1.dtsi"
+	fman@500000 {
+		enet8: ethernet@e0000 {
+		};
+
+		enet9: ethernet@e2000 {
+		};
+
+		enet10: ethernet@e4000 {
+		};
+
+		enet11: ethernet@e6000 {
+		};
+
+		enet12: ethernet@e8000 {
+		};
+
+		enet13: ethernet@ea000 {
+		};
+
+		enet14: ethernet@f0000 {
+		};
+
+		enet15: ethernet@f2000 {
+		};
+
+		mdio@5fc000 {
+			interrupts = <100 1 0 0>;
+		};
+
+		mdio@5fd000 {
+			interrupts = <101 1 0 0>;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/powerpc/dts/u-boot.dtsi b/roms/u-boot/arch/powerpc/dts/u-boot.dtsi
new file mode 100644
index 000000000..9661f4dc8
--- /dev/null
+++ b/roms/u-boot/arch/powerpc/dts/u-boot.dtsi
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <config.h>
+
+/ {
+	binman {
+		filename = "u-boot-with-dtb.bin";
+		skip-at-start = <CONFIG_SYS_TEXT_BASE>;
+		sort-by-offset;
+		pad-byte = <0xff>;
+		size = <CONFIG_SYS_MONITOR_LEN>;
+
+		u-boot-with-ucode-ptr {
+			offset = <CONFIG_SYS_TEXT_BASE>;
+			optional-ucode;
+		};
+
+		u-boot-dtb-with-ucode {
+#ifdef CONFIG_MPC85xx
+			align = <256>;
+#endif
+		};
+#ifdef CONFIG_MPC85XX_HAVE_RESET_VECTOR
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#endif
+		powerpc-mpc85xx-bootpg-resetvec {
+			offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>;
+		};
+#endif
+	};
+};