Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

112 files changed, 12813 insertions, 0 deletions

diff --git a/roms/u-boot/arch/riscv/Kconfig b/roms/u-boot/arch/riscv/Kconfig
new file mode 100644
index 000000000..b3d7fd84c
--- /dev/null
+++ b/roms/u-boot/arch/riscv/Kconfig
@@ -0,0 +1,368 @@
+menu "RISC-V architecture"
+	depends on RISCV
+
+config SYS_ARCH
+	default "riscv"
+
+choice
+	prompt "Target select"
+	optional
+
+config TARGET_AX25_AE350
+	bool "Support ax25-ae350"
+
+config TARGET_MICROCHIP_ICICLE
+	bool "Support Microchip PolarFire-SoC Icicle Board"
+
+config TARGET_QEMU_VIRT
+	bool "Support QEMU Virt Board"
+
+config TARGET_SIFIVE_UNLEASHED
+	bool "Support SiFive Unleashed Board"
+
+config TARGET_SIFIVE_UNMATCHED
+	bool "Support SiFive Unmatched Board"
+
+config TARGET_SIPEED_MAIX
+	bool "Support Sipeed Maix Board"
+
+endchoice
+
+config SYS_ICACHE_OFF
+	bool "Do not enable icache"
+	default n
+	help
+	  Do not enable instruction cache in U-Boot.
+
+config SPL_SYS_ICACHE_OFF
+	bool "Do not enable icache in SPL"
+	depends on SPL
+	default SYS_ICACHE_OFF
+	help
+	  Do not enable instruction cache in SPL.
+
+config SYS_DCACHE_OFF
+	bool "Do not enable dcache"
+	default n
+	help
+	  Do not enable data cache in U-Boot.
+
+config SPL_SYS_DCACHE_OFF
+	bool "Do not enable dcache in SPL"
+	depends on SPL
+	default SYS_DCACHE_OFF
+	help
+	  Do not enable data cache in SPL.
+
+# board-specific options below
+source "board/AndesTech/ax25-ae350/Kconfig"
+source "board/emulation/qemu-riscv/Kconfig"
+source "board/microchip/mpfs_icicle/Kconfig"
+source "board/sifive/unleashed/Kconfig"
+source "board/sifive/unmatched/Kconfig"
+source "board/sipeed/maix/Kconfig"
+
+# platform-specific options below
+source "arch/riscv/cpu/ax25/Kconfig"
+source "arch/riscv/cpu/fu540/Kconfig"
+source "arch/riscv/cpu/fu740/Kconfig"
+source "arch/riscv/cpu/generic/Kconfig"
+
+# architecture-specific options below
+
+choice
+	prompt "Base ISA"
+	default ARCH_RV32I
+
+config ARCH_RV32I
+	bool "RV32I"
+	select 32BIT
+	help
+	  Choose this option to target the RV32I base integer instruction set.
+
+config ARCH_RV64I
+	bool "RV64I"
+	select 64BIT
+	select PHYS_64BIT
+	help
+	  Choose this option to target the RV64I base integer instruction set.
+
+endchoice
+
+choice
+	prompt "Code Model"
+	default CMODEL_MEDLOW
+
+config CMODEL_MEDLOW
+	bool "medium low code model"
+	help
+	  U-Boot and its statically defined symbols must lie within a single 2 GiB
+	  address range and must lie between absolute addresses -2 GiB and +2 GiB.
+
+config CMODEL_MEDANY
+	bool "medium any code model"
+	help
+	  U-Boot and its statically defined symbols must be within any single 2 GiB
+	  address range.
+
+endchoice
+
+choice
+	prompt "Run Mode"
+	default RISCV_MMODE
+
+config RISCV_MMODE
+	bool "Machine"
+	help
+	  Choose this option to build U-Boot for RISC-V M-Mode.
+
+config RISCV_SMODE
+	bool "Supervisor"
+	help
+	  Choose this option to build U-Boot for RISC-V S-Mode.
+
+endchoice
+
+choice
+	prompt "SPL Run Mode"
+	default SPL_RISCV_MMODE
+	depends on SPL
+
+config SPL_RISCV_MMODE
+	bool "Machine"
+	help
+	  Choose this option to build U-Boot SPL for RISC-V M-Mode.
+
+config SPL_RISCV_SMODE
+	bool "Supervisor"
+	help
+	  Choose this option to build U-Boot SPL for RISC-V S-Mode.
+
+endchoice
+
+config RISCV_ISA_C
+	bool "Emit compressed instructions"
+	default y
+	help
+	  Adds "C" to the ISA subsets that the toolchain is allowed to emit
+	  when building U-Boot, which results in compressed instructions in the
+	  U-Boot binary.
+
+config RISCV_ISA_A
+	def_bool y
+
+config 32BIT
+	bool
+
+config 64BIT
+	bool
+
+config DMA_ADDR_T_64BIT
+	bool
+	default y if 64BIT
+
+config SIFIVE_CLINT
+	bool
+	depends on RISCV_MMODE
+	help
+	  The SiFive CLINT block holds memory-mapped control and status registers
+	  associated with software and timer interrupts.
+
+config SPL_SIFIVE_CLINT
+	bool
+	depends on SPL_RISCV_MMODE
+	help
+	  The SiFive CLINT block holds memory-mapped control and status registers
+	  associated with software and timer interrupts.
+
+config ANDES_PLIC
+	bool
+	depends on RISCV_MMODE || SPL_RISCV_MMODE
+	select REGMAP
+	select SYSCON
+	select SPL_REGMAP if SPL
+	select SPL_SYSCON if SPL
+	help
+	  The Andes PLIC block holds memory-mapped claim and pending registers
+	  associated with software interrupt.
+
+config SYS_MALLOC_F_LEN
+	default 0x1000
+
+config SMP
+	bool "Symmetric Multi-Processing"
+	depends on SBI_V01 || !RISCV_SMODE
+	help
+	  This enables support for systems with more than one CPU. If
+	  you say N here, U-Boot will run on single and multiprocessor
+	  machines, but will use only one CPU of a multiprocessor
+	  machine. If you say Y here, U-Boot will run on many, but not
+	  all, single processor machines.
+
+config SPL_SMP
+	bool "Symmetric Multi-Processing in SPL"
+	depends on SPL && SPL_RISCV_MMODE
+	default y
+	help
+	  This enables support for systems with more than one CPU in SPL.
+	  If you say N here, U-Boot SPL will run on single and multiprocessor
+	  machines, but will use only one CPU of a multiprocessor
+	  machine. If you say Y here, U-Boot SPL will run on many, but not
+	  all, single processor machines.
+
+config NR_CPUS
+	int "Maximum number of CPUs (2-32)"
+	range 2 32
+	depends on SMP || SPL_SMP
+	default 8
+	help
+	  On multiprocessor machines, U-Boot sets up a stack for each CPU.
+	  Stack memory is pre-allocated. U-Boot must therefore know the
+	  maximum number of CPUs that may be present.
+
+config SBI
+	bool
+	default y if RISCV_SMODE || SPL_RISCV_SMODE
+
+choice
+	prompt "SBI support"
+	default SBI_V02
+
+config SBI_V01
+	bool "SBI v0.1 support"
+	depends on SBI
+	help
+	  This config allows kernel to use SBI v0.1 APIs. This will be
+	  deprecated in future once legacy M-mode software are no longer in use.
+
+config SBI_V02
+	bool "SBI v0.2 support"
+	depends on SBI
+	help
+	  This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
+	  scalable and extendable to handle future needs for RISC-V supervisor
+	  interfaces. For example, with SBI v0.2 HSM extension, only a single
+	  hart need to boot and enter operating system. The booting hart can
+	  bring up secondary harts one by one afterwards.
+
+	  Choose this option if OpenSBI v0.7 or above release is used together
+	  with U-Boot.
+
+endchoice
+
+config SBI_IPI
+	bool
+	depends on SBI
+	default y if RISCV_SMODE || SPL_RISCV_SMODE
+	depends on SMP
+
+config XIP
+	bool "XIP mode"
+	help
+	  XIP (eXecute In Place) is a method for executing code directly
+	  from a NOR flash memory without copying the code to ram.
+	  Say yes here if U-Boot boots from flash directly.
+
+config SHOW_REGS
+	bool "Show registers on unhandled exception"
+
+config RISCV_PRIV_1_9
+	bool "Use version 1.9 of the RISC-V priviledged specification"
+	help
+	  Older versions of the RISC-V priviledged specification had
+	  separate counter enable CSRs for each privilege mode. Writing
+	  to the unified mcounteren CSR on a processor implementing the
+	  old specification will result in an illegal instruction
+	  exception. In addition to counter CSR changes, the way virtual
+	  memory is configured was also changed.
+
+config STACK_SIZE_SHIFT
+	int
+	default 14
+
+config OF_BOARD_FIXUP
+	default y if OF_SEPARATE && RISCV_SMODE
+
+menu "Use assembly optimized implementation of memory routines"
+
+config USE_ARCH_MEMCPY
+	bool "Use an assembly optimized implementation of memcpy"
+	default y
+	help
+	  Enable the generation of an optimized version of memcpy.
+	  Such an implementation may be faster under some conditions
+	  but may increase the binary size.
+
+config SPL_USE_ARCH_MEMCPY
+	bool "Use an assembly optimized implementation of memcpy for SPL"
+	default y if USE_ARCH_MEMCPY
+	depends on SPL
+	help
+	  Enable the generation of an optimized version of memcpy.
+	  Such an implementation may be faster under some conditions
+	  but may increase the binary size.
+
+config TPL_USE_ARCH_MEMCPY
+	bool "Use an assembly optimized implementation of memcpy for TPL"
+	default y if USE_ARCH_MEMCPY
+	depends on TPL
+	help
+	  Enable the generation of an optimized version of memcpy.
+	  Such an implementation may be faster under some conditions
+	  but may increase the binary size.
+
+config USE_ARCH_MEMMOVE
+	bool "Use an assembly optimized implementation of memmove"
+	default y
+	help
+	  Enable the generation of an optimized version of memmove.
+	  Such an implementation may be faster under some conditions
+	  but may increase the binary size.
+
+config SPL_USE_ARCH_MEMMOVE
+	bool "Use an assembly optimized implementation of memmove for SPL"
+	default y if USE_ARCH_MEMCPY
+	depends on SPL
+	help
+	  Enable the generation of an optimized version of memmove.
+	  Such an implementation may be faster under some conditions
+	  but may increase the binary size.
+
+config TPL_USE_ARCH_MEMMOVE
+	bool "Use an assembly optimized implementation of memmove for TPL"
+	default y if USE_ARCH_MEMCPY
+	depends on TPL
+	help
+	  Enable the generation of an optimized version of memmove.
+	  Such an implementation may be faster under some conditions
+	  but may increase the binary size.
+
+config USE_ARCH_MEMSET
+	bool "Use an assembly optimized implementation of memset"
+	default y
+	help
+	  Enable the generation of an optimized version of memset.
+	  Such an implementation may be faster under some conditions
+	  but may increase the binary size.
+
+config SPL_USE_ARCH_MEMSET
+	bool "Use an assembly optimized implementation of memset for SPL"
+	default y if USE_ARCH_MEMSET
+	depends on SPL
+	help
+	  Enable the generation of an optimized version of memset.
+	  Such an implementation may be faster under some conditions
+	  but may increase the binary size.
+
+config TPL_USE_ARCH_MEMSET
+	bool "Use an assembly optimized implementation of memset for TPL"
+	default y if USE_ARCH_MEMSET
+	depends on TPL
+	help
+	  Enable the generation of an optimized version of memset.
+	  Such an implementation may be faster under some conditions
+	  but may increase the binary size.
+
+endmenu
+
+endmenu
diff --git a/roms/u-boot/arch/riscv/Makefile b/roms/u-boot/arch/riscv/Makefile
new file mode 100644
index 000000000..0b80eb8d8
--- /dev/null
+++ b/roms/u-boot/arch/riscv/Makefile
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2017 Andes Technology Corporation.
+# Rick Chen, Andes Technology Corporation <rick@andestech.com>
+
+ifeq ($(CONFIG_ARCH_RV64I),y)
+	ARCH_BASE = rv64im
+	ABI = lp64
+endif
+ifeq ($(CONFIG_ARCH_RV32I),y)
+	ARCH_BASE = rv32im
+	ABI = ilp32
+endif
+ifeq ($(CONFIG_RISCV_ISA_A),y)
+	ARCH_A = a
+endif
+ifeq ($(CONFIG_RISCV_ISA_C),y)
+	ARCH_C = c
+endif
+ifeq ($(CONFIG_CMODEL_MEDLOW),y)
+	CMODEL = medlow
+endif
+ifeq ($(CONFIG_CMODEL_MEDANY),y)
+	CMODEL = medany
+endif
+
+ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
+	     -mcmodel=$(CMODEL)
+
+PLATFORM_CPPFLAGS	+= $(ARCH_FLAGS)
+CFLAGS_EFI		+= $(ARCH_FLAGS)
+
+head-y := arch/riscv/cpu/start.o
+
+libs-y += arch/riscv/cpu/
+libs-y += arch/riscv/cpu/$(CPU)/
+libs-y += arch/riscv/lib/
diff --git a/roms/u-boot/arch/riscv/config.mk b/roms/u-boot/arch/riscv/config.mk
new file mode 100644
index 000000000..1ebce5bd6
--- /dev/null
+++ b/roms/u-boot/arch/riscv/config.mk
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (c) 2017 Microsemi Corporation.
+# Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
+#
+# Copyright (C) 2017 Andes Technology Corporation
+# Rick Chen, Andes Technology Corporation <rick@andestech.com>
+#
+
+32bit-emul		:= elf32lriscv
+64bit-emul		:= elf64lriscv
+
+ifdef CONFIG_32BIT
+KBUILD_LDFLAGS		+= -m $(32bit-emul)
+EFI_LDS			:= elf_riscv32_efi.lds
+endif
+
+ifdef CONFIG_64BIT
+KBUILD_LDFLAGS		+= -m $(64bit-emul)
+EFI_LDS			:= elf_riscv64_efi.lds
+endif
+
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000
+
+PLATFORM_CPPFLAGS	+= -ffixed-gp -fpic
+PLATFORM_RELFLAGS	+= -fno-common -gdwarf-2 -ffunction-sections \
+			   -fdata-sections
+LDFLAGS_u-boot		+= --gc-sections -static -pie
+
+EFI_CRT0		:= crt0_riscv_efi.o
+EFI_RELOC		:= reloc_riscv_efi.o
diff --git a/roms/u-boot/arch/riscv/cpu/Makefile b/roms/u-boot/arch/riscv/cpu/Makefile
new file mode 100644
index 000000000..6bf6f911c
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+
+extra-y = start.o
+
+obj-y += cpu.o mtrap.o
diff --git a/roms/u-boot/arch/riscv/cpu/ax25/Kconfig b/roms/u-boot/arch/riscv/cpu/ax25/Kconfig
new file mode 100644
index 000000000..941d963ec
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/ax25/Kconfig
@@ -0,0 +1,24 @@
+config RISCV_NDS
+	bool
+	select ARCH_EARLY_INIT_R
+	imply CPU
+	imply CPU_RISCV
+	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
+	imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
+	imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE)
+	imply SPL_CPU
+	imply SPL_OPENSBI
+	imply SPL_LOAD_FIT
+	help
+	  Run U-Boot on AndeStar V5 platforms and use some specific features
+	  which are provided by Andes Technology AndeStar V5 families.
+
+if RISCV_NDS
+
+config RISCV_NDS_CACHE
+	bool "AndeStar V5 families specific cache support"
+	depends on RISCV_MMODE || SPL_RISCV_MMODE
+	help
+	  Provide Andes Technology AndeStar V5 families specific cache support.
+
+endif
diff --git a/roms/u-boot/arch/riscv/cpu/ax25/Makefile b/roms/u-boot/arch/riscv/cpu/ax25/Makefile
new file mode 100644
index 000000000..318baccb0
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/ax25/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2017 Andes Technology Corporation
+# Rick Chen, Andes Technology Corporation <rick@andestech.com>
+
+obj-y	:= cpu.o
+obj-y	+= cache.o
diff --git a/roms/u-boot/arch/riscv/cpu/ax25/cache.c b/roms/u-boot/arch/riscv/cpu/ax25/cache.c
new file mode 100644
index 000000000..35f23c748
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/ax25/cache.c
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <asm/cache.h>
+#include <dm/uclass-internal.h>
+#include <cache.h>
+#include <asm/csr.h>
+
+#ifdef CONFIG_RISCV_NDS_CACHE
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+/* mcctlcommand */
+#define CCTL_REG_MCCTLCOMMAND_NUM	0x7cc
+
+/* D-cache operation */
+#define CCTL_L1D_WBINVAL_ALL	6
+#endif
+#endif
+
+#ifdef CONFIG_V5L2_CACHE
+static void _cache_enable(void)
+{
+	struct udevice *dev = NULL;
+
+	uclass_find_first_device(UCLASS_CACHE, &dev);
+
+	if (dev)
+		cache_enable(dev);
+}
+
+static void _cache_disable(void)
+{
+	struct udevice *dev = NULL;
+
+	uclass_find_first_device(UCLASS_CACHE, &dev);
+
+	if (dev)
+		cache_disable(dev);
+}
+#endif
+
+void flush_dcache_all(void)
+{
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
+#ifdef CONFIG_RISCV_NDS_CACHE
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+	csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
+#endif
+#endif
+#endif
+}
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+	flush_dcache_all();
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+	flush_dcache_all();
+}
+
+void icache_enable(void)
+{
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
+#ifdef CONFIG_RISCV_NDS_CACHE
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+	asm volatile (
+		"csrr t1, mcache_ctl\n\t"
+		"ori t0, t1, 0x1\n\t"
+		"csrw mcache_ctl, t0\n\t"
+	);
+#endif
+#endif
+#endif
+}
+
+void icache_disable(void)
+{
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
+#ifdef CONFIG_RISCV_NDS_CACHE
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+	asm volatile (
+		"fence.i\n\t"
+		"csrr t1, mcache_ctl\n\t"
+		"andi t0, t1, ~0x1\n\t"
+		"csrw mcache_ctl, t0\n\t"
+	);
+#endif
+#endif
+#endif
+}
+
+void dcache_enable(void)
+{
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+#ifdef CONFIG_RISCV_NDS_CACHE
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+	asm volatile (
+		"csrr t1, mcache_ctl\n\t"
+		"ori t0, t1, 0x2\n\t"
+		"csrw mcache_ctl, t0\n\t"
+	);
+#endif
+#ifdef CONFIG_V5L2_CACHE
+	_cache_enable();
+#endif
+#endif
+#endif
+}
+
+void dcache_disable(void)
+{
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+#ifdef CONFIG_RISCV_NDS_CACHE
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+	csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
+	asm volatile (
+		"csrr t1, mcache_ctl\n\t"
+		"andi t0, t1, ~0x2\n\t"
+		"csrw mcache_ctl, t0\n\t"
+	);
+#endif
+#ifdef CONFIG_V5L2_CACHE
+	_cache_disable();
+#endif
+#endif
+#endif
+}
+
+int icache_status(void)
+{
+	int ret = 0;
+
+#ifdef CONFIG_RISCV_NDS_CACHE
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+	asm volatile (
+		"csrr t1, mcache_ctl\n\t"
+		"andi	%0, t1, 0x01\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+#endif
+#endif
+
+	return ret;
+}
+
+int dcache_status(void)
+{
+	int ret = 0;
+
+#ifdef CONFIG_RISCV_NDS_CACHE
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+	asm volatile (
+		"csrr t1, mcache_ctl\n\t"
+		"andi	%0, t1, 0x02\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+#endif
+#endif
+
+	return ret;
+}
diff --git a/roms/u-boot/arch/riscv/cpu/ax25/cpu.c b/roms/u-boot/arch/riscv/cpu/ax25/cpu.c
new file mode 100644
index 000000000..f092600e1
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/ax25/cpu.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+/* CPU specific code */
+#include <common.h>
+#include <cpu_func.h>
+#include <irq_func.h>
+#include <asm/cache.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+	disable_interrupts();
+
+	/* turn off I/D-cache */
+	cache_flush();
+	icache_disable();
+	dcache_disable();
+
+	return 0;
+}
diff --git a/roms/u-boot/arch/riscv/cpu/cpu.c b/roms/u-boot/arch/riscv/cpu/cpu.c
new file mode 100644
index 000000000..c894ac10b
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/cpu.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <cpu.h>
+#include <dm.h>
+#include <init.h>
+#include <log.h>
+#include <asm/encoding.h>
+#include <dm/uclass-internal.h>
+#include <linux/bitops.h>
+
+/*
+ * The variables here must be stored in the data section since they are used
+ * before the bss section is available.
+ */
+#ifdef CONFIG_OF_PRIOR_STAGE
+phys_addr_t prior_stage_fdt_address __section(".data");
+#endif
+#ifndef CONFIG_XIP
+u32 hart_lottery __section(".data") = 0;
+
+/*
+ * The main hart running U-Boot has acquired available_harts_lock until it has
+ * finished initialization of global data.
+ */
+u32 available_harts_lock = 1;
+#endif
+
+static inline bool supports_extension(char ext)
+{
+#ifdef CONFIG_CPU
+	struct udevice *dev;
+	char desc[32];
+
+	uclass_find_first_device(UCLASS_CPU, &dev);
+	if (!dev) {
+		debug("unable to find the RISC-V cpu device\n");
+		return false;
+	}
+	if (!cpu_get_desc(dev, desc, sizeof(desc))) {
+		/* skip the first 4 characters (rv32|rv64) */
+		if (strchr(desc + 4, ext))
+			return true;
+	}
+
+	return false;
+#else  /* !CONFIG_CPU */
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+	return csr_read(CSR_MISA) & (1 << (ext - 'a'));
+#else  /* !CONFIG_IS_ENABLED(RISCV_MMODE) */
+#warning "There is no way to determine the available extensions in S-mode."
+#warning "Please convert your board to use the RISC-V CPU driver."
+	return false;
+#endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */
+#endif /* CONFIG_CPU */
+}
+
+static int riscv_cpu_probe(void)
+{
+#ifdef CONFIG_CPU
+	int ret;
+
+	/* probe cpus so that RISC-V timer can be bound */
+	ret = cpu_probe_all();
+	if (ret)
+		return log_msg_ret("RISC-V cpus probe failed\n", ret);
+#endif
+
+	return 0;
+}
+
+/*
+ * This is called on secondary harts just after the IPI is init'd. Currently
+ * there's nothing to do, since we just need to clear any existing IPIs, and
+ * that is handled by the sending of an ipi itself.
+ */
+#if CONFIG_IS_ENABLED(SMP)
+static void dummy_pending_ipi_clear(ulong hart, ulong arg0, ulong arg1)
+{
+}
+#endif
+
+int arch_cpu_init_dm(void)
+{
+	int ret;
+
+	ret = riscv_cpu_probe();
+	if (ret)
+		return ret;
+
+	/* Enable FPU */
+	if (supports_extension('d') || supports_extension('f')) {
+		csr_set(MODE_PREFIX(status), MSTATUS_FS);
+		csr_write(CSR_FCSR, 0);
+	}
+
+	if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
+		/*
+		 * Enable perf counters for cycle, time,
+		 * and instret counters only
+		 */
+#ifdef CONFIG_RISCV_PRIV_1_9
+		csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0));
+		csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0));
+#else
+		csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
+#endif
+
+		/* Disable paging */
+		if (supports_extension('s'))
+#ifdef CONFIG_RISCV_PRIV_1_9
+			csr_read_clear(CSR_MSTATUS, SR_VM);
+#else
+			csr_write(CSR_SATP, 0);
+#endif
+	}
+
+#if CONFIG_IS_ENABLED(SMP)
+	ret = riscv_init_ipi();
+	if (ret)
+		return ret;
+
+	/*
+	 * Clear all pending IPIs on secondary harts. We don't do anything on
+	 * the boot hart, since we never send an IPI to ourselves, and no
+	 * interrupts are enabled
+	 */
+	ret = smp_call_function((ulong)dummy_pending_ipi_clear, 0, 0, 0);
+	if (ret)
+		return ret;
+#endif
+
+	return 0;
+}
+
+int arch_early_init_r(void)
+{
+	return riscv_cpu_probe();
+}
+
+/**
+ * harts_early_init() - A callback function called by start.S to configure
+ * feature settings of each hart.
+ *
+ * In a multi-core system, memory access shall be careful here, it shall
+ * take care of race conditions.
+ */
+__weak void harts_early_init(void)
+{
+}
diff --git a/roms/u-boot/arch/riscv/cpu/fu540/Kconfig b/roms/u-boot/arch/riscv/cpu/fu540/Kconfig
new file mode 100644
index 000000000..05463b262
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/fu540/Kconfig
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+
+config SIFIVE_FU540
+	bool
+	select ARCH_EARLY_INIT_R
+	select SUPPORT_SPL
+	select RAM
+	select SPL_RAM if SPL
+	imply CPU
+	imply CPU_RISCV
+	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
+	imply SPL_SIFIVE_CLINT
+	imply CMD_CPU
+	imply SPL_CPU
+	imply SPL_OPENSBI
+	imply SPL_LOAD_FIT
+	imply SMP
+	imply CLK_SIFIVE
+	imply CLK_SIFIVE_PRCI
+	imply SIFIVE_SERIAL
+	imply MACB
+	imply MII
+	imply SPI
+	imply SPI_SIFIVE
+	imply MMC
+	imply MMC_SPI
+	imply MMC_BROKEN_CD
+	imply CMD_MMC
+	imply DM_GPIO
+	imply SIFIVE_GPIO
+	imply CMD_GPIO
+	imply MISC
+	imply SIFIVE_OTP
+	imply DM_PWM
+	imply PWM_SIFIVE
+	imply DM_I2C
+	imply SYS_I2C_OCORES
+
+if ENV_IS_IN_SPI_FLASH
+
+config ENV_OFFSET
+	default 0x505000
+
+config ENV_SIZE
+	default 0x20000
+
+config ENV_SECT_SIZE
+	default 0x10000
+
+endif # ENV_IS_IN_SPI_FLASH
diff --git a/roms/u-boot/arch/riscv/cpu/fu540/Makefile b/roms/u-boot/arch/riscv/cpu/fu540/Makefile
new file mode 100644
index 000000000..088205ef5
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/fu540/Makefile
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 SiFive, Inc
+# Pragnesh Patel <pragnesh.patel@sifive.com>
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-y += spl.o
+else
+obj-y += dram.o
+obj-y += cpu.o
+obj-y += cache.o
+endif
diff --git a/roms/u-boot/arch/riscv/cpu/fu540/cache.c b/roms/u-boot/arch/riscv/cpu/fu540/cache.c
new file mode 100644
index 000000000..0fc4ef6c0
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/fu540/cache.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 SiFive, Inc
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#include <common.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+
+/* Register offsets */
+#define L2_CACHE_CONFIG	0x000
+#define L2_CACHE_ENABLE	0x008
+
+#define MASK_NUM_WAYS	GENMASK(15, 8)
+#define NUM_WAYS_SHIFT	8
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int cache_enable_ways(void)
+{
+	const void *blob = gd->fdt_blob;
+	int node;
+	fdt_addr_t base;
+	u32 config;
+	u32 ways;
+
+	volatile u32 *enable;
+
+	node = fdt_node_offset_by_compatible(blob, -1,
+					     "sifive,fu540-c000-ccache");
+
+	if (node < 0)
+		return node;
+
+	base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
+						NULL, false);
+	if (base == FDT_ADDR_T_NONE)
+		return FDT_ADDR_T_NONE;
+
+	config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
+	ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
+
+	enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
+
+	/* memory barrier */
+	mb();
+	(*enable) = ways - 1;
+	/* memory barrier */
+	mb();
+	return 0;
+}
diff --git a/roms/u-boot/arch/riscv/cpu/fu540/cpu.c b/roms/u-boot/arch/riscv/cpu/fu540/cpu.c
new file mode 100644
index 000000000..f13c18942
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/fu540/cpu.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <irq_func.h>
+#include <asm/cache.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+	disable_interrupts();
+
+	cache_flush();
+
+	return 0;
+}
diff --git a/roms/u-boot/arch/riscv/cpu/fu540/dram.c b/roms/u-boot/arch/riscv/cpu/fu540/dram.c
new file mode 100644
index 000000000..1fdc7837b
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/fu540/dram.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+	/*
+	 * Ensure that we run from first 4GB so that all
+	 * addresses used by U-Boot are 32bit addresses.
+	 *
+	 * This in-turn ensures that 32bit DMA capable
+	 * devices work fine because DMA mapping APIs will
+	 * provide 32bit DMA addresses only.
+	 */
+	if (gd->ram_top >= SZ_4G)
+		return SZ_4G - 1;
+
+	return gd->ram_top;
+}
diff --git a/roms/u-boot/arch/riscv/cpu/fu540/spl.c b/roms/u-boot/arch/riscv/cpu/fu540/spl.c
new file mode 100644
index 000000000..45657b790
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/fu540/spl.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 SiFive, Inc
+ * Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#include <dm.h>
+#include <log.h>
+
+int spl_soc_init(void)
+{
+	int ret;
+	struct udevice *dev;
+
+	/* DDR init */
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		debug("DRAM init failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/arch/riscv/cpu/fu740/Kconfig b/roms/u-boot/arch/riscv/cpu/fu740/Kconfig
new file mode 100644
index 000000000..3a5f6e47f
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/fu740/Kconfig
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020-2021 SiFive, Inc
+# Pragnesh Patel <pragnesh.patel@sifive.com>
+
+config SIFIVE_FU740
+	bool
+	select ARCH_EARLY_INIT_R
+	select RAM
+	select SPL_RAM if SPL
+	imply CPU
+	imply CPU_RISCV
+	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
+	imply SPL_SIFIVE_CLINT
+	imply CMD_CPU
+	imply SPL_CPU
+	imply SPL_OPENSBI
+	imply SPL_LOAD_FIT
+	imply SMP
+	imply CLK_SIFIVE
+	imply CLK_SIFIVE_PRCI
+	imply SIFIVE_SERIAL
+	imply MACB
+	imply MII
+	imply SPI
+	imply SPI_SIFIVE
+	imply MMC
+	imply MMC_SPI
+	imply MMC_BROKEN_CD
+	imply CMD_MMC
+	imply DM_GPIO
+	imply SIFIVE_GPIO
+	imply CMD_GPIO
+	imply MISC
+	imply SIFIVE_OTP
+	imply DM_PWM
+	imply PWM_SIFIVE
diff --git a/roms/u-boot/arch/riscv/cpu/fu740/Makefile b/roms/u-boot/arch/riscv/cpu/fu740/Makefile
new file mode 100644
index 000000000..5ef8ac18a
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/fu740/Makefile
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020-2021 SiFive, Inc
+# Pragnesh Patel <pragnesh.patel@sifive.com>
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-y += spl.o
+else
+obj-y += dram.o
+obj-y += cpu.o
+obj-y += cache.o
+endif
diff --git a/roms/u-boot/arch/riscv/cpu/fu740/cache.c b/roms/u-boot/arch/riscv/cpu/fu740/cache.c
new file mode 100644
index 000000000..680955c9e
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/fu740/cache.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020-2021 SiFive, Inc
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <asm/global_data.h>
+
+/* Register offsets */
+#define L2_CACHE_CONFIG	0x000
+#define L2_CACHE_ENABLE	0x008
+
+#define MASK_NUM_WAYS	GENMASK(15, 8)
+#define NUM_WAYS_SHIFT	8
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int cache_enable_ways(void)
+{
+	const void *blob = gd->fdt_blob;
+	int node;
+	fdt_addr_t base;
+	u32 config;
+	u32 ways;
+
+	volatile u32 *enable;
+
+	node = fdt_node_offset_by_compatible(blob, -1,
+					     "sifive,fu740-c000-ccache");
+
+	if (node < 0)
+		return node;
+
+	base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
+						NULL, false);
+	if (base == FDT_ADDR_T_NONE)
+		return FDT_ADDR_T_NONE;
+
+	config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
+	ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
+
+	enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
+
+	/* memory barrier */
+	mb();
+	(*enable) = ways - 1;
+	/* memory barrier */
+	mb();
+	return 0;
+}
diff --git a/roms/u-boot/arch/riscv/cpu/fu740/cpu.c b/roms/u-boot/arch/riscv/cpu/fu740/cpu.c
new file mode 100644
index 000000000..f13c18942
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/fu740/cpu.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <irq_func.h>
+#include <asm/cache.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+	disable_interrupts();
+
+	cache_flush();
+
+	return 0;
+}
diff --git a/roms/u-boot/arch/riscv/cpu/fu740/dram.c b/roms/u-boot/arch/riscv/cpu/fu740/dram.c
new file mode 100644
index 000000000..1dc77efec
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/fu740/dram.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+#ifdef CONFIG_64BIT
+	/*
+	 * Ensure that we run from first 4GB so that all
+	 * addresses used by U-Boot are 32bit addresses.
+	 *
+	 * This in-turn ensures that 32bit DMA capable
+	 * devices work fine because DMA mapping APIs will
+	 * provide 32bit DMA addresses only.
+	 */
+	if (gd->ram_top > SZ_4G)
+		return SZ_4G;
+#endif
+	return gd->ram_top;
+}
diff --git a/roms/u-boot/arch/riscv/cpu/fu740/spl.c b/roms/u-boot/arch/riscv/cpu/fu740/spl.c
new file mode 100644
index 000000000..55e30346f
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/fu740/spl.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020-201 SiFive, Inc
+ * Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#include <dm.h>
+#include <log.h>
+#include <asm/csr.h>
+
+#define CSR_U74_FEATURE_DISABLE	0x7c1
+
+int spl_soc_init(void)
+{
+	int ret;
+	struct udevice *dev;
+
+	/* DDR init */
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		debug("DRAM init failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+void harts_early_init(void)
+{
+	/*
+	 * Feature Disable CSR
+	 *
+	 * Clear feature disable CSR to '0' to turn on all features for
+	 * each core. This operation must be in M-mode.
+	 */
+	if (CONFIG_IS_ENABLED(RISCV_MMODE))
+		csr_write(CSR_U74_FEATURE_DISABLE, 0);
+}
diff --git a/roms/u-boot/arch/riscv/cpu/generic/Kconfig b/roms/u-boot/arch/riscv/cpu/generic/Kconfig
new file mode 100644
index 000000000..e025134b2
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/generic/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+
+config GENERIC_RISCV
+	bool
+	select BINMAN if SPL
+	select ARCH_EARLY_INIT_R
+	imply CPU
+	imply CPU_RISCV
+	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
+	imply SIFIVE_CLINT if RISCV_MMODE
+	imply SPL_SIFIVE_CLINT if SPL_RISCV_MMODE
+	imply CMD_CPU
+	imply SPL_CPU
+	imply SPL_OPENSBI
+	imply SPL_LOAD_FIT
diff --git a/roms/u-boot/arch/riscv/cpu/generic/Makefile b/roms/u-boot/arch/riscv/cpu/generic/Makefile
new file mode 100644
index 000000000..258e4620d
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/generic/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+
+obj-y += dram.o
+obj-y += cpu.o
diff --git a/roms/u-boot/arch/riscv/cpu/generic/cpu.c b/roms/u-boot/arch/riscv/cpu/generic/cpu.c
new file mode 100644
index 000000000..d78e1a345
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/generic/cpu.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <irq_func.h>
+#include <asm/cache.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+	disable_interrupts();
+
+	cache_flush();
+
+	return 0;
+}
diff --git a/roms/u-boot/arch/riscv/cpu/generic/dram.c b/roms/u-boot/arch/riscv/cpu/generic/dram.c
new file mode 100644
index 000000000..1fdc7837b
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/generic/dram.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+	/*
+	 * Ensure that we run from first 4GB so that all
+	 * addresses used by U-Boot are 32bit addresses.
+	 *
+	 * This in-turn ensures that 32bit DMA capable
+	 * devices work fine because DMA mapping APIs will
+	 * provide 32bit DMA addresses only.
+	 */
+	if (gd->ram_top >= SZ_4G)
+		return SZ_4G - 1;
+
+	return gd->ram_top;
+}
diff --git a/roms/u-boot/arch/riscv/cpu/mtrap.S b/roms/u-boot/arch/riscv/cpu/mtrap.S
new file mode 100644
index 000000000..e40c7bd3f
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/mtrap.S
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * M-mode Trap Handler Code for RISC-V Core
+ *
+ * Copyright (c) 2017 Microsemi Corporation.
+ * Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
+ *
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/encoding.h>
+
+#ifdef CONFIG_32BIT
+#define LREG		lw
+#define SREG		sw
+#define REGBYTES	4
+#else
+#define LREG		ld
+#define SREG		sd
+#define REGBYTES	8
+#endif
+
+	.text
+
+	/* trap entry */
+	.align 2
+	.global trap_entry
+trap_entry:
+	addi sp, sp, -32 * REGBYTES
+	SREG x1,   1 * REGBYTES(sp)
+	SREG x2,   2 * REGBYTES(sp)
+	SREG x3,   3 * REGBYTES(sp)
+	SREG x4,   4 * REGBYTES(sp)
+	SREG x5,   5 * REGBYTES(sp)
+	SREG x6,   6 * REGBYTES(sp)
+	SREG x7,   7 * REGBYTES(sp)
+	SREG x8,   8 * REGBYTES(sp)
+	SREG x9,   9 * REGBYTES(sp)
+	SREG x10, 10 * REGBYTES(sp)
+	SREG x11, 11 * REGBYTES(sp)
+	SREG x12, 12 * REGBYTES(sp)
+	SREG x13, 13 * REGBYTES(sp)
+	SREG x14, 14 * REGBYTES(sp)
+	SREG x15, 15 * REGBYTES(sp)
+	SREG x16, 16 * REGBYTES(sp)
+	SREG x17, 17 * REGBYTES(sp)
+	SREG x18, 18 * REGBYTES(sp)
+	SREG x19, 19 * REGBYTES(sp)
+	SREG x20, 20 * REGBYTES(sp)
+	SREG x21, 21 * REGBYTES(sp)
+	SREG x22, 22 * REGBYTES(sp)
+	SREG x23, 23 * REGBYTES(sp)
+	SREG x24, 24 * REGBYTES(sp)
+	SREG x25, 25 * REGBYTES(sp)
+	SREG x26, 26 * REGBYTES(sp)
+	SREG x27, 27 * REGBYTES(sp)
+	SREG x28, 28 * REGBYTES(sp)
+	SREG x29, 29 * REGBYTES(sp)
+	SREG x30, 30 * REGBYTES(sp)
+	SREG x31, 31 * REGBYTES(sp)
+	csrr a0, MODE_PREFIX(cause)
+	csrr a1, MODE_PREFIX(epc)
+	csrr a2, MODE_PREFIX(tval)
+	mv a3, sp
+	jal handle_trap
+	csrw MODE_PREFIX(epc), a0
+
+	LREG x1,   1 * REGBYTES(sp)
+	LREG x3,   3 * REGBYTES(sp)
+	LREG x4,   4 * REGBYTES(sp)
+	LREG x5,   5 * REGBYTES(sp)
+	LREG x6,   6 * REGBYTES(sp)
+	LREG x7,   7 * REGBYTES(sp)
+	LREG x8,   8 * REGBYTES(sp)
+	LREG x9,   9 * REGBYTES(sp)
+	LREG x10, 10 * REGBYTES(sp)
+	LREG x11, 11 * REGBYTES(sp)
+	LREG x12, 12 * REGBYTES(sp)
+	LREG x13, 13 * REGBYTES(sp)
+	LREG x14, 14 * REGBYTES(sp)
+	LREG x15, 15 * REGBYTES(sp)
+	LREG x16, 16 * REGBYTES(sp)
+	LREG x17, 17 * REGBYTES(sp)
+	LREG x18, 18 * REGBYTES(sp)
+	LREG x19, 19 * REGBYTES(sp)
+	LREG x20, 20 * REGBYTES(sp)
+	LREG x21, 21 * REGBYTES(sp)
+	LREG x22, 22 * REGBYTES(sp)
+	LREG x23, 23 * REGBYTES(sp)
+	LREG x24, 24 * REGBYTES(sp)
+	LREG x25, 25 * REGBYTES(sp)
+	LREG x26, 26 * REGBYTES(sp)
+	LREG x27, 27 * REGBYTES(sp)
+	LREG x28, 28 * REGBYTES(sp)
+	LREG x29, 29 * REGBYTES(sp)
+	LREG x30, 30 * REGBYTES(sp)
+	LREG x31, 31 * REGBYTES(sp)
+	LREG x2,   2 * REGBYTES(sp)
+	addi sp, sp, 32 * REGBYTES
+	MODE_PREFIX(ret)
diff --git a/roms/u-boot/arch/riscv/cpu/start.S b/roms/u-boot/arch/riscv/cpu/start.S
new file mode 100644
index 000000000..308b0a97a
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/start.S
@@ -0,0 +1,450 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Startup Code for RISC-V Core
+ *
+ * Copyright (c) 2017 Microsemi Corporation.
+ * Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
+ *
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <common.h>
+#include <elf.h>
+#include <asm/encoding.h>
+#include <generated/asm-offsets.h>
+
+#ifdef CONFIG_32BIT
+#define LREG			lw
+#define SREG			sw
+#define REGBYTES		4
+#define RELOC_TYPE		R_RISCV_32
+#define SYM_INDEX		0x8
+#define SYM_SIZE		0x10
+#else
+#define LREG			ld
+#define SREG			sd
+#define REGBYTES		8
+#define RELOC_TYPE		R_RISCV_64
+#define SYM_INDEX		0x20
+#define SYM_SIZE		0x18
+#endif
+
+.section .data
+secondary_harts_relocation_error:
+	.ascii "Relocation of secondary harts has failed, error %d\n"
+
+.section .text
+.globl _start
+_start:
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+	csrr	a0, CSR_MHARTID
+#endif
+
+	/*
+	 * Save hart id and dtb pointer. The thread pointer register is not
+	 * modified by C code. It is used by secondary_hart_loop.
+	 */
+	mv	tp, a0
+	mv	s1, a1
+
+	/*
+	 * Set the global data pointer to a known value in case we get a very
+	 * early trap. The global data pointer will be set its actual value only
+	 * after it has been initialized.
+	 */
+	mv	gp, zero
+
+	/*
+	 * Set the trap handler. This must happen after initializing gp because
+	 * the handler may use it.
+	 */
+	la	t0, trap_entry
+	csrw	MODE_PREFIX(tvec), t0
+
+	/*
+	 * Mask all interrupts. Interrupts are disabled globally (in m/sstatus)
+	 * for U-Boot, but we will need to read m/sip to determine if we get an
+	 * IPI
+	 */
+	csrw	MODE_PREFIX(ie), zero
+
+#if CONFIG_IS_ENABLED(SMP)
+	/* check if hart is within range */
+	/* tp: hart id */
+	li	t0, CONFIG_NR_CPUS
+	bge	tp, t0, hart_out_of_bounds_loop
+
+	/* set xSIE bit to receive IPIs */
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+	li	t0, MIE_MSIE
+#else
+	li	t0, SIE_SSIE
+#endif
+	csrs	MODE_PREFIX(ie), t0
+#endif
+
+/*
+ * Set stackpointer in internal/ex RAM to call board_init_f
+ */
+call_board_init_f:
+	li	t0, -16
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+	li	t1, CONFIG_SPL_STACK
+#else
+	li	t1, CONFIG_SYS_INIT_SP_ADDR
+#endif
+	and	sp, t1, t0		/* force 16 byte alignment */
+
+call_board_init_f_0:
+	mv	a0, sp
+	jal	board_init_f_alloc_reserve
+
+	/*
+	 * Save global data pointer for later. We don't set it here because it
+	 * is not initialized yet.
+	 */
+	mv	s0, a0
+
+	/* setup stack */
+#if CONFIG_IS_ENABLED(SMP)
+	/* tp: hart id */
+	slli	t0, tp, CONFIG_STACK_SIZE_SHIFT
+	sub	sp, a0, t0
+#else
+	mv	sp, a0
+#endif
+
+	/* Configure proprietary settings and customized CSRs of harts */
+call_harts_early_init:
+	jal	harts_early_init
+
+#ifndef CONFIG_XIP
+	/*
+	 * Pick hart to initialize global data and run U-Boot. The other harts
+	 * wait for initialization to complete.
+	 */
+	la	t0, hart_lottery
+	li	t1, 1
+	amoswap.w s2, t1, 0(t0)
+	bnez	s2, wait_for_gd_init
+#else
+	/*
+	 * FIXME: gp is set before it is initialized. If an XIP U-Boot ever
+	 * encounters a pending IPI on boot it is liable to jump to whatever
+	 * memory happens to be in ipi_data.addr on boot. It may also run into
+	 * problems if it encounters an exception too early (because printf/puts
+	 * accesses gd).
+	 */
+	mv	gp, s0
+	bnez	tp, secondary_hart_loop
+#endif
+
+#ifdef CONFIG_OF_PRIOR_STAGE
+	la	t0, prior_stage_fdt_address
+	SREG	s1, 0(t0)
+#endif
+
+	jal	board_init_f_init_reserve
+
+	SREG	s1, GD_FIRMWARE_FDT_ADDR(gp)
+	/* save the boot hart id to global_data */
+	SREG	tp, GD_BOOT_HART(gp)
+
+#ifndef CONFIG_XIP
+	la	t0, available_harts_lock
+	amoswap.w.rl zero, zero, 0(t0)
+
+wait_for_gd_init:
+	la	t0, available_harts_lock
+	li	t1, 1
+1:	amoswap.w.aq t1, t1, 0(t0)
+	bnez	t1, 1b
+
+	/*
+	 * Set the global data pointer only when gd_t has been initialized.
+	 * This was already set by arch_setup_gd on the boot hart, but all other
+	 * harts' global data pointers gets set here.
+	 */
+	mv	gp, s0
+
+	/* register available harts in the available_harts mask */
+	li	t1, 1
+	sll	t1, t1, tp
+	LREG	t2, GD_AVAILABLE_HARTS(gp)
+	or	t2, t2, t1
+	SREG	t2, GD_AVAILABLE_HARTS(gp)
+
+	amoswap.w.rl zero, zero, 0(t0)
+
+	/*
+	 * Continue on hart lottery winner, others branch to
+	 * secondary_hart_loop.
+	 */
+	bnez	s2, secondary_hart_loop
+#endif
+
+	/* Enable cache */
+	jal	icache_enable
+	jal	dcache_enable
+
+#ifdef CONFIG_DEBUG_UART
+	jal	debug_uart_init
+#endif
+
+	mv	a0, zero		/* a0 <-- boot_flags = 0 */
+	la	t5, board_init_f
+	jalr	t5			/* jump to board_init_f() */
+
+#ifdef CONFIG_SPL_BUILD
+spl_clear_bss:
+	la	t0, __bss_start
+	la	t1, __bss_end
+	beq	t0, t1, spl_stack_gd_setup
+
+spl_clear_bss_loop:
+	SREG	zero, 0(t0)
+	addi	t0, t0, REGBYTES
+	blt	t0, t1, spl_clear_bss_loop
+
+spl_stack_gd_setup:
+	jal	spl_relocate_stack_gd
+
+	/* skip setup if we did not relocate */
+	beqz	a0, spl_call_board_init_r
+	mv	s0, a0
+
+	/* setup stack on main hart */
+#if CONFIG_IS_ENABLED(SMP)
+	/* tp: hart id */
+	slli	t0, tp, CONFIG_STACK_SIZE_SHIFT
+	sub	sp, s0, t0
+#else
+	mv	sp, s0
+#endif
+
+#if CONFIG_IS_ENABLED(SMP)
+	/* set new stack and global data pointer on secondary harts */
+spl_secondary_hart_stack_gd_setup:
+	la	a0, secondary_hart_relocate
+	mv	a1, s0
+	mv	a2, s0
+	mv	a3, zero
+	jal	smp_call_function
+
+	/* hang if relocation of secondary harts has failed */
+	beqz	a0, 1f
+	mv	a1, a0
+	la	a0, secondary_harts_relocation_error
+	jal	printf
+	jal	hang
+#endif
+
+	/* set new global data pointer on main hart */
+1:	mv	gp, s0
+
+spl_call_board_init_r:
+	mv	a0, zero
+	mv	a1, zero
+	jal	board_init_r
+#endif
+
+/*
+ * void relocate_code(addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+.globl relocate_code
+relocate_code:
+	mv	s2, a0			/* save addr_sp */
+	mv	s3, a1			/* save addr of gd */
+	mv	s4, a2			/* save addr of destination */
+
+/*
+ *Set up the stack
+ */
+stack_setup:
+#if CONFIG_IS_ENABLED(SMP)
+	/* tp: hart id */
+	slli	t0, tp, CONFIG_STACK_SIZE_SHIFT
+	sub	sp, s2, t0
+#else
+	mv	sp, s2
+#endif
+
+	la	t0, _start
+	sub	t6, s4, t0		/* t6 <- relocation offset */
+	beq	t0, s4, clear_bss	/* skip relocation */
+
+	mv	t1, s4			/* t1 <- scratch for copy_loop */
+	la	t3, __bss_start
+	sub	t3, t3, t0		/* t3 <- __bss_start_ofs */
+	add	t2, t0, t3		/* t2 <- source end address */
+
+copy_loop:
+	LREG	t5, 0(t0)
+	addi	t0, t0, REGBYTES
+	SREG	t5, 0(t1)
+	addi	t1, t1, REGBYTES
+	blt	t0, t2, copy_loop
+
+/*
+ * Update dynamic relocations after board_init_f
+ */
+fix_rela_dyn:
+	la	t1, __rel_dyn_start
+	la	t2, __rel_dyn_end
+	beq	t1, t2, clear_bss
+	add	t1, t1, t6		/* t1 <- rela_dyn_start in RAM */
+	add	t2, t2, t6		/* t2 <- rela_dyn_end in RAM */
+
+/*
+ * skip first reserved entry: address, type, addend
+ */
+	j	10f
+
+6:
+	LREG	t5, -(REGBYTES*2)(t1)	/* t5 <-- relocation info:type */
+	li	t3, R_RISCV_RELATIVE	/* reloc type R_RISCV_RELATIVE */
+	bne	t5, t3, 8f		/* skip non-RISCV_RELOC entries */
+	LREG	t3, -(REGBYTES*3)(t1)
+	LREG	t5, -(REGBYTES)(t1)	/* t5 <-- addend */
+	add	t5, t5, t6		/* t5 <-- location to fix up in RAM */
+	add	t3, t3, t6		/* t3 <-- location to fix up in RAM */
+	SREG	t5, 0(t3)
+	j	10f
+
+8:
+	la	t4, __dyn_sym_start
+	add	t4, t4, t6
+
+9:
+	LREG	t5, -(REGBYTES*2)(t1)	/* t5 <-- relocation info:type */
+	srli	t0, t5, SYM_INDEX	/* t0 <--- sym table index */
+	andi	t5, t5, 0xFF		/* t5 <--- relocation type */
+	li	t3, RELOC_TYPE
+	bne	t5, t3, 10f		/* skip non-addned entries */
+
+	LREG	t3, -(REGBYTES*3)(t1)
+	li	t5, SYM_SIZE
+	mul	t0, t0, t5
+	add	s5, t4, t0
+	LREG	t0, -(REGBYTES)(t1)	/* t0 <-- addend */
+	LREG	t5, REGBYTES(s5)
+	add	t5, t5, t0
+	add	t5, t5, t6		/* t5 <-- location to fix up in RAM */
+	add	t3, t3, t6		/* t3 <-- location to fix up in RAM */
+	SREG	t5, 0(t3)
+10:
+	addi	t1, t1, (REGBYTES*3)
+	ble	t1, t2, 6b
+
+/*
+ * trap update
+*/
+	la	t0, trap_entry
+	add	t0, t0, t6
+	csrw	MODE_PREFIX(tvec), t0
+
+clear_bss:
+	la	t0, __bss_start		/* t0 <- rel __bss_start in FLASH */
+	add	t0, t0, t6		/* t0 <- rel __bss_start in RAM */
+	la	t1, __bss_end		/* t1 <- rel __bss_end in FLASH */
+	add	t1, t1, t6		/* t1 <- rel __bss_end in RAM */
+	beq	t0, t1, relocate_secondary_harts
+
+clbss_l:
+	SREG	zero, 0(t0)		/* clear loop... */
+	addi	t0, t0, REGBYTES
+	blt	t0, t1, clbss_l
+
+relocate_secondary_harts:
+#if CONFIG_IS_ENABLED(SMP)
+	/* send relocation IPI */
+	la	t0, secondary_hart_relocate
+	add	a0, t0, t6
+
+	/* store relocation offset */
+	mv	s5, t6
+
+	mv	a1, s2
+	mv	a2, s3
+	mv	a3, zero
+	jal	smp_call_function
+
+	/* hang if relocation of secondary harts has failed */
+	beqz	a0, 1f
+	mv	a1, a0
+	la	a0, secondary_harts_relocation_error
+	jal	printf
+	jal	hang
+
+	/* restore relocation offset */
+1:	mv	t6, s5
+#endif
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+call_board_init_r:
+	jal	invalidate_icache_all
+	jal	flush_dcache_all
+	la	t0, board_init_r        /* offset of board_init_r() */
+	add	t4, t0, t6		/* real address of board_init_r() */
+/*
+ * setup parameters for board_init_r
+ */
+	mv	a0, s3			/* gd_t */
+	mv	a1, s4			/* dest_addr */
+
+/*
+ * jump to it ...
+ */
+	jr	t4			/* jump to board_init_r() */
+
+#if CONFIG_IS_ENABLED(SMP)
+hart_out_of_bounds_loop:
+	/* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */
+	wfi
+	j	hart_out_of_bounds_loop
+
+/* SMP relocation entry */
+secondary_hart_relocate:
+	/* a1: new sp */
+	/* a2: new gd */
+	/* tp: hart id */
+
+	/* setup stack */
+	slli	t0, tp, CONFIG_STACK_SIZE_SHIFT
+	sub	sp, a1, t0
+
+	/* update global data pointer */
+	mv	gp, a2
+#endif
+
+/*
+ * Interrupts are disabled globally, but they can still be read from m/sip. The
+ * wfi function will wake us up if we get an IPI, even if we do not trap.
+ */
+secondary_hart_loop:
+	wfi
+
+#if CONFIG_IS_ENABLED(SMP)
+	csrr	t0, MODE_PREFIX(ip)
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+	andi	t0, t0, MIE_MSIE
+#else
+	andi	t0, t0, SIE_SSIE
+#endif
+	beqz	t0, secondary_hart_loop
+
+	mv	a0, tp
+	jal	handle_ipi
+#endif
+
+	j	secondary_hart_loop
diff --git a/roms/u-boot/arch/riscv/cpu/u-boot-spl.lds b/roms/u-boot/arch/riscv/cpu/u-boot-spl.lds
new file mode 100644
index 000000000..d0495ce24
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/u-boot-spl.lds
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Based on arch/riscv/cpu/u-boot.lds, which is
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * and arch/mips/cpu/u-boot-spl.lds.
+ */
+MEMORY { .spl_mem : ORIGIN = IMAGE_TEXT_BASE, LENGTH = IMAGE_MAX_SIZE }
+MEMORY { .bss_mem : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+		    LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_ARCH("riscv")
+ENTRY(_start)
+
+SECTIONS
+{
+	. = ALIGN(4);
+	.text : {
+		arch/riscv/cpu/start.o	(.text)
+		*(.text*)
+	} > .spl_mem
+
+	. = ALIGN(4);
+	.rodata : {
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	} > .spl_mem
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	} > .spl_mem
+	. = ALIGN(4);
+
+	.got : {
+		__got_start = .;
+		*(.got.plt) *(.got)
+		__got_end = .;
+	} > .spl_mem
+
+	. = ALIGN(4);
+
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	} > .spl_mem
+
+	. = ALIGN(4);
+
+	.binman_sym_table : {
+		__binman_sym_start = .;
+		KEEP(*(SORT(.binman_sym*)));
+		__binman_sym_end = .;
+	} > .spl_mem
+
+	. = ALIGN(4);
+
+	/DISCARD/ : { *(.rela.plt*) }
+	.rela.dyn : {
+		__rel_dyn_start = .;
+		*(.rela*)
+		__rel_dyn_end = .;
+	} > .spl_mem
+
+	. = ALIGN(4);
+
+	.dynsym : {
+		__dyn_sym_start = .;
+		*(.dynsym)
+		__dyn_sym_end = .;
+	} > .spl_mem
+
+	. = ALIGN(4);
+
+	_end = .;
+	_image_binary_end = .;
+
+	.bss : {
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(8);
+		__bss_end = .;
+	} > .bss_mem
+}
diff --git a/roms/u-boot/arch/riscv/cpu/u-boot.lds b/roms/u-boot/arch/riscv/cpu/u-boot.lds
new file mode 100644
index 000000000..c00d17c73
--- /dev/null
+++ b/roms/u-boot/arch/riscv/cpu/u-boot.lds
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+OUTPUT_ARCH("riscv")
+ENTRY(_start)
+
+SECTIONS
+{
+	. = ALIGN(4);
+	.text : {
+		arch/riscv/cpu/start.o	(.text)
+	}
+
+	/* This needs to come before *(.text*) */
+	.efi_runtime : {
+		__efi_runtime_start = .;
+		*(.text.efi_runtime*)
+		*(.rodata.efi_runtime*)
+		*(.data.efi_runtime*)
+		__efi_runtime_stop = .;
+	}
+
+	.text_rest : {
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+	. = ALIGN(4);
+
+	.got : {
+		__got_start = .;
+		*(.got.plt) *(.got)
+		__got_end = .;
+	}
+
+	. = ALIGN(4);
+
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+
+	.efi_runtime_rel : {
+		__efi_runtime_rel_start = .;
+		*(.rel*.efi_runtime)
+		*(.rel*.efi_runtime.*)
+		__efi_runtime_rel_stop = .;
+	}
+
+	. = ALIGN(4);
+
+	/DISCARD/ : { *(.rela.plt*) }
+	.rela.dyn : {
+		__rel_dyn_start = .;
+		*(.rela*)
+		__rel_dyn_end = .;
+	}
+
+	. = ALIGN(4);
+
+	.dynsym : {
+		__dyn_sym_start = .;
+		*(.dynsym)
+		__dyn_sym_end = .;
+	}
+
+	. = ALIGN(4);
+
+	_end = .;
+
+	.bss : {
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(8);
+		__bss_end = .;
+	}
+}
diff --git a/roms/u-boot/arch/riscv/dts/Makefile b/roms/u-boot/arch/riscv/dts/Makefile
new file mode 100644
index 000000000..777887483
--- /dev/null
+++ b/roms/u-boot/arch/riscv/dts/Makefile
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
+dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
+dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt.dtb
+dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
+dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
+dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
+
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+	@:
+
+clean-files := *.dtb
diff --git a/roms/u-boot/arch/riscv/dts/ae350-u-boot.dtsi b/roms/u-boot/arch/riscv/dts/ae350-u-boot.dtsi
new file mode 100644
index 000000000..0d4201cfa
--- /dev/null
+++ b/roms/u-boot/arch/riscv/dts/ae350-u-boot.dtsi
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/ {
+	cpus {
+		u-boot,dm-spl;
+		CPU0: cpu@0 {
+			u-boot,dm-spl;
+			CPU0_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+		CPU1: cpu@1 {
+			u-boot,dm-spl;
+			CPU1_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+		CPU2: cpu@2 {
+			u-boot,dm-spl;
+			CPU2_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+		CPU3: cpu@3 {
+			u-boot,dm-spl;
+			CPU3_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+	};
+
+	memory@0 {
+		u-boot,dm-spl;
+	};
+
+	soc {
+		u-boot,dm-spl;
+
+		plic1: interrupt-controller@e6400000 {
+			u-boot,dm-spl;
+		};
+
+		plmt0@e6000000 {
+			u-boot,dm-spl;
+		};
+	};
+
+	serial0: serial@f0300000 {
+		u-boot,dm-spl;
+	};
+
+};
diff --git a/roms/u-boot/arch/riscv/dts/ae350_32.dts b/roms/u-boot/arch/riscv/dts/ae350_32.dts
new file mode 100644
index 000000000..083f67633
--- /dev/null
+++ b/roms/u-boot/arch/riscv/dts/ae350_32.dts
@@ -0,0 +1,327 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include "binman.dtsi"
+#include "ae350-u-boot.dtsi"
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "andestech,a25";
+	model = "andestech,a25";
+
+	aliases {
+		uart0 = &serial0;
+		spi0 = &spi;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,38400n8 debug loglevel=7";
+		stdout-path = "uart0:38400n8";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <60000000>;
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv32imafdc";
+			riscv,priv-major = <1>;
+			riscv,priv-minor = <10>;
+			mmu-type = "riscv,sv32";
+			clock-frequency = <60000000>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <32>;
+			next-level-cache = <&L2>;
+			CPU0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+		CPU1: cpu@1 {
+			device_type = "cpu";
+			reg = <1>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv32imafdc";
+			riscv,priv-major = <1>;
+			riscv,priv-minor = <10>;
+			mmu-type = "riscv,sv32";
+			clock-frequency = <60000000>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <32>;
+			next-level-cache = <&L2>;
+			CPU1_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+		CPU2: cpu@2 {
+			device_type = "cpu";
+			reg = <2>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv32imafdc";
+			riscv,priv-major = <1>;
+			riscv,priv-minor = <10>;
+			mmu-type = "riscv,sv32";
+			clock-frequency = <60000000>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <32>;
+			next-level-cache = <&L2>;
+			CPU2_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+		CPU3: cpu@3 {
+			device_type = "cpu";
+			reg = <3>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv32imafdc";
+			riscv,priv-major = <1>;
+			riscv,priv-minor = <10>;
+			mmu-type = "riscv,sv32";
+			clock-frequency = <60000000>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <32>;
+			next-level-cache = <&L2>;
+			CPU3_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+	};
+
+	L2: l2-cache@e0500000 {
+		compatible = "v5l2cache";
+		cache-level = <2>;
+		cache-size = <0x40000>;
+		reg = <0xe0500000 0x40000>;
+		andes,inst-prefetch = <3>;
+		andes,data-prefetch = <3>;
+		/* The value format is <XRAMOCTL XRAMICTL> */
+		andes,tag-ram-ctl = <0 0>;
+		andes,data-ram-ctl = <0 0>;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		plic0: interrupt-controller@e4000000 {
+			compatible = "riscv,plic0";
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			reg = <0xe4000000 0x2000000>;
+			riscv,ndev=<71>;
+			interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9
+				&CPU1_intc 11 &CPU1_intc 9
+				&CPU2_intc 11 &CPU2_intc 9
+				&CPU3_intc 11 &CPU3_intc 9>;
+		};
+
+		plic1: interrupt-controller@e6400000 {
+			compatible = "riscv,plic1";
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			reg = <0xe6400000 0x400000>;
+			riscv,ndev=<2>;
+			interrupts-extended = <&CPU0_intc 3
+				&CPU1_intc 3
+				&CPU2_intc 3
+				&CPU3_intc 3>;
+		};
+
+		plmt0@e6000000 {
+			compatible = "riscv,plmt0";
+			interrupts-extended = <&CPU0_intc 7
+				&CPU1_intc 7
+				&CPU2_intc 7
+				&CPU3_intc 7>;
+			reg = <0xe6000000 0x100000>;
+		};
+	};
+
+	spiclk: virt_100mhz {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <100000000>;
+	};
+
+	timer0: timer@f0400000 {
+		compatible = "andestech,atcpit100";
+		reg = <0xf0400000 0x1000>;
+		clock-frequency = <60000000>;
+		interrupts = <3 4>;
+		interrupt-parent = <&plic0>;
+	};
+
+	serial0: serial@f0300000 {
+		compatible = "andestech,uart16550", "ns16550a";
+		reg = <0xf0300000 0x1000>;
+		interrupts = <9 4>;
+		clock-frequency = <19660800>;
+		reg-shift = <2>;
+		reg-offset = <32>;
+		no-loopback-test = <1>;
+		interrupt-parent = <&plic0>;
+	};
+
+	mac0: mac@e0100000 {
+		compatible = "andestech,atmac100";
+		reg = <0xe0100000 0x1000>;
+		interrupts = <19 4>;
+		interrupt-parent = <&plic0>;
+	};
+
+	mmc0: mmc@f0e00000 {
+		compatible = "andestech,atfsdc010";
+		max-frequency = <100000000>;
+		clock-freq-min-max = <400000 100000000>;
+		fifo-depth = <0x10>;
+		reg = <0xf0e00000 0x1000>;
+		interrupts = <18 4>;
+		cap-sd-highspeed;
+		interrupt-parent = <&plic0>;
+	};
+
+	dma0: dma@f0c00000 {
+		compatible = "andestech,atcdmac300";
+		reg = <0xf0c00000 0x1000>;
+		interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>;
+		dma-channels = <8>;
+		interrupt-parent = <&plic0>;
+	};
+
+	lcd0: lcd@e0200000 {
+		compatible = "andestech,atflcdc100";
+		reg = <0xe0200000 0x1000>;
+		interrupts = <20 4>;
+		interrupt-parent = <&plic0>;
+	};
+
+	smc0: smc@e0400000 {
+		compatible = "andestech,atfsmc020";
+		reg = <0xe0400000 0x1000>;
+	};
+
+	snd0: snd@f0d00000 {
+		compatible = "andestech,atfac97";
+		reg = <0xf0d00000 0x1000>;
+		interrupts = <17 4>;
+		interrupt-parent = <&plic0>;
+	};
+
+	pmu {
+		compatible = "riscv,base-pmu";
+	};
+
+	virtio_mmio@fe007000 {
+		interrupts = <0x17 0x4>;
+		interrupt-parent = <0x2>;
+		reg = <0xfe007000 0x1000>;
+		compatible = "virtio,mmio";
+	};
+
+	virtio_mmio@fe006000 {
+		interrupts = <0x16 0x4>;
+		interrupt-parent = <0x2>;
+		reg = <0xfe006000 0x1000>;
+		compatible = "virtio,mmio";
+	};
+
+	virtio_mmio@fe005000 {
+		interrupts = <0x15 0x4>;
+		interrupt-parent = <0x2>;
+		reg = <0xfe005000 0x1000>;
+		compatible = "virtio,mmio";
+	};
+
+	virtio_mmio@fe004000 {
+		interrupts = <0x14 0x4>;
+		interrupt-parent = <0x2>;
+		reg = <0xfe004000 0x1000>;
+		compatible = "virtio,mmio";
+	};
+
+	virtio_mmio@fe003000 {
+		interrupts = <0x13 0x4>;
+		interrupt-parent = <0x2>;
+		reg = <0xfe003000 0x1000>;
+		compatible = "virtio,mmio";
+	};
+
+	virtio_mmio@fe002000 {
+		interrupts = <0x12 0x4>;
+		interrupt-parent = <0x2>;
+		reg = <0xfe002000 0x1000>;
+		compatible = "virtio,mmio";
+	};
+
+	virtio_mmio@fe001000 {
+		interrupts = <0x11 0x4>;
+		interrupt-parent = <0x2>;
+		reg = <0xfe001000 0x1000>;
+		compatible = "virtio,mmio";
+	};
+
+	virtio_mmio@fe000000 {
+		interrupts = <0x10 0x4>;
+		interrupt-parent = <0x2>;
+		reg = <0xfe000000 0x1000>;
+		compatible = "virtio,mmio";
+	};
+
+	nor@0,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "cfi-flash";
+		reg = <0x88000000 0x4000000>;
+		bank-width = <2>;
+		device-width = <1>;
+	};
+
+	spi: spi@f0b00000 {
+		compatible = "andestech,atcspi200";
+		reg = <0xf0b00000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		num-cs = <1>;
+		clocks = <&spiclk>;
+		interrupts = <4 4>;
+		interrupt-parent = <&plic0>;
+		flash@0 {
+			compatible = "jedec,spi-nor";
+			spi-max-frequency = <50000000>;
+			reg = <0>;
+			spi-cpol;
+			spi-cpha;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/riscv/dts/ae350_64.dts b/roms/u-boot/arch/riscv/dts/ae350_64.dts
new file mode 100644
index 000000000..74cff9122
--- /dev/null
+++ b/roms/u-boot/arch/riscv/dts/ae350_64.dts
@@ -0,0 +1,327 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include "binman.dtsi"
+#include "ae350-u-boot.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	compatible = "andestech,ax25";
+	model = "andestech,ax25";
+
+	aliases {
+		uart0 = &serial0;
+		spi0 = &spi;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,38400n8 debug loglevel=7";
+		stdout-path = "uart0:38400n8";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <60000000>;
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdc";
+			riscv,priv-major = <1>;
+			riscv,priv-minor = <10>;
+			mmu-type = "riscv,sv39";
+			clock-frequency = <60000000>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <32>;
+			next-level-cache = <&L2>;
+			CPU0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+		CPU1: cpu@1 {
+			device_type = "cpu";
+			reg = <1>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdc";
+			riscv,priv-major = <1>;
+			riscv,priv-minor = <10>;
+			mmu-type = "riscv,sv39";
+			clock-frequency = <60000000>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <32>;
+			next-level-cache = <&L2>;
+			CPU1_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+		CPU2: cpu@2 {
+			device_type = "cpu";
+			reg = <2>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdc";
+			riscv,priv-major = <1>;
+			riscv,priv-minor = <10>;
+			mmu-type = "riscv,sv39";
+			clock-frequency = <60000000>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <32>;
+			next-level-cache = <&L2>;
+			CPU2_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+		CPU3: cpu@3 {
+			device_type = "cpu";
+			reg = <3>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdc";
+			riscv,priv-major = <1>;
+			riscv,priv-minor = <10>;
+			mmu-type = "riscv,sv39";
+			clock-frequency = <60000000>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <32>;
+			next-level-cache = <&L2>;
+			CPU3_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+	};
+
+	L2: l2-cache@e0500000 {
+		compatible = "v5l2cache";
+		cache-level = <2>;
+		cache-size = <0x40000>;
+		reg = <0x0 0xe0500000 0x0 0x40000>;
+		andes,inst-prefetch = <3>;
+		andes,data-prefetch = <3>;
+		/* The value format is <XRAMOCTL XRAMICTL> */
+		andes,tag-ram-ctl = <0 0>;
+		andes,data-ram-ctl = <0 0>;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x00000000 0x0 0x40000000>;
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+
+		plic0: interrupt-controller@e4000000 {
+			compatible = "riscv,plic0";
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			reg = <0x0 0xe4000000 0x0 0x2000000>;
+			riscv,ndev=<71>;
+			interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9
+				&CPU1_intc 11 &CPU1_intc 9
+				&CPU2_intc 11 &CPU2_intc 9
+				&CPU3_intc 11 &CPU3_intc 9>;
+		};
+
+		plic1: interrupt-controller@e6400000 {
+			compatible = "riscv,plic1";
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			reg = <0x0 0xe6400000 0x0 0x400000>;
+			riscv,ndev=<2>;
+			interrupts-extended = <&CPU0_intc 3
+				&CPU1_intc 3
+				&CPU2_intc 3
+				&CPU3_intc 3>;
+		};
+
+		plmt0@e6000000 {
+			compatible = "riscv,plmt0";
+			interrupts-extended = <&CPU0_intc 7
+				&CPU1_intc 7
+				&CPU2_intc 7
+				&CPU3_intc 7>;
+			reg = <0x0 0xe6000000 0x0 0x100000>;
+		};
+	};
+
+	spiclk: virt_100mhz {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <100000000>;
+	};
+
+	timer0: timer@f0400000 {
+		compatible = "andestech,atcpit100";
+		reg = <0x0 0xf0400000 0x0 0x1000>;
+		clock-frequency = <60000000>;
+		interrupts = <3 4>;
+		interrupt-parent = <&plic0>;
+	};
+
+	serial0: serial@f0300000 {
+		compatible = "andestech,uart16550", "ns16550a";
+		reg = <0x0 0xf0300000 0x0 0x1000>;
+		interrupts = <9 4>;
+		clock-frequency = <19660800>;
+		reg-shift = <2>;
+		reg-offset = <32>;
+		no-loopback-test = <1>;
+		interrupt-parent = <&plic0>;
+	};
+
+	mac0: mac@e0100000 {
+		compatible = "andestech,atmac100";
+		reg = <0x0 0xe0100000 0x0 0x1000>;
+		interrupts = <19 4>;
+		interrupt-parent = <&plic0>;
+	};
+
+	mmc0: mmc@f0e00000 {
+		compatible = "andestech,atfsdc010";
+		max-frequency = <100000000>;
+		clock-freq-min-max = <400000 100000000>;
+		fifo-depth = <0x10>;
+		reg = <0x0 0xf0e00000 0x0 0x1000>;
+		interrupts = <18 4>;
+		cap-sd-highspeed;
+		interrupt-parent = <&plic0>;
+	};
+
+	dma0: dma@f0c00000 {
+		compatible = "andestech,atcdmac300";
+		reg = <0x0 0xf0c00000 0x0 0x1000>;
+		interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>;
+		dma-channels = <8>;
+		interrupt-parent = <&plic0>;
+	};
+
+	lcd0: lcd@e0200000 {
+		compatible = "andestech,atflcdc100";
+		reg = <0x0 0xe0200000 0x0 0x1000>;
+		interrupts = <20 4>;
+		interrupt-parent = <&plic0>;
+	};
+
+	smc0: smc@e0400000 {
+		compatible = "andestech,atfsmc020";
+		reg = <0x0 0xe0400000 0x0 0x1000>;
+	};
+
+	snd0: snd@f0d00000 {
+		compatible = "andestech,atfac97";
+		reg = <0x0 0xf0d00000 0x0 0x1000>;
+		interrupts = <17 4>;
+		interrupt-parent = <&plic0>;
+	};
+
+	pmu {
+		compatible = "riscv,base-pmu";
+	};
+
+	virtio_mmio@fe007000 {
+		interrupts = <0x17 0x4>;
+		interrupt-parent = <0x2>;
+		reg = <0x0 0xfe007000 0x0 0x1000>;
+		compatible = "virtio,mmio";
+	};
+
+	virtio_mmio@fe006000 {
+		interrupts = <0x16 0x4>;
+		interrupt-parent = <0x2>;
+		reg = <0x0 0xfe006000 0x0 0x1000>;
+		compatible = "virtio,mmio";
+	};
+
+	virtio_mmio@fe005000 {
+		interrupts = <0x15 0x4>;
+		interrupt-parent = <0x2>;
+		reg = <0x0 0xfe005000 0x0 0x1000>;
+		compatible = "virtio,mmio";
+	};
+
+	virtio_mmio@fe004000 {
+		interrupts = <0x14 0x4>;
+		interrupt-parent = <0x2>;
+		reg = <0x0 0xfe004000 0x0 0x1000>;
+		compatible = "virtio,mmio";
+	};
+
+	virtio_mmio@fe003000 {
+		interrupts = <0x13 0x4>;
+		interrupt-parent = <0x2>;
+		reg = <0x0 0xfe003000 0x0 0x1000>;
+		compatible = "virtio,mmio";
+	};
+
+	virtio_mmio@fe002000 {
+		interrupts = <0x12 0x4>;
+		interrupt-parent = <0x2>;
+		reg = <0x0 0xfe002000 0x0 0x1000>;
+		compatible = "virtio,mmio";
+	};
+
+	virtio_mmio@fe001000 {
+		interrupts = <0x11 0x4>;
+		interrupt-parent = <0x2>;
+		reg = <0x0 0xfe001000 0x0 0x1000>;
+		compatible = "virtio,mmio";
+	};
+
+	virtio_mmio@fe000000 {
+		interrupts = <0x10 0x4>;
+		interrupt-parent = <0x2>;
+		reg = <0x0 0xfe000000 0x0 0x1000>;
+		compatible = "virtio,mmio";
+	};
+
+	nor@0,0 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "cfi-flash";
+		reg = <0x0 0x88000000 0x0 0x4000000>;
+		bank-width = <2>;
+		device-width = <1>;
+	};
+
+	spi: spi@f0b00000 {
+		compatible = "andestech,atcspi200";
+		reg = <0x0 0xf0b00000 0x0 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		num-cs = <1>;
+		clocks = <&spiclk>;
+		interrupts = <4 4>;
+		interrupt-parent = <&plic0>;
+		flash@0 {
+			compatible = "jedec,spi-nor";
+			spi-max-frequency = <50000000>;
+			reg = <0>;
+			spi-cpol;
+			spi-cpha;
+		};
+	};
+};
diff --git a/roms/u-boot/arch/riscv/dts/binman.dtsi b/roms/u-boot/arch/riscv/dts/binman.dtsi
new file mode 100644
index 000000000..d26cfdb78
--- /dev/null
+++ b/roms/u-boot/arch/riscv/dts/binman.dtsi
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <config.h>
+
+/ {
+	binman: binman {
+		multiple-images;
+	};
+};
+
+&binman {
+	itb {
+		filename = "u-boot.itb";
+
+		fit {
+			description = "Configuration to load OpenSBI before U-Boot";
+			#address-cells = <1>;
+			fit,fdt-list = "of-list";
+
+			images {
+				uboot {
+					description = "U-Boot";
+					type = "standalone";
+					os = "U-Boot";
+					arch = "riscv";
+					compression = "none";
+					load = <CONFIG_SYS_TEXT_BASE>;
+
+					uboot_blob: blob-ext {
+						filename = "u-boot-nodtb.bin";
+					};
+				};
+
+				opensbi {
+					description = "OpenSBI fw_dynamic Firmware";
+					type = "firmware";
+					os = "opensbi";
+					arch = "riscv";
+					compression = "none";
+					load = <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
+					entry = <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
+
+					opensbi_blob: opensbi {
+						filename = "fw_dynamic.bin";
+					};
+				};
+
+#ifndef CONFIG_OF_PRIOR_STAGE
+				@fdt-SEQ {
+					description = "NAME";
+					type = "flat_dt";
+					compression = "none";
+				};
+#endif
+			};
+
+			configurations {
+				default = "conf-1";
+
+#ifndef CONFIG_OF_PRIOR_STAGE
+				@conf-SEQ {
+#else
+				conf-1 {
+#endif
+					description = "NAME";
+					firmware = "opensbi";
+					loadables = "uboot";
+#ifndef CONFIG_OF_PRIOR_STAGE
+					fdt = "fdt-SEQ";
+#endif
+				};
+			};
+		};
+	};
+};
diff --git a/roms/u-boot/arch/riscv/dts/fu540-c000-u-boot.dtsi b/roms/u-boot/arch/riscv/dts/fu540-c000-u-boot.dtsi
new file mode 100644
index 000000000..b7cd600b8
--- /dev/null
+++ b/roms/u-boot/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * (C) Copyright 2019 SiFive, Inc
+ */
+
+#include <dt-bindings/reset/sifive-fu540-prci.h>
+
+/ {
+	cpus {
+		assigned-clocks = <&prci PRCI_CLK_COREPLL>;
+		assigned-clock-rates = <1000000000>;
+		u-boot,dm-spl;
+		cpu0: cpu@0 {
+			clocks = <&prci PRCI_CLK_COREPLL>;
+			u-boot,dm-spl;
+			status = "okay";
+			cpu0_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+		cpu1: cpu@1 {
+			clocks = <&prci PRCI_CLK_COREPLL>;
+			u-boot,dm-spl;
+			cpu1_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+		cpu2: cpu@2 {
+			clocks = <&prci PRCI_CLK_COREPLL>;
+			u-boot,dm-spl;
+			cpu2_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+		cpu3: cpu@3 {
+			clocks = <&prci PRCI_CLK_COREPLL>;
+			u-boot,dm-spl;
+			cpu3_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+		cpu4: cpu@4 {
+			clocks = <&prci PRCI_CLK_COREPLL>;
+			u-boot,dm-spl;
+			cpu4_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+	};
+
+	soc {
+		u-boot,dm-spl;
+		otp: otp@10070000 {
+			compatible = "sifive,fu540-c000-otp";
+			reg = <0x0 0x10070000 0x0 0x1000>;
+			fuse-count = <0x1000>;
+		};
+		clint: clint@2000000 {
+			compatible = "riscv,clint0";
+			interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
+					       &cpu1_intc 3 &cpu1_intc 7
+					       &cpu2_intc 3 &cpu2_intc 7
+					       &cpu3_intc 3 &cpu3_intc 7
+					       &cpu4_intc 3 &cpu4_intc 7>;
+			reg = <0x0 0x2000000 0x0 0x10000>;
+			u-boot,dm-spl;
+		};
+		prci: clock-controller@10000000 {
+			#reset-cells = <1>;
+			resets = <&prci PRCI_RST_DDR_CTRL_N>,
+				 <&prci PRCI_RST_DDR_AXI_N>,
+				 <&prci PRCI_RST_DDR_AHB_N>,
+				 <&prci PRCI_RST_DDR_PHY_N>,
+				 <&prci PRCI_RST_GEMGXL_N>;
+			reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb",
+					"ddr_phy", "gemgxl_reset";
+		};
+		dmc: dmc@100b0000 {
+			compatible = "sifive,fu540-c000-ddr";
+			reg = <0x0 0x100b0000 0x0 0x0800
+			       0x0 0x100b2000 0x0 0x2000
+			       0x0 0x100b8000 0x0 0x1000>;
+			clocks = <&prci PRCI_CLK_DDRPLL>;
+			clock-frequency = <933333324>;
+			u-boot,dm-spl;
+		};
+	};
+};
+
+&prci {
+	u-boot,dm-spl;
+};
+
+&uart0 {
+	u-boot,dm-spl;
+};
+
+&qspi2 {
+	u-boot,dm-spl;
+};
+
+&eth0 {
+	assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
+	assigned-clock-rates = <125000000>;
+};
+
+&l2cache {
+	status = "okay";
+};
diff --git a/roms/u-boot/arch/riscv/dts/fu540-c000.dtsi b/roms/u-boot/arch/riscv/dts/fu540-c000.dtsi
new file mode 100644
index 000000000..7db861053
--- /dev/null
+++ b/roms/u-boot/arch/riscv/dts/fu540-c000.dtsi
@@ -0,0 +1,286 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2018-2019 SiFive, Inc */
+
+/dts-v1/;
+
+#include <dt-bindings/clock/sifive-fu540-prci.h>
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	compatible = "sifive,fu540-c000", "sifive,fu540";
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		ethernet0 = &eth0;
+	};
+
+	chosen {
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cpu0: cpu@0 {
+			compatible = "sifive,e51", "sifive,rocket0", "riscv";
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <16384>;
+			reg = <0>;
+			riscv,isa = "rv64imac";
+			status = "disabled";
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		cpu1: cpu@1 {
+			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			reg = <1>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+			next-level-cache = <&l2cache>;
+			cpu1_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		cpu2: cpu@2 {
+			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			reg = <2>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+			next-level-cache = <&l2cache>;
+			cpu2_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		cpu3: cpu@3 {
+			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			reg = <3>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+			next-level-cache = <&l2cache>;
+			cpu3_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		cpu4: cpu@4 {
+			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			reg = <4>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+			next-level-cache = <&l2cache>;
+			cpu4_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
+		ranges;
+		plic0: interrupt-controller@c000000 {
+			#interrupt-cells = <1>;
+			compatible = "sifive,plic-1.0.0";
+			reg = <0x0 0xc000000 0x0 0x4000000>;
+			riscv,ndev = <53>;
+			interrupt-controller;
+			interrupts-extended = <
+				&cpu0_intc 0xffffffff
+				&cpu1_intc 0xffffffff &cpu1_intc 9
+				&cpu2_intc 0xffffffff &cpu2_intc 9
+				&cpu3_intc 0xffffffff &cpu3_intc 9
+				&cpu4_intc 0xffffffff &cpu4_intc 9>;
+		};
+		prci: clock-controller@10000000 {
+			compatible = "sifive,fu540-c000-prci";
+			reg = <0x0 0x10000000 0x0 0x1000>;
+			clocks = <&hfclk>, <&rtcclk>;
+			#clock-cells = <1>;
+		};
+		uart0: serial@10010000 {
+			compatible = "sifive,fu540-c000-uart", "sifive,uart0";
+			reg = <0x0 0x10010000 0x0 0x1000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <4>;
+			clocks = <&prci PRCI_CLK_TLCLK>;
+			status = "disabled";
+		};
+		dma: dma@3000000 {
+			compatible = "sifive,fu540-c000-pdma";
+			reg = <0x0 0x3000000 0x0 0x8000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <23 24 25 26 27 28 29 30>;
+			#dma-cells = <1>;
+		};
+		uart1: serial@10011000 {
+			compatible = "sifive,fu540-c000-uart", "sifive,uart0";
+			reg = <0x0 0x10011000 0x0 0x1000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <5>;
+			clocks = <&prci PRCI_CLK_TLCLK>;
+			status = "disabled";
+		};
+		i2c0: i2c@10030000 {
+			compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
+			reg = <0x0 0x10030000 0x0 0x1000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <50>;
+			clocks = <&prci PRCI_CLK_TLCLK>;
+			reg-shift = <2>;
+			reg-io-width = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		qspi0: spi@10040000 {
+			compatible = "sifive,fu540-c000-spi", "sifive,spi0";
+			reg = <0x0 0x10040000 0x0 0x1000
+			       0x0 0x20000000 0x0 0x10000000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <51>;
+			clocks = <&prci PRCI_CLK_TLCLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		qspi1: spi@10041000 {
+			compatible = "sifive,fu540-c000-spi", "sifive,spi0";
+			reg = <0x0 0x10041000 0x0 0x1000
+			       0x0 0x30000000 0x0 0x10000000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <52>;
+			clocks = <&prci PRCI_CLK_TLCLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		qspi2: spi@10050000 {
+			compatible = "sifive,fu540-c000-spi", "sifive,spi0";
+			reg = <0x0 0x10050000 0x0 0x1000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <6>;
+			clocks = <&prci PRCI_CLK_TLCLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		eth0: ethernet@10090000 {
+			compatible = "sifive,fu540-c000-gem";
+			interrupt-parent = <&plic0>;
+			interrupts = <53>;
+			reg = <0x0 0x10090000 0x0 0x2000
+			       0x0 0x100a0000 0x0 0x1000>;
+			local-mac-address = [00 00 00 00 00 00];
+			clock-names = "pclk", "hclk";
+			clocks = <&prci PRCI_CLK_GEMGXLPLL>,
+				 <&prci PRCI_CLK_GEMGXLPLL>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		pwm0: pwm@10020000 {
+			compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
+			reg = <0x0 0x10020000 0x0 0x1000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <42 43 44 45>;
+			clocks = <&prci PRCI_CLK_TLCLK>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+		pwm1: pwm@10021000 {
+			compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
+			reg = <0x0 0x10021000 0x0 0x1000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <46 47 48 49>;
+			clocks = <&prci PRCI_CLK_TLCLK>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+		l2cache: cache-controller@2010000 {
+			compatible = "sifive,fu540-c000-ccache", "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <1024>;
+			cache-size = <2097152>;
+			cache-unified;
+			interrupt-parent = <&plic0>;
+			interrupts = <1 2 3>;
+			reg = <0x0 0x2010000 0x0 0x1000>;
+		};
+		gpio: gpio@10060000 {
+			compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
+			interrupt-parent = <&plic0>;
+			interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>,
+				     <14>, <15>, <16>, <17>, <18>, <19>, <20>,
+				     <21>, <22>;
+			reg = <0x0 0x10060000 0x0 0x1000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&prci PRCI_CLK_TLCLK>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/roms/u-boot/arch/riscv/dts/fu540-hifive-unleashed-a00-ddr.dtsi b/roms/u-boot/arch/riscv/dts/fu540-hifive-unleashed-a00-ddr.dtsi
new file mode 100644
index 000000000..6ed5ccdbc
--- /dev/null
+++ b/roms/u-boot/arch/riscv/dts/fu540-hifive-unleashed-a00-ddr.dtsi
@@ -0,0 +1,1489 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * (C) Copyright 2020 SiFive, Inc
+ */
+
+&dmc {
+	sifive,ddr-params = <
+		0x00000a00	/* DENALI_CTL_00_DATA */
+		0x00000000	/* DENALI_CTL_01_DATA */
+		0x00000000	/* DENALI_CTL_02_DATA */
+		0x00000000	/* DENALI_CTL_03_DATA */
+		0x00000000	/* DENALI_CTL_04_DATA */
+		0x00000000	/* DENALI_CTL_05_DATA */
+		0x0000000a	/* DENALI_CTL_06_DATA */
+		0x0002d362	/* DENALI_CTL_07_DATA */
+		0x00071073	/* DENALI_CTL_08_DATA */
+		0x0a1c0255	/* DENALI_CTL_09_DATA */
+		0x1c1c0400	/* DENALI_CTL_10_DATA */
+		0x0404990b	/* DENALI_CTL_11_DATA */
+		0x2b050405	/* DENALI_CTL_12_DATA */
+		0x0e0c081e	/* DENALI_CTL_13_DATA */
+		0x08090914	/* DENALI_CTL_14_DATA */
+		0x00fde718	/* DENALI_CTL_15_DATA */
+		0x00180a05	/* DENALI_CTL_16_DATA */
+		0x008b130e	/* DENALI_CTL_17_DATA */
+		0x01000118	/* DENALI_CTL_18_DATA */
+		0x0e032101	/* DENALI_CTL_19_DATA */
+		0x00000000	/* DENALI_CTL_20_DATA */
+		0x00000101	/* DENALI_CTL_21_DATA */
+		0x00000000	/* DENALI_CTL_22_DATA */
+		0x0a000000	/* DENALI_CTL_23_DATA */
+		0x00000000	/* DENALI_CTL_24_DATA */
+		0x01450100	/* DENALI_CTL_25_DATA */
+		0x00001c36	/* DENALI_CTL_26_DATA */
+		0x00000005	/* DENALI_CTL_27_DATA */
+		0x00170006	/* DENALI_CTL_28_DATA */
+		0x014e0300	/* DENALI_CTL_29_DATA */
+		0x03010000	/* DENALI_CTL_30_DATA */
+		0x000a0e00	/* DENALI_CTL_31_DATA */
+		0x04030200	/* DENALI_CTL_32_DATA */
+		0x0000031f	/* DENALI_CTL_33_DATA */
+		0x00070004	/* DENALI_CTL_34_DATA */
+		0x00000000	/* DENALI_CTL_35_DATA */
+		0x00000000	/* DENALI_CTL_36_DATA */
+		0x00000000	/* DENALI_CTL_37_DATA */
+		0x00000000	/* DENALI_CTL_38_DATA */
+		0x00000000	/* DENALI_CTL_39_DATA */
+		0x00000000	/* DENALI_CTL_40_DATA */
+		0x00000000	/* DENALI_CTL_41_DATA */
+		0x00000000	/* DENALI_CTL_42_DATA */
+		0x00000000	/* DENALI_CTL_43_DATA */
+		0x00000000	/* DENALI_CTL_44_DATA */
+		0x00000000	/* DENALI_CTL_45_DATA */
+		0x00000000	/* DENALI_CTL_46_DATA */
+		0x00000000	/* DENALI_CTL_47_DATA */
+		0x00000000	/* DENALI_CTL_48_DATA */
+		0x00000000	/* DENALI_CTL_49_DATA */
+		0x00000000	/* DENALI_CTL_50_DATA */
+		0x00000000	/* DENALI_CTL_51_DATA */
+		0x00000000	/* DENALI_CTL_52_DATA */
+		0x00000000	/* DENALI_CTL_53_DATA */
+		0x00000000	/* DENALI_CTL_54_DATA */
+		0x00000000	/* DENALI_CTL_55_DATA */
+		0x00000000	/* DENALI_CTL_56_DATA */
+		0x00000000	/* DENALI_CTL_57_DATA */
+		0x00000000	/* DENALI_CTL_58_DATA */
+		0x00000000	/* DENALI_CTL_59_DATA */
+		0x00000424	/* DENALI_CTL_60_DATA */
+		0x00000201	/* DENALI_CTL_61_DATA */
+		0x00001008	/* DENALI_CTL_62_DATA */
+		0x00000000	/* DENALI_CTL_63_DATA */
+		0x00000200	/* DENALI_CTL_64_DATA */
+		0x00000000	/* DENALI_CTL_65_DATA */
+		0x00000481	/* DENALI_CTL_66_DATA */
+		0x00000400	/* DENALI_CTL_67_DATA */
+		0x00000424	/* DENALI_CTL_68_DATA */
+		0x00000201	/* DENALI_CTL_69_DATA */
+		0x00001008	/* DENALI_CTL_70_DATA */
+		0x00000000	/* DENALI_CTL_71_DATA */
+		0x00000200	/* DENALI_CTL_72_DATA */
+		0x00000000	/* DENALI_CTL_73_DATA */
+		0x00000481	/* DENALI_CTL_74_DATA */
+		0x00000400	/* DENALI_CTL_75_DATA */
+		0x01010000	/* DENALI_CTL_76_DATA */
+		0x00000000	/* DENALI_CTL_77_DATA */
+		0x00000000	/* DENALI_CTL_78_DATA */
+		0x00000000	/* DENALI_CTL_79_DATA */
+		0x00000000	/* DENALI_CTL_80_DATA */
+		0x00000000	/* DENALI_CTL_81_DATA */
+		0x00000000	/* DENALI_CTL_82_DATA */
+		0x00000000	/* DENALI_CTL_83_DATA */
+		0x00000000	/* DENALI_CTL_84_DATA */
+		0x00000000	/* DENALI_CTL_85_DATA */
+		0x00000000	/* DENALI_CTL_86_DATA */
+		0x00000000	/* DENALI_CTL_87_DATA */
+		0x00000000	/* DENALI_CTL_88_DATA */
+		0x00000000	/* DENALI_CTL_89_DATA */
+		0x00000000	/* DENALI_CTL_90_DATA */
+		0x00000000	/* DENALI_CTL_91_DATA */
+		0x00000000	/* DENALI_CTL_92_DATA */
+		0x00000000	/* DENALI_CTL_93_DATA */
+		0x00000000	/* DENALI_CTL_94_DATA */
+		0x00000000	/* DENALI_CTL_95_DATA */
+		0x00000000	/* DENALI_CTL_96_DATA */
+		0x00000000	/* DENALI_CTL_97_DATA */
+		0x00000000	/* DENALI_CTL_98_DATA */
+		0x00000000	/* DENALI_CTL_99_DATA */
+		0x00000000	/* DENALI_CTL_100_DATA */
+		0x00000000	/* DENALI_CTL_101_DATA */
+		0x00000000	/* DENALI_CTL_102_DATA */
+		0x00000000	/* DENALI_CTL_103_DATA */
+		0x00000000	/* DENALI_CTL_104_DATA */
+		0x00000003	/* DENALI_CTL_105_DATA */
+		0x00000000	/* DENALI_CTL_106_DATA */
+		0x00000000	/* DENALI_CTL_107_DATA */
+		0x00000000	/* DENALI_CTL_108_DATA */
+		0x00000000	/* DENALI_CTL_109_DATA */
+		0x01000000	/* DENALI_CTL_110_DATA */
+		0x00040000	/* DENALI_CTL_111_DATA */
+		0x00800200	/* DENALI_CTL_112_DATA */
+		0x00000200	/* DENALI_CTL_113_DATA */
+		0x00000040	/* DENALI_CTL_114_DATA */
+		0x01000100	/* DENALI_CTL_115_DATA */
+		0x0a000002	/* DENALI_CTL_116_DATA */
+		0x0101ffff	/* DENALI_CTL_117_DATA */
+		0x01010101	/* DENALI_CTL_118_DATA */
+		0x01010101	/* DENALI_CTL_119_DATA */
+		0x0000010b	/* DENALI_CTL_120_DATA */
+		0x00000c01	/* DENALI_CTL_121_DATA */
+		0x00000000	/* DENALI_CTL_122_DATA */
+		0x00000000	/* DENALI_CTL_123_DATA */
+		0x00000000	/* DENALI_CTL_124_DATA */
+		0x00000000	/* DENALI_CTL_125_DATA */
+		0x00030300	/* DENALI_CTL_126_DATA */
+		0x00000000	/* DENALI_CTL_127_DATA */
+		0x00010001	/* DENALI_CTL_128_DATA */
+		0x00000000	/* DENALI_CTL_129_DATA */
+		0x00000000	/* DENALI_CTL_130_DATA */
+		0x00000000	/* DENALI_CTL_131_DATA */
+		0x00000000	/* DENALI_CTL_132_DATA */
+		0x00000000	/* DENALI_CTL_133_DATA */
+		0x00000000	/* DENALI_CTL_134_DATA */
+		0x00000000	/* DENALI_CTL_135_DATA */
+		0x00000000	/* DENALI_CTL_136_DATA */
+		0x00000000	/* DENALI_CTL_137_DATA */
+		0x00000000	/* DENALI_CTL_138_DATA */
+		0x00000000	/* DENALI_CTL_139_DATA */
+		0x00000000	/* DENALI_CTL_140_DATA */
+		0x00000000	/* DENALI_CTL_141_DATA */
+		0x00000000	/* DENALI_CTL_142_DATA */
+		0x00000000	/* DENALI_CTL_143_DATA */
+		0x00000000	/* DENALI_CTL_144_DATA */
+		0x00000000	/* DENALI_CTL_145_DATA */
+		0x00000000	/* DENALI_CTL_146_DATA */
+		0x00000000	/* DENALI_CTL_147_DATA */
+		0x00000000	/* DENALI_CTL_148_DATA */
+		0x00000000	/* DENALI_CTL_149_DATA */
+		0x00000000	/* DENALI_CTL_150_DATA */
+		0x00000000	/* DENALI_CTL_151_DATA */
+		0x00000000	/* DENALI_CTL_152_DATA */
+		0x00000000	/* DENALI_CTL_153_DATA */
+		0x00000000	/* DENALI_CTL_154_DATA */
+		0x00000000	/* DENALI_CTL_155_DATA */
+		0x00000000	/* DENALI_CTL_156_DATA */
+		0x00000000	/* DENALI_CTL_157_DATA */
+		0x00000000	/* DENALI_CTL_158_DATA */
+		0x00000000	/* DENALI_CTL_159_DATA */
+		0x00000000	/* DENALI_CTL_160_DATA */
+		0x02010102	/* DENALI_CTL_161_DATA */
+		0x0107070d	/* DENALI_CTL_162_DATA */
+		0x04040400	/* DENALI_CTL_163_DATA */
+		0x03000503	/* DENALI_CTL_164_DATA */
+		0x00000000	/* DENALI_CTL_165_DATA */
+		0x00000000	/* DENALI_CTL_166_DATA */
+		0x00000000	/* DENALI_CTL_167_DATA */
+		0x00000000	/* DENALI_CTL_168_DATA */
+		0x280d0000	/* DENALI_CTL_169_DATA */
+		0x01000000	/* DENALI_CTL_170_DATA */
+		0x00000000	/* DENALI_CTL_171_DATA */
+		0x00010001	/* DENALI_CTL_172_DATA */
+		0x00000000	/* DENALI_CTL_173_DATA */
+		0x00000000	/* DENALI_CTL_174_DATA */
+		0x00000000	/* DENALI_CTL_175_DATA */
+		0x00000000	/* DENALI_CTL_176_DATA */
+		0x00000000	/* DENALI_CTL_177_DATA */
+		0x00000000	/* DENALI_CTL_178_DATA */
+		0x00000000	/* DENALI_CTL_179_DATA */
+		0x00000000	/* DENALI_CTL_180_DATA */
+		0x01000000	/* DENALI_CTL_181_DATA */
+		0x00000001	/* DENALI_CTL_182_DATA */
+		0x00000100	/* DENALI_CTL_183_DATA */
+		0x00000101	/* DENALI_CTL_184_DATA */
+		0x67676701	/* DENALI_CTL_185_DATA */
+		0x67676767	/* DENALI_CTL_186_DATA */
+		0x67676767	/* DENALI_CTL_187_DATA */
+		0x67676767	/* DENALI_CTL_188_DATA */
+		0x67676767	/* DENALI_CTL_189_DATA */
+		0x67676767	/* DENALI_CTL_190_DATA */
+		0x67676767	/* DENALI_CTL_191_DATA */
+		0x67676767	/* DENALI_CTL_192_DATA */
+		0x67676767	/* DENALI_CTL_193_DATA */
+		0x01000067	/* DENALI_CTL_194_DATA */
+		0x00000001	/* DENALI_CTL_195_DATA */
+		0x00000101	/* DENALI_CTL_196_DATA */
+		0x00000000	/* DENALI_CTL_197_DATA */
+		0x00000000	/* DENALI_CTL_198_DATA */
+		0x00000000	/* DENALI_CTL_199_DATA */
+		0x00000000	/* DENALI_CTL_200_DATA */
+		0x00000000	/* DENALI_CTL_201_DATA */
+		0x00000000	/* DENALI_CTL_202_DATA */
+		0x00000000	/* DENALI_CTL_203_DATA */
+		0x00000000	/* DENALI_CTL_204_DATA */
+		0x00000000	/* DENALI_CTL_205_DATA */
+		0x00000000	/* DENALI_CTL_206_DATA */
+		0x00000000	/* DENALI_CTL_207_DATA */
+		0x00000001	/* DENALI_CTL_208_DATA */
+		0x00000000	/* DENALI_CTL_209_DATA */
+		0x007fffff	/* DENALI_CTL_210_DATA */
+		0x00000000	/* DENALI_CTL_211_DATA */
+		0x007fffff	/* DENALI_CTL_212_DATA */
+		0x00000000	/* DENALI_CTL_213_DATA */
+		0x007fffff	/* DENALI_CTL_214_DATA */
+		0x00000000	/* DENALI_CTL_215_DATA */
+		0x007fffff	/* DENALI_CTL_216_DATA */
+		0x00000000	/* DENALI_CTL_217_DATA */
+		0x007fffff	/* DENALI_CTL_218_DATA */
+		0x00000000	/* DENALI_CTL_219_DATA */
+		0x007fffff	/* DENALI_CTL_220_DATA */
+		0x00000000	/* DENALI_CTL_221_DATA */
+		0x007fffff	/* DENALI_CTL_222_DATA */
+		0x00000000	/* DENALI_CTL_223_DATA */
+		0x037fffff	/* DENALI_CTL_224_DATA */
+		0xffffffff	/* DENALI_CTL_225_DATA */
+		0x000f000f	/* DENALI_CTL_226_DATA */
+		0x00ffff03	/* DENALI_CTL_227_DATA */
+		0x000fffff	/* DENALI_CTL_228_DATA */
+		0x0003000f	/* DENALI_CTL_229_DATA */
+		0xffffffff	/* DENALI_CTL_230_DATA */
+		0x000f000f	/* DENALI_CTL_231_DATA */
+		0x00ffff03	/* DENALI_CTL_232_DATA */
+		0x000fffff	/* DENALI_CTL_233_DATA */
+		0x0003000f	/* DENALI_CTL_234_DATA */
+		0xffffffff	/* DENALI_CTL_235_DATA */
+		0x000f000f	/* DENALI_CTL_236_DATA */
+		0x00ffff03	/* DENALI_CTL_237_DATA */
+		0x000fffff	/* DENALI_CTL_238_DATA */
+		0x0003000f	/* DENALI_CTL_239_DATA */
+		0xffffffff	/* DENALI_CTL_240_DATA */
+		0x000f000f	/* DENALI_CTL_241_DATA */
+		0x00ffff03	/* DENALI_CTL_242_DATA */
+		0x000fffff	/* DENALI_CTL_243_DATA */
+		0x6407000f	/* DENALI_CTL_244_DATA */
+		0x01640001	/* DENALI_CTL_245_DATA */
+		0x00000000	/* DENALI_CTL_246_DATA */
+		0x00000000	/* DENALI_CTL_247_DATA */
+		0x00001700	/* DENALI_CTL_248_DATA */
+		0x00386c05	/* DENALI_CTL_249_DATA */
+		0x02000200	/* DENALI_CTL_250_DATA */
+		0x02000200	/* DENALI_CTL_251_DATA */
+		0x0000386c	/* DENALI_CTL_252_DATA */
+		0x00023438	/* DENALI_CTL_253_DATA */
+		0x02020d10	/* DENALI_CTL_254_DATA */
+		0x00140303	/* DENALI_CTL_255_DATA */
+		0x00000000	/* DENALI_CTL_256_DATA */
+		0x00000000	/* DENALI_CTL_257_DATA */
+		0x00001403	/* DENALI_CTL_258_DATA */
+		0x00000000	/* DENALI_CTL_259_DATA */
+		0x00000000	/* DENALI_CTL_260_DATA */
+		0x00000000	/* DENALI_CTL_261_DATA */
+		0x00000000	/* DENALI_CTL_262_DATA */
+		0x0d010000	/* DENALI_CTL_263_DATA */
+		0x00000008	/* DENALI_CTL_264_DATA */
+		0x31706542	/* DENALI_PHY_00_DATA */
+		0x0004c008	/* DENALI_PHY_01_DATA */
+		0x000000da	/* DENALI_PHY_02_DATA */
+		0x00000000	/* DENALI_PHY_03_DATA */
+		0x00000000	/* DENALI_PHY_04_DATA */
+		0x00010000	/* DENALI_PHY_05_DATA */
+		0x01DDDD90	/* DENALI_PHY_06_DATA */
+		0x01DDDD90	/* DENALI_PHY_07_DATA */
+		0x01030000	/* DENALI_PHY_08_DATA */
+		0x01000000	/* DENALI_PHY_09_DATA */
+		0x00c00000	/* DENALI_PHY_10_DATA */
+		0x00000007	/* DENALI_PHY_11_DATA */
+		0x00000000	/* DENALI_PHY_12_DATA */
+		0x00000000	/* DENALI_PHY_13_DATA */
+		0x04000408	/* DENALI_PHY_14_DATA */
+		0x00000408	/* DENALI_PHY_15_DATA */
+		0x00e4e400	/* DENALI_PHY_16_DATA */
+		0x00000000	/* DENALI_PHY_17_DATA */
+		0x00000000	/* DENALI_PHY_18_DATA */
+		0x00000000	/* DENALI_PHY_19_DATA */
+		0x00000000	/* DENALI_PHY_20_DATA */
+		0x00000000	/* DENALI_PHY_21_DATA */
+		0x00000000	/* DENALI_PHY_22_DATA */
+		0x00000000	/* DENALI_PHY_23_DATA */
+		0x00000000	/* DENALI_PHY_24_DATA */
+		0x00000000	/* DENALI_PHY_25_DATA */
+		0x00000000	/* DENALI_PHY_26_DATA */
+		0x00000000	/* DENALI_PHY_27_DATA */
+		0x00000000	/* DENALI_PHY_28_DATA */
+		0x00000000	/* DENALI_PHY_29_DATA */
+		0x00000000	/* DENALI_PHY_30_DATA */
+		0x00000000	/* DENALI_PHY_31_DATA */
+		0x00000000	/* DENALI_PHY_32_DATA */
+		0x00200000	/* DENALI_PHY_33_DATA */
+		0x00000000	/* DENALI_PHY_34_DATA */
+		0x00000000	/* DENALI_PHY_35_DATA */
+		0x00000000	/* DENALI_PHY_36_DATA */
+		0x00000000	/* DENALI_PHY_37_DATA */
+		0x00000000	/* DENALI_PHY_38_DATA */
+		0x00000000	/* DENALI_PHY_39_DATA */
+		0x02800280	/* DENALI_PHY_40_DATA */
+		0x02800280	/* DENALI_PHY_41_DATA */
+		0x02800280	/* DENALI_PHY_42_DATA */
+		0x02800280	/* DENALI_PHY_43_DATA */
+		0x00000280	/* DENALI_PHY_44_DATA */
+		0x00000000	/* DENALI_PHY_45_DATA */
+		0x00000000	/* DENALI_PHY_46_DATA */
+		0x00000000	/* DENALI_PHY_47_DATA */
+		0x00000000	/* DENALI_PHY_48_DATA */
+		0x00000000	/* DENALI_PHY_49_DATA */
+		0x00800080	/* DENALI_PHY_50_DATA */
+		0x00800080	/* DENALI_PHY_51_DATA */
+		0x00800080	/* DENALI_PHY_52_DATA */
+		0x00800080	/* DENALI_PHY_53_DATA */
+		0x00800080	/* DENALI_PHY_54_DATA */
+		0x00800080	/* DENALI_PHY_55_DATA */
+		0x00800080	/* DENALI_PHY_56_DATA */
+		0x00800080	/* DENALI_PHY_57_DATA */
+		0x00800080	/* DENALI_PHY_58_DATA */
+		0x000100da	/* DENALI_PHY_59_DATA */
+		0x01000200	/* DENALI_PHY_60_DATA */
+		0x00000000	/* DENALI_PHY_61_DATA */
+		0x00000000	/* DENALI_PHY_62_DATA */
+		0x00000002	/* DENALI_PHY_63_DATA */
+		0x51313152	/* DENALI_PHY_64_DATA */
+		0x80013130	/* DENALI_PHY_65_DATA */
+		0x02000080	/* DENALI_PHY_66_DATA */
+		0x00100001	/* DENALI_PHY_67_DATA */
+		0x0c064208	/* DENALI_PHY_68_DATA */
+		0x000f0c0f	/* DENALI_PHY_69_DATA */
+		0x01000140	/* DENALI_PHY_70_DATA */
+		0x0000000c	/* DENALI_PHY_71_DATA */
+		0x00000000	/* DENALI_PHY_72_DATA */
+		0x00000000	/* DENALI_PHY_73_DATA */
+		0x00000000	/* DENALI_PHY_74_DATA */
+		0x00000000	/* DENALI_PHY_75_DATA */
+		0x00000000	/* DENALI_PHY_76_DATA */
+		0x00000000	/* DENALI_PHY_77_DATA */
+		0x00000000	/* DENALI_PHY_78_DATA */
+		0x00000000	/* DENALI_PHY_79_DATA */
+		0x00000000	/* DENALI_PHY_80_DATA */
+		0x00000000	/* DENALI_PHY_81_DATA */
+		0x00000000	/* DENALI_PHY_82_DATA */
+		0x00000000	/* DENALI_PHY_83_DATA */
+		0x00000000	/* DENALI_PHY_84_DATA */
+		0x00000000	/* DENALI_PHY_85_DATA */
+		0x00000000	/* DENALI_PHY_86_DATA */
+		0x00000000	/* DENALI_PHY_87_DATA */
+		0x00000000	/* DENALI_PHY_88_DATA */
+		0x00000000	/* DENALI_PHY_89_DATA */
+		0x00000000	/* DENALI_PHY_90_DATA */
+		0x00000000	/* DENALI_PHY_91_DATA */
+		0x00000000	/* DENALI_PHY_92_DATA */
+		0x00000000	/* DENALI_PHY_93_DATA */
+		0x00000000	/* DENALI_PHY_94_DATA */
+		0x00000000	/* DENALI_PHY_95_DATA */
+		0x00000000	/* DENALI_PHY_96_DATA */
+		0x00000000	/* DENALI_PHY_97_DATA */
+		0x00000000	/* DENALI_PHY_98_DATA */
+		0x00000000	/* DENALI_PHY_99_DATA */
+		0x00000000	/* DENALI_PHY_100_DATA */
+		0x00000000	/* DENALI_PHY_101_DATA */
+		0x00000000	/* DENALI_PHY_102_DATA */
+		0x00000000	/* DENALI_PHY_103_DATA */
+		0x00000000	/* DENALI_PHY_104_DATA */
+		0x00000000	/* DENALI_PHY_105_DATA */
+		0x00000000	/* DENALI_PHY_106_DATA */
+		0x00000000	/* DENALI_PHY_107_DATA */
+		0x00000000	/* DENALI_PHY_108_DATA */
+		0x00000000	/* DENALI_PHY_109_DATA */
+		0x00000000	/* DENALI_PHY_110_DATA */
+		0x00000000	/* DENALI_PHY_111_DATA */
+		0x00000000	/* DENALI_PHY_112_DATA */
+		0x00000000	/* DENALI_PHY_113_DATA */
+		0x00000000	/* DENALI_PHY_114_DATA */
+		0x00000000	/* DENALI_PHY_115_DATA */
+		0x00000000	/* DENALI_PHY_116_DATA */
+		0x00000000	/* DENALI_PHY_117_DATA */
+		0x00000000	/* DENALI_PHY_118_DATA */
+		0x00000000	/* DENALI_PHY_119_DATA */
+		0x00000000	/* DENALI_PHY_120_DATA */
+		0x00000000	/* DENALI_PHY_121_DATA */
+		0x00000000	/* DENALI_PHY_122_DATA */
+		0x00000000	/* DENALI_PHY_123_DATA */
+		0x00000000	/* DENALI_PHY_124_DATA */
+		0x00000000	/* DENALI_PHY_125_DATA */
+		0x00000000	/* DENALI_PHY_126_DATA */
+		0x00000000	/* DENALI_PHY_127_DATA */
+		0x40263571	/* DENALI_PHY_128_DATA */
+		0x0004c008	/* DENALI_PHY_129_DATA */
+		0x000000da	/* DENALI_PHY_130_DATA */
+		0x00000000	/* DENALI_PHY_131_DATA */
+		0x00000000	/* DENALI_PHY_132_DATA */
+		0x00010000	/* DENALI_PHY_133_DATA */
+		0x01DDDD90	/* DENALI_PHY_134_DATA */
+		0x01DDDD90	/* DENALI_PHY_135_DATA */
+		0x01030000	/* DENALI_PHY_136_DATA */
+		0x01000000	/* DENALI_PHY_137_DATA */
+		0x00c00000	/* DENALI_PHY_138_DATA */
+		0x00000007	/* DENALI_PHY_139_DATA */
+		0x00000000	/* DENALI_PHY_140_DATA */
+		0x00000000	/* DENALI_PHY_141_DATA */
+		0x04000408	/* DENALI_PHY_142_DATA */
+		0x00000408	/* DENALI_PHY_143_DATA */
+		0x00e4e400	/* DENALI_PHY_144_DATA */
+		0x00000000	/* DENALI_PHY_145_DATA */
+		0x00000000	/* DENALI_PHY_146_DATA */
+		0x00000000	/* DENALI_PHY_147_DATA */
+		0x00000000	/* DENALI_PHY_148_DATA */
+		0x00000000	/* DENALI_PHY_149_DATA */
+		0x00000000	/* DENALI_PHY_150_DATA */
+		0x00000000	/* DENALI_PHY_151_DATA */
+		0x00000000	/* DENALI_PHY_152_DATA */
+		0x00000000	/* DENALI_PHY_153_DATA */
+		0x00000000	/* DENALI_PHY_154_DATA */
+		0x00000000	/* DENALI_PHY_155_DATA */
+		0x00000000	/* DENALI_PHY_156_DATA */
+		0x00000000	/* DENALI_PHY_157_DATA */
+		0x00000000	/* DENALI_PHY_158_DATA */
+		0x00000000	/* DENALI_PHY_159_DATA */
+		0x00000000	/* DENALI_PHY_160_DATA */
+		0x00200000	/* DENALI_PHY_161_DATA */
+		0x00000000	/* DENALI_PHY_162_DATA */
+		0x00000000	/* DENALI_PHY_163_DATA */
+		0x00000000	/* DENALI_PHY_164_DATA */
+		0x00000000	/* DENALI_PHY_165_DATA */
+		0x00000000	/* DENALI_PHY_166_DATA */
+		0x00000000	/* DENALI_PHY_167_DATA */
+		0x02800280	/* DENALI_PHY_168_DATA */
+		0x02800280	/* DENALI_PHY_169_DATA */
+		0x02800280	/* DENALI_PHY_170_DATA */
+		0x02800280	/* DENALI_PHY_171_DATA */
+		0x00000280	/* DENALI_PHY_172_DATA */
+		0x00000000	/* DENALI_PHY_173_DATA */
+		0x00000000	/* DENALI_PHY_174_DATA */
+		0x00000000	/* DENALI_PHY_175_DATA */
+		0x00000000	/* DENALI_PHY_176_DATA */
+		0x00000000	/* DENALI_PHY_177_DATA */
+		0x00800080	/* DENALI_PHY_178_DATA */
+		0x00800080	/* DENALI_PHY_179_DATA */
+		0x00800080	/* DENALI_PHY_180_DATA */
+		0x00800080	/* DENALI_PHY_181_DATA */
+		0x00800080	/* DENALI_PHY_182_DATA */
+		0x00800080	/* DENALI_PHY_183_DATA */
+		0x00800080	/* DENALI_PHY_184_DATA */
+		0x00800080	/* DENALI_PHY_185_DATA */
+		0x00800080	/* DENALI_PHY_186_DATA */
+		0x000100da	/* DENALI_PHY_187_DATA */
+		0x01000200	/* DENALI_PHY_188_DATA */
+		0x00000000	/* DENALI_PHY_189_DATA */
+		0x00000000	/* DENALI_PHY_190_DATA */
+		0x00000002	/* DENALI_PHY_191_DATA */
+		0x51313152	/* DENALI_PHY_192_DATA */
+		0x80013130	/* DENALI_PHY_193_DATA */
+		0x02000080	/* DENALI_PHY_194_DATA */
+		0x00100001	/* DENALI_PHY_195_DATA */
+		0x0c064208	/* DENALI_PHY_196_DATA */
+		0x000f0c0f	/* DENALI_PHY_197_DATA */
+		0x01000140	/* DENALI_PHY_198_DATA */
+		0x0000000c	/* DENALI_PHY_199_DATA */
+		0x00000000	/* DENALI_PHY_200_DATA */
+		0x00000000	/* DENALI_PHY_201_DATA */
+		0x00000000	/* DENALI_PHY_202_DATA */
+		0x00000000	/* DENALI_PHY_203_DATA */
+		0x00000000	/* DENALI_PHY_204_DATA */
+		0x00000000	/* DENALI_PHY_205_DATA */
+		0x00000000	/* DENALI_PHY_206_DATA */
+		0x00000000	/* DENALI_PHY_207_DATA */
+		0x00000000	/* DENALI_PHY_208_DATA */
+		0x00000000	/* DENALI_PHY_209_DATA */
+		0x00000000	/* DENALI_PHY_210_DATA */
+		0x00000000	/* DENALI_PHY_211_DATA */
+		0x00000000	/* DENALI_PHY_212_DATA */
+		0x00000000	/* DENALI_PHY_213_DATA */
+		0x00000000	/* DENALI_PHY_214_DATA */
+		0x00000000	/* DENALI_PHY_215_DATA */
+		0x00000000	/* DENALI_PHY_216_DATA */
+		0x00000000	/* DENALI_PHY_217_DATA */
+		0x00000000	/* DENALI_PHY_218_DATA */
+		0x00000000	/* DENALI_PHY_219_DATA */
+		0x00000000	/* DENALI_PHY_220_DATA */
+		0x00000000	/* DENALI_PHY_221_DATA */
+		0x00000000	/* DENALI_PHY_222_DATA */
+		0x00000000	/* DENALI_PHY_223_DATA */
+		0x00000000	/* DENALI_PHY_224_DATA */
+		0x00000000	/* DENALI_PHY_225_DATA */
+		0x00000000	/* DENALI_PHY_226_DATA */
+		0x00000000	/* DENALI_PHY_227_DATA */
+		0x00000000	/* DENALI_PHY_228_DATA */
+		0x00000000	/* DENALI_PHY_229_DATA */
+		0x00000000	/* DENALI_PHY_230_DATA */
+		0x00000000	/* DENALI_PHY_231_DATA */
+		0x00000000	/* DENALI_PHY_232_DATA */
+		0x00000000	/* DENALI_PHY_233_DATA */
+		0x00000000	/* DENALI_PHY_234_DATA */
+		0x00000000	/* DENALI_PHY_235_DATA */
+		0x00000000	/* DENALI_PHY_236_DATA */
+		0x00000000	/* DENALI_PHY_237_DATA */
+		0x00000000	/* DENALI_PHY_238_DATA */
+		0x00000000	/* DENALI_PHY_239_DATA */
+		0x00000000	/* DENALI_PHY_240_DATA */
+		0x00000000	/* DENALI_PHY_241_DATA */
+		0x00000000	/* DENALI_PHY_242_DATA */
+		0x00000000	/* DENALI_PHY_243_DATA */
+		0x00000000	/* DENALI_PHY_244_DATA */
+		0x00000000	/* DENALI_PHY_245_DATA */
+		0x00000000	/* DENALI_PHY_246_DATA */
+		0x00000000	/* DENALI_PHY_247_DATA */
+		0x00000000	/* DENALI_PHY_248_DATA */
+		0x00000000	/* DENALI_PHY_249_DATA */
+		0x00000000	/* DENALI_PHY_250_DATA */
+		0x00000000	/* DENALI_PHY_251_DATA */
+		0x00000000	/* DENALI_PHY_252_DATA */
+		0x00000000	/* DENALI_PHY_253_DATA */
+		0x00000000	/* DENALI_PHY_254_DATA */
+		0x00000000	/* DENALI_PHY_255_DATA */
+		0x46052371	/* DENALI_PHY_256_DATA */
+		0x0004c008	/* DENALI_PHY_257_DATA */
+		0x000000da	/* DENALI_PHY_258_DATA */
+		0x00000000	/* DENALI_PHY_259_DATA */
+		0x00000000	/* DENALI_PHY_260_DATA */
+		0x00010000	/* DENALI_PHY_261_DATA */
+		0x01DDDD90	/* DENALI_PHY_262_DATA */
+		0x01DDDD90	/* DENALI_PHY_263_DATA */
+		0x01030000	/* DENALI_PHY_264_DATA */
+		0x01000000	/* DENALI_PHY_265_DATA */
+		0x00c00000	/* DENALI_PHY_266_DATA */
+		0x00000007	/* DENALI_PHY_267_DATA */
+		0x00000000	/* DENALI_PHY_268_DATA */
+		0x00000000	/* DENALI_PHY_269_DATA */
+		0x04000408	/* DENALI_PHY_270_DATA */
+		0x00000408	/* DENALI_PHY_271_DATA */
+		0x00e4e400	/* DENALI_PHY_272_DATA */
+		0x00000000	/* DENALI_PHY_273_DATA */
+		0x00000000	/* DENALI_PHY_274_DATA */
+		0x00000000	/* DENALI_PHY_275_DATA */
+		0x00000000	/* DENALI_PHY_276_DATA */
+		0x00000000	/* DENALI_PHY_277_DATA */
+		0x00000000	/* DENALI_PHY_278_DATA */
+		0x00000000	/* DENALI_PHY_279_DATA */
+		0x00000000	/* DENALI_PHY_280_DATA */
+		0x00000000	/* DENALI_PHY_281_DATA */
+		0x00000000	/* DENALI_PHY_282_DATA */
+		0x00000000	/* DENALI_PHY_283_DATA */
+		0x00000000	/* DENALI_PHY_284_DATA */
+		0x00000000	/* DENALI_PHY_285_DATA */
+		0x00000000	/* DENALI_PHY_286_DATA */
+		0x00000000	/* DENALI_PHY_287_DATA */
+		0x00000000	/* DENALI_PHY_288_DATA */
+		0x00200000	/* DENALI_PHY_289_DATA */
+		0x00000000	/* DENALI_PHY_290_DATA */
+		0x00000000	/* DENALI_PHY_291_DATA */
+		0x00000000	/* DENALI_PHY_292_DATA */
+		0x00000000	/* DENALI_PHY_293_DATA */
+		0x00000000	/* DENALI_PHY_294_DATA */
+		0x00000000	/* DENALI_PHY_295_DATA */
+		0x02800280	/* DENALI_PHY_296_DATA */
+		0x02800280	/* DENALI_PHY_297_DATA */
+		0x02800280	/* DENALI_PHY_298_DATA */
+		0x02800280	/* DENALI_PHY_299_DATA */
+		0x00000280	/* DENALI_PHY_300_DATA */
+		0x00000000	/* DENALI_PHY_301_DATA */
+		0x00000000	/* DENALI_PHY_302_DATA */
+		0x00000000	/* DENALI_PHY_303_DATA */
+		0x00000000	/* DENALI_PHY_304_DATA */
+		0x00000000	/* DENALI_PHY_305_DATA */
+		0x00800080	/* DENALI_PHY_306_DATA */
+		0x00800080	/* DENALI_PHY_307_DATA */
+		0x00800080	/* DENALI_PHY_308_DATA */
+		0x00800080	/* DENALI_PHY_309_DATA */
+		0x00800080	/* DENALI_PHY_310_DATA */
+		0x00800080	/* DENALI_PHY_311_DATA */
+		0x00800080	/* DENALI_PHY_312_DATA */
+		0x00800080	/* DENALI_PHY_313_DATA */
+		0x00800080	/* DENALI_PHY_314_DATA */
+		0x000100da	/* DENALI_PHY_315_DATA */
+		0x00000200	/* DENALI_PHY_316_DATA */
+		0x00000000	/* DENALI_PHY_317_DATA */
+		0x00000000	/* DENALI_PHY_318_DATA */
+		0x00000002	/* DENALI_PHY_319_DATA */
+		0x51313152	/* DENALI_PHY_320_DATA */
+		0x80013130	/* DENALI_PHY_321_DATA */
+		0x02000080	/* DENALI_PHY_322_DATA */
+		0x00100001	/* DENALI_PHY_323_DATA */
+		0x0c064208	/* DENALI_PHY_324_DATA */
+		0x000f0c0f	/* DENALI_PHY_325_DATA */
+		0x01000140	/* DENALI_PHY_326_DATA */
+		0x0000000c	/* DENALI_PHY_327_DATA */
+		0x00000000	/* DENALI_PHY_328_DATA */
+		0x00000000	/* DENALI_PHY_329_DATA */
+		0x00000000	/* DENALI_PHY_330_DATA */
+		0x00000000	/* DENALI_PHY_331_DATA */
+		0x00000000	/* DENALI_PHY_332_DATA */
+		0x00000000	/* DENALI_PHY_333_DATA */
+		0x00000000	/* DENALI_PHY_334_DATA */
+		0x00000000	/* DENALI_PHY_335_DATA */
+		0x00000000	/* DENALI_PHY_336_DATA */
+		0x00000000	/* DENALI_PHY_337_DATA */
+		0x00000000	/* DENALI_PHY_338_DATA */
+		0x00000000	/* DENALI_PHY_339_DATA */
+		0x00000000	/* DENALI_PHY_340_DATA */
+		0x00000000	/* DENALI_PHY_341_DATA */
+		0x00000000	/* DENALI_PHY_342_DATA */
+		0x00000000	/* DENALI_PHY_343_DATA */
+		0x00000000	/* DENALI_PHY_344_DATA */
+		0x00000000	/* DENALI_PHY_345_DATA */
+		0x00000000	/* DENALI_PHY_346_DATA */
+		0x00000000	/* DENALI_PHY_347_DATA */
+		0x00000000	/* DENALI_PHY_348_DATA */
+		0x00000000	/* DENALI_PHY_349_DATA */
+		0x00000000	/* DENALI_PHY_350_DATA */
+		0x00000000	/* DENALI_PHY_351_DATA */
+		0x00000000	/* DENALI_PHY_352_DATA */
+		0x00000000	/* DENALI_PHY_353_DATA */
+		0x00000000	/* DENALI_PHY_354_DATA */
+		0x00000000	/* DENALI_PHY_355_DATA */
+		0x00000000	/* DENALI_PHY_356_DATA */
+		0x00000000	/* DENALI_PHY_357_DATA */
+		0x00000000	/* DENALI_PHY_358_DATA */
+		0x00000000	/* DENALI_PHY_359_DATA */
+		0x00000000	/* DENALI_PHY_360_DATA */
+		0x00000000	/* DENALI_PHY_361_DATA */
+		0x00000000	/* DENALI_PHY_362_DATA */
+		0x00000000	/* DENALI_PHY_363_DATA */
+		0x00000000	/* DENALI_PHY_364_DATA */
+		0x00000000	/* DENALI_PHY_365_DATA */
+		0x00000000	/* DENALI_PHY_366_DATA */
+		0x00000000	/* DENALI_PHY_367_DATA */
+		0x00000000	/* DENALI_PHY_368_DATA */
+		0x00000000	/* DENALI_PHY_369_DATA */
+		0x00000000	/* DENALI_PHY_370_DATA */
+		0x00000000	/* DENALI_PHY_371_DATA */
+		0x00000000	/* DENALI_PHY_372_DATA */
+		0x00000000	/* DENALI_PHY_373_DATA */
+		0x00000000	/* DENALI_PHY_374_DATA */
+		0x00000000	/* DENALI_PHY_375_DATA */
+		0x00000000	/* DENALI_PHY_376_DATA */
+		0x00000000	/* DENALI_PHY_377_DATA */
+		0x00000000	/* DENALI_PHY_378_DATA */
+		0x00000000	/* DENALI_PHY_379_DATA */
+		0x00000000	/* DENALI_PHY_380_DATA */
+		0x00000000	/* DENALI_PHY_381_DATA */
+		0x00000000	/* DENALI_PHY_382_DATA */
+		0x00000000	/* DENALI_PHY_383_DATA */
+		0x37654120	/* DENALI_PHY_384_DATA */
+		0x0004c008	/* DENALI_PHY_385_DATA */
+		0x000000da	/* DENALI_PHY_386_DATA */
+		0x00000000	/* DENALI_PHY_387_DATA */
+		0x00000000	/* DENALI_PHY_388_DATA */
+		0x00010000	/* DENALI_PHY_389_DATA */
+		0x01DDDD90	/* DENALI_PHY_390_DATA */
+		0x01DDDD90	/* DENALI_PHY_391_DATA */
+		0x01030000	/* DENALI_PHY_392_DATA */
+		0x01000000	/* DENALI_PHY_393_DATA */
+		0x00c00000	/* DENALI_PHY_394_DATA */
+		0x00000007	/* DENALI_PHY_395_DATA */
+		0x00000000	/* DENALI_PHY_396_DATA */
+		0x00000000	/* DENALI_PHY_397_DATA */
+		0x04000408	/* DENALI_PHY_398_DATA */
+		0x00000408	/* DENALI_PHY_399_DATA */
+		0x00e4e400	/* DENALI_PHY_400_DATA */
+		0x00000000	/* DENALI_PHY_401_DATA */
+		0x00000000	/* DENALI_PHY_402_DATA */
+		0x00000000	/* DENALI_PHY_403_DATA */
+		0x00000000	/* DENALI_PHY_404_DATA */
+		0x00000000	/* DENALI_PHY_405_DATA */
+		0x00000000	/* DENALI_PHY_406_DATA */
+		0x00000000	/* DENALI_PHY_407_DATA */
+		0x00000000	/* DENALI_PHY_408_DATA */
+		0x00000000	/* DENALI_PHY_409_DATA */
+		0x00000000	/* DENALI_PHY_410_DATA */
+		0x00000000	/* DENALI_PHY_411_DATA */
+		0x00000000	/* DENALI_PHY_412_DATA */
+		0x00000000	/* DENALI_PHY_413_DATA */
+		0x00000000	/* DENALI_PHY_414_DATA */
+		0x00000000	/* DENALI_PHY_415_DATA */
+		0x00000000	/* DENALI_PHY_416_DATA */
+		0x00200000	/* DENALI_PHY_417_DATA */
+		0x00000000	/* DENALI_PHY_418_DATA */
+		0x00000000	/* DENALI_PHY_419_DATA */
+		0x00000000	/* DENALI_PHY_420_DATA */
+		0x00000000	/* DENALI_PHY_421_DATA */
+		0x00000000	/* DENALI_PHY_422_DATA */
+		0x00000000	/* DENALI_PHY_423_DATA */
+		0x02800280	/* DENALI_PHY_424_DATA */
+		0x02800280	/* DENALI_PHY_425_DATA */
+		0x02800280	/* DENALI_PHY_426_DATA */
+		0x02800280	/* DENALI_PHY_427_DATA */
+		0x00000280	/* DENALI_PHY_428_DATA */
+		0x00000000	/* DENALI_PHY_429_DATA */
+		0x00000000	/* DENALI_PHY_430_DATA */
+		0x00000000	/* DENALI_PHY_431_DATA */
+		0x00000000	/* DENALI_PHY_432_DATA */
+		0x00000000	/* DENALI_PHY_433_DATA */
+		0x00800080	/* DENALI_PHY_434_DATA */
+		0x00800080	/* DENALI_PHY_435_DATA */
+		0x00800080	/* DENALI_PHY_436_DATA */
+		0x00800080	/* DENALI_PHY_437_DATA */
+		0x00800080	/* DENALI_PHY_438_DATA */
+		0x00800080	/* DENALI_PHY_439_DATA */
+		0x00800080	/* DENALI_PHY_440_DATA */
+		0x00800080	/* DENALI_PHY_441_DATA */
+		0x00800080	/* DENALI_PHY_442_DATA */
+		0x000100da	/* DENALI_PHY_443_DATA */
+		0x00000200	/* DENALI_PHY_444_DATA */
+		0x00000000	/* DENALI_PHY_445_DATA */
+		0x00000000	/* DENALI_PHY_446_DATA */
+		0x00000002	/* DENALI_PHY_447_DATA */
+		0x51313152	/* DENALI_PHY_448_DATA */
+		0x80013130	/* DENALI_PHY_449_DATA */
+		0x02000080	/* DENALI_PHY_450_DATA */
+		0x00100001	/* DENALI_PHY_451_DATA */
+		0x0c064208	/* DENALI_PHY_452_DATA */
+		0x000f0c0f	/* DENALI_PHY_453_DATA */
+		0x01000140	/* DENALI_PHY_454_DATA */
+		0x0000000c	/* DENALI_PHY_455_DATA */
+		0x00000000	/* DENALI_PHY_456_DATA */
+		0x00000000	/* DENALI_PHY_457_DATA */
+		0x00000000	/* DENALI_PHY_458_DATA */
+		0x00000000	/* DENALI_PHY_459_DATA */
+		0x00000000	/* DENALI_PHY_460_DATA */
+		0x00000000	/* DENALI_PHY_461_DATA */
+		0x00000000	/* DENALI_PHY_462_DATA */
+		0x00000000	/* DENALI_PHY_463_DATA */
+		0x00000000	/* DENALI_PHY_464_DATA */
+		0x00000000	/* DENALI_PHY_465_DATA */
+		0x00000000	/* DENALI_PHY_466_DATA */
+		0x00000000	/* DENALI_PHY_467_DATA */
+		0x00000000	/* DENALI_PHY_468_DATA */
+		0x00000000	/* DENALI_PHY_469_DATA */
+		0x00000000	/* DENALI_PHY_470_DATA */
+		0x00000000	/* DENALI_PHY_471_DATA */
+		0x00000000	/* DENALI_PHY_472_DATA */
+		0x00000000	/* DENALI_PHY_473_DATA */
+		0x00000000	/* DENALI_PHY_474_DATA */
+		0x00000000	/* DENALI_PHY_475_DATA */
+		0x00000000	/* DENALI_PHY_476_DATA */
+		0x00000000	/* DENALI_PHY_477_DATA */
+		0x00000000	/* DENALI_PHY_478_DATA */
+		0x00000000	/* DENALI_PHY_479_DATA */
+		0x00000000	/* DENALI_PHY_480_DATA */
+		0x00000000	/* DENALI_PHY_481_DATA */
+		0x00000000	/* DENALI_PHY_482_DATA */
+		0x00000000	/* DENALI_PHY_483_DATA */
+		0x00000000	/* DENALI_PHY_484_DATA */
+		0x00000000	/* DENALI_PHY_485_DATA */
+		0x00000000	/* DENALI_PHY_486_DATA */
+		0x00000000	/* DENALI_PHY_487_DATA */
+		0x00000000	/* DENALI_PHY_488_DATA */
+		0x00000000	/* DENALI_PHY_489_DATA */
+		0x00000000	/* DENALI_PHY_490_DATA */
+		0x00000000	/* DENALI_PHY_491_DATA */
+		0x00000000	/* DENALI_PHY_492_DATA */
+		0x00000000	/* DENALI_PHY_493_DATA */
+		0x00000000	/* DENALI_PHY_494_DATA */
+		0x00000000	/* DENALI_PHY_495_DATA */
+		0x00000000	/* DENALI_PHY_496_DATA */
+		0x00000000	/* DENALI_PHY_497_DATA */
+		0x00000000	/* DENALI_PHY_498_DATA */
+		0x00000000	/* DENALI_PHY_499_DATA */
+		0x00000000	/* DENALI_PHY_500_DATA */
+		0x00000000	/* DENALI_PHY_501_DATA */
+		0x00000000	/* DENALI_PHY_502_DATA */
+		0x00000000	/* DENALI_PHY_503_DATA */
+		0x00000000	/* DENALI_PHY_504_DATA */
+		0x00000000	/* DENALI_PHY_505_DATA */
+		0x00000000	/* DENALI_PHY_506_DATA */
+		0x00000000	/* DENALI_PHY_507_DATA */
+		0x00000000	/* DENALI_PHY_508_DATA */
+		0x00000000	/* DENALI_PHY_509_DATA */
+		0x00000000	/* DENALI_PHY_510_DATA */
+		0x00000000	/* DENALI_PHY_511_DATA */
+		0x24316750	/* DENALI_PHY_512_DATA */
+		0x0004c008	/* DENALI_PHY_513_DATA */
+		0x000000da	/* DENALI_PHY_514_DATA */
+		0x00000000	/* DENALI_PHY_515_DATA */
+		0x00000000	/* DENALI_PHY_516_DATA */
+		0x00010000	/* DENALI_PHY_517_DATA */
+		0x01DDDD90	/* DENALI_PHY_518_DATA */
+		0x01DDDD90	/* DENALI_PHY_519_DATA */
+		0x01030000	/* DENALI_PHY_520_DATA */
+		0x01000000	/* DENALI_PHY_521_DATA */
+		0x00c00000	/* DENALI_PHY_522_DATA */
+		0x00000007	/* DENALI_PHY_523_DATA */
+		0x00000000	/* DENALI_PHY_524_DATA */
+		0x00000000	/* DENALI_PHY_525_DATA */
+		0x04000408	/* DENALI_PHY_526_DATA */
+		0x00000408	/* DENALI_PHY_527_DATA */
+		0x00e4e400	/* DENALI_PHY_528_DATA */
+		0x00000000	/* DENALI_PHY_529_DATA */
+		0x00000000	/* DENALI_PHY_530_DATA */
+		0x00000000	/* DENALI_PHY_531_DATA */
+		0x00000000	/* DENALI_PHY_532_DATA */
+		0x00000000	/* DENALI_PHY_533_DATA */
+		0x00000000	/* DENALI_PHY_534_DATA */
+		0x00000000	/* DENALI_PHY_535_DATA */
+		0x00000000	/* DENALI_PHY_536_DATA */
+		0x00000000	/* DENALI_PHY_537_DATA */
+		0x00000000	/* DENALI_PHY_538_DATA */
+		0x00000000	/* DENALI_PHY_539_DATA */
+		0x00000000	/* DENALI_PHY_540_DATA */
+		0x00000000	/* DENALI_PHY_541_DATA */
+		0x00000000	/* DENALI_PHY_542_DATA */
+		0x00000000	/* DENALI_PHY_543_DATA */
+		0x00000000	/* DENALI_PHY_544_DATA */
+		0x00200000	/* DENALI_PHY_545_DATA */
+		0x00000000	/* DENALI_PHY_546_DATA */
+		0x00000000	/* DENALI_PHY_547_DATA */
+		0x00000000	/* DENALI_PHY_548_DATA */
+		0x00000000	/* DENALI_PHY_549_DATA */
+		0x00000000	/* DENALI_PHY_550_DATA */
+		0x00000000	/* DENALI_PHY_551_DATA */
+		0x02800280	/* DENALI_PHY_552_DATA */
+		0x02800280	/* DENALI_PHY_553_DATA */
+		0x02800280	/* DENALI_PHY_554_DATA */
+		0x02800280	/* DENALI_PHY_555_DATA */
+		0x00000280	/* DENALI_PHY_556_DATA */
+		0x00000000	/* DENALI_PHY_557_DATA */
+		0x00000000	/* DENALI_PHY_558_DATA */
+		0x00000000	/* DENALI_PHY_559_DATA */
+		0x00000000	/* DENALI_PHY_560_DATA */
+		0x00000000	/* DENALI_PHY_561_DATA */
+		0x00800080	/* DENALI_PHY_562_DATA */
+		0x00800080	/* DENALI_PHY_563_DATA */
+		0x00800080	/* DENALI_PHY_564_DATA */
+		0x00800080	/* DENALI_PHY_565_DATA */
+		0x00800080	/* DENALI_PHY_566_DATA */
+		0x00800080	/* DENALI_PHY_567_DATA */
+		0x00800080	/* DENALI_PHY_568_DATA */
+		0x00800080	/* DENALI_PHY_569_DATA */
+		0x00800080	/* DENALI_PHY_570_DATA */
+		0x000100da	/* DENALI_PHY_571_DATA */
+		0x00000200	/* DENALI_PHY_572_DATA */
+		0x00000000	/* DENALI_PHY_573_DATA */
+		0x00000000	/* DENALI_PHY_574_DATA */
+		0x00000002	/* DENALI_PHY_575_DATA */
+		0x51313152	/* DENALI_PHY_576_DATA */
+		0x80013130	/* DENALI_PHY_577_DATA */
+		0x02000080	/* DENALI_PHY_578_DATA */
+		0x00100001	/* DENALI_PHY_579_DATA */
+		0x0c064208	/* DENALI_PHY_580_DATA */
+		0x000f0c0f	/* DENALI_PHY_581_DATA */
+		0x01000140	/* DENALI_PHY_582_DATA */
+		0x0000000c	/* DENALI_PHY_583_DATA */
+		0x00000000	/* DENALI_PHY_584_DATA */
+		0x00000000	/* DENALI_PHY_585_DATA */
+		0x00000000	/* DENALI_PHY_586_DATA */
+		0x00000000	/* DENALI_PHY_587_DATA */
+		0x00000000	/* DENALI_PHY_588_DATA */
+		0x00000000	/* DENALI_PHY_589_DATA */
+		0x00000000	/* DENALI_PHY_590_DATA */
+		0x00000000	/* DENALI_PHY_591_DATA */
+		0x00000000	/* DENALI_PHY_592_DATA */
+		0x00000000	/* DENALI_PHY_593_DATA */
+		0x00000000	/* DENALI_PHY_594_DATA */
+		0x00000000	/* DENALI_PHY_595_DATA */
+		0x00000000	/* DENALI_PHY_596_DATA */
+		0x00000000	/* DENALI_PHY_597_DATA */
+		0x00000000	/* DENALI_PHY_598_DATA */
+		0x00000000	/* DENALI_PHY_599_DATA */
+		0x00000000	/* DENALI_PHY_600_DATA */
+		0x00000000	/* DENALI_PHY_601_DATA */
+		0x00000000	/* DENALI_PHY_602_DATA */
+		0x00000000	/* DENALI_PHY_603_DATA */
+		0x00000000	/* DENALI_PHY_604_DATA */
+		0x00000000	/* DENALI_PHY_605_DATA */
+		0x00000000	/* DENALI_PHY_606_DATA */
+		0x00000000	/* DENALI_PHY_607_DATA */
+		0x00000000	/* DENALI_PHY_608_DATA */
+		0x00000000	/* DENALI_PHY_609_DATA */
+		0x00000000	/* DENALI_PHY_610_DATA */
+		0x00000000	/* DENALI_PHY_611_DATA */
+		0x00000000	/* DENALI_PHY_612_DATA */
+		0x00000000	/* DENALI_PHY_613_DATA */
+		0x00000000	/* DENALI_PHY_614_DATA */
+		0x00000000	/* DENALI_PHY_615_DATA */
+		0x00000000	/* DENALI_PHY_616_DATA */
+		0x00000000	/* DENALI_PHY_617_DATA */
+		0x00000000	/* DENALI_PHY_618_DATA */
+		0x00000000	/* DENALI_PHY_619_DATA */
+		0x00000000	/* DENALI_PHY_620_DATA */
+		0x00000000	/* DENALI_PHY_621_DATA */
+		0x00000000	/* DENALI_PHY_622_DATA */
+		0x00000000	/* DENALI_PHY_623_DATA */
+		0x00000000	/* DENALI_PHY_624_DATA */
+		0x00000000	/* DENALI_PHY_625_DATA */
+		0x00000000	/* DENALI_PHY_626_DATA */
+		0x00000000	/* DENALI_PHY_627_DATA */
+		0x00000000	/* DENALI_PHY_628_DATA */
+		0x00000000	/* DENALI_PHY_629_DATA */
+		0x00000000	/* DENALI_PHY_630_DATA */
+		0x00000000	/* DENALI_PHY_631_DATA */
+		0x00000000	/* DENALI_PHY_632_DATA */
+		0x00000000	/* DENALI_PHY_633_DATA */
+		0x00000000	/* DENALI_PHY_634_DATA */
+		0x00000000	/* DENALI_PHY_635_DATA */
+		0x00000000	/* DENALI_PHY_636_DATA */
+		0x00000000	/* DENALI_PHY_637_DATA */
+		0x00000000	/* DENALI_PHY_638_DATA */
+		0x00000000	/* DENALI_PHY_639_DATA */
+		0x35174620	/* DENALI_PHY_640_DATA */
+		0x0004c008	/* DENALI_PHY_641_DATA */
+		0x000000da	/* DENALI_PHY_642_DATA */
+		0x00000000	/* DENALI_PHY_643_DATA */
+		0x00000000	/* DENALI_PHY_644_DATA */
+		0x00010000	/* DENALI_PHY_645_DATA */
+		0x01DDDD90	/* DENALI_PHY_646_DATA */
+		0x01DDDD90	/* DENALI_PHY_647_DATA */
+		0x01030000	/* DENALI_PHY_648_DATA */
+		0x01000000	/* DENALI_PHY_649_DATA */
+		0x00c00000	/* DENALI_PHY_650_DATA */
+		0x00000007	/* DENALI_PHY_651_DATA */
+		0x00000000	/* DENALI_PHY_652_DATA */
+		0x00000000	/* DENALI_PHY_653_DATA */
+		0x04000408	/* DENALI_PHY_654_DATA */
+		0x00000408	/* DENALI_PHY_655_DATA */
+		0x00e4e400	/* DENALI_PHY_656_DATA */
+		0x00000000	/* DENALI_PHY_657_DATA */
+		0x00000000	/* DENALI_PHY_658_DATA */
+		0x00000000	/* DENALI_PHY_659_DATA */
+		0x00000000	/* DENALI_PHY_660_DATA */
+		0x00000000	/* DENALI_PHY_661_DATA */
+		0x00000000	/* DENALI_PHY_662_DATA */
+		0x00000000	/* DENALI_PHY_663_DATA */
+		0x00000000	/* DENALI_PHY_664_DATA */
+		0x00000000	/* DENALI_PHY_665_DATA */
+		0x00000000	/* DENALI_PHY_666_DATA */
+		0x00000000	/* DENALI_PHY_667_DATA */
+		0x00000000	/* DENALI_PHY_668_DATA */
+		0x00000000	/* DENALI_PHY_669_DATA */
+		0x00000000	/* DENALI_PHY_670_DATA */
+		0x00000000	/* DENALI_PHY_671_DATA */
+		0x00000000	/* DENALI_PHY_672_DATA */
+		0x00200000	/* DENALI_PHY_673_DATA */
+		0x00000000	/* DENALI_PHY_674_DATA */
+		0x00000000	/* DENALI_PHY_675_DATA */
+		0x00000000	/* DENALI_PHY_676_DATA */
+		0x00000000	/* DENALI_PHY_677_DATA */
+		0x00000000	/* DENALI_PHY_678_DATA */
+		0x00000000	/* DENALI_PHY_679_DATA */
+		0x02800280	/* DENALI_PHY_680_DATA */
+		0x02800280	/* DENALI_PHY_681_DATA */
+		0x02800280	/* DENALI_PHY_682_DATA */
+		0x02800280	/* DENALI_PHY_683_DATA */
+		0x00000280	/* DENALI_PHY_684_DATA */
+		0x00000000	/* DENALI_PHY_685_DATA */
+		0x00000000	/* DENALI_PHY_686_DATA */
+		0x00000000	/* DENALI_PHY_687_DATA */
+		0x00000000	/* DENALI_PHY_688_DATA */
+		0x00000000	/* DENALI_PHY_689_DATA */
+		0x00800080	/* DENALI_PHY_690_DATA */
+		0x00800080	/* DENALI_PHY_691_DATA */
+		0x00800080	/* DENALI_PHY_692_DATA */
+		0x00800080	/* DENALI_PHY_693_DATA */
+		0x00800080	/* DENALI_PHY_694_DATA */
+		0x00800080	/* DENALI_PHY_695_DATA */
+		0x00800080	/* DENALI_PHY_696_DATA */
+		0x00800080	/* DENALI_PHY_697_DATA */
+		0x00800080	/* DENALI_PHY_698_DATA */
+		0x000100da	/* DENALI_PHY_699_DATA */
+		0x00000200	/* DENALI_PHY_700_DATA */
+		0x00000000	/* DENALI_PHY_701_DATA */
+		0x00000000	/* DENALI_PHY_702_DATA */
+		0x00000002	/* DENALI_PHY_703_DATA */
+		0x51313152	/* DENALI_PHY_704_DATA */
+		0x80013130	/* DENALI_PHY_705_DATA */
+		0x02000080	/* DENALI_PHY_706_DATA */
+		0x00100001	/* DENALI_PHY_707_DATA */
+		0x0c064208	/* DENALI_PHY_708_DATA */
+		0x000f0c0f	/* DENALI_PHY_709_DATA */
+		0x01000140	/* DENALI_PHY_710_DATA */
+		0x0000000c	/* DENALI_PHY_711_DATA */
+		0x00000000	/* DENALI_PHY_712_DATA */
+		0x00000000	/* DENALI_PHY_713_DATA */
+		0x00000000	/* DENALI_PHY_714_DATA */
+		0x00000000	/* DENALI_PHY_715_DATA */
+		0x00000000	/* DENALI_PHY_716_DATA */
+		0x00000000	/* DENALI_PHY_717_DATA */
+		0x00000000	/* DENALI_PHY_718_DATA */
+		0x00000000	/* DENALI_PHY_719_DATA */
+		0x00000000	/* DENALI_PHY_720_DATA */
+		0x00000000	/* DENALI_PHY_721_DATA */
+		0x00000000	/* DENALI_PHY_722_DATA */
+		0x00000000	/* DENALI_PHY_723_DATA */
+		0x00000000	/* DENALI_PHY_724_DATA */
+		0x00000000	/* DENALI_PHY_725_DATA */
+		0x00000000	/* DENALI_PHY_726_DATA */
+		0x00000000	/* DENALI_PHY_727_DATA */
+		0x00000000	/* DENALI_PHY_728_DATA */
+		0x00000000	/* DENALI_PHY_729_DATA */
+		0x00000000	/* DENALI_PHY_730_DATA */
+		0x00000000	/* DENALI_PHY_731_DATA */
+		0x00000000	/* DENALI_PHY_732_DATA */
+		0x00000000	/* DENALI_PHY_733_DATA */
+		0x00000000	/* DENALI_PHY_734_DATA */
+		0x00000000	/* DENALI_PHY_735_DATA */
+		0x00000000	/* DENALI_PHY_736_DATA */
+		0x00000000	/* DENALI_PHY_737_DATA */
+		0x00000000	/* DENALI_PHY_738_DATA */
+		0x00000000	/* DENALI_PHY_739_DATA */
+		0x00000000	/* DENALI_PHY_740_DATA */
+		0x00000000	/* DENALI_PHY_741_DATA */
+		0x00000000	/* DENALI_PHY_742_DATA */
+		0x00000000	/* DENALI_PHY_743_DATA */
+		0x00000000	/* DENALI_PHY_744_DATA */
+		0x00000000	/* DENALI_PHY_745_DATA */
+		0x00000000	/* DENALI_PHY_746_DATA */
+		0x00000000	/* DENALI_PHY_747_DATA */
+		0x00000000	/* DENALI_PHY_748_DATA */
+		0x00000000	/* DENALI_PHY_749_DATA */
+		0x00000000	/* DENALI_PHY_750_DATA */
+		0x00000000	/* DENALI_PHY_751_DATA */
+		0x00000000	/* DENALI_PHY_752_DATA */
+		0x00000000	/* DENALI_PHY_753_DATA */
+		0x00000000	/* DENALI_PHY_754_DATA */
+		0x00000000	/* DENALI_PHY_755_DATA */
+		0x00000000	/* DENALI_PHY_756_DATA */
+		0x00000000	/* DENALI_PHY_757_DATA */
+		0x00000000	/* DENALI_PHY_758_DATA */
+		0x00000000	/* DENALI_PHY_759_DATA */
+		0x00000000	/* DENALI_PHY_760_DATA */
+		0x00000000	/* DENALI_PHY_761_DATA */
+		0x00000000	/* DENALI_PHY_762_DATA */
+		0x00000000	/* DENALI_PHY_763_DATA */
+		0x00000000	/* DENALI_PHY_764_DATA */
+		0x00000000	/* DENALI_PHY_765_DATA */
+		0x00000000	/* DENALI_PHY_766_DATA */
+		0x00000000	/* DENALI_PHY_767_DATA */
+		0x15203476	/* DENALI_PHY_768_DATA */
+		0x0004c008	/* DENALI_PHY_769_DATA */
+		0x000000da	/* DENALI_PHY_770_DATA */
+		0x00000000	/* DENALI_PHY_771_DATA */
+		0x00000000	/* DENALI_PHY_772_DATA */
+		0x00010000	/* DENALI_PHY_773_DATA */
+		0x01DDDD90	/* DENALI_PHY_774_DATA */
+		0x01DDDD90	/* DENALI_PHY_775_DATA */
+		0x01030000	/* DENALI_PHY_776_DATA */
+		0x01000000	/* DENALI_PHY_777_DATA */
+		0x00c00000	/* DENALI_PHY_778_DATA */
+		0x00000007	/* DENALI_PHY_779_DATA */
+		0x00000000	/* DENALI_PHY_780_DATA */
+		0x00000000	/* DENALI_PHY_781_DATA */
+		0x04000408	/* DENALI_PHY_782_DATA */
+		0x00000408	/* DENALI_PHY_783_DATA */
+		0x00e4e400	/* DENALI_PHY_784_DATA */
+		0x00000000	/* DENALI_PHY_785_DATA */
+		0x00000000	/* DENALI_PHY_786_DATA */
+		0x00000000	/* DENALI_PHY_787_DATA */
+		0x00000000	/* DENALI_PHY_788_DATA */
+		0x00000000	/* DENALI_PHY_789_DATA */
+		0x00000000	/* DENALI_PHY_790_DATA */
+		0x00000000	/* DENALI_PHY_791_DATA */
+		0x00000000	/* DENALI_PHY_792_DATA */
+		0x00000000	/* DENALI_PHY_793_DATA */
+		0x00000000	/* DENALI_PHY_794_DATA */
+		0x00000000	/* DENALI_PHY_795_DATA */
+		0x00000000	/* DENALI_PHY_796_DATA */
+		0x00000000	/* DENALI_PHY_797_DATA */
+		0x00000000	/* DENALI_PHY_798_DATA */
+		0x00000000	/* DENALI_PHY_799_DATA */
+		0x00000000	/* DENALI_PHY_800_DATA */
+		0x00200000	/* DENALI_PHY_801_DATA */
+		0x00000000	/* DENALI_PHY_802_DATA */
+		0x00000000	/* DENALI_PHY_803_DATA */
+		0x00000000	/* DENALI_PHY_804_DATA */
+		0x00000000	/* DENALI_PHY_805_DATA */
+		0x00000000	/* DENALI_PHY_806_DATA */
+		0x00000000	/* DENALI_PHY_807_DATA */
+		0x02800280	/* DENALI_PHY_808_DATA */
+		0x02800280	/* DENALI_PHY_809_DATA */
+		0x02800280	/* DENALI_PHY_810_DATA */
+		0x02800280	/* DENALI_PHY_811_DATA */
+		0x00000280	/* DENALI_PHY_812_DATA */
+		0x00000000	/* DENALI_PHY_813_DATA */
+		0x00000000	/* DENALI_PHY_814_DATA */
+		0x00000000	/* DENALI_PHY_815_DATA */
+		0x00000000	/* DENALI_PHY_816_DATA */
+		0x00000000	/* DENALI_PHY_817_DATA */
+		0x00800080	/* DENALI_PHY_818_DATA */
+		0x00800080	/* DENALI_PHY_819_DATA */
+		0x00800080	/* DENALI_PHY_820_DATA */
+		0x00800080	/* DENALI_PHY_821_DATA */
+		0x00800080	/* DENALI_PHY_822_DATA */
+		0x00800080	/* DENALI_PHY_823_DATA */
+		0x00800080	/* DENALI_PHY_824_DATA */
+		0x00800080	/* DENALI_PHY_825_DATA */
+		0x00800080	/* DENALI_PHY_826_DATA */
+		0x000100da	/* DENALI_PHY_827_DATA */
+		0x00000200	/* DENALI_PHY_828_DATA */
+		0x00000000	/* DENALI_PHY_829_DATA */
+		0x00000000	/* DENALI_PHY_830_DATA */
+		0x00000002	/* DENALI_PHY_831_DATA */
+		0x51313152	/* DENALI_PHY_832_DATA */
+		0x80013130	/* DENALI_PHY_833_DATA */
+		0x02000080	/* DENALI_PHY_834_DATA */
+		0x00100001	/* DENALI_PHY_835_DATA */
+		0x0c064208	/* DENALI_PHY_836_DATA */
+		0x000f0c0f	/* DENALI_PHY_837_DATA */
+		0x01000140	/* DENALI_PHY_838_DATA */
+		0x0000000c	/* DENALI_PHY_839_DATA */
+		0x00000000	/* DENALI_PHY_840_DATA */
+		0x00000000	/* DENALI_PHY_841_DATA */
+		0x00000000	/* DENALI_PHY_842_DATA */
+		0x00000000	/* DENALI_PHY_843_DATA */
+		0x00000000	/* DENALI_PHY_844_DATA */
+		0x00000000	/* DENALI_PHY_845_DATA */
+		0x00000000	/* DENALI_PHY_846_DATA */
+		0x00000000	/* DENALI_PHY_847_DATA */
+		0x00000000	/* DENALI_PHY_848_DATA */
+		0x00000000	/* DENALI_PHY_849_DATA */
+		0x00000000	/* DENALI_PHY_850_DATA */
+		0x00000000	/* DENALI_PHY_851_DATA */
+		0x00000000	/* DENALI_PHY_852_DATA */
+		0x00000000	/* DENALI_PHY_853_DATA */
+		0x00000000	/* DENALI_PHY_854_DATA */
+		0x00000000	/* DENALI_PHY_855_DATA */
+		0x00000000	/* DENALI_PHY_856_DATA */
+		0x00000000	/* DENALI_PHY_857_DATA */
+		0x00000000	/* DENALI_PHY_858_DATA */
+		0x00000000	/* DENALI_PHY_859_DATA */
+		0x00000000	/* DENALI_PHY_860_DATA */
+		0x00000000	/* DENALI_PHY_861_DATA */
+		0x00000000	/* DENALI_PHY_862_DATA */
+		0x00000000	/* DENALI_PHY_863_DATA */
+		0x00000000	/* DENALI_PHY_864_DATA */
+		0x00000000	/* DENALI_PHY_865_DATA */
+		0x00000000	/* DENALI_PHY_866_DATA */
+		0x00000000	/* DENALI_PHY_867_DATA */
+		0x00000000	/* DENALI_PHY_868_DATA */
+		0x00000000	/* DENALI_PHY_869_DATA */
+		0x00000000	/* DENALI_PHY_870_DATA */
+		0x00000000	/* DENALI_PHY_871_DATA */
+		0x00000000	/* DENALI_PHY_872_DATA */
+		0x00000000	/* DENALI_PHY_873_DATA */
+		0x00000000	/* DENALI_PHY_874_DATA */
+		0x00000000	/* DENALI_PHY_875_DATA */
+		0x00000000	/* DENALI_PHY_876_DATA */
+		0x00000000	/* DENALI_PHY_877_DATA */
+		0x00000000	/* DENALI_PHY_878_DATA */
+		0x00000000	/* DENALI_PHY_879_DATA */
+		0x00000000	/* DENALI_PHY_880_DATA */
+		0x00000000	/* DENALI_PHY_881_DATA */
+		0x00000000	/* DENALI_PHY_882_DATA */
+		0x00000000	/* DENALI_PHY_883_DATA */
+		0x00000000	/* DENALI_PHY_884_DATA */
+		0x00000000	/* DENALI_PHY_885_DATA */
+		0x00000000	/* DENALI_PHY_886_DATA */
+		0x00000000	/* DENALI_PHY_887_DATA */
+		0x00000000	/* DENALI_PHY_888_DATA */
+		0x00000000	/* DENALI_PHY_889_DATA */
+		0x00000000	/* DENALI_PHY_890_DATA */
+		0x00000000	/* DENALI_PHY_891_DATA */
+		0x00000000	/* DENALI_PHY_892_DATA */
+		0x00000000	/* DENALI_PHY_893_DATA */
+		0x00000000	/* DENALI_PHY_894_DATA */
+		0x00000000	/* DENALI_PHY_895_DATA */
+		0x41753206	/* DENALI_PHY_896_DATA */
+		0x0004c008	/* DENALI_PHY_897_DATA */
+		0x000000da	/* DENALI_PHY_898_DATA */
+		0x00000000	/* DENALI_PHY_899_DATA */
+		0x00000000	/* DENALI_PHY_900_DATA */
+		0x00010000	/* DENALI_PHY_901_DATA */
+		0x01DDDD90	/* DENALI_PHY_902_DATA */
+		0x01DDDD90	/* DENALI_PHY_903_DATA */
+		0x01030000	/* DENALI_PHY_904_DATA */
+		0x01000000	/* DENALI_PHY_905_DATA */
+		0x00c00000	/* DENALI_PHY_906_DATA */
+		0x00000007	/* DENALI_PHY_907_DATA */
+		0x00000000	/* DENALI_PHY_908_DATA */
+		0x00000000	/* DENALI_PHY_909_DATA */
+		0x04000408	/* DENALI_PHY_910_DATA */
+		0x00000408	/* DENALI_PHY_911_DATA */
+		0x00e4e400	/* DENALI_PHY_912_DATA */
+		0x00000000	/* DENALI_PHY_913_DATA */
+		0x00000000	/* DENALI_PHY_914_DATA */
+		0x00000000	/* DENALI_PHY_915_DATA */
+		0x00000000	/* DENALI_PHY_916_DATA */
+		0x00000000	/* DENALI_PHY_917_DATA */
+		0x00000000	/* DENALI_PHY_918_DATA */
+		0x00000000	/* DENALI_PHY_919_DATA */
+		0x00000000	/* DENALI_PHY_920_DATA */
+		0x00000000	/* DENALI_PHY_921_DATA */
+		0x00000000	/* DENALI_PHY_922_DATA */
+		0x00000000	/* DENALI_PHY_923_DATA */
+		0x00000000	/* DENALI_PHY_924_DATA */
+		0x00000000	/* DENALI_PHY_925_DATA */
+		0x00000000	/* DENALI_PHY_926_DATA */
+		0x00000000	/* DENALI_PHY_927_DATA */
+		0x00000000	/* DENALI_PHY_928_DATA */
+		0x00200000	/* DENALI_PHY_929_DATA */
+		0x00000000	/* DENALI_PHY_930_DATA */
+		0x00000000	/* DENALI_PHY_931_DATA */
+		0x00000000	/* DENALI_PHY_932_DATA */
+		0x00000000	/* DENALI_PHY_933_DATA */
+		0x00000000	/* DENALI_PHY_934_DATA */
+		0x00000000	/* DENALI_PHY_935_DATA */
+		0x02800280	/* DENALI_PHY_936_DATA */
+		0x02800280	/* DENALI_PHY_937_DATA */
+		0x02800280	/* DENALI_PHY_938_DATA */
+		0x02800280	/* DENALI_PHY_939_DATA */
+		0x00000280	/* DENALI_PHY_940_DATA */
+		0x00000000	/* DENALI_PHY_941_DATA */
+		0x00000000	/* DENALI_PHY_942_DATA */
+		0x00000000	/* DENALI_PHY_943_DATA */
+		0x00000000	/* DENALI_PHY_944_DATA */
+		0x00000000	/* DENALI_PHY_945_DATA */
+		0x00800080	/* DENALI_PHY_946_DATA */
+		0x00800080	/* DENALI_PHY_947_DATA */
+		0x00800080	/* DENALI_PHY_948_DATA */
+		0x00800080	/* DENALI_PHY_949_DATA */
+		0x00800080	/* DENALI_PHY_950_DATA */
+		0x00800080	/* DENALI_PHY_951_DATA */
+		0x00800080	/* DENALI_PHY_952_DATA */
+		0x00800080	/* DENALI_PHY_953_DATA */
+		0x00800080	/* DENALI_PHY_954_DATA */
+		0x000100da	/* DENALI_PHY_955_DATA */
+		0x00000200	/* DENALI_PHY_956_DATA */
+		0x00000000	/* DENALI_PHY_957_DATA */
+		0x00000000	/* DENALI_PHY_958_DATA */
+		0x00000002	/* DENALI_PHY_959_DATA */
+		0x51313152	/* DENALI_PHY_960_DATA */
+		0x80013130	/* DENALI_PHY_961_DATA */
+		0x02000080	/* DENALI_PHY_962_DATA */
+		0x00100001	/* DENALI_PHY_963_DATA */
+		0x0c064208	/* DENALI_PHY_964_DATA */
+		0x000f0c0f	/* DENALI_PHY_965_DATA */
+		0x01000140	/* DENALI_PHY_966_DATA */
+		0x0000000c	/* DENALI_PHY_967_DATA */
+		0x00000000	/* DENALI_PHY_968_DATA */
+		0x00000000	/* DENALI_PHY_969_DATA */
+		0x00000000	/* DENALI_PHY_970_DATA */
+		0x00000000	/* DENALI_PHY_971_DATA */
+		0x00000000	/* DENALI_PHY_972_DATA */
+		0x00000000	/* DENALI_PHY_973_DATA */
+		0x00000000	/* DENALI_PHY_974_DATA */
+		0x00000000	/* DENALI_PHY_975_DATA */
+		0x00000000	/* DENALI_PHY_976_DATA */
+		0x00000000	/* DENALI_PHY_977_DATA */
+		0x00000000	/* DENALI_PHY_978_DATA */
+		0x00000000	/* DENALI_PHY_979_DATA */
+		0x00000000	/* DENALI_PHY_980_DATA */
+		0x00000000	/* DENALI_PHY_981_DATA */
+		0x00000000	/* DENALI_PHY_982_DATA */
+		0x00000000	/* DENALI_PHY_983_DATA */
+		0x00000000	/* DENALI_PHY_984_DATA */
+		0x00000000	/* DENALI_PHY_985_DATA */
+		0x00000000	/* DENALI_PHY_986_DATA */
+		0x00000000	/* DENALI_PHY_987_DATA */
+		0x00000000	/* DENALI_PHY_988_DATA */
+		0x00000000	/* DENALI_PHY_989_DATA */
+		0x00000000	/* DENALI_PHY_990_DATA */
+		0x00000000	/* DENALI_PHY_991_DATA */
+		0x00000000	/* DENALI_PHY_992_DATA */
+		0x00000000	/* DENALI_PHY_993_DATA */
+		0x00000000	/* DENALI_PHY_994_DATA */
+		0x00000000	/* DENALI_PHY_995_DATA */
+		0x00000000	/* DENALI_PHY_996_DATA */
+		0x00000000	/* DENALI_PHY_997_DATA */
+		0x00000000	/* DENALI_PHY_998_DATA */
+		0x00000000	/* DENALI_PHY_999_DATA */
+		0x00000000	/* DENALI_PHY_1000_DATA */
+		0x00000000	/* DENALI_PHY_1001_DATA */
+		0x00000000	/* DENALI_PHY_1002_DATA */
+		0x00000000	/* DENALI_PHY_1003_DATA */
+		0x00000000	/* DENALI_PHY_1004_DATA */
+		0x00000000	/* DENALI_PHY_1005_DATA */
+		0x00000000	/* DENALI_PHY_1006_DATA */
+		0x00000000	/* DENALI_PHY_1007_DATA */
+		0x00000000	/* DENALI_PHY_1008_DATA */
+		0x00000000	/* DENALI_PHY_1009_DATA */
+		0x00000000	/* DENALI_PHY_1010_DATA */
+		0x00000000	/* DENALI_PHY_1011_DATA */
+		0x00000000	/* DENALI_PHY_1012_DATA */
+		0x00000000	/* DENALI_PHY_1013_DATA */
+		0x00000000	/* DENALI_PHY_1014_DATA */
+		0x00000000	/* DENALI_PHY_1015_DATA */
+		0x00000000	/* DENALI_PHY_1016_DATA */
+		0x00000000	/* DENALI_PHY_1017_DATA */
+		0x00000000	/* DENALI_PHY_1018_DATA */
+		0x00000000	/* DENALI_PHY_1019_DATA */
+		0x00000000	/* DENALI_PHY_1020_DATA */
+		0x00000000	/* DENALI_PHY_1021_DATA */
+		0x00000000	/* DENALI_PHY_1022_DATA */
+		0x00000000	/* DENALI_PHY_1023_DATA */
+		0x36025174	/* DENALI_PHY_1024_DATA */
+		0x0004c008	/* DENALI_PHY_1025_DATA */
+		0x000000da	/* DENALI_PHY_1026_DATA */
+		0x00000000	/* DENALI_PHY_1027_DATA */
+		0x00000000	/* DENALI_PHY_1028_DATA */
+		0x00010000	/* DENALI_PHY_1029_DATA */
+		0x01DDDD90	/* DENALI_PHY_1030_DATA */
+		0x01DDDD90	/* DENALI_PHY_1031_DATA */
+		0x01030000	/* DENALI_PHY_1032_DATA */
+		0x01000000	/* DENALI_PHY_1033_DATA */
+		0x00c00000	/* DENALI_PHY_1034_DATA */
+		0x00000007	/* DENALI_PHY_1035_DATA */
+		0x00000000	/* DENALI_PHY_1036_DATA */
+		0x00000000	/* DENALI_PHY_1037_DATA */
+		0x04000408	/* DENALI_PHY_1038_DATA */
+		0x00000408	/* DENALI_PHY_1039_DATA */
+		0x00e4e400	/* DENALI_PHY_1040_DATA */
+		0x00000000	/* DENALI_PHY_1041_DATA */
+		0x00000000	/* DENALI_PHY_1042_DATA */
+		0x00000000	/* DENALI_PHY_1043_DATA */
+		0x00000000	/* DENALI_PHY_1044_DATA */
+		0x00000000	/* DENALI_PHY_1045_DATA */
+		0x00000000	/* DENALI_PHY_1046_DATA */
+		0x00000000	/* DENALI_PHY_1047_DATA */
+		0x00000000	/* DENALI_PHY_1048_DATA */
+		0x00000000	/* DENALI_PHY_1049_DATA */
+		0x00000000	/* DENALI_PHY_1050_DATA */
+		0x00000000	/* DENALI_PHY_1051_DATA */
+		0x00000000	/* DENALI_PHY_1052_DATA */
+		0x00000000	/* DENALI_PHY_1053_DATA */
+		0x00000000	/* DENALI_PHY_1054_DATA */
+		0x00000000	/* DENALI_PHY_1055_DATA */
+		0x00000000	/* DENALI_PHY_1056_DATA */
+		0x00200000	/* DENALI_PHY_1057_DATA */
+		0x00000000	/* DENALI_PHY_1058_DATA */
+		0x00000000	/* DENALI_PHY_1059_DATA */
+		0x00000000	/* DENALI_PHY_1060_DATA */
+		0x00000000	/* DENALI_PHY_1061_DATA */
+		0x00000000	/* DENALI_PHY_1062_DATA */
+		0x00000000	/* DENALI_PHY_1063_DATA */
+		0x02800280	/* DENALI_PHY_1064_DATA */
+		0x02800280	/* DENALI_PHY_1065_DATA */
+		0x02800280	/* DENALI_PHY_1066_DATA */
+		0x02800280	/* DENALI_PHY_1067_DATA */
+		0x00000280	/* DENALI_PHY_1068_DATA */
+		0x00000000	/* DENALI_PHY_1069_DATA */
+		0x00000000	/* DENALI_PHY_1070_DATA */
+		0x00000000	/* DENALI_PHY_1071_DATA */
+		0x00000000	/* DENALI_PHY_1072_DATA */
+		0x00000000	/* DENALI_PHY_1073_DATA */
+		0x00800080	/* DENALI_PHY_1074_DATA */
+		0x00800080	/* DENALI_PHY_1075_DATA */
+		0x00800080	/* DENALI_PHY_1076_DATA */
+		0x00800080	/* DENALI_PHY_1077_DATA */
+		0x00800080	/* DENALI_PHY_1078_DATA */
+		0x00800080	/* DENALI_PHY_1079_DATA */
+		0x00800080	/* DENALI_PHY_1080_DATA */
+		0x00800080	/* DENALI_PHY_1081_DATA */
+		0x00800080	/* DENALI_PHY_1082_DATA */
+		0x000100da	/* DENALI_PHY_1083_DATA */
+		0x00000200	/* DENALI_PHY_1084_DATA */
+		0x00000000	/* DENALI_PHY_1085_DATA */
+		0x00000000	/* DENALI_PHY_1086_DATA */
+		0x00000002	/* DENALI_PHY_1087_DATA */
+		0x51313152	/* DENALI_PHY_1088_DATA */
+		0x80013130	/* DENALI_PHY_1089_DATA */
+		0x02000080	/* DENALI_PHY_1090_DATA */
+		0x00100001	/* DENALI_PHY_1091_DATA */
+		0x0c064208	/* DENALI_PHY_1092_DATA */
+		0x000f0c0f	/* DENALI_PHY_1093_DATA */
+		0x01000140	/* DENALI_PHY_1094_DATA */
+		0x0000000c	/* DENALI_PHY_1095_DATA */
+		0x00000000	/* DENALI_PHY_1096_DATA */
+		0x00000000	/* DENALI_PHY_1097_DATA */
+		0x00000000	/* DENALI_PHY_1098_DATA */
+		0x00000000	/* DENALI_PHY_1099_DATA */
+		0x00000000	/* DENALI_PHY_1100_DATA */
+		0x00000000	/* DENALI_PHY_1101_DATA */
+		0x00000000	/* DENALI_PHY_1102_DATA */
+		0x00000000	/* DENALI_PHY_1103_DATA */
+		0x00000000	/* DENALI_PHY_1104_DATA */
+		0x00000000	/* DENALI_PHY_1105_DATA */
+		0x00000000	/* DENALI_PHY_1106_DATA */
+		0x00000000	/* DENALI_PHY_1107_DATA */
+		0x00000000	/* DENALI_PHY_1108_DATA */
+		0x00000000	/* DENALI_PHY_1109_DATA */
+		0x00000000	/* DENALI_PHY_1110_DATA */
+		0x00000000	/* DENALI_PHY_1111_DATA */
+		0x00000000	/* DENALI_PHY_1112_DATA */
+		0x00000000	/* DENALI_PHY_1113_DATA */
+		0x00000000	/* DENALI_PHY_1114_DATA */
+		0x00000000	/* DENALI_PHY_1115_DATA */
+		0x00000000	/* DENALI_PHY_1116_DATA */
+		0x00000000	/* DENALI_PHY_1117_DATA */
+		0x00000000	/* DENALI_PHY_1118_DATA */
+		0x00000000	/* DENALI_PHY_1119_DATA */
+		0x00000000	/* DENALI_PHY_1120_DATA */
+		0x00000000	/* DENALI_PHY_1121_DATA */
+		0x00000000	/* DENALI_PHY_1122_DATA */
+		0x00000000	/* DENALI_PHY_1123_DATA */
+		0x00000000	/* DENALI_PHY_1124_DATA */
+		0x00000000	/* DENALI_PHY_1125_DATA */
+		0x00000000	/* DENALI_PHY_1126_DATA */
+		0x00000000	/* DENALI_PHY_1127_DATA */
+		0x00000000	/* DENALI_PHY_1128_DATA */
+		0x00000000	/* DENALI_PHY_1129_DATA */
+		0x00000000	/* DENALI_PHY_1130_DATA */
+		0x00000000	/* DENALI_PHY_1131_DATA */
+		0x00000000	/* DENALI_PHY_1132_DATA */
+		0x00000000	/* DENALI_PHY_1133_DATA */
+		0x00000000	/* DENALI_PHY_1134_DATA */
+		0x00000000	/* DENALI_PHY_1135_DATA */
+		0x00000000	/* DENALI_PHY_1136_DATA */
+		0x00000000	/* DENALI_PHY_1137_DATA */
+		0x00000000	/* DENALI_PHY_1138_DATA */
+		0x00000000	/* DENALI_PHY_1139_DATA */
+		0x00000000	/* DENALI_PHY_1140_DATA */
+		0x00000000	/* DENALI_PHY_1141_DATA */
+		0x00000000	/* DENALI_PHY_1142_DATA */
+		0x00000000	/* DENALI_PHY_1143_DATA */
+		0x00000000	/* DENALI_PHY_1144_DATA */
+		0x00000000	/* DENALI_PHY_1145_DATA */
+		0x00000000	/* DENALI_PHY_1146_DATA */
+		0x00000000	/* DENALI_PHY_1147_DATA */
+		0x00000000	/* DENALI_PHY_1148_DATA */
+		0x00000000	/* DENALI_PHY_1149_DATA */
+		0x00000000	/* DENALI_PHY_1150_DATA */
+		0x00000000	/* DENALI_PHY_1151_DATA */
+		0x00000000	/* DENALI_PHY_1152_DATA */
+		0x00000000	/* DENALI_PHY_1153_DATA */
+		0x00050000	/* DENALI_PHY_1154_DATA */
+		0x00000000	/* DENALI_PHY_1155_DATA */
+		0x00000000	/* DENALI_PHY_1156_DATA */
+		0x00000000	/* DENALI_PHY_1157_DATA */
+		0x00000100	/* DENALI_PHY_1158_DATA */
+		0x00000000	/* DENALI_PHY_1159_DATA */
+		0x00000000	/* DENALI_PHY_1160_DATA */
+		0x00506401	/* DENALI_PHY_1161_DATA */
+		0x01221102	/* DENALI_PHY_1162_DATA */
+		0x00000122	/* DENALI_PHY_1163_DATA */
+		0x00000000	/* DENALI_PHY_1164_DATA */
+		0x000B1F00	/* DENALI_PHY_1165_DATA */
+		0x0B1F0B1F	/* DENALI_PHY_1166_DATA */
+		0x0B1F0B1B	/* DENALI_PHY_1167_DATA */
+		0x0B1F0B1F	/* DENALI_PHY_1168_DATA */
+		0x0B1F0B1F	/* DENALI_PHY_1169_DATA */
+		0x00000B00	/* DENALI_PHY_1170_DATA */
+		0x42080010	/* DENALI_PHY_1171_DATA */
+		0x01000100	/* DENALI_PHY_1172_DATA */
+		0x01000100	/* DENALI_PHY_1173_DATA */
+		0x01000100	/* DENALI_PHY_1174_DATA */
+		0x01000100	/* DENALI_PHY_1175_DATA */
+		0x00000000	/* DENALI_PHY_1176_DATA */
+		0x00000000	/* DENALI_PHY_1177_DATA */
+		0x00000000	/* DENALI_PHY_1178_DATA */
+		0x00000000	/* DENALI_PHY_1179_DATA */
+		0x00000000	/* DENALI_PHY_1180_DATA */
+		0x00000803	/* DENALI_PHY_1181_DATA */
+		0x223FFF00	/* DENALI_PHY_1182_DATA */
+		0x000008FF	/* DENALI_PHY_1183_DATA */
+		0x0000057F	/* DENALI_PHY_1184_DATA */
+		0x0000057F	/* DENALI_PHY_1185_DATA */
+		0x00037FFF	/* DENALI_PHY_1186_DATA */
+		0x00037FFF	/* DENALI_PHY_1187_DATA */
+		0x00004410	/* DENALI_PHY_1188_DATA */
+		0x00004410	/* DENALI_PHY_1189_DATA */
+		0x00004410	/* DENALI_PHY_1190_DATA */
+		0x00004410	/* DENALI_PHY_1191_DATA */
+		0x00004410	/* DENALI_PHY_1192_DATA */
+		0x00037FFF	/* DENALI_PHY_1193_DATA */
+		0x00037FFF	/* DENALI_PHY_1194_DATA */
+		0x00000000	/* DENALI_PHY_1195_DATA */
+		0x00000000	/* DENALI_PHY_1196_DATA */
+		0x00000000	/* DENALI_PHY_1197_DATA */
+		0x04000000	/* DENALI_PHY_1198_DATA */
+		0x00000000	/* DENALI_PHY_1199_DATA */
+		0x00000000	/* DENALI_PHY_1200_DATA */
+		0x00000108	/* DENALI_PHY_1201_DATA */
+		0x00000000	/* DENALI_PHY_1202_DATA */
+		0x00000000	/* DENALI_PHY_1203_DATA */
+		0x00000000	/* DENALI_PHY_1204_DATA */
+		0x00000001	/* DENALI_PHY_1205_DATA */
+		0x00000000	/* DENALI_PHY_1206_DATA */
+		0x00000000	/* DENALI_PHY_1207_DATA */
+		0x00000000	/* DENALI_PHY_1208_DATA */
+		0x00000000	/* DENALI_PHY_1209_DATA */
+		0x00000000	/* DENALI_PHY_1210_DATA */
+		0x00000000	/* DENALI_PHY_1211_DATA */
+		0x00020100	/* DENALI_PHY_1212_DATA */
+		0x00000000	/* DENALI_PHY_1213_DATA */
+		0x00000000	/* DENALI_PHY_1214_DATA */
+	>;
+};
diff --git a/roms/u-boot/arch/riscv/dts/fu740-c000-u-boot.dtsi b/roms/u-boot/arch/riscv/dts/fu740-c000-u-boot.dtsi
new file mode 100644
index 000000000..a5d0688b0
--- /dev/null
+++ b/roms/u-boot/arch/riscv/dts/fu740-c000-u-boot.dtsi
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * (C) Copyright 2020-2021 SiFive, Inc
+ */
+
+#include <dt-bindings/reset/sifive-fu740-prci.h>
+
+/ {
+	cpus {
+		assigned-clocks = <&prci PRCI_CLK_COREPLL>;
+		assigned-clock-rates = <1200000000>;
+		u-boot,dm-spl;
+		cpu0: cpu@0 {
+			clocks = <&prci PRCI_CLK_COREPLL>;
+			u-boot,dm-spl;
+			status = "okay";
+			cpu0_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+		cpu1: cpu@1 {
+			clocks = <&prci PRCI_CLK_COREPLL>;
+			u-boot,dm-spl;
+			cpu1_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+		cpu2: cpu@2 {
+			clocks = <&prci PRCI_CLK_COREPLL>;
+			u-boot,dm-spl;
+			cpu2_intc: interrupt-controller {
+				 u-boot,dm-spl;
+			};
+		};
+		cpu3: cpu@3 {
+			clocks = <&prci PRCI_CLK_COREPLL>;
+			u-boot,dm-spl;
+			cpu3_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+		cpu4: cpu@4 {
+			clocks = <&prci PRCI_CLK_COREPLL>;
+			u-boot,dm-spl;
+			cpu4_intc: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+	};
+
+	soc {
+		u-boot,dm-spl;
+		clint: clint@2000000 {
+			compatible = "riscv,clint0";
+			interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
+					       &cpu1_intc 3 &cpu1_intc 7
+					       &cpu2_intc 3 &cpu2_intc 7
+					       &cpu3_intc 3 &cpu3_intc 7
+					       &cpu4_intc 3 &cpu4_intc 7>;
+			reg = <0x0 0x2000000 0x0 0x10000>;
+			u-boot,dm-spl;
+		};
+		prci: clock-controller@10000000 {
+			#reset-cells = <1>;
+			resets = <&prci PRCI_RST_DDR_CTRL_N>,
+				 <&prci PRCI_RST_DDR_AXI_N>,
+				 <&prci PRCI_RST_DDR_AHB_N>,
+				 <&prci PRCI_RST_DDR_PHY_N>,
+				 <&prci PRCI_RST_GEMGXL_N>,
+				 <&prci PRCI_RST_CLTX_N>;
+			reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb",
+					"ddr_phy", "gemgxl_reset", "cltx_reset";
+		};
+		dmc: dmc@100b0000 {
+			compatible = "sifive,fu740-c000-ddr";
+			reg = <0x0 0x100b0000 0x0 0x0800
+			       0x0 0x100b2000 0x0 0x2000
+			       0x0 0x100b8000 0x0 0x1000>;
+			clocks = <&prci PRCI_CLK_DDRPLL>;
+			clock-frequency = <933333324>;
+			u-boot,dm-spl;
+		};
+	};
+};
+
+&prci {
+	u-boot,dm-spl;
+};
+
+&uart0 {
+	u-boot,dm-spl;
+};
+
+&spi0 {
+	u-boot,dm-spl;
+};
+
+&eth0 {
+	assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
+	assigned-clock-rates = <125125000>;
+};
+
+&ccache {
+	status = "okay";
+};
diff --git a/roms/u-boot/arch/riscv/dts/fu740-c000.dtsi b/roms/u-boot/arch/riscv/dts/fu740-c000.dtsi
new file mode 100644
index 000000000..649efe400
--- /dev/null
+++ b/roms/u-boot/arch/riscv/dts/fu740-c000.dtsi
@@ -0,0 +1,329 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2021 SiFive, Inc */
+
+/dts-v1/;
+
+#include <dt-bindings/clock/sifive-fu740-prci.h>
+#include <dt-bindings/reset/sifive-fu740-prci.h>
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	compatible = "sifive,fu740-c000", "sifive,fu740";
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		ethernet0 = &eth0;
+	};
+
+	chosen {
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cpu0: cpu@0 {
+			compatible = "sifive,bullet0", "riscv";
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <16384>;
+			next-level-cache = <&ccache>;
+			reg = <0x0>;
+			riscv,isa = "rv64imac";
+			status = "disabled";
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		cpu1: cpu@1 {
+			compatible = "sifive,bullet0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <40>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <40>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&ccache>;
+			reg = <0x1>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+			cpu1_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		cpu2: cpu@2 {
+			compatible = "sifive,bullet0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <40>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <40>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&ccache>;
+			reg = <0x2>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+			cpu2_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		cpu3: cpu@3 {
+			compatible = "sifive,bullet0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <40>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <40>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&ccache>;
+			reg = <0x3>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+			cpu3_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		cpu4: cpu@4 {
+			compatible = "sifive,bullet0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <40>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <40>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&ccache>;
+			reg = <0x4>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+			cpu4_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "sifive,fu740-c000", "sifive,fu740", "simple-bus";
+		ranges;
+		plic0: interrupt-controller@c000000 {
+			#interrupt-cells = <1>;
+			compatible = "sifive,plic-1.0.0";
+			reg = <0x0 0xc000000 0x0 0x4000000>;
+			riscv,ndev = <69>;
+			interrupt-controller;
+			interrupts-extended = <
+				&cpu0_intc 0xffffffff
+				&cpu1_intc 0xffffffff &cpu1_intc 9
+				&cpu2_intc 0xffffffff &cpu2_intc 9
+				&cpu3_intc 0xffffffff &cpu3_intc 9
+				&cpu4_intc 0xffffffff &cpu4_intc 9>;
+		};
+		prci: clock-controller@10000000 {
+			compatible = "sifive,fu740-c000-prci";
+			reg = <0x0 0x10000000 0x0 0x1000>;
+			clocks = <&hfclk>, <&rtcclk>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+		uart0: serial@10010000 {
+			compatible = "sifive,fu740-c000-uart", "sifive,uart0";
+			reg = <0x0 0x10010000 0x0 0x1000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <39>;
+			clocks = <&prci PRCI_CLK_PCLK>;
+			status = "disabled";
+		};
+		uart1: serial@10011000 {
+			compatible = "sifive,fu740-c000-uart", "sifive,uart0";
+			reg = <0x0 0x10011000 0x0 0x1000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <40>;
+			clocks = <&prci PRCI_CLK_PCLK>;
+			status = "disabled";
+		};
+		i2c0: i2c@10030000 {
+			compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
+			reg = <0x0 0x10030000 0x0 0x1000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <52>;
+			clocks = <&prci PRCI_CLK_PCLK>;
+			reg-shift = <2>;
+			reg-io-width = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i2c1: i2c@10031000 {
+			compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
+			reg = <0x0 0x10031000 0x0 0x1000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <53>;
+			clocks = <&prci PRCI_CLK_PCLK>;
+			reg-shift = <2>;
+			reg-io-width = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		qspi0: spi@10040000 {
+			compatible = "sifive,fu740-c000-spi", "sifive,spi0";
+			reg = <0x0 0x10040000 0x0 0x1000
+			       0x0 0x20000000 0x0 0x10000000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <41>;
+			clocks = <&prci PRCI_CLK_PCLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		qspi1: spi@10041000 {
+			compatible = "sifive,fu740-c000-spi", "sifive,spi0";
+			reg = <0x0 0x10041000 0x0 0x1000
+			       0x0 0x30000000 0x0 0x10000000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <42>;
+			clocks = <&prci PRCI_CLK_PCLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		spi0: spi@10050000 {
+			compatible = "sifive,fu740-c000-spi", "sifive,spi0";
+			reg = <0x0 0x10050000 0x0 0x1000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <43>;
+			clocks = <&prci PRCI_CLK_PCLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		eth0: ethernet@10090000 {
+			compatible = "sifive,fu540-c000-gem";
+			interrupt-parent = <&plic0>;
+			interrupts = <55>;
+			reg = <0x0 0x10090000 0x0 0x2000
+			       0x0 0x100a0000 0x0 0x1000>;
+			local-mac-address = [00 00 00 00 00 00];
+			clock-names = "pclk", "hclk";
+			clocks = <&prci PRCI_CLK_GEMGXLPLL>,
+				 <&prci PRCI_CLK_GEMGXLPLL>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		pwm0: pwm@10020000 {
+			compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
+			reg = <0x0 0x10020000 0x0 0x1000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <44 45 46 47>;
+			clocks = <&prci PRCI_CLK_PCLK>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+		pwm1: pwm@10021000 {
+			compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
+			reg = <0x0 0x10021000 0x0 0x1000>;
+			interrupt-parent = <&plic0>;
+			interrupts = <48 49 50 51>;
+			clocks = <&prci PRCI_CLK_PCLK>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+		ccache: cache-controller@2010000 {
+			compatible = "sifive,fu740-c000-ccache", "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <2048>;
+			cache-size = <2097152>;
+			cache-unified;
+			interrupt-parent = <&plic0>;
+			interrupts = <19 21 22 20>;
+			reg = <0x0 0x2010000 0x0 0x1000>;
+		};
+		gpio: gpio@10060000 {
+			compatible = "sifive,fu740-c000-gpio", "sifive,gpio0";
+			interrupt-parent = <&plic0>;
+			interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
+				     <30>, <31>, <32>, <33>, <34>, <35>, <36>,
+				     <37>, <38>;
+			reg = <0x0 0x10060000 0x0 0x1000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&prci PRCI_CLK_PCLK>;
+			status = "disabled";
+		};
+		pcie@e00000000 {
+			#address-cells = <3>;
+			#interrupt-cells = <1>;
+			#num-lanes = <8>;
+			#size-cells = <2>;
+			compatible = "sifive,fu740-pcie";
+			reg = <0xe 0x00000000 0x1 0x0
+			       0xd 0xf0000000 0x0 0x10000000
+			       0x0 0x100d0000 0x0 0x1000>;
+			reg-names = "dbi", "config", "mgmt";
+			device_type = "pci";
+			dma-coherent;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000  0x0 0x60080000  0x0 0x60080000 0x0 0x10000
+				  0x82000000  0x0 0x60090000  0x0 0x60090000 0x0 0xff70000
+				  0x82000000  0x0 0x70000000  0x0 0x70000000 0x0 0x1000000
+				  0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>;
+			num-lanes = <0x8>;
+			interrupts = <56 57 58 59 60 61 62 63 64>;
+			interrupt-names = "msi", "inta", "intb", "intc", "intd";
+			interrupt-parent = <&plic0>;
+			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+			interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
+					<0x0 0x0 0x0 0x2 &plic0 58>,
+					<0x0 0x0 0x0 0x3 &plic0 59>,
+					<0x0 0x0 0x0 0x4 &plic0 60>;
+			pwren-gpios = <&gpio 5 0>;
+			reset-gpios = <&gpio 8 0>;
+			clocks = <&prci PRCI_CLK_PCIEAUX>;
+			clock-names = "pcieaux";
+			resets = <&prci PRCI_RST_PCIE_POWER_UP_N>;
+			reset-names = "rst_n";
+
+			status = "okay";
+		};
+	};
+};
diff --git a/roms/u-boot/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi b/roms/u-boot/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
new file mode 100644
index 000000000..fc3dfd195
--- /dev/null
+++ b/roms/u-boot/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
@@ -0,0 +1,1489 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * (C) Copyright 2020-2021 SiFive, Inc
+ */
+
+&dmc {
+	sifive,ddr-params = <
+		0x00000a00	/* DENALI_CTL_00_DATA */
+		0x00000000	/* DENALI_CTL_01_DATA */
+		0x00000000	/* DENALI_CTL_02_DATA */
+		0x00000000	/* DENALI_CTL_03_DATA */
+		0x00000000	/* DENALI_CTL_04_DATA */
+		0x00000000	/* DENALI_CTL_05_DATA */
+		0x0000000a	/* DENALI_CTL_06_DATA */
+		0x0002d362	/* DENALI_CTL_07_DATA */
+		0x00071073	/* DENALI_CTL_08_DATA */
+		0x0a1c0255	/* DENALI_CTL_09_DATA */
+		0x1c1c0400	/* DENALI_CTL_10_DATA */
+		0x0404c90b	/* DENALI_CTL_11_DATA */
+		0x2b050405	/* DENALI_CTL_12_DATA */
+		0x0d0c081e	/* DENALI_CTL_13_DATA */
+		0x08090914	/* DENALI_CTL_14_DATA */
+		0x00fde718	/* DENALI_CTL_15_DATA */
+		0x00180a05	/* DENALI_CTL_16_DATA */
+		0x008b130d	/* DENALI_CTL_17_DATA */
+		0x01000118	/* DENALI_CTL_18_DATA */
+		0x0d032001	/* DENALI_CTL_19_DATA */
+		0x00000000	/* DENALI_CTL_20_DATA */
+		0x00000101	/* DENALI_CTL_21_DATA */
+		0x00000000	/* DENALI_CTL_22_DATA */
+		0x0a000000	/* DENALI_CTL_23_DATA */
+		0x00000000	/* DENALI_CTL_24_DATA */
+		0x01450100	/* DENALI_CTL_25_DATA */
+		0x00001c36	/* DENALI_CTL_26_DATA */
+		0x00000005	/* DENALI_CTL_27_DATA */
+		0x00170006	/* DENALI_CTL_28_DATA */
+		0x014e0400	/* DENALI_CTL_29_DATA */
+		0x03010000	/* DENALI_CTL_30_DATA */
+		0x000a0e00	/* DENALI_CTL_31_DATA */
+		0x04030200	/* DENALI_CTL_32_DATA */
+		0x0000031f	/* DENALI_CTL_33_DATA */
+		0x00070004	/* DENALI_CTL_34_DATA */
+		0x00000000	/* DENALI_CTL_35_DATA */
+		0x00000000	/* DENALI_CTL_36_DATA */
+		0x00000000	/* DENALI_CTL_37_DATA */
+		0x00000000	/* DENALI_CTL_38_DATA */
+		0x00000000	/* DENALI_CTL_39_DATA */
+		0x00000000	/* DENALI_CTL_40_DATA */
+		0x00000000	/* DENALI_CTL_41_DATA */
+		0x00000000	/* DENALI_CTL_42_DATA */
+		0x00000000	/* DENALI_CTL_43_DATA */
+		0x00000000	/* DENALI_CTL_44_DATA */
+		0x00000000	/* DENALI_CTL_45_DATA */
+		0x00000000	/* DENALI_CTL_46_DATA */
+		0x00000000	/* DENALI_CTL_47_DATA */
+		0x00000000	/* DENALI_CTL_48_DATA */
+		0x00000000	/* DENALI_CTL_49_DATA */
+		0x00000000	/* DENALI_CTL_50_DATA */
+		0x00000000	/* DENALI_CTL_51_DATA */
+		0x00000000	/* DENALI_CTL_52_DATA */
+		0x00000000	/* DENALI_CTL_53_DATA */
+		0x00000000	/* DENALI_CTL_54_DATA */
+		0x00000000	/* DENALI_CTL_55_DATA */
+		0x00000000	/* DENALI_CTL_56_DATA */
+		0x00000000	/* DENALI_CTL_57_DATA */
+		0x00000000	/* DENALI_CTL_58_DATA */
+		0x00000000	/* DENALI_CTL_59_DATA */
+		0x00000424	/* DENALI_CTL_60_DATA */
+		0x00000201	/* DENALI_CTL_61_DATA */
+		0x00001008	/* DENALI_CTL_62_DATA */
+		0x00000000	/* DENALI_CTL_63_DATA */
+		0x00000200	/* DENALI_CTL_64_DATA */
+		0x00000800	/* DENALI_CTL_65_DATA */
+		0x00000481	/* DENALI_CTL_66_DATA */
+		0x00000400	/* DENALI_CTL_67_DATA */
+		0x00000424	/* DENALI_CTL_68_DATA */
+		0x00000201	/* DENALI_CTL_69_DATA */
+		0x00001008	/* DENALI_CTL_70_DATA */
+		0x00000000	/* DENALI_CTL_71_DATA */
+		0x00000200	/* DENALI_CTL_72_DATA */
+		0x00000800	/* DENALI_CTL_73_DATA */
+		0x00000481	/* DENALI_CTL_74_DATA */
+		0x00000400	/* DENALI_CTL_75_DATA */
+		0x01010000	/* DENALI_CTL_76_DATA */
+		0x00000000	/* DENALI_CTL_77_DATA */
+		0x00000000	/* DENALI_CTL_78_DATA */
+		0x00000000	/* DENALI_CTL_79_DATA */
+		0x00000000	/* DENALI_CTL_80_DATA */
+		0x00000000	/* DENALI_CTL_81_DATA */
+		0x00000000	/* DENALI_CTL_82_DATA */
+		0x00000000	/* DENALI_CTL_83_DATA */
+		0x00000000	/* DENALI_CTL_84_DATA */
+		0x00000000	/* DENALI_CTL_85_DATA */
+		0x00000000	/* DENALI_CTL_86_DATA */
+		0x00000000	/* DENALI_CTL_87_DATA */
+		0x00000000	/* DENALI_CTL_88_DATA */
+		0x00000000	/* DENALI_CTL_89_DATA */
+		0x00000000	/* DENALI_CTL_90_DATA */
+		0x00000000	/* DENALI_CTL_91_DATA */
+		0x00000000	/* DENALI_CTL_92_DATA */
+		0x00000000	/* DENALI_CTL_93_DATA */
+		0x00000000	/* DENALI_CTL_94_DATA */
+		0x00000000	/* DENALI_CTL_95_DATA */
+		0x00000000	/* DENALI_CTL_96_DATA */
+		0x00000000	/* DENALI_CTL_97_DATA */
+		0x00000000	/* DENALI_CTL_98_DATA */
+		0x00000000	/* DENALI_CTL_99_DATA */
+		0x00000000	/* DENALI_CTL_100_DATA */
+		0x00000000	/* DENALI_CTL_101_DATA */
+		0x00000000	/* DENALI_CTL_102_DATA */
+		0x00000000	/* DENALI_CTL_103_DATA */
+		0x00000000	/* DENALI_CTL_104_DATA */
+		0x00000003	/* DENALI_CTL_105_DATA */
+		0x00000000	/* DENALI_CTL_106_DATA */
+		0x00000000	/* DENALI_CTL_107_DATA */
+		0x00000000	/* DENALI_CTL_108_DATA */
+		0x00000000	/* DENALI_CTL_109_DATA */
+		0x01000000	/* DENALI_CTL_110_DATA */
+		0x00040000	/* DENALI_CTL_111_DATA */
+		0x00800200	/* DENALI_CTL_112_DATA */
+		0x00000200	/* DENALI_CTL_113_DATA */
+		0x00000040	/* DENALI_CTL_114_DATA */
+		0x01000100	/* DENALI_CTL_115_DATA */
+		0x0a000002	/* DENALI_CTL_116_DATA */
+		0x0101ffff	/* DENALI_CTL_117_DATA */
+		0x01010101	/* DENALI_CTL_118_DATA */
+		0x01010101	/* DENALI_CTL_119_DATA */
+		0x0000010b	/* DENALI_CTL_120_DATA */
+		0x00000c03	/* DENALI_CTL_121_DATA */
+		0x00000000	/* DENALI_CTL_122_DATA */
+		0x00000000	/* DENALI_CTL_123_DATA */
+		0x00000000	/* DENALI_CTL_124_DATA */
+		0x00000000	/* DENALI_CTL_125_DATA */
+		0x00030300	/* DENALI_CTL_126_DATA */
+		0x00000000	/* DENALI_CTL_127_DATA */
+		0x00010101	/* DENALI_CTL_128_DATA */
+		0x00000000	/* DENALI_CTL_129_DATA */
+		0x00000000	/* DENALI_CTL_130_DATA */
+		0x00000000	/* DENALI_CTL_131_DATA */
+		0x00000000	/* DENALI_CTL_132_DATA */
+		0x00000000	/* DENALI_CTL_133_DATA */
+		0x00000000	/* DENALI_CTL_134_DATA */
+		0x00000000	/* DENALI_CTL_135_DATA */
+		0x00000000	/* DENALI_CTL_136_DATA */
+		0x00000000	/* DENALI_CTL_137_DATA */
+		0x00000000	/* DENALI_CTL_138_DATA */
+		0x00000000	/* DENALI_CTL_139_DATA */
+		0x00000000	/* DENALI_CTL_140_DATA */
+		0x00000000	/* DENALI_CTL_141_DATA */
+		0x00000000	/* DENALI_CTL_142_DATA */
+		0x00000000	/* DENALI_CTL_143_DATA */
+		0x00000000	/* DENALI_CTL_144_DATA */
+		0x00000000	/* DENALI_CTL_145_DATA */
+		0x00000000	/* DENALI_CTL_146_DATA */
+		0x00000000	/* DENALI_CTL_147_DATA */
+		0x00000000	/* DENALI_CTL_148_DATA */
+		0x00000000	/* DENALI_CTL_149_DATA */
+		0x00000000	/* DENALI_CTL_150_DATA */
+		0x00000000	/* DENALI_CTL_151_DATA */
+		0x00000000	/* DENALI_CTL_152_DATA */
+		0x00000000	/* DENALI_CTL_153_DATA */
+		0x00000000	/* DENALI_CTL_154_DATA */
+		0x00000000	/* DENALI_CTL_155_DATA */
+		0x00000000	/* DENALI_CTL_156_DATA */
+		0x00000000	/* DENALI_CTL_157_DATA */
+		0x00000000	/* DENALI_CTL_158_DATA */
+		0x00000000	/* DENALI_CTL_159_DATA */
+		0x00000000	/* DENALI_CTL_160_DATA */
+		0x02010102	/* DENALI_CTL_161_DATA */
+		0x0108070d	/* DENALI_CTL_162_DATA */
+		0x05050300	/* DENALI_CTL_163_DATA */
+		0x04000503	/* DENALI_CTL_164_DATA */
+		0x00000000	/* DENALI_CTL_165_DATA */
+		0x00000000	/* DENALI_CTL_166_DATA */
+		0x00000000	/* DENALI_CTL_167_DATA */
+		0x00000000	/* DENALI_CTL_168_DATA */
+		0x280d0000	/* DENALI_CTL_169_DATA */
+		0x01000000	/* DENALI_CTL_170_DATA */
+		0x00000000	/* DENALI_CTL_171_DATA */
+		0x00030001	/* DENALI_CTL_172_DATA */
+		0x00000000	/* DENALI_CTL_173_DATA */
+		0x00000000	/* DENALI_CTL_174_DATA */
+		0x00000000	/* DENALI_CTL_175_DATA */
+		0x00000000	/* DENALI_CTL_176_DATA */
+		0x00000000	/* DENALI_CTL_177_DATA */
+		0x00000000	/* DENALI_CTL_178_DATA */
+		0x00000000	/* DENALI_CTL_179_DATA */
+		0x00000000	/* DENALI_CTL_180_DATA */
+		0x01000000	/* DENALI_CTL_181_DATA */
+		0x00000001	/* DENALI_CTL_182_DATA */
+		0x00000100	/* DENALI_CTL_183_DATA */
+		0x00010303	/* DENALI_CTL_184_DATA */
+		0x67676701	/* DENALI_CTL_185_DATA */
+		0x67676767	/* DENALI_CTL_186_DATA */
+		0x67676767	/* DENALI_CTL_187_DATA */
+		0x67676767	/* DENALI_CTL_188_DATA */
+		0x67676767	/* DENALI_CTL_189_DATA */
+		0x67676767	/* DENALI_CTL_190_DATA */
+		0x67676767	/* DENALI_CTL_191_DATA */
+		0x67676767	/* DENALI_CTL_192_DATA */
+		0x67676767	/* DENALI_CTL_193_DATA */
+		0x01000067	/* DENALI_CTL_194_DATA */
+		0x00000001	/* DENALI_CTL_195_DATA */
+		0x00000101	/* DENALI_CTL_196_DATA */
+		0x00000000	/* DENALI_CTL_197_DATA */
+		0x00000000	/* DENALI_CTL_198_DATA */
+		0x00000000	/* DENALI_CTL_199_DATA */
+		0x00000000	/* DENALI_CTL_200_DATA */
+		0x00000000	/* DENALI_CTL_201_DATA */
+		0x00000000	/* DENALI_CTL_202_DATA */
+		0x00000000	/* DENALI_CTL_203_DATA */
+		0x00000000	/* DENALI_CTL_204_DATA */
+		0x00000000	/* DENALI_CTL_205_DATA */
+		0x00000000	/* DENALI_CTL_206_DATA */
+		0x00000000	/* DENALI_CTL_207_DATA */
+		0x00000001	/* DENALI_CTL_208_DATA */
+		0x00000000	/* DENALI_CTL_209_DATA */
+		0x007fffff	/* DENALI_CTL_210_DATA */
+		0x00000000	/* DENALI_CTL_211_DATA */
+		0x007fffff	/* DENALI_CTL_212_DATA */
+		0x00000000	/* DENALI_CTL_213_DATA */
+		0x007fffff	/* DENALI_CTL_214_DATA */
+		0x00000000	/* DENALI_CTL_215_DATA */
+		0x007fffff	/* DENALI_CTL_216_DATA */
+		0x00000000	/* DENALI_CTL_217_DATA */
+		0x007fffff	/* DENALI_CTL_218_DATA */
+		0x00000000	/* DENALI_CTL_219_DATA */
+		0x007fffff	/* DENALI_CTL_220_DATA */
+		0x00000000	/* DENALI_CTL_221_DATA */
+		0x007fffff	/* DENALI_CTL_222_DATA */
+		0x00000000	/* DENALI_CTL_223_DATA */
+		0x037fffff	/* DENALI_CTL_224_DATA */
+		0xffffffff	/* DENALI_CTL_225_DATA */
+		0x000f000f	/* DENALI_CTL_226_DATA */
+		0x00ffff03	/* DENALI_CTL_227_DATA */
+		0x000fffff	/* DENALI_CTL_228_DATA */
+		0x0003000f	/* DENALI_CTL_229_DATA */
+		0xffffffff	/* DENALI_CTL_230_DATA */
+		0x000f000f	/* DENALI_CTL_231_DATA */
+		0x00ffff03	/* DENALI_CTL_232_DATA */
+		0x000fffff	/* DENALI_CTL_233_DATA */
+		0x0003000f	/* DENALI_CTL_234_DATA */
+		0xffffffff	/* DENALI_CTL_235_DATA */
+		0x000f000f	/* DENALI_CTL_236_DATA */
+		0x00ffff03	/* DENALI_CTL_237_DATA */
+		0x000fffff	/* DENALI_CTL_238_DATA */
+		0x0003000f	/* DENALI_CTL_239_DATA */
+		0xffffffff	/* DENALI_CTL_240_DATA */
+		0x000f000f	/* DENALI_CTL_241_DATA */
+		0x00ffff03	/* DENALI_CTL_242_DATA */
+		0x000fffff	/* DENALI_CTL_243_DATA */
+		0x6407000f	/* DENALI_CTL_244_DATA */
+		0x01640001	/* DENALI_CTL_245_DATA */
+		0x00000000	/* DENALI_CTL_246_DATA */
+		0x00000000	/* DENALI_CTL_247_DATA */
+		0x00001800	/* DENALI_CTL_248_DATA */
+		0x00386c05	/* DENALI_CTL_249_DATA */
+		0x02000200	/* DENALI_CTL_250_DATA */
+		0x02000200	/* DENALI_CTL_251_DATA */
+		0x0000386c	/* DENALI_CTL_252_DATA */
+		0x00023438	/* DENALI_CTL_253_DATA */
+		0x02020d0f	/* DENALI_CTL_254_DATA */
+		0x00140303	/* DENALI_CTL_255_DATA */
+		0x00000000	/* DENALI_CTL_256_DATA */
+		0x00000000	/* DENALI_CTL_257_DATA */
+		0x00001403	/* DENALI_CTL_258_DATA */
+		0x00000000	/* DENALI_CTL_259_DATA */
+		0x00000000	/* DENALI_CTL_260_DATA */
+		0x00000000	/* DENALI_CTL_261_DATA */
+		0x00000000	/* DENALI_CTL_262_DATA */
+		0x0c010000	/* DENALI_CTL_263_DATA */
+		0x00000008	/* DENALI_CTL_264_DATA */
+		0x01375642	/* DENALI_PHY_00_DATA */
+		0x0004c008	/* DENALI_PHY_01_DATA */
+		0x000000da	/* DENALI_PHY_02_DATA */
+		0x00000000	/* DENALI_PHY_03_DATA */
+		0x00000000	/* DENALI_PHY_04_DATA */
+		0x00010000	/* DENALI_PHY_05_DATA */
+		0x01DDDD90	/* DENALI_PHY_06_DATA */
+		0x01DDDD90	/* DENALI_PHY_07_DATA */
+		0x01030001	/* DENALI_PHY_08_DATA */
+		0x01000000	/* DENALI_PHY_09_DATA */
+		0x00c00000	/* DENALI_PHY_10_DATA */
+		0x00000007	/* DENALI_PHY_11_DATA */
+		0x00000000	/* DENALI_PHY_12_DATA */
+		0x00000000	/* DENALI_PHY_13_DATA */
+		0x04000408	/* DENALI_PHY_14_DATA */
+		0x00000408	/* DENALI_PHY_15_DATA */
+		0x00e4e400	/* DENALI_PHY_16_DATA */
+		0x00000000	/* DENALI_PHY_17_DATA */
+		0x00000000	/* DENALI_PHY_18_DATA */
+		0x00000000	/* DENALI_PHY_19_DATA */
+		0x00000000	/* DENALI_PHY_20_DATA */
+		0x00000000	/* DENALI_PHY_21_DATA */
+		0x00000000	/* DENALI_PHY_22_DATA */
+		0x00000000	/* DENALI_PHY_23_DATA */
+		0x00000000	/* DENALI_PHY_24_DATA */
+		0x00000000	/* DENALI_PHY_25_DATA */
+		0x00000000	/* DENALI_PHY_26_DATA */
+		0x00000000	/* DENALI_PHY_27_DATA */
+		0x00000000	/* DENALI_PHY_28_DATA */
+		0x00000000	/* DENALI_PHY_29_DATA */
+		0x00000000	/* DENALI_PHY_30_DATA */
+		0x00000000	/* DENALI_PHY_31_DATA */
+		0x00000000	/* DENALI_PHY_32_DATA */
+		0x00200000	/* DENALI_PHY_33_DATA */
+		0x00000000	/* DENALI_PHY_34_DATA */
+		0x00000000	/* DENALI_PHY_35_DATA */
+		0x00000000	/* DENALI_PHY_36_DATA */
+		0x00000000	/* DENALI_PHY_37_DATA */
+		0x00000000	/* DENALI_PHY_38_DATA */
+		0x00000000	/* DENALI_PHY_39_DATA */
+		0x02800280	/* DENALI_PHY_40_DATA */
+		0x02800280	/* DENALI_PHY_41_DATA */
+		0x02800280	/* DENALI_PHY_42_DATA */
+		0x02800280	/* DENALI_PHY_43_DATA */
+		0x00000280	/* DENALI_PHY_44_DATA */
+		0x00000000	/* DENALI_PHY_45_DATA */
+		0x00000000	/* DENALI_PHY_46_DATA */
+		0x00000000	/* DENALI_PHY_47_DATA */
+		0x00000000	/* DENALI_PHY_48_DATA */
+		0x00000000	/* DENALI_PHY_49_DATA */
+		0x00800080	/* DENALI_PHY_50_DATA */
+		0x00800080	/* DENALI_PHY_51_DATA */
+		0x00800080	/* DENALI_PHY_52_DATA */
+		0x00800080	/* DENALI_PHY_53_DATA */
+		0x00800080	/* DENALI_PHY_54_DATA */
+		0x00800080	/* DENALI_PHY_55_DATA */
+		0x00800080	/* DENALI_PHY_56_DATA */
+		0x00800080	/* DENALI_PHY_57_DATA */
+		0x00800080	/* DENALI_PHY_58_DATA */
+		0x000100da	/* DENALI_PHY_59_DATA */
+		0x01ff0010	/* DENALI_PHY_60_DATA */
+		0x00000000	/* DENALI_PHY_61_DATA */
+		0x00000000	/* DENALI_PHY_62_DATA */
+		0x00000002	/* DENALI_PHY_63_DATA */
+		0x51313152	/* DENALI_PHY_64_DATA */
+		0x80013130	/* DENALI_PHY_65_DATA */
+		0x02000080	/* DENALI_PHY_66_DATA */
+		0x00100001	/* DENALI_PHY_67_DATA */
+		0x0c064208	/* DENALI_PHY_68_DATA */
+		0x000f0c0f	/* DENALI_PHY_69_DATA */
+		0x01000140	/* DENALI_PHY_70_DATA */
+		0x0000000c	/* DENALI_PHY_71_DATA */
+		0x00000000	/* DENALI_PHY_72_DATA */
+		0x00000000	/* DENALI_PHY_73_DATA */
+		0x00000000	/* DENALI_PHY_74_DATA */
+		0x00000000	/* DENALI_PHY_75_DATA */
+		0x00000000	/* DENALI_PHY_76_DATA */
+		0x00000000	/* DENALI_PHY_77_DATA */
+		0x00000000	/* DENALI_PHY_78_DATA */
+		0x00000000	/* DENALI_PHY_79_DATA */
+		0x00000000	/* DENALI_PHY_80_DATA */
+		0x00000000	/* DENALI_PHY_81_DATA */
+		0x00000000	/* DENALI_PHY_82_DATA */
+		0x00000000	/* DENALI_PHY_83_DATA */
+		0x00000000	/* DENALI_PHY_84_DATA */
+		0x00000000	/* DENALI_PHY_85_DATA */
+		0x00000000	/* DENALI_PHY_86_DATA */
+		0x00000000	/* DENALI_PHY_87_DATA */
+		0x00000000	/* DENALI_PHY_88_DATA */
+		0x00000000	/* DENALI_PHY_89_DATA */
+		0x00000000	/* DENALI_PHY_90_DATA */
+		0x00000000	/* DENALI_PHY_91_DATA */
+		0x00000000	/* DENALI_PHY_92_DATA */
+		0x00000000	/* DENALI_PHY_93_DATA */
+		0x00000000	/* DENALI_PHY_94_DATA */
+		0x00000000	/* DENALI_PHY_95_DATA */
+		0x00000000	/* DENALI_PHY_96_DATA */
+		0x00000000	/* DENALI_PHY_97_DATA */
+		0x00000000	/* DENALI_PHY_98_DATA */
+		0x00000000	/* DENALI_PHY_99_DATA */
+		0x00000000	/* DENALI_PHY_100_DATA */
+		0x00000000	/* DENALI_PHY_101_DATA */
+		0x00000000	/* DENALI_PHY_102_DATA */
+		0x00000000	/* DENALI_PHY_103_DATA */
+		0x00000000	/* DENALI_PHY_104_DATA */
+		0x00000000	/* DENALI_PHY_105_DATA */
+		0x00000000	/* DENALI_PHY_106_DATA */
+		0x00000000	/* DENALI_PHY_107_DATA */
+		0x00000000	/* DENALI_PHY_108_DATA */
+		0x00000000	/* DENALI_PHY_109_DATA */
+		0x00000000	/* DENALI_PHY_110_DATA */
+		0x00000000	/* DENALI_PHY_111_DATA */
+		0x00000000	/* DENALI_PHY_112_DATA */
+		0x00000000	/* DENALI_PHY_113_DATA */
+		0x00000000	/* DENALI_PHY_114_DATA */
+		0x00000000	/* DENALI_PHY_115_DATA */
+		0x00000000	/* DENALI_PHY_116_DATA */
+		0x00000000	/* DENALI_PHY_117_DATA */
+		0x00000000	/* DENALI_PHY_118_DATA */
+		0x00000000	/* DENALI_PHY_119_DATA */
+		0x00000000	/* DENALI_PHY_120_DATA */
+		0x00000000	/* DENALI_PHY_121_DATA */
+		0x00000000	/* DENALI_PHY_122_DATA */
+		0x00000000	/* DENALI_PHY_123_DATA */
+		0x00000000	/* DENALI_PHY_124_DATA */
+		0x00000000	/* DENALI_PHY_125_DATA */
+		0x00000000	/* DENALI_PHY_126_DATA */
+		0x00000000	/* DENALI_PHY_127_DATA */
+		0x40263571	/* DENALI_PHY_128_DATA */
+		0x0004c008	/* DENALI_PHY_129_DATA */
+		0x000000da	/* DENALI_PHY_130_DATA */
+		0x00000000	/* DENALI_PHY_131_DATA */
+		0x00000000	/* DENALI_PHY_132_DATA */
+		0x00010000	/* DENALI_PHY_133_DATA */
+		0x01DDDD90	/* DENALI_PHY_134_DATA */
+		0x01DDDD90	/* DENALI_PHY_135_DATA */
+		0x01030001	/* DENALI_PHY_136_DATA */
+		0x01000000	/* DENALI_PHY_137_DATA */
+		0x00c00000	/* DENALI_PHY_138_DATA */
+		0x00000007	/* DENALI_PHY_139_DATA */
+		0x00000000	/* DENALI_PHY_140_DATA */
+		0x00000000	/* DENALI_PHY_141_DATA */
+		0x04000408	/* DENALI_PHY_142_DATA */
+		0x00000408	/* DENALI_PHY_143_DATA */
+		0x00e4e400	/* DENALI_PHY_144_DATA */
+		0x00000000	/* DENALI_PHY_145_DATA */
+		0x00000000	/* DENALI_PHY_146_DATA */
+		0x00000000	/* DENALI_PHY_147_DATA */
+		0x00000000	/* DENALI_PHY_148_DATA */
+		0x00000000	/* DENALI_PHY_149_DATA */
+		0x00000000	/* DENALI_PHY_150_DATA */
+		0x00000000	/* DENALI_PHY_151_DATA */
+		0x00000000	/* DENALI_PHY_152_DATA */
+		0x00000000	/* DENALI_PHY_153_DATA */
+		0x00000000	/* DENALI_PHY_154_DATA */
+		0x00000000	/* DENALI_PHY_155_DATA */
+		0x00000000	/* DENALI_PHY_156_DATA */
+		0x00000000	/* DENALI_PHY_157_DATA */
+		0x00000000	/* DENALI_PHY_158_DATA */
+		0x00000000	/* DENALI_PHY_159_DATA */
+		0x00000000	/* DENALI_PHY_160_DATA */
+		0x00200000	/* DENALI_PHY_161_DATA */
+		0x00000000	/* DENALI_PHY_162_DATA */
+		0x00000000	/* DENALI_PHY_163_DATA */
+		0x00000000	/* DENALI_PHY_164_DATA */
+		0x00000000	/* DENALI_PHY_165_DATA */
+		0x00000000	/* DENALI_PHY_166_DATA */
+		0x00000000	/* DENALI_PHY_167_DATA */
+		0x02800280	/* DENALI_PHY_168_DATA */
+		0x02800280	/* DENALI_PHY_169_DATA */
+		0x02800280	/* DENALI_PHY_170_DATA */
+		0x02800280	/* DENALI_PHY_171_DATA */
+		0x00000280	/* DENALI_PHY_172_DATA */
+		0x00000000	/* DENALI_PHY_173_DATA */
+		0x00000000	/* DENALI_PHY_174_DATA */
+		0x00000000	/* DENALI_PHY_175_DATA */
+		0x00000000	/* DENALI_PHY_176_DATA */
+		0x00000000	/* DENALI_PHY_177_DATA */
+		0x00800080	/* DENALI_PHY_178_DATA */
+		0x00800080	/* DENALI_PHY_179_DATA */
+		0x00800080	/* DENALI_PHY_180_DATA */
+		0x00800080	/* DENALI_PHY_181_DATA */
+		0x00800080	/* DENALI_PHY_182_DATA */
+		0x00800080	/* DENALI_PHY_183_DATA */
+		0x00800080	/* DENALI_PHY_184_DATA */
+		0x00800080	/* DENALI_PHY_185_DATA */
+		0x00800080	/* DENALI_PHY_186_DATA */
+		0x000100da	/* DENALI_PHY_187_DATA */
+		0x01ff0010	/* DENALI_PHY_188_DATA */
+		0x00000000	/* DENALI_PHY_189_DATA */
+		0x00000000	/* DENALI_PHY_190_DATA */
+		0x00000002	/* DENALI_PHY_191_DATA */
+		0x51313152	/* DENALI_PHY_192_DATA */
+		0x80013130	/* DENALI_PHY_193_DATA */
+		0x02000080	/* DENALI_PHY_194_DATA */
+		0x00100001	/* DENALI_PHY_195_DATA */
+		0x0c064208	/* DENALI_PHY_196_DATA */
+		0x000f0c0f	/* DENALI_PHY_197_DATA */
+		0x01000140	/* DENALI_PHY_198_DATA */
+		0x0000000c	/* DENALI_PHY_199_DATA */
+		0x00000000	/* DENALI_PHY_200_DATA */
+		0x00000000	/* DENALI_PHY_201_DATA */
+		0x00000000	/* DENALI_PHY_202_DATA */
+		0x00000000	/* DENALI_PHY_203_DATA */
+		0x00000000	/* DENALI_PHY_204_DATA */
+		0x00000000	/* DENALI_PHY_205_DATA */
+		0x00000000	/* DENALI_PHY_206_DATA */
+		0x00000000	/* DENALI_PHY_207_DATA */
+		0x00000000	/* DENALI_PHY_208_DATA */
+		0x00000000	/* DENALI_PHY_209_DATA */
+		0x00000000	/* DENALI_PHY_210_DATA */
+		0x00000000	/* DENALI_PHY_211_DATA */
+		0x00000000	/* DENALI_PHY_212_DATA */
+		0x00000000	/* DENALI_PHY_213_DATA */
+		0x00000000	/* DENALI_PHY_214_DATA */
+		0x00000000	/* DENALI_PHY_215_DATA */
+		0x00000000	/* DENALI_PHY_216_DATA */
+		0x00000000	/* DENALI_PHY_217_DATA */
+		0x00000000	/* DENALI_PHY_218_DATA */
+		0x00000000	/* DENALI_PHY_219_DATA */
+		0x00000000	/* DENALI_PHY_220_DATA */
+		0x00000000	/* DENALI_PHY_221_DATA */
+		0x00000000	/* DENALI_PHY_222_DATA */
+		0x00000000	/* DENALI_PHY_223_DATA */
+		0x00000000	/* DENALI_PHY_224_DATA */
+		0x00000000	/* DENALI_PHY_225_DATA */
+		0x00000000	/* DENALI_PHY_226_DATA */
+		0x00000000	/* DENALI_PHY_227_DATA */
+		0x00000000	/* DENALI_PHY_228_DATA */
+		0x00000000	/* DENALI_PHY_229_DATA */
+		0x00000000	/* DENALI_PHY_230_DATA */
+		0x00000000	/* DENALI_PHY_231_DATA */
+		0x00000000	/* DENALI_PHY_232_DATA */
+		0x00000000	/* DENALI_PHY_233_DATA */
+		0x00000000	/* DENALI_PHY_234_DATA */
+		0x00000000	/* DENALI_PHY_235_DATA */
+		0x00000000	/* DENALI_PHY_236_DATA */
+		0x00000000	/* DENALI_PHY_237_DATA */
+		0x00000000	/* DENALI_PHY_238_DATA */
+		0x00000000	/* DENALI_PHY_239_DATA */
+		0x00000000	/* DENALI_PHY_240_DATA */
+		0x00000000	/* DENALI_PHY_241_DATA */
+		0x00000000	/* DENALI_PHY_242_DATA */
+		0x00000000	/* DENALI_PHY_243_DATA */
+		0x00000000	/* DENALI_PHY_244_DATA */
+		0x00000000	/* DENALI_PHY_245_DATA */
+		0x00000000	/* DENALI_PHY_246_DATA */
+		0x00000000	/* DENALI_PHY_247_DATA */
+		0x00000000	/* DENALI_PHY_248_DATA */
+		0x00000000	/* DENALI_PHY_249_DATA */
+		0x00000000	/* DENALI_PHY_250_DATA */
+		0x00000000	/* DENALI_PHY_251_DATA */
+		0x00000000	/* DENALI_PHY_252_DATA */
+		0x00000000	/* DENALI_PHY_253_DATA */
+		0x00000000	/* DENALI_PHY_254_DATA */
+		0x00000000	/* DENALI_PHY_255_DATA */
+		0x46052371	/* DENALI_PHY_256_DATA */
+		0x0004c008	/* DENALI_PHY_257_DATA */
+		0x000000da	/* DENALI_PHY_258_DATA */
+		0x00000000	/* DENALI_PHY_259_DATA */
+		0x00000000	/* DENALI_PHY_260_DATA */
+		0x00010000	/* DENALI_PHY_261_DATA */
+		0x01DDDD90	/* DENALI_PHY_262_DATA */
+		0x01DDDD90	/* DENALI_PHY_263_DATA */
+		0x01030001	/* DENALI_PHY_264_DATA */
+		0x01000000	/* DENALI_PHY_265_DATA */
+		0x00c00000	/* DENALI_PHY_266_DATA */
+		0x00000007	/* DENALI_PHY_267_DATA */
+		0x00000000	/* DENALI_PHY_268_DATA */
+		0x00000000	/* DENALI_PHY_269_DATA */
+		0x04000408	/* DENALI_PHY_270_DATA */
+		0x00000408	/* DENALI_PHY_271_DATA */
+		0x00e4e400	/* DENALI_PHY_272_DATA */
+		0x00000000	/* DENALI_PHY_273_DATA */
+		0x00000000	/* DENALI_PHY_274_DATA */
+		0x00000000	/* DENALI_PHY_275_DATA */
+		0x00000000	/* DENALI_PHY_276_DATA */
+		0x00000000	/* DENALI_PHY_277_DATA */
+		0x00000000	/* DENALI_PHY_278_DATA */
+		0x00000000	/* DENALI_PHY_279_DATA */
+		0x00000000	/* DENALI_PHY_280_DATA */
+		0x00000000	/* DENALI_PHY_281_DATA */
+		0x00000000	/* DENALI_PHY_282_DATA */
+		0x00000000	/* DENALI_PHY_283_DATA */
+		0x00000000	/* DENALI_PHY_284_DATA */
+		0x00000000	/* DENALI_PHY_285_DATA */
+		0x00000000	/* DENALI_PHY_286_DATA */
+		0x00000000	/* DENALI_PHY_287_DATA */
+		0x00000000	/* DENALI_PHY_288_DATA */
+		0x00200000	/* DENALI_PHY_289_DATA */
+		0x00000000	/* DENALI_PHY_290_DATA */
+		0x00000000	/* DENALI_PHY_291_DATA */
+		0x00000000	/* DENALI_PHY_292_DATA */
+		0x00000000	/* DENALI_PHY_293_DATA */
+		0x00000000	/* DENALI_PHY_294_DATA */
+		0x00000000	/* DENALI_PHY_295_DATA */
+		0x02800280	/* DENALI_PHY_296_DATA */
+		0x02800280	/* DENALI_PHY_297_DATA */
+		0x02800280	/* DENALI_PHY_298_DATA */
+		0x02800280	/* DENALI_PHY_299_DATA */
+		0x00000280	/* DENALI_PHY_300_DATA */
+		0x00000000	/* DENALI_PHY_301_DATA */
+		0x00000000	/* DENALI_PHY_302_DATA */
+		0x00000000	/* DENALI_PHY_303_DATA */
+		0x00000000	/* DENALI_PHY_304_DATA */
+		0x00000000	/* DENALI_PHY_305_DATA */
+		0x00800080	/* DENALI_PHY_306_DATA */
+		0x00800080	/* DENALI_PHY_307_DATA */
+		0x00800080	/* DENALI_PHY_308_DATA */
+		0x00800080	/* DENALI_PHY_309_DATA */
+		0x00800080	/* DENALI_PHY_310_DATA */
+		0x00800080	/* DENALI_PHY_311_DATA */
+		0x00800080	/* DENALI_PHY_312_DATA */
+		0x00800080	/* DENALI_PHY_313_DATA */
+		0x00800080	/* DENALI_PHY_314_DATA */
+		0x000100da	/* DENALI_PHY_315_DATA */
+		0x01ff0010	/* DENALI_PHY_316_DATA */
+		0x00000000	/* DENALI_PHY_317_DATA */
+		0x00000000	/* DENALI_PHY_318_DATA */
+		0x00000002	/* DENALI_PHY_319_DATA */
+		0x51313152	/* DENALI_PHY_320_DATA */
+		0x80013130	/* DENALI_PHY_321_DATA */
+		0x02000080	/* DENALI_PHY_322_DATA */
+		0x00100001	/* DENALI_PHY_323_DATA */
+		0x0c064208	/* DENALI_PHY_324_DATA */
+		0x000f0c0f	/* DENALI_PHY_325_DATA */
+		0x01000140	/* DENALI_PHY_326_DATA */
+		0x0000000c	/* DENALI_PHY_327_DATA */
+		0x00000000	/* DENALI_PHY_328_DATA */
+		0x00000000	/* DENALI_PHY_329_DATA */
+		0x00000000	/* DENALI_PHY_330_DATA */
+		0x00000000	/* DENALI_PHY_331_DATA */
+		0x00000000	/* DENALI_PHY_332_DATA */
+		0x00000000	/* DENALI_PHY_333_DATA */
+		0x00000000	/* DENALI_PHY_334_DATA */
+		0x00000000	/* DENALI_PHY_335_DATA */
+		0x00000000	/* DENALI_PHY_336_DATA */
+		0x00000000	/* DENALI_PHY_337_DATA */
+		0x00000000	/* DENALI_PHY_338_DATA */
+		0x00000000	/* DENALI_PHY_339_DATA */
+		0x00000000	/* DENALI_PHY_340_DATA */
+		0x00000000	/* DENALI_PHY_341_DATA */
+		0x00000000	/* DENALI_PHY_342_DATA */
+		0x00000000	/* DENALI_PHY_343_DATA */
+		0x00000000	/* DENALI_PHY_344_DATA */
+		0x00000000	/* DENALI_PHY_345_DATA */
+		0x00000000	/* DENALI_PHY_346_DATA */
+		0x00000000	/* DENALI_PHY_347_DATA */
+		0x00000000	/* DENALI_PHY_348_DATA */
+		0x00000000	/* DENALI_PHY_349_DATA */
+		0x00000000	/* DENALI_PHY_350_DATA */
+		0x00000000	/* DENALI_PHY_351_DATA */
+		0x00000000	/* DENALI_PHY_352_DATA */
+		0x00000000	/* DENALI_PHY_353_DATA */
+		0x00000000	/* DENALI_PHY_354_DATA */
+		0x00000000	/* DENALI_PHY_355_DATA */
+		0x00000000	/* DENALI_PHY_356_DATA */
+		0x00000000	/* DENALI_PHY_357_DATA */
+		0x00000000	/* DENALI_PHY_358_DATA */
+		0x00000000	/* DENALI_PHY_359_DATA */
+		0x00000000	/* DENALI_PHY_360_DATA */
+		0x00000000	/* DENALI_PHY_361_DATA */
+		0x00000000	/* DENALI_PHY_362_DATA */
+		0x00000000	/* DENALI_PHY_363_DATA */
+		0x00000000	/* DENALI_PHY_364_DATA */
+		0x00000000	/* DENALI_PHY_365_DATA */
+		0x00000000	/* DENALI_PHY_366_DATA */
+		0x00000000	/* DENALI_PHY_367_DATA */
+		0x00000000	/* DENALI_PHY_368_DATA */
+		0x00000000	/* DENALI_PHY_369_DATA */
+		0x00000000	/* DENALI_PHY_370_DATA */
+		0x00000000	/* DENALI_PHY_371_DATA */
+		0x00000000	/* DENALI_PHY_372_DATA */
+		0x00000000	/* DENALI_PHY_373_DATA */
+		0x00000000	/* DENALI_PHY_374_DATA */
+		0x00000000	/* DENALI_PHY_375_DATA */
+		0x00000000	/* DENALI_PHY_376_DATA */
+		0x00000000	/* DENALI_PHY_377_DATA */
+		0x00000000	/* DENALI_PHY_378_DATA */
+		0x00000000	/* DENALI_PHY_379_DATA */
+		0x00000000	/* DENALI_PHY_380_DATA */
+		0x00000000	/* DENALI_PHY_381_DATA */
+		0x00000000	/* DENALI_PHY_382_DATA */
+		0x00000000	/* DENALI_PHY_383_DATA */
+		0x37651240	/* DENALI_PHY_384_DATA */
+		0x0004c008	/* DENALI_PHY_385_DATA */
+		0x000000da	/* DENALI_PHY_386_DATA */
+		0x00000000	/* DENALI_PHY_387_DATA */
+		0x00000000	/* DENALI_PHY_388_DATA */
+		0x00010000	/* DENALI_PHY_389_DATA */
+		0x01DDDD90	/* DENALI_PHY_390_DATA */
+		0x01DDDD90	/* DENALI_PHY_391_DATA */
+		0x01030001	/* DENALI_PHY_392_DATA */
+		0x01000000	/* DENALI_PHY_393_DATA */
+		0x00c00000	/* DENALI_PHY_394_DATA */
+		0x00000007	/* DENALI_PHY_395_DATA */
+		0x00000000	/* DENALI_PHY_396_DATA */
+		0x00000000	/* DENALI_PHY_397_DATA */
+		0x04000408	/* DENALI_PHY_398_DATA */
+		0x00000408	/* DENALI_PHY_399_DATA */
+		0x00e4e400	/* DENALI_PHY_400_DATA */
+		0x00000000	/* DENALI_PHY_401_DATA */
+		0x00000000	/* DENALI_PHY_402_DATA */
+		0x00000000	/* DENALI_PHY_403_DATA */
+		0x00000000	/* DENALI_PHY_404_DATA */
+		0x00000000	/* DENALI_PHY_405_DATA */
+		0x00000000	/* DENALI_PHY_406_DATA */
+		0x00000000	/* DENALI_PHY_407_DATA */
+		0x00000000	/* DENALI_PHY_408_DATA */
+		0x00000000	/* DENALI_PHY_409_DATA */
+		0x00000000	/* DENALI_PHY_410_DATA */
+		0x00000000	/* DENALI_PHY_411_DATA */
+		0x00000000	/* DENALI_PHY_412_DATA */
+		0x00000000	/* DENALI_PHY_413_DATA */
+		0x00000000	/* DENALI_PHY_414_DATA */
+		0x00000000	/* DENALI_PHY_415_DATA */
+		0x00000000	/* DENALI_PHY_416_DATA */
+		0x00200000	/* DENALI_PHY_417_DATA */
+		0x00000000	/* DENALI_PHY_418_DATA */
+		0x00000000	/* DENALI_PHY_419_DATA */
+		0x00000000	/* DENALI_PHY_420_DATA */
+		0x00000000	/* DENALI_PHY_421_DATA */
+		0x00000000	/* DENALI_PHY_422_DATA */
+		0x00000000	/* DENALI_PHY_423_DATA */
+		0x02800280	/* DENALI_PHY_424_DATA */
+		0x02800280	/* DENALI_PHY_425_DATA */
+		0x02800280	/* DENALI_PHY_426_DATA */
+		0x02800280	/* DENALI_PHY_427_DATA */
+		0x00000280	/* DENALI_PHY_428_DATA */
+		0x00000000	/* DENALI_PHY_429_DATA */
+		0x00000000	/* DENALI_PHY_430_DATA */
+		0x00000000	/* DENALI_PHY_431_DATA */
+		0x00000000	/* DENALI_PHY_432_DATA */
+		0x00000000	/* DENALI_PHY_433_DATA */
+		0x00800080	/* DENALI_PHY_434_DATA */
+		0x00800080	/* DENALI_PHY_435_DATA */
+		0x00800080	/* DENALI_PHY_436_DATA */
+		0x00800080	/* DENALI_PHY_437_DATA */
+		0x00800080	/* DENALI_PHY_438_DATA */
+		0x00800080	/* DENALI_PHY_439_DATA */
+		0x00800080	/* DENALI_PHY_440_DATA */
+		0x00800080	/* DENALI_PHY_441_DATA */
+		0x00800080	/* DENALI_PHY_442_DATA */
+		0x000100da	/* DENALI_PHY_443_DATA */
+		0x01ff0010	/* DENALI_PHY_444_DATA */
+		0x00000000	/* DENALI_PHY_445_DATA */
+		0x00000000	/* DENALI_PHY_446_DATA */
+		0x00000002	/* DENALI_PHY_447_DATA */
+		0x51313152	/* DENALI_PHY_448_DATA */
+		0x80013130	/* DENALI_PHY_449_DATA */
+		0x02000080	/* DENALI_PHY_450_DATA */
+		0x00100001	/* DENALI_PHY_451_DATA */
+		0x0c064208	/* DENALI_PHY_452_DATA */
+		0x000f0c0f	/* DENALI_PHY_453_DATA */
+		0x01000140	/* DENALI_PHY_454_DATA */
+		0x0000000c	/* DENALI_PHY_455_DATA */
+		0x00000000	/* DENALI_PHY_456_DATA */
+		0x00000000	/* DENALI_PHY_457_DATA */
+		0x00000000	/* DENALI_PHY_458_DATA */
+		0x00000000	/* DENALI_PHY_459_DATA */
+		0x00000000	/* DENALI_PHY_460_DATA */
+		0x00000000	/* DENALI_PHY_461_DATA */
+		0x00000000	/* DENALI_PHY_462_DATA */
+		0x00000000	/* DENALI_PHY_463_DATA */
+		0x00000000	/* DENALI_PHY_464_DATA */
+		0x00000000	/* DENALI_PHY_465_DATA */
+		0x00000000	/* DENALI_PHY_466_DATA */
+		0x00000000	/* DENALI_PHY_467_DATA */
+		0x00000000	/* DENALI_PHY_468_DATA */
+		0x00000000	/* DENALI_PHY_469_DATA */
+		0x00000000	/* DENALI_PHY_470_DATA */
+		0x00000000	/* DENALI_PHY_471_DATA */
+		0x00000000	/* DENALI_PHY_472_DATA */
+		0x00000000	/* DENALI_PHY_473_DATA */
+		0x00000000	/* DENALI_PHY_474_DATA */
+		0x00000000	/* DENALI_PHY_475_DATA */
+		0x00000000	/* DENALI_PHY_476_DATA */
+		0x00000000	/* DENALI_PHY_477_DATA */
+		0x00000000	/* DENALI_PHY_478_DATA */
+		0x00000000	/* DENALI_PHY_479_DATA */
+		0x00000000	/* DENALI_PHY_480_DATA */
+		0x00000000	/* DENALI_PHY_481_DATA */
+		0x00000000	/* DENALI_PHY_482_DATA */
+		0x00000000	/* DENALI_PHY_483_DATA */
+		0x00000000	/* DENALI_PHY_484_DATA */
+		0x00000000	/* DENALI_PHY_485_DATA */
+		0x00000000	/* DENALI_PHY_486_DATA */
+		0x00000000	/* DENALI_PHY_487_DATA */
+		0x00000000	/* DENALI_PHY_488_DATA */
+		0x00000000	/* DENALI_PHY_489_DATA */
+		0x00000000	/* DENALI_PHY_490_DATA */
+		0x00000000	/* DENALI_PHY_491_DATA */
+		0x00000000	/* DENALI_PHY_492_DATA */
+		0x00000000	/* DENALI_PHY_493_DATA */
+		0x00000000	/* DENALI_PHY_494_DATA */
+		0x00000000	/* DENALI_PHY_495_DATA */
+		0x00000000	/* DENALI_PHY_496_DATA */
+		0x00000000	/* DENALI_PHY_497_DATA */
+		0x00000000	/* DENALI_PHY_498_DATA */
+		0x00000000	/* DENALI_PHY_499_DATA */
+		0x00000000	/* DENALI_PHY_500_DATA */
+		0x00000000	/* DENALI_PHY_501_DATA */
+		0x00000000	/* DENALI_PHY_502_DATA */
+		0x00000000	/* DENALI_PHY_503_DATA */
+		0x00000000	/* DENALI_PHY_504_DATA */
+		0x00000000	/* DENALI_PHY_505_DATA */
+		0x00000000	/* DENALI_PHY_506_DATA */
+		0x00000000	/* DENALI_PHY_507_DATA */
+		0x00000000	/* DENALI_PHY_508_DATA */
+		0x00000000	/* DENALI_PHY_509_DATA */
+		0x00000000	/* DENALI_PHY_510_DATA */
+		0x00000000	/* DENALI_PHY_511_DATA */
+		0x34216750	/* DENALI_PHY_512_DATA */
+		0x0004c008	/* DENALI_PHY_513_DATA */
+		0x000000da	/* DENALI_PHY_514_DATA */
+		0x00000000	/* DENALI_PHY_515_DATA */
+		0x00000000	/* DENALI_PHY_516_DATA */
+		0x00010000	/* DENALI_PHY_517_DATA */
+		0x01DDDD90	/* DENALI_PHY_518_DATA */
+		0x01DDDD90	/* DENALI_PHY_519_DATA */
+		0x01030001	/* DENALI_PHY_520_DATA */
+		0x01000000	/* DENALI_PHY_521_DATA */
+		0x00c00000	/* DENALI_PHY_522_DATA */
+		0x00000007	/* DENALI_PHY_523_DATA */
+		0x00000000	/* DENALI_PHY_524_DATA */
+		0x00000000	/* DENALI_PHY_525_DATA */
+		0x04000408	/* DENALI_PHY_526_DATA */
+		0x00000408	/* DENALI_PHY_527_DATA */
+		0x00e4e400	/* DENALI_PHY_528_DATA */
+		0x00000000	/* DENALI_PHY_529_DATA */
+		0x00000000	/* DENALI_PHY_530_DATA */
+		0x00000000	/* DENALI_PHY_531_DATA */
+		0x00000000	/* DENALI_PHY_532_DATA */
+		0x00000000	/* DENALI_PHY_533_DATA */
+		0x00000000	/* DENALI_PHY_534_DATA */
+		0x00000000	/* DENALI_PHY_535_DATA */
+		0x00000000	/* DENALI_PHY_536_DATA */
+		0x00000000	/* DENALI_PHY_537_DATA */
+		0x00000000	/* DENALI_PHY_538_DATA */
+		0x00000000	/* DENALI_PHY_539_DATA */
+		0x00000000	/* DENALI_PHY_540_DATA */
+		0x00000000	/* DENALI_PHY_541_DATA */
+		0x00000000	/* DENALI_PHY_542_DATA */
+		0x00000000	/* DENALI_PHY_543_DATA */
+		0x00000000	/* DENALI_PHY_544_DATA */
+		0x00200000	/* DENALI_PHY_545_DATA */
+		0x00000000	/* DENALI_PHY_546_DATA */
+		0x00000000	/* DENALI_PHY_547_DATA */
+		0x00000000	/* DENALI_PHY_548_DATA */
+		0x00000000	/* DENALI_PHY_549_DATA */
+		0x00000000	/* DENALI_PHY_550_DATA */
+		0x00000000	/* DENALI_PHY_551_DATA */
+		0x02800280	/* DENALI_PHY_552_DATA */
+		0x02800280	/* DENALI_PHY_553_DATA */
+		0x02800280	/* DENALI_PHY_554_DATA */
+		0x02800280	/* DENALI_PHY_555_DATA */
+		0x00000280	/* DENALI_PHY_556_DATA */
+		0x00000000	/* DENALI_PHY_557_DATA */
+		0x00000000	/* DENALI_PHY_558_DATA */
+		0x00000000	/* DENALI_PHY_559_DATA */
+		0x00000000	/* DENALI_PHY_560_DATA */
+		0x00000000	/* DENALI_PHY_561_DATA */
+		0x00800080	/* DENALI_PHY_562_DATA */
+		0x00800080	/* DENALI_PHY_563_DATA */
+		0x00800080	/* DENALI_PHY_564_DATA */
+		0x00800080	/* DENALI_PHY_565_DATA */
+		0x00800080	/* DENALI_PHY_566_DATA */
+		0x00800080	/* DENALI_PHY_567_DATA */
+		0x00800080	/* DENALI_PHY_568_DATA */
+		0x00800080	/* DENALI_PHY_569_DATA */
+		0x00800080	/* DENALI_PHY_570_DATA */
+		0x000100da	/* DENALI_PHY_571_DATA */
+		0x01ff0010	/* DENALI_PHY_572_DATA */
+		0x00000000	/* DENALI_PHY_573_DATA */
+		0x00000000	/* DENALI_PHY_574_DATA */
+		0x00000002	/* DENALI_PHY_575_DATA */
+		0x51313152	/* DENALI_PHY_576_DATA */
+		0x80013130	/* DENALI_PHY_577_DATA */
+		0x02000080	/* DENALI_PHY_578_DATA */
+		0x00100001	/* DENALI_PHY_579_DATA */
+		0x0c064208	/* DENALI_PHY_580_DATA */
+		0x000f0c0f	/* DENALI_PHY_581_DATA */
+		0x01000140	/* DENALI_PHY_582_DATA */
+		0x0000000c	/* DENALI_PHY_583_DATA */
+		0x00000000	/* DENALI_PHY_584_DATA */
+		0x00000000	/* DENALI_PHY_585_DATA */
+		0x00000000	/* DENALI_PHY_586_DATA */
+		0x00000000	/* DENALI_PHY_587_DATA */
+		0x00000000	/* DENALI_PHY_588_DATA */
+		0x00000000	/* DENALI_PHY_589_DATA */
+		0x00000000	/* DENALI_PHY_590_DATA */
+		0x00000000	/* DENALI_PHY_591_DATA */
+		0x00000000	/* DENALI_PHY_592_DATA */
+		0x00000000	/* DENALI_PHY_593_DATA */
+		0x00000000	/* DENALI_PHY_594_DATA */
+		0x00000000	/* DENALI_PHY_595_DATA */
+		0x00000000	/* DENALI_PHY_596_DATA */
+		0x00000000	/* DENALI_PHY_597_DATA */
+		0x00000000	/* DENALI_PHY_598_DATA */
+		0x00000000	/* DENALI_PHY_599_DATA */
+		0x00000000	/* DENALI_PHY_600_DATA */
+		0x00000000	/* DENALI_PHY_601_DATA */
+		0x00000000	/* DENALI_PHY_602_DATA */
+		0x00000000	/* DENALI_PHY_603_DATA */
+		0x00000000	/* DENALI_PHY_604_DATA */
+		0x00000000	/* DENALI_PHY_605_DATA */
+		0x00000000	/* DENALI_PHY_606_DATA */
+		0x00000000	/* DENALI_PHY_607_DATA */
+		0x00000000	/* DENALI_PHY_608_DATA */
+		0x00000000	/* DENALI_PHY_609_DATA */
+		0x00000000	/* DENALI_PHY_610_DATA */
+		0x00000000	/* DENALI_PHY_611_DATA */
+		0x00000000	/* DENALI_PHY_612_DATA */
+		0x00000000	/* DENALI_PHY_613_DATA */
+		0x00000000	/* DENALI_PHY_614_DATA */
+		0x00000000	/* DENALI_PHY_615_DATA */
+		0x00000000	/* DENALI_PHY_616_DATA */
+		0x00000000	/* DENALI_PHY_617_DATA */
+		0x00000000	/* DENALI_PHY_618_DATA */
+		0x00000000	/* DENALI_PHY_619_DATA */
+		0x00000000	/* DENALI_PHY_620_DATA */
+		0x00000000	/* DENALI_PHY_621_DATA */
+		0x00000000	/* DENALI_PHY_622_DATA */
+		0x00000000	/* DENALI_PHY_623_DATA */
+		0x00000000	/* DENALI_PHY_624_DATA */
+		0x00000000	/* DENALI_PHY_625_DATA */
+		0x00000000	/* DENALI_PHY_626_DATA */
+		0x00000000	/* DENALI_PHY_627_DATA */
+		0x00000000	/* DENALI_PHY_628_DATA */
+		0x00000000	/* DENALI_PHY_629_DATA */
+		0x00000000	/* DENALI_PHY_630_DATA */
+		0x00000000	/* DENALI_PHY_631_DATA */
+		0x00000000	/* DENALI_PHY_632_DATA */
+		0x00000000	/* DENALI_PHY_633_DATA */
+		0x00000000	/* DENALI_PHY_634_DATA */
+		0x00000000	/* DENALI_PHY_635_DATA */
+		0x00000000	/* DENALI_PHY_636_DATA */
+		0x00000000	/* DENALI_PHY_637_DATA */
+		0x00000000	/* DENALI_PHY_638_DATA */
+		0x00000000	/* DENALI_PHY_639_DATA */
+		0x35176402	/* DENALI_PHY_640_DATA */
+		0x0004c008	/* DENALI_PHY_641_DATA */
+		0x000000da	/* DENALI_PHY_642_DATA */
+		0x00000000	/* DENALI_PHY_643_DATA */
+		0x00000000	/* DENALI_PHY_644_DATA */
+		0x00010000	/* DENALI_PHY_645_DATA */
+		0x01DDDD90	/* DENALI_PHY_646_DATA */
+		0x01DDDD90	/* DENALI_PHY_647_DATA */
+		0x01030001	/* DENALI_PHY_648_DATA */
+		0x01000000	/* DENALI_PHY_649_DATA */
+		0x00c00000	/* DENALI_PHY_650_DATA */
+		0x00000007	/* DENALI_PHY_651_DATA */
+		0x00000000	/* DENALI_PHY_652_DATA */
+		0x00000000	/* DENALI_PHY_653_DATA */
+		0x04000408	/* DENALI_PHY_654_DATA */
+		0x00000408	/* DENALI_PHY_655_DATA */
+		0x00e4e400	/* DENALI_PHY_656_DATA */
+		0x00000000	/* DENALI_PHY_657_DATA */
+		0x00000000	/* DENALI_PHY_658_DATA */
+		0x00000000	/* DENALI_PHY_659_DATA */
+		0x00000000	/* DENALI_PHY_660_DATA */
+		0x00000000	/* DENALI_PHY_661_DATA */
+		0x00000000	/* DENALI_PHY_662_DATA */
+		0x00000000	/* DENALI_PHY_663_DATA */
+		0x00000000	/* DENALI_PHY_664_DATA */
+		0x00000000	/* DENALI_PHY_665_DATA */
+		0x00000000	/* DENALI_PHY_666_DATA */
+		0x00000000	/* DENALI_PHY_667_DATA */
+		0x00000000	/* DENALI_PHY_668_DATA */
+		0x00000000	/* DENALI_PHY_669_DATA */
+		0x00000000	/* DENALI_PHY_670_DATA */
+		0x00000000	/* DENALI_PHY_671_DATA */
+		0x00000000	/* DENALI_PHY_672_DATA */
+		0x00200000	/* DENALI_PHY_673_DATA */
+		0x00000000	/* DENALI_PHY_674_DATA */
+		0x00000000	/* DENALI_PHY_675_DATA */
+		0x00000000	/* DENALI_PHY_676_DATA */
+		0x00000000	/* DENALI_PHY_677_DATA */
+		0x00000000	/* DENALI_PHY_678_DATA */
+		0x00000000	/* DENALI_PHY_679_DATA */
+		0x02800280	/* DENALI_PHY_680_DATA */
+		0x02800280	/* DENALI_PHY_681_DATA */
+		0x02800280	/* DENALI_PHY_682_DATA */
+		0x02800280	/* DENALI_PHY_683_DATA */
+		0x00000280	/* DENALI_PHY_684_DATA */
+		0x00000000	/* DENALI_PHY_685_DATA */
+		0x00000000	/* DENALI_PHY_686_DATA */
+		0x00000000	/* DENALI_PHY_687_DATA */
+		0x00000000	/* DENALI_PHY_688_DATA */
+		0x00000000	/* DENALI_PHY_689_DATA */
+		0x00800080	/* DENALI_PHY_690_DATA */
+		0x00800080	/* DENALI_PHY_691_DATA */
+		0x00800080	/* DENALI_PHY_692_DATA */
+		0x00800080	/* DENALI_PHY_693_DATA */
+		0x00800080	/* DENALI_PHY_694_DATA */
+		0x00800080	/* DENALI_PHY_695_DATA */
+		0x00800080	/* DENALI_PHY_696_DATA */
+		0x00800080	/* DENALI_PHY_697_DATA */
+		0x00800080	/* DENALI_PHY_698_DATA */
+		0x000100da	/* DENALI_PHY_699_DATA */
+		0x01ff0010	/* DENALI_PHY_700_DATA */
+		0x00000000	/* DENALI_PHY_701_DATA */
+		0x00000000	/* DENALI_PHY_702_DATA */
+		0x00000002	/* DENALI_PHY_703_DATA */
+		0x51313152	/* DENALI_PHY_704_DATA */
+		0x80013130	/* DENALI_PHY_705_DATA */
+		0x02000080	/* DENALI_PHY_706_DATA */
+		0x00100001	/* DENALI_PHY_707_DATA */
+		0x0c064208	/* DENALI_PHY_708_DATA */
+		0x000f0c0f	/* DENALI_PHY_709_DATA */
+		0x01000140	/* DENALI_PHY_710_DATA */
+		0x0000000c	/* DENALI_PHY_711_DATA */
+		0x00000000	/* DENALI_PHY_712_DATA */
+		0x00000000	/* DENALI_PHY_713_DATA */
+		0x00000000	/* DENALI_PHY_714_DATA */
+		0x00000000	/* DENALI_PHY_715_DATA */
+		0x00000000	/* DENALI_PHY_716_DATA */
+		0x00000000	/* DENALI_PHY_717_DATA */
+		0x00000000	/* DENALI_PHY_718_DATA */
+		0x00000000	/* DENALI_PHY_719_DATA */
+		0x00000000	/* DENALI_PHY_720_DATA */
+		0x00000000	/* DENALI_PHY_721_DATA */
+		0x00000000	/* DENALI_PHY_722_DATA */
+		0x00000000	/* DENALI_PHY_723_DATA */
+		0x00000000	/* DENALI_PHY_724_DATA */
+		0x00000000	/* DENALI_PHY_725_DATA */
+		0x00000000	/* DENALI_PHY_726_DATA */
+		0x00000000	/* DENALI_PHY_727_DATA */
+		0x00000000	/* DENALI_PHY_728_DATA */
+		0x00000000	/* DENALI_PHY_729_DATA */
+		0x00000000	/* DENALI_PHY_730_DATA */
+		0x00000000	/* DENALI_PHY_731_DATA */
+		0x00000000	/* DENALI_PHY_732_DATA */
+		0x00000000	/* DENALI_PHY_733_DATA */
+		0x00000000	/* DENALI_PHY_734_DATA */
+		0x00000000	/* DENALI_PHY_735_DATA */
+		0x00000000	/* DENALI_PHY_736_DATA */
+		0x00000000	/* DENALI_PHY_737_DATA */
+		0x00000000	/* DENALI_PHY_738_DATA */
+		0x00000000	/* DENALI_PHY_739_DATA */
+		0x00000000	/* DENALI_PHY_740_DATA */
+		0x00000000	/* DENALI_PHY_741_DATA */
+		0x00000000	/* DENALI_PHY_742_DATA */
+		0x00000000	/* DENALI_PHY_743_DATA */
+		0x00000000	/* DENALI_PHY_744_DATA */
+		0x00000000	/* DENALI_PHY_745_DATA */
+		0x00000000	/* DENALI_PHY_746_DATA */
+		0x00000000	/* DENALI_PHY_747_DATA */
+		0x00000000	/* DENALI_PHY_748_DATA */
+		0x00000000	/* DENALI_PHY_749_DATA */
+		0x00000000	/* DENALI_PHY_750_DATA */
+		0x00000000	/* DENALI_PHY_751_DATA */
+		0x00000000	/* DENALI_PHY_752_DATA */
+		0x00000000	/* DENALI_PHY_753_DATA */
+		0x00000000	/* DENALI_PHY_754_DATA */
+		0x00000000	/* DENALI_PHY_755_DATA */
+		0x00000000	/* DENALI_PHY_756_DATA */
+		0x00000000	/* DENALI_PHY_757_DATA */
+		0x00000000	/* DENALI_PHY_758_DATA */
+		0x00000000	/* DENALI_PHY_759_DATA */
+		0x00000000	/* DENALI_PHY_760_DATA */
+		0x00000000	/* DENALI_PHY_761_DATA */
+		0x00000000	/* DENALI_PHY_762_DATA */
+		0x00000000	/* DENALI_PHY_763_DATA */
+		0x00000000	/* DENALI_PHY_764_DATA */
+		0x00000000	/* DENALI_PHY_765_DATA */
+		0x00000000	/* DENALI_PHY_766_DATA */
+		0x00000000	/* DENALI_PHY_767_DATA */
+		0x10526347	/* DENALI_PHY_768_DATA */
+		0x0004c008	/* DENALI_PHY_769_DATA */
+		0x000000da	/* DENALI_PHY_770_DATA */
+		0x00000000	/* DENALI_PHY_771_DATA */
+		0x00000000	/* DENALI_PHY_772_DATA */
+		0x00010000	/* DENALI_PHY_773_DATA */
+		0x01DDDD90	/* DENALI_PHY_774_DATA */
+		0x01DDDD90	/* DENALI_PHY_775_DATA */
+		0x01030001	/* DENALI_PHY_776_DATA */
+		0x01000000	/* DENALI_PHY_777_DATA */
+		0x00c00000	/* DENALI_PHY_778_DATA */
+		0x00000007	/* DENALI_PHY_779_DATA */
+		0x00000000	/* DENALI_PHY_780_DATA */
+		0x00000000	/* DENALI_PHY_781_DATA */
+		0x04000408	/* DENALI_PHY_782_DATA */
+		0x00000408	/* DENALI_PHY_783_DATA */
+		0x00e4e400	/* DENALI_PHY_784_DATA */
+		0x00000000	/* DENALI_PHY_785_DATA */
+		0x00000000	/* DENALI_PHY_786_DATA */
+		0x00000000	/* DENALI_PHY_787_DATA */
+		0x00000000	/* DENALI_PHY_788_DATA */
+		0x00000000	/* DENALI_PHY_789_DATA */
+		0x00000000	/* DENALI_PHY_790_DATA */
+		0x00000000	/* DENALI_PHY_791_DATA */
+		0x00000000	/* DENALI_PHY_792_DATA */
+		0x00000000	/* DENALI_PHY_793_DATA */
+		0x00000000	/* DENALI_PHY_794_DATA */
+		0x00000000	/* DENALI_PHY_795_DATA */
+		0x00000000	/* DENALI_PHY_796_DATA */
+		0x00000000	/* DENALI_PHY_797_DATA */
+		0x00000000	/* DENALI_PHY_798_DATA */
+		0x00000000	/* DENALI_PHY_799_DATA */
+		0x00000000	/* DENALI_PHY_800_DATA */
+		0x00200000	/* DENALI_PHY_801_DATA */
+		0x00000000	/* DENALI_PHY_802_DATA */
+		0x00000000	/* DENALI_PHY_803_DATA */
+		0x00000000	/* DENALI_PHY_804_DATA */
+		0x00000000	/* DENALI_PHY_805_DATA */
+		0x00000000	/* DENALI_PHY_806_DATA */
+		0x00000000	/* DENALI_PHY_807_DATA */
+		0x02800280	/* DENALI_PHY_808_DATA */
+		0x02800280	/* DENALI_PHY_809_DATA */
+		0x02800280	/* DENALI_PHY_810_DATA */
+		0x02800280	/* DENALI_PHY_811_DATA */
+		0x00000280	/* DENALI_PHY_812_DATA */
+		0x00000000	/* DENALI_PHY_813_DATA */
+		0x00000000	/* DENALI_PHY_814_DATA */
+		0x00000000	/* DENALI_PHY_815_DATA */
+		0x00000000	/* DENALI_PHY_816_DATA */
+		0x00000000	/* DENALI_PHY_817_DATA */
+		0x00800080	/* DENALI_PHY_818_DATA */
+		0x00800080	/* DENALI_PHY_819_DATA */
+		0x00800080	/* DENALI_PHY_820_DATA */
+		0x00800080	/* DENALI_PHY_821_DATA */
+		0x00800080	/* DENALI_PHY_822_DATA */
+		0x00800080	/* DENALI_PHY_823_DATA */
+		0x00800080	/* DENALI_PHY_824_DATA */
+		0x00800080	/* DENALI_PHY_825_DATA */
+		0x00800080	/* DENALI_PHY_826_DATA */
+		0x000100da	/* DENALI_PHY_827_DATA */
+		0x01ff0010	/* DENALI_PHY_828_DATA */
+		0x00000000	/* DENALI_PHY_829_DATA */
+		0x00000000	/* DENALI_PHY_830_DATA */
+		0x00000002	/* DENALI_PHY_831_DATA */
+		0x51313152	/* DENALI_PHY_832_DATA */
+		0x80013130	/* DENALI_PHY_833_DATA */
+		0x02000080	/* DENALI_PHY_834_DATA */
+		0x00100001	/* DENALI_PHY_835_DATA */
+		0x0c064208	/* DENALI_PHY_836_DATA */
+		0x000f0c0f	/* DENALI_PHY_837_DATA */
+		0x01000140	/* DENALI_PHY_838_DATA */
+		0x0000000c	/* DENALI_PHY_839_DATA */
+		0x00000000	/* DENALI_PHY_840_DATA */
+		0x00000000	/* DENALI_PHY_841_DATA */
+		0x00000000	/* DENALI_PHY_842_DATA */
+		0x00000000	/* DENALI_PHY_843_DATA */
+		0x00000000	/* DENALI_PHY_844_DATA */
+		0x00000000	/* DENALI_PHY_845_DATA */
+		0x00000000	/* DENALI_PHY_846_DATA */
+		0x00000000	/* DENALI_PHY_847_DATA */
+		0x00000000	/* DENALI_PHY_848_DATA */
+		0x00000000	/* DENALI_PHY_849_DATA */
+		0x00000000	/* DENALI_PHY_850_DATA */
+		0x00000000	/* DENALI_PHY_851_DATA */
+		0x00000000	/* DENALI_PHY_852_DATA */
+		0x00000000	/* DENALI_PHY_853_DATA */
+		0x00000000	/* DENALI_PHY_854_DATA */
+		0x00000000	/* DENALI_PHY_855_DATA */
+		0x00000000	/* DENALI_PHY_856_DATA */
+		0x00000000	/* DENALI_PHY_857_DATA */
+		0x00000000	/* DENALI_PHY_858_DATA */
+		0x00000000	/* DENALI_PHY_859_DATA */
+		0x00000000	/* DENALI_PHY_860_DATA */
+		0x00000000	/* DENALI_PHY_861_DATA */
+		0x00000000	/* DENALI_PHY_862_DATA */
+		0x00000000	/* DENALI_PHY_863_DATA */
+		0x00000000	/* DENALI_PHY_864_DATA */
+		0x00000000	/* DENALI_PHY_865_DATA */
+		0x00000000	/* DENALI_PHY_866_DATA */
+		0x00000000	/* DENALI_PHY_867_DATA */
+		0x00000000	/* DENALI_PHY_868_DATA */
+		0x00000000	/* DENALI_PHY_869_DATA */
+		0x00000000	/* DENALI_PHY_870_DATA */
+		0x00000000	/* DENALI_PHY_871_DATA */
+		0x00000000	/* DENALI_PHY_872_DATA */
+		0x00000000	/* DENALI_PHY_873_DATA */
+		0x00000000	/* DENALI_PHY_874_DATA */
+		0x00000000	/* DENALI_PHY_875_DATA */
+		0x00000000	/* DENALI_PHY_876_DATA */
+		0x00000000	/* DENALI_PHY_877_DATA */
+		0x00000000	/* DENALI_PHY_878_DATA */
+		0x00000000	/* DENALI_PHY_879_DATA */
+		0x00000000	/* DENALI_PHY_880_DATA */
+		0x00000000	/* DENALI_PHY_881_DATA */
+		0x00000000	/* DENALI_PHY_882_DATA */
+		0x00000000	/* DENALI_PHY_883_DATA */
+		0x00000000	/* DENALI_PHY_884_DATA */
+		0x00000000	/* DENALI_PHY_885_DATA */
+		0x00000000	/* DENALI_PHY_886_DATA */
+		0x00000000	/* DENALI_PHY_887_DATA */
+		0x00000000	/* DENALI_PHY_888_DATA */
+		0x00000000	/* DENALI_PHY_889_DATA */
+		0x00000000	/* DENALI_PHY_890_DATA */
+		0x00000000	/* DENALI_PHY_891_DATA */
+		0x00000000	/* DENALI_PHY_892_DATA */
+		0x00000000	/* DENALI_PHY_893_DATA */
+		0x00000000	/* DENALI_PHY_894_DATA */
+		0x00000000	/* DENALI_PHY_895_DATA */
+		0x41753260	/* DENALI_PHY_896_DATA */
+		0x0004c008	/* DENALI_PHY_897_DATA */
+		0x000000da	/* DENALI_PHY_898_DATA */
+		0x00000000	/* DENALI_PHY_899_DATA */
+		0x00000000	/* DENALI_PHY_900_DATA */
+		0x00010000	/* DENALI_PHY_901_DATA */
+		0x01DDDD90	/* DENALI_PHY_902_DATA */
+		0x01DDDD90	/* DENALI_PHY_903_DATA */
+		0x01030001	/* DENALI_PHY_904_DATA */
+		0x01000000	/* DENALI_PHY_905_DATA */
+		0x00c00000	/* DENALI_PHY_906_DATA */
+		0x00000007	/* DENALI_PHY_907_DATA */
+		0x00000000	/* DENALI_PHY_908_DATA */
+		0x00000000	/* DENALI_PHY_909_DATA */
+		0x04000408	/* DENALI_PHY_910_DATA */
+		0x00000408	/* DENALI_PHY_911_DATA */
+		0x00e4e400	/* DENALI_PHY_912_DATA */
+		0x00000000	/* DENALI_PHY_913_DATA */
+		0x00000000	/* DENALI_PHY_914_DATA */
+		0x00000000	/* DENALI_PHY_915_DATA */
+		0x00000000	/* DENALI_PHY_916_DATA */
+		0x00000000	/* DENALI_PHY_917_DATA */
+		0x00000000	/* DENALI_PHY_918_DATA */
+		0x00000000	/* DENALI_PHY_919_DATA */
+		0x00000000	/* DENALI_PHY_920_DATA */
+		0x00000000	/* DENALI_PHY_921_DATA */
+		0x00000000	/* DENALI_PHY_922_DATA */
+		0x00000000	/* DENALI_PHY_923_DATA */
+		0x00000000	/* DENALI_PHY_924_DATA */
+		0x00000000	/* DENALI_PHY_925_DATA */
+		0x00000000	/* DENALI_PHY_926_DATA */
+		0x00000000	/* DENALI_PHY_927_DATA */
+		0x00000000	/* DENALI_PHY_928_DATA */
+		0x00200000	/* DENALI_PHY_929_DATA */
+		0x00000000	/* DENALI_PHY_930_DATA */
+		0x00000000	/* DENALI_PHY_931_DATA */
+		0x00000000	/* DENALI_PHY_932_DATA */
+		0x00000000	/* DENALI_PHY_933_DATA */
+		0x00000000	/* DENALI_PHY_934_DATA */
+		0x00000000	/* DENALI_PHY_935_DATA */
+		0x02800280	/* DENALI_PHY_936_DATA */
+		0x02800280	/* DENALI_PHY_937_DATA */
+		0x02800280	/* DENALI_PHY_938_DATA */
+		0x02800280	/* DENALI_PHY_939_DATA */
+		0x00000280	/* DENALI_PHY_940_DATA */
+		0x00000000	/* DENALI_PHY_941_DATA */
+		0x00000000	/* DENALI_PHY_942_DATA */
+		0x00000000	/* DENALI_PHY_943_DATA */
+		0x00000000	/* DENALI_PHY_944_DATA */
+		0x00000000	/* DENALI_PHY_945_DATA */
+		0x00800080	/* DENALI_PHY_946_DATA */
+		0x00800080	/* DENALI_PHY_947_DATA */
+		0x00800080	/* DENALI_PHY_948_DATA */
+		0x00800080	/* DENALI_PHY_949_DATA */
+		0x00800080	/* DENALI_PHY_950_DATA */
+		0x00800080	/* DENALI_PHY_951_DATA */
+		0x00800080	/* DENALI_PHY_952_DATA */
+		0x00800080	/* DENALI_PHY_953_DATA */
+		0x00800080	/* DENALI_PHY_954_DATA */
+		0x000100da	/* DENALI_PHY_955_DATA */
+		0x01ff0010	/* DENALI_PHY_956_DATA */
+		0x00000000	/* DENALI_PHY_957_DATA */
+		0x00000000	/* DENALI_PHY_958_DATA */
+		0x00000002	/* DENALI_PHY_959_DATA */
+		0x51313152	/* DENALI_PHY_960_DATA */
+		0x80013130	/* DENALI_PHY_961_DATA */
+		0x02000080	/* DENALI_PHY_962_DATA */
+		0x00100001	/* DENALI_PHY_963_DATA */
+		0x0c064208	/* DENALI_PHY_964_DATA */
+		0x000f0c0f	/* DENALI_PHY_965_DATA */
+		0x01000140	/* DENALI_PHY_966_DATA */
+		0x0000000c	/* DENALI_PHY_967_DATA */
+		0x00000000	/* DENALI_PHY_968_DATA */
+		0x00000000	/* DENALI_PHY_969_DATA */
+		0x00000000	/* DENALI_PHY_970_DATA */
+		0x00000000	/* DENALI_PHY_971_DATA */
+		0x00000000	/* DENALI_PHY_972_DATA */
+		0x00000000	/* DENALI_PHY_973_DATA */
+		0x00000000	/* DENALI_PHY_974_DATA */
+		0x00000000	/* DENALI_PHY_975_DATA */
+		0x00000000	/* DENALI_PHY_976_DATA */
+		0x00000000	/* DENALI_PHY_977_DATA */
+		0x00000000	/* DENALI_PHY_978_DATA */
+		0x00000000	/* DENALI_PHY_979_DATA */
+		0x00000000	/* DENALI_PHY_980_DATA */
+		0x00000000	/* DENALI_PHY_981_DATA */
+		0x00000000	/* DENALI_PHY_982_DATA */
+		0x00000000	/* DENALI_PHY_983_DATA */
+		0x00000000	/* DENALI_PHY_984_DATA */
+		0x00000000	/* DENALI_PHY_985_DATA */
+		0x00000000	/* DENALI_PHY_986_DATA */
+		0x00000000	/* DENALI_PHY_987_DATA */
+		0x00000000	/* DENALI_PHY_988_DATA */
+		0x00000000	/* DENALI_PHY_989_DATA */
+		0x00000000	/* DENALI_PHY_990_DATA */
+		0x00000000	/* DENALI_PHY_991_DATA */
+		0x00000000	/* DENALI_PHY_992_DATA */
+		0x00000000	/* DENALI_PHY_993_DATA */
+		0x00000000	/* DENALI_PHY_994_DATA */
+		0x00000000	/* DENALI_PHY_995_DATA */
+		0x00000000	/* DENALI_PHY_996_DATA */
+		0x00000000	/* DENALI_PHY_997_DATA */
+		0x00000000	/* DENALI_PHY_998_DATA */
+		0x00000000	/* DENALI_PHY_999_DATA */
+		0x00000000	/* DENALI_PHY_1000_DATA */
+		0x00000000	/* DENALI_PHY_1001_DATA */
+		0x00000000	/* DENALI_PHY_1002_DATA */
+		0x00000000	/* DENALI_PHY_1003_DATA */
+		0x00000000	/* DENALI_PHY_1004_DATA */
+		0x00000000	/* DENALI_PHY_1005_DATA */
+		0x00000000	/* DENALI_PHY_1006_DATA */
+		0x00000000	/* DENALI_PHY_1007_DATA */
+		0x00000000	/* DENALI_PHY_1008_DATA */
+		0x00000000	/* DENALI_PHY_1009_DATA */
+		0x00000000	/* DENALI_PHY_1010_DATA */
+		0x00000000	/* DENALI_PHY_1011_DATA */
+		0x00000000	/* DENALI_PHY_1012_DATA */
+		0x00000000	/* DENALI_PHY_1013_DATA */
+		0x00000000	/* DENALI_PHY_1014_DATA */
+		0x00000000	/* DENALI_PHY_1015_DATA */
+		0x00000000	/* DENALI_PHY_1016_DATA */
+		0x00000000	/* DENALI_PHY_1017_DATA */
+		0x00000000	/* DENALI_PHY_1018_DATA */
+		0x00000000	/* DENALI_PHY_1019_DATA */
+		0x00000000	/* DENALI_PHY_1020_DATA */
+		0x00000000	/* DENALI_PHY_1021_DATA */
+		0x00000000	/* DENALI_PHY_1022_DATA */
+		0x00000000	/* DENALI_PHY_1023_DATA */
+		0x76543210	/* DENALI_PHY_1024_DATA */
+		0x0004c008	/* DENALI_PHY_1025_DATA */
+		0x000000da	/* DENALI_PHY_1026_DATA */
+		0x00000000	/* DENALI_PHY_1027_DATA */
+		0x00000000	/* DENALI_PHY_1028_DATA */
+		0x00010000	/* DENALI_PHY_1029_DATA */
+		0x01665555	/* DENALI_PHY_1030_DATA */
+		0x01665555	/* DENALI_PHY_1031_DATA */
+		0x01030001	/* DENALI_PHY_1032_DATA */
+		0x01000000	/* DENALI_PHY_1033_DATA */
+		0x00c00000	/* DENALI_PHY_1034_DATA */
+		0x00000007	/* DENALI_PHY_1035_DATA */
+		0x00000000	/* DENALI_PHY_1036_DATA */
+		0x00000000	/* DENALI_PHY_1037_DATA */
+		0x04000408	/* DENALI_PHY_1038_DATA */
+		0x00000408	/* DENALI_PHY_1039_DATA */
+		0x00e4e400	/* DENALI_PHY_1040_DATA */
+		0x00000000	/* DENALI_PHY_1041_DATA */
+		0x00000000	/* DENALI_PHY_1042_DATA */
+		0x00000000	/* DENALI_PHY_1043_DATA */
+		0x00000000	/* DENALI_PHY_1044_DATA */
+		0x00000000	/* DENALI_PHY_1045_DATA */
+		0x00000000	/* DENALI_PHY_1046_DATA */
+		0x00000000	/* DENALI_PHY_1047_DATA */
+		0x00000000	/* DENALI_PHY_1048_DATA */
+		0x00000000	/* DENALI_PHY_1049_DATA */
+		0x00000000	/* DENALI_PHY_1050_DATA */
+		0x00000000	/* DENALI_PHY_1051_DATA */
+		0x00000000	/* DENALI_PHY_1052_DATA */
+		0x00000000	/* DENALI_PHY_1053_DATA */
+		0x00000000	/* DENALI_PHY_1054_DATA */
+		0x00000000	/* DENALI_PHY_1055_DATA */
+		0x00000000	/* DENALI_PHY_1056_DATA */
+		0x00200000	/* DENALI_PHY_1057_DATA */
+		0x00000000	/* DENALI_PHY_1058_DATA */
+		0x00000000	/* DENALI_PHY_1059_DATA */
+		0x00000000	/* DENALI_PHY_1060_DATA */
+		0x00000000	/* DENALI_PHY_1061_DATA */
+		0x00000000	/* DENALI_PHY_1062_DATA */
+		0x00000000	/* DENALI_PHY_1063_DATA */
+		0x02800280	/* DENALI_PHY_1064_DATA */
+		0x02800280	/* DENALI_PHY_1065_DATA */
+		0x02800280	/* DENALI_PHY_1066_DATA */
+		0x02800280	/* DENALI_PHY_1067_DATA */
+		0x00000280	/* DENALI_PHY_1068_DATA */
+		0x00000000	/* DENALI_PHY_1069_DATA */
+		0x00000000	/* DENALI_PHY_1070_DATA */
+		0x00000000	/* DENALI_PHY_1071_DATA */
+		0x00000000	/* DENALI_PHY_1072_DATA */
+		0x00000000	/* DENALI_PHY_1073_DATA */
+		0x00800080	/* DENALI_PHY_1074_DATA */
+		0x00800080	/* DENALI_PHY_1075_DATA */
+		0x00800080	/* DENALI_PHY_1076_DATA */
+		0x00800080	/* DENALI_PHY_1077_DATA */
+		0x00800080	/* DENALI_PHY_1078_DATA */
+		0x00800080	/* DENALI_PHY_1079_DATA */
+		0x00800080	/* DENALI_PHY_1080_DATA */
+		0x00800080	/* DENALI_PHY_1081_DATA */
+		0x00800080	/* DENALI_PHY_1082_DATA */
+		0x000100da	/* DENALI_PHY_1083_DATA */
+		0x01ff0010	/* DENALI_PHY_1084_DATA */
+		0x00000000	/* DENALI_PHY_1085_DATA */
+		0x00000000	/* DENALI_PHY_1086_DATA */
+		0x00000002	/* DENALI_PHY_1087_DATA */
+		0x51313152	/* DENALI_PHY_1088_DATA */
+		0x80013130	/* DENALI_PHY_1089_DATA */
+		0x02000080	/* DENALI_PHY_1090_DATA */
+		0x00100001	/* DENALI_PHY_1091_DATA */
+		0x0c064208	/* DENALI_PHY_1092_DATA */
+		0x000f0c0f	/* DENALI_PHY_1093_DATA */
+		0x01000140	/* DENALI_PHY_1094_DATA */
+		0x0000000c	/* DENALI_PHY_1095_DATA */
+		0x00000000	/* DENALI_PHY_1096_DATA */
+		0x00000000	/* DENALI_PHY_1097_DATA */
+		0x00000000	/* DENALI_PHY_1098_DATA */
+		0x00000000	/* DENALI_PHY_1099_DATA */
+		0x00000000	/* DENALI_PHY_1100_DATA */
+		0x00000000	/* DENALI_PHY_1101_DATA */
+		0x00000000	/* DENALI_PHY_1102_DATA */
+		0x00000000	/* DENALI_PHY_1103_DATA */
+		0x00000000	/* DENALI_PHY_1104_DATA */
+		0x00000000	/* DENALI_PHY_1105_DATA */
+		0x00000000	/* DENALI_PHY_1106_DATA */
+		0x00000000	/* DENALI_PHY_1107_DATA */
+		0x00000000	/* DENALI_PHY_1108_DATA */
+		0x00000000	/* DENALI_PHY_1109_DATA */
+		0x00000000	/* DENALI_PHY_1110_DATA */
+		0x00000000	/* DENALI_PHY_1111_DATA */
+		0x00000000	/* DENALI_PHY_1112_DATA */
+		0x00000000	/* DENALI_PHY_1113_DATA */
+		0x00000000	/* DENALI_PHY_1114_DATA */
+		0x00000000	/* DENALI_PHY_1115_DATA */
+		0x00000000	/* DENALI_PHY_1116_DATA */
+		0x00000000	/* DENALI_PHY_1117_DATA */
+		0x00000000	/* DENALI_PHY_1118_DATA */
+		0x00000000	/* DENALI_PHY_1119_DATA */
+		0x00000000	/* DENALI_PHY_1120_DATA */
+		0x00000000	/* DENALI_PHY_1121_DATA */
+		0x00000000	/* DENALI_PHY_1122_DATA */
+		0x00000000	/* DENALI_PHY_1123_DATA */
+		0x00000000	/* DENALI_PHY_1124_DATA */
+		0x00000000	/* DENALI_PHY_1125_DATA */
+		0x00000000	/* DENALI_PHY_1126_DATA */
+		0x00000000	/* DENALI_PHY_1127_DATA */
+		0x00000000	/* DENALI_PHY_1128_DATA */
+		0x00000000	/* DENALI_PHY_1129_DATA */
+		0x00000000	/* DENALI_PHY_1130_DATA */
+		0x00000000	/* DENALI_PHY_1131_DATA */
+		0x00000000	/* DENALI_PHY_1132_DATA */
+		0x00000000	/* DENALI_PHY_1133_DATA */
+		0x00000000	/* DENALI_PHY_1134_DATA */
+		0x00000000	/* DENALI_PHY_1135_DATA */
+		0x00000000	/* DENALI_PHY_1136_DATA */
+		0x00000000	/* DENALI_PHY_1137_DATA */
+		0x00000000	/* DENALI_PHY_1138_DATA */
+		0x00000000	/* DENALI_PHY_1139_DATA */
+		0x00000000	/* DENALI_PHY_1140_DATA */
+		0x00000000	/* DENALI_PHY_1141_DATA */
+		0x00000000	/* DENALI_PHY_1142_DATA */
+		0x00000000	/* DENALI_PHY_1143_DATA */
+		0x00000000	/* DENALI_PHY_1144_DATA */
+		0x00000000	/* DENALI_PHY_1145_DATA */
+		0x00000000	/* DENALI_PHY_1146_DATA */
+		0x00000000	/* DENALI_PHY_1147_DATA */
+		0x00000000	/* DENALI_PHY_1148_DATA */
+		0x00000000	/* DENALI_PHY_1149_DATA */
+		0x00000000	/* DENALI_PHY_1150_DATA */
+		0x00000000	/* DENALI_PHY_1151_DATA */
+		0x00000000	/* DENALI_PHY_1152_DATA */
+		0x00000000	/* DENALI_PHY_1153_DATA */
+		0x00050000	/* DENALI_PHY_1154_DATA */
+		0x00000000	/* DENALI_PHY_1155_DATA */
+		0x00000000	/* DENALI_PHY_1156_DATA */
+		0x00000000	/* DENALI_PHY_1157_DATA */
+		0x00000100	/* DENALI_PHY_1158_DATA */
+		0x00000000	/* DENALI_PHY_1159_DATA */
+		0x00000000	/* DENALI_PHY_1160_DATA */
+		0x00506401	/* DENALI_PHY_1161_DATA */
+		0x01221102	/* DENALI_PHY_1162_DATA */
+		0x00000122	/* DENALI_PHY_1163_DATA */
+		0x00000000	/* DENALI_PHY_1164_DATA */
+		0x000B1F00	/* DENALI_PHY_1165_DATA */
+		0x0B1F0B1F	/* DENALI_PHY_1166_DATA */
+		0x0B1F0B1F	/* DENALI_PHY_1167_DATA */
+		0x0B1F0B1F	/* DENALI_PHY_1168_DATA */
+		0x0B1F0B1F	/* DENALI_PHY_1169_DATA */
+		0x00000B00	/* DENALI_PHY_1170_DATA */
+		0x42080010	/* DENALI_PHY_1171_DATA */
+		0x01000100	/* DENALI_PHY_1172_DATA */
+		0x01000100	/* DENALI_PHY_1173_DATA */
+		0x01000100	/* DENALI_PHY_1174_DATA */
+		0x01000100	/* DENALI_PHY_1175_DATA */
+		0x00000000	/* DENALI_PHY_1176_DATA */
+		0x00000000	/* DENALI_PHY_1177_DATA */
+		0x00000000	/* DENALI_PHY_1178_DATA */
+		0x00000000	/* DENALI_PHY_1179_DATA */
+		0x00000000	/* DENALI_PHY_1180_DATA */
+		0x00000803	/* DENALI_PHY_1181_DATA */
+		0x223FFF00	/* DENALI_PHY_1182_DATA */
+		0x000008FF	/* DENALI_PHY_1183_DATA */
+		0x0000057F	/* DENALI_PHY_1184_DATA */
+		0x0000057F	/* DENALI_PHY_1185_DATA */
+		0x00037FFF	/* DENALI_PHY_1186_DATA */
+		0x00037FFF	/* DENALI_PHY_1187_DATA */
+		0x00004410	/* DENALI_PHY_1188_DATA */
+		0x00004410	/* DENALI_PHY_1189_DATA */
+		0x00004410	/* DENALI_PHY_1190_DATA */
+		0x00004410	/* DENALI_PHY_1191_DATA */
+		0x00004410	/* DENALI_PHY_1192_DATA */
+		0x00000111	/* DENALI_PHY_1193_DATA */
+		0x00000111	/* DENALI_PHY_1194_DATA */
+		0x00000000	/* DENALI_PHY_1195_DATA */
+		0x00000000	/* DENALI_PHY_1196_DATA */
+		0x00000000	/* DENALI_PHY_1197_DATA */
+		0x04000000	/* DENALI_PHY_1198_DATA */
+		0x00000000	/* DENALI_PHY_1199_DATA */
+		0x00000000	/* DENALI_PHY_1200_DATA */
+		0x00000108	/* DENALI_PHY_1201_DATA */
+		0x00000000	/* DENALI_PHY_1202_DATA */
+		0x00000000	/* DENALI_PHY_1203_DATA */
+		0x00000000	/* DENALI_PHY_1204_DATA */
+		0x00000001	/* DENALI_PHY_1205_DATA */
+		0x00000000	/* DENALI_PHY_1206_DATA */
+		0x00000000	/* DENALI_PHY_1207_DATA */
+		0x00000000	/* DENALI_PHY_1208_DATA */
+		0x00000000	/* DENALI_PHY_1209_DATA */
+		0x00000000	/* DENALI_PHY_1210_DATA */
+		0x00000000	/* DENALI_PHY_1211_DATA */
+		0x00020100	/* DENALI_PHY_1212_DATA */
+		0x00000000	/* DENALI_PHY_1213_DATA */
+		0x00000000	/* DENALI_PHY_1214_DATA */
+	>;
+};
diff --git a/roms/u-boot/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/roms/u-boot/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
new file mode 100644
index 000000000..51b566116
--- /dev/null
+++ b/roms/u-boot/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "binman.dtsi"
+#include "fu540-c000-u-boot.dtsi"
+#include "fu540-hifive-unleashed-a00-ddr.dtsi"
+
+/ {
+	aliases {
+		cpu1 = &cpu1;
+		cpu2 = &cpu2;
+		cpu3 = &cpu3;
+		cpu4 = &cpu4;
+		spi0 = &qspi0;
+		spi2 = &qspi2;
+	};
+
+	config {
+		u-boot,spl-payload-offset = <0x105000>; /* loader2 @1044KB */
+	};
+
+	memory@80000000 {
+		u-boot,dm-spl;
+	};
+
+	hfclk {
+		u-boot,dm-spl;
+	};
+
+	rtcclk {
+		u-boot,dm-spl;
+	};
+
+};
+
+&clint {
+	clocks = <&rtcclk>;
+};
+
+&qspi0 {
+	u-boot,dm-spl;
+
+	flash@0 {
+		u-boot,dm-spl;
+	};
+};
+
+&qspi2 {
+	mmc@0 {
+		u-boot,dm-spl;
+	};
+};
+
+&gpio {
+	u-boot,dm-spl;
+};
diff --git a/roms/u-boot/arch/riscv/dts/hifive-unleashed-a00.dts b/roms/u-boot/arch/riscv/dts/hifive-unleashed-a00.dts
new file mode 100644
index 000000000..4a2729f5c
--- /dev/null
+++ b/roms/u-boot/arch/riscv/dts/hifive-unleashed-a00.dts
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2018-2019 SiFive, Inc */
+
+#include "fu540-c000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+#define RTCCLK_FREQ		1000000
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "SiFive HiFive Unleashed A00";
+	compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
+
+	chosen {
+		stdout-path = "serial0";
+	};
+
+	cpus {
+		timebase-frequency = <RTCCLK_FREQ>;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x2 0x00000000>;
+	};
+
+	soc {
+	};
+
+	hfclk: hfclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <33333333>;
+		clock-output-names = "hfclk";
+	};
+
+	rtcclk: rtcclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <RTCCLK_FREQ>;
+		clock-output-names = "rtcclk";
+	};
+	gpio-restart {
+		compatible = "gpio-restart";
+		gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&qspi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "issi,is25wp256", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+	};
+};
+
+&qspi2 {
+	status = "okay";
+	mmc@0 {
+		compatible = "mmc-spi-slot";
+		reg = <0>;
+		spi-max-frequency = <20000000>;
+		voltage-ranges = <3300 3300>;
+		disable-wp;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	phy-mode = "gmii";
+	phy-handle = <&phy0>;
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+	};
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&gpio {
+	status = "okay";
+};
diff --git a/roms/u-boot/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi b/roms/u-boot/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
new file mode 100644
index 000000000..c5475aa14
--- /dev/null
+++ b/roms/u-boot/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2020-2021 SiFive, Inc
+ */
+
+#include "binman.dtsi"
+#include "fu740-c000-u-boot.dtsi"
+#include "fu740-hifive-unmatched-a00-ddr.dtsi"
+
+/ {
+	aliases {
+		spi0 = &spi0;
+	};
+
+	memory@80000000 {
+		u-boot,dm-spl;
+	};
+
+	hfclk {
+		u-boot,dm-spl;
+	};
+
+	rtcclk {
+		u-boot,dm-spl;
+	};
+
+};
+
+&clint {
+	clocks = <&rtcclk>;
+};
+
+&spi0 {
+	mmc@0 {
+		u-boot,dm-spl;
+	};
+};
+
+&gpio {
+	u-boot,dm-spl;
+};
diff --git a/roms/u-boot/arch/riscv/dts/hifive-unmatched-a00.dts b/roms/u-boot/arch/riscv/dts/hifive-unmatched-a00.dts
new file mode 100644
index 000000000..b44e8c160
--- /dev/null
+++ b/roms/u-boot/arch/riscv/dts/hifive-unmatched-a00.dts
@@ -0,0 +1,259 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (c) 2019-2021 SiFive, Inc */
+
+#include "fu740-c000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+#define RTCCLK_FREQ		1000000
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "SiFive HiFive Unmatched A00";
+	compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
+		     "sifive,fu740";
+
+	chosen {
+		stdout-path = "serial0";
+	};
+
+	cpus {
+		timebase-frequency = <RTCCLK_FREQ>;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x4 0x00000000>;
+	};
+
+	soc {
+	};
+
+	hfclk: hfclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <26000000>;
+		clock-output-names = "hfclk";
+	};
+
+	rtcclk: rtcclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <RTCCLK_FREQ>;
+		clock-output-names = "rtcclk";
+	};
+
+	gpio-poweroff {
+		compatible = "gpio-poweroff";
+		gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	temperature-sensor@4c {
+		compatible = "ti,tmp451";
+		reg = <0x4c>;
+		interrupt-parent = <&gpio>;
+		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pmic@58 {
+		compatible = "dlg,da9063";
+		reg = <0x58>;
+		interrupt-parent = <&gpio>;
+		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-controller;
+
+		regulators {
+			vdd_bcore1: bcore1 {
+				regulator-min-microvolt = <1050000>;
+				regulator-max-microvolt = <1050000>;
+				regulator-min-microamp = <5000000>;
+				regulator-max-microamp = <5000000>;
+				regulator-always-on;
+			};
+
+			vdd_bcore2: bcore2 {
+				regulator-min-microvolt = <1050000>;
+				regulator-max-microvolt = <1050000>;
+				regulator-min-microamp = <5000000>;
+				regulator-max-microamp = <5000000>;
+				regulator-always-on;
+			};
+
+			vdd_bpro: bpro {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-min-microamp = <2500000>;
+				regulator-max-microamp = <2500000>;
+				regulator-always-on;
+			};
+
+			vdd_bperi: bperi {
+				regulator-min-microvolt = <1050000>;
+				regulator-max-microvolt = <1050000>;
+				regulator-min-microamp = <1500000>;
+				regulator-max-microamp = <1500000>;
+				regulator-always-on;
+			};
+
+			vdd_bmem: bmem {
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-min-microamp = <3000000>;
+				regulator-max-microamp = <3000000>;
+				regulator-always-on;
+			};
+
+			vdd_bio: bio {
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-min-microamp = <3000000>;
+				regulator-max-microamp = <3000000>;
+				regulator-always-on;
+			};
+
+			vdd_ldo1: ldo1 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-min-microamp = <100000>;
+				regulator-max-microamp = <100000>;
+				regulator-always-on;
+			};
+
+			vdd_ldo2: ldo2 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-min-microamp = <200000>;
+				regulator-max-microamp = <200000>;
+				regulator-always-on;
+			};
+
+			vdd_ldo3: ldo3 {
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-min-microamp = <200000>;
+				regulator-max-microamp = <200000>;
+				regulator-always-on;
+			};
+
+			vdd_ldo4: ldo4 {
+				regulator-min-microvolt = <2500000>;
+				regulator-max-microvolt = <2500000>;
+				regulator-min-microamp = <200000>;
+				regulator-max-microamp = <200000>;
+				regulator-always-on;
+			};
+
+			vdd_ldo5: ldo5 {
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-min-microamp = <100000>;
+				regulator-max-microamp = <100000>;
+				regulator-always-on;
+			};
+
+			vdd_ldo6: ldo6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-min-microamp = <200000>;
+				regulator-max-microamp = <200000>;
+				regulator-always-on;
+			};
+
+			vdd_ldo7: ldo7 {
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-min-microamp = <200000>;
+				regulator-max-microamp = <200000>;
+				regulator-always-on;
+			};
+
+			vdd_ldo8: ldo8 {
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-min-microamp = <200000>;
+				regulator-max-microamp = <200000>;
+				regulator-always-on;
+			};
+
+			vdd_ld09: ldo9 {
+				regulator-min-microvolt = <1050000>;
+				regulator-max-microvolt = <1050000>;
+				regulator-min-microamp = <200000>;
+				regulator-max-microamp = <200000>;
+			};
+
+			vdd_ldo10: ldo10 {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-min-microamp = <300000>;
+				regulator-max-microamp = <300000>;
+			};
+
+			vdd_ldo11: ldo11 {
+				regulator-min-microvolt = <2500000>;
+				regulator-max-microvolt = <2500000>;
+				regulator-min-microamp = <300000>;
+				regulator-max-microamp = <300000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&qspi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "issi,is25wp256", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+	};
+};
+
+&spi0 {
+	status = "okay";
+	mmc@0 {
+		compatible = "mmc-spi-slot";
+		reg = <0>;
+		spi-max-frequency = <20000000>;
+		voltage-ranges = <3300 3300>;
+		disable-wp;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	phy-mode = "gmii";
+	phy-handle = <&phy0>;
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+	};
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&gpio {
+	status = "okay";
+};
diff --git a/roms/u-boot/arch/riscv/dts/k210-maix-bit.dts b/roms/u-boot/arch/riscv/dts/k210-maix-bit.dts
new file mode 100644
index 000000000..902dcfd08
--- /dev/null
+++ b/roms/u-boot/arch/riscv/dts/k210-maix-bit.dts
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "k210.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "Sipeed Maix Bit 2.0";
+	compatible = "sipeed,maix-bitm", "sipeed,maix-bit", "kendryte,k210";
+
+	chosen {
+		stdout-path = "serial0:115200";
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		green {
+			gpios = <&gpio1_0 4 GPIO_ACTIVE_LOW>;
+		};
+
+		red {
+			gpios = <&gpio1_0 5 GPIO_ACTIVE_LOW>;
+		};
+
+		blue {
+			gpios = <&gpio1_0 6 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		boot {
+			label = "BOOT";
+			linux,code = <BTN_0>;
+			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		status = "disabled";
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0 0>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&mic>;
+		};
+	};
+
+	mic: mic {
+		#sound-dai-cells = <0>;
+		compatible = "memsensing,msm61s4030h0";
+		status = "disabled";
+	};
+};
+
+&uarths0 {
+	pinctrl-0 = <&fpioa_uarths>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&gpio0 {
+	pinctrl-0 = <&fpioa_gpiohs>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&gpio1 {
+	pinctrl-0 = <&fpioa_gpio>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&i2s0 {
+	#sound-dai-cells = <1>;
+	pinctrl-0 = <&fpioa_i2s0>;
+	pinctrl-names = "default";
+};
+
+&fpioa {
+	status = "okay";
+
+	fpioa_uarths: uarths {
+		pinmux = <K210_FPIOA(4, K210_PCF_UARTHS_RX)>,
+			 <K210_FPIOA(5, K210_PCF_UARTHS_TX)>;
+	};
+
+	fpioa_gpio: gpio {
+		pinmux = <K210_FPIOA(8, K210_PCF_GPIO0)>,
+			 <K210_FPIOA(9, K210_PCF_GPIO1)>,
+			 <K210_FPIOA(10, K210_PCF_GPIO2)>,
+			 <K210_FPIOA(11, K210_PCF_GPIO3)>,
+			 <K210_FPIOA(12, K210_PCF_GPIO4)>,
+			 <K210_FPIOA(13, K210_PCF_GPIO5)>,
+			 <K210_FPIOA(14, K210_PCF_GPIO6)>,
+			 <K210_FPIOA(15, K210_PCF_GPIO7)>;
+	};
+
+	fpioa_gpiohs: gpiohs {
+		pinmux = <K210_FPIOA(16, K210_PCF_GPIOHS0)>,
+			 <K210_FPIOA(17, K210_PCF_GPIOHS1)>,
+			 <K210_FPIOA(21, K210_PCF_GPIOHS5)>,
+			 <K210_FPIOA(22, K210_PCF_GPIOHS6)>,
+			 <K210_FPIOA(23, K210_PCF_GPIOHS7)>,
+			 <K210_FPIOA(24, K210_PCF_GPIOHS8)>,
+			 <K210_FPIOA(25, K210_PCF_GPIOHS9)>,
+			 <K210_FPIOA(30, K210_PCF_GPIOHS14)>,
+			 <K210_FPIOA(31, K210_PCF_GPIOHS15)>,
+			 <K210_FPIOA(32, K210_PCF_GPIOHS16)>,
+			 <K210_FPIOA(33, K210_PCF_GPIOHS17)>,
+			 <K210_FPIOA(34, K210_PCF_GPIOHS18)>,
+			 <K210_FPIOA(35, K210_PCF_GPIOHS19)>;
+	};
+
+	fpioa_i2s0: i2s0 {
+		pinmux = <K210_FPIOA(18, K210_PCF_I2S0_SCLK)>,
+			 <K210_FPIOA(19, K210_PCF_I2S0_WS)>,
+			 <K210_FPIOA(20, K210_PCF_I2S0_IN_D0)>;
+	};
+
+	fpioa_dvp: dvp {
+		pinmux = <K210_FPIOA(40, K210_PCF_SCCB_SDA)>,
+			 <K210_FPIOA(41, K210_PCF_SCCB_SCLK)>,
+			 <K210_FPIOA(42, K210_PCF_DVP_RST)>,
+			 <K210_FPIOA(43, K210_PCF_DVP_VSYNC)>,
+			 <K210_FPIOA(44, K210_PCF_DVP_PWDN)>,
+			 <K210_FPIOA(45, K210_PCF_DVP_HSYNC)>,
+			 <K210_FPIOA(46, K210_PCF_DVP_XCLK)>,
+			 <K210_FPIOA(47, K210_PCF_DVP_PCLK)>;
+	};
+
+	fpioa_spi0: spi0 {
+		pinmux = <K210_FPIOA(36, K210_PCF_GPIOHS20)>,  /* cs */
+			 <K210_FPIOA(37, K210_PCF_GPIOHS21)>,  /* rst */
+			 <K210_FPIOA(38, K210_PCF_GPIOHS22)>,  /* dc */
+			 <K210_FPIOA(39, K210_PCF_SPI0_SCLK)>; /* wr */
+	};
+
+	fpioa_spi1: spi1 {
+		pinmux = <K210_FPIOA(26, K210_PCF_SPI1_D1)>,
+			 <K210_FPIOA(27, K210_PCF_SPI1_SCLK)>,
+			 <K210_FPIOA(28, K210_PCF_SPI1_D0)>,
+			 <K210_FPIOA(29, K210_PCF_GPIOHS13)>; /* cs */
+	};
+};
+
+&dvp0 {
+	pinctrl-0 = <&fpioa_dvp>;
+	pinctrl-names = "default";
+};
+
+&spi0 {
+	pinctrl-0 = <&fpioa_spi0>;
+	pinctrl-names = "default";
+	num-cs = <1>;
+	cs-gpios = <&gpio0 20 0>;
+
+	panel@0 {
+		compatible = "sitronix,st7789v";
+		reg = <0>;
+		reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+		dc-gpios = <&gpio0 22 0>;
+		spi-max-frequency = <15000000>;
+		status = "disabled";
+	};
+};
+
+&spi1 {
+	pinctrl-0 = <&fpioa_spi1>;
+	pinctrl-names = "default";
+	num-cs = <1>;
+	cs-gpios = <&gpio0 13 0>;
+	status = "okay";
+
+	slot@0 {
+		compatible = "mmc-spi-slot";
+		reg = <0>;
+		spi-max-frequency = <25000000>;
+		voltage-ranges = <3300 3300>;
+		broken-cd;
+	};
+};
+
+&spi3 {
+	status = "okay";
+
+	spi-flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+		m25p,fast-read;
+		broken-flash-reset;
+	};
+};
diff --git a/roms/u-boot/arch/riscv/dts/k210.dtsi b/roms/u-boot/arch/riscv/dts/k210.dtsi
new file mode 100644
index 000000000..2492af803
--- /dev/null
+++ b/roms/u-boot/arch/riscv/dts/k210.dtsi
@@ -0,0 +1,603 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+ */
+
+#include <dt-bindings/clock/k210-sysctl.h>
+#include <dt-bindings/mfd/k210-sysctl.h>
+#include <dt-bindings/pinctrl/k210-pinctrl.h>
+#include <dt-bindings/reset/k210-sysctl.h>
+
+/ {
+	/*
+	 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
+	 * wide, and the upper half of all addresses is ignored.
+	 */
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "kendryte,k210";
+
+	aliases {
+		cpu0 = &cpu0;
+		cpu1 = &cpu1;
+		dma0 = &dmac0;
+		gpio0 = &gpio0;
+		gpio1 = &gpio1_0;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		pinctrl0 = &fpioa;
+		serial0 = &uarths0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		spi0 = &spi0;
+		spi1 = &spi1;
+		spi2 = &spi2;
+		spi3 = &spi3;
+		timer0 = &timer0;
+		timer1 = &timer1;
+		timer2 = &timer2;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <7800000>;
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "kendryte,k210", "sifive,rocket0", "riscv";
+			reg = <0>;
+			riscv,isa = "rv64imafdgc";
+			mmu-type = "sv39";
+			i-cache-block-size = <64>;
+			i-cache-size = <0x8000>;
+			d-cache-block-size = <64>;
+			d-cache-size = <0x8000>;
+			clocks = <&sysclk K210_CLK_CPU>;
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "kendryte,k210", "sifive,rocket0", "riscv";
+			reg = <1>;
+			riscv,isa = "rv64imafdgc";
+			mmu-type = "sv39";
+			i-cache-block-size = <64>;
+			i-cache-size = <0x8000>;
+			d-cache-block-size = <64>;
+			d-cache-size = <0x8000>;
+			clocks = <&sysclk K210_CLK_CPU>;
+			cpu1_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+	};
+
+	sram: memory@80000000 {
+		device_type = "memory";
+		compatible = "kendryte,k210-sram";
+		reg = <0x80000000 0x400000>,
+		      <0x80400000 0x200000>,
+		      <0x80600000 0x200000>;
+		reg-names = "sram0", "sram1", "aisram";
+		clocks = <&sysclk K210_CLK_SRAM0>,
+			 <&sysclk K210_CLK_SRAM1>,
+			 <&sysclk K210_CLK_AI>;
+		clock-names = "sram0", "sram1", "aisram";
+		u-boot,dm-pre-reloc;
+	};
+
+	clocks {
+		in0: osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <26000000>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "kendryte,k210-soc", "simple-bus";
+		ranges;
+		interrupt-parent = <&plic0>;
+
+		debug0: debug@0 {
+			compatible = "kendryte,k210-debug", "riscv,debug";
+			reg = <0x0 0x1000>;
+		};
+
+		rom0: nvmem@1000 {
+			reg = <0x1000 0x1000>;
+			read-only;
+		};
+
+		clint0: clint@2000000 {
+			#interrupt-cells = <1>;
+			compatible = "kendryte,k210-clint", "riscv,clint0";
+			reg = <0x2000000 0xC000>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+					      <&cpu1_intc 3>, <&cpu1_intc 7>;
+			clocks = <&sysclk K210_CLK_CLINT>;
+		};
+
+		plic0: interrupt-controller@C000000 {
+			#interrupt-cells = <1>;
+			compatible = "kendryte,k210-plic", "riscv,plic0";
+			reg = <0xC000000 0x4000000>;
+			interrupt-controller;
+			interrupts-extended = <&cpu0_intc 9>, <&cpu0_intc 11>,
+					      <&cpu1_intc 9>, <&cpu1_intc 11>;
+			riscv,ndev = <65>;
+			riscv,max-priority = <7>;
+		};
+
+		uarths0: serial@38000000 {
+			compatible = "kendryte,k210-uarths", "sifive,uart0";
+			reg = <0x38000000 0x1000>;
+			interrupts = <33>;
+			clocks = <&sysclk K210_CLK_CPU>;
+			status = "disabled";
+		};
+
+		gpio0: gpio-controller@38001000 {
+			#interrupt-cells = <2>;
+			#gpio-cells = <2>;
+			compatible = "kendryte,k210-gpiohs", "sifive,gpio0";
+			reg = <0x38001000 0x1000>;
+			interrupt-controller;
+			interrupts = <34 35 36 37 38 39 40 41
+				      42 43 44 45 46 47 48 49
+				      50 51 52 53 54 55 56 57
+				      58 59 60 61 62 63 64 65>;
+			gpio-controller;
+			ngpios = <32>;
+			status = "disabled";
+		};
+
+		kpu0: kpu@40800000 {
+			compatible = "kendryte,k210-kpu";
+			reg = <0x40800000 0xc00000>;
+			interrupts = <25>;
+			clocks = <&sysclk K210_CLK_AI>;
+			status = "disabled";
+		};
+
+		fft0: fft@42000000 {
+			compatible = "kendryte,k210-fft";
+			reg = <0x42000000 0x400000>;
+			interrupts = <26>;
+			clocks = <&sysclk K210_CLK_FFT>;
+			resets = <&sysrst K210_RST_FFT>;
+			status = "disabled";
+		};
+
+		dmac0: dma-controller@50000000 {
+			compatible = "kendryte,k210-dmac", "snps,axi-dma-1.01a";
+			reg = <0x50000000 0x1000>;
+			interrupts = <27 28 29 30 31 32>;
+			clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>;
+			clock-names = "core-clk", "cfgr-clk";
+			resets = <&sysrst K210_RST_DMA>;
+			dma-channels = <6>;
+			snps,dma-masters = <2>;
+			snps,data-width = <5>;
+			snps,block-size = <0x200000 0x200000 0x200000
+					   0x200000 0x200000 0x200000>;
+			snps,axi-max-burst-len = <256>;
+			status = "disabled";
+		};
+
+		apb0: bus@50200000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "kendryte,k210-apb", "simple-pm-bus";
+			ranges;
+			clocks = <&sysclk K210_CLK_APB0>;
+
+			gpio1: gpio-controller@50200000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "kendryte,k210-gpio",
+					     "snps,dw-apb-gpio";
+				reg = <0x50200000 0x80>;
+				clocks = <&sysclk K210_CLK_GPIO>;
+				resets = <&sysrst K210_RST_GPIO>;
+				status = "disabled";
+
+				gpio1_0: gpio1@0 {
+					#gpio-cells = <2>;
+					#interrupt-cells = <2>;
+					compatible = "snps,dw-apb-gpio-port";
+					reg = <0>;
+					interrupt-controller;
+					interrupts = <23>;
+					gpio-controller;
+					snps,nr-gpios = <8>;
+				};
+			};
+
+			uart1: serial@50210000 {
+				compatible = "kendryte,k210-uart",
+					     "snps,dw-apb-uart";
+				reg = <0x50210000 0x100>;
+				interrupts = <11>;
+				clocks = <&sysclk K210_CLK_UART1>;
+				resets = <&sysrst K210_RST_UART1>;
+				reg-io-width = <4>;
+				reg-shift = <2>;
+				dcd-override;
+				dsr-override;
+				cts-override;
+				ri-override;
+				status = "disabled";
+			};
+
+			uart2: serial@50220000 {
+				compatible = "kendryte,k210-uart",
+					     "snps,dw-apb-uart";
+				reg = <0x50220000 0x100>;
+				interrupts = <12>;
+				clocks = <&sysclk K210_CLK_UART2>;
+				resets = <&sysrst K210_RST_UART2>;
+				reg-io-width = <4>;
+				reg-shift = <2>;
+				dcd-override;
+				dsr-override;
+				cts-override;
+				ri-override;
+				status = "disabled";
+			};
+
+			uart3: serial@50230000 {
+				compatible = "kendryte,k210-uart",
+					     "snps,dw-apb-uart";
+				reg = <0x50230000 0x100>;
+				interrupts = <13>;
+				clocks = <&sysclk K210_CLK_UART3>;
+				resets = <&sysrst K210_RST_UART3>;
+				reg-io-width = <4>;
+				reg-shift = <2>;
+				dcd-override;
+				dsr-override;
+				cts-override;
+				ri-override;
+				status = "disabled";
+			};
+
+			spi2: spi@50240000 {
+				compatible = "canaan,kendryte-k210-spi",
+					     "snps,dw-apb-ssi-4.01",
+					     "snps,dw-apb-ssi";
+				spi-slave;
+				reg = <0x50240000 0x100>;
+				interrupts = <2>;
+				clocks = <&sysclk K210_CLK_SPI2>;
+				resets = <&sysrst K210_RST_SPI2>;
+				spi-max-frequency = <25000000>;
+				status = "disabled";
+			};
+
+			i2s0: i2s@50250000 {
+				compatible = "kendryte,k210-i2s",
+					     "snps,designware-i2s";
+				reg = <0x50250000 0x200>;
+				interrupts = <5>;
+				clocks = <&sysclk K210_CLK_I2S0>;
+				clock-names = "i2sclk";
+				resets = <&sysrst K210_RST_I2S0>;
+				status = "disabled";
+			};
+
+			apu0: sound@520250200 {
+				compatible = "kendryte,k210-apu";
+				reg = <0x50250200 0x200>;
+				status = "disabled";
+			};
+
+			i2s1: i2s@50260000 {
+				compatible = "kendryte,k210-i2s",
+					     "snps,designware-i2s";
+				reg = <0x50260000 0x200>;
+				interrupts = <6>;
+				clocks = <&sysclk K210_CLK_I2S1>;
+				clock-names = "i2sclk";
+				resets = <&sysrst K210_RST_I2S1>;
+				status = "disabled";
+			};
+
+			i2s2: i2s@50270000 {
+				compatible = "kendryte,k210-i2s",
+					     "snps,designware-i2s";
+				reg = <0x50270000 0x200>;
+				interrupts = <7>;
+				clocks = <&sysclk K210_CLK_I2S2>;
+				clock-names = "i2sclk";
+				resets = <&sysrst K210_RST_I2S2>;
+				status = "disabled";
+			};
+
+			i2c0: i2c@50280000 {
+				compatible = "kendryte,k210-i2c",
+					     "snps,designware-i2c";
+				reg = <0x50280000 0x100>;
+				interrupts = <8>;
+				clocks = <&sysclk K210_CLK_I2C0>;
+				resets = <&sysrst K210_RST_I2C0>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@50290000 {
+				compatible = "kendryte,k210-i2c",
+					     "snps,designware-i2c";
+				reg = <0x50290000 0x100>;
+				interrupts = <9>;
+				clocks = <&sysclk K210_CLK_I2C1>;
+				resets = <&sysrst K210_RST_I2C1>;
+				status = "disabled";
+			};
+
+			i2c2: i2c@502A0000 {
+				compatible = "kendryte,k210-i2c",
+					     "snps,designware-i2c";
+				reg = <0x502A0000 0x100>;
+				interrupts = <10>;
+				clocks = <&sysclk K210_CLK_I2C2>;
+				resets = <&sysrst K210_RST_I2C2>;
+				status = "disabled";
+			};
+
+			fpioa: pinmux@502B0000 {
+				compatible = "kendryte,k210-fpioa";
+				reg = <0x502B0000 0x100>;
+				clocks = <&sysclk K210_CLK_FPIOA>;
+				resets = <&sysrst K210_RST_FPIOA>;
+				kendryte,sysctl = <&sysctl>;
+				kendryte,power-offset = <K210_SYSCTL_POWER_SEL>;
+				pinctrl-0 = <&fpioa_jtag>;
+				pinctrl-names = "default";
+				status = "disabled";
+
+				fpioa_jtag: jtag {
+					pinmux = <K210_FPIOA(0, K210_PCF_JTAG_TCLK)>,
+						 <K210_FPIOA(1, K210_PCF_JTAG_TDI)>,
+						 <K210_FPIOA(2, K210_PCF_JTAG_TMS)>,
+						 <K210_FPIOA(3, K210_PCF_JTAG_TDO)>;
+				};
+			};
+
+			sha256: sha256@502C0000 {
+				compatible = "kendryte,k210-sha256";
+				reg = <0x502C0000 0x100>;
+				clocks = <&sysclk K210_CLK_SHA>;
+				resets = <&sysrst K210_RST_SHA>;
+				status = "disabled";
+			};
+
+			timer0: timer@502D0000 {
+				compatible = "kendryte,k210-timer",
+					     "snps,dw-apb-timer";
+				reg = <0x502D0000 0x100>;
+				interrupts = <14 15>;
+				clocks = <&sysclk K210_CLK_TIMER0>;
+				clock-names = "timer";
+				resets = <&sysrst K210_RST_TIMER0>;
+				status = "disabled";
+			};
+
+			timer1: timer@502E0000 {
+				compatible = "kendryte,k210-timer",
+					     "snps,dw-apb-timer";
+				reg = <0x502E0000 0x100>;
+				interrupts = <16 17>;
+				clocks = <&sysclk K210_CLK_TIMER1>;
+				clock-names = "timer";
+				resets = <&sysrst K210_RST_TIMER1>;
+				status = "disabled";
+			};
+
+			timer2: timer@502F0000 {
+				compatible = "kendryte,k210-timer",
+					     "snps,dw-apb-timer";
+				reg = <0x502F0000 0x100>;
+				interrupts = <18 19>;
+				clocks = <&sysclk K210_CLK_TIMER2>;
+				clock-names = "timer";
+				resets = <&sysrst K210_RST_TIMER2>;
+				status = "disabled";
+			};
+		};
+
+		apb1: bus@50400000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "kendryte,k210-apb", "simple-pm-bus";
+			ranges;
+			clocks = <&sysclk K210_CLK_APB1>;
+
+			wdt0: watchdog@50400000 {
+				compatible = "kendryte,k210-wdt", "snps,dw-wdt";
+				reg = <0x50400000 0x100>;
+				interrupts = <21>;
+				clocks = <&sysclk K210_CLK_WDT0>;
+				resets = <&sysrst K210_RST_WDT0>;
+			};
+
+			wdt1: watchdog@50410000 {
+				compatible = "kendryte,k210-wdt", "snps,dw-wdt";
+				reg = <0x50410000 0x100>;
+				interrupts = <22>;
+				clocks = <&sysclk K210_CLK_WDT1>;
+				resets = <&sysrst K210_RST_WDT1>;
+				status = "disabled";
+			};
+
+			otp0: nvmem@50420000 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "kendryte,k210-otp";
+				reg = <0x50420000 0x100>,
+				      <0x88000000 0x20000>;
+				reg-names = "reg", "mem";
+				clocks = <&sysclk K210_CLK_ROM>;
+				resets = <&sysrst K210_RST_ROM>;
+				read-only;
+				status = "disabled";
+
+				/* Bootloader */
+				firmware@00000 {
+					reg = <0x00000 0xC200>;
+				};
+
+				/*
+				 * config string as described in RISC-V
+				 * privileged spec 1.9
+				 */
+				config-1-9@1c000 {
+					reg = <0x1C000 0x1000>;
+				};
+
+				/*
+				 * Device tree containing only registers,
+				 * interrupts, and cpus
+				 */
+				fdt@1d000 {
+					reg = <0x1D000 0x2000>;
+				};
+
+				/* CPU/ROM credits */
+				credits@1f000 {
+					reg = <0x1F000 0x1000>;
+				};
+			};
+
+			dvp0: camera@50430000 {
+				compatible = "kendryte,k210-dvp";
+				reg = <0x50430000 0x100>;
+				interrupts = <24>;
+				clocks = <&sysclk K210_CLK_DVP>;
+				resets = <&sysrst K210_RST_DVP>;
+				kendryte,sysctl = <&sysctl>;
+				kendryte,misc-offset = <K210_SYSCTL_MISC>;
+				status = "disabled";
+			};
+
+			sysctl: syscon@50440000 {
+				compatible = "kendryte,k210-sysctl",
+					     "syscon", "simple-mfd";
+				reg = <0x50440000 0x100>;
+				reg-io-width = <4>;
+				u-boot,dm-pre-reloc;
+
+				sysclk: clock-controller {
+					#clock-cells = <1>;
+					compatible = "kendryte,k210-clk";
+					clocks = <&in0>;
+					u-boot,dm-pre-reloc;
+				};
+
+				sysrst: reset-controller {
+					compatible = "kendryte,k210-rst",
+						     "syscon-reset";
+					#reset-cells = <1>;
+					regmap = <&sysctl>;
+					offset = <K210_SYSCTL_PERI_RESET>;
+					mask = <0x27FFFFFF>;
+					assert-high = <1>;
+				};
+
+				reboot {
+					compatible = "syscon-reboot";
+					regmap = <&sysctl>;
+					offset = <K210_SYSCTL_SOFT_RESET>;
+					mask = <1>;
+					value = <1>;
+				};
+			};
+
+			aes0: aes@50450000 {
+				compatible = "kendryte,k210-aes";
+				reg = <0x50450000 0x100>;
+				clocks = <&sysclk K210_CLK_AES>;
+				resets = <&sysrst K210_RST_AES>;
+				status = "disabled";
+			};
+
+			rtc: rtc@50460000 {
+				compatible = "kendryte,k210-rtc";
+				reg = <0x50460000 0x100>;
+				clocks = <&in0>;
+				resets = <&sysrst K210_RST_RTC>;
+				interrupts = <20>;
+				status = "disabled";
+			};
+		};
+
+		apb2: bus@52000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "kendryte,k210-apb", "simple-pm-bus";
+			ranges;
+			clocks = <&sysclk K210_CLK_APB2>;
+
+			spi0: spi@52000000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "canaan,kendryte-k210-spi",
+					     "snps,dw-apb-ssi-4.01",
+					     "snps,dw-apb-ssi";
+				reg = <0x52000000 0x100>;
+				interrupts = <1>;
+				clocks = <&sysclk K210_CLK_SPI0>;
+				clock-names = "ssi_clk";
+				resets = <&sysrst K210_RST_SPI0>;
+				spi-max-frequency = <25000000>;
+				num-cs = <4>;
+				reg-io-width = <4>;
+				status = "disabled";
+			};
+
+			spi1: spi@53000000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "canaan,kendryte-k210-spi",
+					     "snps,dw-apb-ssi-4.01",
+					     "snps,dw-apb-ssi";
+				reg = <0x53000000 0x100>;
+				interrupts = <2>;
+				clocks = <&sysclk K210_CLK_SPI1>;
+				clock-names = "ssi_clk";
+				resets = <&sysrst K210_RST_SPI1>;
+				spi-max-frequency = <25000000>;
+				num-cs = <4>;
+				reg-io-width = <4>;
+				status = "disabled";
+			};
+
+			spi3: spi@54000000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "canaan,kendryte-k210-ssi",
+					     "snps,dwc-ssi-1.01a";
+				reg = <0x54000000 0x200>;
+				interrupts = <4>;
+				clocks = <&sysclk K210_CLK_SPI3>;
+				clock-names = "ssi_clk";
+				resets = <&sysrst K210_RST_SPI3>;
+				/* Could possibly go up to 200 MHz */
+				spi-max-frequency = <100000000>;
+				num-cs = <4>;
+				reg-io-width = <4>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/roms/u-boot/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi b/roms/u-boot/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
new file mode 100644
index 000000000..f60283fb6
--- /dev/null
+++ b/roms/u-boot/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2020 Microchip Technology Inc.
+ * Padmarao Begari <padmarao.begari@microchip.com>
+ */
+
+/ {
+	aliases {
+		cpu1 = &cpu1;
+		cpu2 = &cpu2;
+		cpu3 = &cpu3;
+		cpu4 = &cpu4;
+	};
+};
diff --git a/roms/u-boot/arch/riscv/dts/microchip-mpfs-icicle-kit.dts b/roms/u-boot/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
new file mode 100644
index 000000000..89c4cf5fb
--- /dev/null
+++ b/roms/u-boot/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
@@ -0,0 +1,417 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 Microchip Technology Inc */
+
+/dts-v1/;
+#include "dt-bindings/clock/microchip-mpfs-clock.h"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define RTCCLK_FREQ		1000000
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "Microchip MPFS Icicle Kit";
+	compatible = "microchip,mpfs-icicle-kit";
+
+	aliases {
+		serial0 = &uart0;
+		ethernet0 = &emac1;
+	};
+
+	chosen {
+		stdout-path = "serial0";
+	};
+
+	cpucomplex: cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <RTCCLK_FREQ>;
+		cpu0: cpu@0 {
+			clocks = <&clkcfg CLK_CPU>;
+			compatible = "sifive,e51", "sifive,rocket0", "riscv";
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <16384>;
+			reg = <0>;
+			riscv,isa = "rv64imac";
+			status = "disabled";
+			operating-points = <
+				/* kHz	uV */
+				600000  1100000
+				300000   950000
+				150000   750000
+			>;
+			cpu0intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		cpu1: cpu@1 {
+			clocks = <&clkcfg CLK_CPU>;
+			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			reg = <1>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+			status = "okay";
+			operating-points = <
+				/* kHz	uV */
+				600000  1100000
+				300000   950000
+				150000   750000
+			>;
+			cpu1intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		cpu2: cpu@2 {
+			clocks = <&clkcfg CLK_CPU>;
+			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			reg = <2>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+			status = "okay";
+			operating-points = <
+				/* kHz	uV */
+				600000  1100000
+				300000   950000
+				150000   750000
+			>;
+			cpu2intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		cpu3: cpu@3 {
+			clocks = <&clkcfg CLK_CPU>;
+			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			reg = <3>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+			status = "okay";
+			operating-points = <
+				/* kHz	uV */
+				600000  1100000
+				300000   950000
+				150000   750000
+			>;
+			cpu3intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		cpu4: cpu@4 {
+			clocks = <&clkcfg CLK_CPU>;
+			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			reg = <4>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+			status = "okay";
+			operating-points = <
+				/* kHz	uV */
+				600000  1100000
+				300000   950000
+				150000   750000
+			>;
+			cpu4intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+	refclk: refclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <600000000>;
+		clock-output-names = "msspllclk";
+	};
+	ddr: memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x40000000>;
+		clocks = <&clkcfg CLK_DDRC>;
+	};
+	soc: soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "microchip,mpfs-icicle-kit", "simple-bus";
+		ranges;
+		clint0: clint@2000000 {
+			compatible = "riscv,clint0";
+			interrupts-extended = <&cpu0intc 3 &cpu0intc 7
+						&cpu1intc 3 &cpu1intc 7
+						&cpu2intc 3 &cpu2intc 7
+						&cpu3intc 3 &cpu3intc 7
+						&cpu4intc 3 &cpu4intc 7>;
+			reg = <0x0 0x2000000 0x0 0x10000>;
+			reg-names = "control";
+			clock-frequency = <RTCCLK_FREQ>;
+		};
+		cachecontroller: cache-controller@2010000 {
+			compatible = "sifive,fu540-c000-ccache", "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <1024>;
+			cache-size = <2097152>;
+			cache-unified;
+			interrupt-parent = <&plic>;
+			interrupts = <1 2 3>;
+			reg = <0x0 0x2010000 0x0 0x1000>;
+		};
+		plic: interrupt-controller@c000000 {
+			#interrupt-cells = <1>;
+			compatible = "sifive,plic-1.0.0";
+			reg = <0x0 0xc000000 0x0 0x4000000>;
+			riscv,max-priority = <7>;
+			riscv,ndev = <186>;
+			interrupt-controller;
+			interrupts-extended = <
+				&cpu0intc 11
+				&cpu1intc 11 &cpu1intc 9
+				&cpu2intc 11 &cpu2intc 9
+				&cpu3intc 11 &cpu3intc 9
+				&cpu4intc 11 &cpu4intc 9>;
+		};
+		uart0: serial@20000000 {
+			compatible = "ns16550a";
+			reg = <0x0 0x20000000 0x0 0x400>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			interrupt-parent = <&plic>;
+			interrupts = <90>;
+			clocks = <&clkcfg CLK_MMUART0>;
+			status = "okay";
+		};
+		clkcfg: clkcfg@20002000 {
+			compatible = "microchip,mpfs-clkcfg";
+			reg = <0x0 0x20002000 0x0 0x1000>;
+			reg-names = "mss_sysreg";
+			clocks = <&refclk>;
+			#clock-cells = <1>;
+			clock-output-names = "cpu", "axi", "ahb", "envm",
+					"mac0", "mac1", "mmc", "timer",
+					"mmuart0", "mmuart1", "mmuart2",
+					"mmuart3", "mmuart4", "spi0", "spi1",
+					"i2c0",	"i2c1", "can0", "can1", "usb",
+					"reserved", "rtc", "qspi", "gpio0",
+					"gpio1", "gpio2", "ddrc", "fic0",
+					"fic1", "fic2", "fic3", "athena",
+					"cfm";
+		};
+		emmc: mmc@20008000 {
+			compatible = "cdns,sd4hc";
+			reg = <0x0 0x20008000 0x0 0x1000>;
+			interrupt-parent = <&plic>;
+			interrupts = <88 89>;
+			pinctrl-names = "default";
+			clocks = <&clkcfg CLK_MMC>;
+			bus-width = <4>;
+			cap-mmc-highspeed;
+			mmc-ddr-3_3v;
+			max-frequency = <200000000>;
+			non-removable;
+			no-sd;
+			no-sdio;
+			voltage-ranges = <3300 3300>;
+			status = "okay";
+		};
+		sdcard: sd@20008000 {
+			compatible = "cdns,sd4hc";
+			reg = <0x0 0x20008000 0x0 0x1000>;
+			interrupt-parent = <&plic>;
+			interrupts = <88>;
+			pinctrl-names = "default";
+			clocks = <&clkcfg CLK_MMC>;
+			bus-width = <4>;
+			disable-wp;
+			cap-sd-highspeed;
+			card-detect-delay = <200>;
+			sd-uhs-sdr12;
+			sd-uhs-sdr25;
+			sd-uhs-sdr50;
+			sd-uhs-sdr104;
+			max-frequency = <200000000>;
+			status = "disabled";
+		};
+		uart1: serial@20100000 {
+			compatible = "ns16550a";
+			reg = <0x0 0x20100000 0x0 0x400>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			interrupt-parent = <&plic>;
+			interrupts = <91>;
+			clocks = <&clkcfg CLK_MMUART1>;
+			status = "okay";
+		};
+		uart2: serial@20102000 {
+			compatible = "ns16550a";
+			reg = <0x0 0x20102000 0x0 0x400>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			interrupt-parent = <&plic>;
+			interrupts = <92>;
+			clocks = <&clkcfg CLK_MMUART2>;
+			status = "okay";
+		};
+		uart3: serial@20104000 {
+			compatible = "ns16550a";
+			reg = <0x0 0x20104000 0x0 0x400>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			interrupt-parent = <&plic>;
+			interrupts = <93>;
+			clocks = <&clkcfg CLK_MMUART3>;
+			status = "okay";
+		};
+		i2c0: i2c@2010a000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "microchip,mpfs-mss-i2c";
+			reg = <0x0 0x2010a000 0x0 0x1000>;
+			interrupt-parent = <&plic>;
+			interrupts = <58>;
+			clocks = <&clkcfg CLK_I2C0>;
+			status = "disabled";
+		};
+		i2c1: i2c@2010b000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "microchip,mpfs-mss-i2c";
+			reg = <0x0 0x2010b000 0x0 0x1000>;
+			interrupt-parent = <&plic>;
+			interrupts = <61>;
+			clocks = <&clkcfg CLK_I2C1>;
+			status = "disabled";
+			pac193x@10 {
+				compatible = "microchip,pac1934";
+				reg = <0x10>;
+				samp-rate = <64>;
+				status = "disabled";
+				ch1: channel0 {
+					uohms-shunt-res = <10000>;
+					rail-name = "VDD";
+					channel_enabled;
+				};
+				ch2: channel1 {
+					uohms-shunt-res = <10000>;
+					rail-name = "VDDA25";
+					channel_enabled;
+				};
+				ch3: channel2 {
+					uohms-shunt-res = <10000>;
+					rail-name = "VDD25";
+					channel_enabled;
+				};
+				ch4: channel3 {
+					uohms-shunt-res = <10000>;
+					rail-name = "VDDA";
+					channel_enabled;
+				};
+			};
+		};
+		emac0: ethernet@20110000 {
+			compatible = "microchip,mpfs-mss-gem";
+			reg = <0x0 0x20110000 0x0 0x2000>;
+			interrupt-parent = <&plic>;
+			interrupts = <64 65 66 67>;
+			local-mac-address = [56 34 00 FC 00 02];
+			phy-mode = "sgmii";
+			clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AXI>;
+			clock-names = "pclk", "hclk";
+			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+			phy-handle = <&phy0>;
+			phy0: ethernet-phy@8 {
+				reg = <8>;
+				ti,fifo-depth = <0x01>;
+			};
+		};
+		emac1: ethernet@20112000 {
+			compatible = "microchip,mpfs-mss-gem";
+			reg = <0x0 0x20112000 0x0 0x2000>;
+			interrupt-parent = <&plic>;
+			interrupts = <70 71 72 73>;
+			local-mac-address = [00 00 00 00 00 00];
+			phy-mode = "sgmii";
+			clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
+			clock-names = "pclk", "hclk";
+			status = "okay";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+			phy-handle = <&phy1>;
+			phy1: ethernet-phy@9 {
+				reg = <9>;
+				ti,fifo-depth = <0x01>;
+			};
+		};
+		gpio: gpio@20122000 {
+			compatible = "microchip,mpfs-mss-gpio";
+			interrupt-parent = <&plic>;
+			interrupts = <13 14 15 16 17 18 19 20 21 22 23 24 25 26
+					27 28 29 30 31 32 33 34 35 36 37 38 39
+					40 41 42 43 44>;
+			gpio-controller;
+			clocks = <&clkcfg CLK_GPIO2>;
+			reg = <0x00 0x20122000 0x0 0x1000>;
+			reg-names = "control";
+			#gpio-cells = <2>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/roms/u-boot/arch/riscv/dts/qemu-virt.dts b/roms/u-boot/arch/riscv/dts/qemu-virt.dts
new file mode 100644
index 000000000..fecff542b
--- /dev/null
+++ b/roms/u-boot/arch/riscv/dts/qemu-virt.dts
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "binman.dtsi"
diff --git a/roms/u-boot/arch/riscv/include/asm/arch-fu540/cache.h b/roms/u-boot/arch/riscv/include/asm/arch-fu540/cache.h
new file mode 100644
index 000000000..135a17c67
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/arch-fu540/cache.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 SiFive, Inc.
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel@sifve.com>
+ */
+
+#ifndef _CACHE_SIFIVE_H
+#define _CACHE_SIFIVE_H
+
+int cache_enable_ways(void);
+
+#endif /* _CACHE_SIFIVE_H */
diff --git a/roms/u-boot/arch/riscv/include/asm/arch-fu540/clk.h b/roms/u-boot/arch/riscv/include/asm/arch-fu540/clk.h
new file mode 100644
index 000000000..d71ed4357
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/arch-fu540/clk.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020 SiFive Inc
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#ifndef __CLK_SIFIVE_H
+#define __CLK_SIFIVE_H
+
+/* Note: This is a placeholder header for driver compilation. */
+
+#endif
diff --git a/roms/u-boot/arch/riscv/include/asm/arch-fu540/gpio.h b/roms/u-boot/arch/riscv/include/asm/arch-fu540/gpio.h
new file mode 100644
index 000000000..b87282b97
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/arch-fu540/gpio.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 SiFive, Inc.
+ */
+
+#ifndef _GPIO_SIFIVE_H
+#define _GPIO_SIFIVE_H
+
+#define GPIO_INPUT_VAL	0x00
+#define GPIO_INPUT_EN	0x04
+#define GPIO_OUTPUT_EN	0x08
+#define GPIO_OUTPUT_VAL	0x0C
+#define GPIO_RISE_IE	0x18
+#define GPIO_RISE_IP	0x1C
+#define GPIO_FALL_IE	0x20
+#define GPIO_FALL_IP	0x24
+#define GPIO_HIGH_IE	0x28
+#define GPIO_HIGH_IP	0x2C
+#define GPIO_LOW_IE	0x30
+#define GPIO_LOW_IP	0x34
+#define GPIO_OUTPUT_XOR	0x40
+
+#define NR_GPIOS	16
+
+enum gpio_state {
+	LOW,
+	HIGH
+};
+
+/* Details about a GPIO bank */
+struct sifive_gpio_plat {
+	void *base;     /* address of registers in physical memory */
+};
+
+#define SIFIVE_GENERIC_GPIO_NR(port, index) \
+		(((port) * NR_GPIOS) + ((index) & (NR_GPIOS - 1)))
+
+#endif /* _GPIO_SIFIVE_H */
diff --git a/roms/u-boot/arch/riscv/include/asm/arch-fu540/reset.h b/roms/u-boot/arch/riscv/include/asm/arch-fu540/reset.h
new file mode 100644
index 000000000..e42797a39
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/arch-fu540/reset.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020 SiFive, Inc.
+ *
+ * Author: Sagar Kadam <sagar.kadam@sifive.com>
+ */
+
+#ifndef __RESET_SIFIVE_H
+#define __RESET_SIFIVE_H
+
+int sifive_reset_bind(struct udevice *dev, ulong count);
+
+#endif
diff --git a/roms/u-boot/arch/riscv/include/asm/arch-fu540/spl.h b/roms/u-boot/arch/riscv/include/asm/arch-fu540/spl.h
new file mode 100644
index 000000000..4697279f4
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/arch-fu540/spl.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 SiFive, Inc.
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel@sifve.com>
+ */
+
+#ifndef _SPL_SIFIVE_H
+#define _SPL_SIFIVE_H
+
+int spl_soc_init(void);
+
+#endif /* _SPL_SIFIVE_H */
diff --git a/roms/u-boot/arch/riscv/include/asm/arch-fu740/cache.h b/roms/u-boot/arch/riscv/include/asm/arch-fu740/cache.h
new file mode 100644
index 000000000..7d4fe9942
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/arch-fu740/cache.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020-2021 SiFive, Inc.
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel@sifve.com>
+ */
+
+#ifndef _CACHE_SIFIVE_H
+#define _CACHE_SIFIVE_H
+
+int cache_enable_ways(void);
+
+#endif /* _CACHE_SIFIVE_H */
diff --git a/roms/u-boot/arch/riscv/include/asm/arch-fu740/clk.h b/roms/u-boot/arch/riscv/include/asm/arch-fu740/clk.h
new file mode 100644
index 000000000..9f883616b
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/arch-fu740/clk.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020-2021 SiFive Inc
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#ifndef __CLK_SIFIVE_H
+#define __CLK_SIFIVE_H
+
+/* Note: This is a placeholder header for driver compilation. */
+
+#endif
diff --git a/roms/u-boot/arch/riscv/include/asm/arch-fu740/gpio.h b/roms/u-boot/arch/riscv/include/asm/arch-fu740/gpio.h
new file mode 100644
index 000000000..908e2e556
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/arch-fu740/gpio.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020-2021 SiFive, Inc.
+ */
+
+#ifndef _GPIO_SIFIVE_H
+#define _GPIO_SIFIVE_H
+
+#define GPIO_INPUT_VAL	0x00
+#define GPIO_INPUT_EN	0x04
+#define GPIO_OUTPUT_EN	0x08
+#define GPIO_OUTPUT_VAL	0x0C
+#define GPIO_RISE_IE	0x18
+#define GPIO_RISE_IP	0x1C
+#define GPIO_FALL_IE	0x20
+#define GPIO_FALL_IP	0x24
+#define GPIO_HIGH_IE	0x28
+#define GPIO_HIGH_IP	0x2C
+#define GPIO_LOW_IE	0x30
+#define GPIO_LOW_IP	0x34
+#define GPIO_OUTPUT_XOR	0x40
+
+#define NR_GPIOS	16
+
+enum gpio_state {
+	LOW,
+	HIGH
+};
+
+/* Details about a GPIO bank */
+struct sifive_gpio_plat {
+	void *base;     /* address of registers in physical memory */
+};
+
+#define SIFIVE_GENERIC_GPIO_NR(port, index) \
+		(((port) * NR_GPIOS) + ((index) & (NR_GPIOS - 1)))
+
+#endif /* _GPIO_SIFIVE_H */
diff --git a/roms/u-boot/arch/riscv/include/asm/arch-fu740/reset.h b/roms/u-boot/arch/riscv/include/asm/arch-fu740/reset.h
new file mode 100644
index 000000000..538ef8741
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/arch-fu740/reset.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020-2021 SiFive, Inc.
+ *
+ * Author: Sagar Kadam <sagar.kadam@sifive.com>
+ */
+
+#ifndef __RESET_SIFIVE_H
+#define __RESET_SIFIVE_H
+
+int sifive_reset_bind(struct udevice *dev, ulong count);
+
+#endif
diff --git a/roms/u-boot/arch/riscv/include/asm/arch-fu740/spl.h b/roms/u-boot/arch/riscv/include/asm/arch-fu740/spl.h
new file mode 100644
index 000000000..15ad9e7c8
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/arch-fu740/spl.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020-2021 SiFive, Inc.
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel@sifve.com>
+ */
+
+#ifndef _SPL_SIFIVE_H
+#define _SPL_SIFIVE_H
+
+int spl_soc_init(void);
+
+#endif /* _SPL_SIFIVE_H */
diff --git a/roms/u-boot/arch/riscv/include/asm/arch-generic/clk.h b/roms/u-boot/arch/riscv/include/asm/arch-generic/clk.h
new file mode 100644
index 000000000..1631f5f0b
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/arch-generic/clk.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __ASM_RISCV_ARCH_CLK_H
+#define __ASM_RISCV_ARCH_CLK_H
+
+/* Note: This is a placeholder header for driver compilation. */
+
+#endif
diff --git a/roms/u-boot/arch/riscv/include/asm/arch-generic/gpio.h b/roms/u-boot/arch/riscv/include/asm/arch-generic/gpio.h
new file mode 100644
index 000000000..b1f403027
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/arch-generic/gpio.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 SiFive, Inc.
+ */
+
+#ifndef _GPIO_SIFIVE_H
+#define _GPIO_SIFIVE_H
+
+#define GPIO_INPUT_VAL	0x00
+#define GPIO_INPUT_EN	0x04
+#define GPIO_OUTPUT_EN	0x08
+#define GPIO_OUTPUT_VAL	0x0C
+#define GPIO_RISE_IE	0x18
+#define GPIO_RISE_IP	0x1C
+#define GPIO_FALL_IE	0x20
+#define GPIO_FALL_IP	0x24
+#define GPIO_HIGH_IE	0x28
+#define GPIO_HIGH_IP	0x2C
+#define GPIO_LOW_IE	0x30
+#define GPIO_LOW_IP	0x34
+#define GPIO_OUTPUT_XOR	0x40
+
+#define NR_GPIOS	16
+
+enum gpio_state {
+	LOW,
+	HIGH
+};
+
+/* Details about a GPIO bank */
+struct sifive_gpio_plat {
+	void *base;     /* address of registers in physical memory */
+};
+
+#endif /* _GPIO_SIFIVE_H */
diff --git a/roms/u-boot/arch/riscv/include/asm/asm.h b/roms/u-boot/arch/riscv/include/asm/asm.h
new file mode 100644
index 000000000..5a02b7d50
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/asm.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2015 Regents of the University of California
+ */
+
+#ifndef _ASM_RISCV_ASM_H
+#define _ASM_RISCV_ASM_H
+
+#ifdef __ASSEMBLY__
+#define __ASM_STR(x)	x
+#else
+#define __ASM_STR(x)	#x
+#endif
+
+#if __riscv_xlen == 64
+#define __REG_SEL(a, b)	__ASM_STR(a)
+#elif __riscv_xlen == 32
+#define __REG_SEL(a, b)	__ASM_STR(b)
+#else
+#error "Unexpected __riscv_xlen"
+#endif
+
+#define REG_L		__REG_SEL(ld, lw)
+#define REG_S		__REG_SEL(sd, sw)
+#define SZREG		__REG_SEL(8, 4)
+#define LGREG		__REG_SEL(3, 2)
+
+#if __SIZEOF_POINTER__ == 8
+#ifdef __ASSEMBLY__
+#define RISCV_PTR		.dword
+#define RISCV_SZPTR		8
+#define RISCV_LGPTR		3
+#else
+#define RISCV_PTR		".dword"
+#define RISCV_SZPTR		"8"
+#define RISCV_LGPTR		"3"
+#endif
+#elif __SIZEOF_POINTER__ == 4
+#ifdef __ASSEMBLY__
+#define RISCV_PTR		.word
+#define RISCV_SZPTR		4
+#define RISCV_LGPTR		2
+#else
+#define RISCV_PTR		".word"
+#define RISCV_SZPTR		"4"
+#define RISCV_LGPTR		"2"
+#endif
+#else
+#error "Unexpected __SIZEOF_POINTER__"
+#endif
+
+#if (__SIZEOF_INT__ == 4)
+#define RISCV_INT		__ASM_STR(.word)
+#define RISCV_SZINT		__ASM_STR(4)
+#define RISCV_LGINT		__ASM_STR(2)
+#else
+#error "Unexpected __SIZEOF_INT__"
+#endif
+
+#if (__SIZEOF_SHORT__ == 2)
+#define RISCV_SHORT		__ASM_STR(.half)
+#define RISCV_SZSHORT		__ASM_STR(2)
+#define RISCV_LGSHORT		__ASM_STR(1)
+#else
+#error "Unexpected __SIZEOF_SHORT__"
+#endif
+
+#endif /* _ASM_RISCV_ASM_H */
diff --git a/roms/u-boot/arch/riscv/include/asm/barrier.h b/roms/u-boot/arch/riscv/include/asm/barrier.h
new file mode 100644
index 000000000..a3f60a845
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/barrier.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ * Copyright (C) 2013 Regents of the University of California
+ * Copyright (C) 2017 SiFive
+ *
+ * Taken from Linux arch/riscv/include/asm/barrier.h, which is based on
+ * arch/arm/include/asm/barrier.h
+ */
+
+#ifndef _ASM_RISCV_BARRIER_H
+#define _ASM_RISCV_BARRIER_H
+
+#ifndef __ASSEMBLY__
+
+#define nop()		__asm__ __volatile__ ("nop")
+
+#define RISCV_FENCE(p, s) \
+	__asm__ __volatile__ ("fence " #p "," #s : : : "memory")
+
+/* These barriers need to enforce ordering on both devices or memory. */
+#define mb()		RISCV_FENCE(iorw,iorw)
+#define rmb()		RISCV_FENCE(ir,ir)
+#define wmb()		RISCV_FENCE(ow,ow)
+
+/* These barriers do not need to enforce ordering on devices, just memory. */
+#define __smp_mb()	RISCV_FENCE(rw,rw)
+#define __smp_rmb()	RISCV_FENCE(r,r)
+#define __smp_wmb()	RISCV_FENCE(w,w)
+
+#define __smp_store_release(p, v)					\
+do {									\
+	compiletime_assert_atomic_type(*p);				\
+	RISCV_FENCE(rw,w);						\
+	WRITE_ONCE(*p, v);						\
+} while (0)
+
+#define __smp_load_acquire(p)						\
+({									\
+	typeof(*p) ___p1 = READ_ONCE(*p);				\
+	compiletime_assert_atomic_type(*p);				\
+	RISCV_FENCE(r,rw);						\
+	___p1;								\
+})
+
+/*
+ * This is a very specific barrier: it's currently only used in two places in
+ * the kernel, both in the scheduler.  See include/linux/spinlock.h for the two
+ * orderings it guarantees, but the "critical section is RCsc" guarantee
+ * mandates a barrier on RISC-V.  The sequence looks like:
+ *
+ *    lr.aq lock
+ *    sc    lock <= LOCKED
+ *    smp_mb__after_spinlock()
+ *    // critical section
+ *    lr    lock
+ *    sc.rl lock <= UNLOCKED
+ *
+ * The AQ/RL pair provides a RCpc critical section, but there's not really any
+ * way we can take advantage of that here because the ordering is only enforced
+ * on that one lock.  Thus, we're just doing a full fence.
+ */
+#define smp_mb__after_spinlock()	RISCV_FENCE(rw,rw)
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_RISCV_BARRIER_H */
diff --git a/roms/u-boot/arch/riscv/include/asm/bitops.h b/roms/u-boot/arch/riscv/include/asm/bitops.h
new file mode 100644
index 000000000..536629bbe
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/bitops.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright 1995, Russell King.
+ * Various bits and pieces copyrights include:
+ * Linus Torvalds (test_bit).
+ *
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ *
+ * Please note that the code in this file should never be included
+ * from user space.  Many of these are not implemented in assembler
+ * since they would be too costly.  Also, they require priviledged
+ * instructions (which are not available from user mode) to ensure
+ * that they are atomic.
+ */
+
+#ifndef __ASM_RISCV_BITOPS_H
+#define __ASM_RISCV_BITOPS_H
+
+#ifdef __KERNEL__
+
+#include <asm/system.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
+
+#define smp_mb__before_clear_bit()	do { } while (0)
+#define smp_mb__after_clear_bit()	do { } while (0)
+
+/*
+ * Function prototypes to keep gcc -Wall happy.
+ */
+static inline void __set_bit(int nr, void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	*a |= mask;
+}
+
+#define PLATFORM__SET_BIT
+
+static inline void __clear_bit(int nr, void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	*a &= ~mask;
+}
+
+#define PLATFORM__CLEAR_BIT
+
+static inline void __change_bit(int nr, void *addr)
+{
+	int mask;
+	unsigned long *ADDR = (unsigned long *)addr;
+
+	ADDR += nr >> 5;
+	mask = 1 << (nr & 31);
+	*ADDR ^= mask;
+}
+
+static inline int __test_and_set_bit(int nr, void *addr)
+{
+	int mask, retval;
+	unsigned int *a = (unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	return retval;
+}
+
+static inline int __test_and_clear_bit(int nr, void *addr)
+{
+	int mask, retval;
+	unsigned int *a = (unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	return retval;
+}
+
+static inline int __test_and_change_bit(int nr, void *addr)
+{
+	int mask, retval;
+	unsigned int *a = (unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	return retval;
+}
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static inline int test_bit(int nr, const void *addr)
+{
+	return ((unsigned char *)addr)[nr >> 3] & (1U << (nr & 7));
+}
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+	int k;
+
+	word = ~word;
+	k = 31;
+	if (word & 0x0000ffff) {
+		k -= 16; word <<= 16;
+	}
+	if (word & 0x00ff0000) {
+		k -= 8;  word <<= 8;
+	}
+	if (word & 0x0f000000) {
+		k -= 4;  word <<= 4;
+	}
+	if (word & 0x30000000) {
+		k -= 2;  word <<= 2;
+	}
+	if (word & 0x40000000)
+		k -= 1;
+
+	return k;
+}
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+/*
+ * redefined in include/linux/bitops.h
+ * #define ffs(x) generic_ffs(x)
+ */
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#define ext2_set_bit			test_and_set_bit
+#define ext2_clear_bit			test_and_clear_bit
+#define ext2_test_bit			test_bit
+#define ext2_find_first_zero_bit	find_first_zero_bit
+#define ext2_find_next_zero_bit		find_next_zero_bit
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr, addr)	test_and_set_bit(nr, addr)
+#define minix_set_bit(nr, addr)			set_bit(nr, addr)
+#define minix_test_and_clear_bit(nr, addr)	test_and_clear_bit(nr, addr)
+#define minix_test_bit(nr, addr)		test_bit(nr, addr)
+#define minix_find_first_zero_bit(addr, size)	find_first_zero_bit(addr, size)
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_RISCV_BITOPS_H */
diff --git a/roms/u-boot/arch/riscv/include/asm/byteorder.h b/roms/u-boot/arch/riscv/include/asm/byteorder.h
new file mode 100644
index 000000000..d26ac5688
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/byteorder.h
@@ -0,0 +1,35 @@
+/*
+ *  linux/include/asm-arm/byteorder.h
+ *
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * ARM Endian-ness.  In little endian mode, the data bus is connected such
+ * that byte accesses appear as:
+ *  0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ *
+ * When in big endian mode, byte accesses appear as:
+ *  0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ */
+
+#ifndef __ASM_RISCV_BYTEORDER_H
+#define __ASM_RISCV_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __RISCVEB__
+#include <linux/byteorder/big_endian.h>
+#else
+#include <linux/byteorder/little_endian.h>
+#endif
+
+#endif
diff --git a/roms/u-boot/arch/riscv/include/asm/cache.h b/roms/u-boot/arch/riscv/include/asm/cache.h
new file mode 100644
index 000000000..ec8fe201d
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/cache.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#ifndef _ASM_RISCV_CACHE_H
+#define _ASM_RISCV_CACHE_H
+
+/* cache */
+void	cache_flush(void);
+
+/*
+ * The current upper bound for RISCV L1 data cache line sizes is 32 bytes.
+ * We use that value for aligning DMA buffers unless the board config has
+ * specified an alternate cache line size.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN	32
+#endif
+
+#endif /* _ASM_RISCV_CACHE_H */
diff --git a/roms/u-boot/arch/riscv/include/asm/config.h b/roms/u-boot/arch/riscv/include/asm/config.h
new file mode 100644
index 000000000..d91100753
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/config.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
+#endif
diff --git a/roms/u-boot/arch/riscv/include/asm/csr.h b/roms/u-boot/arch/riscv/include/asm/csr.h
new file mode 100644
index 000000000..1a15089ca
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/csr.h
@@ -0,0 +1,211 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2015 Regents of the University of California
+ *
+ * Taken from Linux arch/riscv/include/asm/csr.h
+ */
+
+#ifndef _ASM_RISCV_CSR_H
+#define _ASM_RISCV_CSR_H
+
+#include <asm/asm.h>
+#include <linux/const.h>
+
+/* Status register flags */
+#define SR_SIE		_AC(0x00000002, UL) /* Supervisor Interrupt Enable */
+#define SR_SPIE		_AC(0x00000020, UL) /* Previous Supervisor IE */
+#define SR_SPP		_AC(0x00000100, UL) /* Previously Supervisor */
+#ifdef CONFIG_RISCV_PRIV_1_9
+#define SR_PUM		_AC(0x00040000, UL) /* Protect User Memory Access */
+#else
+#define SR_SUM		_AC(0x00040000, UL) /* Supervisor User Memory Access */
+#endif
+
+#define SR_FS		_AC(0x00006000, UL) /* Floating-point Status */
+#define SR_FS_OFF	_AC(0x00000000, UL)
+#define SR_FS_INITIAL	_AC(0x00002000, UL)
+#define SR_FS_CLEAN	_AC(0x00004000, UL)
+#define SR_FS_DIRTY	_AC(0x00006000, UL)
+
+#define SR_XS		_AC(0x00018000, UL) /* Extension Status */
+#define SR_XS_OFF	_AC(0x00000000, UL)
+#define SR_XS_INITIAL	_AC(0x00008000, UL)
+#define SR_XS_CLEAN	_AC(0x00010000, UL)
+#define SR_XS_DIRTY	_AC(0x00018000, UL)
+
+#ifdef CONFIG_RISCV_PRIV_1_9
+#define SR_VM		_AC(0x1F000000, UL) /* Virtualization Management */
+#define SR_VM_MODE_BARE	_AC(0x00000000, UL) /* No translation or protection */
+#define SR_VM_MODE_BB	_AC(0x01000000, UL) /* Single base-and-bound */
+/* Separate instruction and data base-and-bound */
+#define SR_VM_MODE_BBID	_AC(0x02000000, UL)
+#ifndef CONFIG_64BIT
+#define SR_VM_MODE_32	_AC(0x08000000, UL)
+#define SR_VM_MODE	SR_VM_MODE_32
+#else
+#define SR_VM_MODE_39	_AC(0x09000000, UL)
+#define SR_VM_MODE_48	_AC(0x0A000000, UL)
+#define SR_VM_MODE	SR_VM_MODE_39
+#endif
+#endif
+
+#ifndef CONFIG_64BIT
+#define SR_SD		_AC(0x80000000, UL) /* FS/XS dirty */
+#else
+#define SR_SD		_AC(0x8000000000000000, UL) /* FS/XS dirty */
+#endif
+
+/* SATP flags */
+#ifndef CONFIG_RISCV_PRIV_1_9
+#ifndef CONFIG_64BIT
+#define SATP_PPN	_AC(0x003FFFFF, UL)
+#define SATP_MODE_32	_AC(0x80000000, UL)
+#define SATP_MODE	SATP_MODE_32
+#else
+#define SATP_PPN	_AC(0x00000FFFFFFFFFFF, UL)
+#define SATP_MODE_39	_AC(0x8000000000000000, UL)
+#define SATP_MODE	SATP_MODE_39
+#endif
+#endif
+
+/* SCAUSE */
+#define SCAUSE_IRQ_FLAG		(_AC(1, UL) << (__riscv_xlen - 1))
+
+#define IRQ_U_SOFT		0
+#define IRQ_S_SOFT		1
+#define IRQ_M_SOFT		3
+#define IRQ_U_TIMER		4
+#define IRQ_S_TIMER		5
+#define IRQ_M_TIMER		7
+#define IRQ_U_EXT		8
+#define IRQ_S_EXT		9
+#define IRQ_M_EXT		11
+
+#define EXC_INST_MISALIGNED	0
+#define EXC_INST_ACCESS		1
+#define EXC_BREAKPOINT		3
+#define EXC_LOAD_ACCESS		5
+#define EXC_STORE_ACCESS	7
+#define EXC_SYSCALL		8
+#define EXC_INST_PAGE_FAULT	12
+#define EXC_LOAD_PAGE_FAULT	13
+#define EXC_STORE_PAGE_FAULT	15
+
+/* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */
+#define MIE_MSIE		(_AC(0x1, UL) << IRQ_M_SOFT)
+#define SIE_SSIE		(_AC(0x1, UL) << IRQ_S_SOFT)
+#define SIE_STIE		(_AC(0x1, UL) << IRQ_S_TIMER)
+#define SIE_SEIE		(_AC(0x1, UL) << IRQ_S_EXT)
+
+#define CSR_FCSR		0x003
+#define CSR_CYCLE		0xc00
+#define CSR_TIME		0xc01
+#define CSR_INSTRET		0xc02
+#define CSR_SSTATUS		0x100
+#define CSR_SIE			0x104
+#define CSR_STVEC		0x105
+#define CSR_SCOUNTEREN		0x106
+#define CSR_SSCRATCH		0x140
+#define CSR_SEPC		0x141
+#define CSR_SCAUSE		0x142
+#define CSR_STVAL		0x143
+#define CSR_SIP			0x144
+#ifdef CONFIG_RISCV_PRIV_1_9
+#define CSR_SPTBR		0x180
+#else
+#define CSR_SATP		0x180
+#endif
+#define CSR_MSTATUS		0x300
+#define CSR_MISA		0x301
+#define CSR_MIE			0x304
+#define CSR_MTVEC		0x305
+#ifdef CONFIG_RISCV_PRIV_1_9
+#define CSR_MUCOUNTEREN         0x320
+#define CSR_MSCOUNTEREN         0x321
+#define CSR_MHCOUNTEREN         0x322
+#else
+#define CSR_MCOUNTEREN		0x306
+#endif
+#define CSR_MSCRATCH		0x340
+#define CSR_MEPC		0x341
+#define CSR_MCAUSE		0x342
+#define CSR_MTVAL		0x343
+#define CSR_MIP			0x344
+#ifdef CONFIG_RISCV_PRIV_1_9
+#define CSR_MBASE		0x380
+#define CSR_MBOUND		0x381
+#define CSR_MIBASE		0x382
+#define CSR_MIBOUND		0x383
+#define CSR_MDBASE		0x384
+#define CSR_MDBOUND		0x385
+#endif
+#define CSR_CYCLEH		0xc80
+#define CSR_TIMEH		0xc81
+#define CSR_INSTRETH		0xc82
+#define CSR_MHARTID		0xf14
+
+#ifndef __ASSEMBLY__
+
+#define csr_swap(csr, val)					\
+({								\
+	unsigned long __v = (unsigned long)(val);		\
+	__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
+			      : "=r" (__v) : "rK" (__v)		\
+			      : "memory");			\
+	__v;							\
+})
+
+#define csr_read(csr)						\
+({								\
+	register unsigned long __v;				\
+	__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr)	\
+			      : "=r" (__v) :			\
+			      : "memory");			\
+	__v;							\
+})
+
+#define csr_write(csr, val)					\
+({								\
+	unsigned long __v = (unsigned long)(val);		\
+	__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0"	\
+			      : : "rK" (__v)			\
+			      : "memory");			\
+})
+
+#define csr_read_set(csr, val)					\
+({								\
+	unsigned long __v = (unsigned long)(val);		\
+	__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
+			      : "=r" (__v) : "rK" (__v)		\
+			      : "memory");			\
+	__v;							\
+})
+
+#define csr_set(csr, val)					\
+({								\
+	unsigned long __v = (unsigned long)(val);		\
+	__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0"	\
+			      : : "rK" (__v)			\
+			      : "memory");			\
+})
+
+#define csr_read_clear(csr, val)				\
+({								\
+	unsigned long __v = (unsigned long)(val);		\
+	__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
+			      : "=r" (__v) : "rK" (__v)		\
+			      : "memory");			\
+	__v;							\
+})
+
+#define csr_clear(csr, val)					\
+({								\
+	unsigned long __v = (unsigned long)(val);		\
+	__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0"	\
+			      : : "rK" (__v)			\
+			      : "memory");			\
+})
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_RISCV_CSR_H */
diff --git a/roms/u-boot/arch/riscv/include/asm/dma-mapping.h b/roms/u-boot/arch/riscv/include/asm/dma-mapping.h
new file mode 100644
index 000000000..6ecadab41
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/dma-mapping.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2018 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __ASM_RISCV_DMA_MAPPING_H
+#define __ASM_RISCV_DMA_MAPPING_H
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/cache.h>
+#include <cpu_func.h>
+#include <linux/dma-direction.h>
+#include <malloc.h>
+
+static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
+{
+	*handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
+	return (void *)*handle;
+}
+
+static inline void dma_free_coherent(void *addr)
+{
+	free(addr);
+}
+
+#endif /* __ASM_RISCV_DMA_MAPPING_H */
diff --git a/roms/u-boot/arch/riscv/include/asm/encoding.h b/roms/u-boot/arch/riscv/include/asm/encoding.h
new file mode 100644
index 000000000..edafad36b
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/encoding.h
@@ -0,0 +1,162 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Microsemi Corporation.
+ * Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
+ */
+
+#ifndef RISCV_CSR_ENCODING_H
+#define RISCV_CSR_ENCODING_H
+
+#include <asm/csr.h>
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#endif
+
+#if CONFIG_IS_ENABLED(RISCV_SMODE)
+#define MODE_PREFIX(__suffix)	s##__suffix
+#else
+#define MODE_PREFIX(__suffix)	m##__suffix
+#endif
+
+#define MSTATUS_UIE	0x00000001
+#define MSTATUS_SIE	0x00000002
+#define MSTATUS_HIE	0x00000004
+#define MSTATUS_MIE	0x00000008
+#define MSTATUS_UPIE	0x00000010
+#define MSTATUS_SPIE	0x00000020
+#define MSTATUS_HPIE	0x00000040
+#define MSTATUS_MPIE	0x00000080
+#define MSTATUS_SPP	0x00000100
+#define MSTATUS_HPP	0x00000600
+#define MSTATUS_MPP	0x00001800
+#define MSTATUS_FS	0x00006000
+#define MSTATUS_XS	0x00018000
+#define MSTATUS_MPRV	0x00020000
+#define MSTATUS_PUM	0x00040000
+#define MSTATUS_VM	0x1F000000
+#define MSTATUS32_SD	0x80000000
+#define MSTATUS64_SD	0x8000000000000000
+
+#define MCAUSE32_CAUSE	0x7FFFFFFF
+#define MCAUSE64_CAUSE	0x7FFFFFFFFFFFFFFF
+#define MCAUSE32_INT	0x80000000
+#define MCAUSE64_INT	0x8000000000000000
+
+#define SSTATUS_UIE	0x00000001
+#define SSTATUS_SIE	0x00000002
+#define SSTATUS_UPIE	0x00000010
+#define SSTATUS_SPIE	0x00000020
+#define SSTATUS_SPP	0x00000100
+#define SSTATUS_FS	0x00006000
+#define SSTATUS_XS	0x00018000
+#define SSTATUS_PUM	0x00040000
+#define SSTATUS32_SD	0x80000000
+#define SSTATUS64_SD	0x8000000000000000
+
+#define MIP_SSIP	BIT(IRQ_S_SOFT)
+#define MIP_MSIP	BIT(IRQ_M_SOFT)
+#define MIP_STIP	BIT(IRQ_S_TIMER)
+#define MIP_MTIP	BIT(IRQ_M_TIMER)
+#define MIP_SEIP	BIT(IRQ_S_EXT)
+#define MIP_MEIP	BIT(IRQ_M_EXT)
+
+#define SIP_SSIP	MIP_SSIP
+#define SIP_STIP	MIP_STIP
+
+#define PRV_U	0
+#define PRV_S	1
+#define PRV_H	2
+#define PRV_M	3
+
+#define VM_MBARE	0
+#define VM_MBB		1
+#define VM_MBBID	2
+#define VM_SV32		8
+#define VM_SV39		9
+#define VM_SV48		10
+
+#define CAUSE_MISALIGNED_FETCH		0
+#define CAUSE_FETCH_ACCESS		1
+#define CAUSE_ILLEGAL_INSTRUCTION	2
+#define CAUSE_BREAKPOINT		3
+#define CAUSE_MISALIGNED_LOAD		4
+#define CAUSE_LOAD_ACCESS		5
+#define CAUSE_MISALIGNED_STORE		6
+#define CAUSE_STORE_ACCESS		7
+#define CAUSE_USER_ECALL		8
+#define CAUSE_SUPERVISOR_ECALL		9
+#define CAUSE_MACHINE_ECALL		11
+#define CAUSE_FETCH_PAGE_FAULT		12
+#define CAUSE_LOAD_PAGE_FAULT		13
+#define CAUSE_STORE_PAGE_FAULT		15
+
+#define DEFAULT_RSTVEC		0x00001000
+#define DEFAULT_NMIVEC		0x00001004
+#define DEFAULT_MTVEC		0x00001010
+#define CONFIG_STRING_ADDR	0x0000100C
+#define EXT_IO_BASE		0x40000000
+#define DRAM_BASE		0x80000000
+
+// page table entry (PTE) fields
+#define PTE_V		0x001 // Valid
+#define PTE_TYPE	0x01E // Type
+#define PTE_R		0x020 // Referenced
+#define PTE_D		0x040 // Dirty
+#define PTE_SOFT	0x380 // Reserved for Software
+
+#define PTE_TYPE_TABLE		0x00
+#define PTE_TYPE_TABLE_GLOBAL	0x02
+#define PTE_TYPE_URX_SR		0x04
+#define PTE_TYPE_URWX_SRW	0x06
+#define PTE_TYPE_UR_SR		0x08
+#define PTE_TYPE_URW_SRW	0x0A
+#define PTE_TYPE_URX_SRX	0x0C
+#define PTE_TYPE_URWX_SRWX0x0E
+#define PTE_TYPE_SR		0x10
+#define PTE_TYPE_SRW		0x12
+#define PTE_TYPE_SRX		0x14
+#define PTE_TYPE_SRWX		0x16
+#define PTE_TYPE_SR_GLOBAL	0x18
+#define PTE_TYPE_SRW_GLOBAL	0x1A
+#define PTE_TYPE_SRX_GLOBAL	0x1C
+#define PTE_TYPE_SRWX_GLOBAL	0x1E
+
+#define PTE_PPN_SHIFT	10
+
+#define PTE_TABLE(PTE)	((0x0000000AU >> ((PTE) & 0x1F)) & 1)
+#define PTE_UR(PTE)	((0x0000AAA0U >> ((PTE) & 0x1F)) & 1)
+#define PTE_UW(PTE)	((0x00008880U >> ((PTE) & 0x1F)) & 1)
+#define PTE_UX(PTE)	((0x0000A0A0U >> ((PTE) & 0x1F)) & 1)
+#define PTE_SR(PTE)	((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1)
+#define PTE_SW(PTE)	((0x88888880U >> ((PTE) & 0x1F)) & 1)
+#define PTE_SX(PTE)	((0xA0A0A000U >> ((PTE) & 0x1F)) & 1)
+
+#define PTE_CHECK_PERM(_PTE, _SUPERVISOR, STORE, FETCH) \
+	typeof(_PTE) (PTE) = (_PTE); \
+	typeof(_SUPERVISOR) (SUPERVISOR) = (_SUPERVISOR); \
+	((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \
+	(FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \
+	((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
+
+#ifdef __riscv
+
+#ifdef CONFIG_64BIT
+# define MSTATUS_SD MSTATUS64_SD
+# define SSTATUS_SD SSTATUS64_SD
+# define MCAUSE_INT MCAUSE64_INT
+# define MCAUSE_CAUSE MCAUSE64_CAUSE
+# define RISCV_PGLEVEL_BITS 9
+#else
+# define MSTATUS_SD MSTATUS32_SD
+# define SSTATUS_SD SSTATUS32_SD
+# define RISCV_PGLEVEL_BITS 10
+# define MCAUSE_INT MCAUSE32_INT
+# define MCAUSE_CAUSE MCAUSE32_CAUSE
+#endif
+
+#define RISCV_PGSHIFT 12
+#define RISCV_PGSIZE BIT(RISCV_PGSHIFT)
+
+#endif /* __riscv */
+
+#endif /* RISCV_CSR_ENCODING_H */
diff --git a/roms/u-boot/arch/riscv/include/asm/global_data.h b/roms/u-boot/arch/riscv/include/asm/global_data.h
new file mode 100644
index 000000000..095484a63
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/global_data.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (c) 2017 Microsemi Corporation.
+ * Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
+ */
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+
+#include <asm/smp.h>
+#include <asm/u-boot.h>
+#include <compiler.h>
+
+/* Architecture-specific global data */
+struct arch_global_data {
+	long boot_hart;		/* boot hart id */
+	phys_addr_t firmware_fdt_addr;
+#if CONFIG_IS_ENABLED(SIFIVE_CLINT)
+	void __iomem *clint;	/* clint base address */
+#endif
+#ifdef CONFIG_ANDES_PLIC
+	void __iomem *plic;	/* plic base address */
+#endif
+#if CONFIG_IS_ENABLED(SMP)
+	struct ipi_data ipi[CONFIG_NR_CPUS];
+#endif
+#ifndef CONFIG_XIP
+	ulong available_harts;
+#endif
+};
+
+#include <asm-generic/global_data.h>
+
+#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("gp")
+
+static inline void set_gd(volatile gd_t *gd_ptr)
+{
+#ifdef CONFIG_64BIT
+	asm volatile("ld gp, %0\n" : : "m"(gd_ptr));
+#else
+	asm volatile("lw gp, %0\n" : : "m"(gd_ptr));
+#endif
+}
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/roms/u-boot/arch/riscv/include/asm/gpio.h b/roms/u-boot/arch/riscv/include/asm/gpio.h
new file mode 100644
index 000000000..008d75698
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/gpio.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 SiFive, Inc.
+ */
+
+#include <asm-generic/gpio.h>
diff --git a/roms/u-boot/arch/riscv/include/asm/io.h b/roms/u-boot/arch/riscv/include/asm/io.h
new file mode 100644
index 000000000..acf5a9644
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/io.h
@@ -0,0 +1,462 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ */
+#ifndef __ASM_RISCV_IO_H
+#define __ASM_RISCV_IO_H
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <asm/barrier.h>
+#include <asm/byteorder.h>
+
+static inline void sync(void)
+{
+}
+
+#ifdef CONFIG_ARCH_MAP_SYSMEM
+static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
+{
+	if (paddr < PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE)
+		paddr = paddr | 0x40000000;
+	return (void *)(uintptr_t)paddr;
+}
+
+static inline void *unmap_sysmem(const void *vaddr)
+{
+	phys_addr_t paddr = (phys_addr_t)vaddr;
+
+	paddr = paddr & ~0x40000000;
+	return (void *)(uintptr_t)paddr;
+}
+
+static inline phys_addr_t map_to_sysmem(const void *ptr)
+{
+	return (phys_addr_t)(uintptr_t)ptr;
+}
+#endif
+
+/*
+ * Generic virtual read/write.  Note that we don't support half-word
+ * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
+ * to the architecture specific code.
+ */
+#define __arch_getb(a)			(*(unsigned char *)(a))
+#define __arch_getw(a)			(*(unsigned short *)(a))
+#define __arch_getl(a)			(*(unsigned int *)(a))
+#define __arch_getq(a)			(*(unsigned long long *)(a))
+
+#define __arch_putb(v, a)		(*(unsigned char *)(a) = (v))
+#define __arch_putw(v, a)		(*(unsigned short *)(a) = (v))
+#define __arch_putl(v, a)		(*(unsigned int *)(a) = (v))
+#define __arch_putq(v, a)		(*(unsigned long long *)(a) = (v))
+
+#define __raw_writeb(v, a)		__arch_putb(v, a)
+#define __raw_writew(v, a)		__arch_putw(v, a)
+#define __raw_writel(v, a)		__arch_putl(v, a)
+#define __raw_writeq(v, a)		__arch_putq(v, a)
+
+#define __raw_readb(a)			__arch_getb(a)
+#define __raw_readw(a)			__arch_getw(a)
+#define __raw_readl(a)			__arch_getl(a)
+#define __raw_readq(a)			__arch_getq(a)
+
+#define dmb()		mb()
+#define __iormb()	rmb()
+#define __iowmb()	wmb()
+
+static inline void writeb(u8 val, volatile void __iomem *addr)
+{
+	__iowmb();
+	__arch_putb(val, addr);
+}
+
+static inline void writew(u16 val, volatile void __iomem *addr)
+{
+	__iowmb();
+	__arch_putw(val, addr);
+}
+
+static inline void writel(u32 val, volatile void __iomem *addr)
+{
+	__iowmb();
+	__arch_putl(val, addr);
+}
+
+static inline void writeq(u64 val, volatile void __iomem *addr)
+{
+	__iowmb();
+	__arch_putq(val, addr);
+}
+
+static inline u8 readb(const volatile void __iomem *addr)
+{
+	u8	val;
+
+	val = __arch_getb(addr);
+	__iormb();
+	return val;
+}
+
+static inline u16 readw(const volatile void __iomem *addr)
+{
+	u16	val;
+
+	val = __arch_getw(addr);
+	__iormb();
+	return val;
+}
+
+static inline u32 readl(const volatile void __iomem *addr)
+{
+	u32	val;
+
+	val = __arch_getl(addr);
+	__iormb();
+	return val;
+}
+
+static inline u64 readq(const volatile void __iomem *addr)
+{
+	u64	val;
+
+	val = __arch_getq(addr);
+	__iormb();
+	return val;
+}
+
+/*
+ * The compiler seems to be incapable of optimising constants
+ * properly.  Spell it out to the compiler in some cases.
+ * These are only valid for small values of "off" (< 1<<12)
+ */
+#define __raw_base_writeb(val, base, off)	__arch_base_putb(val, base, off)
+#define __raw_base_writew(val, base, off)	__arch_base_putw(val, base, off)
+#define __raw_base_writel(val, base, off)	__arch_base_putl(val, base, off)
+
+#define __raw_base_readb(base, off)	__arch_base_getb(base, off)
+#define __raw_base_readw(base, off)	__arch_base_getw(base, off)
+#define __raw_base_readl(base, off)	__arch_base_getl(base, off)
+
+#define out_arch(type, endian, a, v)	__raw_write##type(cpu_to_##endian(v), a)
+#define in_arch(type, endian, a)	endian##_to_cpu(__raw_read##type(a))
+
+#define out_le32(a, v)			out_arch(l, le32, a, v)
+#define out_le16(a, v)			out_arch(w, le16, a, v)
+
+#define in_le32(a)			in_arch(l, le32, a)
+#define in_le16(a)			in_arch(w, le16, a)
+
+#define out_be32(a, v)			out_arch(l, be32, a, v)
+#define out_be16(a, v)			out_arch(w, be16, a, v)
+
+#define in_be32(a)			in_arch(l, be32, a)
+#define in_be16(a)			in_arch(w, be16, a)
+
+#define out_8(a, v)			__raw_writeb(v, a)
+#define in_8(a)				__raw_readb(a)
+
+/*
+ * Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrbits(type, addr, clear) \
+	out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+	out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
+/*
+ * Now, pick up the machine-defined IO definitions
+ * #include <asm/arch/io.h>
+ */
+
+/*
+ *  IO port access primitives
+ *  -------------------------
+ *
+ * The NDS32 doesn't have special IO access instructions just like ARM;
+ * all IO is memory mapped.
+ * Note that these are defined to perform little endian accesses
+ * only.  Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * Note that for a big endian machine, this implies that the following
+ * big endian mode connectivity is in place, as described by numerious
+ * ARM documents:
+ *
+ *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
+ *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
+ *
+ * The machine specific io.h include defines __io to translate an "IO"
+ * address to a memory address.
+ *
+ * Note that we prevent GCC re-ordering or caching values in expressions
+ * by introducing sequence points into the in*() definitions.  Note that
+ * __raw_* do not guarantee this behaviour.
+ *
+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
+ */
+#ifdef __io
+#define outb(v, p)			__raw_writeb(v, __io(p))
+#define outw(v, p)			__raw_writew(cpu_to_le16(v), __io(p))
+#define outl(v, p)			__raw_writel(cpu_to_le32(v), __io(p))
+
+#define inb(p)	({ unsigned int __v = __raw_readb(__io(p)); __v; })
+#define inw(p)	({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
+#define inl(p)	({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
+
+#define outsb(p, d, l)			writesb(__io(p), d, l)
+#define outsw(p, d, l)			writesw(__io(p), d, l)
+#define outsl(p, d, l)			writesl(__io(p), d, l)
+
+#define insb(p, d, l)			readsb(__io(p), d, l)
+#define insw(p, d, l)			readsw(__io(p), d, l)
+#define insl(p, d, l)			readsl(__io(p), d, l)
+
+static inline void readsb(unsigned int *addr, void *data, int bytelen)
+{
+	unsigned char *ptr;
+	unsigned char *ptr2;
+
+	ptr = (unsigned char *)addr;
+	ptr2 = (unsigned char *)data;
+
+	while (bytelen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		bytelen--;
+	}
+}
+
+static inline void readsw(unsigned int *addr, void *data, int wordlen)
+{
+	unsigned short *ptr;
+	unsigned short *ptr2;
+
+	ptr = (unsigned short *)addr;
+	ptr2 = (unsigned short *)data;
+
+	while (wordlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		wordlen--;
+	}
+}
+
+static inline void readsl(unsigned int *addr, void *data, int longlen)
+{
+	unsigned int *ptr;
+	unsigned int *ptr2;
+
+	ptr = (unsigned int *)addr;
+	ptr2 = (unsigned int *)data;
+
+	while (longlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		longlen--;
+	}
+}
+
+static inline void writesb(unsigned int *addr, const void *data, int bytelen)
+{
+	unsigned char *ptr;
+	unsigned char *ptr2;
+
+	ptr = (unsigned char *)addr;
+	ptr2 = (unsigned char *)data;
+
+	while (bytelen) {
+		*ptr = *ptr2;
+		ptr2++;
+		bytelen--;
+	}
+}
+
+static inline void writesw(unsigned int *addr, const void *data, int wordlen)
+{
+	unsigned short *ptr;
+	unsigned short *ptr2;
+
+	ptr = (unsigned short *)addr;
+	ptr2 = (unsigned short *)data;
+
+	while (wordlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		wordlen--;
+	}
+}
+
+static inline void writesl(unsigned int *addr, const void *data, int longlen)
+{
+	unsigned int *ptr;
+	unsigned int *ptr2;
+
+	ptr = (unsigned int *)addr;
+	ptr2 = (unsigned int *)data;
+
+	while (longlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		longlen--;
+	}
+}
+#endif
+
+#define outb_p(val, port)		outb((val), (port))
+#define outw_p(val, port)		outw((val), (port))
+#define outl_p(val, port)		outl((val), (port))
+#define inb_p(port)			inb((port))
+#define inw_p(port)			inw((port))
+#define inl_p(port)			inl((port))
+
+#define outsb_p(port, from, len)	outsb(port, from, len)
+#define outsw_p(port, from, len)	outsw(port, from, len)
+#define outsl_p(port, from, len)	outsl(port, from, len)
+#define insb_p(port, to, len)		insb(port, to, len)
+#define insw_p(port, to, len)		insw(port, to, len)
+#define insl_p(port, to, len)		insl(port, to, len)
+
+/*
+ * DMA-consistent mapping functions.  These allocate/free a region of
+ * uncached, unwrite-buffered mapped memory space for use with DMA
+ * devices.  This is the "generic" version.  The PCI specific version
+ * is in pci.h
+ */
+
+/*
+ * String version of IO memory access ops:
+ */
+
+/*
+ * If this architecture has PCI memory IO, then define the read/write
+ * macros.  These should only be used with the cookie passed from
+ * ioremap.
+ */
+#ifdef __mem_pci
+
+#define readb(c) ({ unsigned int __v = \
+			__raw_readb(__mem_pci(c)); __v; })
+#define readw(c) ({ unsigned int __v = \
+			le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c) ({ unsigned int __v = \
+			le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+
+#define writeb(v, c)		__raw_writeb(v, __mem_pci(c))
+#define writew(v, c)		__raw_writew(cpu_to_le16(v), __mem_pci(c))
+#define writel(v, c)		__raw_writel(cpu_to_le32(v), __mem_pci(c))
+
+#define memset_io(c, v, l)	_memset_io(__mem_pci(c), (v), (l))
+#define memcpy_fromio(a, c, l)	_memcpy_fromio((a), __mem_pci(c), (l))
+#define memcpy_toio(c, a, l)	_memcpy_toio(__mem_pci(c), (a), (l))
+
+#define eth_io_copy_and_sum(s, c, l, b) \
+	eth_copy_and_sum((s), __mem_pci(c), (l), (b))
+
+static inline int check_signature(ulong io_addr, const uchar *s, int len)
+{
+	int retval = 0;
+
+	do {
+		if (readb(io_addr) != *s)
+			goto out;
+		io_addr++;
+		s++;
+		len--;
+	} while (len);
+	retval = 1;
+out:
+	return retval;
+}
+#endif	/* __mem_pci */
+
+/*
+ * If this architecture has ISA IO, then define the isa_read/isa_write
+ * macros.
+ */
+#ifdef __mem_isa
+
+#define isa_readb(addr)			__raw_readb(__mem_isa(addr))
+#define isa_readw(addr)			__raw_readw(__mem_isa(addr))
+#define isa_readl(addr)			__raw_readl(__mem_isa(addr))
+#define isa_writeb(val, addr)		__raw_writeb(val, __mem_isa(addr))
+#define isa_writew(val, addr)		__raw_writew(val, __mem_isa(addr))
+#define isa_writel(val, addr)		__raw_writel(val, __mem_isa(addr))
+#define isa_memset_io(a, b, c)		_memset_io(__mem_isa(a), (b), (c))
+#define isa_memcpy_fromio(a, b, c)	_memcpy_fromio((a), __mem_isa(b), (c))
+#define isa_memcpy_toio(a, b, c)	_memcpy_toio(__mem_isa((a)), (b), (c))
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	eth_copy_and_sum((a), __mem_isa(b), (c), (d))
+
+static inline int
+isa_check_signature(ulong io_addr, const uchar *s, int len)
+{
+	int retval = 0;
+
+	do {
+		if (isa_readb(io_addr) != *s)
+			goto out;
+		io_addr++;
+		s++;
+		len--;
+	} while (len);
+	retval = 1;
+out:
+	return retval;
+}
+
+#else	/* __mem_isa */
+
+#define isa_readb(addr)			(__readwrite_bug("isa_readb"), 0)
+#define isa_readw(addr)			(__readwrite_bug("isa_readw"), 0)
+#define isa_readl(addr)			(__readwrite_bug("isa_readl"), 0)
+#define isa_writeb(val, addr)		__readwrite_bug("isa_writeb")
+#define isa_writew(val, addr)		__readwrite_bug("isa_writew")
+#define isa_writel(val, addr)		__readwrite_bug("isa_writel")
+#define isa_memset_io(a, b, c)		__readwrite_bug("isa_memset_io")
+#define isa_memcpy_fromio(a, b, c)	__readwrite_bug("isa_memcpy_fromio")
+#define isa_memcpy_toio(a, b, c)	__readwrite_bug("isa_memcpy_toio")
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	__readwrite_bug("isa_eth_io_copy_and_sum")
+
+#define isa_check_signature(io, sig, len)	(0)
+
+#endif	/* __mem_isa */
+#endif	/* __KERNEL__ */
+
+#include <asm-generic/io.h>
+
+#endif	/* __ASM_RISCV_IO_H */
diff --git a/roms/u-boot/arch/riscv/include/asm/linkage.h b/roms/u-boot/arch/riscv/include/asm/linkage.h
new file mode 100644
index 000000000..0c8822b7d
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/linkage.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * U-Boot - linkage.h
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ */
+
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+#endif
diff --git a/roms/u-boot/arch/riscv/include/asm/posix_types.h b/roms/u-boot/arch/riscv/include/asm/posix_types.h
new file mode 100644
index 000000000..0fc052082
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/posix_types.h
@@ -0,0 +1,93 @@
+/*
+ * linux/include/asm-arm/posix_types.h
+ *
+ * Copyright (C) 1996-1998 Russell King.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ * Copyright (C) 2017 Rick Chen (rick@andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   27-06-1996	RMK	Created
+ *   25-10-2017	Modified for arch RISCV
+ */
+#ifndef __ARCH_RISCV_POSIX_TYPES_H
+#define __ARCH_RISCV_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short		__kernel_dev_t;
+typedef unsigned long		__kernel_ino_t;
+typedef unsigned short		__kernel_mode_t;
+typedef unsigned short		__kernel_nlink_t;
+typedef long			__kernel_off_t;
+typedef int			__kernel_pid_t;
+typedef unsigned short		__kernel_ipc_pid_t;
+typedef unsigned short		__kernel_uid_t;
+typedef unsigned short		__kernel_gid_t;
+#ifdef __GNUC__
+typedef __SIZE_TYPE__		__kernel_size_t;
+#else
+typedef unsigned long		__kernel_size_t;
+#endif
+typedef long			__kernel_ssize_t;
+typedef long			__kernel_ptrdiff_t;
+typedef long			__kernel_time_t;
+typedef long			__kernel_suseconds_t;
+typedef long			__kernel_clock_t;
+typedef int			__kernel_daddr_t;
+typedef char			*__kernel_caddr_t;
+typedef unsigned short		__kernel_uid16_t;
+typedef unsigned short		__kernel_gid16_t;
+typedef unsigned int		__kernel_uid32_t;
+typedef unsigned int		__kernel_gid32_t;
+
+typedef unsigned short		__kernel_old_uid_t;
+typedef unsigned short		__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long		__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+#define __FD_SET(_fd, fdsetp) \
+	typeof(_fd) (fd) = (_fd); \
+	(((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1 << (fd & 31)))
+
+#undef	__FD_CLR
+#define __FD_CLR(_fd, fdsetp) \
+	typeof(_fd) (fd) = (_fd); \
+	(((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1 << (fd & 31)))
+
+#undef	__FD_ISSET
+#define __FD_ISSET(_fd, fdsetp) \
+	typeof(_fd) (fd) = (_fd); \
+	((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1 << (fd & 31))) != 0)
+
+#undef	__FD_ZERO
+#define __FD_ZERO(_fdsetp) \
+	typeof(_fdsetp) (fd) = (_fdsetp); \
+	(memset(fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
+
+#endif
+
+#endif /* __ARCH_RISCV_POSIX_TYPES_H */
diff --git a/roms/u-boot/arch/riscv/include/asm/processor.h b/roms/u-boot/arch/riscv/include/asm/processor.h
new file mode 100644
index 000000000..fe3575298
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/processor.h
@@ -0,0 +1,26 @@
+/*
+ * linux/include/asm-arm/processor.h
+ *
+ * Copyright (C) 1995-2002 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ * Copyright (C) 2017 Rick Chen (rick@andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_RISCV_PROCESSOR_H
+#define __ASM_RISCV_PROCESSOR_H
+
+/**************************************************************
+ * CAUTION:
+ *   - do not implement for RISCV Arch yet.
+ *   - so far some files include /asm/processor.h, but
+ *     no one uses the macros defined in this head file.
+ **************************************************************/
+
+#endif /* __ASM_RISCV_PROCESSOR_H */
diff --git a/roms/u-boot/arch/riscv/include/asm/ptrace.h b/roms/u-boot/arch/riscv/include/asm/ptrace.h
new file mode 100644
index 000000000..651078fcf
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/ptrace.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2017 Microsemi Corporation.
+ * Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_RISCV_PTRACE_H
+#define __ASM_RISCV_PTRACE_H
+
+struct pt_regs {
+	unsigned long sepc;
+	unsigned long ra;
+	unsigned long sp;
+	unsigned long gp;
+	unsigned long tp;
+	unsigned long t0;
+	unsigned long t1;
+	unsigned long t2;
+	unsigned long s0;
+	unsigned long s1;
+	unsigned long a0;
+	unsigned long a1;
+	unsigned long a2;
+	unsigned long a3;
+	unsigned long a4;
+	unsigned long a5;
+	unsigned long a6;
+	unsigned long a7;
+	unsigned long s2;
+	unsigned long s3;
+	unsigned long s4;
+	unsigned long s5;
+	unsigned long s6;
+	unsigned long s7;
+	unsigned long s8;
+	unsigned long s9;
+	unsigned long s10;
+	unsigned long s11;
+	unsigned long t3;
+	unsigned long t4;
+	unsigned long t5;
+	unsigned long t6;
+	/* Supervisor CSRs */
+	unsigned long sstatus;
+	unsigned long sbadaddr;
+	unsigned long scause;
+};
+
+#ifdef CONFIG_64BIT
+#define REG_FMT "%016lx"
+#else
+#define REG_FMT "%08lx"
+#endif
+
+#define user_mode(regs) (((regs)->sstatus & SR_PS) == 0)
+
+/* Helpers for working with the instruction pointer */
+#define GET_IP(regs) ((regs)->sepc)
+#define SET_IP(regs, val) (GET_IP(regs) = (val))
+
+static inline unsigned long instruction_pointer(struct pt_regs *regs)
+{
+	return GET_IP(regs);
+}
+
+static inline void instruction_pointer_set(struct pt_regs *regs, ulong val)
+{
+	SET_IP(regs, val);
+}
+
+#define profile_pc(regs) instruction_pointer(regs)
+
+/* Helpers for working with the user stack pointer */
+#define GET_USP(regs) ((regs)->sp)
+#define SET_USP(regs, val) (GET_USP(regs) = (val))
+
+static inline unsigned long user_stack_pointer(struct pt_regs *regs)
+{
+	return GET_USP(regs);
+}
+
+static inline void user_stack_pointer_set(struct pt_regs *regs, ulong val)
+{
+	SET_USP(regs, val);
+}
+
+/* Helpers for working with the frame pointer */
+#define GET_FP(regs) ((regs)->s0)
+#define SET_FP(regs, val) (GET_FP(regs) = (val))
+
+static inline unsigned long frame_pointer(struct pt_regs *regs)
+{
+	return GET_FP(regs);
+}
+
+static inline void frame_pointer_set(struct pt_regs *regs, ulong val)
+{
+	SET_FP(regs, val);
+}
+
+#endif /* __ASM_RISCV_PTRACE_H */
diff --git a/roms/u-boot/arch/riscv/include/asm/sbi.h b/roms/u-boot/arch/riscv/include/asm/sbi.h
new file mode 100644
index 000000000..53ca31618
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/sbi.h
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2015 Regents of the University of California
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Taken from Linux arch/riscv/include/asm/sbi.h
+ */
+
+#ifndef _ASM_RISCV_SBI_H
+#define _ASM_RISCV_SBI_H
+
+#include <linux/types.h>
+
+enum sbi_ext_id {
+#ifdef CONFIG_SBI_V01
+	SBI_EXT_0_1_SET_TIMER = 0x0,
+	SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
+	SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
+	SBI_EXT_0_1_CLEAR_IPI = 0x3,
+	SBI_EXT_0_1_SEND_IPI = 0x4,
+	SBI_EXT_0_1_REMOTE_FENCE_I = 0x5,
+	SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
+	SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
+	SBI_EXT_0_1_SHUTDOWN = 0x8,
+#endif
+	SBI_EXT_BASE = 0x10,
+	SBI_EXT_TIME = 0x54494D45,
+	SBI_EXT_IPI = 0x735049,
+	SBI_EXT_RFENCE = 0x52464E43,
+};
+
+enum sbi_ext_base_fid {
+	SBI_EXT_BASE_GET_SPEC_VERSION = 0,
+	SBI_EXT_BASE_GET_IMP_ID,
+	SBI_EXT_BASE_GET_IMP_VERSION,
+	SBI_EXT_BASE_PROBE_EXT,
+	SBI_EXT_BASE_GET_MVENDORID,
+	SBI_EXT_BASE_GET_MARCHID,
+	SBI_EXT_BASE_GET_MIMPID,
+};
+
+enum sbi_ext_time_fid {
+	SBI_EXT_TIME_SET_TIMER = 0,
+};
+
+enum sbi_ext_ipi_fid {
+	SBI_EXT_IPI_SEND_IPI = 0,
+};
+
+enum sbi_ext_rfence_fid {
+	SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
+	SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
+	SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
+};
+
+#ifdef CONFIG_SBI_V01
+#define SBI_EXT_SET_TIMER		SBI_EXT_0_1_SET_TIMER
+#define SBI_FID_SET_TIMER		0
+#define SBI_EXT_SEND_IPI		SBI_EXT_0_1_SEND_IPI
+#define SBI_FID_SEND_IPI		0
+#define SBI_EXT_REMOTE_FENCE_I		SBI_EXT_0_1_REMOTE_FENCE_I
+#define SBI_FID_REMOTE_FENCE_I		0
+#define SBI_EXT_REMOTE_SFENCE_VMA	SBI_EXT_0_1_REMOTE_SFENCE_VMA
+#define SBI_FID_REMOTE_SFENCE_VMA	0
+#define SBI_EXT_REMOTE_SFENCE_VMA_ASID	SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID
+#define SBI_FID_REMOTE_SFENCE_VMA_ASID	0
+#else
+#define SBI_EXT_SET_TIMER		SBI_EXT_TIME
+#define SBI_FID_SET_TIMER		SBI_EXT_TIME_SET_TIMER
+#define SBI_EXT_SEND_IPI		SBI_EXT_IPI
+#define SBI_FID_SEND_IPI		SBI_EXT_IPI_SEND_IPI
+#define SBI_EXT_REMOTE_FENCE_I		SBI_EXT_RFENCE
+#define SBI_FID_REMOTE_FENCE_I		SBI_EXT_RFENCE_REMOTE_FENCE_I
+#define SBI_EXT_REMOTE_SFENCE_VMA	SBI_EXT_RFENCE
+#define SBI_FID_REMOTE_SFENCE_VMA	SBI_EXT_RFENCE_REMOTE_SFENCE_VMA
+#define SBI_EXT_REMOTE_SFENCE_VMA_ASID	SBI_EXT_RFENCE
+#define SBI_FID_REMOTE_SFENCE_VMA_ASID	SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID
+#endif
+
+#define SBI_SPEC_VERSION_MAJOR_SHIFT	24
+#define SBI_SPEC_VERSION_MAJOR_MASK	0x7f
+#define SBI_SPEC_VERSION_MINOR_MASK	0xffffff
+
+/* SBI return error codes */
+#define SBI_SUCCESS			0
+#define SBI_ERR_FAILURE			-1
+#define SBI_ERR_NOT_SUPPORTED		-2
+#define SBI_ERR_INVALID_PARAM		-3
+#define SBI_ERR_DENIED			-4
+#define SBI_ERR_INVALID_ADDRESS		-5
+
+struct sbiret {
+	long error;
+	long value;
+};
+
+struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
+			unsigned long arg1, unsigned long arg2,
+			unsigned long arg3, unsigned long arg4,
+			unsigned long arg5);
+
+#ifdef CONFIG_SBI_V01
+void sbi_console_putchar(int ch);
+int sbi_console_getchar(void);
+void sbi_clear_ipi(void);
+void sbi_shutdown(void);
+void sbi_send_ipi(const unsigned long *hart_mask);
+void sbi_remote_fence_i(const unsigned long *hart_mask);
+void sbi_remote_sfence_vma(const unsigned long *hart_mask,
+			   unsigned long start,
+			   unsigned long size);
+void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
+				unsigned long start,
+				unsigned long size,
+				unsigned long asid);
+#endif
+void sbi_set_timer(uint64_t stime_value);
+long sbi_get_spec_version(void);
+int sbi_get_impl_id(void);
+int sbi_probe_extension(int ext);
+
+#endif
diff --git a/roms/u-boot/arch/riscv/include/asm/sections.h b/roms/u-boot/arch/riscv/include/asm/sections.h
new file mode 100644
index 000000000..9dd36ddda
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/sections.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ */
+
+#ifndef __ASM_RISCV_SECTIONS_H
+#define __ASM_RISCV_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif
diff --git a/roms/u-boot/arch/riscv/include/asm/setjmp.h b/roms/u-boot/arch/riscv/include/asm/setjmp.h
new file mode 100644
index 000000000..72383d433
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/setjmp.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018 Alexander Graf <agraf@suse.de>
+ */
+
+#ifndef _SETJMP_H_
+#define _SETJMP_H_	1
+
+/*
+ * This really should be opaque, but the EFI implementation wrongly
+ * assumes that a 'struct jmp_buf_data' is defined.
+ */
+struct jmp_buf_data {
+	/* x2, x8, x9, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, sp */
+	unsigned long s_regs[12];	/* s0 - s11 */
+	unsigned long ra;
+	unsigned long sp;
+};
+
+typedef struct jmp_buf_data jmp_buf[1];
+
+int setjmp(jmp_buf jmp);
+void longjmp(jmp_buf jmp, int ret);
+
+#endif /* _SETJMP_H_ */
diff --git a/roms/u-boot/arch/riscv/include/asm/smp.h b/roms/u-boot/arch/riscv/include/asm/smp.h
new file mode 100644
index 000000000..2dae0800c
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/smp.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Fraunhofer AISEC,
+ * Lukas Auer <lukas.auer@aisec.fraunhofer.de>
+ */
+
+#ifndef _ASM_RISCV_SMP_H
+#define _ASM_RISCV_SMP_H
+
+/**
+ * struct ipi_data - Inter-processor interrupt (IPI) data structure
+ *
+ * IPIs are used for SMP support to communicate to other harts what function to
+ * call. Functions are in the form
+ * void (*addr)(ulong hart, ulong arg0, ulong arg1).
+ *
+ * The function address and the two arguments, arg0 and arg1, are stored in the
+ * IPI data structure. The hart ID is inserted by the hart handling the IPI and
+ * calling the function.
+ *
+ * @valid is used to determine whether a sent IPI originated from U-Boot. It is
+ * initialized to zero by board_init_f_alloc_reserve. When U-Boot sends its
+ * first IPI, it is set to 1. This prevents already-pending IPIs not sent by
+ * U-Boot from being taken.
+ *
+ * @addr: Address of function
+ * @arg0: First argument of function
+ * @arg1: Second argument of function
+ * @valid: Whether this IPI is valid
+ */
+struct ipi_data {
+	ulong addr;
+	ulong arg0;
+	ulong arg1;
+	unsigned int valid;
+};
+
+/**
+ * handle_ipi() - interrupt handler for software interrupts
+ *
+ * The IPI interrupt handler must be called to handle software interrupts. It
+ * calls the function specified in the hart's IPI data structure.
+ *
+ * @hart: Hart ID of the current hart
+ */
+void handle_ipi(ulong hart);
+
+/**
+ * smp_call_function() - Call a function on all other harts
+ *
+ * Send IPIs with the specified function call to all harts.
+ *
+ * @addr: Address of function
+ * @arg0: First argument of function
+ * @arg1: Second argument of function
+ * @wait: Wait for harts to acknowledge request
+ * @return 0 if OK, -ve on error
+ */
+int smp_call_function(ulong addr, ulong arg0, ulong arg1, int wait);
+
+/**
+ * riscv_init_ipi() - Initialize inter-process interrupt (IPI) driver
+ *
+ * Platform code must provide this function. This function is called once after
+ * the cpu driver is initialized. No other riscv_*_ipi() calls will be made
+ * before this function is called.
+ *
+ * @return 0 if OK, -ve on error
+ */
+int riscv_init_ipi(void);
+
+/**
+ * riscv_send_ipi() - Send inter-processor interrupt (IPI)
+ *
+ * Platform code must provide this function.
+ *
+ * @hart: Hart ID of receiving hart
+ * @return 0 if OK, -ve on error
+ */
+int riscv_send_ipi(int hart);
+
+/**
+ * riscv_clear_ipi() - Clear inter-processor interrupt (IPI)
+ *
+ * Platform code must provide this function.
+ *
+ * @hart: Hart ID of hart to be cleared
+ * @return 0 if OK, -ve on error
+ */
+int riscv_clear_ipi(int hart);
+
+/**
+ * riscv_get_ipi() - Get status of inter-processor interrupt (IPI)
+ *
+ * Platform code must provide this function.
+ *
+ * @hart: Hart ID of hart to be checked
+ * @pending: Pointer to variable with result of the check,
+ *           1 if IPI is pending, 0 otherwise
+ * @return 0 if OK, -ve on error
+ */
+int riscv_get_ipi(int hart, int *pending);
+
+#endif
diff --git a/roms/u-boot/arch/riscv/include/asm/spl.h b/roms/u-boot/arch/riscv/include/asm/spl.h
new file mode 100644
index 000000000..1487f2d91
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/spl.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Based on arch/mips/include/asm/spl.h.
+ *
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ */
+#ifndef _ASM_RISCV_SPL_H_
+#define _ASM_RISCV_SPL_H_
+
+enum {
+	BOOT_DEVICE_RAM,
+	BOOT_DEVICE_MMC1,
+	BOOT_DEVICE_MMC2,
+	BOOT_DEVICE_MMC2_2,
+	BOOT_DEVICE_NAND,
+	BOOT_DEVICE_ONENAND,
+	BOOT_DEVICE_NOR,
+	BOOT_DEVICE_UART,
+	BOOT_DEVICE_SPI,
+	BOOT_DEVICE_USB,
+	BOOT_DEVICE_SATA,
+	BOOT_DEVICE_I2C,
+	BOOT_DEVICE_BOARD,
+	BOOT_DEVICE_DFU,
+	BOOT_DEVICE_XIP,
+	BOOT_DEVICE_BOOTROM,
+	BOOT_DEVICE_NONE
+};
+
+/**
+ * spl_board_init_f() - initialize board in the SPL phase
+ *
+ * @return 0 if succeeded, -ve on error
+ */
+int spl_board_init_f(void);
+
+#endif
diff --git a/roms/u-boot/arch/riscv/include/asm/string.h b/roms/u-boot/arch/riscv/include/asm/string.h
new file mode 100644
index 000000000..7dee3e4c9
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/string.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ * Copyright (C) 2017 Rick Chen (rick@andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_RISCV_STRING_H
+#define __ASM_RISCV_STRING_H
+
+/*
+ * We don't do inline string functions, since the
+ * optimised inline asm versions are not small.
+ */
+
+#undef __HAVE_ARCH_STRRCHR
+#undef __HAVE_ARCH_STRCHR
+#undef __HAVE_ARCH_MEMCHR
+#undef __HAVE_ARCH_MEMZERO
+
+#undef __HAVE_ARCH_MEMCPY
+#if CONFIG_IS_ENABLED(USE_ARCH_MEMCPY)
+#define __HAVE_ARCH_MEMCPY
+#endif
+extern void *memcpy(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMMOVE
+#if CONFIG_IS_ENABLED(USE_ARCH_MEMMOVE)
+#define __HAVE_ARCH_MEMMOVE
+#endif
+extern void *memmove(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMZERO
+#if CONFIG_IS_ENABLED(USE_ARCH_MEMSET)
+#define __HAVE_ARCH_MEMSET
+#endif
+extern void *memset(void *, int, __kernel_size_t);
+
+#endif /* __ASM_RISCV_STRING_H */
diff --git a/roms/u-boot/arch/riscv/include/asm/syscon.h b/roms/u-boot/arch/riscv/include/asm/syscon.h
new file mode 100644
index 000000000..c3629e4b5
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/syscon.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _ASM_SYSCON_H
+#define _ASM_SYSCON_H
+
+/*
+ * System controllers in a RISC-V system. These should only be used for
+ * identifying IPI controllers. Other devices should use DM to probe.
+ */
+enum {
+	RISCV_NONE,
+	RISCV_SYSCON_CLINT,	/* Core Local Interruptor (CLINT) */
+	RISCV_SYSCON_PLIC,	/* Platform Level Interrupt Controller (PLIC) */
+};
+
+#endif /* _ASM_SYSCON_H */
diff --git a/roms/u-boot/arch/riscv/include/asm/system.h b/roms/u-boot/arch/riscv/include/asm/system.h
new file mode 100644
index 000000000..a34047582
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/system.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#ifndef __ASM_RISCV_SYSTEM_H
+#define __ASM_RISCV_SYSTEM_H
+
+/*
+ * Interrupt configuring macros.
+ *
+ * TODO
+ *
+ */
+
+#endif	/* __ASM_RISCV_SYSTEM_H */
diff --git a/roms/u-boot/arch/riscv/include/asm/types.h b/roms/u-boot/arch/riscv/include/asm/types.h
new file mode 100644
index 000000000..49f7a5d6b
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/types.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ * Copyright (C) 2017 Rick Chen (rick@andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_RISCV_TYPES_H
+#define __ASM_RISCV_TYPES_H
+
+#include <asm-generic/int-ll64.h>
+
+typedef unsigned short umode_t;
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#ifdef CONFIG_ARCH_RV64I
+#define BITS_PER_LONG 64
+#else
+#define BITS_PER_LONG 32
+#endif
+
+#include <stddef.h>
+
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+typedef u64 dma_addr_t;
+#else
+typedef u32 dma_addr_t;
+#endif
+
+typedef unsigned long long phys_addr_t;
+typedef unsigned long long phys_size_t;
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/roms/u-boot/arch/riscv/include/asm/u-boot-riscv.h b/roms/u-boot/arch/riscv/include/asm/u-boot-riscv.h
new file mode 100644
index 000000000..543a1688d
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/u-boot-riscv.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#ifndef _U_BOOT_RISCV_H_
+#define _U_BOOT_RISCV_H_	1
+
+/* cpu/.../cpu.c */
+int cleanup_before_linux(void);
+
+/* board/.../... */
+int board_init(void);
+void board_quiesce_devices(void);
+int riscv_board_reserved_mem_fixup(void *fdt);
+int riscv_fdt_copy_resv_mem_node(const void *src_fdt, void *dest_fdt);
+
+#endif	/* _U_BOOT_RISCV_H_ */
diff --git a/roms/u-boot/arch/riscv/include/asm/u-boot.h b/roms/u-boot/arch/riscv/include/asm/u-boot.h
new file mode 100644
index 000000000..d5e1d5f32
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/u-boot.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_	1
+
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
+#include <asm/u-boot-riscv.h>
+
+/* For image.h:image_check_target_arch() */
+#define IH_ARCH_DEFAULT IH_ARCH_RISCV
+
+#endif	/* _U_BOOT_H_ */
diff --git a/roms/u-boot/arch/riscv/include/asm/unaligned.h b/roms/u-boot/arch/riscv/include/asm/unaligned.h
new file mode 100644
index 000000000..6cecbbb21
--- /dev/null
+++ b/roms/u-boot/arch/riscv/include/asm/unaligned.h
@@ -0,0 +1 @@
+#include <asm-generic/unaligned.h>
diff --git a/roms/u-boot/arch/riscv/lib/Makefile b/roms/u-boot/arch/riscv/lib/Makefile
new file mode 100644
index 000000000..c4cc41434
--- /dev/null
+++ b/roms/u-boot/arch/riscv/lib/Makefile
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2017 Andes Technology Corporation
+# Rick Chen, Andes Technology Corporation <rick@andestech.com>
+
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
+obj-$(CONFIG_CMD_GO) += boot.o
+obj-y	+= cache.o
+ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
+obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
+obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
+else
+obj-$(CONFIG_SBI) += sbi.o
+obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
+endif
+obj-y	+= interrupts.o
+ifeq ($(CONFIG_$(SPL_)SYSRESET),)
+obj-y	+= reset.o
+endif
+obj-y   += setjmp.o
+obj-$(CONFIG_$(SPL_)SMP) += smp.o
+obj-$(CONFIG_SPL_BUILD)	+= spl.o
+obj-y   += fdt_fixup.o
+
+# For building EFI apps
+CFLAGS_NON_EFI := -fstack-protector-strong
+CFLAGS_$(EFI_CRT0) := $(CFLAGS_EFI)
+CFLAGS_REMOVE_$(EFI_CRT0) := $(CFLAGS_NON_EFI)
+
+CFLAGS_$(EFI_RELOC) := $(CFLAGS_EFI)
+CFLAGS_REMOVE_$(EFI_RELOC) := $(CFLAGS_NON_EFI)
+
+extra-$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE) += $(EFI_CRT0) $(EFI_RELOC)
+extra-$(CONFIG_CMD_BOOTEFI_SELFTEST) += $(EFI_CRT0) $(EFI_RELOC)
+extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC)
+
+obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o
+obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMMOVE) += memmove.o
+obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o
diff --git a/roms/u-boot/arch/riscv/lib/andes_plic.c b/roms/u-boot/arch/riscv/lib/andes_plic.c
new file mode 100644
index 000000000..5e113ee8c
--- /dev/null
+++ b/roms/u-boot/arch/riscv/lib/andes_plic.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019, Rick Chen <rick@andestech.com>
+ *
+ * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC).
+ * The PLIC block holds memory-mapped claim and pending registers
+ * associated with software interrupt.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/global_data.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/uclass-internal.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/syscon.h>
+#include <cpu.h>
+#include <linux/err.h>
+
+/* pending register */
+#define PENDING_REG(base, hart)	((ulong)(base) + 0x1000 + ((hart) / 4) * 4)
+/* enable register */
+#define ENABLE_REG(base, hart)	((ulong)(base) + 0x2000 + (hart) * 0x80)
+/* claim register */
+#define CLAIM_REG(base, hart)	((ulong)(base) + 0x200004 + (hart) * 0x1000)
+
+#define ENABLE_HART_IPI         (0x80808080)
+#define SEND_IPI_TO_HART(hart)  (0x80 >> (hart))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int enable_ipi(int hart)
+{
+	unsigned int en;
+
+	en = ENABLE_HART_IPI >> hart;
+	writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));
+
+	return 0;
+}
+
+int riscv_init_ipi(void)
+{
+	int ret;
+	long *base = syscon_get_first_range(RISCV_SYSCON_PLIC);
+	ofnode node;
+	struct udevice *dev;
+	u32 reg;
+
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+	gd->arch.plic = base;
+
+	ret = uclass_find_first_device(UCLASS_CPU, &dev);
+	if (ret)
+		return ret;
+	else if (!dev)
+		return -ENODEV;
+
+	ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
+		const char *device_type;
+
+		device_type = ofnode_read_string(node, "device_type");
+		if (!device_type)
+			continue;
+
+		if (strcmp(device_type, "cpu"))
+			continue;
+
+		/* skip if hart is marked as not available */
+		if (!ofnode_is_available(node))
+			continue;
+
+		/* read hart ID of CPU */
+		ret = ofnode_read_u32(node, "reg", &reg);
+		if (ret == 0)
+			enable_ipi(reg);
+	}
+
+	return 0;
+}
+
+int riscv_send_ipi(int hart)
+{
+	unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
+
+	writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
+				gd->arch.boot_hart));
+
+	return 0;
+}
+
+int riscv_clear_ipi(int hart)
+{
+	u32 source_id;
+
+	source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
+	writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
+
+	return 0;
+}
+
+int riscv_get_ipi(int hart, int *pending)
+{
+	unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
+
+	*pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
+						     gd->arch.boot_hart));
+	*pending = !!(*pending & ipi);
+
+	return 0;
+}
+
+static const struct udevice_id andes_plic_ids[] = {
+	{ .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
+	{ }
+};
+
+U_BOOT_DRIVER(andes_plic) = {
+	.name		= "andes_plic",
+	.id		= UCLASS_SYSCON,
+	.of_match	= andes_plic_ids,
+	.flags		= DM_FLAG_PRE_RELOC,
+};
diff --git a/roms/u-boot/arch/riscv/lib/asm-offsets.c b/roms/u-boot/arch/riscv/lib/asm-offsets.c
new file mode 100644
index 000000000..f1fe089b3
--- /dev/null
+++ b/roms/u-boot/arch/riscv/lib/asm-offsets.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * From arch/x86/lib/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ */
+
+#include <common.h>
+#include <asm/global_data.h>
+#include <linux/kbuild.h>
+
+int main(void)
+{
+	DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
+	DEFINE(GD_FIRMWARE_FDT_ADDR, offsetof(gd_t, arch.firmware_fdt_addr));
+#ifndef CONFIG_XIP
+	DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
+#endif
+
+	return 0;
+}
diff --git a/roms/u-boot/arch/riscv/lib/boot.c b/roms/u-boot/arch/riscv/lib/boot.c
new file mode 100644
index 000000000..778d011f7
--- /dev/null
+++ b/roms/u-boot/arch/riscv/lib/boot.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#include <common.h>
+#include <command.h>
+
+unsigned long do_go_exec(ulong (*entry)(int, char * const []),
+			 int argc, char *const argv[])
+{
+	cleanup_before_linux();
+
+	return entry(argc, argv);
+}
diff --git a/roms/u-boot/arch/riscv/lib/bootm.c b/roms/u-boot/arch/riscv/lib/bootm.c
new file mode 100644
index 000000000..8dd182054
--- /dev/null
+++ b/roms/u-boot/arch/riscv/lib/bootm.c
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#include <common.h>
+#include <bootstage.h>
+#include <command.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <hang.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <dm/root.h>
+#include <image.h>
+#include <asm/byteorder.h>
+#include <asm/csr.h>
+#include <asm/smp.h>
+#include <dm/device.h>
+#include <dm/root.h>
+#include <u-boot/zlib.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak void board_quiesce_devices(void)
+{
+}
+
+/**
+ * announce_and_cleanup() - Print message and prepare for kernel boot
+ *
+ * @fake: non-zero to do everything except actually boot
+ */
+static void announce_and_cleanup(int fake)
+{
+	printf("\nStarting kernel ...%s\n\n", fake ?
+		"(fake run for tracing)" : "");
+	bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
+#ifdef CONFIG_BOOTSTAGE_FDT
+	bootstage_fdt_add_report();
+#endif
+#ifdef CONFIG_BOOTSTAGE_REPORT
+	bootstage_report();
+#endif
+
+#ifdef CONFIG_USB_DEVICE
+	udc_disconnect();
+#endif
+
+	board_quiesce_devices();
+
+	/*
+	 * Call remove function of all devices with a removal flag set.
+	 * This may be useful for last-stage operations, like cancelling
+	 * of DMA operation or releasing device internal buffers.
+	 */
+	dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
+
+	cleanup_before_linux();
+}
+
+static void boot_prep_linux(bootm_headers_t *images)
+{
+	if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+#ifdef CONFIG_OF_LIBFDT
+		debug("using: FDT\n");
+		if (image_setup_linux(images)) {
+			printf("FDT creation failed! hanging...");
+			hang();
+		}
+#endif
+	} else {
+		printf("Device tree not found or missing FDT support\n");
+		hang();
+	}
+}
+
+static void boot_jump_linux(bootm_headers_t *images, int flag)
+{
+	void (*kernel)(ulong hart, void *dtb);
+	int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
+#ifdef CONFIG_SMP
+	int ret;
+#endif
+
+	kernel = (void (*)(ulong, void *))images->ep;
+
+	bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+
+	debug("## Transferring control to kernel (at address %08lx) ...\n",
+	      (ulong)kernel);
+
+	announce_and_cleanup(fake);
+
+	if (!fake) {
+		if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+#ifdef CONFIG_SMP
+			ret = smp_call_function(images->ep,
+						(ulong)images->ft_addr, 0, 0);
+			if (ret)
+				hang();
+#endif
+			kernel(gd->arch.boot_hart, images->ft_addr);
+		}
+	}
+}
+
+int do_bootm_linux(int flag, int argc, char *const argv[],
+		   bootm_headers_t *images)
+{
+	/* No need for those on RISC-V */
+	if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE)
+		return -1;
+
+	if (flag & BOOTM_STATE_OS_PREP) {
+		boot_prep_linux(images);
+		return 0;
+	}
+
+	if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) {
+		boot_jump_linux(images, flag);
+		return 0;
+	}
+
+	boot_prep_linux(images);
+	boot_jump_linux(images, flag);
+	return 0;
+}
+
+int do_bootm_vxworks(int flag, int argc, char *const argv[],
+		     bootm_headers_t *images)
+{
+	return do_bootm_linux(flag, argc, argv, images);
+}
diff --git a/roms/u-boot/arch/riscv/lib/cache.c b/roms/u-boot/arch/riscv/lib/cache.c
new file mode 100644
index 000000000..b1d42bcc2
--- /dev/null
+++ b/roms/u-boot/arch/riscv/lib/cache.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+
+void invalidate_icache_all(void)
+{
+	asm volatile ("fence.i" ::: "memory");
+}
+
+__weak void flush_dcache_all(void)
+{
+}
+
+__weak void flush_dcache_range(unsigned long start, unsigned long end)
+{
+}
+
+void invalidate_icache_range(unsigned long start, unsigned long end)
+{
+	/*
+	 * RISC-V does not have an instruction for invalidating parts of the
+	 * instruction cache. Invalidate all of it instead.
+	 */
+	invalidate_icache_all();
+}
+
+__weak void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+}
+
+void cache_flush(void)
+{
+	invalidate_icache_all();
+	flush_dcache_all();
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+	invalidate_icache_range(addr, addr + size);
+	flush_dcache_range(addr, addr + size);
+}
+
+__weak void icache_enable(void)
+{
+}
+
+__weak void icache_disable(void)
+{
+}
+
+__weak int icache_status(void)
+{
+	return 0;
+}
+
+__weak void dcache_enable(void)
+{
+}
+
+__weak void dcache_disable(void)
+{
+}
+
+__weak int dcache_status(void)
+{
+	return 0;
+}
diff --git a/roms/u-boot/arch/riscv/lib/crt0_riscv_efi.S b/roms/u-boot/arch/riscv/lib/crt0_riscv_efi.S
new file mode 100644
index 000000000..e7c4d99c2
--- /dev/null
+++ b/roms/u-boot/arch/riscv/lib/crt0_riscv_efi.S
@@ -0,0 +1,176 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * crt0-efi-riscv.S - PE/COFF header for RISC-V EFI applications
+ *
+ * Copright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
+ * Copright (C) 2018 Alexander Graf <agraf@suse.de>
+ *
+ * This file is inspired by arch/arm/lib/crt0_aarch64_efi.S
+ */
+
+#include <asm-generic/pe.h>
+
+#if __riscv_xlen == 64
+#define SIZE_LONG	8
+#define SAVE_LONG(reg, idx)	sd	reg, (idx*SIZE_LONG)(sp)
+#define LOAD_LONG(reg, idx)	ld	reg, (idx*SIZE_LONG)(sp)
+#define PE_MACHINE	IMAGE_FILE_MACHINE_RISCV64
+#define PE_MAGIC    IMAGE_NT_OPTIONAL_HDR64_MAGIC
+#else
+#define SIZE_LONG	4
+#define SAVE_LONG(reg, idx)	sw	reg, (idx*SIZE_LONG)(sp)
+#define LOAD_LONG(reg, idx)	lw	reg, (idx*SIZE_LONG)(sp)
+#define PE_MACHINE	IMAGE_FILE_MACHINE_RISCV32
+#define PE_MAGIC    IMAGE_NT_OPTIONAL_HDR32_MAGIC
+#endif
+
+
+	.section	.text.head
+
+	/*
+	 * Magic "MZ" signature for PE/COFF
+	 */
+	.globl	ImageBase
+ImageBase:
+	.short	IMAGE_DOS_SIGNATURE		/* 'MZ' */
+	.skip	58				/* 'MZ' + pad + offset == 64 */
+	.long	pe_header - ImageBase		/* Offset to the PE header */
+pe_header:
+	.long	IMAGE_NT_SIGNATURE		/* 'PE' */
+coff_header:
+	.short	PE_MACHINE			/* RISC-V 64/32-bit */
+	.short	2				/* nr_sections */
+	.long	0				/* TimeDateStamp */
+	.long	0				/* PointerToSymbolTable */
+	.long	0				/* NumberOfSymbols */
+	.short	section_table - optional_header	/* SizeOfOptionalHeader */
+	/* Characteristics */
+	.short	(IMAGE_FILE_EXECUTABLE_IMAGE | \
+		 IMAGE_FILE_LINE_NUMS_STRIPPED | \
+		 IMAGE_FILE_LOCAL_SYMS_STRIPPED | \
+		 IMAGE_FILE_DEBUG_STRIPPED)
+optional_header:
+	.short	PE_MAGIC			/* PE32(+) format */
+	.byte	0x02				/* MajorLinkerVersion */
+	.byte	0x14				/* MinorLinkerVersion */
+	.long	_edata - _start			/* SizeOfCode */
+	.long	0				/* SizeOfInitializedData */
+	.long	0				/* SizeOfUninitializedData */
+	.long	_start - ImageBase		/* AddressOfEntryPoint */
+	.long	_start - ImageBase		/* BaseOfCode */
+#if __riscv_xlen == 32
+	.long	0				/* BaseOfData */
+#endif
+
+extra_header_fields:
+#if __riscv_xlen == 32
+	.long	0				/* ImageBase */
+#else
+	.quad	0				/* ImageBase */
+#endif
+	.long	0x20				/* SectionAlignment */
+	.long	0x8				/* FileAlignment */
+	.short	0				/* MajorOperatingSystemVersion */
+	.short	0				/* MinorOperatingSystemVersion */
+	.short	0				/* MajorImageVersion */
+	.short	0				/* MinorImageVersion */
+	.short	0				/* MajorSubsystemVersion */
+	.short	0				/* MinorSubsystemVersion */
+	.long	0				/* Win32VersionValue */
+
+	.long	_edata - ImageBase		/* SizeOfImage */
+
+	/*
+	 * Everything before the kernel image is considered part of the header
+	 */
+	.long	_start - ImageBase		/* SizeOfHeaders */
+	.long	0				/* CheckSum */
+	.short	IMAGE_SUBSYSTEM_EFI_APPLICATION /* Subsystem */
+	.short	0				/* DllCharacteristics */
+#if __riscv_xlen == 32
+	.long	0				/* SizeOfStackReserve */
+	.long	0				/* SizeOfStackCommit */
+	.long	0				/* SizeOfHeapReserve */
+	.long	0				/* SizeOfHeapCommit */
+#else
+	.quad	0				/* SizeOfStackReserve */
+	.quad	0				/* SizeOfStackCommit */
+	.quad	0				/* SizeOfHeapReserve */
+	.quad	0				/* SizeOfHeapCommit */
+#endif
+	.long	0				/* LoaderFlags */
+	.long	0x6				/* NumberOfRvaAndSizes */
+
+	.quad	0				/* ExportTable */
+	.quad	0				/* ImportTable */
+	.quad	0				/* ResourceTable */
+	.quad	0				/* ExceptionTable */
+	.quad	0				/* CertificationTable */
+	.quad	0				/* BaseRelocationTable */
+	.quad	0				/* Debug */
+	.quad	0				/* Architecture */
+	.quad	0				/* Global Ptr */
+	.quad	0				/* TLS Table */
+	.quad	0				/* Load Config Table */
+	.quad	0				/* Bound Import */
+	.quad	0				/* IAT */
+	.quad	0				/* Delay Import Descriptor */
+	.quad	0				/* CLR Runtime Header */
+	.quad	0				/* Reserved */
+
+	/* Section table */
+section_table:
+
+	/*
+	 * The EFI application loader requires a relocation section
+	 * because EFI applications must be relocatable.  This is a
+	 * dummy section as far as we are concerned.
+	 */
+	.ascii	".reloc"
+	.byte	0
+	.byte	0			/* end of 0 padding of section name */
+	.long	0
+	.long	0
+	.long	0			/* SizeOfRawData */
+	.long	0			/* PointerToRawData */
+	.long	0			/* PointerToRelocations */
+	.long	0			/* PointerToLineNumbers */
+	.short	0			/* NumberOfRelocations */
+	.short	0			/* NumberOfLineNumbers */
+	.long	0x42100040		/* Characteristics (section flags) */
+
+
+	.ascii	".text"
+	.byte	0
+	.byte	0
+	.byte	0			/* end of 0 padding of section name */
+	.long	_edata - _start		/* VirtualSize */
+	.long	_start - ImageBase	/* VirtualAddress */
+	.long	_edata - _start		/* SizeOfRawData */
+	.long	_start - ImageBase	/* PointerToRawData */
+
+	.long	0		/* PointerToRelocations (0 for executables) */
+	.long	0		/* PointerToLineNumbers (0 for executables) */
+	.short	0		/* NumberOfRelocations  (0 for executables) */
+	.short	0		/* NumberOfLineNumbers  (0 for executables) */
+	.long	0xe0500020	/* Characteristics (section flags) */
+
+_start:
+	addi		sp, sp, -(SIZE_LONG * 3)
+	SAVE_LONG(a0, 0)
+	SAVE_LONG(a1, 1)
+	SAVE_LONG(ra, 2)
+
+	lla		a0, ImageBase
+	lla		a1, _DYNAMIC
+	call		_relocate
+	bne		a0, zero, 0f
+
+	LOAD_LONG(a1, 1)
+	LOAD_LONG(a0, 0)
+	call		efi_main
+
+	LOAD_LONG(ra, 2)
+
+0:	addi		sp, sp, (SIZE_LONG * 3)
+	ret
diff --git a/roms/u-boot/arch/riscv/lib/elf_riscv32_efi.lds b/roms/u-boot/arch/riscv/lib/elf_riscv32_efi.lds
new file mode 100644
index 000000000..629705fc2
--- /dev/null
+++ b/roms/u-boot/arch/riscv/lib/elf_riscv32_efi.lds
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * U-Boot riscv32 EFI linker script
+ *
+ * SPDX-License-Identifier:	BSD-2-Clause
+ *
+ * Modified from arch/arm/lib/elf_aarch64_efi.lds
+ */
+
+OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv")
+OUTPUT_ARCH(riscv)
+ENTRY(_start)
+SECTIONS
+{
+	.text 0x0 : {
+		_text = .;
+		*(.text.head)
+		*(.text)
+		*(.text.*)
+		*(.gnu.linkonce.t.*)
+		*(.srodata)
+		*(.rodata*)
+		. = ALIGN(16);
+	}
+	_etext = .;
+	_text_size = . - _text;
+	.dynamic  : { *(.dynamic) }
+	.data : {
+		_data = .;
+		*(.sdata)
+		*(.data)
+		*(.data1)
+		*(.data.*)
+		*(.got.plt)
+		*(.got)
+
+		/*
+		 * The EFI loader doesn't seem to like a .bss section, so we
+		 * stick it all into .data:
+		 */
+		. = ALIGN(16);
+		_bss = .;
+		*(.sbss)
+		*(.scommon)
+		*(.dynbss)
+		*(.bss)
+		*(.bss.*)
+		*(COMMON)
+		. = ALIGN(16);
+		_bss_end = .;
+		_edata = .;
+	}
+	.rela.dyn : { *(.rela.dyn) }
+	.rela.plt : { *(.rela.plt) }
+	.rela.got : { *(.rela.got) }
+	.rela.data : { *(.rela.data) *(.rela.data*) }
+	_data_size = . - _etext;
+
+	. = ALIGN(4096);
+	.dynsym   : { *(.dynsym) }
+	. = ALIGN(4096);
+	.dynstr   : { *(.dynstr) }
+	. = ALIGN(4096);
+	.note.gnu.build-id : { *(.note.gnu.build-id) }
+	/DISCARD/ : {
+		*(.rel.reloc)
+		*(.eh_frame)
+		*(.note.GNU-stack)
+	}
+	.comment 0 : { *(.comment) }
+}
diff --git a/roms/u-boot/arch/riscv/lib/elf_riscv64_efi.lds b/roms/u-boot/arch/riscv/lib/elf_riscv64_efi.lds
new file mode 100644
index 000000000..aece030c3
--- /dev/null
+++ b/roms/u-boot/arch/riscv/lib/elf_riscv64_efi.lds
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * U-Boot riscv64 EFI linker script
+ *
+ * SPDX-License-Identifier:	BSD-2-Clause
+ *
+ * Modified from arch/arm/lib/elf_aarch64_efi.lds
+ */
+
+OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv")
+OUTPUT_ARCH(riscv)
+ENTRY(_start)
+SECTIONS
+{
+	.text 0x0 : {
+		_text = .;
+		*(.text.head)
+		*(.text)
+		*(.text.*)
+		*(.gnu.linkonce.t.*)
+		*(.srodata)
+		*(.rodata*)
+		. = ALIGN(16);
+	}
+	_etext = .;
+	_text_size = . - _text;
+	.dynamic  : { *(.dynamic) }
+	.data : {
+		_data = .;
+		*(.sdata)
+		*(.data)
+		*(.data1)
+		*(.data.*)
+		*(.got.plt)
+		*(.got)
+
+		/*
+		 * The EFI loader doesn't seem to like a .bss section, so we
+		 * stick it all into .data:
+		 */
+		. = ALIGN(16);
+		_bss = .;
+		*(.sbss)
+		*(.scommon)
+		*(.dynbss)
+		*(.bss)
+		*(.bss.*)
+		*(COMMON)
+		. = ALIGN(16);
+		_bss_end = .;
+		_edata = .;
+	}
+	.rela.dyn : { *(.rela.dyn) }
+	.rela.plt : { *(.rela.plt) }
+	.rela.got : { *(.rela.got) }
+	.rela.data : { *(.rela.data) *(.rela.data*) }
+	_data_size = . - _etext;
+
+	. = ALIGN(4096);
+	.dynsym   : { *(.dynsym) }
+	. = ALIGN(4096);
+	.dynstr   : { *(.dynstr) }
+	. = ALIGN(4096);
+	.note.gnu.build-id : { *(.note.gnu.build-id) }
+	/DISCARD/ : {
+		*(.rel.reloc)
+		*(.eh_frame)
+		*(.note.GNU-stack)
+	}
+	.comment 0 : { *(.comment) }
+}
diff --git a/roms/u-boot/arch/riscv/lib/fdt_fixup.c b/roms/u-boot/arch/riscv/lib/fdt_fixup.c
new file mode 100644
index 000000000..f636b2844
--- /dev/null
+++ b/roms/u-boot/arch/riscv/lib/fdt_fixup.c
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates
+ *
+ */
+
+#define LOG_CATEGORY LOGC_ARCH
+
+#include <common.h>
+#include <fdt_support.h>
+#include <log.h>
+#include <mapmem.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * riscv_fdt_copy_resv_mem_node() - Copy reserve memory node entry
+ * @src: Pointer to the source device tree from which reserved memory node
+ *	 needs to be copied.
+ * @dst: Pointer to the destination device tree to which reserved memory node
+ *	 needs to be copied.
+ *
+ * Return: 0 on success or if source doesn't have reserved memory node.
+ *	   Error if copy process failed.
+ */
+int riscv_fdt_copy_resv_mem_node(const void *src, void *dst)
+{
+	u32 phandle;
+	struct fdt_memory pmp_mem;
+	fdt_addr_t addr;
+	fdt_size_t size;
+	int offset, node, err, rmem_offset;
+	bool nomap = true;
+	char basename[32] = {0};
+	int bname_len;
+	int max_len = sizeof(basename);
+	const char *name;
+	char *temp;
+
+	offset = fdt_path_offset(src, "/reserved-memory");
+	if (offset < 0) {
+		log_debug("No reserved memory region found in source FDT\n");
+		return 0;
+	}
+
+	/*
+	 * Extend the FDT by the following estimated size:
+	 *
+	 * Each PMP memory region entry occupies 64 bytes.
+	 * With 16 PMP memory regions we need 64 * 16 = 1024 bytes.
+	 */
+	err = fdt_open_into(dst, dst, fdt_totalsize(dst) + 1024);
+	if (err < 0) {
+		printf("Device Tree can't be expanded to accommodate new node");
+		return err;
+	}
+
+	fdt_for_each_subnode(node, src, offset) {
+		name = fdt_get_name(src, node, NULL);
+
+		addr = fdtdec_get_addr_size_auto_parent(src, offset, node,
+							"reg", 0, &size,
+							false);
+		if (addr == FDT_ADDR_T_NONE) {
+			log_debug("failed to read address/size for %s\n", name);
+			continue;
+		}
+		strncpy(basename, name, max_len);
+		temp = strchr(basename, '@');
+		if (temp) {
+			bname_len = strnlen(basename, max_len) - strnlen(temp,
+								       max_len);
+			*(basename + bname_len) = '\0';
+		}
+		pmp_mem.start = addr;
+		pmp_mem.end = addr + size - 1;
+		err = fdtdec_add_reserved_memory(dst, basename, &pmp_mem,
+						 &phandle, false);
+		if (err < 0 && err != -FDT_ERR_EXISTS) {
+			log_err("failed to add reserved memory: %d\n", err);
+			return err;
+		}
+		if (!fdt_getprop(src, node, "no-map", NULL))
+			nomap = false;
+		if (nomap) {
+			rmem_offset = fdt_node_offset_by_phandle(dst, phandle);
+			fdt_setprop_empty(dst, rmem_offset, "no-map");
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * riscv_board_reserved_mem_fixup() - Fix up reserved memory node for a board
+ * @fdt: Pointer to the device tree in which reserved memory node needs to be
+ *	 added.
+ *
+ * In RISC-V, any board needs to copy the reserved memory node from the device
+ * tree provided by the firmware to the device tree used by U-Boot. This is a
+ * common function that individual board fixup functions can invoke.
+ *
+ * Return: 0 on success or error otherwise.
+ */
+int riscv_board_reserved_mem_fixup(void *fdt)
+{
+	int err;
+	void *src_fdt_addr;
+
+	src_fdt_addr = map_sysmem(gd->arch.firmware_fdt_addr, 0);
+
+	/* avoid the copy if we are using the same device tree */
+	if (src_fdt_addr == fdt)
+		return 0;
+
+	err = riscv_fdt_copy_resv_mem_node(src_fdt_addr, fdt);
+	if (err < 0)
+		return err;
+
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_FIXUP
+int board_fix_fdt(void *fdt)
+{
+	int err;
+
+	err = riscv_board_reserved_mem_fixup(fdt);
+	if (err < 0) {
+		log_err("failed to fixup DT for reserved memory: %d\n", err);
+		return err;
+	}
+
+	return 0;
+}
+#endif
+
+int arch_fixup_fdt(void *blob)
+{
+	int err;
+#ifdef CONFIG_EFI_LOADER
+	u32 size;
+	int chosen_offset;
+
+	size = fdt_totalsize(blob);
+	err  = fdt_open_into(blob, blob, size + 32);
+	if (err < 0) {
+		log_err("Device Tree can't be expanded to accommodate new node");
+		return err;
+	}
+	chosen_offset = fdt_path_offset(blob, "/chosen");
+	if (chosen_offset < 0) {
+		chosen_offset = fdt_add_subnode(blob, 0, "chosen");
+		if (chosen_offset < 0) {
+			log_err("chosen node cannot be added\n");
+			return chosen_offset;
+		}
+	}
+	/* Overwrite the boot-hartid as U-Boot is the last stage BL */
+	err = fdt_setprop_u32(blob, chosen_offset, "boot-hartid",
+			      gd->arch.boot_hart);
+	if (err < 0)
+		return log_msg_ret("could not set boot-hartid", err);
+#endif
+
+	/* Copy the reserved-memory node to the DT used by OS */
+	err = riscv_fdt_copy_resv_mem_node(gd->fdt_blob, blob);
+	if (err < 0)
+		return err;
+
+	return 0;
+}
diff --git a/roms/u-boot/arch/riscv/lib/image.c b/roms/u-boot/arch/riscv/lib/image.c
new file mode 100644
index 000000000..47f2edcf7
--- /dev/null
+++ b/roms/u-boot/arch/riscv/lib/image.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Western Digital Corporation or its affiliates.
+ * Authors:
+ *	Atish Patra <atish.patra@wdc.com>
+ * Based on arm/lib/image.c
+ */
+
+#include <common.h>
+#include <image.h>
+#include <mapmem.h>
+#include <errno.h>
+#include <asm/global_data.h>
+#include <linux/sizes.h>
+#include <linux/stddef.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ASCII version of "RSC\0x5" defined in Linux kernel */
+#define LINUX_RISCV_IMAGE_MAGIC 0x05435352
+
+struct linux_image_h {
+	uint32_t	code0;		/* Executable code */
+	uint32_t	code1;		/* Executable code */
+	uint64_t	text_offset;	/* Image load offset */
+	uint64_t	image_size;	/* Effective Image size */
+	uint64_t	flags;		/* kernel flags (little endian) */
+	uint32_t	version;	/* version of the header */
+	uint32_t	res1;		/* reserved */
+	uint64_t	res2;		/* reserved */
+	uint64_t	res3;		/* reserved */
+	uint32_t	magic;		/* Magic number */
+	uint32_t	res4;		/* reserved */
+};
+
+int booti_setup(ulong image, ulong *relocated_addr, ulong *size,
+		bool force_reloc)
+{
+	struct linux_image_h *lhdr;
+
+	lhdr = (struct linux_image_h *)map_sysmem(image, 0);
+
+	if (lhdr->magic != LINUX_RISCV_IMAGE_MAGIC) {
+		puts("Bad Linux RISCV Image magic!\n");
+		return -EINVAL;
+	}
+
+	if (lhdr->image_size == 0) {
+		puts("Image lacks image_size field, error!\n");
+		return -EINVAL;
+	}
+	*size = lhdr->image_size;
+	*relocated_addr = gd->ram_base + lhdr->text_offset;
+
+	unmap_sysmem(lhdr);
+
+	return 0;
+}
diff --git a/roms/u-boot/arch/riscv/lib/interrupts.c b/roms/u-boot/arch/riscv/lib/interrupts.c
new file mode 100644
index 000000000..7525c152b
--- /dev/null
+++ b/roms/u-boot/arch/riscv/lib/interrupts.c
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2016-17 Microsemi Corporation.
+ * Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
+ *
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com>
+ */
+
+#include <common.h>
+#include <efi_loader.h>
+#include <hang.h>
+#include <irq_func.h>
+#include <asm/global_data.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#include <asm/encoding.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void show_efi_loaded_images(uintptr_t epc)
+{
+	efi_print_image_infos((void *)epc);
+}
+
+static void show_regs(struct pt_regs *regs)
+{
+#ifdef CONFIG_SHOW_REGS
+	printf("\nSP:  " REG_FMT " GP:  " REG_FMT " TP:  " REG_FMT "\n",
+	       regs->sp, regs->gp, regs->tp);
+	printf("T0:  " REG_FMT " T1:  " REG_FMT " T2:  " REG_FMT "\n",
+	       regs->t0, regs->t1, regs->t2);
+	printf("S0:  " REG_FMT " S1:  " REG_FMT " A0:  " REG_FMT "\n",
+	       regs->s0, regs->s1, regs->a0);
+	printf("A1:  " REG_FMT " A2:  " REG_FMT " A3:  " REG_FMT "\n",
+	       regs->a1, regs->a2, regs->a3);
+	printf("A4:  " REG_FMT " A5:  " REG_FMT " A6:  " REG_FMT "\n",
+	       regs->a4, regs->a5, regs->a6);
+	printf("A7:  " REG_FMT " S2:  " REG_FMT " S3:  " REG_FMT "\n",
+	       regs->a7, regs->s2, regs->s3);
+	printf("S4:  " REG_FMT " S5:  " REG_FMT " S6:  " REG_FMT "\n",
+	       regs->s4, regs->s5, regs->s6);
+	printf("S7:  " REG_FMT " S8:  " REG_FMT " S9:  " REG_FMT "\n",
+	       regs->s7, regs->s8, regs->s9);
+	printf("S10: " REG_FMT " S11: " REG_FMT " T3:  " REG_FMT "\n",
+	       regs->s10, regs->s11, regs->t3);
+	printf("T4:  " REG_FMT " T5:  " REG_FMT " T6:  " REG_FMT "\n",
+	       regs->t4, regs->t5, regs->t6);
+#endif
+}
+
+static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs)
+{
+	static const char * const exception_code[] = {
+		"Instruction address misaligned",
+		"Instruction access fault",
+		"Illegal instruction",
+		"Breakpoint",
+		"Load address misaligned",
+		"Load access fault",
+		"Store/AMO address misaligned",
+		"Store/AMO access fault",
+		"Environment call from U-mode",
+		"Environment call from S-mode",
+		"Reserved",
+		"Environment call from M-mode",
+		"Instruction page fault",
+		"Load page fault",
+		"Reserved",
+		"Store/AMO page fault",
+	};
+
+	if (code < ARRAY_SIZE(exception_code))
+		printf("Unhandled exception: %s\n", exception_code[code]);
+	else
+		printf("Unhandled exception code: %ld\n", code);
+
+	printf("EPC: " REG_FMT " RA: " REG_FMT " TVAL: " REG_FMT "\n",
+	       epc, regs->ra, tval);
+	/* Print relocation adjustments, but only if gd is initialized */
+	if (gd && gd->flags & GD_FLG_RELOC)
+		printf("EPC: " REG_FMT " RA: " REG_FMT " reloc adjusted\n",
+		       epc - gd->reloc_off, regs->ra - gd->reloc_off);
+
+	show_regs(regs);
+	show_efi_loaded_images(epc);
+	panic("\n");
+}
+
+int interrupt_init(void)
+{
+	return 0;
+}
+
+/*
+ * enable interrupts
+ */
+void enable_interrupts(void)
+{
+}
+
+/*
+ * disable interrupts
+ */
+int disable_interrupts(void)
+{
+	return 0;
+}
+
+ulong handle_trap(ulong cause, ulong epc, ulong tval, struct pt_regs *regs)
+{
+	ulong is_irq, irq;
+
+	/* An UEFI application may have changed gd. Restore U-Boot's gd. */
+	efi_restore_gd();
+
+	is_irq = (cause & MCAUSE_INT);
+	irq = (cause & ~MCAUSE_INT);
+
+	if (is_irq) {
+		switch (irq) {
+		case IRQ_M_EXT:
+		case IRQ_S_EXT:
+			external_interrupt(0);	/* handle external interrupt */
+			break;
+		case IRQ_M_TIMER:
+		case IRQ_S_TIMER:
+			timer_interrupt(0);	/* handle timer interrupt */
+			break;
+		default:
+			_exit_trap(cause, epc, tval, regs);
+			break;
+		};
+	} else {
+		_exit_trap(cause, epc, tval, regs);
+	}
+
+	return epc;
+}
+
+/*
+ *Entry Point for PLIC Interrupt Handler
+ */
+__attribute__((weak)) void external_interrupt(struct pt_regs *regs)
+{
+}
+
+__attribute__((weak)) void timer_interrupt(struct pt_regs *regs)
+{
+}
diff --git a/roms/u-boot/arch/riscv/lib/memcpy.S b/roms/u-boot/arch/riscv/lib/memcpy.S
new file mode 100644
index 000000000..00672c19a
--- /dev/null
+++ b/roms/u-boot/arch/riscv/lib/memcpy.S
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2013 Regents of the University of California
+ */
+
+#include <linux/linkage.h>
+#include <asm/asm.h>
+
+/* void *memcpy(void *, const void *, size_t) */
+ENTRY(__memcpy)
+WEAK(memcpy)
+	/* Save for return value */
+	mv	t6, a0
+
+	/*
+	 * Register allocation for code below:
+	 * a0 - start of uncopied dst
+	 * a1 - start of uncopied src
+	 * t0 - end of uncopied dst
+	 */
+	add	t0, a0, a2
+
+	/*
+	 * Use bytewise copy if too small.
+	 *
+	 * This threshold must be at least 2*SZREG to ensure at least one
+	 * wordwise copy is performed. It is chosen to be 16 because it will
+	 * save at least 7 iterations of bytewise copy, which pays off the
+	 * fixed overhead.
+	 */
+	li	a3, 16
+	bltu	a2, a3, .Lbyte_copy_tail
+
+	/*
+	 * Bytewise copy first to align a0 to word boundary.
+	 */
+	addi	a2, a0, SZREG-1
+	andi	a2, a2, ~(SZREG-1)
+	beq	a0, a2, 2f
+1:
+	lb	a5, 0(a1)
+	addi	a1, a1, 1
+	sb	a5, 0(a0)
+	addi	a0, a0, 1
+	bne	a0, a2, 1b
+2:
+
+	/*
+	 * Now a0 is word-aligned. If a1 is also word aligned, we could perform
+	 * aligned word-wise copy. Otherwise we need to perform misaligned
+	 * word-wise copy.
+	 */
+	andi	a3, a1, SZREG-1
+	bnez	a3, .Lmisaligned_word_copy
+
+	/* Unrolled wordwise copy */
+	addi	t0, t0, -(16*SZREG-1)
+	bgeu	a0, t0, 2f
+1:
+	REG_L	a2,        0(a1)
+	REG_L	a3,    SZREG(a1)
+	REG_L	a4,  2*SZREG(a1)
+	REG_L	a5,  3*SZREG(a1)
+	REG_L	a6,  4*SZREG(a1)
+	REG_L	a7,  5*SZREG(a1)
+	REG_L	t1,  6*SZREG(a1)
+	REG_L	t2,  7*SZREG(a1)
+	REG_L	t3,  8*SZREG(a1)
+	REG_L	t4,  9*SZREG(a1)
+	REG_L	t5, 10*SZREG(a1)
+	REG_S	a2,        0(a0)
+	REG_S	a3,    SZREG(a0)
+	REG_S	a4,  2*SZREG(a0)
+	REG_S	a5,  3*SZREG(a0)
+	REG_S	a6,  4*SZREG(a0)
+	REG_S	a7,  5*SZREG(a0)
+	REG_S	t1,  6*SZREG(a0)
+	REG_S	t2,  7*SZREG(a0)
+	REG_S	t3,  8*SZREG(a0)
+	REG_S	t4,  9*SZREG(a0)
+	REG_S	t5, 10*SZREG(a0)
+	REG_L	a2, 11*SZREG(a1)
+	REG_L	a3, 12*SZREG(a1)
+	REG_L	a4, 13*SZREG(a1)
+	REG_L	a5, 14*SZREG(a1)
+	REG_L	a6, 15*SZREG(a1)
+	addi	a1, a1, 16*SZREG
+	REG_S	a2, 11*SZREG(a0)
+	REG_S	a3, 12*SZREG(a0)
+	REG_S	a4, 13*SZREG(a0)
+	REG_S	a5, 14*SZREG(a0)
+	REG_S	a6, 15*SZREG(a0)
+	addi	a0, a0, 16*SZREG
+	bltu	a0, t0, 1b
+2:
+	/* Post-loop increment by 16*SZREG-1 and pre-loop decrement by SZREG-1 */
+	addi	t0, t0, 15*SZREG
+
+	/* Wordwise copy */
+	bgeu	a0, t0, 2f
+1:
+	REG_L	a5, 0(a1)
+	addi	a1, a1, SZREG
+	REG_S	a5, 0(a0)
+	addi	a0, a0, SZREG
+	bltu	a0, t0, 1b
+2:
+	addi	t0, t0, SZREG-1
+
+.Lbyte_copy_tail:
+	/*
+	 * Bytewise copy anything left.
+	 */
+	beq	a0, t0, 2f
+1:
+	lb	a5, 0(a1)
+	addi	a1, a1, 1
+	sb	a5, 0(a0)
+	addi	a0, a0, 1
+	bne	a0, t0, 1b
+2:
+
+	mv	a0, t6
+	ret
+
+.Lmisaligned_word_copy:
+	/*
+	 * Misaligned word-wise copy.
+	 * For misaligned copy we still perform word-wise copy, but we need to
+	 * use the value fetched from the previous iteration and do some shifts.
+	 * This is safe because we wouldn't access more words than necessary.
+	 */
+
+	/* Calculate shifts */
+	slli	t3, a3, 3
+	sub	t4, x0, t3 /* negate is okay as shift will only look at LSBs */
+
+	/* Load the initial value and align a1 */
+	andi	a1, a1, ~(SZREG-1)
+	REG_L	a5, 0(a1)
+
+	addi	t0, t0, -(SZREG-1)
+	/* At least one iteration will be executed here, no check */
+1:
+	srl	a4, a5, t3
+	REG_L	a5, SZREG(a1)
+	addi	a1, a1, SZREG
+	sll	a2, a5, t4
+	or	a2, a2, a4
+	REG_S	a2, 0(a0)
+	addi	a0, a0, SZREG
+	bltu	a0, t0, 1b
+
+	/* Update pointers to correct value */
+	addi	t0, t0, SZREG-1
+	add	a1, a1, a3
+
+	j	.Lbyte_copy_tail
+END(__memcpy)
diff --git a/roms/u-boot/arch/riscv/lib/memmove.S b/roms/u-boot/arch/riscv/lib/memmove.S
new file mode 100644
index 000000000..fbe6701db
--- /dev/null
+++ b/roms/u-boot/arch/riscv/lib/memmove.S
@@ -0,0 +1,128 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#include <linux/linkage.h>
+#include <asm/asm.h>
+
+ENTRY(__memmove)
+WEAK(memmove)
+	/*
+	 * Here we determine if forward copy is possible. Forward copy is
+	 * preferred to backward copy as it is more cache friendly.
+	 *
+	 * If a0 >= a1, t0 gives their distance, if t0 >= a2 then we can
+	 *   copy forward.
+	 * If a0 < a1, we can always copy forward. This will make t0 negative,
+	 *   so a *unsigned* comparison will always have t0 >= a2.
+	 *
+	 * For forward copy we just delegate the task to memcpy.
+	 */
+	sub	t0, a0, a1
+	bltu	t0, a2, 1f
+	tail	__memcpy
+1:
+
+	/*
+	 * Register allocation for code below:
+	 * a0 - end of uncopied dst
+	 * a1 - end of uncopied src
+	 * t0 - start of uncopied dst
+	 */
+	mv	t0, a0
+	add	a0, a0, a2
+	add	a1, a1, a2
+
+	/*
+	 * Use bytewise copy if too small.
+	 *
+	 * This threshold must be at least 2*SZREG to ensure at least one
+	 * wordwise copy is performed. It is chosen to be 16 because it will
+	 * save at least 7 iterations of bytewise copy, which pays off the
+	 * fixed overhead.
+	 */
+	li	a3, 16
+	bltu	a2, a3, .Lbyte_copy_tail
+
+	/*
+	 * Bytewise copy first to align t0 to word boundary.
+	 */
+	andi	a2, a0, ~(SZREG-1)
+	beq	a0, a2, 2f
+1:
+	addi	a1, a1, -1
+	lb	a5, 0(a1)
+	addi	a0, a0, -1
+	sb	a5, 0(a0)
+	bne	a0, a2, 1b
+2:
+
+	/*
+	 * Now a0 is word-aligned. If a1 is also word aligned, we could perform
+	 * aligned word-wise copy. Otherwise we need to perform misaligned
+	 * word-wise copy.
+	 */
+	andi	a3, a1, SZREG-1
+	bnez	a3, .Lmisaligned_word_copy
+
+	/* Wordwise copy */
+	addi	t0, t0, SZREG-1
+	bleu	a0, t0, 2f
+1:
+	addi	a1, a1, -SZREG
+	REG_L	a5, 0(a1)
+	addi	a0, a0, -SZREG
+	REG_S	a5, 0(a0)
+	bgtu	a0, t0, 1b
+2:
+	addi	t0, t0, -(SZREG-1)
+
+.Lbyte_copy_tail:
+	/*
+	 * Bytewise copy anything left.
+	 */
+	beq	a0, t0, 2f
+1:
+	addi	a1, a1, -1
+	lb	a5, 0(a1)
+	addi	a0, a0, -1
+	sb	a5, 0(a0)
+	bne	a0, t0, 1b
+2:
+
+	mv	a0, t0
+	ret
+
+.Lmisaligned_word_copy:
+	/*
+	 * Misaligned word-wise copy.
+	 * For misaligned copy we still perform word-wise copy, but we need to
+	 * use the value fetched from the previous iteration and do some shifts.
+	 * This is safe because we wouldn't access more words than necessary.
+	 */
+
+	/* Calculate shifts */
+	slli	t3, a3, 3
+	sub	t4, x0, t3 /* negate is okay as shift will only look at LSBs */
+
+	/* Load the initial value and align a1 */
+	andi	a1, a1, ~(SZREG-1)
+	REG_L	a5, 0(a1)
+
+	addi	t0, t0, SZREG-1
+	/* At least one iteration will be executed here, no check */
+1:
+	sll	a4, a5, t4
+	addi	a1, a1, -SZREG
+	REG_L	a5, 0(a1)
+	srl	a2, a5, t3
+	or	a2, a2, a4
+	addi	a0, a0, -SZREG
+	REG_S	a2, 0(a0)
+	bgtu	a0, t0, 1b
+
+	/* Update pointers to correct value */
+	addi	t0, t0, -(SZREG-1)
+	add	a1, a1, a3
+
+	j	.Lbyte_copy_tail
+
+END(__memmove)
diff --git a/roms/u-boot/arch/riscv/lib/memset.S b/roms/u-boot/arch/riscv/lib/memset.S
new file mode 100644
index 000000000..34c5360c6
--- /dev/null
+++ b/roms/u-boot/arch/riscv/lib/memset.S
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2013 Regents of the University of California
+ */
+
+
+#include <linux/linkage.h>
+#include <asm/asm.h>
+
+/* void *memset(void *, int, size_t) */
+ENTRY(__memset)
+WEAK(memset)
+	move t0, a0  /* Preserve return value */
+
+	/* Defer to byte-oriented fill for small sizes */
+	sltiu a3, a2, 16
+	bnez a3, 4f
+
+	/*
+	 * Round to nearest XLEN-aligned address
+	 * greater than or equal to start address
+	 */
+	addi a3, t0, SZREG-1
+	andi a3, a3, ~(SZREG-1)
+	beq a3, t0, 2f  /* Skip if already aligned */
+	/* Handle initial misalignment */
+	sub a4, a3, t0
+1:
+	sb a1, 0(t0)
+	addi t0, t0, 1
+	bltu t0, a3, 1b
+	sub a2, a2, a4  /* Update count */
+
+2: /* Duff's device with 32 XLEN stores per iteration */
+	/* Broadcast value into all bytes */
+	andi a1, a1, 0xff
+	slli a3, a1, 8
+	or a1, a3, a1
+	slli a3, a1, 16
+	or a1, a3, a1
+#ifdef CONFIG_64BIT
+	slli a3, a1, 32
+	or a1, a3, a1
+#endif
+
+	/* Calculate end address */
+	andi a4, a2, ~(SZREG-1)
+	add a3, t0, a4
+
+	andi a4, a4, 31*SZREG  /* Calculate remainder */
+	beqz a4, 3f            /* Shortcut if no remainder */
+	neg a4, a4
+	addi a4, a4, 32*SZREG  /* Calculate initial offset */
+
+	/* Adjust start address with offset */
+	sub t0, t0, a4
+
+	/* Jump into loop body */
+	/* Assumes 32-bit instruction lengths */
+	la a5, 3f
+#ifdef CONFIG_64BIT
+	srli a4, a4, 1
+#endif
+	add a5, a5, a4
+	jr a5
+3:
+	REG_S a1,        0(t0)
+	REG_S a1,    SZREG(t0)
+	REG_S a1,  2*SZREG(t0)
+	REG_S a1,  3*SZREG(t0)
+	REG_S a1,  4*SZREG(t0)
+	REG_S a1,  5*SZREG(t0)
+	REG_S a1,  6*SZREG(t0)
+	REG_S a1,  7*SZREG(t0)
+	REG_S a1,  8*SZREG(t0)
+	REG_S a1,  9*SZREG(t0)
+	REG_S a1, 10*SZREG(t0)
+	REG_S a1, 11*SZREG(t0)
+	REG_S a1, 12*SZREG(t0)
+	REG_S a1, 13*SZREG(t0)
+	REG_S a1, 14*SZREG(t0)
+	REG_S a1, 15*SZREG(t0)
+	REG_S a1, 16*SZREG(t0)
+	REG_S a1, 17*SZREG(t0)
+	REG_S a1, 18*SZREG(t0)
+	REG_S a1, 19*SZREG(t0)
+	REG_S a1, 20*SZREG(t0)
+	REG_S a1, 21*SZREG(t0)
+	REG_S a1, 22*SZREG(t0)
+	REG_S a1, 23*SZREG(t0)
+	REG_S a1, 24*SZREG(t0)
+	REG_S a1, 25*SZREG(t0)
+	REG_S a1, 26*SZREG(t0)
+	REG_S a1, 27*SZREG(t0)
+	REG_S a1, 28*SZREG(t0)
+	REG_S a1, 29*SZREG(t0)
+	REG_S a1, 30*SZREG(t0)
+	REG_S a1, 31*SZREG(t0)
+	addi t0, t0, 32*SZREG
+	bltu t0, a3, 3b
+	andi a2, a2, SZREG-1  /* Update count */
+
+4:
+	/* Handle trailing misalignment */
+	beqz a2, 6f
+	add a3, t0, a2
+5:
+	sb a1, 0(t0)
+	addi t0, t0, 1
+	bltu t0, a3, 5b
+6:
+	ret
+END(__memset)
diff --git a/roms/u-boot/arch/riscv/lib/reloc_riscv_efi.c b/roms/u-boot/arch/riscv/lib/reloc_riscv_efi.c
new file mode 100644
index 000000000..c1039dd16
--- /dev/null
+++ b/roms/u-boot/arch/riscv/lib/reloc_riscv_efi.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* reloc_riscv.c - position independent ELF shared object relocator
+   Copyright (C) 2018 Alexander Graf <agraf@suse.de>
+   Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
+   Copyright (C) 1999 Hewlett-Packard Co.
+	Contributed by David Mosberger <davidm@hpl.hp.com>.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without
+    modification, are permitted provided that the following conditions
+    are met:
+
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above
+      copyright notice, this list of conditions and the following
+      disclaimer in the documentation and/or other materials
+      provided with the distribution.
+    * Neither the name of Hewlett-Packard Co. nor the names of its
+      contributors may be used to endorse or promote products derived
+      from this software without specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+    CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+    INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+    BE LIABLE FOR ANYDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+    OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+    PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+    PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+    THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+    TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+    THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+    SUCH DAMAGE.
+*/
+
+#include <efi.h>
+
+#include <elf.h>
+
+#if __riscv_xlen == 64
+#define Elf_Dyn		Elf64_Dyn
+#define Elf_Rela	Elf64_Rela
+#define ELF_R_TYPE	ELF64_R_TYPE
+#else
+#define Elf_Dyn		Elf32_Dyn
+#define Elf_Rela	Elf32_Rela
+#define ELF_R_TYPE	ELF32_R_TYPE
+#endif
+
+efi_status_t EFIAPI _relocate(long ldbase, Elf_Dyn *dyn)
+{
+	long relsz = 0, relent = 0;
+	Elf_Rela *rel = 0;
+	unsigned long *addr;
+	int i;
+
+	for (i = 0; dyn[i].d_tag != DT_NULL; ++i) {
+		switch (dyn[i].d_tag) {
+		case DT_RELA:
+			rel = (Elf_Rela *)((ulong)dyn[i].d_un.d_ptr + ldbase);
+			break;
+		case DT_RELASZ:
+			relsz = dyn[i].d_un.d_val;
+			break;
+		case DT_RELAENT:
+			relent = dyn[i].d_un.d_val;
+			break;
+		default:
+			break;
+		}
+	}
+
+	if (!rel && relent == 0)
+		return EFI_SUCCESS;
+
+	if (!rel || relent == 0)
+		return EFI_LOAD_ERROR;
+
+	while (relsz > 0) {
+		/* apply the relocs */
+		switch (ELF_R_TYPE(rel->r_info)) {
+		case R_RISCV_RELATIVE:
+			addr = (ulong *)(ldbase + rel->r_offset);
+			*addr = ldbase + rel->r_addend;
+			break;
+		default:
+			/* Panic */
+			while (1) ;
+		}
+		rel = (Elf_Rela *)((char *)rel + relent);
+		relsz -= relent;
+	}
+	return EFI_SUCCESS;
+}
diff --git a/roms/u-boot/arch/riscv/lib/reset.c b/roms/u-boot/arch/riscv/lib/reset.c
new file mode 100644
index 000000000..8779c619c
--- /dev/null
+++ b/roms/u-boot/arch/riscv/lib/reset.c
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <hang.h>
+
+int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	printf("resetting ...\n");
+
+	printf("reset not supported yet\n");
+	hang();
+
+	return 0;
+}
diff --git a/roms/u-boot/arch/riscv/lib/sbi.c b/roms/u-boot/arch/riscv/lib/sbi.c
new file mode 100644
index 000000000..77845a73c
--- /dev/null
+++ b/roms/u-boot/arch/riscv/lib/sbi.c
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * SBI initialilization and all extension implementation.
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Taken from Linux arch/riscv/kernel/sbi.c
+ */
+
+#include <common.h>
+#include <asm/encoding.h>
+#include <asm/sbi.h>
+
+struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
+			unsigned long arg1, unsigned long arg2,
+			unsigned long arg3, unsigned long arg4,
+			unsigned long arg5)
+{
+	struct sbiret ret;
+
+	register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);
+	register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);
+	register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);
+	register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3);
+	register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4);
+	register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5);
+	register uintptr_t a6 asm ("a6") = (uintptr_t)(fid);
+	register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
+	asm volatile ("ecall"
+		      : "+r" (a0), "+r" (a1)
+		      : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)
+		      : "memory");
+	ret.error = a0;
+	ret.value = a1;
+
+	return ret;
+}
+
+/**
+ * sbi_set_timer() - Program the timer for next timer event.
+ * @stime_value: The value after which next timer event should fire.
+ *
+ * Return: None
+ */
+void sbi_set_timer(uint64_t stime_value)
+{
+#if __riscv_xlen == 32
+	sbi_ecall(SBI_EXT_SET_TIMER, SBI_FID_SET_TIMER, stime_value,
+		  stime_value >> 32, 0, 0, 0, 0);
+#else
+	sbi_ecall(SBI_EXT_SET_TIMER, SBI_FID_SET_TIMER, stime_value,
+		  0, 0, 0, 0, 0);
+#endif
+}
+
+/**
+ * sbi_get_spec_version() - get current SBI specification version
+ *
+ * Return: version id
+ */
+long sbi_get_spec_version(void)
+{
+	struct sbiret ret;
+
+	ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION,
+			0, 0, 0, 0, 0, 0);
+	if (!ret.error)
+		if (ret.value)
+			return ret.value;
+
+	return -ENOTSUPP;
+}
+
+/**
+ * sbi_get_impl_id() - get SBI implementation ID
+ *
+ * Return: implementation ID
+ */
+int sbi_get_impl_id(void)
+{
+	struct sbiret ret;
+
+	ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_ID,
+			0, 0, 0, 0, 0, 0);
+	if (!ret.error)
+		if (ret.value)
+			return ret.value;
+
+	return -ENOTSUPP;
+}
+
+/**
+ * sbi_probe_extension() - Check if an SBI extension ID is supported or not.
+ * @extid: The extension ID to be probed.
+ *
+ * Return: Extension specific nonzero value f yes, -ENOTSUPP otherwise.
+ */
+int sbi_probe_extension(int extid)
+{
+	struct sbiret ret;
+
+	ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, extid,
+			0, 0, 0, 0, 0);
+	if (!ret.error)
+		if (ret.value)
+			return ret.value;
+
+	return -ENOTSUPP;
+}
+
+#ifdef CONFIG_SBI_V01
+
+/**
+ * sbi_console_putchar() - Writes given character to the console device.
+ * @ch: The data to be written to the console.
+ *
+ * Return: None
+ */
+void sbi_console_putchar(int ch)
+{
+	sbi_ecall(SBI_EXT_0_1_CONSOLE_PUTCHAR, 0, ch, 0, 0, 0, 0, 0);
+}
+
+/**
+ * sbi_console_getchar() - Reads a byte from console device.
+ *
+ * Returns the value read from console.
+ */
+int sbi_console_getchar(void)
+{
+	struct sbiret ret;
+
+	ret = sbi_ecall(SBI_EXT_0_1_CONSOLE_GETCHAR, 0, 0, 0, 0, 0, 0, 0);
+
+	return ret.error;
+}
+
+/**
+ * sbi_clear_ipi() - Clear any pending IPIs for the calling hart.
+ *
+ * Return: None
+ */
+void sbi_clear_ipi(void)
+{
+	sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0);
+}
+
+/**
+ * sbi_shutdown() - Remove all the harts from executing supervisor code.
+ *
+ * Return: None
+ */
+void sbi_shutdown(void)
+{
+	sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0);
+}
+
+/**
+ * sbi_send_ipi() - Send an IPI to any hart.
+ * @hart_mask: A cpu mask containing all the target harts.
+ *
+ * Return: None
+ */
+void sbi_send_ipi(const unsigned long *hart_mask)
+{
+	sbi_ecall(SBI_EXT_SEND_IPI, SBI_FID_SEND_IPI, (unsigned long)hart_mask,
+		  0, 0, 0, 0, 0);
+}
+
+/**
+ * sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts.
+ * @hart_mask: A cpu mask containing all the target harts.
+ *
+ * Return: None
+ */
+void sbi_remote_fence_i(const unsigned long *hart_mask)
+{
+	sbi_ecall(SBI_EXT_REMOTE_FENCE_I, SBI_FID_REMOTE_FENCE_I,
+		  (unsigned long)hart_mask, 0, 0, 0, 0, 0);
+}
+
+/**
+ * sbi_remote_sfence_vma() - Execute SFENCE.VMA instructions on given remote
+ *			     harts for the specified virtual address range.
+ * @hart_mask: A cpu mask containing all the target harts.
+ * @start: Start of the virtual address
+ * @size: Total size of the virtual address range.
+ *
+ * Return: None
+ */
+void sbi_remote_sfence_vma(const unsigned long *hart_mask,
+			   unsigned long start,
+			   unsigned long size)
+{
+	sbi_ecall(SBI_EXT_REMOTE_SFENCE_VMA, SBI_FID_REMOTE_SFENCE_VMA,
+		  (unsigned long)hart_mask, start, size, 0, 0, 0);
+}
+
+/**
+ * sbi_remote_sfence_vma_asid() - Execute SFENCE.VMA instructions on given
+ * remote harts for a virtual address range belonging to a specific ASID.
+ *
+ * @hart_mask: A cpu mask containing all the target harts.
+ * @start: Start of the virtual address
+ * @size: Total size of the virtual address range.
+ * @asid: The value of address space identifier (ASID).
+ *
+ * Return: None
+ */
+void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
+				unsigned long start,
+				unsigned long size,
+				unsigned long asid)
+{
+	sbi_ecall(SBI_EXT_REMOTE_SFENCE_VMA_ASID,
+		  SBI_FID_REMOTE_SFENCE_VMA_ASID,
+		  (unsigned long)hart_mask, start, size, asid, 0, 0);
+}
+
+#endif /* CONFIG_SBI_V01 */
diff --git a/roms/u-boot/arch/riscv/lib/sbi_ipi.c b/roms/u-boot/arch/riscv/lib/sbi_ipi.c
new file mode 100644
index 000000000..d02e2b4c4
--- /dev/null
+++ b/roms/u-boot/arch/riscv/lib/sbi_ipi.c
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Fraunhofer AISEC,
+ * Lukas Auer <lukas.auer@aisec.fraunhofer.de>
+ */
+
+#include <common.h>
+#include <asm/encoding.h>
+#include <asm/sbi.h>
+
+int riscv_init_ipi(void)
+{
+	return 0;
+}
+
+int riscv_send_ipi(int hart)
+{
+	ulong mask;
+
+	mask = 1UL << hart;
+	sbi_send_ipi(&mask);
+
+	return 0;
+}
+
+int riscv_clear_ipi(int hart)
+{
+	csr_clear(CSR_SIP, SIP_SSIP);
+
+	return 0;
+}
+
+int riscv_get_ipi(int hart, int *pending)
+{
+	/*
+	 * The SBI does not support reading the IPI status. We always return 0
+	 * to indicate that no IPI is pending.
+	 */
+	*pending = 0;
+
+	return 0;
+}
diff --git a/roms/u-boot/arch/riscv/lib/setjmp.S b/roms/u-boot/arch/riscv/lib/setjmp.S
new file mode 100644
index 000000000..99d619582
--- /dev/null
+++ b/roms/u-boot/arch/riscv/lib/setjmp.S
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) 2018 Alexander Graf <agraf@suse.de>
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+#ifdef CONFIG_ARCH_RV64I
+#define STORE_IDX(reg, idx)	sd reg, (idx*8)(a0)
+#define LOAD_IDX(reg, idx)	ld reg, (idx*8)(a0)
+#else
+#define STORE_IDX(reg, idx)	sw reg, (idx*4)(a0)
+#define LOAD_IDX(reg, idx)	lw reg, (idx*4)(a0)
+#endif
+
+.pushsection .text.setjmp, "ax"
+ENTRY(setjmp)
+	/* Preserve all callee-saved registers and the SP */
+	STORE_IDX(s0, 0)
+	STORE_IDX(s1, 1)
+	STORE_IDX(s2, 2)
+	STORE_IDX(s3, 3)
+	STORE_IDX(s4, 4)
+	STORE_IDX(s5, 5)
+	STORE_IDX(s6, 6)
+	STORE_IDX(s7, 7)
+	STORE_IDX(s8, 8)
+	STORE_IDX(s9, 9)
+	STORE_IDX(s10, 10)
+	STORE_IDX(s11, 11)
+	STORE_IDX(ra, 12)
+	STORE_IDX(sp, 13)
+	li  a0, 0
+	ret
+ENDPROC(setjmp)
+.popsection
+
+.pushsection .text.longjmp, "ax"
+ENTRY(longjmp)
+	LOAD_IDX(s0, 0)
+	LOAD_IDX(s1, 1)
+	LOAD_IDX(s2, 2)
+	LOAD_IDX(s3, 3)
+	LOAD_IDX(s4, 4)
+	LOAD_IDX(s5, 5)
+	LOAD_IDX(s6, 6)
+	LOAD_IDX(s7, 7)
+	LOAD_IDX(s8, 8)
+	LOAD_IDX(s9, 9)
+	LOAD_IDX(s10, 10)
+	LOAD_IDX(s11, 11)
+	LOAD_IDX(ra, 12)
+	LOAD_IDX(sp, 13)
+
+	/* Move the return value in place, but return 1 if passed 0. */
+	seqz a0, a1
+	add a0, a0, a1
+	ret
+ENDPROC(longjmp)
+.popsection
diff --git a/roms/u-boot/arch/riscv/lib/sifive_clint.c b/roms/u-boot/arch/riscv/lib/sifive_clint.c
new file mode 100644
index 000000000..ab22395c5
--- /dev/null
+++ b/roms/u-boot/arch/riscv/lib/sifive_clint.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT).
+ * The CLINT block holds memory-mapped control and status registers
+ * associated with software and timer interrupts.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/smp.h>
+#include <linux/err.h>
+
+/* MSIP registers */
+#define MSIP_REG(base, hart)		((ulong)(base) + (hart) * 4)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int riscv_init_ipi(void)
+{
+	int ret;
+	struct udevice *dev;
+
+	ret = uclass_get_device_by_driver(UCLASS_TIMER,
+					  DM_DRIVER_GET(sifive_clint), &dev);
+	if (ret)
+		return ret;
+
+	gd->arch.clint = dev_read_addr_ptr(dev);
+	if (!gd->arch.clint)
+		return -EINVAL;
+
+	return 0;
+}
+
+int riscv_send_ipi(int hart)
+{
+	writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
+
+	return 0;
+}
+
+int riscv_clear_ipi(int hart)
+{
+	writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
+
+	return 0;
+}
+
+int riscv_get_ipi(int hart, int *pending)
+{
+	*pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart));
+
+	return 0;
+}
diff --git a/roms/u-boot/arch/riscv/lib/smp.c b/roms/u-boot/arch/riscv/lib/smp.c
new file mode 100644
index 000000000..ba992100a
--- /dev/null
+++ b/roms/u-boot/arch/riscv/lib/smp.c
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Fraunhofer AISEC,
+ * Lukas Auer <lukas.auer@aisec.fraunhofer.de>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <asm/barrier.h>
+#include <asm/global_data.h>
+#include <asm/smp.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int send_ipi_many(struct ipi_data *ipi, int wait)
+{
+	ofnode node, cpus;
+	u32 reg;
+	int ret, pending;
+
+	cpus = ofnode_path("/cpus");
+	if (!ofnode_valid(cpus)) {
+		pr_err("Can't find cpus node!\n");
+		return -EINVAL;
+	}
+
+	ofnode_for_each_subnode(node, cpus) {
+		/* skip if hart is marked as not available in the device tree */
+		if (!ofnode_is_available(node))
+			continue;
+
+		/* read hart ID of CPU */
+		ret = ofnode_read_u32(node, "reg", &reg);
+		if (ret)
+			continue;
+
+		/* skip if it is the hart we are running on */
+		if (reg == gd->arch.boot_hart)
+			continue;
+
+		if (reg >= CONFIG_NR_CPUS) {
+			pr_err("Hart ID %d is out of range, increase CONFIG_NR_CPUS\n",
+			       reg);
+			continue;
+		}
+
+#ifndef CONFIG_XIP
+		/* skip if hart is not available */
+		if (!(gd->arch.available_harts & (1 << reg)))
+			continue;
+#endif
+
+		gd->arch.ipi[reg].addr = ipi->addr;
+		gd->arch.ipi[reg].arg0 = ipi->arg0;
+		gd->arch.ipi[reg].arg1 = ipi->arg1;
+
+		/*
+		 * Ensure valid only becomes set when the IPI parameters are
+		 * set. An IPI may already be pending on other harts, so we
+		 * need a way to signal that the IPI device has been
+		 * initialized, and that it is ok to call the function.
+		 */
+		__smp_store_release(&gd->arch.ipi[reg].valid, 1);
+
+		ret = riscv_send_ipi(reg);
+		if (ret) {
+			pr_err("Cannot send IPI to hart %d\n", reg);
+			return ret;
+		}
+
+		if (wait) {
+			pending = 1;
+			while (pending) {
+				ret = riscv_get_ipi(reg, &pending);
+				if (ret)
+					return ret;
+			}
+		}
+	}
+
+	return 0;
+}
+
+void handle_ipi(ulong hart)
+{
+	int ret;
+	void (*smp_function)(ulong hart, ulong arg0, ulong arg1);
+
+	if (hart >= CONFIG_NR_CPUS)
+		return;
+
+	/*
+	 * If valid is not set, then U-Boot has not requested the IPI. The
+	 * IPI device may not be initialized, so all we can do is wait for
+	 * U-Boot to initialize it and send an IPI
+	 */
+	if (!__smp_load_acquire(&gd->arch.ipi[hart].valid))
+		return;
+
+	smp_function = (void (*)(ulong, ulong, ulong))gd->arch.ipi[hart].addr;
+	invalidate_icache_all();
+
+	/*
+	 * Clear the IPI to acknowledge the request before jumping to the
+	 * requested function.
+	 */
+	ret = riscv_clear_ipi(hart);
+	if (ret) {
+		pr_err("Cannot clear IPI of hart %ld (error %d)\n", hart, ret);
+		return;
+	}
+
+	smp_function(hart, gd->arch.ipi[hart].arg0, gd->arch.ipi[hart].arg1);
+}
+
+int smp_call_function(ulong addr, ulong arg0, ulong arg1, int wait)
+{
+	struct ipi_data ipi = {
+		.addr = addr,
+		.arg0 = arg0,
+		.arg1 = arg1,
+	};
+
+	return send_ipi_many(&ipi, wait);
+}
diff --git a/roms/u-boot/arch/riscv/lib/spl.c b/roms/u-boot/arch/riscv/lib/spl.c
new file mode 100644
index 000000000..8baee07be
--- /dev/null
+++ b/roms/u-boot/arch/riscv/lib/spl.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Fraunhofer AISEC,
+ * Lukas Auer <lukas.auer@aisec.fraunhofer.de>
+ */
+#include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <asm/smp.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak int spl_board_init_f(void)
+{
+	return 0;
+}
+
+__weak void board_init_f(ulong dummy)
+{
+	int ret;
+
+	ret = spl_early_init();
+	if (ret)
+		panic("spl_early_init() failed: %d\n", ret);
+
+	arch_cpu_init_dm();
+
+	preloader_console_init();
+
+	ret = spl_board_init_f();
+	if (ret)
+		panic("spl_board_init_f() failed: %d\n", ret);
+}
+
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+	typedef void __noreturn (*image_entry_riscv_t)(ulong hart, void *dtb);
+	void *fdt_blob;
+	__maybe_unused int ret;
+
+#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
+	fdt_blob = spl_image->fdt_addr;
+#else
+	fdt_blob = (void *)gd->fdt_blob;
+#endif
+
+	image_entry_riscv_t image_entry =
+		(image_entry_riscv_t)spl_image->entry_point;
+	invalidate_icache_all();
+
+	debug("image entry point: 0x%lX\n", spl_image->entry_point);
+#ifdef CONFIG_SPL_SMP
+	ret = smp_call_function(spl_image->entry_point, (ulong)fdt_blob, 0, 0);
+	if (ret)
+		hang();
+#endif
+	image_entry(gd->arch.boot_hart, fdt_blob);
+}