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author | 2023-10-10 14:33:42 +0000 | |
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committer | 2023-10-10 14:33:42 +0000 | |
commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/arch/sh/include/asm/cpu_sh4.h | |
parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/u-boot/arch/sh/include/asm/cpu_sh4.h')
-rw-r--r-- | roms/u-boot/arch/sh/include/asm/cpu_sh4.h | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/roms/u-boot/arch/sh/include/asm/cpu_sh4.h b/roms/u-boot/arch/sh/include/asm/cpu_sh4.h new file mode 100644 index 000000000..ed7c243b3 --- /dev/null +++ b/roms/u-boot/arch/sh/include/asm/cpu_sh4.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + */ + +#ifndef _ASM_CPU_SH4_H_ +#define _ASM_CPU_SH4_H_ + +/* cache control */ +#define CCR_CACHE_STOP 0x00000808 +#define CCR_CACHE_ENABLE 0x00000101 +#define CCR_CACHE_ICI 0x00000800 + +#define CACHE_OC_ADDRESS_ARRAY 0xf4000000 + +#if defined (CONFIG_CPU_SH7750) || \ + defined(CONFIG_CPU_SH7751) +#define CACHE_OC_WAY_SHIFT 14 +#define CACHE_OC_NUM_ENTRIES 512 +#else +#define CACHE_OC_WAY_SHIFT 13 +#define CACHE_OC_NUM_ENTRIES 256 +#endif +#define CACHE_OC_ENTRY_SHIFT 5 + +#if defined (CONFIG_CPU_SH7750) || \ + defined(CONFIG_CPU_SH7751) +# include <asm/cpu_sh7750.h> +#elif defined (CONFIG_CPU_SH7722) +# include <asm/cpu_sh7722.h> +#elif defined (CONFIG_CPU_SH7723) +# include <asm/cpu_sh7723.h> +#elif defined (CONFIG_CPU_SH7734) +# include <asm/cpu_sh7734.h> +#elif defined (CONFIG_CPU_SH7752) +# include <asm/cpu_sh7752.h> +#elif defined (CONFIG_CPU_SH7753) +# include <asm/cpu_sh7753.h> +#elif defined (CONFIG_CPU_SH7757) +# include <asm/cpu_sh7757.h> +#elif defined (CONFIG_CPU_SH7763) +# include <asm/cpu_sh7763.h> +#elif defined (CONFIG_CPU_SH7780) +# include <asm/cpu_sh7780.h> +#else +# error "Unknown SH4 variant" +#endif + +#endif /* _ASM_CPU_SH4_H_ */ |