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authorAngelos Mouzakitis <a.mouzakitis@virtualopensystems.com>2023-10-10 14:33:42 +0000
committerAngelos Mouzakitis <a.mouzakitis@virtualopensystems.com>2023-10-10 14:33:42 +0000
commitaf1a266670d040d2f4083ff309d732d648afba2a (patch)
tree2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/arch/x86/cpu/baytrail/valleyview.c
parente02cda008591317b1625707ff8e115a4841aa889 (diff)
Add submodule dependency filesHEADmaster
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/u-boot/arch/x86/cpu/baytrail/valleyview.c')
-rw-r--r--roms/u-boot/arch/x86/cpu/baytrail/valleyview.c59
1 files changed, 59 insertions, 0 deletions
diff --git a/roms/u-boot/arch/x86/cpu/baytrail/valleyview.c b/roms/u-boot/arch/x86/cpu/baytrail/valleyview.c
new file mode 100644
index 000000000..f73738ce5
--- /dev/null
+++ b/roms/u-boot/arch/x86/cpu/baytrail/valleyview.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <mmc.h>
+#include <pci_ids.h>
+#include <asm/irq.h>
+#include <asm/mrccache.h>
+#include <asm/post.h>
+#include <asm/arch/iomap.h>
+#include <linux/bitops.h>
+
+/* GPIO SUS */
+#define GPIO_SUS_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS)
+#define GPIO_SUS_DFX5_CONF0 0x150
+#define BYT_TRIG_LVL BIT(24)
+#define BYT_TRIG_POS BIT(25)
+
+int arch_cpu_init(void)
+{
+ post_code(POST_CPU_INIT);
+
+ return x86_cpu_init_f();
+}
+
+int arch_misc_init(void)
+{
+ if (!ll_boot_init())
+ return 0;
+
+#ifdef CONFIG_ENABLE_MRC_CACHE
+ /*
+ * We intend not to check any return value here, as even MRC cache
+ * is not saved successfully, it is not a severe error that will
+ * prevent system from continuing to boot.
+ */
+ mrccache_save();
+#endif
+
+ /*
+ * For some unknown reason, FSP (gold4) for BayTrail configures
+ * the GPIO DFX5 PAD to enable level interrupt (bit 24 and 25).
+ * This does not cause any issue when Linux kernel runs w/ or w/o
+ * the pinctrl driver for BayTrail. However this causes unstable
+ * S3 resume if the pinctrl driver is included in the kernel build.
+ * As this pin keeps generating interrupts during an S3 resume,
+ * and there is no IRQ requester in the kernel to handle it, the
+ * kernel seems to hang and does not continue resuming.
+ *
+ * Clear the mysterious interrupt bits for this pin.
+ */
+ clrbits_le32(GPIO_SUS_PAD_BASE + GPIO_SUS_DFX5_CONF0,
+ BYT_TRIG_LVL | BYT_TRIG_POS);
+
+ return 0;
+}