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author | 2023-10-10 14:33:42 +0000 | |
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committer | 2023-10-10 14:33:42 +0000 | |
commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/arch/x86/include/asm/arch-apollolake/acpi/southbridge.asl | |
parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/u-boot/arch/x86/include/asm/arch-apollolake/acpi/southbridge.asl')
-rw-r--r-- | roms/u-boot/arch/x86/include/asm/arch-apollolake/acpi/southbridge.asl | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/roms/u-boot/arch/x86/include/asm/arch-apollolake/acpi/southbridge.asl b/roms/u-boot/arch/x86/include/asm/arch-apollolake/acpi/southbridge.asl new file mode 100644 index 000000000..08290194f --- /dev/null +++ b/roms/u-boot/arch/x86/include/asm/arch-apollolake/acpi/southbridge.asl @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) + */ + +#include <p2sb.h> +#include <asm/arch/gpe.h> + +/* PCIE device */ +#include "pcie.asl" + +/* LPSS device */ +#include "lpss.asl" + +/* PCI IRQ assignment */ +#include "pci_irqs.asl" + +/* GPIO controller */ +#include "gpio.asl" + +#include "xhci.asl" + +/* LPC */ +#include <asm/acpi/lpc.asl> + +/* eMMC */ +#include "scs.asl" + +/* PMC IPC controller */ +#include "pmc_ipc.asl" + +/* PCI _OSC */ +#include <asm/acpi/pci_osc.asl> |