Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

16 files changed, 756 insertions, 0 deletions

diff --git a/roms/u-boot/board/alliedtelesis/SBx81LIFKW/Kconfig b/roms/u-boot/board/alliedtelesis/SBx81LIFKW/Kconfig
new file mode 100644
index 000000000..5c2609b7f
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/SBx81LIFKW/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SBx81LIFKW
+
+config SYS_BOARD
+       default "SBx81LIFKW"
+
+config SYS_VENDOR
+       default "alliedtelesis"
+
+config SYS_CONFIG_NAME
+       default "SBx81LIFKW"
+
+endif
diff --git a/roms/u-boot/board/alliedtelesis/SBx81LIFKW/MAINTAINERS b/roms/u-boot/board/alliedtelesis/SBx81LIFKW/MAINTAINERS
new file mode 100644
index 000000000..31ccec0e9
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/SBx81LIFKW/MAINTAINERS
@@ -0,0 +1,7 @@
+SBx81LIFKW BOARD
+M:	Chris Packham <chris.packham@alliedtelesis.co.nz>
+S:	Maintained
+F:	board/alliedtelesis/SBx81LIFKW/
+F:	include/configs/SBx81LIFKW
+F:	configs/SBx81LIFKW_defconfig
+F:	arch/arm/dts/kirkwood-atl-sbx81lifkw.dts
diff --git a/roms/u-boot/board/alliedtelesis/SBx81LIFKW/Makefile b/roms/u-boot/board/alliedtelesis/SBx81LIFKW/Makefile
new file mode 100644
index 000000000..806020ed8
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/SBx81LIFKW/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2010, 2018
+# Allied Telesis <www.alliedtelesis.com>
+#
+
+obj-y	+= sbx81lifkw.o
diff --git a/roms/u-boot/board/alliedtelesis/SBx81LIFKW/kwbimage.cfg b/roms/u-boot/board/alliedtelesis/SBx81LIFKW/kwbimage.cfg
new file mode 100644
index 000000000..9726f15e2
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/SBx81LIFKW/kwbimage.cfg
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2018 Allied Telesis
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+DATA 0xffd100e0 0x1b1b1b1b
+DATA 0xffd20134 0xffffffff
+DATA 0xffd20138 0x009fffff
+DATA 0xffd20154 0x00000000
+DATA 0xffd2014c 0x00000000
+DATA 0xffd20148 0x00000001
+
+# Dram initalization for 1 x x16
+#  DDR II Micron part number MT47H64M16HR-3
+#  MClk 333MHz, Size 128MB, ECC disable
+#
+DATA 0xffd01400 0x43000618
+DATA 0xffd01404 0x35143000
+DATA 0xffd01408 0x11012227
+DATA 0xffd0140c 0x00000819
+DATA 0xffd01410 0x0000000d
+DATA 0xffd01414 0x00000000
+DATA 0xffd01418 0x00000000
+DATA 0xffd0141c 0x00000632
+DATA 0xffd01420 0x00000040
+DATA 0xffd01424 0x0000f07f
+DATA 0xffd01500 0x00000000	# SDRAM CS[0] Base address at 0x00000000
+DATA 0xffd01504 0x07FFFFF1	# SDRAM CS[0] Size 128MiB
+DATA 0xffd01508 0x10000000
+DATA 0xffd0150c 0x00FFFFF4	# SDRAM CS[1] Size, window disabled
+DATA 0xffd01514 0x00FFFFF8	# SDRAM CS[2] Size, window disabled
+DATA 0xffd0151c 0x00FFFFFC	# SDRAM CS[3] Size, window disabled
+DATA 0xffd01494 0x00030000
+DATA 0xffd01498 0x00000000
+DATA 0xffd0149c 0x0000e803
+DATA 0xffd01480 0x00000001
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c b/roms/u-boot/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c
new file mode 100644
index 000000000..d8b9fdfe3
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010, 2018
+ * Allied Telesis <www.alliedtelesis.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <status_led.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+/* Note: GPIO differences between specific boards
+ *
+ * We're trying to avoid having multiple build targets for all the Kirkwood
+ * based boards one area where things tend to differ is GPIO usage. For the
+ * most part the GPIOs driven by the bootloader are similar enough in function
+ * that there is no harm in driving them.
+ *
+ *         XZ4  XS6     XS16  GS24A         GT40   GP24A         GT24A
+ * GPIO39  -    INT(<)  NC    MUX_RST_N(>)  NC     POE_DIS_N(>)  NC
+ */
+
+#define SBX81LIFKW_OE_LOW	~(BIT(31) | BIT(30) | BIT(28) | BIT(27) | \
+				  BIT(18) | BIT(17) | BIT(13) | BIT(12) | \
+				  BIT(10))
+#define SBX81LIFKW_OE_HIGH	~(BIT(0) | BIT(1) | BIT(7))
+#define SBX81LIFKW_OE_VAL_LOW	 (BIT(31) | BIT(30) | BIT(28) | BIT(27))
+#define SBX81LIFKW_OE_VAL_HIGH	 (BIT(0) | BIT(1))
+
+#define MV88E6097_RESET		27
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct led {
+	u32 reg;
+	u32 value;
+	u32 mask;
+};
+
+struct led amber_solid = {
+	MVEBU_GPIO0_BASE,
+	BIT(10),
+	BIT(18) | BIT(10)
+};
+
+struct led green_solid = {
+	MVEBU_GPIO0_BASE,
+	BIT(18) | BIT(10),
+	BIT(18) | BIT(10)
+};
+
+struct led amber_flash = {
+	MVEBU_GPIO0_BASE,
+	0,
+	BIT(18) | BIT(10)
+};
+
+struct led green_flash = {
+	MVEBU_GPIO0_BASE,
+	BIT(18),
+	BIT(18) | BIT(10)
+};
+
+static void status_led_set(struct led *led)
+{
+	clrsetbits_le32(led->reg, led->mask, led->value);
+}
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the  below configuration configures mainly initial LED status
+	 */
+	mvebu_config_gpio(SBX81LIFKW_OE_VAL_LOW,
+			  SBX81LIFKW_OE_VAL_HIGH,
+			  SBX81LIFKW_OE_LOW, SBX81LIFKW_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	static const u32 kwmpp_config[] = {
+		MPP0_SPI_SCn,
+		MPP1_SPI_MOSI,
+		MPP2_SPI_SCK,
+		MPP3_SPI_MISO,
+		MPP4_UART0_RXD,
+		MPP5_UART0_TXD,
+		MPP6_SYSRST_OUTn,
+		MPP7_PEX_RST_OUTn,
+		MPP8_TW_SDA,
+		MPP9_TW_SCK,
+		MPP10_GPO,
+		MPP11_GPIO,
+		MPP12_GPO,
+		MPP13_GPIO,
+		MPP14_GPIO,
+		MPP15_UART0_RTS,
+		MPP16_UART0_CTS,
+		MPP17_GPIO,
+		MPP18_GPO,
+		MPP19_GPO,
+		MPP20_GPIO,
+		MPP21_GPIO,
+		MPP22_GPIO,
+		MPP23_GPIO,
+		MPP24_GPIO,
+		MPP25_GPIO,
+		MPP26_GPIO,
+		MPP27_GPIO,
+		MPP28_GPIO,
+		MPP29_GPIO,
+		MPP30_GPIO,
+		MPP31_GPIO,
+		MPP32_GPIO,
+		MPP33_GPIO,
+		MPP34_GPIO,
+		MPP35_GPIO,
+		MPP36_GPIO,
+		MPP37_GPIO,
+		MPP38_GPIO,
+		MPP39_GPIO,
+		MPP40_GPIO,
+		MPP41_GPIO,
+		MPP42_GPIO,
+		MPP43_GPIO,
+		MPP44_GPIO,
+		MPP45_GPIO,
+		MPP46_GPIO,
+		MPP47_GPIO,
+		MPP48_GPIO,
+		MPP49_GPIO,
+		0
+	};
+
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Power-down unused subsystems. The required
+	 * subsystems are:
+	 *
+	 *  GE0         b0
+	 *  PEX0 PHY    b1
+	 *  PEX0.0      b2
+	 *  TSU         b5
+	 *  SDRAM       b6
+	 *  RUNIT       b7
+	 */
+	writel((BIT(0) | BIT(1) | BIT(2) |
+		BIT(5) | BIT(6) | BIT(7)),
+		KW_CPU_REG_BASE + 0x1c);
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	status_led_set(&amber_solid);
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* automatically defined by kirkwood config.h */
+void reset_phy(void)
+{
+}
+#endif
+
+#ifdef CONFIG_MV88E61XX_SWITCH
+int mv88e61xx_hw_reset(struct phy_device *phydev)
+{
+	/* Ensure the 88e6097 gets at least 10ms Reset
+	 */
+	kw_gpio_set_value(MV88E6097_RESET, 0);
+	mdelay(20);
+	kw_gpio_set_value(MV88E6097_RESET, 1);
+	mdelay(20);
+
+	phydev->advertising = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	status_led_set(&green_flash);
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/Kconfig b/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/Kconfig
new file mode 100644
index 000000000..524c29008
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SBx81LIFXCAT
+
+config SYS_BOARD
+       default "SBx81LIFXCAT"
+
+config SYS_VENDOR
+       default "alliedtelesis"
+
+config SYS_CONFIG_NAME
+       default "SBx81LIFXCAT"
+
+endif
diff --git a/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/MAINTAINERS b/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/MAINTAINERS
new file mode 100644
index 000000000..6b722ded2
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/MAINTAINERS
@@ -0,0 +1,7 @@
+SBx81LIFXCAT BOARD
+M:	Chris Packham <chris.packham@alliedtelesis.co.nz>
+S:	Maintained
+F:	board/alliedtelesis/SBx81LIFXCAT/
+F:	include/configs/SBx81LIFXCAT
+F:	configs/SBx81LIFXCAT_defconfig
+F:	arch/arm/dts/kirkwood-atl-sbx81lifxcat.dts
diff --git a/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/Makefile b/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/Makefile
new file mode 100644
index 000000000..f21c8ef9d
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2010, 2018
+# Allied Telesis <www.alliedtelesis.com>
+#
+
+obj-y	+= sbx81lifxcat.o
diff --git a/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/kwbimage.cfg b/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/kwbimage.cfg
new file mode 100644
index 000000000..53d4812f3
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/kwbimage.cfg
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2018 Allied Telesis
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+DATA 0xffd100e0 0x1b1b1b1b
+DATA 0xffd20134 0xffffffff
+DATA 0xffd20138 0x009fffff
+DATA 0xffd20154 0x00000000
+DATA 0xffd2014c 0x00000000
+DATA 0xffd20148 0x00000001
+
+# Dram initalization for 1 x x16
+#  DDR II Micron part number MT47H64M16HR-3
+#  MClk 333MHz, Size 128MB, ECC disable
+#
+DATA 0xffd01400 0x43000618
+DATA 0xffd01404 0x38543000
+DATA 0xffd01408 0x23125441
+DATA 0xffd0140c 0x00000832
+DATA 0xffd01410 0x0000000D
+DATA 0xffd01414 0x00000000
+DATA 0xffd01418 0x00000000
+DATA 0xffd0141c 0x00000652
+DATA 0xffd01420 0x00000042
+DATA 0xffd01424 0x0000F0FF
+DATA 0xffd01428 0x00074410
+DATA 0xffd0147C 0x00007441
+DATA 0xffd01500 0x00000000	# SDRAM CS[0] Base address at 0x00000000
+DATA 0xffd01504 0x07FFFFF1	# SDRAM CS[0] Size 128MiB
+DATA 0xffd01508 0x10000000
+DATA 0xffd0150c 0x00FFFFF4	# SDRAM CS[1] Size, window disabled
+DATA 0xffd01514 0x00FFFFF8	# SDRAM CS[2] Size, window disabled
+DATA 0xffd0151c 0x00FFFFFC	# SDRAM CS[3] Size, window disabled
+DATA 0xffd01494 0x84210000
+DATA 0xffd01498 0x00000000
+DATA 0xffd0149c 0x0000F80F
+DATA 0xffd01480 0x00000001
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/sbx81lifxcat.c b/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/sbx81lifxcat.c
new file mode 100644
index 000000000..52b8eba92
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/SBx81LIFXCAT/sbx81lifxcat.c
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010, 2018
+ * Allied Telesis <www.alliedtelesis.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+#include <led.h>
+#include <asm/global_data.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+#define SBX81LIFXCAT_OE_LOW		(~0)
+#define SBX81LIFXCAT_OE_HIGH		(~BIT(11))
+#define SBX81LIFXCAT_OE_VAL_LOW		(0)
+#define SBX81LIFXCAT_OE_VAL_HIGH	(BIT(11))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the  below configuration configures mainly initial LED status
+	 */
+	mvebu_config_gpio(SBX81LIFXCAT_OE_VAL_LOW,
+			  SBX81LIFXCAT_OE_VAL_HIGH,
+			  SBX81LIFXCAT_OE_LOW, SBX81LIFXCAT_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	static const u32 kwmpp_config[] = {
+		MPP0_SPI_SCn,
+		MPP1_SPI_MOSI,
+		MPP2_SPI_SCK,
+		MPP3_SPI_MISO,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,
+		MPP8_TW_SDA,
+		MPP9_TW_SCK,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_GPO,
+		MPP13_UART1_TXD,
+		MPP14_UART1_RXD,
+		MPP15_GPIO,
+		MPP16_GPIO,
+		MPP17_GPIO,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_GE1_0,
+		MPP21_GE1_1,
+		MPP22_GE1_2,
+		MPP23_GE1_3,
+		MPP24_GE1_4,
+		MPP25_GE1_5,
+		MPP26_GE1_6,
+		MPP27_GE1_7,
+		MPP28_GE1_8,
+		MPP29_GE1_9,
+		MPP30_GE1_10,
+		MPP31_GE1_11,
+		MPP32_GE1_12,
+		MPP33_GE1_13,
+		MPP34_GPIO,
+		MPP35_GPIO,
+		MPP36_GPIO,
+		MPP37_GPIO,
+		MPP38_GPIO,
+		MPP39_GPIO,
+		MPP40_GPIO,
+		MPP41_GPIO,
+		MPP42_GPIO,
+		MPP43_GPIO,
+		MPP44_GPIO,
+		MPP45_GPIO,
+		MPP46_GPIO,
+		MPP47_GPIO,
+		MPP48_GPIO,
+		MPP49_GPIO,
+		0
+	};
+
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* automatically defined by kirkwood config.h */
+void reset_phy(void)
+{
+}
+#endif
+
+#ifdef CONFIG_MV88E61XX_SWITCH
+int mv88e61xx_hw_reset(struct phy_device *phydev)
+{
+	phydev->advertising = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = led_get_by_label("status:ledp", &dev);
+	if (!ret)
+		led_set_state(dev, LEDST_ON);
+
+	ret = led_get_by_label("status:ledn", &dev);
+	if (!ret)
+		led_set_state(dev, LEDST_OFF);
+
+	return 0;
+}
+#endif
diff --git a/roms/u-boot/board/alliedtelesis/common/gpio_hog.c b/roms/u-boot/board/alliedtelesis/common/gpio_hog.c
new file mode 100644
index 000000000..4aecf7e2c
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/common/gpio_hog.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Allied Telesis Labs
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int gpio_hog_list(struct gpio_desc *gpiod, int max_count,
+		  const char *node_name, const char *gpio_name, int value)
+{
+	int node;
+	int count;
+	int i;
+
+	node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, node_name);
+	if (node < 0)
+		return -ENODEV;
+
+	if (!dm_gpio_is_valid(gpiod)) {
+		count =
+		    gpio_request_list_by_name_nodev(offset_to_ofnode(node),
+						    gpio_name, gpiod, max_count,
+						    GPIOD_IS_OUT);
+		if (count < 0)
+			return count;
+
+		for (i = 0; i < count; i++)
+			dm_gpio_set_value(&gpiod[i], value);
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/board/alliedtelesis/common/gpio_hog.h b/roms/u-boot/board/alliedtelesis/common/gpio_hog.h
new file mode 100644
index 000000000..edb744313
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/common/gpio_hog.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Allied Telesis Labs
+ */
+
+int gpio_hog_list(struct gpio_desc *gpiod, int max_count, const char *node_name,
+		  const char *gpio_name, int value);
+
+static inline int gpio_hog(struct gpio_desc *gpiod, const char *node_name,
+			   const char *gpio_name, int value)
+{
+	return gpio_hog_list(gpiod, 1, node_name, gpio_name, value);
+}
diff --git a/roms/u-boot/board/alliedtelesis/x530/MAINTAINERS b/roms/u-boot/board/alliedtelesis/x530/MAINTAINERS
new file mode 100644
index 000000000..8d2d7271b
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/x530/MAINTAINERS
@@ -0,0 +1,12 @@
+x530 BOARD
+M:	Chris Packham <chris.packham@alliedtelesis.co.nz>
+S:	Maintained
+F:	board/alliedtelesis/x530/
+F:	board/alliedtelesis/common/gpio_hog.c
+F:	board/alliedtelesis/common/gpio_hog.h
+F:	arch/arm/dts/armada-385-atl-x530.dts
+F:	arch/arm/dts/armada-385-atl-x530.dtsi
+F:	arch/arm/dts/armada-385-atl-x530DP.dts
+F:	arch/arm/dts/armada-385-atl-x530DP.dtsi
+F:	include/configs/x530.h
+F:	configs/x530_defconfig
diff --git a/roms/u-boot/board/alliedtelesis/x530/Makefile b/roms/u-boot/board/alliedtelesis/x530/Makefile
new file mode 100644
index 000000000..97de1d463
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/x530/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Copyright (C) 2017 Allied Telesis Labs
+#
+
+obj-y	:= $(BOARD).o
+ifndef CONFIG_SPL_BUILD
+obj-y	+= ../common/gpio_hog.o
+endif
diff --git a/roms/u-boot/board/alliedtelesis/x530/kwbimage.cfg b/roms/u-boot/board/alliedtelesis/x530/kwbimage.cfg
new file mode 100644
index 000000000..f58d38882
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/x530/kwbimage.cfg
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2017 Allied Telesis Labs
+#
+
+# Armada XP uses version 1 image format
+VERSION		1
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
diff --git a/roms/u-boot/board/alliedtelesis/x530/x530.c b/roms/u-boot/board/alliedtelesis/x530/x530.c
new file mode 100644
index 000000000..7bcfa828d
--- /dev/null
+++ b/roms/u-boot/board/alliedtelesis/x530/x530.c
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Allied Telesis Labs
+ */
+
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <env.h>
+#include <i2c.h>
+#include <init.h>
+#include <wdt.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <linux/bitops.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include "../common/gpio_hog.h"
+
+#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
+#include <../serdes/a38x/high_speed_env_spec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MVEBU_DEV_BUS_BASE		(MVEBU_REGISTER(0x10400))
+
+#define CONFIG_NVS_LOCATION		0xf4800000
+#define CONFIG_NVS_SIZE			(512 << 10)
+
+static struct serdes_map board_serdes_map[] = {
+	{PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+	{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+	{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
+};
+
+int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
+{
+	*serdes_map_array = board_serdes_map;
+	*count = ARRAY_SIZE(board_serdes_map);
+	return 0;
+}
+
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR3 init code in the SPL U-Boot version to configure
+ * the DDR3 controller.
+ */
+static struct mv_ddr_topology_map board_topology_map = {
+	DEBUG_LEVEL_ERROR,
+	0x1, /* active interfaces */
+	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+	{ { { {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0} },
+	    SPEED_BIN_DDR_1866M,	/* speed_bin */
+	    MV_DDR_DEV_WIDTH_16BIT,	/* sdram device width */
+	    MV_DDR_DIE_CAP_4GBIT,	/* die capacity */
+	    MV_DDR_FREQ_SAR,		/* frequency */
+	    0, 0,			/* cas_l cas_wl */
+	    MV_DDR_TEMP_LOW,		/* temperature */
+	    MV_DDR_TIM_2T} },		/* timing */
+	BUS_MASK_32BIT_ECC,		/* subphys mask */
+	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+	NOT_COMBINED,			/* ddr twin-die combined */
+	{ {0} },			/* raw spd data */
+	{0},				/* timing parameters */
+	{ {0} },			/* electrical configuration */
+	{0},				/* electrical parameters */
+	0,				/* Clock enable mask */
+	160				/* Clock delay */
+};
+
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
+{
+	/* Return the board topology as defined in the board code */
+	return &board_topology_map;
+}
+
+int board_early_init_f(void)
+{
+	/* Configure MPP */
+	writel(0x00001111, MVEBU_MPP_BASE + 0x00);
+	writel(0x00000000, MVEBU_MPP_BASE + 0x04);
+	writel(0x55000000, MVEBU_MPP_BASE + 0x08);
+	writel(0x55550550, MVEBU_MPP_BASE + 0x0c);
+	writel(0x55555555, MVEBU_MPP_BASE + 0x10);
+	writel(0x00100565, MVEBU_MPP_BASE + 0x14);
+	writel(0x40000000, MVEBU_MPP_BASE + 0x18);
+	writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
+
+	return 0;
+}
+
+void spl_board_init(void)
+{
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	/* window for NVS */
+	mbus_dt_setup_win(&mbus_state, CONFIG_NVS_LOCATION, CONFIG_NVS_SIZE,
+			  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
+
+	/* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */
+	writel(0x00004001, MVEBU_DEV_BUS_BASE + 0xc8);
+
+	spl_board_init();
+
+	return 0;
+}
+
+void arch_preboot_os(void)
+{
+#ifdef CONFIG_WATCHDOG
+	wdt_stop(gd->watchdog_dev);
+#endif
+}
+
+static int led_7seg_init(unsigned int segments)
+{
+	int node;
+	int ret;
+	int i;
+	struct gpio_desc desc[8];
+
+	node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
+					     "atl,of-led-7seg");
+	if (node < 0)
+		return -ENODEV;
+
+	ret = gpio_request_list_by_name_nodev(offset_to_ofnode(node),
+					      "segment-gpios", desc,
+					      ARRAY_SIZE(desc), GPIOD_IS_OUT);
+	if (ret < 0)
+		return ret;
+
+	for (i = 0; i < ARRAY_SIZE(desc); i++) {
+		ret = dm_gpio_set_value(&desc[i], !(segments & BIT(i)));
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	static struct gpio_desc usb_en = {}, nand_wp = {}, phy_reset[2] = {},
+				led_en = {};
+
+	gpio_hog(&usb_en, "atl,usb-enable", "enable-gpio", 1);
+	gpio_hog(&nand_wp, "atl,nand-protect", "protect-gpio", 1);
+	gpio_hog_list(phy_reset, ARRAY_SIZE(phy_reset), "atl,phy-reset", "reset-gpio", 0);
+	gpio_hog(&led_en, "atl,led-enable", "enable-gpio", 1);
+
+#ifdef MTDPARTS_MTDOOPS
+	env_set("mtdoops", MTDPARTS_MTDOOPS);
+#endif
+
+	led_7seg_init(0xff);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	puts("Board: " CONFIG_SYS_BOARD "\n");
+
+	return 0;
+}
+#endif